drivers/gpu/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28 #include <drm/i915_drm.h>
  29 #include "i915_drv.h"
  30 #include "i915_reg.h"
  31 #include "intel_drv.h"
  32 #include "intel_frontbuffer.h"
  33
  34 /* Limits for overlay size. According to intel doc, the real limits are:
  35  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  36  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  37  * the mininum of both.  */
  38 #define IMAGE_MAX_WIDTH         2048
  39 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  40 /* on 830 and 845 these large limits result in the card hanging */
  41 #define IMAGE_MAX_WIDTH_LEGACY  1024
  42 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  43
  44 /* overlay register definitions */
  45 /* OCMD register */
  46 #define OCMD_TILED_SURFACE      (0x1<<19)
  47 #define OCMD_MIRROR_MASK        (0x3<<17)
  48 #define OCMD_MIRROR_MODE        (0x3<<17)
  49 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  50 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  51 #define OCMD_MIRROR_BOTH        (0x3<<17)
  52 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  53 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  54 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  55 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  56 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  57 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  58 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  59 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  60 #define OCMD_YUV_422_PACKED     (0x8<<10)
  61 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  62 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  63 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  64 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  65 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  66 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  67 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  68 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  69 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  70 #define OCMD_TEST_MODE          (0x1<<4)
  71 #define OCMD_BUFFER_SELECT      (0x3<<2)
  72 #define OCMD_BUFFER0            (0x0<<2)
  73 #define OCMD_BUFFER1            (0x1<<2)
  74 #define OCMD_FIELD_SELECT       (0x1<<2)
  75 #define OCMD_FIELD0             (0x0<<1)
  76 #define OCMD_FIELD1             (0x1<<1)
  77 #define OCMD_ENABLE             (0x1<<0)
  78
  79 /* OCONFIG register */
  80 #define OCONF_PIPE_MASK         (0x1<<18)
  81 #define OCONF_PIPE_A            (0x0<<18)
  82 #define OCONF_PIPE_B            (0x1<<18)
  83 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  84 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  85 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  86 #define OCONF_CSC_BYPASS        (0x1<<4)
  87 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  88 #define OCONF_TEST_MODE         (0x1<<2)
  89 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  90 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  91
  92 /* DCLRKM (dst-key) register */
  93 #define DST_KEY_ENABLE          (0x1<<31)
  94 #define CLK_RGB24_MASK          0x0
  95 #define CLK_RGB16_MASK          0x070307
  96 #define CLK_RGB15_MASK          0x070707
  97 #define CLK_RGB8I_MASK          0xffffff
  98
  99 #define RGB16_TO_COLORKEY(c) \
 100         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 101 #define RGB15_TO_COLORKEY(c) \
 102         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 103
 104 /* overlay flip addr flag */
 105 #define OFC_UPDATE              0x1
 106
 107 /* polyphase filter coefficients */
 108 #define N_HORIZ_Y_TAPS          5
 109 #define N_VERT_Y_TAPS           3
 110 #define N_HORIZ_UV_TAPS         3
 111 #define N_VERT_UV_TAPS          3
 112 #define N_PHASES                17
 113 #define MAX_TAPS                5
 114
 115 /* memory bufferd overlay registers */
 116 struct overlay_registers {
 117         u32 OBUF_0Y;
 118         u32 OBUF_1Y;
 119         u32 OBUF_0U;
 120         u32 OBUF_0V;
 121         u32 OBUF_1U;
 122         u32 OBUF_1V;
 123         u32 OSTRIDE;
 124         u32 YRGB_VPH;
 125         u32 UV_VPH;
 126         u32 HORZ_PH;
 127         u32 INIT_PHS;
 128         u32 DWINPOS;
 129         u32 DWINSZ;
 130         u32 SWIDTH;
 131         u32 SWIDTHSW;
 132         u32 SHEIGHT;
 133         u32 YRGBSCALE;
 134         u32 UVSCALE;
 135         u32 OCLRC0;
 136         u32 OCLRC1;
 137         u32 DCLRKV;
 138         u32 DCLRKM;
 139         u32 SCLRKVH;
 140         u32 SCLRKVL;
 141         u32 SCLRKEN;
 142         u32 OCONFIG;
 143         u32 OCMD;
 144         u32 RESERVED1; /* 0x6C */
 145         u32 OSTART_0Y;
 146         u32 OSTART_1Y;
 147         u32 OSTART_0U;
 148         u32 OSTART_0V;
 149         u32 OSTART_1U;
 150         u32 OSTART_1V;
 151         u32 OTILEOFF_0Y;
 152         u32 OTILEOFF_1Y;
 153         u32 OTILEOFF_0U;
 154         u32 OTILEOFF_0V;
 155         u32 OTILEOFF_1U;
 156         u32 OTILEOFF_1V;
 157         u32 FASTHSCALE; /* 0xA0 */
 158         u32 UVSCALEV; /* 0xA4 */
 159         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 160         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 161         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 162         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 163         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 164         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 165         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 166         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 167         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 168 };
 169
 170 struct intel_overlay {
 171         struct drm_i915_private *i915;
 172         struct intel_crtc *crtc;
 173         struct i915_vma *vma;
 174         struct i915_vma *old_vma;
 175         bool active;
 176         bool pfit_active;
 177         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 178         u32 color_key:24;
 179         u32 color_key_enabled:1;
 180         u32 brightness, contrast, saturation;
 181         u32 old_xscale, old_yscale;
 182         /* register access */
 183         struct drm_i915_gem_object *reg_bo;
 184         struct overlay_registers __iomem *regs;
 185         u32 flip_addr;
 186         /* flip handling */
 187         struct i915_gem_active last_flip;
 188 };
 189
 190 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
 191                                       bool enable)
 192 {
 193         struct pci_dev *pdev = dev_priv->drm.pdev;
 194         u8 val;
 195
 196         /* WA_OVERLAY_CLKGATE:alm */
 197         if (enable)
 198                 I915_WRITE(DSPCLK_GATE_D, 0);
 199         else
 200                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
 201
 202         /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
 203         pci_bus_read_config_byte(pdev->bus,
 204                                  PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
 205         if (enable)
 206                 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
 207         else
 208                 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
 209         pci_bus_write_config_byte(pdev->bus,
 210                                   PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
 211 }
 212
 213 static void intel_overlay_submit_request(struct intel_overlay *overlay,
 214                                          struct i915_request *rq,
 215                                          i915_gem_retire_fn retire)
 216 {
 217         GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip,
 218                                         &overlay->i915->drm.struct_mutex));
 219         i915_gem_active_set_retire_fn(&overlay->last_flip, retire,
 220                                       &overlay->i915->drm.struct_mutex);
 221         i915_gem_active_set(&overlay->last_flip, rq);
 222         i915_request_add(rq);
 223 }
 224
 225 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 226                                          struct i915_request *rq,
 227                                          i915_gem_retire_fn retire)
 228 {
 229         intel_overlay_submit_request(overlay, rq, retire);
 230         return i915_gem_active_retire(&overlay->last_flip,
 231                                       &overlay->i915->drm.struct_mutex);
 232 }
 233
 234 static struct i915_request *alloc_request(struct intel_overlay *overlay)
 235 {
 236         struct drm_i915_private *dev_priv = overlay->i915;
 237         struct intel_engine_cs *engine = dev_priv->engine[RCS];
 238
 239         return i915_request_alloc(engine, dev_priv->kernel_context);
 240 }
 241
 242 /* overlay needs to be disable in OCMD reg */
 243 static int intel_overlay_on(struct intel_overlay *overlay)
 244 {
 245         struct drm_i915_private *dev_priv = overlay->i915;
 246         struct i915_request *rq;
 247         u32 *cs;
 248
 249         WARN_ON(overlay->active);
 250
 251         rq = alloc_request(overlay);
 252         if (IS_ERR(rq))
 253                 return PTR_ERR(rq);
 254
 255         cs = intel_ring_begin(rq, 4);
 256         if (IS_ERR(cs)) {
 257                 i915_request_add(rq);
 258                 return PTR_ERR(cs);
 259         }
 260
 261         overlay->active = true;
 262
 263         if (IS_I830(dev_priv))
 264                 i830_overlay_clock_gating(dev_priv, false);
 265
 266         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
 267         *cs++ = overlay->flip_addr | OFC_UPDATE;
 268         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 269         *cs++ = MI_NOOP;
 270         intel_ring_advance(rq, cs);
 271
 272         return intel_overlay_do_wait_request(overlay, rq, NULL);
 273 }
 274
 275 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
 276                                        struct i915_vma *vma)
 277 {
 278         enum pipe pipe = overlay->crtc->pipe;
 279
 280         WARN_ON(overlay->old_vma);
 281
 282         i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL,
 283                           vma ? vma->obj : NULL,
 284                           INTEL_FRONTBUFFER_OVERLAY(pipe));
 285
 286         intel_frontbuffer_flip_prepare(overlay->i915,
 287                                        INTEL_FRONTBUFFER_OVERLAY(pipe));
 288
 289         overlay->old_vma = overlay->vma;
 290         if (vma)
 291                 overlay->vma = i915_vma_get(vma);
 292         else
 293                 overlay->vma = NULL;
 294 }
 295
 296 /* overlay needs to be enabled in OCMD reg */
 297 static int intel_overlay_continue(struct intel_overlay *overlay,
 298                                   struct i915_vma *vma,
 299                                   bool load_polyphase_filter)
 300 {
 301         struct drm_i915_private *dev_priv = overlay->i915;
 302         struct i915_request *rq;
 303         u32 flip_addr = overlay->flip_addr;
 304         u32 tmp, *cs;
 305
 306         WARN_ON(!overlay->active);
 307
 308         if (load_polyphase_filter)
 309                 flip_addr |= OFC_UPDATE;
 310
 311         /* check for underruns */
 312         tmp = I915_READ(DOVSTA);
 313         if (tmp & (1 << 17))
 314                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 315
 316         rq = alloc_request(overlay);
 317         if (IS_ERR(rq))
 318                 return PTR_ERR(rq);
 319
 320         cs = intel_ring_begin(rq, 2);
 321         if (IS_ERR(cs)) {
 322                 i915_request_add(rq);
 323                 return PTR_ERR(cs);
 324         }
 325
 326         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
 327         *cs++ = flip_addr;
 328         intel_ring_advance(rq, cs);
 329
 330         intel_overlay_flip_prepare(overlay, vma);
 331
 332         intel_overlay_submit_request(overlay, rq, NULL);
 333
 334         return 0;
 335 }
 336
 337 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
 338 {
 339         struct i915_vma *vma;
 340
 341         vma = fetch_and_zero(&overlay->old_vma);
 342         if (WARN_ON(!vma))
 343                 return;
 344
 345         intel_frontbuffer_flip_complete(overlay->i915,
 346                                         INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
 347
 348         i915_gem_object_unpin_from_display_plane(vma);
 349         i915_vma_put(vma);
 350 }
 351
 352 static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
 353                                                struct i915_request *rq)
 354 {
 355         struct intel_overlay *overlay =
 356                 container_of(active, typeof(*overlay), last_flip);
 357
 358         intel_overlay_release_old_vma(overlay);
 359 }
 360
 361 static void intel_overlay_off_tail(struct i915_gem_active *active,
 362                                    struct i915_request *rq)
 363 {
 364         struct intel_overlay *overlay =
 365                 container_of(active, typeof(*overlay), last_flip);
 366         struct drm_i915_private *dev_priv = overlay->i915;
 367
 368         intel_overlay_release_old_vma(overlay);
 369
 370         overlay->crtc->overlay = NULL;
 371         overlay->crtc = NULL;
 372         overlay->active = false;
 373
 374         if (IS_I830(dev_priv))
 375                 i830_overlay_clock_gating(dev_priv, true);
 376 }
 377
 378 /* overlay needs to be disabled in OCMD reg */
 379 static int intel_overlay_off(struct intel_overlay *overlay)
 380 {
 381         struct i915_request *rq;
 382         u32 *cs, flip_addr = overlay->flip_addr;
 383
 384         WARN_ON(!overlay->active);
 385
 386         /* According to intel docs the overlay hw may hang (when switching
 387          * off) without loading the filter coeffs. It is however unclear whether
 388          * this applies to the disabling of the overlay or to the switching off
 389          * of the hw. Do it in both cases */
 390         flip_addr |= OFC_UPDATE;
 391
 392         rq = alloc_request(overlay);
 393         if (IS_ERR(rq))
 394                 return PTR_ERR(rq);
 395
 396         cs = intel_ring_begin(rq, 6);
 397         if (IS_ERR(cs)) {
 398                 i915_request_add(rq);
 399                 return PTR_ERR(cs);
 400         }
 401
 402         /* wait for overlay to go idle */
 403         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
 404         *cs++ = flip_addr;
 405         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 406
 407         /* turn overlay off */
 408         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
 409         *cs++ = flip_addr;
 410         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 411
 412         intel_ring_advance(rq, cs);
 413
 414         intel_overlay_flip_prepare(overlay, NULL);
 415
 416         return intel_overlay_do_wait_request(overlay, rq,
 417                                              intel_overlay_off_tail);
 418 }
 419
 420 /* recover from an interruption due to a signal
 421  * We have to be careful not to repeat work forever an make forward progess. */
 422 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 423 {
 424         return i915_gem_active_retire(&overlay->last_flip,
 425                                       &overlay->i915->drm.struct_mutex);
 426 }
 427
 428 /* Wait for pending overlay flip and release old frame.
 429  * Needs to be called before the overlay register are changed
 430  * via intel_overlay_(un)map_regs
 431  */
 432 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 433 {
 434         struct drm_i915_private *dev_priv = overlay->i915;
 435         u32 *cs;
 436         int ret;
 437
 438         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 439
 440         /* Only wait if there is actually an old frame to release to
 441          * guarantee forward progress.
 442          */
 443         if (!overlay->old_vma)
 444                 return 0;
 445
 446         if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 447                 /* synchronous slowpath */
 448                 struct i915_request *rq;
 449
 450                 rq = alloc_request(overlay);
 451                 if (IS_ERR(rq))
 452                         return PTR_ERR(rq);
 453
 454                 cs = intel_ring_begin(rq, 2);
 455                 if (IS_ERR(cs)) {
 456                         i915_request_add(rq);
 457                         return PTR_ERR(cs);
 458                 }
 459
 460                 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 461                 *cs++ = MI_NOOP;
 462                 intel_ring_advance(rq, cs);
 463
 464                 ret = intel_overlay_do_wait_request(overlay, rq,
 465                                                     intel_overlay_release_old_vid_tail);
 466                 if (ret)
 467                         return ret;
 468         } else
 469                 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
 470
 471         return 0;
 472 }
 473
 474 void intel_overlay_reset(struct drm_i915_private *dev_priv)
 475 {
 476         struct intel_overlay *overlay = dev_priv->overlay;
 477
 478         if (!overlay)
 479                 return;
 480
 481         overlay->old_xscale = 0;
 482         overlay->old_yscale = 0;
 483         overlay->crtc = NULL;
 484         overlay->active = false;
 485 }
 486
 487 static int packed_depth_bytes(u32 format)
 488 {
 489         switch (format & I915_OVERLAY_DEPTH_MASK) {
 490         case I915_OVERLAY_YUV422:
 491                 return 4;
 492         case I915_OVERLAY_YUV411:
 493                 /* return 6; not implemented */
 494         default:
 495                 return -EINVAL;
 496         }
 497 }
 498
 499 static int packed_width_bytes(u32 format, short width)
 500 {
 501         switch (format & I915_OVERLAY_DEPTH_MASK) {
 502         case I915_OVERLAY_YUV422:
 503                 return width << 1;
 504         default:
 505                 return -EINVAL;
 506         }
 507 }
 508
 509 static int uv_hsubsampling(u32 format)
 510 {
 511         switch (format & I915_OVERLAY_DEPTH_MASK) {
 512         case I915_OVERLAY_YUV422:
 513         case I915_OVERLAY_YUV420:
 514                 return 2;
 515         case I915_OVERLAY_YUV411:
 516         case I915_OVERLAY_YUV410:
 517                 return 4;
 518         default:
 519                 return -EINVAL;
 520         }
 521 }
 522
 523 static int uv_vsubsampling(u32 format)
 524 {
 525         switch (format & I915_OVERLAY_DEPTH_MASK) {
 526         case I915_OVERLAY_YUV420:
 527         case I915_OVERLAY_YUV410:
 528                 return 2;
 529         case I915_OVERLAY_YUV422:
 530         case I915_OVERLAY_YUV411:
 531                 return 1;
 532         default:
 533                 return -EINVAL;
 534         }
 535 }
 536
 537 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
 538 {
 539         u32 sw;
 540
 541         if (IS_GEN(dev_priv, 2))
 542                 sw = ALIGN((offset & 31) + width, 32);
 543         else
 544                 sw = ALIGN((offset & 63) + width, 64);
 545
 546         if (sw == 0)
 547                 return 0;
 548
 549         return (sw - 32) >> 3;
 550 }
 551
 552 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
 553         [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
 554         [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
 555         [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
 556         [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
 557         [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
 558         [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
 559         [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
 560         [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
 561         [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
 562         [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
 563         [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
 564         [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
 565         [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
 566         [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
 567         [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
 568         [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
 569         [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
 570 };
 571
 572 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
 573         [ 0] = { 0x3000, 0x1800, 0x1800, },
 574         [ 1] = { 0xb000, 0x18d0, 0x2e60, },
 575         [ 2] = { 0xb000, 0x1990, 0x2ce0, },
 576         [ 3] = { 0xb020, 0x1a68, 0x2b40, },
 577         [ 4] = { 0xb040, 0x1b20, 0x29e0, },
 578         [ 5] = { 0xb060, 0x1bd8, 0x2880, },
 579         [ 6] = { 0xb080, 0x1c88, 0x3e60, },
 580         [ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
 581         [ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
 582         [ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
 583         [10] = { 0xb100, 0x1eb8, 0x3620, },
 584         [11] = { 0xb100, 0x1f18, 0x34a0, },
 585         [12] = { 0xb100, 0x1f68, 0x3360, },
 586         [13] = { 0xb0e0, 0x1fa8, 0x3240, },
 587         [14] = { 0xb0c0, 0x1fe0, 0x3140, },
 588         [15] = { 0xb060, 0x1ff0, 0x30a0, },
 589         [16] = { 0x3000, 0x0800, 0x3000, },
 590 };
 591
 592 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 593 {
 594         memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 595         memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 596                     sizeof(uv_static_hcoeffs));
 597 }
 598
 599 static bool update_scaling_factors(struct intel_overlay *overlay,
 600                                    struct overlay_registers __iomem *regs,
 601                                    struct drm_intel_overlay_put_image *params)
 602 {
 603         /* fixed point with a 12 bit shift */
 604         u32 xscale, yscale, xscale_UV, yscale_UV;
 605 #define FP_SHIFT 12
 606 #define FRACT_MASK 0xfff
 607         bool scale_changed = false;
 608         int uv_hscale = uv_hsubsampling(params->flags);
 609         int uv_vscale = uv_vsubsampling(params->flags);
 610
 611         if (params->dst_width > 1)
 612                 xscale = ((params->src_scan_width - 1) << FP_SHIFT) /
 613                         params->dst_width;
 614         else
 615                 xscale = 1 << FP_SHIFT;
 616
 617         if (params->dst_height > 1)
 618                 yscale = ((params->src_scan_height - 1) << FP_SHIFT) /
 619                         params->dst_height;
 620         else
 621                 yscale = 1 << FP_SHIFT;
 622
 623         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 624         xscale_UV = xscale/uv_hscale;
 625         yscale_UV = yscale/uv_vscale;
 626         /* make the Y scale to UV scale ratio an exact multiply */
 627         xscale = xscale_UV * uv_hscale;
 628         yscale = yscale_UV * uv_vscale;
 629         /*} else {
 630           xscale_UV = 0;
 631           yscale_UV = 0;
 632           }*/
 633
 634         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 635                 scale_changed = true;
 636         overlay->old_xscale = xscale;
 637         overlay->old_yscale = yscale;
 638
 639         iowrite32(((yscale & FRACT_MASK) << 20) |
 640                   ((xscale >> FP_SHIFT)  << 16) |
 641                   ((xscale & FRACT_MASK) << 3),
 642                  &regs->YRGBSCALE);
 643
 644         iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 645                   ((xscale_UV >> FP_SHIFT)  << 16) |
 646                   ((xscale_UV & FRACT_MASK) << 3),
 647                  &regs->UVSCALE);
 648
 649         iowrite32((((yscale    >> FP_SHIFT) << 16) |
 650                    ((yscale_UV >> FP_SHIFT) << 0)),
 651                  &regs->UVSCALEV);
 652
 653         if (scale_changed)
 654                 update_polyphase_filter(regs);
 655
 656         return scale_changed;
 657 }
 658
 659 static void update_colorkey(struct intel_overlay *overlay,
 660                             struct overlay_registers __iomem *regs)
 661 {
 662         const struct intel_plane_state *state =
 663                 to_intel_plane_state(overlay->crtc->base.primary->state);
 664         u32 key = overlay->color_key;
 665         u32 format = 0;
 666         u32 flags = 0;
 667
 668         if (overlay->color_key_enabled)
 669                 flags |= DST_KEY_ENABLE;
 670
 671         if (state->base.visible)
 672                 format = state->base.fb->format->format;
 673
 674         switch (format) {
 675         case DRM_FORMAT_C8:
 676                 key = 0;
 677                 flags |= CLK_RGB8I_MASK;
 678                 break;
 679         case DRM_FORMAT_XRGB1555:
 680                 key = RGB15_TO_COLORKEY(key);
 681                 flags |= CLK_RGB15_MASK;
 682                 break;
 683         case DRM_FORMAT_RGB565:
 684                 key = RGB16_TO_COLORKEY(key);
 685                 flags |= CLK_RGB16_MASK;
 686                 break;
 687         default:
 688                 flags |= CLK_RGB24_MASK;
 689                 break;
 690         }
 691
 692         iowrite32(key, &regs->DCLRKV);
 693         iowrite32(flags, &regs->DCLRKM);
 694 }
 695
 696 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
 697 {
 698         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 699
 700         if (params->flags & I915_OVERLAY_YUV_PLANAR) {
 701                 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
 702                 case I915_OVERLAY_YUV422:
 703                         cmd |= OCMD_YUV_422_PLANAR;
 704                         break;
 705                 case I915_OVERLAY_YUV420:
 706                         cmd |= OCMD_YUV_420_PLANAR;
 707                         break;
 708                 case I915_OVERLAY_YUV411:
 709                 case I915_OVERLAY_YUV410:
 710                         cmd |= OCMD_YUV_410_PLANAR;
 711                         break;
 712                 }
 713         } else { /* YUV packed */
 714                 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
 715                 case I915_OVERLAY_YUV422:
 716                         cmd |= OCMD_YUV_422_PACKED;
 717                         break;
 718                 case I915_OVERLAY_YUV411:
 719                         cmd |= OCMD_YUV_411_PACKED;
 720                         break;
 721                 }
 722
 723                 switch (params->flags & I915_OVERLAY_SWAP_MASK) {
 724                 case I915_OVERLAY_NO_SWAP:
 725                         break;
 726                 case I915_OVERLAY_UV_SWAP:
 727                         cmd |= OCMD_UV_SWAP;
 728                         break;
 729                 case I915_OVERLAY_Y_SWAP:
 730                         cmd |= OCMD_Y_SWAP;
 731                         break;
 732                 case I915_OVERLAY_Y_AND_UV_SWAP:
 733                         cmd |= OCMD_Y_AND_UV_SWAP;
 734                         break;
 735                 }
 736         }
 737
 738         return cmd;
 739 }
 740
 741 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 742                                       struct drm_i915_gem_object *new_bo,
 743                                       struct drm_intel_overlay_put_image *params)
 744 {
 745         struct overlay_registers __iomem *regs = overlay->regs;
 746         struct drm_i915_private *dev_priv = overlay->i915;
 747         u32 swidth, swidthsw, sheight, ostride;
 748         enum pipe pipe = overlay->crtc->pipe;
 749         bool scale_changed = false;
 750         struct i915_vma *vma;
 751         int ret, tmp_width;
 752
 753         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 754         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 755
 756         ret = intel_overlay_release_old_vid(overlay);
 757         if (ret != 0)
 758                 return ret;
 759
 760         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
 761
 762         vma = i915_gem_object_pin_to_display_plane(new_bo,
 763                                                    0, NULL, PIN_MAPPABLE);
 764         if (IS_ERR(vma)) {
 765                 ret = PTR_ERR(vma);
 766                 goto out_pin_section;
 767         }
 768         intel_fb_obj_flush(new_bo, ORIGIN_DIRTYFB);
 769
 770         ret = i915_vma_put_fence(vma);
 771         if (ret)
 772                 goto out_unpin;
 773
 774         if (!overlay->active) {
 775                 u32 oconfig;
 776
 777                 oconfig = OCONF_CC_OUT_8BIT;
 778                 if (IS_GEN(dev_priv, 4))
 779                         oconfig |= OCONF_CSC_MODE_BT709;
 780                 oconfig |= pipe == 0 ?
 781                         OCONF_PIPE_A : OCONF_PIPE_B;
 782                 iowrite32(oconfig, &regs->OCONFIG);
 783
 784                 ret = intel_overlay_on(overlay);
 785                 if (ret != 0)
 786                         goto out_unpin;
 787         }
 788
 789         iowrite32(params->dst_y << 16 | params->dst_x, &regs->DWINPOS);
 790         iowrite32(params->dst_height << 16 | params->dst_width, &regs->DWINSZ);
 791
 792         if (params->flags & I915_OVERLAY_YUV_PACKED)
 793                 tmp_width = packed_width_bytes(params->flags,
 794                                                params->src_width);
 795         else
 796                 tmp_width = params->src_width;
 797
 798         swidth = params->src_width;
 799         swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
 800         sheight = params->src_height;
 801         iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
 802         ostride = params->stride_Y;
 803
 804         if (params->flags & I915_OVERLAY_YUV_PLANAR) {
 805                 int uv_hscale = uv_hsubsampling(params->flags);
 806                 int uv_vscale = uv_vsubsampling(params->flags);
 807                 u32 tmp_U, tmp_V;
 808
 809                 swidth |= (params->src_width / uv_hscale) << 16;
 810                 sheight |= (params->src_height / uv_vscale) << 16;
 811
 812                 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
 813                                       params->src_width / uv_hscale);
 814                 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
 815                                       params->src_width / uv_hscale);
 816                 swidthsw |= max(tmp_U, tmp_V) << 16;
 817
 818                 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
 819                           &regs->OBUF_0U);
 820                 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
 821                           &regs->OBUF_0V);
 822
 823                 ostride |= params->stride_UV << 16;
 824         }
 825
 826         iowrite32(swidth, &regs->SWIDTH);
 827         iowrite32(swidthsw, &regs->SWIDTHSW);
 828         iowrite32(sheight, &regs->SHEIGHT);
 829         iowrite32(ostride, &regs->OSTRIDE);
 830
 831         scale_changed = update_scaling_factors(overlay, regs, params);
 832
 833         update_colorkey(overlay, regs);
 834
 835         iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 836
 837         ret = intel_overlay_continue(overlay, vma, scale_changed);
 838         if (ret)
 839                 goto out_unpin;
 840
 841         return 0;
 842
 843 out_unpin:
 844         i915_gem_object_unpin_from_display_plane(vma);
 845 out_pin_section:
 846         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
 847
 848         return ret;
 849 }
 850
 851 int intel_overlay_switch_off(struct intel_overlay *overlay)
 852 {
 853         struct drm_i915_private *dev_priv = overlay->i915;
 854         int ret;
 855
 856         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 857         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 858
 859         ret = intel_overlay_recover_from_interrupt(overlay);
 860         if (ret != 0)
 861                 return ret;
 862
 863         if (!overlay->active)
 864                 return 0;
 865
 866         ret = intel_overlay_release_old_vid(overlay);
 867         if (ret != 0)
 868                 return ret;
 869
 870         iowrite32(0, &overlay->regs->OCMD);
 871
 872         return intel_overlay_off(overlay);
 873 }
 874
 875 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 876                                           struct intel_crtc *crtc)
 877 {
 878         if (!crtc->active)
 879                 return -EINVAL;
 880
 881         /* can't use the overlay with double wide pipe */
 882         if (crtc->config->double_wide)
 883                 return -EINVAL;
 884
 885         return 0;
 886 }
 887
 888 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 889 {
 890         struct drm_i915_private *dev_priv = overlay->i915;
 891         u32 pfit_control = I915_READ(PFIT_CONTROL);
 892         u32 ratio;
 893
 894         /* XXX: This is not the same logic as in the xorg driver, but more in
 895          * line with the intel documentation for the i965
 896          */
 897         if (INTEL_GEN(dev_priv) >= 4) {
 898                 /* on i965 use the PGM reg to read out the autoscaler values */
 899                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 900         } else {
 901                 if (pfit_control & VERT_AUTO_SCALE)
 902                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 903                 else
 904                         ratio = I915_READ(PFIT_PGM_RATIOS);
 905                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 906         }
 907
 908         overlay->pfit_vscale_ratio = ratio;
 909 }
 910
 911 static int check_overlay_dst(struct intel_overlay *overlay,
 912                              struct drm_intel_overlay_put_image *rec)
 913 {
 914         const struct intel_crtc_state *pipe_config =
 915                 overlay->crtc->config;
 916
 917         if (rec->dst_x < pipe_config->pipe_src_w &&
 918             rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
 919             rec->dst_y < pipe_config->pipe_src_h &&
 920             rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
 921                 return 0;
 922         else
 923                 return -EINVAL;
 924 }
 925
 926 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec)
 927 {
 928         u32 tmp;
 929
 930         /* downscaling limit is 8.0 */
 931         tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
 932         if (tmp > 7)
 933                 return -EINVAL;
 934
 935         tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
 936         if (tmp > 7)
 937                 return -EINVAL;
 938
 939         return 0;
 940 }
 941
 942 static int check_overlay_src(struct drm_i915_private *dev_priv,
 943                              struct drm_intel_overlay_put_image *rec,
 944                              struct drm_i915_gem_object *new_bo)
 945 {
 946         int uv_hscale = uv_hsubsampling(rec->flags);
 947         int uv_vscale = uv_vsubsampling(rec->flags);
 948         u32 stride_mask;
 949         int depth;
 950         u32 tmp;
 951
 952         /* check src dimensions */
 953         if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
 954                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
 955                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
 956                         return -EINVAL;
 957         } else {
 958                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
 959                     rec->src_width  > IMAGE_MAX_WIDTH)
 960                         return -EINVAL;
 961         }
 962
 963         /* better safe than sorry, use 4 as the maximal subsampling ratio */
 964         if (rec->src_height < N_VERT_Y_TAPS*4 ||
 965             rec->src_width  < N_HORIZ_Y_TAPS*4)
 966                 return -EINVAL;
 967
 968         /* check alignment constraints */
 969         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
 970         case I915_OVERLAY_RGB:
 971                 /* not implemented */
 972                 return -EINVAL;
 973
 974         case I915_OVERLAY_YUV_PACKED:
 975                 if (uv_vscale != 1)
 976                         return -EINVAL;
 977
 978                 depth = packed_depth_bytes(rec->flags);
 979                 if (depth < 0)
 980                         return depth;
 981
 982                 /* ignore UV planes */
 983                 rec->stride_UV = 0;
 984                 rec->offset_U = 0;
 985                 rec->offset_V = 0;
 986                 /* check pixel alignment */
 987                 if (rec->offset_Y % depth)
 988                         return -EINVAL;
 989                 break;
 990
 991         case I915_OVERLAY_YUV_PLANAR:
 992                 if (uv_vscale < 0 || uv_hscale < 0)
 993                         return -EINVAL;
 994                 /* no offset restrictions for planar formats */
 995                 break;
 996
 997         default:
 998                 return -EINVAL;
 999         }
1000
1001         if (rec->src_width % uv_hscale)
1002                 return -EINVAL;
1003
1004         /* stride checking */
1005         if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1006                 stride_mask = 255;
1007         else
1008                 stride_mask = 63;
1009
1010         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1011                 return -EINVAL;
1012         if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512)
1013                 return -EINVAL;
1014
1015         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1016                 4096 : 8192;
1017         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1018                 return -EINVAL;
1019
1020         /* check buffer dimensions */
1021         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1022         case I915_OVERLAY_RGB:
1023         case I915_OVERLAY_YUV_PACKED:
1024                 /* always 4 Y values per depth pixels */
1025                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1026                         return -EINVAL;
1027
1028                 tmp = rec->stride_Y*rec->src_height;
1029                 if (rec->offset_Y + tmp > new_bo->base.size)
1030                         return -EINVAL;
1031                 break;
1032
1033         case I915_OVERLAY_YUV_PLANAR:
1034                 if (rec->src_width > rec->stride_Y)
1035                         return -EINVAL;
1036                 if (rec->src_width/uv_hscale > rec->stride_UV)
1037                         return -EINVAL;
1038
1039                 tmp = rec->stride_Y * rec->src_height;
1040                 if (rec->offset_Y + tmp > new_bo->base.size)
1041                         return -EINVAL;
1042
1043                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1044                 if (rec->offset_U + tmp > new_bo->base.size ||
1045                     rec->offset_V + tmp > new_bo->base.size)
1046                         return -EINVAL;
1047                 break;
1048         }
1049
1050         return 0;
1051 }
1052
1053 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1054                                   struct drm_file *file_priv)
1055 {
1056         struct drm_intel_overlay_put_image *params = data;
1057         struct drm_i915_private *dev_priv = to_i915(dev);
1058         struct intel_overlay *overlay;
1059         struct drm_crtc *drmmode_crtc;
1060         struct intel_crtc *crtc;
1061         struct drm_i915_gem_object *new_bo;
1062         int ret;
1063
1064         overlay = dev_priv->overlay;
1065         if (!overlay) {
1066                 DRM_DEBUG("userspace bug: no overlay\n");
1067                 return -ENODEV;
1068         }
1069
1070         if (!(params->flags & I915_OVERLAY_ENABLE)) {
1071                 drm_modeset_lock_all(dev);
1072                 mutex_lock(&dev->struct_mutex);
1073
1074                 ret = intel_overlay_switch_off(overlay);
1075
1076                 mutex_unlock(&dev->struct_mutex);
1077                 drm_modeset_unlock_all(dev);
1078
1079                 return ret;
1080         }
1081
1082         drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);
1083         if (!drmmode_crtc)
1084                 return -ENOENT;
1085         crtc = to_intel_crtc(drmmode_crtc);
1086
1087         new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);
1088         if (!new_bo)
1089                 return -ENOENT;
1090
1091         drm_modeset_lock_all(dev);
1092         mutex_lock(&dev->struct_mutex);
1093
1094         if (i915_gem_object_is_tiled(new_bo)) {
1095                 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1096                 ret = -EINVAL;
1097                 goto out_unlock;
1098         }
1099
1100         ret = intel_overlay_recover_from_interrupt(overlay);
1101         if (ret != 0)
1102                 goto out_unlock;
1103
1104         if (overlay->crtc != crtc) {
1105                 ret = intel_overlay_switch_off(overlay);
1106                 if (ret != 0)
1107                         goto out_unlock;
1108
1109                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1110                 if (ret != 0)
1111                         goto out_unlock;
1112
1113                 overlay->crtc = crtc;
1114                 crtc->overlay = overlay;
1115
1116                 /* line too wide, i.e. one-line-mode */
1117                 if (crtc->config->pipe_src_w > 1024 &&
1118                     crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1119                         overlay->pfit_active = true;
1120                         update_pfit_vscale_ratio(overlay);
1121                 } else
1122                         overlay->pfit_active = false;
1123         }
1124
1125         ret = check_overlay_dst(overlay, params);
1126         if (ret != 0)
1127                 goto out_unlock;
1128
1129         if (overlay->pfit_active) {
1130                 params->dst_y = (((u32)params->dst_y << 12) /
1131                                  overlay->pfit_vscale_ratio);
1132                 /* shifting right rounds downwards, so add 1 */
1133                 params->dst_height = (((u32)params->dst_height << 12) /
1134                                  overlay->pfit_vscale_ratio) + 1;
1135         }
1136
1137         if (params->src_scan_height > params->src_height ||
1138             params->src_scan_width > params->src_width) {
1139                 ret = -EINVAL;
1140                 goto out_unlock;
1141         }
1142
1143         ret = check_overlay_src(dev_priv, params, new_bo);
1144         if (ret != 0)
1145                 goto out_unlock;
1146
1147         /* Check scaling after src size to prevent a divide-by-zero. */
1148         ret = check_overlay_scaling(params);
1149         if (ret != 0)
1150                 goto out_unlock;
1151
1152         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1153         if (ret != 0)
1154                 goto out_unlock;
1155
1156         mutex_unlock(&dev->struct_mutex);
1157         drm_modeset_unlock_all(dev);
1158         i915_gem_object_put(new_bo);
1159
1160         return 0;
1161
1162 out_unlock:
1163         mutex_unlock(&dev->struct_mutex);
1164         drm_modeset_unlock_all(dev);
1165         i915_gem_object_put(new_bo);
1166
1167         return ret;
1168 }
1169
1170 static void update_reg_attrs(struct intel_overlay *overlay,
1171                              struct overlay_registers __iomem *regs)
1172 {
1173         iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1174                   &regs->OCLRC0);
1175         iowrite32(overlay->saturation, &regs->OCLRC1);
1176 }
1177
1178 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1179 {
1180         int i;
1181
1182         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1183                 return false;
1184
1185         for (i = 0; i < 3; i++) {
1186                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1187                         return false;
1188         }
1189
1190         return true;
1191 }
1192
1193 static bool check_gamma5_errata(u32 gamma5)
1194 {
1195         int i;
1196
1197         for (i = 0; i < 3; i++) {
1198                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1199                         return false;
1200         }
1201
1202         return true;
1203 }
1204
1205 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1206 {
1207         if (!check_gamma_bounds(0, attrs->gamma0) ||
1208             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1209             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1210             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1211             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1212             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1213             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1214                 return -EINVAL;
1215
1216         if (!check_gamma5_errata(attrs->gamma5))
1217                 return -EINVAL;
1218
1219         return 0;
1220 }
1221
1222 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1223                               struct drm_file *file_priv)
1224 {
1225         struct drm_intel_overlay_attrs *attrs = data;
1226         struct drm_i915_private *dev_priv = to_i915(dev);
1227         struct intel_overlay *overlay;
1228         int ret;
1229
1230         overlay = dev_priv->overlay;
1231         if (!overlay) {
1232                 DRM_DEBUG("userspace bug: no overlay\n");
1233                 return -ENODEV;
1234         }
1235
1236         drm_modeset_lock_all(dev);
1237         mutex_lock(&dev->struct_mutex);
1238
1239         ret = -EINVAL;
1240         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1241                 attrs->color_key  = overlay->color_key;
1242                 attrs->brightness = overlay->brightness;
1243                 attrs->contrast   = overlay->contrast;
1244                 attrs->saturation = overlay->saturation;
1245
1246                 if (!IS_GEN(dev_priv, 2)) {
1247                         attrs->gamma0 = I915_READ(OGAMC0);
1248                         attrs->gamma1 = I915_READ(OGAMC1);
1249                         attrs->gamma2 = I915_READ(OGAMC2);
1250                         attrs->gamma3 = I915_READ(OGAMC3);
1251                         attrs->gamma4 = I915_READ(OGAMC4);
1252                         attrs->gamma5 = I915_READ(OGAMC5);
1253                 }
1254         } else {
1255                 if (attrs->brightness < -128 || attrs->brightness > 127)
1256                         goto out_unlock;
1257                 if (attrs->contrast > 255)
1258                         goto out_unlock;
1259                 if (attrs->saturation > 1023)
1260                         goto out_unlock;
1261
1262                 overlay->color_key  = attrs->color_key;
1263                 overlay->brightness = attrs->brightness;
1264                 overlay->contrast   = attrs->contrast;
1265                 overlay->saturation = attrs->saturation;
1266
1267                 update_reg_attrs(overlay, overlay->regs);
1268
1269                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1270                         if (IS_GEN(dev_priv, 2))
1271                                 goto out_unlock;
1272
1273                         if (overlay->active) {
1274                                 ret = -EBUSY;
1275                                 goto out_unlock;
1276                         }
1277
1278                         ret = check_gamma(attrs);
1279                         if (ret)
1280                                 goto out_unlock;
1281
1282                         I915_WRITE(OGAMC0, attrs->gamma0);
1283                         I915_WRITE(OGAMC1, attrs->gamma1);
1284                         I915_WRITE(OGAMC2, attrs->gamma2);
1285                         I915_WRITE(OGAMC3, attrs->gamma3);
1286                         I915_WRITE(OGAMC4, attrs->gamma4);
1287                         I915_WRITE(OGAMC5, attrs->gamma5);
1288                 }
1289         }
1290         overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1291
1292         ret = 0;
1293 out_unlock:
1294         mutex_unlock(&dev->struct_mutex);
1295         drm_modeset_unlock_all(dev);
1296
1297         return ret;
1298 }
1299
1300 static int get_registers(struct intel_overlay *overlay, bool use_phys)
1301 {
1302         struct drm_i915_gem_object *obj;
1303         struct i915_vma *vma;
1304         int err;
1305
1306         obj = i915_gem_object_create_stolen(overlay->i915, PAGE_SIZE);
1307         if (obj == NULL)
1308                 obj = i915_gem_object_create_internal(overlay->i915, PAGE_SIZE);
1309         if (IS_ERR(obj))
1310                 return PTR_ERR(obj);
1311
1312         vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
1313         if (IS_ERR(vma)) {
1314                 err = PTR_ERR(vma);
1315                 goto err_put_bo;
1316         }
1317
1318         if (use_phys)
1319                 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);
1320         else
1321                 overlay->flip_addr = i915_ggtt_offset(vma);
1322         overlay->regs = i915_vma_pin_iomap(vma);
1323         i915_vma_unpin(vma);
1324
1325         if (IS_ERR(overlay->regs)) {
1326                 err = PTR_ERR(overlay->regs);
1327                 goto err_put_bo;
1328         }
1329
1330         overlay->reg_bo = obj;
1331         return 0;
1332
1333 err_put_bo:
1334         i915_gem_object_put(obj);
1335         return err;
1336 }
1337
1338 void intel_overlay_setup(struct drm_i915_private *dev_priv)
1339 {
1340         struct intel_overlay *overlay;
1341         int ret;
1342
1343         if (!HAS_OVERLAY(dev_priv))
1344                 return;
1345
1346         overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1347         if (!overlay)
1348                 return;
1349
1350         overlay->i915 = dev_priv;
1351
1352         overlay->color_key = 0x0101fe;
1353         overlay->color_key_enabled = true;
1354         overlay->brightness = -19;
1355         overlay->contrast = 75;
1356         overlay->saturation = 146;
1357
1358         init_request_active(&overlay->last_flip, NULL);
1359
1360         mutex_lock(&dev_priv->drm.struct_mutex);
1361
1362         ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
1363         if (ret)
1364                 goto out_free;
1365
1366         ret = i915_gem_object_set_to_gtt_domain(overlay->reg_bo, true);
1367         if (ret)
1368                 goto out_reg_bo;
1369
1370         mutex_unlock(&dev_priv->drm.struct_mutex);
1371
1372         memset_io(overlay->regs, 0, sizeof(struct overlay_registers));
1373         update_polyphase_filter(overlay->regs);
1374         update_reg_attrs(overlay, overlay->regs);
1375
1376         dev_priv->overlay = overlay;
1377         DRM_INFO("Initialized overlay support.\n");
1378         return;
1379
1380 out_reg_bo:
1381         i915_gem_object_put(overlay->reg_bo);
1382 out_free:
1383         mutex_unlock(&dev_priv->drm.struct_mutex);
1384         kfree(overlay);
1385 }
1386
1387 void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
1388 {
1389         struct intel_overlay *overlay;
1390
1391         overlay = fetch_and_zero(&dev_priv->overlay);
1392         if (!overlay)
1393                 return;
1394
1395         /*
1396          * The bo's should be free'd by the generic code already.
1397          * Furthermore modesetting teardown happens beforehand so the
1398          * hardware should be off already.
1399          */
1400         WARN_ON(overlay->active);
1401
1402         i915_gem_object_put(overlay->reg_bo);
1403
1404         kfree(overlay);
1405 }
1406
1407 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1408
1409 struct intel_overlay_error_state {
1410         struct overlay_registers regs;
1411         unsigned long base;
1412         u32 dovsta;
1413         u32 isr;
1414 };
1415
1416 struct intel_overlay_error_state *
1417 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1418 {
1419         struct intel_overlay *overlay = dev_priv->overlay;
1420         struct intel_overlay_error_state *error;
1421
1422         if (!overlay || !overlay->active)
1423                 return NULL;
1424
1425         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1426         if (error == NULL)
1427                 return NULL;
1428
1429         error->dovsta = I915_READ(DOVSTA);
1430         error->isr = I915_READ(ISR);
1431         error->base = overlay->flip_addr;
1432
1433         memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
1434
1435         return error;
1436 }
1437
1438 void
1439 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1440                                 struct intel_overlay_error_state *error)
1441 {
1442         i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1443                           error->dovsta, error->isr);
1444         i915_error_printf(m, "  Register file at 0x%08lx:\n",
1445                           error->base);
1446
1447 #define P(x) i915_error_printf(m, "    " #x ":  0x%08x\n", error->regs.x)
1448         P(OBUF_0Y);
1449         P(OBUF_1Y);
1450         P(OBUF_0U);
1451         P(OBUF_0V);
1452         P(OBUF_1U);
1453         P(OBUF_1V);
1454         P(OSTRIDE);
1455         P(YRGB_VPH);
1456         P(UV_VPH);
1457         P(HORZ_PH);
1458         P(INIT_PHS);
1459         P(DWINPOS);
1460         P(DWINSZ);
1461         P(SWIDTH);
1462         P(SWIDTHSW);
1463         P(SHEIGHT);
1464         P(YRGBSCALE);
1465         P(UVSCALE);
1466         P(OCLRC0);
1467         P(OCLRC1);
1468         P(DCLRKV);
1469         P(DCLRKM);
1470         P(SCLRKVH);
1471         P(SCLRKVL);
1472         P(SCLRKEN);
1473         P(OCONFIG);
1474         P(OCMD);
1475         P(OSTART_0Y);
1476         P(OSTART_1Y);
1477         P(OSTART_0U);
1478         P(OSTART_0V);
1479         P(OSTART_1U);
1480         P(OSTART_1V);
1481         P(OTILEOFF_0Y);
1482         P(OTILEOFF_1Y);
1483         P(OTILEOFF_0U);
1484         P(OTILEOFF_0V);
1485         P(OTILEOFF_1U);
1486         P(OTILEOFF_1V);
1487         P(FASTHSCALE);
1488         P(UVSCALEV);
1489 #undef P
1490 }
1491
1492 #endif