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23 #include "intel_mocs.h"
24 #include "intel_lrc.h"
25 #include "intel_ringbuffer.h"
27 /* structures required */
28 struct drm_i915_mocs_entry {
34 struct drm_i915_mocs_table {
36 unsigned int n_entries;
37 const struct drm_i915_mocs_entry *table;
40 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
41 #define _LE_CACHEABILITY(value) ((value) << 0)
42 #define _LE_TGT_CACHE(value) ((value) << 2)
43 #define LE_LRUM(value) ((value) << 4)
44 #define LE_AOM(value) ((value) << 6)
45 #define LE_RSC(value) ((value) << 7)
46 #define LE_SCC(value) ((value) << 8)
47 #define LE_PFM(value) ((value) << 11)
48 #define LE_SCF(value) ((value) << 14)
49 #define LE_COS(value) ((value) << 15)
50 #define LE_SSE(value) ((value) << 17)
52 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
53 #define L3_ESC(value) ((value) << 0)
54 #define L3_SCC(value) ((value) << 1)
55 #define _L3_CACHEABILITY(value) ((value) << 4)
58 #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
59 #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
61 /* (e)LLC caching options */
62 #define LE_0_PAGETABLE _LE_CACHEABILITY(0)
63 #define LE_1_UC _LE_CACHEABILITY(1)
64 #define LE_2_WT _LE_CACHEABILITY(2)
65 #define LE_3_WB _LE_CACHEABILITY(3)
68 #define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0)
69 #define LE_TC_1_LLC _LE_TGT_CACHE(1)
70 #define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2)
71 #define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3)
73 /* L3 caching options */
74 #define L3_0_DIRECT _L3_CACHEABILITY(0)
75 #define L3_1_UC _L3_CACHEABILITY(1)
76 #define L3_2_RESERVED _L3_CACHEABILITY(2)
77 #define L3_3_WB _L3_CACHEABILITY(3)
79 #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
81 .control_value = __control_value, \
82 .l3cc_value = __l3cc_value, \
89 * These are the MOCS tables that are programmed across all the rings.
90 * The control value is programmed to all the rings that support the
91 * MOCS registers. While the l3cc_values are only programmed to the
92 * LNCFCMOCS0 - LNCFCMOCS32 registers.
94 * These tables are intended to be kept reasonably consistent across
95 * HW platforms, and for ICL+, be identical across OSes. To achieve
96 * that, for Icelake and above, list of entries is published as part
99 * Entries not part of the following tables are undefined as far as
100 * userspace is concerned and shouldn't be relied upon. For the time
101 * being they will be initialized to PTE.
103 * The last two entries are reserved by the hardware. For ICL+ they
104 * should be initialized according to bspec and never used, for older
105 * platforms they should never be written to.
107 * NOTE: These tables are part of bspec and defined as part of hardware
108 * interface for ICL+. For older platforms, they are part of kernel
109 * ABI. It is expected that, for specific hardware platform, existing
110 * entries will remain constant and the table will only be updated by
111 * adding new entries, filling unused positions.
113 #define GEN9_MOCS_ENTRIES \
114 MOCS_ENTRY(I915_MOCS_UNCACHED, \
115 LE_1_UC | LE_TC_2_LLC_ELLC, \
117 MOCS_ENTRY(I915_MOCS_PTE, \
118 LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \
121 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
123 MOCS_ENTRY(I915_MOCS_CACHED,
124 LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
128 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
129 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
131 MOCS_ENTRY(I915_MOCS_CACHED,
132 LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
136 #define GEN11_MOCS_ENTRIES \
137 /* Base - Uncached (Deprecated) */ \
138 MOCS_ENTRY(I915_MOCS_UNCACHED, \
139 LE_1_UC | LE_TC_1_LLC, \
141 /* Base - L3 + LeCC:PAT (Deprecated) */ \
142 MOCS_ENTRY(I915_MOCS_PTE, \
143 LE_0_PAGETABLE | LE_TC_1_LLC, \
145 /* Base - L3 + LLC */ \
147 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
149 /* Base - Uncached */ \
151 LE_1_UC | LE_TC_1_LLC, \
155 LE_1_UC | LE_TC_1_LLC, \
159 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
163 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
165 /* Age 0 - L3 + LLC */ \
167 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
169 /* Age: Don't Chg. - LLC */ \
171 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
173 /* Age: Don't Chg. - L3 + LLC */ \
175 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
179 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
181 /* No AOM - L3 + LLC */ \
183 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
185 /* No AOM; Age 0 - LLC */ \
187 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
189 /* No AOM; Age 0 - L3 + LLC */ \
191 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
193 /* No AOM; Age:DC - LLC */ \
195 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
197 /* No AOM; Age:DC - L3 + LLC */ \
199 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
201 /* Self-Snoop - L3 + LLC */ \
203 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
205 /* Skip Caching - L3 + LLC(12.5%) */ \
207 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \
209 /* Skip Caching - L3 + LLC(25%) */ \
211 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \
213 /* Skip Caching - L3 + LLC(50%) */ \
215 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \
217 /* Skip Caching - L3 + LLC(75%) */ \
219 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \
221 /* Skip Caching - L3 + LLC(87.5%) */ \
223 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
225 /* HW Reserved - SW program but never use */ \
227 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
229 /* HW Reserved - SW program but never use */ \
231 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
234 static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
239 * get_mocs_settings()
240 * @dev_priv: i915 device.
241 * @table: Output table that will be made to point at appropriate
242 * MOCS values for the device.
244 * This function will return the values of the MOCS table that needs to
245 * be programmed for the platform. It will return the values that need
246 * to be programmed and if they need to be programmed.
248 * Return: true if there are applicable MOCS settings for the device.
250 static bool get_mocs_settings(struct drm_i915_private *dev_priv,
251 struct drm_i915_mocs_table *table)
255 if (IS_ICELAKE(dev_priv)) {
256 table->size = ARRAY_SIZE(icelake_mocs_table);
257 table->table = icelake_mocs_table;
258 table->n_entries = GEN11_NUM_MOCS_ENTRIES;
260 } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
261 table->size = ARRAY_SIZE(skylake_mocs_table);
262 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
263 table->table = skylake_mocs_table;
265 } else if (IS_GEN9_LP(dev_priv)) {
266 table->size = ARRAY_SIZE(broxton_mocs_table);
267 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
268 table->table = broxton_mocs_table;
271 WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
272 "Platform that should have a MOCS table does not.\n");
275 /* WaDisableSkipCaching:skl,bxt,kbl,glk */
276 if (IS_GEN(dev_priv, 9)) {
279 for (i = 0; i < table->size; i++)
280 if (WARN_ON(table->table[i].l3cc_value &
281 (L3_ESC(1) | L3_SCC(0x7))))
288 static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
292 return GEN9_GFX_MOCS(index);
294 return GEN9_MFX0_MOCS(index);
296 return GEN9_BLT_MOCS(index);
298 return GEN9_VEBOX_MOCS(index);
300 return GEN9_MFX1_MOCS(index);
302 return GEN11_MFX2_MOCS(index);
304 MISSING_CASE(engine_id);
305 return INVALID_MMIO_REG;
310 * Get control_value from MOCS entry taking into account when it's not used:
311 * I915_MOCS_PTE's value is returned in this case.
313 static u32 get_entry_control(const struct drm_i915_mocs_table *table,
316 if (table->table[index].used)
317 return table->table[index].control_value;
319 return table->table[I915_MOCS_PTE].control_value;
323 * intel_mocs_init_engine() - emit the mocs control table
324 * @engine: The engine for whom to emit the registers.
326 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
327 * given table starting at the given address.
329 void intel_mocs_init_engine(struct intel_engine_cs *engine)
331 struct drm_i915_private *dev_priv = engine->i915;
332 struct drm_i915_mocs_table table;
336 if (!get_mocs_settings(dev_priv, &table))
339 /* Set unused values to PTE */
340 unused_value = table.table[I915_MOCS_PTE].control_value;
342 for (index = 0; index < table.size; index++) {
343 u32 value = get_entry_control(&table, index);
345 I915_WRITE(mocs_register(engine->id, index), value);
348 /* All remaining entries are also unused */
349 for (; index < table.n_entries; index++)
350 I915_WRITE(mocs_register(engine->id, index), unused_value);
354 * emit_mocs_control_table() - emit the mocs control table
355 * @rq: Request to set up the MOCS table for.
356 * @table: The values to program into the control regs.
358 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
359 * given table starting at the given address.
361 * Return: 0 on success, otherwise the error status.
363 static int emit_mocs_control_table(struct i915_request *rq,
364 const struct drm_i915_mocs_table *table)
366 enum intel_engine_id engine = rq->engine->id;
371 if (GEM_WARN_ON(table->size > table->n_entries))
374 /* Set unused values to PTE */
375 unused_value = table->table[I915_MOCS_PTE].control_value;
377 cs = intel_ring_begin(rq, 2 + 2 * table->n_entries);
381 *cs++ = MI_LOAD_REGISTER_IMM(table->n_entries);
383 for (index = 0; index < table->size; index++) {
384 u32 value = get_entry_control(table, index);
386 *cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
390 /* All remaining entries are also unused */
391 for (; index < table->n_entries; index++) {
392 *cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
393 *cs++ = unused_value;
397 intel_ring_advance(rq, cs);
403 * Get l3cc_value from MOCS entry taking into account when it's not used:
404 * I915_MOCS_PTE's value is returned in this case.
406 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
409 if (table->table[index].used)
410 return table->table[index].l3cc_value;
412 return table->table[I915_MOCS_PTE].l3cc_value;
415 static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
419 return low | high << 16;
423 * emit_mocs_l3cc_table() - emit the mocs control table
424 * @rq: Request to set up the MOCS table for.
425 * @table: The values to program into the control regs.
427 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
428 * given table starting at the given address. This register set is
429 * programmed in pairs.
431 * Return: 0 on success, otherwise the error status.
433 static int emit_mocs_l3cc_table(struct i915_request *rq,
434 const struct drm_i915_mocs_table *table)
440 if (GEM_WARN_ON(table->size > table->n_entries))
443 /* Set unused values to PTE */
444 unused_value = table->table[I915_MOCS_PTE].l3cc_value;
446 cs = intel_ring_begin(rq, 2 + table->n_entries);
450 *cs++ = MI_LOAD_REGISTER_IMM(table->n_entries / 2);
452 for (i = 0; i < table->size / 2; i++) {
453 u16 low = get_entry_l3cc(table, 2 * i);
454 u16 high = get_entry_l3cc(table, 2 * i + 1);
456 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
457 *cs++ = l3cc_combine(table, low, high);
460 /* Odd table size - 1 left over */
461 if (table->size & 0x01) {
462 u16 low = get_entry_l3cc(table, 2 * i);
464 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
465 *cs++ = l3cc_combine(table, low, unused_value);
469 /* All remaining entries are also unused */
470 for (; i < table->n_entries / 2; i++) {
471 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
472 *cs++ = l3cc_combine(table, unused_value, unused_value);
476 intel_ring_advance(rq, cs);
482 * intel_mocs_init_l3cc_table() - program the mocs control table
483 * @dev_priv: i915 device private
485 * This function simply programs the mocs registers for the given table
486 * starting at the given address. This register set is programmed in pairs.
488 * These registers may get programmed more than once, it is simpler to
489 * re-program 32 registers than maintain the state of when they were programmed.
490 * We are always reprogramming with the same values and this only on context
495 void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
497 struct drm_i915_mocs_table table;
501 if (!get_mocs_settings(dev_priv, &table))
504 /* Set unused values to PTE */
505 unused_value = table.table[I915_MOCS_PTE].l3cc_value;
507 for (i = 0; i < table.size / 2; i++) {
508 u16 low = get_entry_l3cc(&table, 2 * i);
509 u16 high = get_entry_l3cc(&table, 2 * i + 1);
511 I915_WRITE(GEN9_LNCFCMOCS(i),
512 l3cc_combine(&table, low, high));
515 /* Odd table size - 1 left over */
516 if (table.size & 0x01) {
517 u16 low = get_entry_l3cc(&table, 2 * i);
519 I915_WRITE(GEN9_LNCFCMOCS(i),
520 l3cc_combine(&table, low, unused_value));
524 /* All remaining entries are also unused */
525 for (; i < table.n_entries / 2; i++)
526 I915_WRITE(GEN9_LNCFCMOCS(i),
527 l3cc_combine(&table, unused_value, unused_value));
531 * intel_rcs_context_init_mocs() - program the MOCS register.
532 * @rq: Request to set up the MOCS tables for.
534 * This function will emit a batch buffer with the values required for
535 * programming the MOCS register values for all the currently supported
538 * These registers are partially stored in the RCS context, so they are
539 * emitted at the same time so that when a context is created these registers
540 * are set up. These registers have to be emitted into the start of the
541 * context as setting the ELSP will re-init some of these registers back
544 * Return: 0 on success, otherwise the error status.
546 int intel_rcs_context_init_mocs(struct i915_request *rq)
548 struct drm_i915_mocs_table t;
551 if (get_mocs_settings(rq->i915, &t)) {
552 /* Program the RCS control registers */
553 ret = emit_mocs_control_table(rq, &t);
557 /* Now program the l3cc registers */
558 ret = emit_mocs_l3cc_table(rq, &t);