drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include <drm/intel_lpe_audio.h>
  40 #include "i915_drv.h"
  41
  42 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  43 {
  44         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  45 }
  46
  47 static void
  48 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  49 {
  50         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  51         struct drm_i915_private *dev_priv = to_i915(dev);
  52         uint32_t enabled_bits;
  53
  54         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  55
  56         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  57              "HDMI port enabled, expecting disabled\n");
  58 }
  59
  60 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  61 {
  62         struct intel_digital_port *intel_dig_port =
  63                 container_of(encoder, struct intel_digital_port, base.base);
  64         return &intel_dig_port->hdmi;
  65 }
  66
  67 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  68 {
  69         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  70 }
  71
  72 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  73 {
  74         switch (type) {
  75         case HDMI_INFOFRAME_TYPE_AVI:
  76                 return VIDEO_DIP_SELECT_AVI;
  77         case HDMI_INFOFRAME_TYPE_SPD:
  78                 return VIDEO_DIP_SELECT_SPD;
  79         case HDMI_INFOFRAME_TYPE_VENDOR:
  80                 return VIDEO_DIP_SELECT_VENDOR;
  81         default:
  82                 MISSING_CASE(type);
  83                 return 0;
  84         }
  85 }
  86
  87 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  88 {
  89         switch (type) {
  90         case HDMI_INFOFRAME_TYPE_AVI:
  91                 return VIDEO_DIP_ENABLE_AVI;
  92         case HDMI_INFOFRAME_TYPE_SPD:
  93                 return VIDEO_DIP_ENABLE_SPD;
  94         case HDMI_INFOFRAME_TYPE_VENDOR:
  95                 return VIDEO_DIP_ENABLE_VENDOR;
  96         default:
  97                 MISSING_CASE(type);
  98                 return 0;
  99         }
 100 }
 101
 102 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 103 {
 104         switch (type) {
 105         case HDMI_INFOFRAME_TYPE_AVI:
 106                 return VIDEO_DIP_ENABLE_AVI_HSW;
 107         case HDMI_INFOFRAME_TYPE_SPD:
 108                 return VIDEO_DIP_ENABLE_SPD_HSW;
 109         case HDMI_INFOFRAME_TYPE_VENDOR:
 110                 return VIDEO_DIP_ENABLE_VS_HSW;
 111         default:
 112                 MISSING_CASE(type);
 113                 return 0;
 114         }
 115 }
 116
 117 static i915_reg_t
 118 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 119                  enum transcoder cpu_transcoder,
 120                  enum hdmi_infoframe_type type,
 121                  int i)
 122 {
 123         switch (type) {
 124         case HDMI_INFOFRAME_TYPE_AVI:
 125                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 126         case HDMI_INFOFRAME_TYPE_SPD:
 127                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 128         case HDMI_INFOFRAME_TYPE_VENDOR:
 129                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 130         default:
 131                 MISSING_CASE(type);
 132                 return INVALID_MMIO_REG;
 133         }
 134 }
 135
 136 static void g4x_write_infoframe(struct drm_encoder *encoder,
 137                                 const struct intel_crtc_state *crtc_state,
 138                                 enum hdmi_infoframe_type type,
 139                                 const void *frame, ssize_t len)
 140 {
 141         const uint32_t *data = frame;
 142         struct drm_device *dev = encoder->dev;
 143         struct drm_i915_private *dev_priv = to_i915(dev);
 144         u32 val = I915_READ(VIDEO_DIP_CTL);
 145         int i;
 146
 147         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 148
 149         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 150         val |= g4x_infoframe_index(type);
 151
 152         val &= ~g4x_infoframe_enable(type);
 153
 154         I915_WRITE(VIDEO_DIP_CTL, val);
 155
 156         mmiowb();
 157         for (i = 0; i < len; i += 4) {
 158                 I915_WRITE(VIDEO_DIP_DATA, *data);
 159                 data++;
 160         }
 161         /* Write every possible data byte to force correct ECC calculation. */
 162         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 163                 I915_WRITE(VIDEO_DIP_DATA, 0);
 164         mmiowb();
 165
 166         val |= g4x_infoframe_enable(type);
 167         val &= ~VIDEO_DIP_FREQ_MASK;
 168         val |= VIDEO_DIP_FREQ_VSYNC;
 169
 170         I915_WRITE(VIDEO_DIP_CTL, val);
 171         POSTING_READ(VIDEO_DIP_CTL);
 172 }
 173
 174 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
 175                                   const struct intel_crtc_state *pipe_config)
 176 {
 177         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 178         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 179         u32 val = I915_READ(VIDEO_DIP_CTL);
 180
 181         if ((val & VIDEO_DIP_ENABLE) == 0)
 182                 return false;
 183
 184         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 185                 return false;
 186
 187         return val & (VIDEO_DIP_ENABLE_AVI |
 188                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 189 }
 190
 191 static void ibx_write_infoframe(struct drm_encoder *encoder,
 192                                 const struct intel_crtc_state *crtc_state,
 193                                 enum hdmi_infoframe_type type,
 194                                 const void *frame, ssize_t len)
 195 {
 196         const uint32_t *data = frame;
 197         struct drm_device *dev = encoder->dev;
 198         struct drm_i915_private *dev_priv = to_i915(dev);
 199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 200         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 201         u32 val = I915_READ(reg);
 202         int i;
 203
 204         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 205
 206         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 207         val |= g4x_infoframe_index(type);
 208
 209         val &= ~g4x_infoframe_enable(type);
 210
 211         I915_WRITE(reg, val);
 212
 213         mmiowb();
 214         for (i = 0; i < len; i += 4) {
 215                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 216                 data++;
 217         }
 218         /* Write every possible data byte to force correct ECC calculation. */
 219         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 220                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 221         mmiowb();
 222
 223         val |= g4x_infoframe_enable(type);
 224         val &= ~VIDEO_DIP_FREQ_MASK;
 225         val |= VIDEO_DIP_FREQ_VSYNC;
 226
 227         I915_WRITE(reg, val);
 228         POSTING_READ(reg);
 229 }
 230
 231 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
 232                                   const struct intel_crtc_state *pipe_config)
 233 {
 234         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 235         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 236         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 237         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 238         u32 val = I915_READ(reg);
 239
 240         if ((val & VIDEO_DIP_ENABLE) == 0)
 241                 return false;
 242
 243         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 244                 return false;
 245
 246         return val & (VIDEO_DIP_ENABLE_AVI |
 247                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 248                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 249 }
 250
 251 static void cpt_write_infoframe(struct drm_encoder *encoder,
 252                                 const struct intel_crtc_state *crtc_state,
 253                                 enum hdmi_infoframe_type type,
 254                                 const void *frame, ssize_t len)
 255 {
 256         const uint32_t *data = frame;
 257         struct drm_device *dev = encoder->dev;
 258         struct drm_i915_private *dev_priv = to_i915(dev);
 259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 260         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 261         u32 val = I915_READ(reg);
 262         int i;
 263
 264         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 265
 266         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 267         val |= g4x_infoframe_index(type);
 268
 269         /* The DIP control register spec says that we need to update the AVI
 270          * infoframe without clearing its enable bit */
 271         if (type != HDMI_INFOFRAME_TYPE_AVI)
 272                 val &= ~g4x_infoframe_enable(type);
 273
 274         I915_WRITE(reg, val);
 275
 276         mmiowb();
 277         for (i = 0; i < len; i += 4) {
 278                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 279                 data++;
 280         }
 281         /* Write every possible data byte to force correct ECC calculation. */
 282         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 283                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 284         mmiowb();
 285
 286         val |= g4x_infoframe_enable(type);
 287         val &= ~VIDEO_DIP_FREQ_MASK;
 288         val |= VIDEO_DIP_FREQ_VSYNC;
 289
 290         I915_WRITE(reg, val);
 291         POSTING_READ(reg);
 292 }
 293
 294 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
 295                                   const struct intel_crtc_state *pipe_config)
 296 {
 297         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 298         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 299         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 300
 301         if ((val & VIDEO_DIP_ENABLE) == 0)
 302                 return false;
 303
 304         return val & (VIDEO_DIP_ENABLE_AVI |
 305                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 306                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 307 }
 308
 309 static void vlv_write_infoframe(struct drm_encoder *encoder,
 310                                 const struct intel_crtc_state *crtc_state,
 311                                 enum hdmi_infoframe_type type,
 312                                 const void *frame, ssize_t len)
 313 {
 314         const uint32_t *data = frame;
 315         struct drm_device *dev = encoder->dev;
 316         struct drm_i915_private *dev_priv = to_i915(dev);
 317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 318         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 319         u32 val = I915_READ(reg);
 320         int i;
 321
 322         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 323
 324         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 325         val |= g4x_infoframe_index(type);
 326
 327         val &= ~g4x_infoframe_enable(type);
 328
 329         I915_WRITE(reg, val);
 330
 331         mmiowb();
 332         for (i = 0; i < len; i += 4) {
 333                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 334                 data++;
 335         }
 336         /* Write every possible data byte to force correct ECC calculation. */
 337         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 338                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 339         mmiowb();
 340
 341         val |= g4x_infoframe_enable(type);
 342         val &= ~VIDEO_DIP_FREQ_MASK;
 343         val |= VIDEO_DIP_FREQ_VSYNC;
 344
 345         I915_WRITE(reg, val);
 346         POSTING_READ(reg);
 347 }
 348
 349 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
 350                                   const struct intel_crtc_state *pipe_config)
 351 {
 352         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 353         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 354         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 355         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 356
 357         if ((val & VIDEO_DIP_ENABLE) == 0)
 358                 return false;
 359
 360         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 361                 return false;
 362
 363         return val & (VIDEO_DIP_ENABLE_AVI |
 364                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 365                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 366 }
 367
 368 static void hsw_write_infoframe(struct drm_encoder *encoder,
 369                                 const struct intel_crtc_state *crtc_state,
 370                                 enum hdmi_infoframe_type type,
 371                                 const void *frame, ssize_t len)
 372 {
 373         const uint32_t *data = frame;
 374         struct drm_device *dev = encoder->dev;
 375         struct drm_i915_private *dev_priv = to_i915(dev);
 376         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 377         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 378         i915_reg_t data_reg;
 379         int i;
 380         u32 val = I915_READ(ctl_reg);
 381
 382         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
 383
 384         val &= ~hsw_infoframe_enable(type);
 385         I915_WRITE(ctl_reg, val);
 386
 387         mmiowb();
 388         for (i = 0; i < len; i += 4) {
 389                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 390                                             type, i >> 2), *data);
 391                 data++;
 392         }
 393         /* Write every possible data byte to force correct ECC calculation. */
 394         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 395                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 396                                             type, i >> 2), 0);
 397         mmiowb();
 398
 399         val |= hsw_infoframe_enable(type);
 400         I915_WRITE(ctl_reg, val);
 401         POSTING_READ(ctl_reg);
 402 }
 403
 404 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
 405                                   const struct intel_crtc_state *pipe_config)
 406 {
 407         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 408         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 409
 410         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 411                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 412                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 413 }
 414
 415 /*
 416  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 417  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 418  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 419  * used for both technologies.
 420  *
 421  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 422  * DW1:       DB3       | DB2 | DB1 | DB0
 423  * DW2:       DB7       | DB6 | DB5 | DB4
 424  * DW3: ...
 425  *
 426  * (HB is Header Byte, DB is Data Byte)
 427  *
 428  * The hdmi pack() functions don't know about that hardware specific hole so we
 429  * trick them by giving an offset into the buffer and moving back the header
 430  * bytes by one.
 431  */
 432 static void intel_write_infoframe(struct drm_encoder *encoder,
 433                                   const struct intel_crtc_state *crtc_state,
 434                                   union hdmi_infoframe *frame)
 435 {
 436         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 437         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 438         ssize_t len;
 439
 440         /* see comment above for the reason for this offset */
 441         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 442         if (len < 0)
 443                 return;
 444
 445         /* Insert the 'hole' (see big comment above) at position 3 */
 446         buffer[0] = buffer[1];
 447         buffer[1] = buffer[2];
 448         buffer[2] = buffer[3];
 449         buffer[3] = 0;
 450         len++;
 451
 452         intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
 453 }
 454
 455 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 456                                          const struct intel_crtc_state *crtc_state)
 457 {
 458         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 459         const struct drm_display_mode *adjusted_mode =
 460                 &crtc_state->base.adjusted_mode;
 461         union hdmi_infoframe frame;
 462         int ret;
 463
 464         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 465                                                        adjusted_mode);
 466         if (ret < 0) {
 467                 DRM_ERROR("couldn't fill AVI infoframe\n");
 468                 return;
 469         }
 470
 471         drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
 472                                            crtc_state->limited_color_range ?
 473                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 474                                            HDMI_QUANTIZATION_RANGE_FULL,
 475                                            intel_hdmi->rgb_quant_range_selectable);
 476
 477         intel_write_infoframe(encoder, crtc_state, &frame);
 478 }
 479
 480 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
 481                                          const struct intel_crtc_state *crtc_state)
 482 {
 483         union hdmi_infoframe frame;
 484         int ret;
 485
 486         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 487         if (ret < 0) {
 488                 DRM_ERROR("couldn't fill SPD infoframe\n");
 489                 return;
 490         }
 491
 492         frame.spd.sdi = HDMI_SPD_SDI_PC;
 493
 494         intel_write_infoframe(encoder, crtc_state, &frame);
 495 }
 496
 497 static void
 498 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 499                               const struct intel_crtc_state *crtc_state)
 500 {
 501         union hdmi_infoframe frame;
 502         int ret;
 503
 504         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 505                                                           &crtc_state->base.adjusted_mode);
 506         if (ret < 0)
 507                 return;
 508
 509         intel_write_infoframe(encoder, crtc_state, &frame);
 510 }
 511
 512 static void g4x_set_infoframes(struct drm_encoder *encoder,
 513                                bool enable,
 514                                const struct intel_crtc_state *crtc_state,
 515                                const struct drm_connector_state *conn_state)
 516 {
 517         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 518         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 519         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 520         i915_reg_t reg = VIDEO_DIP_CTL;
 521         u32 val = I915_READ(reg);
 522         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 523
 524         assert_hdmi_port_disabled(intel_hdmi);
 525
 526         /* If the registers were not initialized yet, they might be zeroes,
 527          * which means we're selecting the AVI DIP and we're setting its
 528          * frequency to once. This seems to really confuse the HW and make
 529          * things stop working (the register spec says the AVI always needs to
 530          * be sent every VSync). So here we avoid writing to the register more
 531          * than we need and also explicitly select the AVI DIP and explicitly
 532          * set its frequency to every VSync. Avoiding to write it twice seems to
 533          * be enough to solve the problem, but being defensive shouldn't hurt us
 534          * either. */
 535         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 536
 537         if (!enable) {
 538                 if (!(val & VIDEO_DIP_ENABLE))
 539                         return;
 540                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 541                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 542                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 543                         return;
 544                 }
 545                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 546                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 547                 I915_WRITE(reg, val);
 548                 POSTING_READ(reg);
 549                 return;
 550         }
 551
 552         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 553                 if (val & VIDEO_DIP_ENABLE) {
 554                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 555                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 556                         return;
 557                 }
 558                 val &= ~VIDEO_DIP_PORT_MASK;
 559                 val |= port;
 560         }
 561
 562         val |= VIDEO_DIP_ENABLE;
 563         val &= ~(VIDEO_DIP_ENABLE_AVI |
 564                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 565
 566         I915_WRITE(reg, val);
 567         POSTING_READ(reg);
 568
 569         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 570         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 571         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 572 }
 573
 574 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
 575 {
 576         struct drm_connector *connector = conn_state->connector;
 577
 578         /*
 579          * HDMI cloning is only supported on g4x which doesn't
 580          * support deep color or GCP infoframes anyway so no
 581          * need to worry about multiple HDMI sinks here.
 582          */
 583
 584         return connector->display_info.bpc > 8;
 585 }
 586
 587 /*
 588  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 589  *
 590  * From HDMI specification 1.4a:
 591  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 592  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 593  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 594  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 595  *   phase of 0
 596  */
 597 static bool gcp_default_phase_possible(int pipe_bpp,
 598                                        const struct drm_display_mode *mode)
 599 {
 600         unsigned int pixels_per_group;
 601
 602         switch (pipe_bpp) {
 603         case 30:
 604                 /* 4 pixels in 5 clocks */
 605                 pixels_per_group = 4;
 606                 break;
 607         case 36:
 608                 /* 2 pixels in 3 clocks */
 609                 pixels_per_group = 2;
 610                 break;
 611         case 48:
 612                 /* 1 pixel in 2 clocks */
 613                 pixels_per_group = 1;
 614                 break;
 615         default:
 616                 /* phase information not relevant for 8bpc */
 617                 return false;
 618         }
 619
 620         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 621                 mode->crtc_htotal % pixels_per_group == 0 &&
 622                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 623                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 624                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 625                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 626                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 627                  mode->crtc_htotal/2 % pixels_per_group == 0);
 628 }
 629
 630 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
 631                                          const struct intel_crtc_state *crtc_state,
 632                                          const struct drm_connector_state *conn_state)
 633 {
 634         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 635         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 636         i915_reg_t reg;
 637         u32 val = 0;
 638
 639         if (HAS_DDI(dev_priv))
 640                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 641         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 642                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 643         else if (HAS_PCH_SPLIT(dev_priv))
 644                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 645         else
 646                 return false;
 647
 648         /* Indicate color depth whenever the sink supports deep color */
 649         if (hdmi_sink_is_deep_color(conn_state))
 650                 val |= GCP_COLOR_INDICATION;
 651
 652         /* Enable default_phase whenever the display mode is suitably aligned */
 653         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
 654                                        &crtc_state->base.adjusted_mode))
 655                 val |= GCP_DEFAULT_PHASE_ENABLE;
 656
 657         I915_WRITE(reg, val);
 658
 659         return val != 0;
 660 }
 661
 662 static void ibx_set_infoframes(struct drm_encoder *encoder,
 663                                bool enable,
 664                                const struct intel_crtc_state *crtc_state,
 665                                const struct drm_connector_state *conn_state)
 666 {
 667         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 669         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 670         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 671         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 672         u32 val = I915_READ(reg);
 673         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 674
 675         assert_hdmi_port_disabled(intel_hdmi);
 676
 677         /* See the big comment in g4x_set_infoframes() */
 678         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 679
 680         if (!enable) {
 681                 if (!(val & VIDEO_DIP_ENABLE))
 682                         return;
 683                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 684                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 685                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 686                 I915_WRITE(reg, val);
 687                 POSTING_READ(reg);
 688                 return;
 689         }
 690
 691         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 692                 WARN(val & VIDEO_DIP_ENABLE,
 693                      "DIP already enabled on port %c\n",
 694                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 695                 val &= ~VIDEO_DIP_PORT_MASK;
 696                 val |= port;
 697         }
 698
 699         val |= VIDEO_DIP_ENABLE;
 700         val &= ~(VIDEO_DIP_ENABLE_AVI |
 701                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 702                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 703
 704         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 705                 val |= VIDEO_DIP_ENABLE_GCP;
 706
 707         I915_WRITE(reg, val);
 708         POSTING_READ(reg);
 709
 710         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 711         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 712         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 713 }
 714
 715 static void cpt_set_infoframes(struct drm_encoder *encoder,
 716                                bool enable,
 717                                const struct intel_crtc_state *crtc_state,
 718                                const struct drm_connector_state *conn_state)
 719 {
 720         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 721         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 722         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 723         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 724         u32 val = I915_READ(reg);
 725
 726         assert_hdmi_port_disabled(intel_hdmi);
 727
 728         /* See the big comment in g4x_set_infoframes() */
 729         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 730
 731         if (!enable) {
 732                 if (!(val & VIDEO_DIP_ENABLE))
 733                         return;
 734                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 735                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 736                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 737                 I915_WRITE(reg, val);
 738                 POSTING_READ(reg);
 739                 return;
 740         }
 741
 742         /* Set both together, unset both together: see the spec. */
 743         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 744         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 745                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 746
 747         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 748                 val |= VIDEO_DIP_ENABLE_GCP;
 749
 750         I915_WRITE(reg, val);
 751         POSTING_READ(reg);
 752
 753         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 754         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 755         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 756 }
 757
 758 static void vlv_set_infoframes(struct drm_encoder *encoder,
 759                                bool enable,
 760                                const struct intel_crtc_state *crtc_state,
 761                                const struct drm_connector_state *conn_state)
 762 {
 763         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 764         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 766         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 767         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 768         u32 val = I915_READ(reg);
 769         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 770
 771         assert_hdmi_port_disabled(intel_hdmi);
 772
 773         /* See the big comment in g4x_set_infoframes() */
 774         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 775
 776         if (!enable) {
 777                 if (!(val & VIDEO_DIP_ENABLE))
 778                         return;
 779                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 780                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 781                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 782                 I915_WRITE(reg, val);
 783                 POSTING_READ(reg);
 784                 return;
 785         }
 786
 787         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 788                 WARN(val & VIDEO_DIP_ENABLE,
 789                      "DIP already enabled on port %c\n",
 790                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 791                 val &= ~VIDEO_DIP_PORT_MASK;
 792                 val |= port;
 793         }
 794
 795         val |= VIDEO_DIP_ENABLE;
 796         val &= ~(VIDEO_DIP_ENABLE_AVI |
 797                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 798                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 799
 800         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 801                 val |= VIDEO_DIP_ENABLE_GCP;
 802
 803         I915_WRITE(reg, val);
 804         POSTING_READ(reg);
 805
 806         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 807         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 808         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 809 }
 810
 811 static void hsw_set_infoframes(struct drm_encoder *encoder,
 812                                bool enable,
 813                                const struct intel_crtc_state *crtc_state,
 814                                const struct drm_connector_state *conn_state)
 815 {
 816         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 817         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 818         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
 819         u32 val = I915_READ(reg);
 820
 821         assert_hdmi_port_disabled(intel_hdmi);
 822
 823         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 824                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 825                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 826
 827         if (!enable) {
 828                 I915_WRITE(reg, val);
 829                 POSTING_READ(reg);
 830                 return;
 831         }
 832
 833         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 834                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 835
 836         I915_WRITE(reg, val);
 837         POSTING_READ(reg);
 838
 839         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 840         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 841         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 842 }
 843
 844 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
 845 {
 846         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
 847         struct i2c_adapter *adapter =
 848                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
 849
 850         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
 851                 return;
 852
 853         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
 854                       enable ? "Enabling" : "Disabling");
 855
 856         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
 857                                          adapter, enable);
 858 }
 859
 860 static void intel_hdmi_prepare(struct intel_encoder *encoder,
 861                                const struct intel_crtc_state *crtc_state)
 862 {
 863         struct drm_device *dev = encoder->base.dev;
 864         struct drm_i915_private *dev_priv = to_i915(dev);
 865         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 866         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 867         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 868         u32 hdmi_val;
 869
 870         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
 871
 872         hdmi_val = SDVO_ENCODING_HDMI;
 873         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
 874                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
 875         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 876                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 877         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 878                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 879
 880         if (crtc_state->pipe_bpp > 24)
 881                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 882         else
 883                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 884
 885         if (crtc_state->has_hdmi_sink)
 886                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 887
 888         if (HAS_PCH_CPT(dev_priv))
 889                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 890         else if (IS_CHERRYVIEW(dev_priv))
 891                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 892         else
 893                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 894
 895         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 896         POSTING_READ(intel_hdmi->hdmi_reg);
 897 }
 898
 899 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 900                                     enum pipe *pipe)
 901 {
 902         struct drm_device *dev = encoder->base.dev;
 903         struct drm_i915_private *dev_priv = to_i915(dev);
 904         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 905         enum intel_display_power_domain power_domain;
 906         u32 tmp;
 907         bool ret;
 908
 909         power_domain = intel_display_port_power_domain(encoder);
 910         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 911                 return false;
 912
 913         ret = false;
 914
 915         tmp = I915_READ(intel_hdmi->hdmi_reg);
 916
 917         if (!(tmp & SDVO_ENABLE))
 918                 goto out;
 919
 920         if (HAS_PCH_CPT(dev_priv))
 921                 *pipe = PORT_TO_PIPE_CPT(tmp);
 922         else if (IS_CHERRYVIEW(dev_priv))
 923                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 924         else
 925                 *pipe = PORT_TO_PIPE(tmp);
 926
 927         ret = true;
 928
 929 out:
 930         intel_display_power_put(dev_priv, power_domain);
 931
 932         return ret;
 933 }
 934
 935 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 936                                   struct intel_crtc_state *pipe_config)
 937 {
 938         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 939         struct drm_device *dev = encoder->base.dev;
 940         struct drm_i915_private *dev_priv = to_i915(dev);
 941         u32 tmp, flags = 0;
 942         int dotclock;
 943
 944         tmp = I915_READ(intel_hdmi->hdmi_reg);
 945
 946         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 947                 flags |= DRM_MODE_FLAG_PHSYNC;
 948         else
 949                 flags |= DRM_MODE_FLAG_NHSYNC;
 950
 951         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 952                 flags |= DRM_MODE_FLAG_PVSYNC;
 953         else
 954                 flags |= DRM_MODE_FLAG_NVSYNC;
 955
 956         if (tmp & HDMI_MODE_SELECT_HDMI)
 957                 pipe_config->has_hdmi_sink = true;
 958
 959         if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
 960                 pipe_config->has_infoframe = true;
 961
 962         if (tmp & SDVO_AUDIO_ENABLE)
 963                 pipe_config->has_audio = true;
 964
 965         if (!HAS_PCH_SPLIT(dev_priv) &&
 966             tmp & HDMI_COLOR_RANGE_16_235)
 967                 pipe_config->limited_color_range = true;
 968
 969         pipe_config->base.adjusted_mode.flags |= flags;
 970
 971         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 972                 dotclock = pipe_config->port_clock * 2 / 3;
 973         else
 974                 dotclock = pipe_config->port_clock;
 975
 976         if (pipe_config->pixel_multiplier)
 977                 dotclock /= pipe_config->pixel_multiplier;
 978
 979         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 980
 981         pipe_config->lane_count = 4;
 982 }
 983
 984 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
 985                                     struct intel_crtc_state *pipe_config,
 986                                     struct drm_connector_state *conn_state)
 987 {
 988         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 989
 990         WARN_ON(!pipe_config->has_hdmi_sink);
 991         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 992                          pipe_name(crtc->pipe));
 993         intel_audio_codec_enable(encoder, pipe_config, conn_state);
 994 }
 995
 996 static void g4x_enable_hdmi(struct intel_encoder *encoder,
 997                             struct intel_crtc_state *pipe_config,
 998                             struct drm_connector_state *conn_state)
 999 {
1000         struct drm_device *dev = encoder->base.dev;
1001         struct drm_i915_private *dev_priv = to_i915(dev);
1002         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1003         u32 temp;
1004
1005         temp = I915_READ(intel_hdmi->hdmi_reg);
1006
1007         temp |= SDVO_ENABLE;
1008         if (pipe_config->has_audio)
1009                 temp |= SDVO_AUDIO_ENABLE;
1010
1011         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1012         POSTING_READ(intel_hdmi->hdmi_reg);
1013
1014         if (pipe_config->has_audio)
1015                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1016 }
1017
1018 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1019                             struct intel_crtc_state *pipe_config,
1020                             struct drm_connector_state *conn_state)
1021 {
1022         struct drm_device *dev = encoder->base.dev;
1023         struct drm_i915_private *dev_priv = to_i915(dev);
1024         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1025         u32 temp;
1026
1027         temp = I915_READ(intel_hdmi->hdmi_reg);
1028
1029         temp |= SDVO_ENABLE;
1030         if (pipe_config->has_audio)
1031                 temp |= SDVO_AUDIO_ENABLE;
1032
1033         /*
1034          * HW workaround, need to write this twice for issue
1035          * that may result in first write getting masked.
1036          */
1037         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1038         POSTING_READ(intel_hdmi->hdmi_reg);
1039         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1040         POSTING_READ(intel_hdmi->hdmi_reg);
1041
1042         /*
1043          * HW workaround, need to toggle enable bit off and on
1044          * for 12bpc with pixel repeat.
1045          *
1046          * FIXME: BSpec says this should be done at the end of
1047          * of the modeset sequence, so not sure if this isn't too soon.
1048          */
1049         if (pipe_config->pipe_bpp > 24 &&
1050             pipe_config->pixel_multiplier > 1) {
1051                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1052                 POSTING_READ(intel_hdmi->hdmi_reg);
1053
1054                 /*
1055                  * HW workaround, need to write this twice for issue
1056                  * that may result in first write getting masked.
1057                  */
1058                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1059                 POSTING_READ(intel_hdmi->hdmi_reg);
1060                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1061                 POSTING_READ(intel_hdmi->hdmi_reg);
1062         }
1063
1064         if (pipe_config->has_audio)
1065                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1066 }
1067
1068 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1069                             struct intel_crtc_state *pipe_config,
1070                             struct drm_connector_state *conn_state)
1071 {
1072         struct drm_device *dev = encoder->base.dev;
1073         struct drm_i915_private *dev_priv = to_i915(dev);
1074         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1075         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1076         enum pipe pipe = crtc->pipe;
1077         u32 temp;
1078
1079         temp = I915_READ(intel_hdmi->hdmi_reg);
1080
1081         temp |= SDVO_ENABLE;
1082         if (pipe_config->has_audio)
1083                 temp |= SDVO_AUDIO_ENABLE;
1084
1085         /*
1086          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1087          *
1088          * The procedure for 12bpc is as follows:
1089          * 1. disable HDMI clock gating
1090          * 2. enable HDMI with 8bpc
1091          * 3. enable HDMI with 12bpc
1092          * 4. enable HDMI clock gating
1093          */
1094
1095         if (pipe_config->pipe_bpp > 24) {
1096                 I915_WRITE(TRANS_CHICKEN1(pipe),
1097                            I915_READ(TRANS_CHICKEN1(pipe)) |
1098                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1099
1100                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1101                 temp |= SDVO_COLOR_FORMAT_8bpc;
1102         }
1103
1104         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1105         POSTING_READ(intel_hdmi->hdmi_reg);
1106
1107         if (pipe_config->pipe_bpp > 24) {
1108                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1109                 temp |= HDMI_COLOR_FORMAT_12bpc;
1110
1111                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1112                 POSTING_READ(intel_hdmi->hdmi_reg);
1113
1114                 I915_WRITE(TRANS_CHICKEN1(pipe),
1115                            I915_READ(TRANS_CHICKEN1(pipe)) &
1116                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1117         }
1118
1119         if (pipe_config->has_audio)
1120                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1121 }
1122
1123 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1124                             struct intel_crtc_state *pipe_config,
1125                             struct drm_connector_state *conn_state)
1126 {
1127 }
1128
1129 static void intel_disable_hdmi(struct intel_encoder *encoder,
1130                                struct intel_crtc_state *old_crtc_state,
1131                                struct drm_connector_state *old_conn_state)
1132 {
1133         struct drm_device *dev = encoder->base.dev;
1134         struct drm_i915_private *dev_priv = to_i915(dev);
1135         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1136         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1137         u32 temp;
1138
1139         temp = I915_READ(intel_hdmi->hdmi_reg);
1140
1141         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1142         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1143         POSTING_READ(intel_hdmi->hdmi_reg);
1144
1145         /*
1146          * HW workaround for IBX, we need to move the port
1147          * to transcoder A after disabling it to allow the
1148          * matching DP port to be enabled on transcoder A.
1149          */
1150         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1151                 /*
1152                  * We get CPU/PCH FIFO underruns on the other pipe when
1153                  * doing the workaround. Sweep them under the rug.
1154                  */
1155                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1156                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1157
1158                 temp &= ~SDVO_PIPE_B_SELECT;
1159                 temp |= SDVO_ENABLE;
1160                 /*
1161                  * HW workaround, need to write this twice for issue
1162                  * that may result in first write getting masked.
1163                  */
1164                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1165                 POSTING_READ(intel_hdmi->hdmi_reg);
1166                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1167                 POSTING_READ(intel_hdmi->hdmi_reg);
1168
1169                 temp &= ~SDVO_ENABLE;
1170                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1171                 POSTING_READ(intel_hdmi->hdmi_reg);
1172
1173                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1174                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1175                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1176         }
1177
1178         intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state);
1179
1180         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1181 }
1182
1183 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1184                              struct intel_crtc_state *old_crtc_state,
1185                              struct drm_connector_state *old_conn_state)
1186 {
1187         if (old_crtc_state->has_audio)
1188                 intel_audio_codec_disable(encoder);
1189
1190         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1191 }
1192
1193 static void pch_disable_hdmi(struct intel_encoder *encoder,
1194                              struct intel_crtc_state *old_crtc_state,
1195                              struct drm_connector_state *old_conn_state)
1196 {
1197         if (old_crtc_state->has_audio)
1198                 intel_audio_codec_disable(encoder);
1199 }
1200
1201 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1202                                   struct intel_crtc_state *old_crtc_state,
1203                                   struct drm_connector_state *old_conn_state)
1204 {
1205         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1206 }
1207
1208 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1209 {
1210         if (IS_G4X(dev_priv))
1211                 return 165000;
1212         else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1213                 return 300000;
1214         else
1215                 return 225000;
1216 }
1217
1218 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1219                                  bool respect_downstream_limits)
1220 {
1221         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1222         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1223
1224         if (respect_downstream_limits) {
1225                 struct intel_connector *connector = hdmi->attached_connector;
1226                 const struct drm_display_info *info = &connector->base.display_info;
1227
1228                 if (hdmi->dp_dual_mode.max_tmds_clock)
1229                         max_tmds_clock = min(max_tmds_clock,
1230                                              hdmi->dp_dual_mode.max_tmds_clock);
1231
1232                 if (info->max_tmds_clock)
1233                         max_tmds_clock = min(max_tmds_clock,
1234                                              info->max_tmds_clock);
1235                 else if (!hdmi->has_hdmi_sink)
1236                         max_tmds_clock = min(max_tmds_clock, 165000);
1237         }
1238
1239         return max_tmds_clock;
1240 }
1241
1242 static enum drm_mode_status
1243 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1244                       int clock, bool respect_downstream_limits)
1245 {
1246         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1247
1248         if (clock < 25000)
1249                 return MODE_CLOCK_LOW;
1250         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits))
1251                 return MODE_CLOCK_HIGH;
1252
1253         /* BXT DPLL can't generate 223-240 MHz */
1254         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1255                 return MODE_CLOCK_RANGE;
1256
1257         /* CHV DPLL can't generate 216-240 MHz */
1258         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1259                 return MODE_CLOCK_RANGE;
1260
1261         return MODE_OK;
1262 }
1263
1264 static enum drm_mode_status
1265 intel_hdmi_mode_valid(struct drm_connector *connector,
1266                       struct drm_display_mode *mode)
1267 {
1268         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1269         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1270         struct drm_i915_private *dev_priv = to_i915(dev);
1271         enum drm_mode_status status;
1272         int clock;
1273         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1274
1275         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1276                 return MODE_NO_DBLESCAN;
1277
1278         clock = mode->clock;
1279
1280         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1281                 clock *= 2;
1282
1283         if (clock > max_dotclk)
1284                 return MODE_CLOCK_HIGH;
1285
1286         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1287                 clock *= 2;
1288
1289         /* check if we can do 8bpc */
1290         status = hdmi_port_clock_valid(hdmi, clock, true);
1291
1292         /* if we can't do 8bpc we may still be able to do 12bpc */
1293         if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK)
1294                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1295
1296         return status;
1297 }
1298
1299 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1300 {
1301         struct drm_device *dev = crtc_state->base.crtc->dev;
1302
1303         if (HAS_GMCH_DISPLAY(to_i915(dev)))
1304                 return false;
1305
1306         /*
1307          * HDMI 12bpc affects the clocks, so it's only possible
1308          * when not cloning with other encoder types.
1309          */
1310         return crtc_state->output_types == 1 << INTEL_OUTPUT_HDMI;
1311 }
1312
1313 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1314                                struct intel_crtc_state *pipe_config,
1315                                struct drm_connector_state *conn_state)
1316 {
1317         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1318         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1319         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1320         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1321         int clock_12bpc = clock_8bpc * 3 / 2;
1322         int desired_bpp;
1323
1324         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1325
1326         if (pipe_config->has_hdmi_sink)
1327                 pipe_config->has_infoframe = true;
1328
1329         if (intel_hdmi->color_range_auto) {
1330                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1331                 pipe_config->limited_color_range =
1332                         pipe_config->has_hdmi_sink &&
1333                         drm_default_rgb_quant_range(adjusted_mode) ==
1334                         HDMI_QUANTIZATION_RANGE_LIMITED;
1335         } else {
1336                 pipe_config->limited_color_range =
1337                         intel_hdmi->limited_color_range;
1338         }
1339
1340         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1341                 pipe_config->pixel_multiplier = 2;
1342                 clock_8bpc *= 2;
1343                 clock_12bpc *= 2;
1344         }
1345
1346         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1347                 pipe_config->has_pch_encoder = true;
1348
1349         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1350                 pipe_config->has_audio = true;
1351
1352         /*
1353          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1354          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1355          * outputs. We also need to check that the higher clock still fits
1356          * within limits.
1357          */
1358         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1359             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK &&
1360             hdmi_12bpc_possible(pipe_config)) {
1361                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1362                 desired_bpp = 12*3;
1363
1364                 /* Need to adjust the port link by 1.5x for 12bpc. */
1365                 pipe_config->port_clock = clock_12bpc;
1366         } else {
1367                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1368                 desired_bpp = 8*3;
1369
1370                 pipe_config->port_clock = clock_8bpc;
1371         }
1372
1373         if (!pipe_config->bw_constrained) {
1374                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1375                 pipe_config->pipe_bpp = desired_bpp;
1376         }
1377
1378         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1379                                   false) != MODE_OK) {
1380                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1381                 return false;
1382         }
1383
1384         /* Set user selected PAR to incoming mode's member */
1385         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1386
1387         pipe_config->lane_count = 4;
1388
1389         return true;
1390 }
1391
1392 static void
1393 intel_hdmi_unset_edid(struct drm_connector *connector)
1394 {
1395         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1396
1397         intel_hdmi->has_hdmi_sink = false;
1398         intel_hdmi->has_audio = false;
1399         intel_hdmi->rgb_quant_range_selectable = false;
1400
1401         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1402         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1403
1404         kfree(to_intel_connector(connector)->detect_edid);
1405         to_intel_connector(connector)->detect_edid = NULL;
1406 }
1407
1408 static void
1409 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1410 {
1411         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1412         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1413         enum port port = hdmi_to_dig_port(hdmi)->port;
1414         struct i2c_adapter *adapter =
1415                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1416         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1417
1418         /*
1419          * Type 1 DVI adaptors are not required to implement any
1420          * registers, so we can't always detect their presence.
1421          * Ideally we should be able to check the state of the
1422          * CONFIG1 pin, but no such luck on our hardware.
1423          *
1424          * The only method left to us is to check the VBT to see
1425          * if the port is a dual mode capable DP port. But let's
1426          * only do that when we sucesfully read the EDID, to avoid
1427          * confusing log messages about DP dual mode adaptors when
1428          * there's nothing connected to the port.
1429          */
1430         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1431                 if (has_edid &&
1432                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1433                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1434                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1435                 } else {
1436                         type = DRM_DP_DUAL_MODE_NONE;
1437                 }
1438         }
1439
1440         if (type == DRM_DP_DUAL_MODE_NONE)
1441                 return;
1442
1443         hdmi->dp_dual_mode.type = type;
1444         hdmi->dp_dual_mode.max_tmds_clock =
1445                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1446
1447         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1448                       drm_dp_get_dual_mode_type_name(type),
1449                       hdmi->dp_dual_mode.max_tmds_clock);
1450 }
1451
1452 static bool
1453 intel_hdmi_set_edid(struct drm_connector *connector)
1454 {
1455         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1456         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1457         struct edid *edid;
1458         bool connected = false;
1459
1460         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1461
1462         edid = drm_get_edid(connector,
1463                             intel_gmbus_get_adapter(dev_priv,
1464                             intel_hdmi->ddc_bus));
1465
1466         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1467
1468         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1469
1470         to_intel_connector(connector)->detect_edid = edid;
1471         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1472                 intel_hdmi->rgb_quant_range_selectable =
1473                         drm_rgb_quant_range_selectable(edid);
1474
1475                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1476                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1477                         intel_hdmi->has_audio =
1478                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1479
1480                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1481                         intel_hdmi->has_hdmi_sink =
1482                                 drm_detect_hdmi_monitor(edid);
1483
1484                 connected = true;
1485         }
1486
1487         return connected;
1488 }
1489
1490 static enum drm_connector_status
1491 intel_hdmi_detect(struct drm_connector *connector, bool force)
1492 {
1493         enum drm_connector_status status;
1494         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1495
1496         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1497                       connector->base.id, connector->name);
1498
1499         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1500
1501         intel_hdmi_unset_edid(connector);
1502
1503         if (intel_hdmi_set_edid(connector)) {
1504                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1505
1506                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1507                 status = connector_status_connected;
1508         } else
1509                 status = connector_status_disconnected;
1510
1511         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1512
1513         return status;
1514 }
1515
1516 static void
1517 intel_hdmi_force(struct drm_connector *connector)
1518 {
1519         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1520
1521         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1522                       connector->base.id, connector->name);
1523
1524         intel_hdmi_unset_edid(connector);
1525
1526         if (connector->status != connector_status_connected)
1527                 return;
1528
1529         intel_hdmi_set_edid(connector);
1530         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1531 }
1532
1533 static int intel_hdmi_get_modes(struct drm_connector *connector)
1534 {
1535         struct edid *edid;
1536
1537         edid = to_intel_connector(connector)->detect_edid;
1538         if (edid == NULL)
1539                 return 0;
1540
1541         return intel_connector_update_modes(connector, edid);
1542 }
1543
1544 static bool
1545 intel_hdmi_detect_audio(struct drm_connector *connector)
1546 {
1547         bool has_audio = false;
1548         struct edid *edid;
1549
1550         edid = to_intel_connector(connector)->detect_edid;
1551         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1552                 has_audio = drm_detect_monitor_audio(edid);
1553
1554         return has_audio;
1555 }
1556
1557 static int
1558 intel_hdmi_set_property(struct drm_connector *connector,
1559                         struct drm_property *property,
1560                         uint64_t val)
1561 {
1562         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1563         struct intel_digital_port *intel_dig_port =
1564                 hdmi_to_dig_port(intel_hdmi);
1565         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1566         int ret;
1567
1568         ret = drm_object_property_set_value(&connector->base, property, val);
1569         if (ret)
1570                 return ret;
1571
1572         if (property == dev_priv->force_audio_property) {
1573                 enum hdmi_force_audio i = val;
1574                 bool has_audio;
1575
1576                 if (i == intel_hdmi->force_audio)
1577                         return 0;
1578
1579                 intel_hdmi->force_audio = i;
1580
1581                 if (i == HDMI_AUDIO_AUTO)
1582                         has_audio = intel_hdmi_detect_audio(connector);
1583                 else
1584                         has_audio = (i == HDMI_AUDIO_ON);
1585
1586                 if (i == HDMI_AUDIO_OFF_DVI)
1587                         intel_hdmi->has_hdmi_sink = 0;
1588
1589                 intel_hdmi->has_audio = has_audio;
1590                 goto done;
1591         }
1592
1593         if (property == dev_priv->broadcast_rgb_property) {
1594                 bool old_auto = intel_hdmi->color_range_auto;
1595                 bool old_range = intel_hdmi->limited_color_range;
1596
1597                 switch (val) {
1598                 case INTEL_BROADCAST_RGB_AUTO:
1599                         intel_hdmi->color_range_auto = true;
1600                         break;
1601                 case INTEL_BROADCAST_RGB_FULL:
1602                         intel_hdmi->color_range_auto = false;
1603                         intel_hdmi->limited_color_range = false;
1604                         break;
1605                 case INTEL_BROADCAST_RGB_LIMITED:
1606                         intel_hdmi->color_range_auto = false;
1607                         intel_hdmi->limited_color_range = true;
1608                         break;
1609                 default:
1610                         return -EINVAL;
1611                 }
1612
1613                 if (old_auto == intel_hdmi->color_range_auto &&
1614                     old_range == intel_hdmi->limited_color_range)
1615                         return 0;
1616
1617                 goto done;
1618         }
1619
1620         if (property == connector->dev->mode_config.aspect_ratio_property) {
1621                 switch (val) {
1622                 case DRM_MODE_PICTURE_ASPECT_NONE:
1623                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1624                         break;
1625                 case DRM_MODE_PICTURE_ASPECT_4_3:
1626                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1627                         break;
1628                 case DRM_MODE_PICTURE_ASPECT_16_9:
1629                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1630                         break;
1631                 default:
1632                         return -EINVAL;
1633                 }
1634                 goto done;
1635         }
1636
1637         return -EINVAL;
1638
1639 done:
1640         if (intel_dig_port->base.base.crtc)
1641                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1642
1643         return 0;
1644 }
1645
1646 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1647                                   struct intel_crtc_state *pipe_config,
1648                                   struct drm_connector_state *conn_state)
1649 {
1650         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1651
1652         intel_hdmi_prepare(encoder, pipe_config);
1653
1654         intel_hdmi->set_infoframes(&encoder->base,
1655                                    pipe_config->has_hdmi_sink,
1656                                    pipe_config, conn_state);
1657 }
1658
1659 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1660                                 struct intel_crtc_state *pipe_config,
1661                                 struct drm_connector_state *conn_state)
1662 {
1663         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1664         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1665         struct drm_device *dev = encoder->base.dev;
1666         struct drm_i915_private *dev_priv = to_i915(dev);
1667
1668         vlv_phy_pre_encoder_enable(encoder);
1669
1670         /* HDMI 1.0V-2dB */
1671         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1672                                  0x2b247878);
1673
1674         intel_hdmi->set_infoframes(&encoder->base,
1675                                    pipe_config->has_hdmi_sink,
1676                                    pipe_config, conn_state);
1677
1678         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1679
1680         vlv_wait_port_ready(dev_priv, dport, 0x0);
1681 }
1682
1683 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1684                                     struct intel_crtc_state *pipe_config,
1685                                     struct drm_connector_state *conn_state)
1686 {
1687         intel_hdmi_prepare(encoder, pipe_config);
1688
1689         vlv_phy_pre_pll_enable(encoder);
1690 }
1691
1692 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1693                                     struct intel_crtc_state *pipe_config,
1694                                     struct drm_connector_state *conn_state)
1695 {
1696         intel_hdmi_prepare(encoder, pipe_config);
1697
1698         chv_phy_pre_pll_enable(encoder);
1699 }
1700
1701 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1702                                       struct intel_crtc_state *old_crtc_state,
1703                                       struct drm_connector_state *old_conn_state)
1704 {
1705         chv_phy_post_pll_disable(encoder);
1706 }
1707
1708 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1709                                   struct intel_crtc_state *old_crtc_state,
1710                                   struct drm_connector_state *old_conn_state)
1711 {
1712         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1713         vlv_phy_reset_lanes(encoder);
1714 }
1715
1716 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1717                                   struct intel_crtc_state *old_crtc_state,
1718                                   struct drm_connector_state *old_conn_state)
1719 {
1720         struct drm_device *dev = encoder->base.dev;
1721         struct drm_i915_private *dev_priv = to_i915(dev);
1722
1723         mutex_lock(&dev_priv->sb_lock);
1724
1725         /* Assert data lane reset */
1726         chv_data_lane_soft_reset(encoder, true);
1727
1728         mutex_unlock(&dev_priv->sb_lock);
1729 }
1730
1731 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1732                                 struct intel_crtc_state *pipe_config,
1733                                 struct drm_connector_state *conn_state)
1734 {
1735         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1736         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1737         struct drm_device *dev = encoder->base.dev;
1738         struct drm_i915_private *dev_priv = to_i915(dev);
1739
1740         chv_phy_pre_encoder_enable(encoder);
1741
1742         /* FIXME: Program the support xxx V-dB */
1743         /* Use 800mV-0dB */
1744         chv_set_phy_signal_level(encoder, 128, 102, false);
1745
1746         intel_hdmi->set_infoframes(&encoder->base,
1747                                    pipe_config->has_hdmi_sink,
1748                                    pipe_config, conn_state);
1749
1750         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1751
1752         vlv_wait_port_ready(dev_priv, dport, 0x0);
1753
1754         /* Second common lane will stay alive on its own now */
1755         chv_phy_release_cl2_override(encoder);
1756 }
1757
1758 static void intel_hdmi_destroy(struct drm_connector *connector)
1759 {
1760         kfree(to_intel_connector(connector)->detect_edid);
1761         drm_connector_cleanup(connector);
1762         kfree(connector);
1763 }
1764
1765 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1766         .dpms = drm_atomic_helper_connector_dpms,
1767         .detect = intel_hdmi_detect,
1768         .force = intel_hdmi_force,
1769         .fill_modes = drm_helper_probe_single_connector_modes,
1770         .set_property = intel_hdmi_set_property,
1771         .atomic_get_property = intel_connector_atomic_get_property,
1772         .late_register = intel_connector_register,
1773         .early_unregister = intel_connector_unregister,
1774         .destroy = intel_hdmi_destroy,
1775         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1776         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1777 };
1778
1779 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1780         .get_modes = intel_hdmi_get_modes,
1781         .mode_valid = intel_hdmi_mode_valid,
1782 };
1783
1784 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1785         .destroy = intel_encoder_destroy,
1786 };
1787
1788 static void
1789 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1790 {
1791         intel_attach_force_audio_property(connector);
1792         intel_attach_broadcast_rgb_property(connector);
1793         intel_hdmi->color_range_auto = true;
1794         intel_attach_aspect_ratio_property(connector);
1795         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1796 }
1797
1798 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1799                              enum port port)
1800 {
1801         const struct ddi_vbt_port_info *info =
1802                 &dev_priv->vbt.ddi_port_info[port];
1803         u8 ddc_pin;
1804
1805         if (info->alternate_ddc_pin) {
1806                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1807                               info->alternate_ddc_pin, port_name(port));
1808                 return info->alternate_ddc_pin;
1809         }
1810
1811         switch (port) {
1812         case PORT_B:
1813                 if (IS_GEN9_LP(dev_priv))
1814                         ddc_pin = GMBUS_PIN_1_BXT;
1815                 else
1816                         ddc_pin = GMBUS_PIN_DPB;
1817                 break;
1818         case PORT_C:
1819                 if (IS_GEN9_LP(dev_priv))
1820                         ddc_pin = GMBUS_PIN_2_BXT;
1821                 else
1822                         ddc_pin = GMBUS_PIN_DPC;
1823                 break;
1824         case PORT_D:
1825                 if (IS_CHERRYVIEW(dev_priv))
1826                         ddc_pin = GMBUS_PIN_DPD_CHV;
1827                 else
1828                         ddc_pin = GMBUS_PIN_DPD;
1829                 break;
1830         default:
1831                 MISSING_CASE(port);
1832                 ddc_pin = GMBUS_PIN_DPB;
1833                 break;
1834         }
1835
1836         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1837                       ddc_pin, port_name(port));
1838
1839         return ddc_pin;
1840 }
1841
1842 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1843                                struct intel_connector *intel_connector)
1844 {
1845         struct drm_connector *connector = &intel_connector->base;
1846         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1847         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1848         struct drm_device *dev = intel_encoder->base.dev;
1849         struct drm_i915_private *dev_priv = to_i915(dev);
1850         enum port port = intel_dig_port->port;
1851
1852         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
1853                       port_name(port));
1854
1855         if (WARN(intel_dig_port->max_lanes < 4,
1856                  "Not enough lanes (%d) for HDMI on port %c\n",
1857                  intel_dig_port->max_lanes, port_name(port)))
1858                 return;
1859
1860         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1861                            DRM_MODE_CONNECTOR_HDMIA);
1862         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1863
1864         connector->interlace_allowed = 1;
1865         connector->doublescan_allowed = 0;
1866         connector->stereo_allowed = 1;
1867
1868         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
1869
1870         switch (port) {
1871         case PORT_B:
1872                 /*
1873                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
1874                  * interrupts to check the external panel connection.
1875                  */
1876                 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1877                         intel_encoder->hpd_pin = HPD_PORT_A;
1878                 else
1879                         intel_encoder->hpd_pin = HPD_PORT_B;
1880                 break;
1881         case PORT_C:
1882                 intel_encoder->hpd_pin = HPD_PORT_C;
1883                 break;
1884         case PORT_D:
1885                 intel_encoder->hpd_pin = HPD_PORT_D;
1886                 break;
1887         case PORT_E:
1888                 intel_encoder->hpd_pin = HPD_PORT_E;
1889                 break;
1890         default:
1891                 MISSING_CASE(port);
1892                 return;
1893         }
1894
1895         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1896                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1897                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1898                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1899         } else if (IS_G4X(dev_priv)) {
1900                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1901                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1902                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1903         } else if (HAS_DDI(dev_priv)) {
1904                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1905                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1906                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1907         } else if (HAS_PCH_IBX(dev_priv)) {
1908                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1909                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1910                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1911         } else {
1912                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1913                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1914                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1915         }
1916
1917         if (HAS_DDI(dev_priv))
1918                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1919         else
1920                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1921
1922         intel_hdmi_add_properties(intel_hdmi, connector);
1923
1924         intel_connector_attach_encoder(intel_connector, intel_encoder);
1925         intel_hdmi->attached_connector = intel_connector;
1926
1927         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1928          * 0xd.  Failure to do so will result in spurious interrupts being
1929          * generated on the port when a cable is not attached.
1930          */
1931         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
1932                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1933                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1934         }
1935 }
1936
1937 void intel_hdmi_init(struct drm_i915_private *dev_priv,
1938                      i915_reg_t hdmi_reg, enum port port)
1939 {
1940         struct intel_digital_port *intel_dig_port;
1941         struct intel_encoder *intel_encoder;
1942         struct intel_connector *intel_connector;
1943
1944         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1945         if (!intel_dig_port)
1946                 return;
1947
1948         intel_connector = intel_connector_alloc();
1949         if (!intel_connector) {
1950                 kfree(intel_dig_port);
1951                 return;
1952         }
1953
1954         intel_encoder = &intel_dig_port->base;
1955
1956         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
1957                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
1958                          "HDMI %c", port_name(port));
1959
1960         intel_encoder->compute_config = intel_hdmi_compute_config;
1961         if (HAS_PCH_SPLIT(dev_priv)) {
1962                 intel_encoder->disable = pch_disable_hdmi;
1963                 intel_encoder->post_disable = pch_post_disable_hdmi;
1964         } else {
1965                 intel_encoder->disable = g4x_disable_hdmi;
1966         }
1967         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1968         intel_encoder->get_config = intel_hdmi_get_config;
1969         if (IS_CHERRYVIEW(dev_priv)) {
1970                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1971                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1972                 intel_encoder->enable = vlv_enable_hdmi;
1973                 intel_encoder->post_disable = chv_hdmi_post_disable;
1974                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
1975         } else if (IS_VALLEYVIEW(dev_priv)) {
1976                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1977                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1978                 intel_encoder->enable = vlv_enable_hdmi;
1979                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1980         } else {
1981                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1982                 if (HAS_PCH_CPT(dev_priv))
1983                         intel_encoder->enable = cpt_enable_hdmi;
1984                 else if (HAS_PCH_IBX(dev_priv))
1985                         intel_encoder->enable = ibx_enable_hdmi;
1986                 else
1987                         intel_encoder->enable = g4x_enable_hdmi;
1988         }
1989
1990         intel_encoder->type = INTEL_OUTPUT_HDMI;
1991         intel_encoder->port = port;
1992         if (IS_CHERRYVIEW(dev_priv)) {
1993                 if (port == PORT_D)
1994                         intel_encoder->crtc_mask = 1 << 2;
1995                 else
1996                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1997         } else {
1998                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1999         }
2000         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2001         /*
2002          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2003          * to work on real hardware. And since g4x can send infoframes to
2004          * only one port anyway, nothing is lost by allowing it.
2005          */
2006         if (IS_G4X(dev_priv))
2007                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2008
2009         intel_dig_port->port = port;
2010         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2011         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2012         intel_dig_port->max_lanes = 4;
2013
2014         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2015 }