Merge tag 'drm-misc-next-2019-03-21' of git://anongit.freedesktop.org/drm/drm-misc...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_hdmi.c
1 /*
2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2009 Intel Corporation
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *      Eric Anholt <eric@anholt.net>
26  *      Jesse Barnes <jesse.barnes@intel.com>
27  */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_hdcp.h>
37 #include <drm/drm_scdc_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
41 #include "i915_drv.h"
42
43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
44 {
45         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
46 }
47
48 static void
49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
50 {
51         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
52         struct drm_i915_private *dev_priv = to_i915(dev);
53         u32 enabled_bits;
54
55         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
56
57         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
58              "HDMI port enabled, expecting disabled\n");
59 }
60
61 static void
62 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
63                                      enum transcoder cpu_transcoder)
64 {
65         WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
66              TRANS_DDI_FUNC_ENABLE,
67              "HDMI transcoder function enabled, expecting disabled\n");
68 }
69
70 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
71 {
72         struct intel_digital_port *intel_dig_port =
73                 container_of(encoder, struct intel_digital_port, base.base);
74         return &intel_dig_port->hdmi;
75 }
76
77 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
78 {
79         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
80 }
81
82 static u32 g4x_infoframe_index(unsigned int type)
83 {
84         switch (type) {
85         case HDMI_INFOFRAME_TYPE_AVI:
86                 return VIDEO_DIP_SELECT_AVI;
87         case HDMI_INFOFRAME_TYPE_SPD:
88                 return VIDEO_DIP_SELECT_SPD;
89         case HDMI_INFOFRAME_TYPE_VENDOR:
90                 return VIDEO_DIP_SELECT_VENDOR;
91         default:
92                 MISSING_CASE(type);
93                 return 0;
94         }
95 }
96
97 static u32 g4x_infoframe_enable(unsigned int type)
98 {
99         switch (type) {
100         case HDMI_INFOFRAME_TYPE_AVI:
101                 return VIDEO_DIP_ENABLE_AVI;
102         case HDMI_INFOFRAME_TYPE_SPD:
103                 return VIDEO_DIP_ENABLE_SPD;
104         case HDMI_INFOFRAME_TYPE_VENDOR:
105                 return VIDEO_DIP_ENABLE_VENDOR;
106         default:
107                 MISSING_CASE(type);
108                 return 0;
109         }
110 }
111
112 static u32 hsw_infoframe_enable(unsigned int type)
113 {
114         switch (type) {
115         case DP_SDP_VSC:
116                 return VIDEO_DIP_ENABLE_VSC_HSW;
117         case DP_SDP_PPS:
118                 return VDIP_ENABLE_PPS;
119         case HDMI_INFOFRAME_TYPE_AVI:
120                 return VIDEO_DIP_ENABLE_AVI_HSW;
121         case HDMI_INFOFRAME_TYPE_SPD:
122                 return VIDEO_DIP_ENABLE_SPD_HSW;
123         case HDMI_INFOFRAME_TYPE_VENDOR:
124                 return VIDEO_DIP_ENABLE_VS_HSW;
125         default:
126                 MISSING_CASE(type);
127                 return 0;
128         }
129 }
130
131 static i915_reg_t
132 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
133                  enum transcoder cpu_transcoder,
134                  unsigned int type,
135                  int i)
136 {
137         switch (type) {
138         case DP_SDP_VSC:
139                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
140         case DP_SDP_PPS:
141                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
142         case HDMI_INFOFRAME_TYPE_AVI:
143                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
144         case HDMI_INFOFRAME_TYPE_SPD:
145                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
146         case HDMI_INFOFRAME_TYPE_VENDOR:
147                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
148         default:
149                 MISSING_CASE(type);
150                 return INVALID_MMIO_REG;
151         }
152 }
153
154 static int hsw_dip_data_size(unsigned int type)
155 {
156         switch (type) {
157         case DP_SDP_VSC:
158                 return VIDEO_DIP_VSC_DATA_SIZE;
159         case DP_SDP_PPS:
160                 return VIDEO_DIP_PPS_DATA_SIZE;
161         default:
162                 return VIDEO_DIP_DATA_SIZE;
163         }
164 }
165
166 static void g4x_write_infoframe(struct intel_encoder *encoder,
167                                 const struct intel_crtc_state *crtc_state,
168                                 unsigned int type,
169                                 const void *frame, ssize_t len)
170 {
171         const u32 *data = frame;
172         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
173         u32 val = I915_READ(VIDEO_DIP_CTL);
174         int i;
175
176         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
177
178         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
179         val |= g4x_infoframe_index(type);
180
181         val &= ~g4x_infoframe_enable(type);
182
183         I915_WRITE(VIDEO_DIP_CTL, val);
184
185         mmiowb();
186         for (i = 0; i < len; i += 4) {
187                 I915_WRITE(VIDEO_DIP_DATA, *data);
188                 data++;
189         }
190         /* Write every possible data byte to force correct ECC calculation. */
191         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
192                 I915_WRITE(VIDEO_DIP_DATA, 0);
193         mmiowb();
194
195         val |= g4x_infoframe_enable(type);
196         val &= ~VIDEO_DIP_FREQ_MASK;
197         val |= VIDEO_DIP_FREQ_VSYNC;
198
199         I915_WRITE(VIDEO_DIP_CTL, val);
200         POSTING_READ(VIDEO_DIP_CTL);
201 }
202
203 static bool g4x_infoframe_enabled(struct intel_encoder *encoder,
204                                   const struct intel_crtc_state *pipe_config)
205 {
206         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
207         u32 val = I915_READ(VIDEO_DIP_CTL);
208
209         if ((val & VIDEO_DIP_ENABLE) == 0)
210                 return false;
211
212         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
213                 return false;
214
215         return val & (VIDEO_DIP_ENABLE_AVI |
216                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
217 }
218
219 static void ibx_write_infoframe(struct intel_encoder *encoder,
220                                 const struct intel_crtc_state *crtc_state,
221                                 unsigned int type,
222                                 const void *frame, ssize_t len)
223 {
224         const u32 *data = frame;
225         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
226         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
227         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
228         u32 val = I915_READ(reg);
229         int i;
230
231         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
232
233         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
234         val |= g4x_infoframe_index(type);
235
236         val &= ~g4x_infoframe_enable(type);
237
238         I915_WRITE(reg, val);
239
240         mmiowb();
241         for (i = 0; i < len; i += 4) {
242                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
243                 data++;
244         }
245         /* Write every possible data byte to force correct ECC calculation. */
246         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
247                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
248         mmiowb();
249
250         val |= g4x_infoframe_enable(type);
251         val &= ~VIDEO_DIP_FREQ_MASK;
252         val |= VIDEO_DIP_FREQ_VSYNC;
253
254         I915_WRITE(reg, val);
255         POSTING_READ(reg);
256 }
257
258 static bool ibx_infoframe_enabled(struct intel_encoder *encoder,
259                                   const struct intel_crtc_state *pipe_config)
260 {
261         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
262         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
263         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
264         u32 val = I915_READ(reg);
265
266         if ((val & VIDEO_DIP_ENABLE) == 0)
267                 return false;
268
269         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
270                 return false;
271
272         return val & (VIDEO_DIP_ENABLE_AVI |
273                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
274                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
275 }
276
277 static void cpt_write_infoframe(struct intel_encoder *encoder,
278                                 const struct intel_crtc_state *crtc_state,
279                                 unsigned int type,
280                                 const void *frame, ssize_t len)
281 {
282         const u32 *data = frame;
283         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
285         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
286         u32 val = I915_READ(reg);
287         int i;
288
289         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
290
291         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
292         val |= g4x_infoframe_index(type);
293
294         /* The DIP control register spec says that we need to update the AVI
295          * infoframe without clearing its enable bit */
296         if (type != HDMI_INFOFRAME_TYPE_AVI)
297                 val &= ~g4x_infoframe_enable(type);
298
299         I915_WRITE(reg, val);
300
301         mmiowb();
302         for (i = 0; i < len; i += 4) {
303                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
304                 data++;
305         }
306         /* Write every possible data byte to force correct ECC calculation. */
307         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
308                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
309         mmiowb();
310
311         val |= g4x_infoframe_enable(type);
312         val &= ~VIDEO_DIP_FREQ_MASK;
313         val |= VIDEO_DIP_FREQ_VSYNC;
314
315         I915_WRITE(reg, val);
316         POSTING_READ(reg);
317 }
318
319 static bool cpt_infoframe_enabled(struct intel_encoder *encoder,
320                                   const struct intel_crtc_state *pipe_config)
321 {
322         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
323         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
324         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
325
326         if ((val & VIDEO_DIP_ENABLE) == 0)
327                 return false;
328
329         return val & (VIDEO_DIP_ENABLE_AVI |
330                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
331                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
332 }
333
334 static void vlv_write_infoframe(struct intel_encoder *encoder,
335                                 const struct intel_crtc_state *crtc_state,
336                                 unsigned int type,
337                                 const void *frame, ssize_t len)
338 {
339         const u32 *data = frame;
340         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
342         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
343         u32 val = I915_READ(reg);
344         int i;
345
346         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
347
348         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
349         val |= g4x_infoframe_index(type);
350
351         val &= ~g4x_infoframe_enable(type);
352
353         I915_WRITE(reg, val);
354
355         mmiowb();
356         for (i = 0; i < len; i += 4) {
357                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
358                 data++;
359         }
360         /* Write every possible data byte to force correct ECC calculation. */
361         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
362                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
363         mmiowb();
364
365         val |= g4x_infoframe_enable(type);
366         val &= ~VIDEO_DIP_FREQ_MASK;
367         val |= VIDEO_DIP_FREQ_VSYNC;
368
369         I915_WRITE(reg, val);
370         POSTING_READ(reg);
371 }
372
373 static bool vlv_infoframe_enabled(struct intel_encoder *encoder,
374                                   const struct intel_crtc_state *pipe_config)
375 {
376         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
377         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
378         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
379
380         if ((val & VIDEO_DIP_ENABLE) == 0)
381                 return false;
382
383         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
384                 return false;
385
386         return val & (VIDEO_DIP_ENABLE_AVI |
387                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
388                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
389 }
390
391 static void hsw_write_infoframe(struct intel_encoder *encoder,
392                                 const struct intel_crtc_state *crtc_state,
393                                 unsigned int type,
394                                 const void *frame, ssize_t len)
395 {
396         const u32 *data = frame;
397         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
398         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
399         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
400         int data_size;
401         int i;
402         u32 val = I915_READ(ctl_reg);
403
404         data_size = hsw_dip_data_size(type);
405
406         val &= ~hsw_infoframe_enable(type);
407         I915_WRITE(ctl_reg, val);
408
409         mmiowb();
410         for (i = 0; i < len; i += 4) {
411                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
412                                             type, i >> 2), *data);
413                 data++;
414         }
415         /* Write every possible data byte to force correct ECC calculation. */
416         for (; i < data_size; i += 4)
417                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
418                                             type, i >> 2), 0);
419         mmiowb();
420
421         val |= hsw_infoframe_enable(type);
422         I915_WRITE(ctl_reg, val);
423         POSTING_READ(ctl_reg);
424 }
425
426 static bool hsw_infoframe_enabled(struct intel_encoder *encoder,
427                                   const struct intel_crtc_state *pipe_config)
428 {
429         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
430         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
431
432         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
433                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
434                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
435 }
436
437 /*
438  * The data we write to the DIP data buffer registers is 1 byte bigger than the
439  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
440  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
441  * used for both technologies.
442  *
443  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
444  * DW1:       DB3       | DB2 | DB1 | DB0
445  * DW2:       DB7       | DB6 | DB5 | DB4
446  * DW3: ...
447  *
448  * (HB is Header Byte, DB is Data Byte)
449  *
450  * The hdmi pack() functions don't know about that hardware specific hole so we
451  * trick them by giving an offset into the buffer and moving back the header
452  * bytes by one.
453  */
454 static void intel_write_infoframe(struct intel_encoder *encoder,
455                                   const struct intel_crtc_state *crtc_state,
456                                   union hdmi_infoframe *frame)
457 {
458         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
459         u8 buffer[VIDEO_DIP_DATA_SIZE];
460         ssize_t len;
461
462         /* see comment above for the reason for this offset */
463         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
464         if (len < 0)
465                 return;
466
467         /* Insert the 'hole' (see big comment above) at position 3 */
468         memmove(&buffer[0], &buffer[1], 3);
469         buffer[3] = 0;
470         len++;
471
472         intel_dig_port->write_infoframe(encoder,
473                                         crtc_state,
474                                         frame->any.type, buffer, len);
475 }
476
477 static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder,
478                                          const struct intel_crtc_state *crtc_state,
479                                          const struct drm_connector_state *conn_state)
480 {
481         const struct drm_display_mode *adjusted_mode =
482                 &crtc_state->base.adjusted_mode;
483         union hdmi_infoframe frame;
484         int ret;
485
486         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
487                                                        conn_state->connector,
488                                                        adjusted_mode);
489         if (ret < 0) {
490                 DRM_ERROR("couldn't fill AVI infoframe\n");
491                 return;
492         }
493
494         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
495                 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
496         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
497                 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
498         else
499                 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
500
501         drm_hdmi_avi_infoframe_colorspace(&frame.avi, conn_state);
502
503         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
504                                            conn_state->connector,
505                                            adjusted_mode,
506                                            crtc_state->limited_color_range ?
507                                            HDMI_QUANTIZATION_RANGE_LIMITED :
508                                            HDMI_QUANTIZATION_RANGE_FULL);
509
510         drm_hdmi_avi_infoframe_content_type(&frame.avi,
511                                             conn_state);
512
513         /* TODO: handle pixel repetition for YCBCR420 outputs */
514         intel_write_infoframe(encoder, crtc_state,
515                               &frame);
516 }
517
518 static void intel_hdmi_set_spd_infoframe(struct intel_encoder *encoder,
519                                          const struct intel_crtc_state *crtc_state)
520 {
521         union hdmi_infoframe frame;
522         int ret;
523
524         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
525         if (ret < 0) {
526                 DRM_ERROR("couldn't fill SPD infoframe\n");
527                 return;
528         }
529
530         frame.spd.sdi = HDMI_SPD_SDI_PC;
531
532         intel_write_infoframe(encoder, crtc_state,
533                               &frame);
534 }
535
536 static void
537 intel_hdmi_set_hdmi_infoframe(struct intel_encoder *encoder,
538                               const struct intel_crtc_state *crtc_state,
539                               const struct drm_connector_state *conn_state)
540 {
541         union hdmi_infoframe frame;
542         int ret;
543
544         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
545                                                           conn_state->connector,
546                                                           &crtc_state->base.adjusted_mode);
547         if (ret < 0)
548                 return;
549
550         intel_write_infoframe(encoder, crtc_state,
551                               &frame);
552 }
553
554 static void g4x_set_infoframes(struct intel_encoder *encoder,
555                                bool enable,
556                                const struct intel_crtc_state *crtc_state,
557                                const struct drm_connector_state *conn_state)
558 {
559         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
560         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
561         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
562         i915_reg_t reg = VIDEO_DIP_CTL;
563         u32 val = I915_READ(reg);
564         u32 port = VIDEO_DIP_PORT(encoder->port);
565
566         assert_hdmi_port_disabled(intel_hdmi);
567
568         /* If the registers were not initialized yet, they might be zeroes,
569          * which means we're selecting the AVI DIP and we're setting its
570          * frequency to once. This seems to really confuse the HW and make
571          * things stop working (the register spec says the AVI always needs to
572          * be sent every VSync). So here we avoid writing to the register more
573          * than we need and also explicitly select the AVI DIP and explicitly
574          * set its frequency to every VSync. Avoiding to write it twice seems to
575          * be enough to solve the problem, but being defensive shouldn't hurt us
576          * either. */
577         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
578
579         if (!enable) {
580                 if (!(val & VIDEO_DIP_ENABLE))
581                         return;
582                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
583                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
584                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
585                         return;
586                 }
587                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
588                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
589                 I915_WRITE(reg, val);
590                 POSTING_READ(reg);
591                 return;
592         }
593
594         if (port != (val & VIDEO_DIP_PORT_MASK)) {
595                 if (val & VIDEO_DIP_ENABLE) {
596                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
597                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
598                         return;
599                 }
600                 val &= ~VIDEO_DIP_PORT_MASK;
601                 val |= port;
602         }
603
604         val |= VIDEO_DIP_ENABLE;
605         val &= ~(VIDEO_DIP_ENABLE_AVI |
606                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
607
608         I915_WRITE(reg, val);
609         POSTING_READ(reg);
610
611         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
612         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
613         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
614 }
615
616 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
617 {
618         struct drm_connector *connector = conn_state->connector;
619
620         /*
621          * HDMI cloning is only supported on g4x which doesn't
622          * support deep color or GCP infoframes anyway so no
623          * need to worry about multiple HDMI sinks here.
624          */
625
626         return connector->display_info.bpc > 8;
627 }
628
629 /*
630  * Determine if default_phase=1 can be indicated in the GCP infoframe.
631  *
632  * From HDMI specification 1.4a:
633  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
634  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
635  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
636  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
637  *   phase of 0
638  */
639 static bool gcp_default_phase_possible(int pipe_bpp,
640                                        const struct drm_display_mode *mode)
641 {
642         unsigned int pixels_per_group;
643
644         switch (pipe_bpp) {
645         case 30:
646                 /* 4 pixels in 5 clocks */
647                 pixels_per_group = 4;
648                 break;
649         case 36:
650                 /* 2 pixels in 3 clocks */
651                 pixels_per_group = 2;
652                 break;
653         case 48:
654                 /* 1 pixel in 2 clocks */
655                 pixels_per_group = 1;
656                 break;
657         default:
658                 /* phase information not relevant for 8bpc */
659                 return false;
660         }
661
662         return mode->crtc_hdisplay % pixels_per_group == 0 &&
663                 mode->crtc_htotal % pixels_per_group == 0 &&
664                 mode->crtc_hblank_start % pixels_per_group == 0 &&
665                 mode->crtc_hblank_end % pixels_per_group == 0 &&
666                 mode->crtc_hsync_start % pixels_per_group == 0 &&
667                 mode->crtc_hsync_end % pixels_per_group == 0 &&
668                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
669                  mode->crtc_htotal/2 % pixels_per_group == 0);
670 }
671
672 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
673                                          const struct intel_crtc_state *crtc_state,
674                                          const struct drm_connector_state *conn_state)
675 {
676         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
677         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
678         i915_reg_t reg;
679         u32 val = 0;
680
681         if (HAS_DDI(dev_priv))
682                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
683         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
684                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
685         else if (HAS_PCH_SPLIT(dev_priv))
686                 reg = TVIDEO_DIP_GCP(crtc->pipe);
687         else
688                 return false;
689
690         /* Indicate color depth whenever the sink supports deep color */
691         if (hdmi_sink_is_deep_color(conn_state))
692                 val |= GCP_COLOR_INDICATION;
693
694         /* Enable default_phase whenever the display mode is suitably aligned */
695         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
696                                        &crtc_state->base.adjusted_mode))
697                 val |= GCP_DEFAULT_PHASE_ENABLE;
698
699         I915_WRITE(reg, val);
700
701         return val != 0;
702 }
703
704 static void ibx_set_infoframes(struct intel_encoder *encoder,
705                                bool enable,
706                                const struct intel_crtc_state *crtc_state,
707                                const struct drm_connector_state *conn_state)
708 {
709         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
711         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
712         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
713         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
714         u32 val = I915_READ(reg);
715         u32 port = VIDEO_DIP_PORT(encoder->port);
716
717         assert_hdmi_port_disabled(intel_hdmi);
718
719         /* See the big comment in g4x_set_infoframes() */
720         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
721
722         if (!enable) {
723                 if (!(val & VIDEO_DIP_ENABLE))
724                         return;
725                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
726                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
727                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
728                 I915_WRITE(reg, val);
729                 POSTING_READ(reg);
730                 return;
731         }
732
733         if (port != (val & VIDEO_DIP_PORT_MASK)) {
734                 WARN(val & VIDEO_DIP_ENABLE,
735                      "DIP already enabled on port %c\n",
736                      (val & VIDEO_DIP_PORT_MASK) >> 29);
737                 val &= ~VIDEO_DIP_PORT_MASK;
738                 val |= port;
739         }
740
741         val |= VIDEO_DIP_ENABLE;
742         val &= ~(VIDEO_DIP_ENABLE_AVI |
743                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
744                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
745
746         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
747                 val |= VIDEO_DIP_ENABLE_GCP;
748
749         I915_WRITE(reg, val);
750         POSTING_READ(reg);
751
752         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
753         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
754         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
755 }
756
757 static void cpt_set_infoframes(struct intel_encoder *encoder,
758                                bool enable,
759                                const struct intel_crtc_state *crtc_state,
760                                const struct drm_connector_state *conn_state)
761 {
762         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
764         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
765         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
766         u32 val = I915_READ(reg);
767
768         assert_hdmi_port_disabled(intel_hdmi);
769
770         /* See the big comment in g4x_set_infoframes() */
771         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
772
773         if (!enable) {
774                 if (!(val & VIDEO_DIP_ENABLE))
775                         return;
776                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
777                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
778                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
779                 I915_WRITE(reg, val);
780                 POSTING_READ(reg);
781                 return;
782         }
783
784         /* Set both together, unset both together: see the spec. */
785         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
786         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
787                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
788
789         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
790                 val |= VIDEO_DIP_ENABLE_GCP;
791
792         I915_WRITE(reg, val);
793         POSTING_READ(reg);
794
795         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
796         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
797         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
798 }
799
800 static void vlv_set_infoframes(struct intel_encoder *encoder,
801                                bool enable,
802                                const struct intel_crtc_state *crtc_state,
803                                const struct drm_connector_state *conn_state)
804 {
805         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
807         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
808         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
809         u32 val = I915_READ(reg);
810         u32 port = VIDEO_DIP_PORT(encoder->port);
811
812         assert_hdmi_port_disabled(intel_hdmi);
813
814         /* See the big comment in g4x_set_infoframes() */
815         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
816
817         if (!enable) {
818                 if (!(val & VIDEO_DIP_ENABLE))
819                         return;
820                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
821                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
822                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
823                 I915_WRITE(reg, val);
824                 POSTING_READ(reg);
825                 return;
826         }
827
828         if (port != (val & VIDEO_DIP_PORT_MASK)) {
829                 WARN(val & VIDEO_DIP_ENABLE,
830                      "DIP already enabled on port %c\n",
831                      (val & VIDEO_DIP_PORT_MASK) >> 29);
832                 val &= ~VIDEO_DIP_PORT_MASK;
833                 val |= port;
834         }
835
836         val |= VIDEO_DIP_ENABLE;
837         val &= ~(VIDEO_DIP_ENABLE_AVI |
838                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
839                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
840
841         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
842                 val |= VIDEO_DIP_ENABLE_GCP;
843
844         I915_WRITE(reg, val);
845         POSTING_READ(reg);
846
847         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
848         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
849         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
850 }
851
852 static void hsw_set_infoframes(struct intel_encoder *encoder,
853                                bool enable,
854                                const struct intel_crtc_state *crtc_state,
855                                const struct drm_connector_state *conn_state)
856 {
857         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
858         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
859         u32 val = I915_READ(reg);
860
861         assert_hdmi_transcoder_func_disabled(dev_priv,
862                                              crtc_state->cpu_transcoder);
863
864         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
865                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
866                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
867
868         if (!enable) {
869                 I915_WRITE(reg, val);
870                 POSTING_READ(reg);
871                 return;
872         }
873
874         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
875                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
876
877         I915_WRITE(reg, val);
878         POSTING_READ(reg);
879
880         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
881         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
882         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
883 }
884
885 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
886 {
887         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
888         struct i2c_adapter *adapter =
889                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
890
891         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
892                 return;
893
894         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
895                       enable ? "Enabling" : "Disabling");
896
897         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
898                                          adapter, enable);
899 }
900
901 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
902                                 unsigned int offset, void *buffer, size_t size)
903 {
904         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
905         struct drm_i915_private *dev_priv =
906                 intel_dig_port->base.base.dev->dev_private;
907         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
908                                                               hdmi->ddc_bus);
909         int ret;
910         u8 start = offset & 0xff;
911         struct i2c_msg msgs[] = {
912                 {
913                         .addr = DRM_HDCP_DDC_ADDR,
914                         .flags = 0,
915                         .len = 1,
916                         .buf = &start,
917                 },
918                 {
919                         .addr = DRM_HDCP_DDC_ADDR,
920                         .flags = I2C_M_RD,
921                         .len = size,
922                         .buf = buffer
923                 }
924         };
925         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
926         if (ret == ARRAY_SIZE(msgs))
927                 return 0;
928         return ret >= 0 ? -EIO : ret;
929 }
930
931 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
932                                  unsigned int offset, void *buffer, size_t size)
933 {
934         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
935         struct drm_i915_private *dev_priv =
936                 intel_dig_port->base.base.dev->dev_private;
937         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
938                                                               hdmi->ddc_bus);
939         int ret;
940         u8 *write_buf;
941         struct i2c_msg msg;
942
943         write_buf = kzalloc(size + 1, GFP_KERNEL);
944         if (!write_buf)
945                 return -ENOMEM;
946
947         write_buf[0] = offset & 0xff;
948         memcpy(&write_buf[1], buffer, size);
949
950         msg.addr = DRM_HDCP_DDC_ADDR;
951         msg.flags = 0,
952         msg.len = size + 1,
953         msg.buf = write_buf;
954
955         ret = i2c_transfer(adapter, &msg, 1);
956         if (ret == 1)
957                 ret = 0;
958         else if (ret >= 0)
959                 ret = -EIO;
960
961         kfree(write_buf);
962         return ret;
963 }
964
965 static
966 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
967                                   u8 *an)
968 {
969         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
970         struct drm_i915_private *dev_priv =
971                 intel_dig_port->base.base.dev->dev_private;
972         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
973                                                               hdmi->ddc_bus);
974         int ret;
975
976         ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
977                                     DRM_HDCP_AN_LEN);
978         if (ret) {
979                 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
980                 return ret;
981         }
982
983         ret = intel_gmbus_output_aksv(adapter);
984         if (ret < 0) {
985                 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
986                 return ret;
987         }
988         return 0;
989 }
990
991 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
992                                      u8 *bksv)
993 {
994         int ret;
995         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
996                                    DRM_HDCP_KSV_LEN);
997         if (ret)
998                 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
999         return ret;
1000 }
1001
1002 static
1003 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1004                                  u8 *bstatus)
1005 {
1006         int ret;
1007         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1008                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1009         if (ret)
1010                 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1011         return ret;
1012 }
1013
1014 static
1015 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1016                                      bool *repeater_present)
1017 {
1018         int ret;
1019         u8 val;
1020
1021         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1022         if (ret) {
1023                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1024                 return ret;
1025         }
1026         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1027         return 0;
1028 }
1029
1030 static
1031 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1032                                   u8 *ri_prime)
1033 {
1034         int ret;
1035         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1036                                    ri_prime, DRM_HDCP_RI_LEN);
1037         if (ret)
1038                 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1039         return ret;
1040 }
1041
1042 static
1043 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1044                                    bool *ksv_ready)
1045 {
1046         int ret;
1047         u8 val;
1048
1049         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1050         if (ret) {
1051                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1052                 return ret;
1053         }
1054         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1055         return 0;
1056 }
1057
1058 static
1059 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1060                                   int num_downstream, u8 *ksv_fifo)
1061 {
1062         int ret;
1063         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1064                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1065         if (ret) {
1066                 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1067                 return ret;
1068         }
1069         return 0;
1070 }
1071
1072 static
1073 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1074                                       int i, u32 *part)
1075 {
1076         int ret;
1077
1078         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1079                 return -EINVAL;
1080
1081         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1082                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1083         if (ret)
1084                 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1085         return ret;
1086 }
1087
1088 static
1089 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1090                                       bool enable)
1091 {
1092         int ret;
1093
1094         if (!enable)
1095                 usleep_range(6, 60); /* Bspec says >= 6us */
1096
1097         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1098         if (ret) {
1099                 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1100                           enable ? "Enable" : "Disable", ret);
1101                 return ret;
1102         }
1103         return 0;
1104 }
1105
1106 static
1107 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1108 {
1109         struct drm_i915_private *dev_priv =
1110                 intel_dig_port->base.base.dev->dev_private;
1111         enum port port = intel_dig_port->base.port;
1112         int ret;
1113         union {
1114                 u32 reg;
1115                 u8 shim[DRM_HDCP_RI_LEN];
1116         } ri;
1117
1118         ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1119         if (ret)
1120                 return false;
1121
1122         I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1123
1124         /* Wait for Ri prime match */
1125         if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1126                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1127                 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1128                           I915_READ(PORT_HDCP_STATUS(port)));
1129                 return false;
1130         }
1131         return true;
1132 }
1133
1134 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1135         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1136         .read_bksv = intel_hdmi_hdcp_read_bksv,
1137         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1138         .repeater_present = intel_hdmi_hdcp_repeater_present,
1139         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1140         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1141         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1142         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1143         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1144         .check_link = intel_hdmi_hdcp_check_link,
1145 };
1146
1147 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1148                                const struct intel_crtc_state *crtc_state)
1149 {
1150         struct drm_device *dev = encoder->base.dev;
1151         struct drm_i915_private *dev_priv = to_i915(dev);
1152         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1153         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1154         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1155         u32 hdmi_val;
1156
1157         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1158
1159         hdmi_val = SDVO_ENCODING_HDMI;
1160         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1161                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1162         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1163                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1164         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1165                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1166
1167         if (crtc_state->pipe_bpp > 24)
1168                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1169         else
1170                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1171
1172         if (crtc_state->has_hdmi_sink)
1173                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1174
1175         if (HAS_PCH_CPT(dev_priv))
1176                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1177         else if (IS_CHERRYVIEW(dev_priv))
1178                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1179         else
1180                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1181
1182         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1183         POSTING_READ(intel_hdmi->hdmi_reg);
1184 }
1185
1186 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1187                                     enum pipe *pipe)
1188 {
1189         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1190         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1191         intel_wakeref_t wakeref;
1192         bool ret;
1193
1194         wakeref = intel_display_power_get_if_enabled(dev_priv,
1195                                                      encoder->power_domain);
1196         if (!wakeref)
1197                 return false;
1198
1199         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1200
1201         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1202
1203         return ret;
1204 }
1205
1206 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1207                                   struct intel_crtc_state *pipe_config)
1208 {
1209         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1210         struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
1211         struct drm_device *dev = encoder->base.dev;
1212         struct drm_i915_private *dev_priv = to_i915(dev);
1213         u32 tmp, flags = 0;
1214         int dotclock;
1215
1216         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1217
1218         tmp = I915_READ(intel_hdmi->hdmi_reg);
1219
1220         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1221                 flags |= DRM_MODE_FLAG_PHSYNC;
1222         else
1223                 flags |= DRM_MODE_FLAG_NHSYNC;
1224
1225         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1226                 flags |= DRM_MODE_FLAG_PVSYNC;
1227         else
1228                 flags |= DRM_MODE_FLAG_NVSYNC;
1229
1230         if (tmp & HDMI_MODE_SELECT_HDMI)
1231                 pipe_config->has_hdmi_sink = true;
1232
1233         if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
1234                 pipe_config->has_infoframe = true;
1235
1236         if (tmp & SDVO_AUDIO_ENABLE)
1237                 pipe_config->has_audio = true;
1238
1239         if (!HAS_PCH_SPLIT(dev_priv) &&
1240             tmp & HDMI_COLOR_RANGE_16_235)
1241                 pipe_config->limited_color_range = true;
1242
1243         pipe_config->base.adjusted_mode.flags |= flags;
1244
1245         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1246                 dotclock = pipe_config->port_clock * 2 / 3;
1247         else
1248                 dotclock = pipe_config->port_clock;
1249
1250         if (pipe_config->pixel_multiplier)
1251                 dotclock /= pipe_config->pixel_multiplier;
1252
1253         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1254
1255         pipe_config->lane_count = 4;
1256 }
1257
1258 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1259                                     const struct intel_crtc_state *pipe_config,
1260                                     const struct drm_connector_state *conn_state)
1261 {
1262         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1263
1264         WARN_ON(!pipe_config->has_hdmi_sink);
1265         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1266                          pipe_name(crtc->pipe));
1267         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1268 }
1269
1270 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1271                             const struct intel_crtc_state *pipe_config,
1272                             const struct drm_connector_state *conn_state)
1273 {
1274         struct drm_device *dev = encoder->base.dev;
1275         struct drm_i915_private *dev_priv = to_i915(dev);
1276         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1277         u32 temp;
1278
1279         temp = I915_READ(intel_hdmi->hdmi_reg);
1280
1281         temp |= SDVO_ENABLE;
1282         if (pipe_config->has_audio)
1283                 temp |= SDVO_AUDIO_ENABLE;
1284
1285         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1286         POSTING_READ(intel_hdmi->hdmi_reg);
1287
1288         if (pipe_config->has_audio)
1289                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1290 }
1291
1292 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1293                             const struct intel_crtc_state *pipe_config,
1294                             const struct drm_connector_state *conn_state)
1295 {
1296         struct drm_device *dev = encoder->base.dev;
1297         struct drm_i915_private *dev_priv = to_i915(dev);
1298         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1299         u32 temp;
1300
1301         temp = I915_READ(intel_hdmi->hdmi_reg);
1302
1303         temp |= SDVO_ENABLE;
1304         if (pipe_config->has_audio)
1305                 temp |= SDVO_AUDIO_ENABLE;
1306
1307         /*
1308          * HW workaround, need to write this twice for issue
1309          * that may result in first write getting masked.
1310          */
1311         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1312         POSTING_READ(intel_hdmi->hdmi_reg);
1313         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1314         POSTING_READ(intel_hdmi->hdmi_reg);
1315
1316         /*
1317          * HW workaround, need to toggle enable bit off and on
1318          * for 12bpc with pixel repeat.
1319          *
1320          * FIXME: BSpec says this should be done at the end of
1321          * of the modeset sequence, so not sure if this isn't too soon.
1322          */
1323         if (pipe_config->pipe_bpp > 24 &&
1324             pipe_config->pixel_multiplier > 1) {
1325                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1326                 POSTING_READ(intel_hdmi->hdmi_reg);
1327
1328                 /*
1329                  * HW workaround, need to write this twice for issue
1330                  * that may result in first write getting masked.
1331                  */
1332                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1333                 POSTING_READ(intel_hdmi->hdmi_reg);
1334                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1335                 POSTING_READ(intel_hdmi->hdmi_reg);
1336         }
1337
1338         if (pipe_config->has_audio)
1339                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1340 }
1341
1342 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1343                             const struct intel_crtc_state *pipe_config,
1344                             const struct drm_connector_state *conn_state)
1345 {
1346         struct drm_device *dev = encoder->base.dev;
1347         struct drm_i915_private *dev_priv = to_i915(dev);
1348         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1349         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1350         enum pipe pipe = crtc->pipe;
1351         u32 temp;
1352
1353         temp = I915_READ(intel_hdmi->hdmi_reg);
1354
1355         temp |= SDVO_ENABLE;
1356         if (pipe_config->has_audio)
1357                 temp |= SDVO_AUDIO_ENABLE;
1358
1359         /*
1360          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1361          *
1362          * The procedure for 12bpc is as follows:
1363          * 1. disable HDMI clock gating
1364          * 2. enable HDMI with 8bpc
1365          * 3. enable HDMI with 12bpc
1366          * 4. enable HDMI clock gating
1367          */
1368
1369         if (pipe_config->pipe_bpp > 24) {
1370                 I915_WRITE(TRANS_CHICKEN1(pipe),
1371                            I915_READ(TRANS_CHICKEN1(pipe)) |
1372                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1373
1374                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1375                 temp |= SDVO_COLOR_FORMAT_8bpc;
1376         }
1377
1378         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1379         POSTING_READ(intel_hdmi->hdmi_reg);
1380
1381         if (pipe_config->pipe_bpp > 24) {
1382                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1383                 temp |= HDMI_COLOR_FORMAT_12bpc;
1384
1385                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1386                 POSTING_READ(intel_hdmi->hdmi_reg);
1387
1388                 I915_WRITE(TRANS_CHICKEN1(pipe),
1389                            I915_READ(TRANS_CHICKEN1(pipe)) &
1390                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1391         }
1392
1393         if (pipe_config->has_audio)
1394                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1395 }
1396
1397 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1398                             const struct intel_crtc_state *pipe_config,
1399                             const struct drm_connector_state *conn_state)
1400 {
1401 }
1402
1403 static void intel_disable_hdmi(struct intel_encoder *encoder,
1404                                const struct intel_crtc_state *old_crtc_state,
1405                                const struct drm_connector_state *old_conn_state)
1406 {
1407         struct drm_device *dev = encoder->base.dev;
1408         struct drm_i915_private *dev_priv = to_i915(dev);
1409         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1410         struct intel_digital_port *intel_dig_port =
1411                 hdmi_to_dig_port(intel_hdmi);
1412         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1413         u32 temp;
1414
1415         temp = I915_READ(intel_hdmi->hdmi_reg);
1416
1417         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1418         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1419         POSTING_READ(intel_hdmi->hdmi_reg);
1420
1421         /*
1422          * HW workaround for IBX, we need to move the port
1423          * to transcoder A after disabling it to allow the
1424          * matching DP port to be enabled on transcoder A.
1425          */
1426         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1427                 /*
1428                  * We get CPU/PCH FIFO underruns on the other pipe when
1429                  * doing the workaround. Sweep them under the rug.
1430                  */
1431                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1432                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1433
1434                 temp &= ~SDVO_PIPE_SEL_MASK;
1435                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1436                 /*
1437                  * HW workaround, need to write this twice for issue
1438                  * that may result in first write getting masked.
1439                  */
1440                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1441                 POSTING_READ(intel_hdmi->hdmi_reg);
1442                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1443                 POSTING_READ(intel_hdmi->hdmi_reg);
1444
1445                 temp &= ~SDVO_ENABLE;
1446                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1447                 POSTING_READ(intel_hdmi->hdmi_reg);
1448
1449                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1450                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1451                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1452         }
1453
1454         intel_dig_port->set_infoframes(encoder,
1455                                        false,
1456                                        old_crtc_state, old_conn_state);
1457
1458         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1459 }
1460
1461 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1462                              const struct intel_crtc_state *old_crtc_state,
1463                              const struct drm_connector_state *old_conn_state)
1464 {
1465         if (old_crtc_state->has_audio)
1466                 intel_audio_codec_disable(encoder,
1467                                           old_crtc_state, old_conn_state);
1468
1469         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1470 }
1471
1472 static void pch_disable_hdmi(struct intel_encoder *encoder,
1473                              const struct intel_crtc_state *old_crtc_state,
1474                              const struct drm_connector_state *old_conn_state)
1475 {
1476         if (old_crtc_state->has_audio)
1477                 intel_audio_codec_disable(encoder,
1478                                           old_crtc_state, old_conn_state);
1479 }
1480
1481 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1482                                   const struct intel_crtc_state *old_crtc_state,
1483                                   const struct drm_connector_state *old_conn_state)
1484 {
1485         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1486 }
1487
1488 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1489 {
1490         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1491         const struct ddi_vbt_port_info *info =
1492                 &dev_priv->vbt.ddi_port_info[encoder->port];
1493         int max_tmds_clock;
1494
1495         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1496                 max_tmds_clock = 594000;
1497         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1498                 max_tmds_clock = 300000;
1499         else if (INTEL_GEN(dev_priv) >= 5)
1500                 max_tmds_clock = 225000;
1501         else
1502                 max_tmds_clock = 165000;
1503
1504         if (info->max_tmds_clock)
1505                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1506
1507         return max_tmds_clock;
1508 }
1509
1510 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1511                                  bool respect_downstream_limits,
1512                                  bool force_dvi)
1513 {
1514         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1515         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1516
1517         if (respect_downstream_limits) {
1518                 struct intel_connector *connector = hdmi->attached_connector;
1519                 const struct drm_display_info *info = &connector->base.display_info;
1520
1521                 if (hdmi->dp_dual_mode.max_tmds_clock)
1522                         max_tmds_clock = min(max_tmds_clock,
1523                                              hdmi->dp_dual_mode.max_tmds_clock);
1524
1525                 if (info->max_tmds_clock)
1526                         max_tmds_clock = min(max_tmds_clock,
1527                                              info->max_tmds_clock);
1528                 else if (!hdmi->has_hdmi_sink || force_dvi)
1529                         max_tmds_clock = min(max_tmds_clock, 165000);
1530         }
1531
1532         return max_tmds_clock;
1533 }
1534
1535 static enum drm_mode_status
1536 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1537                       int clock, bool respect_downstream_limits,
1538                       bool force_dvi)
1539 {
1540         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1541
1542         if (clock < 25000)
1543                 return MODE_CLOCK_LOW;
1544         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1545                 return MODE_CLOCK_HIGH;
1546
1547         /* BXT DPLL can't generate 223-240 MHz */
1548         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1549                 return MODE_CLOCK_RANGE;
1550
1551         /* CHV DPLL can't generate 216-240 MHz */
1552         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1553                 return MODE_CLOCK_RANGE;
1554
1555         return MODE_OK;
1556 }
1557
1558 static enum drm_mode_status
1559 intel_hdmi_mode_valid(struct drm_connector *connector,
1560                       struct drm_display_mode *mode)
1561 {
1562         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1563         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1564         struct drm_i915_private *dev_priv = to_i915(dev);
1565         enum drm_mode_status status;
1566         int clock;
1567         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1568         bool force_dvi =
1569                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1570
1571         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1572                 return MODE_NO_DBLESCAN;
1573
1574         clock = mode->clock;
1575
1576         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1577                 clock *= 2;
1578
1579         if (clock > max_dotclk)
1580                 return MODE_CLOCK_HIGH;
1581
1582         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1583                 clock *= 2;
1584
1585         if (drm_mode_is_420_only(&connector->display_info, mode))
1586                 clock /= 2;
1587
1588         /* check if we can do 8bpc */
1589         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1590
1591         if (hdmi->has_hdmi_sink && !force_dvi) {
1592                 /* if we can't do 8bpc we may still be able to do 12bpc */
1593                 if (status != MODE_OK && !HAS_GMCH(dev_priv))
1594                         status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
1595                                                        true, force_dvi);
1596
1597                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1598                 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
1599                         status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
1600                                                        true, force_dvi);
1601         }
1602
1603         return status;
1604 }
1605
1606 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1607                                      int bpc)
1608 {
1609         struct drm_i915_private *dev_priv =
1610                 to_i915(crtc_state->base.crtc->dev);
1611         struct drm_atomic_state *state = crtc_state->base.state;
1612         struct drm_connector_state *connector_state;
1613         struct drm_connector *connector;
1614         const struct drm_display_mode *adjusted_mode =
1615                 &crtc_state->base.adjusted_mode;
1616         int i;
1617
1618         if (HAS_GMCH(dev_priv))
1619                 return false;
1620
1621         if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
1622                 return false;
1623
1624         if (crtc_state->pipe_bpp <= 8*3)
1625                 return false;
1626
1627         if (!crtc_state->has_hdmi_sink)
1628                 return false;
1629
1630         /*
1631          * HDMI deep color affects the clocks, so it's only possible
1632          * when not cloning with other encoder types.
1633          */
1634         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1635                 return false;
1636
1637         for_each_new_connector_in_state(state, connector, connector_state, i) {
1638                 const struct drm_display_info *info = &connector->display_info;
1639
1640                 if (connector_state->crtc != crtc_state->base.crtc)
1641                         continue;
1642
1643                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1644                         const struct drm_hdmi_info *hdmi = &info->hdmi;
1645
1646                         if (bpc == 12 && !(hdmi->y420_dc_modes &
1647                                            DRM_EDID_YCBCR420_DC_36))
1648                                 return false;
1649                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
1650                                                 DRM_EDID_YCBCR420_DC_30))
1651                                 return false;
1652                 } else {
1653                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
1654                                            DRM_EDID_HDMI_DC_36))
1655                                 return false;
1656                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
1657                                                 DRM_EDID_HDMI_DC_30))
1658                                 return false;
1659                 }
1660         }
1661
1662         /* Display WA #1139: glk */
1663         if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1664             adjusted_mode->htotal > 5460)
1665                 return false;
1666
1667         /* Display Wa_1405510057:icl */
1668         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1669             bpc == 10 && IS_ICELAKE(dev_priv) &&
1670             (adjusted_mode->crtc_hblank_end -
1671              adjusted_mode->crtc_hblank_start) % 8 == 2)
1672                 return false;
1673
1674         return true;
1675 }
1676
1677 static bool
1678 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1679                            struct intel_crtc_state *config,
1680                            int *clock_12bpc, int *clock_10bpc,
1681                            int *clock_8bpc)
1682 {
1683         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1684
1685         if (!connector->ycbcr_420_allowed) {
1686                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1687                 return false;
1688         }
1689
1690         /* YCBCR420 TMDS rate requirement is half the pixel clock */
1691         config->port_clock /= 2;
1692         *clock_12bpc /= 2;
1693         *clock_10bpc /= 2;
1694         *clock_8bpc /= 2;
1695         config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1696
1697         /* YCBCR 420 output conversion needs a scaler */
1698         if (skl_update_scaler_crtc(config)) {
1699                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1700                 return false;
1701         }
1702
1703         intel_pch_panel_fitting(intel_crtc, config,
1704                                 DRM_MODE_SCALE_FULLSCREEN);
1705
1706         return true;
1707 }
1708
1709 int intel_hdmi_compute_config(struct intel_encoder *encoder,
1710                               struct intel_crtc_state *pipe_config,
1711                               struct drm_connector_state *conn_state)
1712 {
1713         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1714         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1715         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1716         struct drm_connector *connector = conn_state->connector;
1717         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1718         struct intel_digital_connector_state *intel_conn_state =
1719                 to_intel_digital_connector_state(conn_state);
1720         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1721         int clock_10bpc = clock_8bpc * 5 / 4;
1722         int clock_12bpc = clock_8bpc * 3 / 2;
1723         int desired_bpp;
1724         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1725
1726         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1727                 return -EINVAL;
1728
1729         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1730         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1731
1732         if (pipe_config->has_hdmi_sink)
1733                 pipe_config->has_infoframe = true;
1734
1735         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1736                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1737                 pipe_config->limited_color_range =
1738                         pipe_config->has_hdmi_sink &&
1739                         drm_default_rgb_quant_range(adjusted_mode) ==
1740                         HDMI_QUANTIZATION_RANGE_LIMITED;
1741         } else {
1742                 pipe_config->limited_color_range =
1743                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1744         }
1745
1746         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1747                 pipe_config->pixel_multiplier = 2;
1748                 clock_8bpc *= 2;
1749                 clock_10bpc *= 2;
1750                 clock_12bpc *= 2;
1751         }
1752
1753         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1754                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1755                                                 &clock_12bpc, &clock_10bpc,
1756                                                 &clock_8bpc)) {
1757                         DRM_ERROR("Can't support YCBCR420 output\n");
1758                         return -EINVAL;
1759                 }
1760         }
1761
1762         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1763                 pipe_config->has_pch_encoder = true;
1764
1765         if (pipe_config->has_hdmi_sink) {
1766                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1767                         pipe_config->has_audio = intel_hdmi->has_audio;
1768                 else
1769                         pipe_config->has_audio =
1770                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1771         }
1772
1773         /*
1774          * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
1775          * to check that the higher clock still fits within limits.
1776          */
1777         if (hdmi_deep_color_possible(pipe_config, 12) &&
1778             hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
1779                                   true, force_dvi) == MODE_OK) {
1780                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1781                 desired_bpp = 12*3;
1782
1783                 /* Need to adjust the port link by 1.5x for 12bpc. */
1784                 pipe_config->port_clock = clock_12bpc;
1785         } else if (hdmi_deep_color_possible(pipe_config, 10) &&
1786                    hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
1787                                          true, force_dvi) == MODE_OK) {
1788                 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
1789                 desired_bpp = 10 * 3;
1790
1791                 /* Need to adjust the port link by 1.25x for 10bpc. */
1792                 pipe_config->port_clock = clock_10bpc;
1793         } else {
1794                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1795                 desired_bpp = 8*3;
1796
1797                 pipe_config->port_clock = clock_8bpc;
1798         }
1799
1800         if (!pipe_config->bw_constrained) {
1801                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1802                 pipe_config->pipe_bpp = desired_bpp;
1803         }
1804
1805         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1806                                   false, force_dvi) != MODE_OK) {
1807                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1808                 return -EINVAL;
1809         }
1810
1811         /* Set user selected PAR to incoming mode's member */
1812         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1813
1814         pipe_config->lane_count = 4;
1815
1816         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
1817                                            IS_GEMINILAKE(dev_priv))) {
1818                 if (scdc->scrambling.low_rates)
1819                         pipe_config->hdmi_scrambling = true;
1820
1821                 if (pipe_config->port_clock > 340000) {
1822                         pipe_config->hdmi_scrambling = true;
1823                         pipe_config->hdmi_high_tmds_clock_ratio = true;
1824                 }
1825         }
1826
1827         return 0;
1828 }
1829
1830 static void
1831 intel_hdmi_unset_edid(struct drm_connector *connector)
1832 {
1833         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1834
1835         intel_hdmi->has_hdmi_sink = false;
1836         intel_hdmi->has_audio = false;
1837
1838         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1839         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1840
1841         kfree(to_intel_connector(connector)->detect_edid);
1842         to_intel_connector(connector)->detect_edid = NULL;
1843 }
1844
1845 static void
1846 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1847 {
1848         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1849         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1850         enum port port = hdmi_to_dig_port(hdmi)->base.port;
1851         struct i2c_adapter *adapter =
1852                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1853         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1854
1855         /*
1856          * Type 1 DVI adaptors are not required to implement any
1857          * registers, so we can't always detect their presence.
1858          * Ideally we should be able to check the state of the
1859          * CONFIG1 pin, but no such luck on our hardware.
1860          *
1861          * The only method left to us is to check the VBT to see
1862          * if the port is a dual mode capable DP port. But let's
1863          * only do that when we sucesfully read the EDID, to avoid
1864          * confusing log messages about DP dual mode adaptors when
1865          * there's nothing connected to the port.
1866          */
1867         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1868                 /* An overridden EDID imply that we want this port for testing.
1869                  * Make sure not to set limits for that port.
1870                  */
1871                 if (has_edid && !connector->override_edid &&
1872                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1873                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1874                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1875                 } else {
1876                         type = DRM_DP_DUAL_MODE_NONE;
1877                 }
1878         }
1879
1880         if (type == DRM_DP_DUAL_MODE_NONE)
1881                 return;
1882
1883         hdmi->dp_dual_mode.type = type;
1884         hdmi->dp_dual_mode.max_tmds_clock =
1885                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1886
1887         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1888                       drm_dp_get_dual_mode_type_name(type),
1889                       hdmi->dp_dual_mode.max_tmds_clock);
1890 }
1891
1892 static bool
1893 intel_hdmi_set_edid(struct drm_connector *connector)
1894 {
1895         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1896         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1897         intel_wakeref_t wakeref;
1898         struct edid *edid;
1899         bool connected = false;
1900         struct i2c_adapter *i2c;
1901
1902         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1903
1904         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
1905
1906         edid = drm_get_edid(connector, i2c);
1907
1908         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
1909                 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
1910                 intel_gmbus_force_bit(i2c, true);
1911                 edid = drm_get_edid(connector, i2c);
1912                 intel_gmbus_force_bit(i2c, false);
1913         }
1914
1915         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1916
1917         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
1918
1919         to_intel_connector(connector)->detect_edid = edid;
1920         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1921                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1922                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1923
1924                 connected = true;
1925         }
1926
1927         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
1928
1929         return connected;
1930 }
1931
1932 static enum drm_connector_status
1933 intel_hdmi_detect(struct drm_connector *connector, bool force)
1934 {
1935         enum drm_connector_status status = connector_status_disconnected;
1936         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1937         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1938         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
1939         intel_wakeref_t wakeref;
1940
1941         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1942                       connector->base.id, connector->name);
1943
1944         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1945
1946         if (IS_ICELAKE(dev_priv) &&
1947             !intel_digital_port_connected(encoder))
1948                 goto out;
1949
1950         intel_hdmi_unset_edid(connector);
1951
1952         if (intel_hdmi_set_edid(connector))
1953                 status = connector_status_connected;
1954
1955 out:
1956         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
1957
1958         if (status != connector_status_connected)
1959                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
1960
1961         return status;
1962 }
1963
1964 static void
1965 intel_hdmi_force(struct drm_connector *connector)
1966 {
1967         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1968                       connector->base.id, connector->name);
1969
1970         intel_hdmi_unset_edid(connector);
1971
1972         if (connector->status != connector_status_connected)
1973                 return;
1974
1975         intel_hdmi_set_edid(connector);
1976 }
1977
1978 static int intel_hdmi_get_modes(struct drm_connector *connector)
1979 {
1980         struct edid *edid;
1981
1982         edid = to_intel_connector(connector)->detect_edid;
1983         if (edid == NULL)
1984                 return 0;
1985
1986         return intel_connector_update_modes(connector, edid);
1987 }
1988
1989 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1990                                   const struct intel_crtc_state *pipe_config,
1991                                   const struct drm_connector_state *conn_state)
1992 {
1993         struct intel_digital_port *intel_dig_port =
1994                 enc_to_dig_port(&encoder->base);
1995
1996         intel_hdmi_prepare(encoder, pipe_config);
1997
1998         intel_dig_port->set_infoframes(encoder,
1999                                        pipe_config->has_infoframe,
2000                                        pipe_config, conn_state);
2001 }
2002
2003 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2004                                 const struct intel_crtc_state *pipe_config,
2005                                 const struct drm_connector_state *conn_state)
2006 {
2007         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2008         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2009
2010         vlv_phy_pre_encoder_enable(encoder, pipe_config);
2011
2012         /* HDMI 1.0V-2dB */
2013         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2014                                  0x2b247878);
2015
2016         dport->set_infoframes(encoder,
2017                               pipe_config->has_infoframe,
2018                               pipe_config, conn_state);
2019
2020         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2021
2022         vlv_wait_port_ready(dev_priv, dport, 0x0);
2023 }
2024
2025 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2026                                     const struct intel_crtc_state *pipe_config,
2027                                     const struct drm_connector_state *conn_state)
2028 {
2029         intel_hdmi_prepare(encoder, pipe_config);
2030
2031         vlv_phy_pre_pll_enable(encoder, pipe_config);
2032 }
2033
2034 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2035                                     const struct intel_crtc_state *pipe_config,
2036                                     const struct drm_connector_state *conn_state)
2037 {
2038         intel_hdmi_prepare(encoder, pipe_config);
2039
2040         chv_phy_pre_pll_enable(encoder, pipe_config);
2041 }
2042
2043 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2044                                       const struct intel_crtc_state *old_crtc_state,
2045                                       const struct drm_connector_state *old_conn_state)
2046 {
2047         chv_phy_post_pll_disable(encoder, old_crtc_state);
2048 }
2049
2050 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2051                                   const struct intel_crtc_state *old_crtc_state,
2052                                   const struct drm_connector_state *old_conn_state)
2053 {
2054         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2055         vlv_phy_reset_lanes(encoder, old_crtc_state);
2056 }
2057
2058 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2059                                   const struct intel_crtc_state *old_crtc_state,
2060                                   const struct drm_connector_state *old_conn_state)
2061 {
2062         struct drm_device *dev = encoder->base.dev;
2063         struct drm_i915_private *dev_priv = to_i915(dev);
2064
2065         mutex_lock(&dev_priv->sb_lock);
2066
2067         /* Assert data lane reset */
2068         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2069
2070         mutex_unlock(&dev_priv->sb_lock);
2071 }
2072
2073 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2074                                 const struct intel_crtc_state *pipe_config,
2075                                 const struct drm_connector_state *conn_state)
2076 {
2077         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2078         struct drm_device *dev = encoder->base.dev;
2079         struct drm_i915_private *dev_priv = to_i915(dev);
2080
2081         chv_phy_pre_encoder_enable(encoder, pipe_config);
2082
2083         /* FIXME: Program the support xxx V-dB */
2084         /* Use 800mV-0dB */
2085         chv_set_phy_signal_level(encoder, 128, 102, false);
2086
2087         dport->set_infoframes(encoder,
2088                               pipe_config->has_infoframe,
2089                               pipe_config, conn_state);
2090
2091         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2092
2093         vlv_wait_port_ready(dev_priv, dport, 0x0);
2094
2095         /* Second common lane will stay alive on its own now */
2096         chv_phy_release_cl2_override(encoder);
2097 }
2098
2099 static int
2100 intel_hdmi_connector_register(struct drm_connector *connector)
2101 {
2102         int ret;
2103
2104         ret = intel_connector_register(connector);
2105         if (ret)
2106                 return ret;
2107
2108         i915_debugfs_connector_add(connector);
2109
2110         return ret;
2111 }
2112
2113 static void intel_hdmi_destroy(struct drm_connector *connector)
2114 {
2115         if (intel_attached_hdmi(connector)->cec_notifier)
2116                 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2117
2118         intel_connector_destroy(connector);
2119 }
2120
2121 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2122         .detect = intel_hdmi_detect,
2123         .force = intel_hdmi_force,
2124         .fill_modes = drm_helper_probe_single_connector_modes,
2125         .atomic_get_property = intel_digital_connector_atomic_get_property,
2126         .atomic_set_property = intel_digital_connector_atomic_set_property,
2127         .late_register = intel_hdmi_connector_register,
2128         .early_unregister = intel_connector_unregister,
2129         .destroy = intel_hdmi_destroy,
2130         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2131         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2132 };
2133
2134 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2135         .get_modes = intel_hdmi_get_modes,
2136         .mode_valid = intel_hdmi_mode_valid,
2137         .atomic_check = intel_digital_connector_atomic_check,
2138 };
2139
2140 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2141         .destroy = intel_encoder_destroy,
2142 };
2143
2144 static void
2145 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2146 {
2147         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2148         struct intel_digital_port *intel_dig_port =
2149                                 hdmi_to_dig_port(intel_hdmi);
2150
2151         intel_attach_force_audio_property(connector);
2152         intel_attach_broadcast_rgb_property(connector);
2153         intel_attach_aspect_ratio_property(connector);
2154
2155         /*
2156          * Attach Colorspace property for Non LSPCON based device
2157          * ToDo: This needs to be extended for LSPCON implementation
2158          * as well. Will be implemented separately.
2159          */
2160         if (!intel_dig_port->lspcon.active)
2161                 intel_attach_colorspace_property(connector);
2162
2163         drm_connector_attach_content_type_property(connector);
2164         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2165
2166         if (!HAS_GMCH(dev_priv))
2167                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2168 }
2169
2170 /*
2171  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2172  * @encoder: intel_encoder
2173  * @connector: drm_connector
2174  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2175  *  or reset the high tmds clock ratio for scrambling
2176  * @scrambling: bool to Indicate if the function needs to set or reset
2177  *  sink scrambling
2178  *
2179  * This function handles scrambling on HDMI 2.0 capable sinks.
2180  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2181  * it enables scrambling. This should be called before enabling the HDMI
2182  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2183  * detect a scrambled clock within 100 ms.
2184  *
2185  * Returns:
2186  * True on success, false on failure.
2187  */
2188 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2189                                        struct drm_connector *connector,
2190                                        bool high_tmds_clock_ratio,
2191                                        bool scrambling)
2192 {
2193         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2194         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2195         struct drm_scrambling *sink_scrambling =
2196                 &connector->display_info.hdmi.scdc.scrambling;
2197         struct i2c_adapter *adapter =
2198                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2199
2200         if (!sink_scrambling->supported)
2201                 return true;
2202
2203         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2204                       connector->base.id, connector->name,
2205                       yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2206
2207         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2208         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2209                                                   high_tmds_clock_ratio) &&
2210                 drm_scdc_set_scrambling(adapter, scrambling);
2211 }
2212
2213 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2214 {
2215         u8 ddc_pin;
2216
2217         switch (port) {
2218         case PORT_B:
2219                 ddc_pin = GMBUS_PIN_DPB;
2220                 break;
2221         case PORT_C:
2222                 ddc_pin = GMBUS_PIN_DPC;
2223                 break;
2224         case PORT_D:
2225                 ddc_pin = GMBUS_PIN_DPD_CHV;
2226                 break;
2227         default:
2228                 MISSING_CASE(port);
2229                 ddc_pin = GMBUS_PIN_DPB;
2230                 break;
2231         }
2232         return ddc_pin;
2233 }
2234
2235 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2236 {
2237         u8 ddc_pin;
2238
2239         switch (port) {
2240         case PORT_B:
2241                 ddc_pin = GMBUS_PIN_1_BXT;
2242                 break;
2243         case PORT_C:
2244                 ddc_pin = GMBUS_PIN_2_BXT;
2245                 break;
2246         default:
2247                 MISSING_CASE(port);
2248                 ddc_pin = GMBUS_PIN_1_BXT;
2249                 break;
2250         }
2251         return ddc_pin;
2252 }
2253
2254 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2255                               enum port port)
2256 {
2257         u8 ddc_pin;
2258
2259         switch (port) {
2260         case PORT_B:
2261                 ddc_pin = GMBUS_PIN_1_BXT;
2262                 break;
2263         case PORT_C:
2264                 ddc_pin = GMBUS_PIN_2_BXT;
2265                 break;
2266         case PORT_D:
2267                 ddc_pin = GMBUS_PIN_4_CNP;
2268                 break;
2269         case PORT_F:
2270                 ddc_pin = GMBUS_PIN_3_BXT;
2271                 break;
2272         default:
2273                 MISSING_CASE(port);
2274                 ddc_pin = GMBUS_PIN_1_BXT;
2275                 break;
2276         }
2277         return ddc_pin;
2278 }
2279
2280 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2281 {
2282         u8 ddc_pin;
2283
2284         switch (port) {
2285         case PORT_A:
2286                 ddc_pin = GMBUS_PIN_1_BXT;
2287                 break;
2288         case PORT_B:
2289                 ddc_pin = GMBUS_PIN_2_BXT;
2290                 break;
2291         case PORT_C:
2292                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2293                 break;
2294         case PORT_D:
2295                 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2296                 break;
2297         case PORT_E:
2298                 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2299                 break;
2300         case PORT_F:
2301                 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2302                 break;
2303         default:
2304                 MISSING_CASE(port);
2305                 ddc_pin = GMBUS_PIN_2_BXT;
2306                 break;
2307         }
2308         return ddc_pin;
2309 }
2310
2311 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2312                               enum port port)
2313 {
2314         u8 ddc_pin;
2315
2316         switch (port) {
2317         case PORT_B:
2318                 ddc_pin = GMBUS_PIN_DPB;
2319                 break;
2320         case PORT_C:
2321                 ddc_pin = GMBUS_PIN_DPC;
2322                 break;
2323         case PORT_D:
2324                 ddc_pin = GMBUS_PIN_DPD;
2325                 break;
2326         default:
2327                 MISSING_CASE(port);
2328                 ddc_pin = GMBUS_PIN_DPB;
2329                 break;
2330         }
2331         return ddc_pin;
2332 }
2333
2334 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2335                              enum port port)
2336 {
2337         const struct ddi_vbt_port_info *info =
2338                 &dev_priv->vbt.ddi_port_info[port];
2339         u8 ddc_pin;
2340
2341         if (info->alternate_ddc_pin) {
2342                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2343                               info->alternate_ddc_pin, port_name(port));
2344                 return info->alternate_ddc_pin;
2345         }
2346
2347         if (IS_CHERRYVIEW(dev_priv))
2348                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2349         else if (IS_GEN9_LP(dev_priv))
2350                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2351         else if (HAS_PCH_CNP(dev_priv))
2352                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2353         else if (HAS_PCH_ICP(dev_priv))
2354                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2355         else
2356                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2357
2358         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2359                       ddc_pin, port_name(port));
2360
2361         return ddc_pin;
2362 }
2363
2364 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2365 {
2366         struct drm_i915_private *dev_priv =
2367                 to_i915(intel_dig_port->base.base.dev);
2368
2369         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2370                 intel_dig_port->write_infoframe = vlv_write_infoframe;
2371                 intel_dig_port->set_infoframes = vlv_set_infoframes;
2372                 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
2373         } else if (IS_G4X(dev_priv)) {
2374                 intel_dig_port->write_infoframe = g4x_write_infoframe;
2375                 intel_dig_port->set_infoframes = g4x_set_infoframes;
2376                 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
2377         } else if (HAS_DDI(dev_priv)) {
2378                 if (intel_dig_port->lspcon.active) {
2379                         intel_dig_port->write_infoframe =
2380                                         lspcon_write_infoframe;
2381                         intel_dig_port->set_infoframes = lspcon_set_infoframes;
2382                         intel_dig_port->infoframe_enabled =
2383                                                 lspcon_infoframe_enabled;
2384                 } else {
2385                         intel_dig_port->set_infoframes = hsw_set_infoframes;
2386                         intel_dig_port->infoframe_enabled =
2387                                                 hsw_infoframe_enabled;
2388                         intel_dig_port->write_infoframe = hsw_write_infoframe;
2389                 }
2390         } else if (HAS_PCH_IBX(dev_priv)) {
2391                 intel_dig_port->write_infoframe = ibx_write_infoframe;
2392                 intel_dig_port->set_infoframes = ibx_set_infoframes;
2393                 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
2394         } else {
2395                 intel_dig_port->write_infoframe = cpt_write_infoframe;
2396                 intel_dig_port->set_infoframes = cpt_set_infoframes;
2397                 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
2398         }
2399 }
2400
2401 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2402                                struct intel_connector *intel_connector)
2403 {
2404         struct drm_connector *connector = &intel_connector->base;
2405         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2406         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2407         struct drm_device *dev = intel_encoder->base.dev;
2408         struct drm_i915_private *dev_priv = to_i915(dev);
2409         enum port port = intel_encoder->port;
2410
2411         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2412                       port_name(port));
2413
2414         if (WARN(intel_dig_port->max_lanes < 4,
2415                  "Not enough lanes (%d) for HDMI on port %c\n",
2416                  intel_dig_port->max_lanes, port_name(port)))
2417                 return;
2418
2419         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2420                            DRM_MODE_CONNECTOR_HDMIA);
2421         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2422
2423         connector->interlace_allowed = 1;
2424         connector->doublescan_allowed = 0;
2425         connector->stereo_allowed = 1;
2426
2427         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2428                 connector->ycbcr_420_allowed = true;
2429
2430         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2431
2432         if (WARN_ON(port == PORT_A))
2433                 return;
2434         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2435
2436         if (HAS_DDI(dev_priv))
2437                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2438         else
2439                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2440
2441         intel_hdmi_add_properties(intel_hdmi, connector);
2442
2443         if (is_hdcp_supported(dev_priv, port)) {
2444                 int ret = intel_hdcp_init(intel_connector,
2445                                           &intel_hdmi_hdcp_shim);
2446                 if (ret)
2447                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
2448         }
2449
2450         intel_connector_attach_encoder(intel_connector, intel_encoder);
2451         intel_hdmi->attached_connector = intel_connector;
2452
2453         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2454          * 0xd.  Failure to do so will result in spurious interrupts being
2455          * generated on the port when a cable is not attached.
2456          */
2457         if (IS_G45(dev_priv)) {
2458                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2459                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2460         }
2461
2462         intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
2463                                                          port_identifier(port));
2464         if (!intel_hdmi->cec_notifier)
2465                 DRM_DEBUG_KMS("CEC notifier get failed\n");
2466 }
2467
2468 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2469                      i915_reg_t hdmi_reg, enum port port)
2470 {
2471         struct intel_digital_port *intel_dig_port;
2472         struct intel_encoder *intel_encoder;
2473         struct intel_connector *intel_connector;
2474
2475         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2476         if (!intel_dig_port)
2477                 return;
2478
2479         intel_connector = intel_connector_alloc();
2480         if (!intel_connector) {
2481                 kfree(intel_dig_port);
2482                 return;
2483         }
2484
2485         intel_encoder = &intel_dig_port->base;
2486
2487         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2488                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2489                          "HDMI %c", port_name(port));
2490
2491         intel_encoder->hotplug = intel_encoder_hotplug;
2492         intel_encoder->compute_config = intel_hdmi_compute_config;
2493         if (HAS_PCH_SPLIT(dev_priv)) {
2494                 intel_encoder->disable = pch_disable_hdmi;
2495                 intel_encoder->post_disable = pch_post_disable_hdmi;
2496         } else {
2497                 intel_encoder->disable = g4x_disable_hdmi;
2498         }
2499         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2500         intel_encoder->get_config = intel_hdmi_get_config;
2501         if (IS_CHERRYVIEW(dev_priv)) {
2502                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2503                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2504                 intel_encoder->enable = vlv_enable_hdmi;
2505                 intel_encoder->post_disable = chv_hdmi_post_disable;
2506                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2507         } else if (IS_VALLEYVIEW(dev_priv)) {
2508                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2509                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2510                 intel_encoder->enable = vlv_enable_hdmi;
2511                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2512         } else {
2513                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2514                 if (HAS_PCH_CPT(dev_priv))
2515                         intel_encoder->enable = cpt_enable_hdmi;
2516                 else if (HAS_PCH_IBX(dev_priv))
2517                         intel_encoder->enable = ibx_enable_hdmi;
2518                 else
2519                         intel_encoder->enable = g4x_enable_hdmi;
2520         }
2521
2522         intel_encoder->type = INTEL_OUTPUT_HDMI;
2523         intel_encoder->power_domain = intel_port_to_power_domain(port);
2524         intel_encoder->port = port;
2525         if (IS_CHERRYVIEW(dev_priv)) {
2526                 if (port == PORT_D)
2527                         intel_encoder->crtc_mask = 1 << 2;
2528                 else
2529                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2530         } else {
2531                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2532         }
2533         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2534         /*
2535          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2536          * to work on real hardware. And since g4x can send infoframes to
2537          * only one port anyway, nothing is lost by allowing it.
2538          */
2539         if (IS_G4X(dev_priv))
2540                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2541
2542         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2543         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2544         intel_dig_port->max_lanes = 4;
2545
2546         intel_infoframe_init(intel_dig_port);
2547
2548         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
2549         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2550 }