drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_scdc_helper.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include <drm/intel_lpe_audio.h>
  41 #include "i915_drv.h"
  42
  43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  44 {
  45         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  46 }
  47
  48 static void
  49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  50 {
  51         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  52         struct drm_i915_private *dev_priv = to_i915(dev);
  53         uint32_t enabled_bits;
  54
  55         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  56
  57         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  58              "HDMI port enabled, expecting disabled\n");
  59 }
  60
  61 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  62 {
  63         struct intel_digital_port *intel_dig_port =
  64                 container_of(encoder, struct intel_digital_port, base.base);
  65         return &intel_dig_port->hdmi;
  66 }
  67
  68 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  69 {
  70         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  71 }
  72
  73 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  74 {
  75         switch (type) {
  76         case HDMI_INFOFRAME_TYPE_AVI:
  77                 return VIDEO_DIP_SELECT_AVI;
  78         case HDMI_INFOFRAME_TYPE_SPD:
  79                 return VIDEO_DIP_SELECT_SPD;
  80         case HDMI_INFOFRAME_TYPE_VENDOR:
  81                 return VIDEO_DIP_SELECT_VENDOR;
  82         default:
  83                 MISSING_CASE(type);
  84                 return 0;
  85         }
  86 }
  87
  88 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  89 {
  90         switch (type) {
  91         case HDMI_INFOFRAME_TYPE_AVI:
  92                 return VIDEO_DIP_ENABLE_AVI;
  93         case HDMI_INFOFRAME_TYPE_SPD:
  94                 return VIDEO_DIP_ENABLE_SPD;
  95         case HDMI_INFOFRAME_TYPE_VENDOR:
  96                 return VIDEO_DIP_ENABLE_VENDOR;
  97         default:
  98                 MISSING_CASE(type);
  99                 return 0;
 100         }
 101 }
 102
 103 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 104 {
 105         switch (type) {
 106         case HDMI_INFOFRAME_TYPE_AVI:
 107                 return VIDEO_DIP_ENABLE_AVI_HSW;
 108         case HDMI_INFOFRAME_TYPE_SPD:
 109                 return VIDEO_DIP_ENABLE_SPD_HSW;
 110         case HDMI_INFOFRAME_TYPE_VENDOR:
 111                 return VIDEO_DIP_ENABLE_VS_HSW;
 112         default:
 113                 MISSING_CASE(type);
 114                 return 0;
 115         }
 116 }
 117
 118 static i915_reg_t
 119 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 120                  enum transcoder cpu_transcoder,
 121                  enum hdmi_infoframe_type type,
 122                  int i)
 123 {
 124         switch (type) {
 125         case HDMI_INFOFRAME_TYPE_AVI:
 126                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 127         case HDMI_INFOFRAME_TYPE_SPD:
 128                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 129         case HDMI_INFOFRAME_TYPE_VENDOR:
 130                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 131         default:
 132                 MISSING_CASE(type);
 133                 return INVALID_MMIO_REG;
 134         }
 135 }
 136
 137 static void g4x_write_infoframe(struct drm_encoder *encoder,
 138                                 const struct intel_crtc_state *crtc_state,
 139                                 enum hdmi_infoframe_type type,
 140                                 const void *frame, ssize_t len)
 141 {
 142         const uint32_t *data = frame;
 143         struct drm_device *dev = encoder->dev;
 144         struct drm_i915_private *dev_priv = to_i915(dev);
 145         u32 val = I915_READ(VIDEO_DIP_CTL);
 146         int i;
 147
 148         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 149
 150         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 151         val |= g4x_infoframe_index(type);
 152
 153         val &= ~g4x_infoframe_enable(type);
 154
 155         I915_WRITE(VIDEO_DIP_CTL, val);
 156
 157         mmiowb();
 158         for (i = 0; i < len; i += 4) {
 159                 I915_WRITE(VIDEO_DIP_DATA, *data);
 160                 data++;
 161         }
 162         /* Write every possible data byte to force correct ECC calculation. */
 163         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 164                 I915_WRITE(VIDEO_DIP_DATA, 0);
 165         mmiowb();
 166
 167         val |= g4x_infoframe_enable(type);
 168         val &= ~VIDEO_DIP_FREQ_MASK;
 169         val |= VIDEO_DIP_FREQ_VSYNC;
 170
 171         I915_WRITE(VIDEO_DIP_CTL, val);
 172         POSTING_READ(VIDEO_DIP_CTL);
 173 }
 174
 175 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
 176                                   const struct intel_crtc_state *pipe_config)
 177 {
 178         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 179         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 180         u32 val = I915_READ(VIDEO_DIP_CTL);
 181
 182         if ((val & VIDEO_DIP_ENABLE) == 0)
 183                 return false;
 184
 185         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 186                 return false;
 187
 188         return val & (VIDEO_DIP_ENABLE_AVI |
 189                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 190 }
 191
 192 static void ibx_write_infoframe(struct drm_encoder *encoder,
 193                                 const struct intel_crtc_state *crtc_state,
 194                                 enum hdmi_infoframe_type type,
 195                                 const void *frame, ssize_t len)
 196 {
 197         const uint32_t *data = frame;
 198         struct drm_device *dev = encoder->dev;
 199         struct drm_i915_private *dev_priv = to_i915(dev);
 200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 201         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 202         u32 val = I915_READ(reg);
 203         int i;
 204
 205         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 206
 207         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 208         val |= g4x_infoframe_index(type);
 209
 210         val &= ~g4x_infoframe_enable(type);
 211
 212         I915_WRITE(reg, val);
 213
 214         mmiowb();
 215         for (i = 0; i < len; i += 4) {
 216                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 217                 data++;
 218         }
 219         /* Write every possible data byte to force correct ECC calculation. */
 220         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 221                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 222         mmiowb();
 223
 224         val |= g4x_infoframe_enable(type);
 225         val &= ~VIDEO_DIP_FREQ_MASK;
 226         val |= VIDEO_DIP_FREQ_VSYNC;
 227
 228         I915_WRITE(reg, val);
 229         POSTING_READ(reg);
 230 }
 231
 232 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
 233                                   const struct intel_crtc_state *pipe_config)
 234 {
 235         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 236         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 237         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 238         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 239         u32 val = I915_READ(reg);
 240
 241         if ((val & VIDEO_DIP_ENABLE) == 0)
 242                 return false;
 243
 244         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 245                 return false;
 246
 247         return val & (VIDEO_DIP_ENABLE_AVI |
 248                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 249                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 250 }
 251
 252 static void cpt_write_infoframe(struct drm_encoder *encoder,
 253                                 const struct intel_crtc_state *crtc_state,
 254                                 enum hdmi_infoframe_type type,
 255                                 const void *frame, ssize_t len)
 256 {
 257         const uint32_t *data = frame;
 258         struct drm_device *dev = encoder->dev;
 259         struct drm_i915_private *dev_priv = to_i915(dev);
 260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 261         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 262         u32 val = I915_READ(reg);
 263         int i;
 264
 265         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 266
 267         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 268         val |= g4x_infoframe_index(type);
 269
 270         /* The DIP control register spec says that we need to update the AVI
 271          * infoframe without clearing its enable bit */
 272         if (type != HDMI_INFOFRAME_TYPE_AVI)
 273                 val &= ~g4x_infoframe_enable(type);
 274
 275         I915_WRITE(reg, val);
 276
 277         mmiowb();
 278         for (i = 0; i < len; i += 4) {
 279                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 280                 data++;
 281         }
 282         /* Write every possible data byte to force correct ECC calculation. */
 283         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 284                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 285         mmiowb();
 286
 287         val |= g4x_infoframe_enable(type);
 288         val &= ~VIDEO_DIP_FREQ_MASK;
 289         val |= VIDEO_DIP_FREQ_VSYNC;
 290
 291         I915_WRITE(reg, val);
 292         POSTING_READ(reg);
 293 }
 294
 295 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
 296                                   const struct intel_crtc_state *pipe_config)
 297 {
 298         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 299         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 300         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 301
 302         if ((val & VIDEO_DIP_ENABLE) == 0)
 303                 return false;
 304
 305         return val & (VIDEO_DIP_ENABLE_AVI |
 306                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 307                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 308 }
 309
 310 static void vlv_write_infoframe(struct drm_encoder *encoder,
 311                                 const struct intel_crtc_state *crtc_state,
 312                                 enum hdmi_infoframe_type type,
 313                                 const void *frame, ssize_t len)
 314 {
 315         const uint32_t *data = frame;
 316         struct drm_device *dev = encoder->dev;
 317         struct drm_i915_private *dev_priv = to_i915(dev);
 318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 319         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 320         u32 val = I915_READ(reg);
 321         int i;
 322
 323         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 324
 325         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 326         val |= g4x_infoframe_index(type);
 327
 328         val &= ~g4x_infoframe_enable(type);
 329
 330         I915_WRITE(reg, val);
 331
 332         mmiowb();
 333         for (i = 0; i < len; i += 4) {
 334                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 335                 data++;
 336         }
 337         /* Write every possible data byte to force correct ECC calculation. */
 338         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 339                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 340         mmiowb();
 341
 342         val |= g4x_infoframe_enable(type);
 343         val &= ~VIDEO_DIP_FREQ_MASK;
 344         val |= VIDEO_DIP_FREQ_VSYNC;
 345
 346         I915_WRITE(reg, val);
 347         POSTING_READ(reg);
 348 }
 349
 350 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
 351                                   const struct intel_crtc_state *pipe_config)
 352 {
 353         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 354         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 355         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 356         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 357
 358         if ((val & VIDEO_DIP_ENABLE) == 0)
 359                 return false;
 360
 361         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 362                 return false;
 363
 364         return val & (VIDEO_DIP_ENABLE_AVI |
 365                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 366                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 367 }
 368
 369 static void hsw_write_infoframe(struct drm_encoder *encoder,
 370                                 const struct intel_crtc_state *crtc_state,
 371                                 enum hdmi_infoframe_type type,
 372                                 const void *frame, ssize_t len)
 373 {
 374         const uint32_t *data = frame;
 375         struct drm_device *dev = encoder->dev;
 376         struct drm_i915_private *dev_priv = to_i915(dev);
 377         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 378         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 379         i915_reg_t data_reg;
 380         int i;
 381         u32 val = I915_READ(ctl_reg);
 382
 383         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
 384
 385         val &= ~hsw_infoframe_enable(type);
 386         I915_WRITE(ctl_reg, val);
 387
 388         mmiowb();
 389         for (i = 0; i < len; i += 4) {
 390                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 391                                             type, i >> 2), *data);
 392                 data++;
 393         }
 394         /* Write every possible data byte to force correct ECC calculation. */
 395         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 396                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 397                                             type, i >> 2), 0);
 398         mmiowb();
 399
 400         val |= hsw_infoframe_enable(type);
 401         I915_WRITE(ctl_reg, val);
 402         POSTING_READ(ctl_reg);
 403 }
 404
 405 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
 406                                   const struct intel_crtc_state *pipe_config)
 407 {
 408         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 409         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 410
 411         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 412                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 413                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 414 }
 415
 416 /*
 417  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 418  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 419  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 420  * used for both technologies.
 421  *
 422  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 423  * DW1:       DB3       | DB2 | DB1 | DB0
 424  * DW2:       DB7       | DB6 | DB5 | DB4
 425  * DW3: ...
 426  *
 427  * (HB is Header Byte, DB is Data Byte)
 428  *
 429  * The hdmi pack() functions don't know about that hardware specific hole so we
 430  * trick them by giving an offset into the buffer and moving back the header
 431  * bytes by one.
 432  */
 433 static void intel_write_infoframe(struct drm_encoder *encoder,
 434                                   const struct intel_crtc_state *crtc_state,
 435                                   union hdmi_infoframe *frame)
 436 {
 437         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 438         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 439         ssize_t len;
 440
 441         /* see comment above for the reason for this offset */
 442         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 443         if (len < 0)
 444                 return;
 445
 446         /* Insert the 'hole' (see big comment above) at position 3 */
 447         buffer[0] = buffer[1];
 448         buffer[1] = buffer[2];
 449         buffer[2] = buffer[3];
 450         buffer[3] = 0;
 451         len++;
 452
 453         intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
 454 }
 455
 456 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 457                                          const struct intel_crtc_state *crtc_state)
 458 {
 459         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 460         const struct drm_display_mode *adjusted_mode =
 461                 &crtc_state->base.adjusted_mode;
 462         struct drm_connector *connector = &intel_hdmi->attached_connector->base;
 463         bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
 464         union hdmi_infoframe frame;
 465         int ret;
 466
 467         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 468                                                        adjusted_mode,
 469                                                        is_hdmi2_sink);
 470         if (ret < 0) {
 471                 DRM_ERROR("couldn't fill AVI infoframe\n");
 472                 return;
 473         }
 474
 475         if (crtc_state->ycbcr420)
 476                 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
 477         else
 478                 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 479
 480         drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
 481                                            crtc_state->limited_color_range ?
 482                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 483                                            HDMI_QUANTIZATION_RANGE_FULL,
 484                                            intel_hdmi->rgb_quant_range_selectable,
 485                                            is_hdmi2_sink);
 486
 487         /* TODO: handle pixel repetition for YCBCR420 outputs */
 488         intel_write_infoframe(encoder, crtc_state, &frame);
 489 }
 490
 491 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
 492                                          const struct intel_crtc_state *crtc_state)
 493 {
 494         union hdmi_infoframe frame;
 495         int ret;
 496
 497         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 498         if (ret < 0) {
 499                 DRM_ERROR("couldn't fill SPD infoframe\n");
 500                 return;
 501         }
 502
 503         frame.spd.sdi = HDMI_SPD_SDI_PC;
 504
 505         intel_write_infoframe(encoder, crtc_state, &frame);
 506 }
 507
 508 static void
 509 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 510                               const struct intel_crtc_state *crtc_state)
 511 {
 512         union hdmi_infoframe frame;
 513         int ret;
 514
 515         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 516                                                           &crtc_state->base.adjusted_mode);
 517         if (ret < 0)
 518                 return;
 519
 520         intel_write_infoframe(encoder, crtc_state, &frame);
 521 }
 522
 523 static void g4x_set_infoframes(struct drm_encoder *encoder,
 524                                bool enable,
 525                                const struct intel_crtc_state *crtc_state,
 526                                const struct drm_connector_state *conn_state)
 527 {
 528         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 529         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 530         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 531         i915_reg_t reg = VIDEO_DIP_CTL;
 532         u32 val = I915_READ(reg);
 533         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 534
 535         assert_hdmi_port_disabled(intel_hdmi);
 536
 537         /* If the registers were not initialized yet, they might be zeroes,
 538          * which means we're selecting the AVI DIP and we're setting its
 539          * frequency to once. This seems to really confuse the HW and make
 540          * things stop working (the register spec says the AVI always needs to
 541          * be sent every VSync). So here we avoid writing to the register more
 542          * than we need and also explicitly select the AVI DIP and explicitly
 543          * set its frequency to every VSync. Avoiding to write it twice seems to
 544          * be enough to solve the problem, but being defensive shouldn't hurt us
 545          * either. */
 546         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 547
 548         if (!enable) {
 549                 if (!(val & VIDEO_DIP_ENABLE))
 550                         return;
 551                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 552                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 553                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 554                         return;
 555                 }
 556                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 557                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 558                 I915_WRITE(reg, val);
 559                 POSTING_READ(reg);
 560                 return;
 561         }
 562
 563         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 564                 if (val & VIDEO_DIP_ENABLE) {
 565                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 566                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 567                         return;
 568                 }
 569                 val &= ~VIDEO_DIP_PORT_MASK;
 570                 val |= port;
 571         }
 572
 573         val |= VIDEO_DIP_ENABLE;
 574         val &= ~(VIDEO_DIP_ENABLE_AVI |
 575                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 576
 577         I915_WRITE(reg, val);
 578         POSTING_READ(reg);
 579
 580         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 581         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 582         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 583 }
 584
 585 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
 586 {
 587         struct drm_connector *connector = conn_state->connector;
 588
 589         /*
 590          * HDMI cloning is only supported on g4x which doesn't
 591          * support deep color or GCP infoframes anyway so no
 592          * need to worry about multiple HDMI sinks here.
 593          */
 594
 595         return connector->display_info.bpc > 8;
 596 }
 597
 598 /*
 599  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 600  *
 601  * From HDMI specification 1.4a:
 602  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 603  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 604  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 605  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 606  *   phase of 0
 607  */
 608 static bool gcp_default_phase_possible(int pipe_bpp,
 609                                        const struct drm_display_mode *mode)
 610 {
 611         unsigned int pixels_per_group;
 612
 613         switch (pipe_bpp) {
 614         case 30:
 615                 /* 4 pixels in 5 clocks */
 616                 pixels_per_group = 4;
 617                 break;
 618         case 36:
 619                 /* 2 pixels in 3 clocks */
 620                 pixels_per_group = 2;
 621                 break;
 622         case 48:
 623                 /* 1 pixel in 2 clocks */
 624                 pixels_per_group = 1;
 625                 break;
 626         default:
 627                 /* phase information not relevant for 8bpc */
 628                 return false;
 629         }
 630
 631         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 632                 mode->crtc_htotal % pixels_per_group == 0 &&
 633                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 634                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 635                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 636                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 637                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 638                  mode->crtc_htotal/2 % pixels_per_group == 0);
 639 }
 640
 641 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
 642                                          const struct intel_crtc_state *crtc_state,
 643                                          const struct drm_connector_state *conn_state)
 644 {
 645         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 646         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 647         i915_reg_t reg;
 648         u32 val = 0;
 649
 650         if (HAS_DDI(dev_priv))
 651                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 652         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 653                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 654         else if (HAS_PCH_SPLIT(dev_priv))
 655                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 656         else
 657                 return false;
 658
 659         /* Indicate color depth whenever the sink supports deep color */
 660         if (hdmi_sink_is_deep_color(conn_state))
 661                 val |= GCP_COLOR_INDICATION;
 662
 663         /* Enable default_phase whenever the display mode is suitably aligned */
 664         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
 665                                        &crtc_state->base.adjusted_mode))
 666                 val |= GCP_DEFAULT_PHASE_ENABLE;
 667
 668         I915_WRITE(reg, val);
 669
 670         return val != 0;
 671 }
 672
 673 static void ibx_set_infoframes(struct drm_encoder *encoder,
 674                                bool enable,
 675                                const struct intel_crtc_state *crtc_state,
 676                                const struct drm_connector_state *conn_state)
 677 {
 678         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 680         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 681         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 682         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 683         u32 val = I915_READ(reg);
 684         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 685
 686         assert_hdmi_port_disabled(intel_hdmi);
 687
 688         /* See the big comment in g4x_set_infoframes() */
 689         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 690
 691         if (!enable) {
 692                 if (!(val & VIDEO_DIP_ENABLE))
 693                         return;
 694                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 695                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 696                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 697                 I915_WRITE(reg, val);
 698                 POSTING_READ(reg);
 699                 return;
 700         }
 701
 702         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 703                 WARN(val & VIDEO_DIP_ENABLE,
 704                      "DIP already enabled on port %c\n",
 705                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 706                 val &= ~VIDEO_DIP_PORT_MASK;
 707                 val |= port;
 708         }
 709
 710         val |= VIDEO_DIP_ENABLE;
 711         val &= ~(VIDEO_DIP_ENABLE_AVI |
 712                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 713                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 714
 715         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 716                 val |= VIDEO_DIP_ENABLE_GCP;
 717
 718         I915_WRITE(reg, val);
 719         POSTING_READ(reg);
 720
 721         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 722         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 723         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 724 }
 725
 726 static void cpt_set_infoframes(struct drm_encoder *encoder,
 727                                bool enable,
 728                                const struct intel_crtc_state *crtc_state,
 729                                const struct drm_connector_state *conn_state)
 730 {
 731         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 733         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 734         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 735         u32 val = I915_READ(reg);
 736
 737         assert_hdmi_port_disabled(intel_hdmi);
 738
 739         /* See the big comment in g4x_set_infoframes() */
 740         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 741
 742         if (!enable) {
 743                 if (!(val & VIDEO_DIP_ENABLE))
 744                         return;
 745                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 746                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 747                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 748                 I915_WRITE(reg, val);
 749                 POSTING_READ(reg);
 750                 return;
 751         }
 752
 753         /* Set both together, unset both together: see the spec. */
 754         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 755         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 756                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 757
 758         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 759                 val |= VIDEO_DIP_ENABLE_GCP;
 760
 761         I915_WRITE(reg, val);
 762         POSTING_READ(reg);
 763
 764         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 765         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 766         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 767 }
 768
 769 static void vlv_set_infoframes(struct drm_encoder *encoder,
 770                                bool enable,
 771                                const struct intel_crtc_state *crtc_state,
 772                                const struct drm_connector_state *conn_state)
 773 {
 774         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 775         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 777         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 778         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 779         u32 val = I915_READ(reg);
 780         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 781
 782         assert_hdmi_port_disabled(intel_hdmi);
 783
 784         /* See the big comment in g4x_set_infoframes() */
 785         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 786
 787         if (!enable) {
 788                 if (!(val & VIDEO_DIP_ENABLE))
 789                         return;
 790                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 791                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 792                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 793                 I915_WRITE(reg, val);
 794                 POSTING_READ(reg);
 795                 return;
 796         }
 797
 798         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 799                 WARN(val & VIDEO_DIP_ENABLE,
 800                      "DIP already enabled on port %c\n",
 801                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 802                 val &= ~VIDEO_DIP_PORT_MASK;
 803                 val |= port;
 804         }
 805
 806         val |= VIDEO_DIP_ENABLE;
 807         val &= ~(VIDEO_DIP_ENABLE_AVI |
 808                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 809                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 810
 811         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 812                 val |= VIDEO_DIP_ENABLE_GCP;
 813
 814         I915_WRITE(reg, val);
 815         POSTING_READ(reg);
 816
 817         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 818         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 819         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 820 }
 821
 822 static void hsw_set_infoframes(struct drm_encoder *encoder,
 823                                bool enable,
 824                                const struct intel_crtc_state *crtc_state,
 825                                const struct drm_connector_state *conn_state)
 826 {
 827         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 828         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 829         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
 830         u32 val = I915_READ(reg);
 831
 832         assert_hdmi_port_disabled(intel_hdmi);
 833
 834         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 835                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 836                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 837
 838         if (!enable) {
 839                 I915_WRITE(reg, val);
 840                 POSTING_READ(reg);
 841                 return;
 842         }
 843
 844         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 845                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 846
 847         I915_WRITE(reg, val);
 848         POSTING_READ(reg);
 849
 850         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 851         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 852         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 853 }
 854
 855 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
 856 {
 857         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
 858         struct i2c_adapter *adapter =
 859                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
 860
 861         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
 862                 return;
 863
 864         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
 865                       enable ? "Enabling" : "Disabling");
 866
 867         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
 868                                          adapter, enable);
 869 }
 870
 871 static void intel_hdmi_prepare(struct intel_encoder *encoder,
 872                                const struct intel_crtc_state *crtc_state)
 873 {
 874         struct drm_device *dev = encoder->base.dev;
 875         struct drm_i915_private *dev_priv = to_i915(dev);
 876         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 877         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 878         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 879         u32 hdmi_val;
 880
 881         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
 882
 883         hdmi_val = SDVO_ENCODING_HDMI;
 884         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
 885                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
 886         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 887                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 888         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 889                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 890
 891         if (crtc_state->pipe_bpp > 24)
 892                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 893         else
 894                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 895
 896         if (crtc_state->has_hdmi_sink)
 897                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 898
 899         if (HAS_PCH_CPT(dev_priv))
 900                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 901         else if (IS_CHERRYVIEW(dev_priv))
 902                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 903         else
 904                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 905
 906         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 907         POSTING_READ(intel_hdmi->hdmi_reg);
 908 }
 909
 910 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 911                                     enum pipe *pipe)
 912 {
 913         struct drm_device *dev = encoder->base.dev;
 914         struct drm_i915_private *dev_priv = to_i915(dev);
 915         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 916         u32 tmp;
 917         bool ret;
 918
 919         if (!intel_display_power_get_if_enabled(dev_priv,
 920                                                 encoder->power_domain))
 921                 return false;
 922
 923         ret = false;
 924
 925         tmp = I915_READ(intel_hdmi->hdmi_reg);
 926
 927         if (!(tmp & SDVO_ENABLE))
 928                 goto out;
 929
 930         if (HAS_PCH_CPT(dev_priv))
 931                 *pipe = PORT_TO_PIPE_CPT(tmp);
 932         else if (IS_CHERRYVIEW(dev_priv))
 933                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 934         else
 935                 *pipe = PORT_TO_PIPE(tmp);
 936
 937         ret = true;
 938
 939 out:
 940         intel_display_power_put(dev_priv, encoder->power_domain);
 941
 942         return ret;
 943 }
 944
 945 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 946                                   struct intel_crtc_state *pipe_config)
 947 {
 948         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 949         struct drm_device *dev = encoder->base.dev;
 950         struct drm_i915_private *dev_priv = to_i915(dev);
 951         u32 tmp, flags = 0;
 952         int dotclock;
 953
 954         tmp = I915_READ(intel_hdmi->hdmi_reg);
 955
 956         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 957                 flags |= DRM_MODE_FLAG_PHSYNC;
 958         else
 959                 flags |= DRM_MODE_FLAG_NHSYNC;
 960
 961         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 962                 flags |= DRM_MODE_FLAG_PVSYNC;
 963         else
 964                 flags |= DRM_MODE_FLAG_NVSYNC;
 965
 966         if (tmp & HDMI_MODE_SELECT_HDMI)
 967                 pipe_config->has_hdmi_sink = true;
 968
 969         if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
 970                 pipe_config->has_infoframe = true;
 971
 972         if (tmp & SDVO_AUDIO_ENABLE)
 973                 pipe_config->has_audio = true;
 974
 975         if (!HAS_PCH_SPLIT(dev_priv) &&
 976             tmp & HDMI_COLOR_RANGE_16_235)
 977                 pipe_config->limited_color_range = true;
 978
 979         pipe_config->base.adjusted_mode.flags |= flags;
 980
 981         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 982                 dotclock = pipe_config->port_clock * 2 / 3;
 983         else
 984                 dotclock = pipe_config->port_clock;
 985
 986         if (pipe_config->pixel_multiplier)
 987                 dotclock /= pipe_config->pixel_multiplier;
 988
 989         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 990
 991         pipe_config->lane_count = 4;
 992 }
 993
 994 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
 995                                     struct intel_crtc_state *pipe_config,
 996                                     struct drm_connector_state *conn_state)
 997 {
 998         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 999
1000         WARN_ON(!pipe_config->has_hdmi_sink);
1001         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1002                          pipe_name(crtc->pipe));
1003         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1004 }
1005
1006 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1007                             struct intel_crtc_state *pipe_config,
1008                             struct drm_connector_state *conn_state)
1009 {
1010         struct drm_device *dev = encoder->base.dev;
1011         struct drm_i915_private *dev_priv = to_i915(dev);
1012         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1013         u32 temp;
1014
1015         temp = I915_READ(intel_hdmi->hdmi_reg);
1016
1017         temp |= SDVO_ENABLE;
1018         if (pipe_config->has_audio)
1019                 temp |= SDVO_AUDIO_ENABLE;
1020
1021         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1022         POSTING_READ(intel_hdmi->hdmi_reg);
1023
1024         if (pipe_config->has_audio)
1025                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1026 }
1027
1028 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1029                             struct intel_crtc_state *pipe_config,
1030                             struct drm_connector_state *conn_state)
1031 {
1032         struct drm_device *dev = encoder->base.dev;
1033         struct drm_i915_private *dev_priv = to_i915(dev);
1034         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1035         u32 temp;
1036
1037         temp = I915_READ(intel_hdmi->hdmi_reg);
1038
1039         temp |= SDVO_ENABLE;
1040         if (pipe_config->has_audio)
1041                 temp |= SDVO_AUDIO_ENABLE;
1042
1043         /*
1044          * HW workaround, need to write this twice for issue
1045          * that may result in first write getting masked.
1046          */
1047         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1048         POSTING_READ(intel_hdmi->hdmi_reg);
1049         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1050         POSTING_READ(intel_hdmi->hdmi_reg);
1051
1052         /*
1053          * HW workaround, need to toggle enable bit off and on
1054          * for 12bpc with pixel repeat.
1055          *
1056          * FIXME: BSpec says this should be done at the end of
1057          * of the modeset sequence, so not sure if this isn't too soon.
1058          */
1059         if (pipe_config->pipe_bpp > 24 &&
1060             pipe_config->pixel_multiplier > 1) {
1061                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1062                 POSTING_READ(intel_hdmi->hdmi_reg);
1063
1064                 /*
1065                  * HW workaround, need to write this twice for issue
1066                  * that may result in first write getting masked.
1067                  */
1068                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1069                 POSTING_READ(intel_hdmi->hdmi_reg);
1070                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1071                 POSTING_READ(intel_hdmi->hdmi_reg);
1072         }
1073
1074         if (pipe_config->has_audio)
1075                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1076 }
1077
1078 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1079                             struct intel_crtc_state *pipe_config,
1080                             struct drm_connector_state *conn_state)
1081 {
1082         struct drm_device *dev = encoder->base.dev;
1083         struct drm_i915_private *dev_priv = to_i915(dev);
1084         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1085         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1086         enum pipe pipe = crtc->pipe;
1087         u32 temp;
1088
1089         temp = I915_READ(intel_hdmi->hdmi_reg);
1090
1091         temp |= SDVO_ENABLE;
1092         if (pipe_config->has_audio)
1093                 temp |= SDVO_AUDIO_ENABLE;
1094
1095         /*
1096          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1097          *
1098          * The procedure for 12bpc is as follows:
1099          * 1. disable HDMI clock gating
1100          * 2. enable HDMI with 8bpc
1101          * 3. enable HDMI with 12bpc
1102          * 4. enable HDMI clock gating
1103          */
1104
1105         if (pipe_config->pipe_bpp > 24) {
1106                 I915_WRITE(TRANS_CHICKEN1(pipe),
1107                            I915_READ(TRANS_CHICKEN1(pipe)) |
1108                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1109
1110                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1111                 temp |= SDVO_COLOR_FORMAT_8bpc;
1112         }
1113
1114         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1115         POSTING_READ(intel_hdmi->hdmi_reg);
1116
1117         if (pipe_config->pipe_bpp > 24) {
1118                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1119                 temp |= HDMI_COLOR_FORMAT_12bpc;
1120
1121                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1122                 POSTING_READ(intel_hdmi->hdmi_reg);
1123
1124                 I915_WRITE(TRANS_CHICKEN1(pipe),
1125                            I915_READ(TRANS_CHICKEN1(pipe)) &
1126                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1127         }
1128
1129         if (pipe_config->has_audio)
1130                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1131 }
1132
1133 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1134                             struct intel_crtc_state *pipe_config,
1135                             struct drm_connector_state *conn_state)
1136 {
1137 }
1138
1139 static void intel_disable_hdmi(struct intel_encoder *encoder,
1140                                struct intel_crtc_state *old_crtc_state,
1141                                struct drm_connector_state *old_conn_state)
1142 {
1143         struct drm_device *dev = encoder->base.dev;
1144         struct drm_i915_private *dev_priv = to_i915(dev);
1145         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1146         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1147         u32 temp;
1148
1149         temp = I915_READ(intel_hdmi->hdmi_reg);
1150
1151         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1152         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1153         POSTING_READ(intel_hdmi->hdmi_reg);
1154
1155         /*
1156          * HW workaround for IBX, we need to move the port
1157          * to transcoder A after disabling it to allow the
1158          * matching DP port to be enabled on transcoder A.
1159          */
1160         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1161                 /*
1162                  * We get CPU/PCH FIFO underruns on the other pipe when
1163                  * doing the workaround. Sweep them under the rug.
1164                  */
1165                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1166                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1167
1168                 temp &= ~SDVO_PIPE_B_SELECT;
1169                 temp |= SDVO_ENABLE;
1170                 /*
1171                  * HW workaround, need to write this twice for issue
1172                  * that may result in first write getting masked.
1173                  */
1174                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1175                 POSTING_READ(intel_hdmi->hdmi_reg);
1176                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1177                 POSTING_READ(intel_hdmi->hdmi_reg);
1178
1179                 temp &= ~SDVO_ENABLE;
1180                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1181                 POSTING_READ(intel_hdmi->hdmi_reg);
1182
1183                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1184                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1185                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1186         }
1187
1188         intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state);
1189
1190         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1191 }
1192
1193 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1194                              struct intel_crtc_state *old_crtc_state,
1195                              struct drm_connector_state *old_conn_state)
1196 {
1197         if (old_crtc_state->has_audio)
1198                 intel_audio_codec_disable(encoder);
1199
1200         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1201 }
1202
1203 static void pch_disable_hdmi(struct intel_encoder *encoder,
1204                              struct intel_crtc_state *old_crtc_state,
1205                              struct drm_connector_state *old_conn_state)
1206 {
1207         if (old_crtc_state->has_audio)
1208                 intel_audio_codec_disable(encoder);
1209 }
1210
1211 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1212                                   struct intel_crtc_state *old_crtc_state,
1213                                   struct drm_connector_state *old_conn_state)
1214 {
1215         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1216 }
1217
1218 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1219 {
1220         if (IS_G4X(dev_priv))
1221                 return 165000;
1222         else if (IS_GEMINILAKE(dev_priv))
1223                 return 594000;
1224         else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1225                 return 300000;
1226         else
1227                 return 225000;
1228 }
1229
1230 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1231                                  bool respect_downstream_limits,
1232                                  bool force_dvi)
1233 {
1234         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1235         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1236
1237         if (respect_downstream_limits) {
1238                 struct intel_connector *connector = hdmi->attached_connector;
1239                 const struct drm_display_info *info = &connector->base.display_info;
1240
1241                 if (hdmi->dp_dual_mode.max_tmds_clock)
1242                         max_tmds_clock = min(max_tmds_clock,
1243                                              hdmi->dp_dual_mode.max_tmds_clock);
1244
1245                 if (info->max_tmds_clock)
1246                         max_tmds_clock = min(max_tmds_clock,
1247                                              info->max_tmds_clock);
1248                 else if (!hdmi->has_hdmi_sink || force_dvi)
1249                         max_tmds_clock = min(max_tmds_clock, 165000);
1250         }
1251
1252         return max_tmds_clock;
1253 }
1254
1255 static enum drm_mode_status
1256 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1257                       int clock, bool respect_downstream_limits,
1258                       bool force_dvi)
1259 {
1260         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1261
1262         if (clock < 25000)
1263                 return MODE_CLOCK_LOW;
1264         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1265                 return MODE_CLOCK_HIGH;
1266
1267         /* BXT DPLL can't generate 223-240 MHz */
1268         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1269                 return MODE_CLOCK_RANGE;
1270
1271         /* CHV DPLL can't generate 216-240 MHz */
1272         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1273                 return MODE_CLOCK_RANGE;
1274
1275         return MODE_OK;
1276 }
1277
1278 static enum drm_mode_status
1279 intel_hdmi_mode_valid(struct drm_connector *connector,
1280                       struct drm_display_mode *mode)
1281 {
1282         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1283         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1284         struct drm_i915_private *dev_priv = to_i915(dev);
1285         enum drm_mode_status status;
1286         int clock;
1287         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1288         bool force_dvi =
1289                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1290
1291         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1292                 return MODE_NO_DBLESCAN;
1293
1294         clock = mode->clock;
1295
1296         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1297                 clock *= 2;
1298
1299         if (clock > max_dotclk)
1300                 return MODE_CLOCK_HIGH;
1301
1302         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1303                 clock *= 2;
1304
1305         if (drm_mode_is_420_only(&connector->display_info, mode))
1306                 clock /= 2;
1307
1308         /* check if we can do 8bpc */
1309         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1310
1311         /* if we can't do 8bpc we may still be able to do 12bpc */
1312         if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi)
1313                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi);
1314
1315         return status;
1316 }
1317
1318 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1319 {
1320         struct drm_i915_private *dev_priv =
1321                 to_i915(crtc_state->base.crtc->dev);
1322         struct drm_atomic_state *state = crtc_state->base.state;
1323         struct drm_connector_state *connector_state;
1324         struct drm_connector *connector;
1325         int i;
1326
1327         if (HAS_GMCH_DISPLAY(dev_priv))
1328                 return false;
1329
1330         /*
1331          * HDMI 12bpc affects the clocks, so it's only possible
1332          * when not cloning with other encoder types.
1333          */
1334         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1335                 return false;
1336
1337         for_each_new_connector_in_state(state, connector, connector_state, i) {
1338                 const struct drm_display_info *info = &connector->display_info;
1339
1340                 if (connector_state->crtc != crtc_state->base.crtc)
1341                         continue;
1342
1343                 if (crtc_state->ycbcr420) {
1344                         const struct drm_hdmi_info *hdmi = &info->hdmi;
1345
1346                         if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
1347                                 return false;
1348                 } else {
1349                         if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36))
1350                                 return false;
1351                 }
1352         }
1353
1354         /* Display Wa #1139 */
1355         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1356             crtc_state->base.adjusted_mode.htotal > 5460)
1357                 return false;
1358
1359         return true;
1360 }
1361
1362 static bool
1363 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1364                            struct intel_crtc_state *config,
1365                            int *clock_12bpc, int *clock_8bpc)
1366 {
1367         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1368
1369         if (!connector->ycbcr_420_allowed) {
1370                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1371                 return false;
1372         }
1373
1374         /* YCBCR420 TMDS rate requirement is half the pixel clock */
1375         config->port_clock /= 2;
1376         *clock_12bpc /= 2;
1377         *clock_8bpc /= 2;
1378         config->ycbcr420 = true;
1379
1380         /* YCBCR 420 output conversion needs a scaler */
1381         if (skl_update_scaler_crtc(config)) {
1382                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1383                 return false;
1384         }
1385
1386         intel_pch_panel_fitting(intel_crtc, config,
1387                                 DRM_MODE_SCALE_FULLSCREEN);
1388
1389         return true;
1390 }
1391
1392 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1393                                struct intel_crtc_state *pipe_config,
1394                                struct drm_connector_state *conn_state)
1395 {
1396         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1397         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1398         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1399         struct drm_connector *connector = conn_state->connector;
1400         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1401         struct intel_digital_connector_state *intel_conn_state =
1402                 to_intel_digital_connector_state(conn_state);
1403         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1404         int clock_12bpc = clock_8bpc * 3 / 2;
1405         int desired_bpp;
1406         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1407
1408         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1409
1410         if (pipe_config->has_hdmi_sink)
1411                 pipe_config->has_infoframe = true;
1412
1413         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1414                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1415                 pipe_config->limited_color_range =
1416                         pipe_config->has_hdmi_sink &&
1417                         drm_default_rgb_quant_range(adjusted_mode) ==
1418                         HDMI_QUANTIZATION_RANGE_LIMITED;
1419         } else {
1420                 pipe_config->limited_color_range =
1421                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1422         }
1423
1424         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1425                 pipe_config->pixel_multiplier = 2;
1426                 clock_8bpc *= 2;
1427                 clock_12bpc *= 2;
1428         }
1429
1430         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1431                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1432                                                 &clock_12bpc, &clock_8bpc)) {
1433                         DRM_ERROR("Can't support YCBCR420 output\n");
1434                         return false;
1435                 }
1436         }
1437
1438         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1439                 pipe_config->has_pch_encoder = true;
1440
1441         if (pipe_config->has_hdmi_sink) {
1442                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1443                         pipe_config->has_audio = intel_hdmi->has_audio;
1444                 else
1445                         pipe_config->has_audio =
1446                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1447         }
1448
1449         /*
1450          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1451          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1452          * outputs. We also need to check that the higher clock still fits
1453          * within limits.
1454          */
1455         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && !force_dvi &&
1456             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK &&
1457             hdmi_12bpc_possible(pipe_config)) {
1458                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1459                 desired_bpp = 12*3;
1460
1461                 /* Need to adjust the port link by 1.5x for 12bpc. */
1462                 pipe_config->port_clock = clock_12bpc;
1463         } else {
1464                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1465                 desired_bpp = 8*3;
1466
1467                 pipe_config->port_clock = clock_8bpc;
1468         }
1469
1470         if (!pipe_config->bw_constrained) {
1471                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1472                 pipe_config->pipe_bpp = desired_bpp;
1473         }
1474
1475         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1476                                   false, force_dvi) != MODE_OK) {
1477                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1478                 return false;
1479         }
1480
1481         /* Set user selected PAR to incoming mode's member */
1482         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1483
1484         pipe_config->lane_count = 4;
1485
1486         if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) {
1487                 if (scdc->scrambling.low_rates)
1488                         pipe_config->hdmi_scrambling = true;
1489
1490                 if (pipe_config->port_clock > 340000) {
1491                         pipe_config->hdmi_scrambling = true;
1492                         pipe_config->hdmi_high_tmds_clock_ratio = true;
1493                 }
1494         }
1495
1496         return true;
1497 }
1498
1499 static void
1500 intel_hdmi_unset_edid(struct drm_connector *connector)
1501 {
1502         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1503
1504         intel_hdmi->has_hdmi_sink = false;
1505         intel_hdmi->has_audio = false;
1506         intel_hdmi->rgb_quant_range_selectable = false;
1507
1508         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1509         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1510
1511         kfree(to_intel_connector(connector)->detect_edid);
1512         to_intel_connector(connector)->detect_edid = NULL;
1513 }
1514
1515 static void
1516 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1517 {
1518         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1519         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1520         enum port port = hdmi_to_dig_port(hdmi)->port;
1521         struct i2c_adapter *adapter =
1522                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1523         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1524
1525         /*
1526          * Type 1 DVI adaptors are not required to implement any
1527          * registers, so we can't always detect their presence.
1528          * Ideally we should be able to check the state of the
1529          * CONFIG1 pin, but no such luck on our hardware.
1530          *
1531          * The only method left to us is to check the VBT to see
1532          * if the port is a dual mode capable DP port. But let's
1533          * only do that when we sucesfully read the EDID, to avoid
1534          * confusing log messages about DP dual mode adaptors when
1535          * there's nothing connected to the port.
1536          */
1537         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1538                 if (has_edid &&
1539                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1540                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1541                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1542                 } else {
1543                         type = DRM_DP_DUAL_MODE_NONE;
1544                 }
1545         }
1546
1547         if (type == DRM_DP_DUAL_MODE_NONE)
1548                 return;
1549
1550         hdmi->dp_dual_mode.type = type;
1551         hdmi->dp_dual_mode.max_tmds_clock =
1552                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1553
1554         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1555                       drm_dp_get_dual_mode_type_name(type),
1556                       hdmi->dp_dual_mode.max_tmds_clock);
1557 }
1558
1559 static bool
1560 intel_hdmi_set_edid(struct drm_connector *connector)
1561 {
1562         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1563         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1564         struct edid *edid;
1565         bool connected = false;
1566
1567         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1568
1569         edid = drm_get_edid(connector,
1570                             intel_gmbus_get_adapter(dev_priv,
1571                             intel_hdmi->ddc_bus));
1572
1573         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1574
1575         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1576
1577         to_intel_connector(connector)->detect_edid = edid;
1578         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1579                 intel_hdmi->rgb_quant_range_selectable =
1580                         drm_rgb_quant_range_selectable(edid);
1581
1582                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1583                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1584
1585                 connected = true;
1586         }
1587
1588         return connected;
1589 }
1590
1591 static enum drm_connector_status
1592 intel_hdmi_detect(struct drm_connector *connector, bool force)
1593 {
1594         enum drm_connector_status status;
1595         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1596
1597         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1598                       connector->base.id, connector->name);
1599
1600         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1601
1602         intel_hdmi_unset_edid(connector);
1603
1604         if (intel_hdmi_set_edid(connector)) {
1605                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1606
1607                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1608                 status = connector_status_connected;
1609         } else
1610                 status = connector_status_disconnected;
1611
1612         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1613
1614         return status;
1615 }
1616
1617 static void
1618 intel_hdmi_force(struct drm_connector *connector)
1619 {
1620         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1621
1622         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1623                       connector->base.id, connector->name);
1624
1625         intel_hdmi_unset_edid(connector);
1626
1627         if (connector->status != connector_status_connected)
1628                 return;
1629
1630         intel_hdmi_set_edid(connector);
1631         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1632 }
1633
1634 static int intel_hdmi_get_modes(struct drm_connector *connector)
1635 {
1636         struct edid *edid;
1637
1638         edid = to_intel_connector(connector)->detect_edid;
1639         if (edid == NULL)
1640                 return 0;
1641
1642         return intel_connector_update_modes(connector, edid);
1643 }
1644
1645 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1646                                   struct intel_crtc_state *pipe_config,
1647                                   struct drm_connector_state *conn_state)
1648 {
1649         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1650
1651         intel_hdmi_prepare(encoder, pipe_config);
1652
1653         intel_hdmi->set_infoframes(&encoder->base,
1654                                    pipe_config->has_hdmi_sink,
1655                                    pipe_config, conn_state);
1656 }
1657
1658 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1659                                 struct intel_crtc_state *pipe_config,
1660                                 struct drm_connector_state *conn_state)
1661 {
1662         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1663         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1664         struct drm_device *dev = encoder->base.dev;
1665         struct drm_i915_private *dev_priv = to_i915(dev);
1666
1667         vlv_phy_pre_encoder_enable(encoder);
1668
1669         /* HDMI 1.0V-2dB */
1670         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1671                                  0x2b247878);
1672
1673         intel_hdmi->set_infoframes(&encoder->base,
1674                                    pipe_config->has_hdmi_sink,
1675                                    pipe_config, conn_state);
1676
1677         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1678
1679         vlv_wait_port_ready(dev_priv, dport, 0x0);
1680 }
1681
1682 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1683                                     struct intel_crtc_state *pipe_config,
1684                                     struct drm_connector_state *conn_state)
1685 {
1686         intel_hdmi_prepare(encoder, pipe_config);
1687
1688         vlv_phy_pre_pll_enable(encoder);
1689 }
1690
1691 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1692                                     struct intel_crtc_state *pipe_config,
1693                                     struct drm_connector_state *conn_state)
1694 {
1695         intel_hdmi_prepare(encoder, pipe_config);
1696
1697         chv_phy_pre_pll_enable(encoder);
1698 }
1699
1700 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1701                                       struct intel_crtc_state *old_crtc_state,
1702                                       struct drm_connector_state *old_conn_state)
1703 {
1704         chv_phy_post_pll_disable(encoder);
1705 }
1706
1707 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1708                                   struct intel_crtc_state *old_crtc_state,
1709                                   struct drm_connector_state *old_conn_state)
1710 {
1711         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1712         vlv_phy_reset_lanes(encoder);
1713 }
1714
1715 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1716                                   struct intel_crtc_state *old_crtc_state,
1717                                   struct drm_connector_state *old_conn_state)
1718 {
1719         struct drm_device *dev = encoder->base.dev;
1720         struct drm_i915_private *dev_priv = to_i915(dev);
1721
1722         mutex_lock(&dev_priv->sb_lock);
1723
1724         /* Assert data lane reset */
1725         chv_data_lane_soft_reset(encoder, true);
1726
1727         mutex_unlock(&dev_priv->sb_lock);
1728 }
1729
1730 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1731                                 struct intel_crtc_state *pipe_config,
1732                                 struct drm_connector_state *conn_state)
1733 {
1734         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1735         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1736         struct drm_device *dev = encoder->base.dev;
1737         struct drm_i915_private *dev_priv = to_i915(dev);
1738
1739         chv_phy_pre_encoder_enable(encoder);
1740
1741         /* FIXME: Program the support xxx V-dB */
1742         /* Use 800mV-0dB */
1743         chv_set_phy_signal_level(encoder, 128, 102, false);
1744
1745         intel_hdmi->set_infoframes(&encoder->base,
1746                                    pipe_config->has_hdmi_sink,
1747                                    pipe_config, conn_state);
1748
1749         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1750
1751         vlv_wait_port_ready(dev_priv, dport, 0x0);
1752
1753         /* Second common lane will stay alive on its own now */
1754         chv_phy_release_cl2_override(encoder);
1755 }
1756
1757 static void intel_hdmi_destroy(struct drm_connector *connector)
1758 {
1759         kfree(to_intel_connector(connector)->detect_edid);
1760         drm_connector_cleanup(connector);
1761         kfree(connector);
1762 }
1763
1764 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1765         .detect = intel_hdmi_detect,
1766         .force = intel_hdmi_force,
1767         .fill_modes = drm_helper_probe_single_connector_modes,
1768         .atomic_get_property = intel_digital_connector_atomic_get_property,
1769         .atomic_set_property = intel_digital_connector_atomic_set_property,
1770         .late_register = intel_connector_register,
1771         .early_unregister = intel_connector_unregister,
1772         .destroy = intel_hdmi_destroy,
1773         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1774         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1775 };
1776
1777 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1778         .get_modes = intel_hdmi_get_modes,
1779         .mode_valid = intel_hdmi_mode_valid,
1780         .atomic_check = intel_digital_connector_atomic_check,
1781 };
1782
1783 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1784         .destroy = intel_encoder_destroy,
1785 };
1786
1787 static void
1788 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1789 {
1790         intel_attach_force_audio_property(connector);
1791         intel_attach_broadcast_rgb_property(connector);
1792         intel_attach_aspect_ratio_property(connector);
1793         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1794 }
1795
1796 /*
1797  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
1798  * @encoder: intel_encoder
1799  * @connector: drm_connector
1800  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
1801  *  or reset the high tmds clock ratio for scrambling
1802  * @scrambling: bool to Indicate if the function needs to set or reset
1803  *  sink scrambling
1804  *
1805  * This function handles scrambling on HDMI 2.0 capable sinks.
1806  * If required clock rate is > 340 Mhz && scrambling is supported by sink
1807  * it enables scrambling. This should be called before enabling the HDMI
1808  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
1809  * detect a scrambled clock within 100 ms.
1810  */
1811 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1812                                        struct drm_connector *connector,
1813                                        bool high_tmds_clock_ratio,
1814                                        bool scrambling)
1815 {
1816         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1817         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1818         struct drm_scrambling *sink_scrambling =
1819                                 &connector->display_info.hdmi.scdc.scrambling;
1820         struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
1821                                                            intel_hdmi->ddc_bus);
1822         bool ret;
1823
1824         if (!sink_scrambling->supported)
1825                 return;
1826
1827         DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
1828                       encoder->base.name, connector->name);
1829
1830         /* Set TMDS bit clock ratio to 1/40 or 1/10 */
1831         ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio);
1832         if (!ret) {
1833                 DRM_ERROR("Set TMDS ratio failed\n");
1834                 return;
1835         }
1836
1837         /* Enable/disable sink scrambling */
1838         ret = drm_scdc_set_scrambling(adptr, scrambling);
1839         if (!ret) {
1840                 DRM_ERROR("Set sink scrambling failed\n");
1841                 return;
1842         }
1843
1844         DRM_DEBUG_KMS("sink scrambling handled\n");
1845 }
1846
1847 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
1848 {
1849         u8 ddc_pin;
1850
1851         switch (port) {
1852         case PORT_B:
1853                 ddc_pin = GMBUS_PIN_DPB;
1854                 break;
1855         case PORT_C:
1856                 ddc_pin = GMBUS_PIN_DPC;
1857                 break;
1858         case PORT_D:
1859                 ddc_pin = GMBUS_PIN_DPD_CHV;
1860                 break;
1861         default:
1862                 MISSING_CASE(port);
1863                 ddc_pin = GMBUS_PIN_DPB;
1864                 break;
1865         }
1866         return ddc_pin;
1867 }
1868
1869 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
1870 {
1871         u8 ddc_pin;
1872
1873         switch (port) {
1874         case PORT_B:
1875                 ddc_pin = GMBUS_PIN_1_BXT;
1876                 break;
1877         case PORT_C:
1878                 ddc_pin = GMBUS_PIN_2_BXT;
1879                 break;
1880         default:
1881                 MISSING_CASE(port);
1882                 ddc_pin = GMBUS_PIN_1_BXT;
1883                 break;
1884         }
1885         return ddc_pin;
1886 }
1887
1888 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
1889                               enum port port)
1890 {
1891         u8 ddc_pin;
1892
1893         switch (port) {
1894         case PORT_B:
1895                 ddc_pin = GMBUS_PIN_1_BXT;
1896                 break;
1897         case PORT_C:
1898                 ddc_pin = GMBUS_PIN_2_BXT;
1899                 break;
1900         case PORT_D:
1901                 ddc_pin = GMBUS_PIN_4_CNP;
1902                 break;
1903         default:
1904                 MISSING_CASE(port);
1905                 ddc_pin = GMBUS_PIN_1_BXT;
1906                 break;
1907         }
1908         return ddc_pin;
1909 }
1910
1911 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
1912                               enum port port)
1913 {
1914         u8 ddc_pin;
1915
1916         switch (port) {
1917         case PORT_B:
1918                 ddc_pin = GMBUS_PIN_DPB;
1919                 break;
1920         case PORT_C:
1921                 ddc_pin = GMBUS_PIN_DPC;
1922                 break;
1923         case PORT_D:
1924                 ddc_pin = GMBUS_PIN_DPD;
1925                 break;
1926         default:
1927                 MISSING_CASE(port);
1928                 ddc_pin = GMBUS_PIN_DPB;
1929                 break;
1930         }
1931         return ddc_pin;
1932 }
1933
1934 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1935                              enum port port)
1936 {
1937         const struct ddi_vbt_port_info *info =
1938                 &dev_priv->vbt.ddi_port_info[port];
1939         u8 ddc_pin;
1940
1941         if (info->alternate_ddc_pin) {
1942                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1943                               info->alternate_ddc_pin, port_name(port));
1944                 return info->alternate_ddc_pin;
1945         }
1946
1947         if (IS_CHERRYVIEW(dev_priv))
1948                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
1949         else if (IS_GEN9_LP(dev_priv))
1950                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
1951         else if (HAS_PCH_CNP(dev_priv))
1952                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
1953         else
1954                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
1955
1956         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1957                       ddc_pin, port_name(port));
1958
1959         return ddc_pin;
1960 }
1961
1962 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1963                                struct intel_connector *intel_connector)
1964 {
1965         struct drm_connector *connector = &intel_connector->base;
1966         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1967         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1968         struct drm_device *dev = intel_encoder->base.dev;
1969         struct drm_i915_private *dev_priv = to_i915(dev);
1970         enum port port = intel_dig_port->port;
1971
1972         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
1973                       port_name(port));
1974
1975         if (WARN(intel_dig_port->max_lanes < 4,
1976                  "Not enough lanes (%d) for HDMI on port %c\n",
1977                  intel_dig_port->max_lanes, port_name(port)))
1978                 return;
1979
1980         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1981                            DRM_MODE_CONNECTOR_HDMIA);
1982         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1983
1984         connector->interlace_allowed = 1;
1985         connector->doublescan_allowed = 0;
1986         connector->stereo_allowed = 1;
1987
1988         if (IS_GEMINILAKE(dev_priv))
1989                 connector->ycbcr_420_allowed = true;
1990
1991         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
1992
1993         if (WARN_ON(port == PORT_A))
1994                 return;
1995         intel_encoder->hpd_pin = intel_hpd_pin(port);
1996
1997         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1998                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1999                 intel_hdmi->set_infoframes = vlv_set_infoframes;
2000                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2001         } else if (IS_G4X(dev_priv)) {
2002                 intel_hdmi->write_infoframe = g4x_write_infoframe;
2003                 intel_hdmi->set_infoframes = g4x_set_infoframes;
2004                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2005         } else if (HAS_DDI(dev_priv)) {
2006                 intel_hdmi->write_infoframe = hsw_write_infoframe;
2007                 intel_hdmi->set_infoframes = hsw_set_infoframes;
2008                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2009         } else if (HAS_PCH_IBX(dev_priv)) {
2010                 intel_hdmi->write_infoframe = ibx_write_infoframe;
2011                 intel_hdmi->set_infoframes = ibx_set_infoframes;
2012                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2013         } else {
2014                 intel_hdmi->write_infoframe = cpt_write_infoframe;
2015                 intel_hdmi->set_infoframes = cpt_set_infoframes;
2016                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2017         }
2018
2019         if (HAS_DDI(dev_priv))
2020                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2021         else
2022                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2023
2024         intel_hdmi_add_properties(intel_hdmi, connector);
2025
2026         intel_connector_attach_encoder(intel_connector, intel_encoder);
2027         intel_hdmi->attached_connector = intel_connector;
2028
2029         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2030          * 0xd.  Failure to do so will result in spurious interrupts being
2031          * generated on the port when a cable is not attached.
2032          */
2033         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
2034                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2035                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2036         }
2037 }
2038
2039 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2040                      i915_reg_t hdmi_reg, enum port port)
2041 {
2042         struct intel_digital_port *intel_dig_port;
2043         struct intel_encoder *intel_encoder;
2044         struct intel_connector *intel_connector;
2045
2046         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2047         if (!intel_dig_port)
2048                 return;
2049
2050         intel_connector = intel_connector_alloc();
2051         if (!intel_connector) {
2052                 kfree(intel_dig_port);
2053                 return;
2054         }
2055
2056         intel_encoder = &intel_dig_port->base;
2057
2058         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2059                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2060                          "HDMI %c", port_name(port));
2061
2062         intel_encoder->compute_config = intel_hdmi_compute_config;
2063         if (HAS_PCH_SPLIT(dev_priv)) {
2064                 intel_encoder->disable = pch_disable_hdmi;
2065                 intel_encoder->post_disable = pch_post_disable_hdmi;
2066         } else {
2067                 intel_encoder->disable = g4x_disable_hdmi;
2068         }
2069         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2070         intel_encoder->get_config = intel_hdmi_get_config;
2071         if (IS_CHERRYVIEW(dev_priv)) {
2072                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2073                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2074                 intel_encoder->enable = vlv_enable_hdmi;
2075                 intel_encoder->post_disable = chv_hdmi_post_disable;
2076                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2077         } else if (IS_VALLEYVIEW(dev_priv)) {
2078                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2079                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2080                 intel_encoder->enable = vlv_enable_hdmi;
2081                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2082         } else {
2083                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2084                 if (HAS_PCH_CPT(dev_priv))
2085                         intel_encoder->enable = cpt_enable_hdmi;
2086                 else if (HAS_PCH_IBX(dev_priv))
2087                         intel_encoder->enable = ibx_enable_hdmi;
2088                 else
2089                         intel_encoder->enable = g4x_enable_hdmi;
2090         }
2091
2092         intel_encoder->type = INTEL_OUTPUT_HDMI;
2093         intel_encoder->power_domain = intel_port_to_power_domain(port);
2094         intel_encoder->port = port;
2095         if (IS_CHERRYVIEW(dev_priv)) {
2096                 if (port == PORT_D)
2097                         intel_encoder->crtc_mask = 1 << 2;
2098                 else
2099                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2100         } else {
2101                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2102         }
2103         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2104         /*
2105          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2106          * to work on real hardware. And since g4x can send infoframes to
2107          * only one port anyway, nothing is lost by allowing it.
2108          */
2109         if (IS_G4X(dev_priv))
2110                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2111
2112         intel_dig_port->port = port;
2113         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2114         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2115         intel_dig_port->max_lanes = 4;
2116
2117         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2118 }