26767785f14aa2d9120e53641f5f03752c90731a
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_hdmi.c
1 /*
2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2009 Intel Corporation
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *      Eric Anholt <eric@anholt.net>
26  *      Jesse Barnes <jesse.barnes@intel.com>
27  */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_hdcp.h>
37 #include <drm/drm_scdc_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
41 #include "i915_drv.h"
42
43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
44 {
45         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
46 }
47
48 static void
49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
50 {
51         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
52         struct drm_i915_private *dev_priv = to_i915(dev);
53         u32 enabled_bits;
54
55         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
56
57         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
58              "HDMI port enabled, expecting disabled\n");
59 }
60
61 static void
62 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
63                                      enum transcoder cpu_transcoder)
64 {
65         WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
66              TRANS_DDI_FUNC_ENABLE,
67              "HDMI transcoder function enabled, expecting disabled\n");
68 }
69
70 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
71 {
72         struct intel_digital_port *intel_dig_port =
73                 container_of(encoder, struct intel_digital_port, base.base);
74         return &intel_dig_port->hdmi;
75 }
76
77 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
78 {
79         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
80 }
81
82 static u32 g4x_infoframe_index(unsigned int type)
83 {
84         switch (type) {
85         case HDMI_PACKET_TYPE_GAMUT_METADATA:
86                 return VIDEO_DIP_SELECT_GAMUT;
87         case HDMI_INFOFRAME_TYPE_AVI:
88                 return VIDEO_DIP_SELECT_AVI;
89         case HDMI_INFOFRAME_TYPE_SPD:
90                 return VIDEO_DIP_SELECT_SPD;
91         case HDMI_INFOFRAME_TYPE_VENDOR:
92                 return VIDEO_DIP_SELECT_VENDOR;
93         default:
94                 MISSING_CASE(type);
95                 return 0;
96         }
97 }
98
99 static u32 g4x_infoframe_enable(unsigned int type)
100 {
101         switch (type) {
102         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
103                 return VIDEO_DIP_ENABLE_GCP;
104         case HDMI_PACKET_TYPE_GAMUT_METADATA:
105                 return VIDEO_DIP_ENABLE_GAMUT;
106         case DP_SDP_VSC:
107                 return 0;
108         case HDMI_INFOFRAME_TYPE_AVI:
109                 return VIDEO_DIP_ENABLE_AVI;
110         case HDMI_INFOFRAME_TYPE_SPD:
111                 return VIDEO_DIP_ENABLE_SPD;
112         case HDMI_INFOFRAME_TYPE_VENDOR:
113                 return VIDEO_DIP_ENABLE_VENDOR;
114         default:
115                 MISSING_CASE(type);
116                 return 0;
117         }
118 }
119
120 static u32 hsw_infoframe_enable(unsigned int type)
121 {
122         switch (type) {
123         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
124                 return VIDEO_DIP_ENABLE_GCP_HSW;
125         case HDMI_PACKET_TYPE_GAMUT_METADATA:
126                 return VIDEO_DIP_ENABLE_GMP_HSW;
127         case DP_SDP_VSC:
128                 return VIDEO_DIP_ENABLE_VSC_HSW;
129         case DP_SDP_PPS:
130                 return VDIP_ENABLE_PPS;
131         case HDMI_INFOFRAME_TYPE_AVI:
132                 return VIDEO_DIP_ENABLE_AVI_HSW;
133         case HDMI_INFOFRAME_TYPE_SPD:
134                 return VIDEO_DIP_ENABLE_SPD_HSW;
135         case HDMI_INFOFRAME_TYPE_VENDOR:
136                 return VIDEO_DIP_ENABLE_VS_HSW;
137         default:
138                 MISSING_CASE(type);
139                 return 0;
140         }
141 }
142
143 static i915_reg_t
144 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
145                  enum transcoder cpu_transcoder,
146                  unsigned int type,
147                  int i)
148 {
149         switch (type) {
150         case HDMI_PACKET_TYPE_GAMUT_METADATA:
151                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
152         case DP_SDP_VSC:
153                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
154         case DP_SDP_PPS:
155                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
156         case HDMI_INFOFRAME_TYPE_AVI:
157                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
158         case HDMI_INFOFRAME_TYPE_SPD:
159                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
160         case HDMI_INFOFRAME_TYPE_VENDOR:
161                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
162         default:
163                 MISSING_CASE(type);
164                 return INVALID_MMIO_REG;
165         }
166 }
167
168 static int hsw_dip_data_size(unsigned int type)
169 {
170         switch (type) {
171         case DP_SDP_VSC:
172                 return VIDEO_DIP_VSC_DATA_SIZE;
173         case DP_SDP_PPS:
174                 return VIDEO_DIP_PPS_DATA_SIZE;
175         default:
176                 return VIDEO_DIP_DATA_SIZE;
177         }
178 }
179
180 static void g4x_write_infoframe(struct intel_encoder *encoder,
181                                 const struct intel_crtc_state *crtc_state,
182                                 unsigned int type,
183                                 const void *frame, ssize_t len)
184 {
185         const u32 *data = frame;
186         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
187         u32 val = I915_READ(VIDEO_DIP_CTL);
188         int i;
189
190         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
191
192         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
193         val |= g4x_infoframe_index(type);
194
195         val &= ~g4x_infoframe_enable(type);
196
197         I915_WRITE(VIDEO_DIP_CTL, val);
198
199         mmiowb();
200         for (i = 0; i < len; i += 4) {
201                 I915_WRITE(VIDEO_DIP_DATA, *data);
202                 data++;
203         }
204         /* Write every possible data byte to force correct ECC calculation. */
205         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
206                 I915_WRITE(VIDEO_DIP_DATA, 0);
207         mmiowb();
208
209         val |= g4x_infoframe_enable(type);
210         val &= ~VIDEO_DIP_FREQ_MASK;
211         val |= VIDEO_DIP_FREQ_VSYNC;
212
213         I915_WRITE(VIDEO_DIP_CTL, val);
214         POSTING_READ(VIDEO_DIP_CTL);
215 }
216
217 static void g4x_read_infoframe(struct intel_encoder *encoder,
218                                const struct intel_crtc_state *crtc_state,
219                                unsigned int type,
220                                void *frame, ssize_t len)
221 {
222         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
223         u32 val, *data = frame;
224         int i;
225
226         val = I915_READ(VIDEO_DIP_CTL);
227
228         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
229         val |= g4x_infoframe_index(type);
230
231         I915_WRITE(VIDEO_DIP_CTL, val);
232
233         for (i = 0; i < len; i += 4)
234                 *data++ = I915_READ(VIDEO_DIP_DATA);
235 }
236
237 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
238                                   const struct intel_crtc_state *pipe_config)
239 {
240         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
241         u32 val = I915_READ(VIDEO_DIP_CTL);
242
243         if ((val & VIDEO_DIP_ENABLE) == 0)
244                 return 0;
245
246         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
247                 return 0;
248
249         return val & (VIDEO_DIP_ENABLE_AVI |
250                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
251 }
252
253 static void ibx_write_infoframe(struct intel_encoder *encoder,
254                                 const struct intel_crtc_state *crtc_state,
255                                 unsigned int type,
256                                 const void *frame, ssize_t len)
257 {
258         const u32 *data = frame;
259         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
261         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
262         u32 val = I915_READ(reg);
263         int i;
264
265         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
266
267         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
268         val |= g4x_infoframe_index(type);
269
270         val &= ~g4x_infoframe_enable(type);
271
272         I915_WRITE(reg, val);
273
274         mmiowb();
275         for (i = 0; i < len; i += 4) {
276                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
277                 data++;
278         }
279         /* Write every possible data byte to force correct ECC calculation. */
280         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
281                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
282         mmiowb();
283
284         val |= g4x_infoframe_enable(type);
285         val &= ~VIDEO_DIP_FREQ_MASK;
286         val |= VIDEO_DIP_FREQ_VSYNC;
287
288         I915_WRITE(reg, val);
289         POSTING_READ(reg);
290 }
291
292 static void ibx_read_infoframe(struct intel_encoder *encoder,
293                                const struct intel_crtc_state *crtc_state,
294                                unsigned int type,
295                                void *frame, ssize_t len)
296 {
297         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
298         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
299         u32 val, *data = frame;
300         int i;
301
302         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
303
304         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
305         val |= g4x_infoframe_index(type);
306
307         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
308
309         for (i = 0; i < len; i += 4)
310                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
311 }
312
313 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
314                                   const struct intel_crtc_state *pipe_config)
315 {
316         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
317         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
318         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
319         u32 val = I915_READ(reg);
320
321         if ((val & VIDEO_DIP_ENABLE) == 0)
322                 return 0;
323
324         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
325                 return 0;
326
327         return val & (VIDEO_DIP_ENABLE_AVI |
328                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
329                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
330 }
331
332 static void cpt_write_infoframe(struct intel_encoder *encoder,
333                                 const struct intel_crtc_state *crtc_state,
334                                 unsigned int type,
335                                 const void *frame, ssize_t len)
336 {
337         const u32 *data = frame;
338         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
340         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
341         u32 val = I915_READ(reg);
342         int i;
343
344         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
345
346         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
347         val |= g4x_infoframe_index(type);
348
349         /* The DIP control register spec says that we need to update the AVI
350          * infoframe without clearing its enable bit */
351         if (type != HDMI_INFOFRAME_TYPE_AVI)
352                 val &= ~g4x_infoframe_enable(type);
353
354         I915_WRITE(reg, val);
355
356         mmiowb();
357         for (i = 0; i < len; i += 4) {
358                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
359                 data++;
360         }
361         /* Write every possible data byte to force correct ECC calculation. */
362         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
363                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
364         mmiowb();
365
366         val |= g4x_infoframe_enable(type);
367         val &= ~VIDEO_DIP_FREQ_MASK;
368         val |= VIDEO_DIP_FREQ_VSYNC;
369
370         I915_WRITE(reg, val);
371         POSTING_READ(reg);
372 }
373
374 static void cpt_read_infoframe(struct intel_encoder *encoder,
375                                const struct intel_crtc_state *crtc_state,
376                                unsigned int type,
377                                void *frame, ssize_t len)
378 {
379         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
380         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
381         u32 val, *data = frame;
382         int i;
383
384         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
385
386         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
387         val |= g4x_infoframe_index(type);
388
389         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
390
391         for (i = 0; i < len; i += 4)
392                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
393 }
394
395 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
396                                   const struct intel_crtc_state *pipe_config)
397 {
398         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
399         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
400         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
401
402         if ((val & VIDEO_DIP_ENABLE) == 0)
403                 return 0;
404
405         return val & (VIDEO_DIP_ENABLE_AVI |
406                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
407                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
408 }
409
410 static void vlv_write_infoframe(struct intel_encoder *encoder,
411                                 const struct intel_crtc_state *crtc_state,
412                                 unsigned int type,
413                                 const void *frame, ssize_t len)
414 {
415         const u32 *data = frame;
416         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
418         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
419         u32 val = I915_READ(reg);
420         int i;
421
422         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
423
424         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
425         val |= g4x_infoframe_index(type);
426
427         val &= ~g4x_infoframe_enable(type);
428
429         I915_WRITE(reg, val);
430
431         mmiowb();
432         for (i = 0; i < len; i += 4) {
433                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
434                 data++;
435         }
436         /* Write every possible data byte to force correct ECC calculation. */
437         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
438                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
439         mmiowb();
440
441         val |= g4x_infoframe_enable(type);
442         val &= ~VIDEO_DIP_FREQ_MASK;
443         val |= VIDEO_DIP_FREQ_VSYNC;
444
445         I915_WRITE(reg, val);
446         POSTING_READ(reg);
447 }
448
449 static void vlv_read_infoframe(struct intel_encoder *encoder,
450                                const struct intel_crtc_state *crtc_state,
451                                unsigned int type,
452                                void *frame, ssize_t len)
453 {
454         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
455         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
456         u32 val, *data = frame;
457         int i;
458
459         val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe));
460
461         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
462         val |= g4x_infoframe_index(type);
463
464         I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
465
466         for (i = 0; i < len; i += 4)
467                 *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe));
468 }
469
470 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
471                                   const struct intel_crtc_state *pipe_config)
472 {
473         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
474         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
475         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
476
477         if ((val & VIDEO_DIP_ENABLE) == 0)
478                 return 0;
479
480         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
481                 return 0;
482
483         return val & (VIDEO_DIP_ENABLE_AVI |
484                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
485                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
486 }
487
488 static void hsw_write_infoframe(struct intel_encoder *encoder,
489                                 const struct intel_crtc_state *crtc_state,
490                                 unsigned int type,
491                                 const void *frame, ssize_t len)
492 {
493         const u32 *data = frame;
494         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
495         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
496         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
497         int data_size;
498         int i;
499         u32 val = I915_READ(ctl_reg);
500
501         data_size = hsw_dip_data_size(type);
502
503         val &= ~hsw_infoframe_enable(type);
504         I915_WRITE(ctl_reg, val);
505
506         mmiowb();
507         for (i = 0; i < len; i += 4) {
508                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
509                                             type, i >> 2), *data);
510                 data++;
511         }
512         /* Write every possible data byte to force correct ECC calculation. */
513         for (; i < data_size; i += 4)
514                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
515                                             type, i >> 2), 0);
516         mmiowb();
517
518         val |= hsw_infoframe_enable(type);
519         I915_WRITE(ctl_reg, val);
520         POSTING_READ(ctl_reg);
521 }
522
523 static void hsw_read_infoframe(struct intel_encoder *encoder,
524                                const struct intel_crtc_state *crtc_state,
525                                unsigned int type,
526                                void *frame, ssize_t len)
527 {
528         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
529         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
530         u32 val, *data = frame;
531         int i;
532
533         val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));
534
535         for (i = 0; i < len; i += 4)
536                 *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,
537                                                      type, i >> 2));
538 }
539
540 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
541                                   const struct intel_crtc_state *pipe_config)
542 {
543         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
544         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
545
546         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
547                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
548                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
549 }
550
551 static const u8 infoframe_type_to_idx[] = {
552         HDMI_PACKET_TYPE_GENERAL_CONTROL,
553         HDMI_PACKET_TYPE_GAMUT_METADATA,
554         DP_SDP_VSC,
555         HDMI_INFOFRAME_TYPE_AVI,
556         HDMI_INFOFRAME_TYPE_SPD,
557         HDMI_INFOFRAME_TYPE_VENDOR,
558 };
559
560 u32 intel_hdmi_infoframe_enable(unsigned int type)
561 {
562         int i;
563
564         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
565                 if (infoframe_type_to_idx[i] == type)
566                         return BIT(i);
567         }
568
569         return 0;
570 }
571
572 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
573                                   const struct intel_crtc_state *crtc_state)
574 {
575         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
576         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
577         u32 val, ret = 0;
578         int i;
579
580         val = dig_port->infoframes_enabled(encoder, crtc_state);
581
582         /* map from hardware bits to dip idx */
583         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
584                 unsigned int type = infoframe_type_to_idx[i];
585
586                 if (HAS_DDI(dev_priv)) {
587                         if (val & hsw_infoframe_enable(type))
588                                 ret |= BIT(i);
589                 } else {
590                         if (val & g4x_infoframe_enable(type))
591                                 ret |= BIT(i);
592                 }
593         }
594
595         return ret;
596 }
597
598 /*
599  * The data we write to the DIP data buffer registers is 1 byte bigger than the
600  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
601  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
602  * used for both technologies.
603  *
604  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
605  * DW1:       DB3       | DB2 | DB1 | DB0
606  * DW2:       DB7       | DB6 | DB5 | DB4
607  * DW3: ...
608  *
609  * (HB is Header Byte, DB is Data Byte)
610  *
611  * The hdmi pack() functions don't know about that hardware specific hole so we
612  * trick them by giving an offset into the buffer and moving back the header
613  * bytes by one.
614  */
615 static void intel_write_infoframe(struct intel_encoder *encoder,
616                                   const struct intel_crtc_state *crtc_state,
617                                   enum hdmi_infoframe_type type,
618                                   const union hdmi_infoframe *frame)
619 {
620         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
621         u8 buffer[VIDEO_DIP_DATA_SIZE];
622         ssize_t len;
623
624         if ((crtc_state->infoframes.enable &
625              intel_hdmi_infoframe_enable(type)) == 0)
626                 return;
627
628         if (WARN_ON(frame->any.type != type))
629                 return;
630
631         /* see comment above for the reason for this offset */
632         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
633         if (WARN_ON(len < 0))
634                 return;
635
636         /* Insert the 'hole' (see big comment above) at position 3 */
637         memmove(&buffer[0], &buffer[1], 3);
638         buffer[3] = 0;
639         len++;
640
641         intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
642 }
643
644 void intel_read_infoframe(struct intel_encoder *encoder,
645                           const struct intel_crtc_state *crtc_state,
646                           enum hdmi_infoframe_type type,
647                           union hdmi_infoframe *frame)
648 {
649         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
650         u8 buffer[VIDEO_DIP_DATA_SIZE];
651         int ret;
652
653         if ((crtc_state->infoframes.enable &
654              intel_hdmi_infoframe_enable(type)) == 0)
655                 return;
656
657         intel_dig_port->read_infoframe(encoder, crtc_state,
658                                        type, buffer, sizeof(buffer));
659
660         /* Fill the 'hole' (see big comment above) at position 3 */
661         memmove(&buffer[1], &buffer[0], 3);
662
663         /* see comment above for the reason for this offset */
664         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
665         if (ret) {
666                 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type);
667                 return;
668         }
669
670         if (frame->any.type != type)
671                 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
672                               frame->any.type, type);
673 }
674
675 static bool
676 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
677                                  struct intel_crtc_state *crtc_state,
678                                  struct drm_connector_state *conn_state)
679 {
680         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
681         const struct drm_display_mode *adjusted_mode =
682                 &crtc_state->base.adjusted_mode;
683         struct drm_connector *connector = conn_state->connector;
684         int ret;
685
686         if (!crtc_state->has_infoframe)
687                 return true;
688
689         crtc_state->infoframes.enable |=
690                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
691
692         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
693                                                        adjusted_mode);
694         if (ret)
695                 return false;
696
697         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
698                 frame->colorspace = HDMI_COLORSPACE_YUV420;
699         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
700                 frame->colorspace = HDMI_COLORSPACE_YUV444;
701         else
702                 frame->colorspace = HDMI_COLORSPACE_RGB;
703
704         drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
705
706         drm_hdmi_avi_infoframe_quant_range(frame, connector,
707                                            adjusted_mode,
708                                            crtc_state->limited_color_range ?
709                                            HDMI_QUANTIZATION_RANGE_LIMITED :
710                                            HDMI_QUANTIZATION_RANGE_FULL);
711
712         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
713
714         /* TODO: handle pixel repetition for YCBCR420 outputs */
715
716         ret = hdmi_avi_infoframe_check(frame);
717         if (WARN_ON(ret))
718                 return false;
719
720         return true;
721 }
722
723 static bool
724 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
725                                  struct intel_crtc_state *crtc_state,
726                                  struct drm_connector_state *conn_state)
727 {
728         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
729         int ret;
730
731         if (!crtc_state->has_infoframe)
732                 return true;
733
734         crtc_state->infoframes.enable |=
735                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
736
737         ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
738         if (WARN_ON(ret))
739                 return false;
740
741         frame->sdi = HDMI_SPD_SDI_PC;
742
743         ret = hdmi_spd_infoframe_check(frame);
744         if (WARN_ON(ret))
745                 return false;
746
747         return true;
748 }
749
750 static bool
751 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
752                                   struct intel_crtc_state *crtc_state,
753                                   struct drm_connector_state *conn_state)
754 {
755         struct hdmi_vendor_infoframe *frame =
756                 &crtc_state->infoframes.hdmi.vendor.hdmi;
757         const struct drm_display_info *info =
758                 &conn_state->connector->display_info;
759         int ret;
760
761         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
762                 return true;
763
764         crtc_state->infoframes.enable |=
765                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
766
767         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
768                                                           conn_state->connector,
769                                                           &crtc_state->base.adjusted_mode);
770         if (WARN_ON(ret))
771                 return false;
772
773         ret = hdmi_vendor_infoframe_check(frame);
774         if (WARN_ON(ret))
775                 return false;
776
777         return true;
778 }
779
780 static void g4x_set_infoframes(struct intel_encoder *encoder,
781                                bool enable,
782                                const struct intel_crtc_state *crtc_state,
783                                const struct drm_connector_state *conn_state)
784 {
785         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
786         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
787         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
788         i915_reg_t reg = VIDEO_DIP_CTL;
789         u32 val = I915_READ(reg);
790         u32 port = VIDEO_DIP_PORT(encoder->port);
791
792         assert_hdmi_port_disabled(intel_hdmi);
793
794         /* If the registers were not initialized yet, they might be zeroes,
795          * which means we're selecting the AVI DIP and we're setting its
796          * frequency to once. This seems to really confuse the HW and make
797          * things stop working (the register spec says the AVI always needs to
798          * be sent every VSync). So here we avoid writing to the register more
799          * than we need and also explicitly select the AVI DIP and explicitly
800          * set its frequency to every VSync. Avoiding to write it twice seems to
801          * be enough to solve the problem, but being defensive shouldn't hurt us
802          * either. */
803         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
804
805         if (!enable) {
806                 if (!(val & VIDEO_DIP_ENABLE))
807                         return;
808                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
809                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
810                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
811                         return;
812                 }
813                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
814                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
815                 I915_WRITE(reg, val);
816                 POSTING_READ(reg);
817                 return;
818         }
819
820         if (port != (val & VIDEO_DIP_PORT_MASK)) {
821                 if (val & VIDEO_DIP_ENABLE) {
822                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
823                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
824                         return;
825                 }
826                 val &= ~VIDEO_DIP_PORT_MASK;
827                 val |= port;
828         }
829
830         val |= VIDEO_DIP_ENABLE;
831         val &= ~(VIDEO_DIP_ENABLE_AVI |
832                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
833
834         I915_WRITE(reg, val);
835         POSTING_READ(reg);
836
837         intel_write_infoframe(encoder, crtc_state,
838                               HDMI_INFOFRAME_TYPE_AVI,
839                               &crtc_state->infoframes.avi);
840         intel_write_infoframe(encoder, crtc_state,
841                               HDMI_INFOFRAME_TYPE_SPD,
842                               &crtc_state->infoframes.spd);
843         intel_write_infoframe(encoder, crtc_state,
844                               HDMI_INFOFRAME_TYPE_VENDOR,
845                               &crtc_state->infoframes.hdmi);
846 }
847
848 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
849 {
850         struct drm_connector *connector = conn_state->connector;
851
852         /*
853          * HDMI cloning is only supported on g4x which doesn't
854          * support deep color or GCP infoframes anyway so no
855          * need to worry about multiple HDMI sinks here.
856          */
857
858         return connector->display_info.bpc > 8;
859 }
860
861 /*
862  * Determine if default_phase=1 can be indicated in the GCP infoframe.
863  *
864  * From HDMI specification 1.4a:
865  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
866  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
867  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
868  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
869  *   phase of 0
870  */
871 static bool gcp_default_phase_possible(int pipe_bpp,
872                                        const struct drm_display_mode *mode)
873 {
874         unsigned int pixels_per_group;
875
876         switch (pipe_bpp) {
877         case 30:
878                 /* 4 pixels in 5 clocks */
879                 pixels_per_group = 4;
880                 break;
881         case 36:
882                 /* 2 pixels in 3 clocks */
883                 pixels_per_group = 2;
884                 break;
885         case 48:
886                 /* 1 pixel in 2 clocks */
887                 pixels_per_group = 1;
888                 break;
889         default:
890                 /* phase information not relevant for 8bpc */
891                 return false;
892         }
893
894         return mode->crtc_hdisplay % pixels_per_group == 0 &&
895                 mode->crtc_htotal % pixels_per_group == 0 &&
896                 mode->crtc_hblank_start % pixels_per_group == 0 &&
897                 mode->crtc_hblank_end % pixels_per_group == 0 &&
898                 mode->crtc_hsync_start % pixels_per_group == 0 &&
899                 mode->crtc_hsync_end % pixels_per_group == 0 &&
900                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
901                  mode->crtc_htotal/2 % pixels_per_group == 0);
902 }
903
904 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
905                                          const struct intel_crtc_state *crtc_state,
906                                          const struct drm_connector_state *conn_state)
907 {
908         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
909         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
910         i915_reg_t reg;
911
912         if ((crtc_state->infoframes.enable &
913              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
914                 return false;
915
916         if (HAS_DDI(dev_priv))
917                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
918         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
919                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
920         else if (HAS_PCH_SPLIT(dev_priv))
921                 reg = TVIDEO_DIP_GCP(crtc->pipe);
922         else
923                 return false;
924
925         I915_WRITE(reg, crtc_state->infoframes.gcp);
926
927         return true;
928 }
929
930 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
931                                    struct intel_crtc_state *crtc_state)
932 {
933         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
934         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
935         i915_reg_t reg;
936
937         if ((crtc_state->infoframes.enable &
938              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
939                 return;
940
941         if (HAS_DDI(dev_priv))
942                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
943         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
944                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
945         else if (HAS_PCH_SPLIT(dev_priv))
946                 reg = TVIDEO_DIP_GCP(crtc->pipe);
947         else
948                 return;
949
950         crtc_state->infoframes.gcp = I915_READ(reg);
951 }
952
953 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
954                                              struct intel_crtc_state *crtc_state,
955                                              struct drm_connector_state *conn_state)
956 {
957         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
958
959         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
960                 return;
961
962         crtc_state->infoframes.enable |=
963                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
964
965         /* Indicate color depth whenever the sink supports deep color */
966         if (hdmi_sink_is_deep_color(conn_state))
967                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
968
969         /* Enable default_phase whenever the display mode is suitably aligned */
970         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
971                                        &crtc_state->base.adjusted_mode))
972                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
973 }
974
975 static void ibx_set_infoframes(struct intel_encoder *encoder,
976                                bool enable,
977                                const struct intel_crtc_state *crtc_state,
978                                const struct drm_connector_state *conn_state)
979 {
980         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
982         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
983         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
984         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
985         u32 val = I915_READ(reg);
986         u32 port = VIDEO_DIP_PORT(encoder->port);
987
988         assert_hdmi_port_disabled(intel_hdmi);
989
990         /* See the big comment in g4x_set_infoframes() */
991         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
992
993         if (!enable) {
994                 if (!(val & VIDEO_DIP_ENABLE))
995                         return;
996                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
997                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
998                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
999                 I915_WRITE(reg, val);
1000                 POSTING_READ(reg);
1001                 return;
1002         }
1003
1004         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1005                 WARN(val & VIDEO_DIP_ENABLE,
1006                      "DIP already enabled on port %c\n",
1007                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1008                 val &= ~VIDEO_DIP_PORT_MASK;
1009                 val |= port;
1010         }
1011
1012         val |= VIDEO_DIP_ENABLE;
1013         val &= ~(VIDEO_DIP_ENABLE_AVI |
1014                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1015                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1016
1017         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1018                 val |= VIDEO_DIP_ENABLE_GCP;
1019
1020         I915_WRITE(reg, val);
1021         POSTING_READ(reg);
1022
1023         intel_write_infoframe(encoder, crtc_state,
1024                               HDMI_INFOFRAME_TYPE_AVI,
1025                               &crtc_state->infoframes.avi);
1026         intel_write_infoframe(encoder, crtc_state,
1027                               HDMI_INFOFRAME_TYPE_SPD,
1028                               &crtc_state->infoframes.spd);
1029         intel_write_infoframe(encoder, crtc_state,
1030                               HDMI_INFOFRAME_TYPE_VENDOR,
1031                               &crtc_state->infoframes.hdmi);
1032 }
1033
1034 static void cpt_set_infoframes(struct intel_encoder *encoder,
1035                                bool enable,
1036                                const struct intel_crtc_state *crtc_state,
1037                                const struct drm_connector_state *conn_state)
1038 {
1039         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1041         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1042         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1043         u32 val = I915_READ(reg);
1044
1045         assert_hdmi_port_disabled(intel_hdmi);
1046
1047         /* See the big comment in g4x_set_infoframes() */
1048         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1049
1050         if (!enable) {
1051                 if (!(val & VIDEO_DIP_ENABLE))
1052                         return;
1053                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1054                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1055                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1056                 I915_WRITE(reg, val);
1057                 POSTING_READ(reg);
1058                 return;
1059         }
1060
1061         /* Set both together, unset both together: see the spec. */
1062         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1063         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1064                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1065
1066         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1067                 val |= VIDEO_DIP_ENABLE_GCP;
1068
1069         I915_WRITE(reg, val);
1070         POSTING_READ(reg);
1071
1072         intel_write_infoframe(encoder, crtc_state,
1073                               HDMI_INFOFRAME_TYPE_AVI,
1074                               &crtc_state->infoframes.avi);
1075         intel_write_infoframe(encoder, crtc_state,
1076                               HDMI_INFOFRAME_TYPE_SPD,
1077                               &crtc_state->infoframes.spd);
1078         intel_write_infoframe(encoder, crtc_state,
1079                               HDMI_INFOFRAME_TYPE_VENDOR,
1080                               &crtc_state->infoframes.hdmi);
1081 }
1082
1083 static void vlv_set_infoframes(struct intel_encoder *encoder,
1084                                bool enable,
1085                                const struct intel_crtc_state *crtc_state,
1086                                const struct drm_connector_state *conn_state)
1087 {
1088         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1090         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1091         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1092         u32 val = I915_READ(reg);
1093         u32 port = VIDEO_DIP_PORT(encoder->port);
1094
1095         assert_hdmi_port_disabled(intel_hdmi);
1096
1097         /* See the big comment in g4x_set_infoframes() */
1098         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1099
1100         if (!enable) {
1101                 if (!(val & VIDEO_DIP_ENABLE))
1102                         return;
1103                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1104                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1105                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1106                 I915_WRITE(reg, val);
1107                 POSTING_READ(reg);
1108                 return;
1109         }
1110
1111         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1112                 WARN(val & VIDEO_DIP_ENABLE,
1113                      "DIP already enabled on port %c\n",
1114                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1115                 val &= ~VIDEO_DIP_PORT_MASK;
1116                 val |= port;
1117         }
1118
1119         val |= VIDEO_DIP_ENABLE;
1120         val &= ~(VIDEO_DIP_ENABLE_AVI |
1121                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1122                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1123
1124         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1125                 val |= VIDEO_DIP_ENABLE_GCP;
1126
1127         I915_WRITE(reg, val);
1128         POSTING_READ(reg);
1129
1130         intel_write_infoframe(encoder, crtc_state,
1131                               HDMI_INFOFRAME_TYPE_AVI,
1132                               &crtc_state->infoframes.avi);
1133         intel_write_infoframe(encoder, crtc_state,
1134                               HDMI_INFOFRAME_TYPE_SPD,
1135                               &crtc_state->infoframes.spd);
1136         intel_write_infoframe(encoder, crtc_state,
1137                               HDMI_INFOFRAME_TYPE_VENDOR,
1138                               &crtc_state->infoframes.hdmi);
1139 }
1140
1141 static void hsw_set_infoframes(struct intel_encoder *encoder,
1142                                bool enable,
1143                                const struct intel_crtc_state *crtc_state,
1144                                const struct drm_connector_state *conn_state)
1145 {
1146         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1147         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1148         u32 val = I915_READ(reg);
1149
1150         assert_hdmi_transcoder_func_disabled(dev_priv,
1151                                              crtc_state->cpu_transcoder);
1152
1153         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1154                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1155                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
1156
1157         if (!enable) {
1158                 I915_WRITE(reg, val);
1159                 POSTING_READ(reg);
1160                 return;
1161         }
1162
1163         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1164                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1165
1166         I915_WRITE(reg, val);
1167         POSTING_READ(reg);
1168
1169         intel_write_infoframe(encoder, crtc_state,
1170                               HDMI_INFOFRAME_TYPE_AVI,
1171                               &crtc_state->infoframes.avi);
1172         intel_write_infoframe(encoder, crtc_state,
1173                               HDMI_INFOFRAME_TYPE_SPD,
1174                               &crtc_state->infoframes.spd);
1175         intel_write_infoframe(encoder, crtc_state,
1176                               HDMI_INFOFRAME_TYPE_VENDOR,
1177                               &crtc_state->infoframes.hdmi);
1178 }
1179
1180 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1181 {
1182         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1183         struct i2c_adapter *adapter =
1184                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1185
1186         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1187                 return;
1188
1189         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1190                       enable ? "Enabling" : "Disabling");
1191
1192         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1193                                          adapter, enable);
1194 }
1195
1196 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
1197                                 unsigned int offset, void *buffer, size_t size)
1198 {
1199         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1200         struct drm_i915_private *dev_priv =
1201                 intel_dig_port->base.base.dev->dev_private;
1202         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1203                                                               hdmi->ddc_bus);
1204         int ret;
1205         u8 start = offset & 0xff;
1206         struct i2c_msg msgs[] = {
1207                 {
1208                         .addr = DRM_HDCP_DDC_ADDR,
1209                         .flags = 0,
1210                         .len = 1,
1211                         .buf = &start,
1212                 },
1213                 {
1214                         .addr = DRM_HDCP_DDC_ADDR,
1215                         .flags = I2C_M_RD,
1216                         .len = size,
1217                         .buf = buffer
1218                 }
1219         };
1220         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1221         if (ret == ARRAY_SIZE(msgs))
1222                 return 0;
1223         return ret >= 0 ? -EIO : ret;
1224 }
1225
1226 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
1227                                  unsigned int offset, void *buffer, size_t size)
1228 {
1229         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1230         struct drm_i915_private *dev_priv =
1231                 intel_dig_port->base.base.dev->dev_private;
1232         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1233                                                               hdmi->ddc_bus);
1234         int ret;
1235         u8 *write_buf;
1236         struct i2c_msg msg;
1237
1238         write_buf = kzalloc(size + 1, GFP_KERNEL);
1239         if (!write_buf)
1240                 return -ENOMEM;
1241
1242         write_buf[0] = offset & 0xff;
1243         memcpy(&write_buf[1], buffer, size);
1244
1245         msg.addr = DRM_HDCP_DDC_ADDR;
1246         msg.flags = 0,
1247         msg.len = size + 1,
1248         msg.buf = write_buf;
1249
1250         ret = i2c_transfer(adapter, &msg, 1);
1251         if (ret == 1)
1252                 ret = 0;
1253         else if (ret >= 0)
1254                 ret = -EIO;
1255
1256         kfree(write_buf);
1257         return ret;
1258 }
1259
1260 static
1261 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
1262                                   u8 *an)
1263 {
1264         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1265         struct drm_i915_private *dev_priv =
1266                 intel_dig_port->base.base.dev->dev_private;
1267         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1268                                                               hdmi->ddc_bus);
1269         int ret;
1270
1271         ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
1272                                     DRM_HDCP_AN_LEN);
1273         if (ret) {
1274                 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
1275                 return ret;
1276         }
1277
1278         ret = intel_gmbus_output_aksv(adapter);
1279         if (ret < 0) {
1280                 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
1281                 return ret;
1282         }
1283         return 0;
1284 }
1285
1286 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
1287                                      u8 *bksv)
1288 {
1289         int ret;
1290         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1291                                    DRM_HDCP_KSV_LEN);
1292         if (ret)
1293                 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1294         return ret;
1295 }
1296
1297 static
1298 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1299                                  u8 *bstatus)
1300 {
1301         int ret;
1302         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1303                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1304         if (ret)
1305                 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1306         return ret;
1307 }
1308
1309 static
1310 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1311                                      bool *repeater_present)
1312 {
1313         int ret;
1314         u8 val;
1315
1316         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1317         if (ret) {
1318                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1319                 return ret;
1320         }
1321         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1322         return 0;
1323 }
1324
1325 static
1326 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1327                                   u8 *ri_prime)
1328 {
1329         int ret;
1330         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1331                                    ri_prime, DRM_HDCP_RI_LEN);
1332         if (ret)
1333                 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1334         return ret;
1335 }
1336
1337 static
1338 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1339                                    bool *ksv_ready)
1340 {
1341         int ret;
1342         u8 val;
1343
1344         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1345         if (ret) {
1346                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1347                 return ret;
1348         }
1349         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1350         return 0;
1351 }
1352
1353 static
1354 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1355                                   int num_downstream, u8 *ksv_fifo)
1356 {
1357         int ret;
1358         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1359                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1360         if (ret) {
1361                 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1362                 return ret;
1363         }
1364         return 0;
1365 }
1366
1367 static
1368 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1369                                       int i, u32 *part)
1370 {
1371         int ret;
1372
1373         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1374                 return -EINVAL;
1375
1376         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1377                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1378         if (ret)
1379                 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1380         return ret;
1381 }
1382
1383 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1384 {
1385         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1386         struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
1387         struct drm_crtc *crtc = connector->base.state->crtc;
1388         struct intel_crtc *intel_crtc = container_of(crtc,
1389                                                      struct intel_crtc, base);
1390         u32 scanline;
1391         int ret;
1392
1393         for (;;) {
1394                 scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
1395                 if (scanline > 100 && scanline < 200)
1396                         break;
1397                 usleep_range(25, 50);
1398         }
1399
1400         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
1401         if (ret) {
1402                 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
1403                 return ret;
1404         }
1405         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
1406         if (ret) {
1407                 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
1408                 return ret;
1409         }
1410
1411         return 0;
1412 }
1413
1414 static
1415 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1416                                       bool enable)
1417 {
1418         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1419         struct intel_connector *connector = hdmi->attached_connector;
1420         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1421         int ret;
1422
1423         if (!enable)
1424                 usleep_range(6, 60); /* Bspec says >= 6us */
1425
1426         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1427         if (ret) {
1428                 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1429                           enable ? "Enable" : "Disable", ret);
1430                 return ret;
1431         }
1432
1433         /*
1434          * WA: To fix incorrect positioning of the window of
1435          * opportunity and enc_en signalling in KABYLAKE.
1436          */
1437         if (IS_KABYLAKE(dev_priv) && enable)
1438                 return kbl_repositioning_enc_en_signal(connector);
1439
1440         return 0;
1441 }
1442
1443 static
1444 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1445 {
1446         struct drm_i915_private *dev_priv =
1447                 intel_dig_port->base.base.dev->dev_private;
1448         enum port port = intel_dig_port->base.port;
1449         int ret;
1450         union {
1451                 u32 reg;
1452                 u8 shim[DRM_HDCP_RI_LEN];
1453         } ri;
1454
1455         ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1456         if (ret)
1457                 return false;
1458
1459         I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1460
1461         /* Wait for Ri prime match */
1462         if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1463                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1464                 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1465                           I915_READ(PORT_HDCP_STATUS(port)));
1466                 return false;
1467         }
1468         return true;
1469 }
1470
1471 static struct hdcp2_hdmi_msg_data {
1472         u8 msg_id;
1473         u32 timeout;
1474         u32 timeout2;
1475         } hdcp2_msg_data[] = {
1476                 {HDCP_2_2_AKE_INIT, 0, 0},
1477                 {HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0},
1478                 {HDCP_2_2_AKE_NO_STORED_KM, 0, 0},
1479                 {HDCP_2_2_AKE_STORED_KM, 0, 0},
1480                 {HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
1481                                 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS},
1482                 {HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS,
1483                                 0},
1484                 {HDCP_2_2_LC_INIT, 0, 0},
1485                 {HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0},
1486                 {HDCP_2_2_SKE_SEND_EKS, 0, 0},
1487                 {HDCP_2_2_REP_SEND_RECVID_LIST,
1488                                 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0},
1489                 {HDCP_2_2_REP_SEND_ACK, 0, 0},
1490                 {HDCP_2_2_REP_STREAM_MANAGE, 0, 0},
1491                 {HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS,
1492                                 0},
1493         };
1494
1495 static
1496 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
1497                                     u8 *rx_status)
1498 {
1499         return intel_hdmi_hdcp_read(intel_dig_port,
1500                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1501                                     rx_status,
1502                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1503 }
1504
1505 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1506 {
1507         int i;
1508
1509         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
1510                 if (hdcp2_msg_data[i].msg_id == msg_id &&
1511                     (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
1512                         return hdcp2_msg_data[i].timeout;
1513                 else if (hdcp2_msg_data[i].msg_id == msg_id)
1514                         return hdcp2_msg_data[i].timeout2;
1515
1516         return -EINVAL;
1517 }
1518
1519 static inline
1520 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
1521                                   u8 msg_id, bool *msg_ready,
1522                                   ssize_t *msg_sz)
1523 {
1524         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1525         int ret;
1526
1527         ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
1528         if (ret < 0) {
1529                 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
1530                 return ret;
1531         }
1532
1533         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1534                   rx_status[0]);
1535
1536         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1537                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1538                              *msg_sz);
1539         else
1540                 *msg_ready = *msg_sz;
1541
1542         return 0;
1543 }
1544
1545 static ssize_t
1546 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
1547                               u8 msg_id, bool paired)
1548 {
1549         bool msg_ready = false;
1550         int timeout, ret;
1551         ssize_t msg_sz = 0;
1552
1553         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1554         if (timeout < 0)
1555                 return timeout;
1556
1557         ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
1558                                                              msg_id, &msg_ready,
1559                                                              &msg_sz),
1560                          !ret && msg_ready && msg_sz, timeout * 1000,
1561                          1000, 5 * 1000);
1562         if (ret)
1563                 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1564                               msg_id, ret, timeout);
1565
1566         return ret ? ret : msg_sz;
1567 }
1568
1569 static
1570 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
1571                                void *buf, size_t size)
1572 {
1573         unsigned int offset;
1574
1575         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1576         return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
1577 }
1578
1579 static
1580 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
1581                               u8 msg_id, void *buf, size_t size)
1582 {
1583         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1584         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1585         unsigned int offset;
1586         ssize_t ret;
1587
1588         ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
1589                                             hdcp->is_paired);
1590         if (ret < 0)
1591                 return ret;
1592
1593         /*
1594          * Available msg size should be equal to or lesser than the
1595          * available buffer.
1596          */
1597         if (ret > size) {
1598                 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1599                               ret, size);
1600                 return -1;
1601         }
1602
1603         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1604         ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
1605         if (ret)
1606                 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
1607
1608         return ret;
1609 }
1610
1611 static
1612 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
1613 {
1614         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1615         int ret;
1616
1617         ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
1618         if (ret)
1619                 return ret;
1620
1621         /*
1622          * Re-auth request and Link Integrity Failures are represented by
1623          * same bit. i.e reauth_req.
1624          */
1625         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1626                 ret = HDCP_REAUTH_REQUEST;
1627         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1628                 ret = HDCP_TOPOLOGY_CHANGE;
1629
1630         return ret;
1631 }
1632
1633 static
1634 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
1635                              bool *capable)
1636 {
1637         u8 hdcp2_version;
1638         int ret;
1639
1640         *capable = false;
1641         ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1642                                    &hdcp2_version, sizeof(hdcp2_version));
1643         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1644                 *capable = true;
1645
1646         return ret;
1647 }
1648
1649 static inline
1650 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
1651 {
1652         return HDCP_PROTOCOL_HDMI;
1653 }
1654
1655 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1656         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1657         .read_bksv = intel_hdmi_hdcp_read_bksv,
1658         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1659         .repeater_present = intel_hdmi_hdcp_repeater_present,
1660         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1661         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1662         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1663         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1664         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1665         .check_link = intel_hdmi_hdcp_check_link,
1666         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1667         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1668         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1669         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1670         .protocol = HDCP_PROTOCOL_HDMI,
1671 };
1672
1673 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1674                                const struct intel_crtc_state *crtc_state)
1675 {
1676         struct drm_device *dev = encoder->base.dev;
1677         struct drm_i915_private *dev_priv = to_i915(dev);
1678         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1679         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1680         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1681         u32 hdmi_val;
1682
1683         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1684
1685         hdmi_val = SDVO_ENCODING_HDMI;
1686         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1687                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1688         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1689                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1690         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1691                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1692
1693         if (crtc_state->pipe_bpp > 24)
1694                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1695         else
1696                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1697
1698         if (crtc_state->has_hdmi_sink)
1699                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1700
1701         if (HAS_PCH_CPT(dev_priv))
1702                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1703         else if (IS_CHERRYVIEW(dev_priv))
1704                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1705         else
1706                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1707
1708         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1709         POSTING_READ(intel_hdmi->hdmi_reg);
1710 }
1711
1712 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1713                                     enum pipe *pipe)
1714 {
1715         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1716         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1717         intel_wakeref_t wakeref;
1718         bool ret;
1719
1720         wakeref = intel_display_power_get_if_enabled(dev_priv,
1721                                                      encoder->power_domain);
1722         if (!wakeref)
1723                 return false;
1724
1725         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1726
1727         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1728
1729         return ret;
1730 }
1731
1732 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1733                                   struct intel_crtc_state *pipe_config)
1734 {
1735         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1736         struct drm_device *dev = encoder->base.dev;
1737         struct drm_i915_private *dev_priv = to_i915(dev);
1738         u32 tmp, flags = 0;
1739         int dotclock;
1740
1741         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1742
1743         tmp = I915_READ(intel_hdmi->hdmi_reg);
1744
1745         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1746                 flags |= DRM_MODE_FLAG_PHSYNC;
1747         else
1748                 flags |= DRM_MODE_FLAG_NHSYNC;
1749
1750         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1751                 flags |= DRM_MODE_FLAG_PVSYNC;
1752         else
1753                 flags |= DRM_MODE_FLAG_NVSYNC;
1754
1755         if (tmp & HDMI_MODE_SELECT_HDMI)
1756                 pipe_config->has_hdmi_sink = true;
1757
1758         pipe_config->infoframes.enable |=
1759                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1760
1761         if (pipe_config->infoframes.enable)
1762                 pipe_config->has_infoframe = true;
1763
1764         if (tmp & SDVO_AUDIO_ENABLE)
1765                 pipe_config->has_audio = true;
1766
1767         if (!HAS_PCH_SPLIT(dev_priv) &&
1768             tmp & HDMI_COLOR_RANGE_16_235)
1769                 pipe_config->limited_color_range = true;
1770
1771         pipe_config->base.adjusted_mode.flags |= flags;
1772
1773         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1774                 dotclock = pipe_config->port_clock * 2 / 3;
1775         else
1776                 dotclock = pipe_config->port_clock;
1777
1778         if (pipe_config->pixel_multiplier)
1779                 dotclock /= pipe_config->pixel_multiplier;
1780
1781         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1782
1783         pipe_config->lane_count = 4;
1784
1785         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1786
1787         intel_read_infoframe(encoder, pipe_config,
1788                              HDMI_INFOFRAME_TYPE_AVI,
1789                              &pipe_config->infoframes.avi);
1790         intel_read_infoframe(encoder, pipe_config,
1791                              HDMI_INFOFRAME_TYPE_SPD,
1792                              &pipe_config->infoframes.spd);
1793         intel_read_infoframe(encoder, pipe_config,
1794                              HDMI_INFOFRAME_TYPE_VENDOR,
1795                              &pipe_config->infoframes.hdmi);
1796 }
1797
1798 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1799                                     const struct intel_crtc_state *pipe_config,
1800                                     const struct drm_connector_state *conn_state)
1801 {
1802         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1803
1804         WARN_ON(!pipe_config->has_hdmi_sink);
1805         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1806                          pipe_name(crtc->pipe));
1807         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1808 }
1809
1810 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1811                             const struct intel_crtc_state *pipe_config,
1812                             const struct drm_connector_state *conn_state)
1813 {
1814         struct drm_device *dev = encoder->base.dev;
1815         struct drm_i915_private *dev_priv = to_i915(dev);
1816         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1817         u32 temp;
1818
1819         temp = I915_READ(intel_hdmi->hdmi_reg);
1820
1821         temp |= SDVO_ENABLE;
1822         if (pipe_config->has_audio)
1823                 temp |= SDVO_AUDIO_ENABLE;
1824
1825         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1826         POSTING_READ(intel_hdmi->hdmi_reg);
1827
1828         if (pipe_config->has_audio)
1829                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1830 }
1831
1832 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1833                             const struct intel_crtc_state *pipe_config,
1834                             const struct drm_connector_state *conn_state)
1835 {
1836         struct drm_device *dev = encoder->base.dev;
1837         struct drm_i915_private *dev_priv = to_i915(dev);
1838         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1839         u32 temp;
1840
1841         temp = I915_READ(intel_hdmi->hdmi_reg);
1842
1843         temp |= SDVO_ENABLE;
1844         if (pipe_config->has_audio)
1845                 temp |= SDVO_AUDIO_ENABLE;
1846
1847         /*
1848          * HW workaround, need to write this twice for issue
1849          * that may result in first write getting masked.
1850          */
1851         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1852         POSTING_READ(intel_hdmi->hdmi_reg);
1853         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1854         POSTING_READ(intel_hdmi->hdmi_reg);
1855
1856         /*
1857          * HW workaround, need to toggle enable bit off and on
1858          * for 12bpc with pixel repeat.
1859          *
1860          * FIXME: BSpec says this should be done at the end of
1861          * of the modeset sequence, so not sure if this isn't too soon.
1862          */
1863         if (pipe_config->pipe_bpp > 24 &&
1864             pipe_config->pixel_multiplier > 1) {
1865                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1866                 POSTING_READ(intel_hdmi->hdmi_reg);
1867
1868                 /*
1869                  * HW workaround, need to write this twice for issue
1870                  * that may result in first write getting masked.
1871                  */
1872                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1873                 POSTING_READ(intel_hdmi->hdmi_reg);
1874                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1875                 POSTING_READ(intel_hdmi->hdmi_reg);
1876         }
1877
1878         if (pipe_config->has_audio)
1879                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1880 }
1881
1882 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1883                             const struct intel_crtc_state *pipe_config,
1884                             const struct drm_connector_state *conn_state)
1885 {
1886         struct drm_device *dev = encoder->base.dev;
1887         struct drm_i915_private *dev_priv = to_i915(dev);
1888         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1889         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1890         enum pipe pipe = crtc->pipe;
1891         u32 temp;
1892
1893         temp = I915_READ(intel_hdmi->hdmi_reg);
1894
1895         temp |= SDVO_ENABLE;
1896         if (pipe_config->has_audio)
1897                 temp |= SDVO_AUDIO_ENABLE;
1898
1899         /*
1900          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1901          *
1902          * The procedure for 12bpc is as follows:
1903          * 1. disable HDMI clock gating
1904          * 2. enable HDMI with 8bpc
1905          * 3. enable HDMI with 12bpc
1906          * 4. enable HDMI clock gating
1907          */
1908
1909         if (pipe_config->pipe_bpp > 24) {
1910                 I915_WRITE(TRANS_CHICKEN1(pipe),
1911                            I915_READ(TRANS_CHICKEN1(pipe)) |
1912                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1913
1914                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1915                 temp |= SDVO_COLOR_FORMAT_8bpc;
1916         }
1917
1918         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1919         POSTING_READ(intel_hdmi->hdmi_reg);
1920
1921         if (pipe_config->pipe_bpp > 24) {
1922                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1923                 temp |= HDMI_COLOR_FORMAT_12bpc;
1924
1925                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1926                 POSTING_READ(intel_hdmi->hdmi_reg);
1927
1928                 I915_WRITE(TRANS_CHICKEN1(pipe),
1929                            I915_READ(TRANS_CHICKEN1(pipe)) &
1930                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1931         }
1932
1933         if (pipe_config->has_audio)
1934                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1935 }
1936
1937 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1938                             const struct intel_crtc_state *pipe_config,
1939                             const struct drm_connector_state *conn_state)
1940 {
1941 }
1942
1943 static void intel_disable_hdmi(struct intel_encoder *encoder,
1944                                const struct intel_crtc_state *old_crtc_state,
1945                                const struct drm_connector_state *old_conn_state)
1946 {
1947         struct drm_device *dev = encoder->base.dev;
1948         struct drm_i915_private *dev_priv = to_i915(dev);
1949         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1950         struct intel_digital_port *intel_dig_port =
1951                 hdmi_to_dig_port(intel_hdmi);
1952         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1953         u32 temp;
1954
1955         temp = I915_READ(intel_hdmi->hdmi_reg);
1956
1957         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1958         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1959         POSTING_READ(intel_hdmi->hdmi_reg);
1960
1961         /*
1962          * HW workaround for IBX, we need to move the port
1963          * to transcoder A after disabling it to allow the
1964          * matching DP port to be enabled on transcoder A.
1965          */
1966         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1967                 /*
1968                  * We get CPU/PCH FIFO underruns on the other pipe when
1969                  * doing the workaround. Sweep them under the rug.
1970                  */
1971                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1972                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1973
1974                 temp &= ~SDVO_PIPE_SEL_MASK;
1975                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1976                 /*
1977                  * HW workaround, need to write this twice for issue
1978                  * that may result in first write getting masked.
1979                  */
1980                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1981                 POSTING_READ(intel_hdmi->hdmi_reg);
1982                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1983                 POSTING_READ(intel_hdmi->hdmi_reg);
1984
1985                 temp &= ~SDVO_ENABLE;
1986                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1987                 POSTING_READ(intel_hdmi->hdmi_reg);
1988
1989                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1990                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1991                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1992         }
1993
1994         intel_dig_port->set_infoframes(encoder,
1995                                        false,
1996                                        old_crtc_state, old_conn_state);
1997
1998         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1999 }
2000
2001 static void g4x_disable_hdmi(struct intel_encoder *encoder,
2002                              const struct intel_crtc_state *old_crtc_state,
2003                              const struct drm_connector_state *old_conn_state)
2004 {
2005         if (old_crtc_state->has_audio)
2006                 intel_audio_codec_disable(encoder,
2007                                           old_crtc_state, old_conn_state);
2008
2009         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2010 }
2011
2012 static void pch_disable_hdmi(struct intel_encoder *encoder,
2013                              const struct intel_crtc_state *old_crtc_state,
2014                              const struct drm_connector_state *old_conn_state)
2015 {
2016         if (old_crtc_state->has_audio)
2017                 intel_audio_codec_disable(encoder,
2018                                           old_crtc_state, old_conn_state);
2019 }
2020
2021 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
2022                                   const struct intel_crtc_state *old_crtc_state,
2023                                   const struct drm_connector_state *old_conn_state)
2024 {
2025         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2026 }
2027
2028 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2029 {
2030         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2031         const struct ddi_vbt_port_info *info =
2032                 &dev_priv->vbt.ddi_port_info[encoder->port];
2033         int max_tmds_clock;
2034
2035         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2036                 max_tmds_clock = 594000;
2037         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2038                 max_tmds_clock = 300000;
2039         else if (INTEL_GEN(dev_priv) >= 5)
2040                 max_tmds_clock = 225000;
2041         else
2042                 max_tmds_clock = 165000;
2043
2044         if (info->max_tmds_clock)
2045                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
2046
2047         return max_tmds_clock;
2048 }
2049
2050 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2051                                  bool respect_downstream_limits,
2052                                  bool force_dvi)
2053 {
2054         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2055         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2056
2057         if (respect_downstream_limits) {
2058                 struct intel_connector *connector = hdmi->attached_connector;
2059                 const struct drm_display_info *info = &connector->base.display_info;
2060
2061                 if (hdmi->dp_dual_mode.max_tmds_clock)
2062                         max_tmds_clock = min(max_tmds_clock,
2063                                              hdmi->dp_dual_mode.max_tmds_clock);
2064
2065                 if (info->max_tmds_clock)
2066                         max_tmds_clock = min(max_tmds_clock,
2067                                              info->max_tmds_clock);
2068                 else if (!hdmi->has_hdmi_sink || force_dvi)
2069                         max_tmds_clock = min(max_tmds_clock, 165000);
2070         }
2071
2072         return max_tmds_clock;
2073 }
2074
2075 static enum drm_mode_status
2076 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2077                       int clock, bool respect_downstream_limits,
2078                       bool force_dvi)
2079 {
2080         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2081
2082         if (clock < 25000)
2083                 return MODE_CLOCK_LOW;
2084         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
2085                 return MODE_CLOCK_HIGH;
2086
2087         /* BXT DPLL can't generate 223-240 MHz */
2088         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2089                 return MODE_CLOCK_RANGE;
2090
2091         /* CHV DPLL can't generate 216-240 MHz */
2092         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2093                 return MODE_CLOCK_RANGE;
2094
2095         return MODE_OK;
2096 }
2097
2098 static enum drm_mode_status
2099 intel_hdmi_mode_valid(struct drm_connector *connector,
2100                       struct drm_display_mode *mode)
2101 {
2102         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2103         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2104         struct drm_i915_private *dev_priv = to_i915(dev);
2105         enum drm_mode_status status;
2106         int clock;
2107         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2108         bool force_dvi =
2109                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
2110
2111         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2112                 return MODE_NO_DBLESCAN;
2113
2114         clock = mode->clock;
2115
2116         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2117                 clock *= 2;
2118
2119         if (clock > max_dotclk)
2120                 return MODE_CLOCK_HIGH;
2121
2122         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2123                 clock *= 2;
2124
2125         if (drm_mode_is_420_only(&connector->display_info, mode))
2126                 clock /= 2;
2127
2128         /* check if we can do 8bpc */
2129         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
2130
2131         if (hdmi->has_hdmi_sink && !force_dvi) {
2132                 /* if we can't do 8bpc we may still be able to do 12bpc */
2133                 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2134                         status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2135                                                        true, force_dvi);
2136
2137                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2138                 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2139                         status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2140                                                        true, force_dvi);
2141         }
2142
2143         return status;
2144 }
2145
2146 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2147                                      int bpc)
2148 {
2149         struct drm_i915_private *dev_priv =
2150                 to_i915(crtc_state->base.crtc->dev);
2151         struct drm_atomic_state *state = crtc_state->base.state;
2152         struct drm_connector_state *connector_state;
2153         struct drm_connector *connector;
2154         const struct drm_display_mode *adjusted_mode =
2155                 &crtc_state->base.adjusted_mode;
2156         int i;
2157
2158         if (HAS_GMCH(dev_priv))
2159                 return false;
2160
2161         if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2162                 return false;
2163
2164         if (crtc_state->pipe_bpp <= 8*3)
2165                 return false;
2166
2167         if (!crtc_state->has_hdmi_sink)
2168                 return false;
2169
2170         /*
2171          * HDMI deep color affects the clocks, so it's only possible
2172          * when not cloning with other encoder types.
2173          */
2174         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2175                 return false;
2176
2177         for_each_new_connector_in_state(state, connector, connector_state, i) {
2178                 const struct drm_display_info *info = &connector->display_info;
2179
2180                 if (connector_state->crtc != crtc_state->base.crtc)
2181                         continue;
2182
2183                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2184                         const struct drm_hdmi_info *hdmi = &info->hdmi;
2185
2186                         if (bpc == 12 && !(hdmi->y420_dc_modes &
2187                                            DRM_EDID_YCBCR420_DC_36))
2188                                 return false;
2189                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
2190                                                 DRM_EDID_YCBCR420_DC_30))
2191                                 return false;
2192                 } else {
2193                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2194                                            DRM_EDID_HDMI_DC_36))
2195                                 return false;
2196                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2197                                                 DRM_EDID_HDMI_DC_30))
2198                                 return false;
2199                 }
2200         }
2201
2202         /* Display WA #1139: glk */
2203         if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
2204             adjusted_mode->htotal > 5460)
2205                 return false;
2206
2207         /* Display Wa_1405510057:icl */
2208         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2209             bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
2210             (adjusted_mode->crtc_hblank_end -
2211              adjusted_mode->crtc_hblank_start) % 8 == 2)
2212                 return false;
2213
2214         return true;
2215 }
2216
2217 static bool
2218 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
2219                            struct intel_crtc_state *config,
2220                            int *clock_12bpc, int *clock_10bpc,
2221                            int *clock_8bpc)
2222 {
2223         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
2224
2225         if (!connector->ycbcr_420_allowed) {
2226                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2227                 return false;
2228         }
2229
2230         /* YCBCR420 TMDS rate requirement is half the pixel clock */
2231         config->port_clock /= 2;
2232         *clock_12bpc /= 2;
2233         *clock_10bpc /= 2;
2234         *clock_8bpc /= 2;
2235         config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2236
2237         /* YCBCR 420 output conversion needs a scaler */
2238         if (skl_update_scaler_crtc(config)) {
2239                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2240                 return false;
2241         }
2242
2243         intel_pch_panel_fitting(intel_crtc, config,
2244                                 DRM_MODE_SCALE_FULLSCREEN);
2245
2246         return true;
2247 }
2248
2249 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2250                               struct intel_crtc_state *pipe_config,
2251                               struct drm_connector_state *conn_state)
2252 {
2253         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2254         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2255         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2256         struct drm_connector *connector = conn_state->connector;
2257         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2258         struct intel_digital_connector_state *intel_conn_state =
2259                 to_intel_digital_connector_state(conn_state);
2260         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
2261         int clock_10bpc = clock_8bpc * 5 / 4;
2262         int clock_12bpc = clock_8bpc * 3 / 2;
2263         int desired_bpp;
2264         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
2265
2266         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2267                 return -EINVAL;
2268
2269         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2270         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
2271
2272         if (pipe_config->has_hdmi_sink)
2273                 pipe_config->has_infoframe = true;
2274
2275         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2276                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2277                 pipe_config->limited_color_range =
2278                         pipe_config->has_hdmi_sink &&
2279                         drm_default_rgb_quant_range(adjusted_mode) ==
2280                         HDMI_QUANTIZATION_RANGE_LIMITED;
2281         } else {
2282                 pipe_config->limited_color_range =
2283                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2284         }
2285
2286         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
2287                 pipe_config->pixel_multiplier = 2;
2288                 clock_8bpc *= 2;
2289                 clock_10bpc *= 2;
2290                 clock_12bpc *= 2;
2291         }
2292
2293         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
2294                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
2295                                                 &clock_12bpc, &clock_10bpc,
2296                                                 &clock_8bpc)) {
2297                         DRM_ERROR("Can't support YCBCR420 output\n");
2298                         return -EINVAL;
2299                 }
2300         }
2301
2302         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2303                 pipe_config->has_pch_encoder = true;
2304
2305         if (pipe_config->has_hdmi_sink) {
2306                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2307                         pipe_config->has_audio = intel_hdmi->has_audio;
2308                 else
2309                         pipe_config->has_audio =
2310                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2311         }
2312
2313         /*
2314          * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
2315          * to check that the higher clock still fits within limits.
2316          */
2317         if (hdmi_deep_color_possible(pipe_config, 12) &&
2318             hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
2319                                   true, force_dvi) == MODE_OK) {
2320                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
2321                 desired_bpp = 12*3;
2322
2323                 /* Need to adjust the port link by 1.5x for 12bpc. */
2324                 pipe_config->port_clock = clock_12bpc;
2325         } else if (hdmi_deep_color_possible(pipe_config, 10) &&
2326                    hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
2327                                          true, force_dvi) == MODE_OK) {
2328                 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
2329                 desired_bpp = 10 * 3;
2330
2331                 /* Need to adjust the port link by 1.25x for 10bpc. */
2332                 pipe_config->port_clock = clock_10bpc;
2333         } else {
2334                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
2335                 desired_bpp = 8*3;
2336
2337                 pipe_config->port_clock = clock_8bpc;
2338         }
2339
2340         if (!pipe_config->bw_constrained) {
2341                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
2342                 pipe_config->pipe_bpp = desired_bpp;
2343         }
2344
2345         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
2346                                   false, force_dvi) != MODE_OK) {
2347                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
2348                 return -EINVAL;
2349         }
2350
2351         /* Set user selected PAR to incoming mode's member */
2352         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
2353
2354         pipe_config->lane_count = 4;
2355
2356         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2357                                            IS_GEMINILAKE(dev_priv))) {
2358                 if (scdc->scrambling.low_rates)
2359                         pipe_config->hdmi_scrambling = true;
2360
2361                 if (pipe_config->port_clock > 340000) {
2362                         pipe_config->hdmi_scrambling = true;
2363                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2364                 }
2365         }
2366
2367         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state);
2368
2369         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2370                 DRM_DEBUG_KMS("bad AVI infoframe\n");
2371                 return -EINVAL;
2372         }
2373
2374         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2375                 DRM_DEBUG_KMS("bad SPD infoframe\n");
2376                 return -EINVAL;
2377         }
2378
2379         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2380                 DRM_DEBUG_KMS("bad HDMI infoframe\n");
2381                 return -EINVAL;
2382         }
2383
2384         return 0;
2385 }
2386
2387 static void
2388 intel_hdmi_unset_edid(struct drm_connector *connector)
2389 {
2390         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2391
2392         intel_hdmi->has_hdmi_sink = false;
2393         intel_hdmi->has_audio = false;
2394
2395         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2396         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2397
2398         kfree(to_intel_connector(connector)->detect_edid);
2399         to_intel_connector(connector)->detect_edid = NULL;
2400 }
2401
2402 static void
2403 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2404 {
2405         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2406         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2407         enum port port = hdmi_to_dig_port(hdmi)->base.port;
2408         struct i2c_adapter *adapter =
2409                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2410         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2411
2412         /*
2413          * Type 1 DVI adaptors are not required to implement any
2414          * registers, so we can't always detect their presence.
2415          * Ideally we should be able to check the state of the
2416          * CONFIG1 pin, but no such luck on our hardware.
2417          *
2418          * The only method left to us is to check the VBT to see
2419          * if the port is a dual mode capable DP port. But let's
2420          * only do that when we sucesfully read the EDID, to avoid
2421          * confusing log messages about DP dual mode adaptors when
2422          * there's nothing connected to the port.
2423          */
2424         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2425                 /* An overridden EDID imply that we want this port for testing.
2426                  * Make sure not to set limits for that port.
2427                  */
2428                 if (has_edid && !connector->override_edid &&
2429                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2430                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2431                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2432                 } else {
2433                         type = DRM_DP_DUAL_MODE_NONE;
2434                 }
2435         }
2436
2437         if (type == DRM_DP_DUAL_MODE_NONE)
2438                 return;
2439
2440         hdmi->dp_dual_mode.type = type;
2441         hdmi->dp_dual_mode.max_tmds_clock =
2442                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2443
2444         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2445                       drm_dp_get_dual_mode_type_name(type),
2446                       hdmi->dp_dual_mode.max_tmds_clock);
2447 }
2448
2449 static bool
2450 intel_hdmi_set_edid(struct drm_connector *connector)
2451 {
2452         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2453         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2454         intel_wakeref_t wakeref;
2455         struct edid *edid;
2456         bool connected = false;
2457         struct i2c_adapter *i2c;
2458
2459         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2460
2461         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2462
2463         edid = drm_get_edid(connector, i2c);
2464
2465         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2466                 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2467                 intel_gmbus_force_bit(i2c, true);
2468                 edid = drm_get_edid(connector, i2c);
2469                 intel_gmbus_force_bit(i2c, false);
2470         }
2471
2472         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2473
2474         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2475
2476         to_intel_connector(connector)->detect_edid = edid;
2477         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2478                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2479                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2480
2481                 connected = true;
2482         }
2483
2484         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2485
2486         return connected;
2487 }
2488
2489 static enum drm_connector_status
2490 intel_hdmi_detect(struct drm_connector *connector, bool force)
2491 {
2492         enum drm_connector_status status = connector_status_disconnected;
2493         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2494         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2495         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2496         intel_wakeref_t wakeref;
2497
2498         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2499                       connector->base.id, connector->name);
2500
2501         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2502
2503         if (INTEL_GEN(dev_priv) >= 11 &&
2504             !intel_digital_port_connected(encoder))
2505                 goto out;
2506
2507         intel_hdmi_unset_edid(connector);
2508
2509         if (intel_hdmi_set_edid(connector))
2510                 status = connector_status_connected;
2511
2512 out:
2513         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2514
2515         if (status != connector_status_connected)
2516                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2517
2518         return status;
2519 }
2520
2521 static void
2522 intel_hdmi_force(struct drm_connector *connector)
2523 {
2524         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2525                       connector->base.id, connector->name);
2526
2527         intel_hdmi_unset_edid(connector);
2528
2529         if (connector->status != connector_status_connected)
2530                 return;
2531
2532         intel_hdmi_set_edid(connector);
2533 }
2534
2535 static int intel_hdmi_get_modes(struct drm_connector *connector)
2536 {
2537         struct edid *edid;
2538
2539         edid = to_intel_connector(connector)->detect_edid;
2540         if (edid == NULL)
2541                 return 0;
2542
2543         return intel_connector_update_modes(connector, edid);
2544 }
2545
2546 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
2547                                   const struct intel_crtc_state *pipe_config,
2548                                   const struct drm_connector_state *conn_state)
2549 {
2550         struct intel_digital_port *intel_dig_port =
2551                 enc_to_dig_port(&encoder->base);
2552
2553         intel_hdmi_prepare(encoder, pipe_config);
2554
2555         intel_dig_port->set_infoframes(encoder,
2556                                        pipe_config->has_infoframe,
2557                                        pipe_config, conn_state);
2558 }
2559
2560 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2561                                 const struct intel_crtc_state *pipe_config,
2562                                 const struct drm_connector_state *conn_state)
2563 {
2564         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2565         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2566
2567         vlv_phy_pre_encoder_enable(encoder, pipe_config);
2568
2569         /* HDMI 1.0V-2dB */
2570         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2571                                  0x2b247878);
2572
2573         dport->set_infoframes(encoder,
2574                               pipe_config->has_infoframe,
2575                               pipe_config, conn_state);
2576
2577         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2578
2579         vlv_wait_port_ready(dev_priv, dport, 0x0);
2580 }
2581
2582 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2583                                     const struct intel_crtc_state *pipe_config,
2584                                     const struct drm_connector_state *conn_state)
2585 {
2586         intel_hdmi_prepare(encoder, pipe_config);
2587
2588         vlv_phy_pre_pll_enable(encoder, pipe_config);
2589 }
2590
2591 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2592                                     const struct intel_crtc_state *pipe_config,
2593                                     const struct drm_connector_state *conn_state)
2594 {
2595         intel_hdmi_prepare(encoder, pipe_config);
2596
2597         chv_phy_pre_pll_enable(encoder, pipe_config);
2598 }
2599
2600 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2601                                       const struct intel_crtc_state *old_crtc_state,
2602                                       const struct drm_connector_state *old_conn_state)
2603 {
2604         chv_phy_post_pll_disable(encoder, old_crtc_state);
2605 }
2606
2607 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2608                                   const struct intel_crtc_state *old_crtc_state,
2609                                   const struct drm_connector_state *old_conn_state)
2610 {
2611         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2612         vlv_phy_reset_lanes(encoder, old_crtc_state);
2613 }
2614
2615 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2616                                   const struct intel_crtc_state *old_crtc_state,
2617                                   const struct drm_connector_state *old_conn_state)
2618 {
2619         struct drm_device *dev = encoder->base.dev;
2620         struct drm_i915_private *dev_priv = to_i915(dev);
2621
2622         mutex_lock(&dev_priv->sb_lock);
2623
2624         /* Assert data lane reset */
2625         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2626
2627         mutex_unlock(&dev_priv->sb_lock);
2628 }
2629
2630 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2631                                 const struct intel_crtc_state *pipe_config,
2632                                 const struct drm_connector_state *conn_state)
2633 {
2634         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2635         struct drm_device *dev = encoder->base.dev;
2636         struct drm_i915_private *dev_priv = to_i915(dev);
2637
2638         chv_phy_pre_encoder_enable(encoder, pipe_config);
2639
2640         /* FIXME: Program the support xxx V-dB */
2641         /* Use 800mV-0dB */
2642         chv_set_phy_signal_level(encoder, 128, 102, false);
2643
2644         dport->set_infoframes(encoder,
2645                               pipe_config->has_infoframe,
2646                               pipe_config, conn_state);
2647
2648         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2649
2650         vlv_wait_port_ready(dev_priv, dport, 0x0);
2651
2652         /* Second common lane will stay alive on its own now */
2653         chv_phy_release_cl2_override(encoder);
2654 }
2655
2656 static int
2657 intel_hdmi_connector_register(struct drm_connector *connector)
2658 {
2659         int ret;
2660
2661         ret = intel_connector_register(connector);
2662         if (ret)
2663                 return ret;
2664
2665         i915_debugfs_connector_add(connector);
2666
2667         return ret;
2668 }
2669
2670 static void intel_hdmi_destroy(struct drm_connector *connector)
2671 {
2672         if (intel_attached_hdmi(connector)->cec_notifier)
2673                 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2674
2675         intel_connector_destroy(connector);
2676 }
2677
2678 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2679         .detect = intel_hdmi_detect,
2680         .force = intel_hdmi_force,
2681         .fill_modes = drm_helper_probe_single_connector_modes,
2682         .atomic_get_property = intel_digital_connector_atomic_get_property,
2683         .atomic_set_property = intel_digital_connector_atomic_set_property,
2684         .late_register = intel_hdmi_connector_register,
2685         .early_unregister = intel_connector_unregister,
2686         .destroy = intel_hdmi_destroy,
2687         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2688         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2689 };
2690
2691 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2692         .get_modes = intel_hdmi_get_modes,
2693         .mode_valid = intel_hdmi_mode_valid,
2694         .atomic_check = intel_digital_connector_atomic_check,
2695 };
2696
2697 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2698         .destroy = intel_encoder_destroy,
2699 };
2700
2701 static void
2702 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2703 {
2704         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2705         struct intel_digital_port *intel_dig_port =
2706                                 hdmi_to_dig_port(intel_hdmi);
2707
2708         intel_attach_force_audio_property(connector);
2709         intel_attach_broadcast_rgb_property(connector);
2710         intel_attach_aspect_ratio_property(connector);
2711
2712         /*
2713          * Attach Colorspace property for Non LSPCON based device
2714          * ToDo: This needs to be extended for LSPCON implementation
2715          * as well. Will be implemented separately.
2716          */
2717         if (!intel_dig_port->lspcon.active)
2718                 intel_attach_colorspace_property(connector);
2719
2720         drm_connector_attach_content_type_property(connector);
2721         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2722
2723         if (!HAS_GMCH(dev_priv))
2724                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2725 }
2726
2727 /*
2728  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2729  * @encoder: intel_encoder
2730  * @connector: drm_connector
2731  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2732  *  or reset the high tmds clock ratio for scrambling
2733  * @scrambling: bool to Indicate if the function needs to set or reset
2734  *  sink scrambling
2735  *
2736  * This function handles scrambling on HDMI 2.0 capable sinks.
2737  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2738  * it enables scrambling. This should be called before enabling the HDMI
2739  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2740  * detect a scrambled clock within 100 ms.
2741  *
2742  * Returns:
2743  * True on success, false on failure.
2744  */
2745 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2746                                        struct drm_connector *connector,
2747                                        bool high_tmds_clock_ratio,
2748                                        bool scrambling)
2749 {
2750         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2751         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2752         struct drm_scrambling *sink_scrambling =
2753                 &connector->display_info.hdmi.scdc.scrambling;
2754         struct i2c_adapter *adapter =
2755                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2756
2757         if (!sink_scrambling->supported)
2758                 return true;
2759
2760         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2761                       connector->base.id, connector->name,
2762                       yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2763
2764         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2765         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2766                                                   high_tmds_clock_ratio) &&
2767                 drm_scdc_set_scrambling(adapter, scrambling);
2768 }
2769
2770 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2771 {
2772         u8 ddc_pin;
2773
2774         switch (port) {
2775         case PORT_B:
2776                 ddc_pin = GMBUS_PIN_DPB;
2777                 break;
2778         case PORT_C:
2779                 ddc_pin = GMBUS_PIN_DPC;
2780                 break;
2781         case PORT_D:
2782                 ddc_pin = GMBUS_PIN_DPD_CHV;
2783                 break;
2784         default:
2785                 MISSING_CASE(port);
2786                 ddc_pin = GMBUS_PIN_DPB;
2787                 break;
2788         }
2789         return ddc_pin;
2790 }
2791
2792 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2793 {
2794         u8 ddc_pin;
2795
2796         switch (port) {
2797         case PORT_B:
2798                 ddc_pin = GMBUS_PIN_1_BXT;
2799                 break;
2800         case PORT_C:
2801                 ddc_pin = GMBUS_PIN_2_BXT;
2802                 break;
2803         default:
2804                 MISSING_CASE(port);
2805                 ddc_pin = GMBUS_PIN_1_BXT;
2806                 break;
2807         }
2808         return ddc_pin;
2809 }
2810
2811 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2812                               enum port port)
2813 {
2814         u8 ddc_pin;
2815
2816         switch (port) {
2817         case PORT_B:
2818                 ddc_pin = GMBUS_PIN_1_BXT;
2819                 break;
2820         case PORT_C:
2821                 ddc_pin = GMBUS_PIN_2_BXT;
2822                 break;
2823         case PORT_D:
2824                 ddc_pin = GMBUS_PIN_4_CNP;
2825                 break;
2826         case PORT_F:
2827                 ddc_pin = GMBUS_PIN_3_BXT;
2828                 break;
2829         default:
2830                 MISSING_CASE(port);
2831                 ddc_pin = GMBUS_PIN_1_BXT;
2832                 break;
2833         }
2834         return ddc_pin;
2835 }
2836
2837 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2838 {
2839         u8 ddc_pin;
2840
2841         switch (port) {
2842         case PORT_A:
2843                 ddc_pin = GMBUS_PIN_1_BXT;
2844                 break;
2845         case PORT_B:
2846                 ddc_pin = GMBUS_PIN_2_BXT;
2847                 break;
2848         case PORT_C:
2849                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2850                 break;
2851         case PORT_D:
2852                 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2853                 break;
2854         case PORT_E:
2855                 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2856                 break;
2857         case PORT_F:
2858                 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2859                 break;
2860         default:
2861                 MISSING_CASE(port);
2862                 ddc_pin = GMBUS_PIN_2_BXT;
2863                 break;
2864         }
2865         return ddc_pin;
2866 }
2867
2868 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2869                               enum port port)
2870 {
2871         u8 ddc_pin;
2872
2873         switch (port) {
2874         case PORT_B:
2875                 ddc_pin = GMBUS_PIN_DPB;
2876                 break;
2877         case PORT_C:
2878                 ddc_pin = GMBUS_PIN_DPC;
2879                 break;
2880         case PORT_D:
2881                 ddc_pin = GMBUS_PIN_DPD;
2882                 break;
2883         default:
2884                 MISSING_CASE(port);
2885                 ddc_pin = GMBUS_PIN_DPB;
2886                 break;
2887         }
2888         return ddc_pin;
2889 }
2890
2891 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2892                              enum port port)
2893 {
2894         const struct ddi_vbt_port_info *info =
2895                 &dev_priv->vbt.ddi_port_info[port];
2896         u8 ddc_pin;
2897
2898         if (info->alternate_ddc_pin) {
2899                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2900                               info->alternate_ddc_pin, port_name(port));
2901                 return info->alternate_ddc_pin;
2902         }
2903
2904         if (HAS_PCH_ICP(dev_priv))
2905                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2906         else if (HAS_PCH_CNP(dev_priv))
2907                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2908         else if (IS_GEN9_LP(dev_priv))
2909                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2910         else if (IS_CHERRYVIEW(dev_priv))
2911                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2912         else
2913                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2914
2915         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2916                       ddc_pin, port_name(port));
2917
2918         return ddc_pin;
2919 }
2920
2921 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2922 {
2923         struct drm_i915_private *dev_priv =
2924                 to_i915(intel_dig_port->base.base.dev);
2925
2926         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2927                 intel_dig_port->write_infoframe = vlv_write_infoframe;
2928                 intel_dig_port->read_infoframe = vlv_read_infoframe;
2929                 intel_dig_port->set_infoframes = vlv_set_infoframes;
2930                 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
2931         } else if (IS_G4X(dev_priv)) {
2932                 intel_dig_port->write_infoframe = g4x_write_infoframe;
2933                 intel_dig_port->read_infoframe = g4x_read_infoframe;
2934                 intel_dig_port->set_infoframes = g4x_set_infoframes;
2935                 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
2936         } else if (HAS_DDI(dev_priv)) {
2937                 if (intel_dig_port->lspcon.active) {
2938                         intel_dig_port->write_infoframe = lspcon_write_infoframe;
2939                         intel_dig_port->read_infoframe = lspcon_read_infoframe;
2940                         intel_dig_port->set_infoframes = lspcon_set_infoframes;
2941                         intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2942                 } else {
2943                         intel_dig_port->write_infoframe = hsw_write_infoframe;
2944                         intel_dig_port->read_infoframe = hsw_read_infoframe;
2945                         intel_dig_port->set_infoframes = hsw_set_infoframes;
2946                         intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
2947                 }
2948         } else if (HAS_PCH_IBX(dev_priv)) {
2949                 intel_dig_port->write_infoframe = ibx_write_infoframe;
2950                 intel_dig_port->read_infoframe = ibx_read_infoframe;
2951                 intel_dig_port->set_infoframes = ibx_set_infoframes;
2952                 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
2953         } else {
2954                 intel_dig_port->write_infoframe = cpt_write_infoframe;
2955                 intel_dig_port->read_infoframe = cpt_read_infoframe;
2956                 intel_dig_port->set_infoframes = cpt_set_infoframes;
2957                 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
2958         }
2959 }
2960
2961 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2962                                struct intel_connector *intel_connector)
2963 {
2964         struct drm_connector *connector = &intel_connector->base;
2965         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2966         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2967         struct drm_device *dev = intel_encoder->base.dev;
2968         struct drm_i915_private *dev_priv = to_i915(dev);
2969         enum port port = intel_encoder->port;
2970
2971         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2972                       port_name(port));
2973
2974         if (WARN(intel_dig_port->max_lanes < 4,
2975                  "Not enough lanes (%d) for HDMI on port %c\n",
2976                  intel_dig_port->max_lanes, port_name(port)))
2977                 return;
2978
2979         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2980                            DRM_MODE_CONNECTOR_HDMIA);
2981         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2982
2983         connector->interlace_allowed = 1;
2984         connector->doublescan_allowed = 0;
2985         connector->stereo_allowed = 1;
2986
2987         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2988                 connector->ycbcr_420_allowed = true;
2989
2990         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2991
2992         if (WARN_ON(port == PORT_A))
2993                 return;
2994         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2995
2996         if (HAS_DDI(dev_priv))
2997                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2998         else
2999                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3000
3001         intel_hdmi_add_properties(intel_hdmi, connector);
3002
3003         intel_connector_attach_encoder(intel_connector, intel_encoder);
3004         intel_hdmi->attached_connector = intel_connector;
3005
3006         if (is_hdcp_supported(dev_priv, port)) {
3007                 int ret = intel_hdcp_init(intel_connector,
3008                                           &intel_hdmi_hdcp_shim);
3009                 if (ret)
3010                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
3011         }
3012
3013         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3014          * 0xd.  Failure to do so will result in spurious interrupts being
3015          * generated on the port when a cable is not attached.
3016          */
3017         if (IS_G45(dev_priv)) {
3018                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3019                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3020         }
3021
3022         intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
3023                                                          port_identifier(port));
3024         if (!intel_hdmi->cec_notifier)
3025                 DRM_DEBUG_KMS("CEC notifier get failed\n");
3026 }
3027
3028 void intel_hdmi_init(struct drm_i915_private *dev_priv,
3029                      i915_reg_t hdmi_reg, enum port port)
3030 {
3031         struct intel_digital_port *intel_dig_port;
3032         struct intel_encoder *intel_encoder;
3033         struct intel_connector *intel_connector;
3034
3035         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3036         if (!intel_dig_port)
3037                 return;
3038
3039         intel_connector = intel_connector_alloc();
3040         if (!intel_connector) {
3041                 kfree(intel_dig_port);
3042                 return;
3043         }
3044
3045         intel_encoder = &intel_dig_port->base;
3046
3047         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3048                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3049                          "HDMI %c", port_name(port));
3050
3051         intel_encoder->hotplug = intel_encoder_hotplug;
3052         intel_encoder->compute_config = intel_hdmi_compute_config;
3053         if (HAS_PCH_SPLIT(dev_priv)) {
3054                 intel_encoder->disable = pch_disable_hdmi;
3055                 intel_encoder->post_disable = pch_post_disable_hdmi;
3056         } else {
3057                 intel_encoder->disable = g4x_disable_hdmi;
3058         }
3059         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3060         intel_encoder->get_config = intel_hdmi_get_config;
3061         if (IS_CHERRYVIEW(dev_priv)) {
3062                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3063                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3064                 intel_encoder->enable = vlv_enable_hdmi;
3065                 intel_encoder->post_disable = chv_hdmi_post_disable;
3066                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3067         } else if (IS_VALLEYVIEW(dev_priv)) {
3068                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3069                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3070                 intel_encoder->enable = vlv_enable_hdmi;
3071                 intel_encoder->post_disable = vlv_hdmi_post_disable;
3072         } else {
3073                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3074                 if (HAS_PCH_CPT(dev_priv))
3075                         intel_encoder->enable = cpt_enable_hdmi;
3076                 else if (HAS_PCH_IBX(dev_priv))
3077                         intel_encoder->enable = ibx_enable_hdmi;
3078                 else
3079                         intel_encoder->enable = g4x_enable_hdmi;
3080         }
3081
3082         intel_encoder->type = INTEL_OUTPUT_HDMI;
3083         intel_encoder->power_domain = intel_port_to_power_domain(port);
3084         intel_encoder->port = port;
3085         if (IS_CHERRYVIEW(dev_priv)) {
3086                 if (port == PORT_D)
3087                         intel_encoder->crtc_mask = 1 << 2;
3088                 else
3089                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
3090         } else {
3091                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3092         }
3093         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3094         /*
3095          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3096          * to work on real hardware. And since g4x can send infoframes to
3097          * only one port anyway, nothing is lost by allowing it.
3098          */
3099         if (IS_G4X(dev_priv))
3100                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3101
3102         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
3103         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3104         intel_dig_port->max_lanes = 4;
3105
3106         intel_infoframe_init(intel_dig_port);
3107
3108         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3109         intel_hdmi_init_connector(intel_dig_port, intel_connector);
3110 }