07893ad2ad1f93c0c56e07a1bf69def94adfc349
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_hdmi.c
1 /*
2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2009 Intel Corporation
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *      Eric Anholt <eric@anholt.net>
26  *      Jesse Barnes <jesse.barnes@intel.com>
27  */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_hdcp.h>
37 #include <drm/drm_scdc_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
41 #include "i915_drv.h"
42
43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
44 {
45         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
46 }
47
48 static void
49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
50 {
51         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
52         struct drm_i915_private *dev_priv = to_i915(dev);
53         u32 enabled_bits;
54
55         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
56
57         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
58              "HDMI port enabled, expecting disabled\n");
59 }
60
61 static void
62 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
63                                      enum transcoder cpu_transcoder)
64 {
65         WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
66              TRANS_DDI_FUNC_ENABLE,
67              "HDMI transcoder function enabled, expecting disabled\n");
68 }
69
70 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
71 {
72         struct intel_digital_port *intel_dig_port =
73                 container_of(encoder, struct intel_digital_port, base.base);
74         return &intel_dig_port->hdmi;
75 }
76
77 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
78 {
79         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
80 }
81
82 static u32 g4x_infoframe_index(unsigned int type)
83 {
84         switch (type) {
85         case HDMI_PACKET_TYPE_GAMUT_METADATA:
86                 return VIDEO_DIP_SELECT_GAMUT;
87         case HDMI_INFOFRAME_TYPE_AVI:
88                 return VIDEO_DIP_SELECT_AVI;
89         case HDMI_INFOFRAME_TYPE_SPD:
90                 return VIDEO_DIP_SELECT_SPD;
91         case HDMI_INFOFRAME_TYPE_VENDOR:
92                 return VIDEO_DIP_SELECT_VENDOR;
93         default:
94                 MISSING_CASE(type);
95                 return 0;
96         }
97 }
98
99 static u32 g4x_infoframe_enable(unsigned int type)
100 {
101         switch (type) {
102         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
103                 return VIDEO_DIP_ENABLE_GCP;
104         case HDMI_PACKET_TYPE_GAMUT_METADATA:
105                 return VIDEO_DIP_ENABLE_GAMUT;
106         case DP_SDP_VSC:
107                 return 0;
108         case HDMI_INFOFRAME_TYPE_AVI:
109                 return VIDEO_DIP_ENABLE_AVI;
110         case HDMI_INFOFRAME_TYPE_SPD:
111                 return VIDEO_DIP_ENABLE_SPD;
112         case HDMI_INFOFRAME_TYPE_VENDOR:
113                 return VIDEO_DIP_ENABLE_VENDOR;
114         default:
115                 MISSING_CASE(type);
116                 return 0;
117         }
118 }
119
120 static u32 hsw_infoframe_enable(unsigned int type)
121 {
122         switch (type) {
123         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
124                 return VIDEO_DIP_ENABLE_GCP_HSW;
125         case HDMI_PACKET_TYPE_GAMUT_METADATA:
126                 return VIDEO_DIP_ENABLE_GMP_HSW;
127         case DP_SDP_VSC:
128                 return VIDEO_DIP_ENABLE_VSC_HSW;
129         case DP_SDP_PPS:
130                 return VDIP_ENABLE_PPS;
131         case HDMI_INFOFRAME_TYPE_AVI:
132                 return VIDEO_DIP_ENABLE_AVI_HSW;
133         case HDMI_INFOFRAME_TYPE_SPD:
134                 return VIDEO_DIP_ENABLE_SPD_HSW;
135         case HDMI_INFOFRAME_TYPE_VENDOR:
136                 return VIDEO_DIP_ENABLE_VS_HSW;
137         default:
138                 MISSING_CASE(type);
139                 return 0;
140         }
141 }
142
143 static i915_reg_t
144 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
145                  enum transcoder cpu_transcoder,
146                  unsigned int type,
147                  int i)
148 {
149         switch (type) {
150         case HDMI_PACKET_TYPE_GAMUT_METADATA:
151                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
152         case DP_SDP_VSC:
153                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
154         case DP_SDP_PPS:
155                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
156         case HDMI_INFOFRAME_TYPE_AVI:
157                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
158         case HDMI_INFOFRAME_TYPE_SPD:
159                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
160         case HDMI_INFOFRAME_TYPE_VENDOR:
161                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
162         default:
163                 MISSING_CASE(type);
164                 return INVALID_MMIO_REG;
165         }
166 }
167
168 static int hsw_dip_data_size(unsigned int type)
169 {
170         switch (type) {
171         case DP_SDP_VSC:
172                 return VIDEO_DIP_VSC_DATA_SIZE;
173         case DP_SDP_PPS:
174                 return VIDEO_DIP_PPS_DATA_SIZE;
175         default:
176                 return VIDEO_DIP_DATA_SIZE;
177         }
178 }
179
180 static void g4x_write_infoframe(struct intel_encoder *encoder,
181                                 const struct intel_crtc_state *crtc_state,
182                                 unsigned int type,
183                                 const void *frame, ssize_t len)
184 {
185         const u32 *data = frame;
186         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
187         u32 val = I915_READ(VIDEO_DIP_CTL);
188         int i;
189
190         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
191
192         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
193         val |= g4x_infoframe_index(type);
194
195         val &= ~g4x_infoframe_enable(type);
196
197         I915_WRITE(VIDEO_DIP_CTL, val);
198
199         mmiowb();
200         for (i = 0; i < len; i += 4) {
201                 I915_WRITE(VIDEO_DIP_DATA, *data);
202                 data++;
203         }
204         /* Write every possible data byte to force correct ECC calculation. */
205         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
206                 I915_WRITE(VIDEO_DIP_DATA, 0);
207         mmiowb();
208
209         val |= g4x_infoframe_enable(type);
210         val &= ~VIDEO_DIP_FREQ_MASK;
211         val |= VIDEO_DIP_FREQ_VSYNC;
212
213         I915_WRITE(VIDEO_DIP_CTL, val);
214         POSTING_READ(VIDEO_DIP_CTL);
215 }
216
217 static void g4x_read_infoframe(struct intel_encoder *encoder,
218                                const struct intel_crtc_state *crtc_state,
219                                unsigned int type,
220                                void *frame, ssize_t len)
221 {
222         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
223         u32 val, *data = frame;
224         int i;
225
226         val = I915_READ(VIDEO_DIP_CTL);
227
228         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
229         val |= g4x_infoframe_index(type);
230
231         I915_WRITE(VIDEO_DIP_CTL, val);
232
233         for (i = 0; i < len; i += 4)
234                 *data++ = I915_READ(VIDEO_DIP_DATA);
235 }
236
237 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
238                                   const struct intel_crtc_state *pipe_config)
239 {
240         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
241         u32 val = I915_READ(VIDEO_DIP_CTL);
242
243         if ((val & VIDEO_DIP_ENABLE) == 0)
244                 return 0;
245
246         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
247                 return 0;
248
249         return val & (VIDEO_DIP_ENABLE_AVI |
250                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
251 }
252
253 static void ibx_write_infoframe(struct intel_encoder *encoder,
254                                 const struct intel_crtc_state *crtc_state,
255                                 unsigned int type,
256                                 const void *frame, ssize_t len)
257 {
258         const u32 *data = frame;
259         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
261         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
262         u32 val = I915_READ(reg);
263         int i;
264
265         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
266
267         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
268         val |= g4x_infoframe_index(type);
269
270         val &= ~g4x_infoframe_enable(type);
271
272         I915_WRITE(reg, val);
273
274         mmiowb();
275         for (i = 0; i < len; i += 4) {
276                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
277                 data++;
278         }
279         /* Write every possible data byte to force correct ECC calculation. */
280         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
281                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
282         mmiowb();
283
284         val |= g4x_infoframe_enable(type);
285         val &= ~VIDEO_DIP_FREQ_MASK;
286         val |= VIDEO_DIP_FREQ_VSYNC;
287
288         I915_WRITE(reg, val);
289         POSTING_READ(reg);
290 }
291
292 static void ibx_read_infoframe(struct intel_encoder *encoder,
293                                const struct intel_crtc_state *crtc_state,
294                                unsigned int type,
295                                void *frame, ssize_t len)
296 {
297         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
298         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
299         u32 val, *data = frame;
300         int i;
301
302         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
303
304         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
305         val |= g4x_infoframe_index(type);
306
307         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
308
309         for (i = 0; i < len; i += 4)
310                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
311 }
312
313 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
314                                   const struct intel_crtc_state *pipe_config)
315 {
316         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
317         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
318         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
319         u32 val = I915_READ(reg);
320
321         if ((val & VIDEO_DIP_ENABLE) == 0)
322                 return 0;
323
324         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
325                 return 0;
326
327         return val & (VIDEO_DIP_ENABLE_AVI |
328                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
329                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
330 }
331
332 static void cpt_write_infoframe(struct intel_encoder *encoder,
333                                 const struct intel_crtc_state *crtc_state,
334                                 unsigned int type,
335                                 const void *frame, ssize_t len)
336 {
337         const u32 *data = frame;
338         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
340         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
341         u32 val = I915_READ(reg);
342         int i;
343
344         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
345
346         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
347         val |= g4x_infoframe_index(type);
348
349         /* The DIP control register spec says that we need to update the AVI
350          * infoframe without clearing its enable bit */
351         if (type != HDMI_INFOFRAME_TYPE_AVI)
352                 val &= ~g4x_infoframe_enable(type);
353
354         I915_WRITE(reg, val);
355
356         mmiowb();
357         for (i = 0; i < len; i += 4) {
358                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
359                 data++;
360         }
361         /* Write every possible data byte to force correct ECC calculation. */
362         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
363                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
364         mmiowb();
365
366         val |= g4x_infoframe_enable(type);
367         val &= ~VIDEO_DIP_FREQ_MASK;
368         val |= VIDEO_DIP_FREQ_VSYNC;
369
370         I915_WRITE(reg, val);
371         POSTING_READ(reg);
372 }
373
374 static void cpt_read_infoframe(struct intel_encoder *encoder,
375                                const struct intel_crtc_state *crtc_state,
376                                unsigned int type,
377                                void *frame, ssize_t len)
378 {
379         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
380         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
381         u32 val, *data = frame;
382         int i;
383
384         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
385
386         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
387         val |= g4x_infoframe_index(type);
388
389         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
390
391         for (i = 0; i < len; i += 4)
392                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
393 }
394
395 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
396                                   const struct intel_crtc_state *pipe_config)
397 {
398         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
399         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
400         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
401
402         if ((val & VIDEO_DIP_ENABLE) == 0)
403                 return 0;
404
405         return val & (VIDEO_DIP_ENABLE_AVI |
406                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
407                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
408 }
409
410 static void vlv_write_infoframe(struct intel_encoder *encoder,
411                                 const struct intel_crtc_state *crtc_state,
412                                 unsigned int type,
413                                 const void *frame, ssize_t len)
414 {
415         const u32 *data = frame;
416         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
418         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
419         u32 val = I915_READ(reg);
420         int i;
421
422         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
423
424         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
425         val |= g4x_infoframe_index(type);
426
427         val &= ~g4x_infoframe_enable(type);
428
429         I915_WRITE(reg, val);
430
431         mmiowb();
432         for (i = 0; i < len; i += 4) {
433                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
434                 data++;
435         }
436         /* Write every possible data byte to force correct ECC calculation. */
437         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
438                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
439         mmiowb();
440
441         val |= g4x_infoframe_enable(type);
442         val &= ~VIDEO_DIP_FREQ_MASK;
443         val |= VIDEO_DIP_FREQ_VSYNC;
444
445         I915_WRITE(reg, val);
446         POSTING_READ(reg);
447 }
448
449 static void vlv_read_infoframe(struct intel_encoder *encoder,
450                                const struct intel_crtc_state *crtc_state,
451                                unsigned int type,
452                                void *frame, ssize_t len)
453 {
454         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
455         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
456         u32 val, *data = frame;
457         int i;
458
459         val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe));
460
461         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
462         val |= g4x_infoframe_index(type);
463
464         I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
465
466         for (i = 0; i < len; i += 4)
467                 *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe));
468 }
469
470 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
471                                   const struct intel_crtc_state *pipe_config)
472 {
473         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
474         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
475         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
476
477         if ((val & VIDEO_DIP_ENABLE) == 0)
478                 return 0;
479
480         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
481                 return 0;
482
483         return val & (VIDEO_DIP_ENABLE_AVI |
484                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
485                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
486 }
487
488 static void hsw_write_infoframe(struct intel_encoder *encoder,
489                                 const struct intel_crtc_state *crtc_state,
490                                 unsigned int type,
491                                 const void *frame, ssize_t len)
492 {
493         const u32 *data = frame;
494         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
495         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
496         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
497         int data_size;
498         int i;
499         u32 val = I915_READ(ctl_reg);
500
501         data_size = hsw_dip_data_size(type);
502
503         val &= ~hsw_infoframe_enable(type);
504         I915_WRITE(ctl_reg, val);
505
506         mmiowb();
507         for (i = 0; i < len; i += 4) {
508                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
509                                             type, i >> 2), *data);
510                 data++;
511         }
512         /* Write every possible data byte to force correct ECC calculation. */
513         for (; i < data_size; i += 4)
514                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
515                                             type, i >> 2), 0);
516         mmiowb();
517
518         val |= hsw_infoframe_enable(type);
519         I915_WRITE(ctl_reg, val);
520         POSTING_READ(ctl_reg);
521 }
522
523 static void hsw_read_infoframe(struct intel_encoder *encoder,
524                                const struct intel_crtc_state *crtc_state,
525                                unsigned int type,
526                                void *frame, ssize_t len)
527 {
528         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
529         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
530         u32 val, *data = frame;
531         int i;
532
533         val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));
534
535         for (i = 0; i < len; i += 4)
536                 *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,
537                                                      type, i >> 2));
538 }
539
540 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
541                                   const struct intel_crtc_state *pipe_config)
542 {
543         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
544         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
545
546         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
547                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
548                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
549 }
550
551 static const u8 infoframe_type_to_idx[] = {
552         HDMI_PACKET_TYPE_GENERAL_CONTROL,
553         HDMI_PACKET_TYPE_GAMUT_METADATA,
554         DP_SDP_VSC,
555         HDMI_INFOFRAME_TYPE_AVI,
556         HDMI_INFOFRAME_TYPE_SPD,
557         HDMI_INFOFRAME_TYPE_VENDOR,
558 };
559
560 u32 intel_hdmi_infoframe_enable(unsigned int type)
561 {
562         int i;
563
564         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
565                 if (infoframe_type_to_idx[i] == type)
566                         return BIT(i);
567         }
568
569         return 0;
570 }
571
572 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
573                                   const struct intel_crtc_state *crtc_state)
574 {
575         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
576         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
577         u32 val, ret = 0;
578         int i;
579
580         val = dig_port->infoframes_enabled(encoder, crtc_state);
581
582         /* map from hardware bits to dip idx */
583         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
584                 unsigned int type = infoframe_type_to_idx[i];
585
586                 if (HAS_DDI(dev_priv)) {
587                         if (val & hsw_infoframe_enable(type))
588                                 ret |= BIT(i);
589                 } else {
590                         if (val & g4x_infoframe_enable(type))
591                                 ret |= BIT(i);
592                 }
593         }
594
595         return ret;
596 }
597
598 /*
599  * The data we write to the DIP data buffer registers is 1 byte bigger than the
600  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
601  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
602  * used for both technologies.
603  *
604  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
605  * DW1:       DB3       | DB2 | DB1 | DB0
606  * DW2:       DB7       | DB6 | DB5 | DB4
607  * DW3: ...
608  *
609  * (HB is Header Byte, DB is Data Byte)
610  *
611  * The hdmi pack() functions don't know about that hardware specific hole so we
612  * trick them by giving an offset into the buffer and moving back the header
613  * bytes by one.
614  */
615 static void intel_write_infoframe(struct intel_encoder *encoder,
616                                   const struct intel_crtc_state *crtc_state,
617                                   enum hdmi_infoframe_type type,
618                                   const union hdmi_infoframe *frame)
619 {
620         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
621         u8 buffer[VIDEO_DIP_DATA_SIZE];
622         ssize_t len;
623
624         if ((crtc_state->infoframes.enable &
625              intel_hdmi_infoframe_enable(type)) == 0)
626                 return;
627
628         if (WARN_ON(frame->any.type != type))
629                 return;
630
631         /* see comment above for the reason for this offset */
632         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
633         if (WARN_ON(len < 0))
634                 return;
635
636         /* Insert the 'hole' (see big comment above) at position 3 */
637         memmove(&buffer[0], &buffer[1], 3);
638         buffer[3] = 0;
639         len++;
640
641         intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
642 }
643
644 void intel_read_infoframe(struct intel_encoder *encoder,
645                           const struct intel_crtc_state *crtc_state,
646                           enum hdmi_infoframe_type type,
647                           union hdmi_infoframe *frame)
648 {
649         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
650         u8 buffer[VIDEO_DIP_DATA_SIZE];
651         int ret;
652
653         if ((crtc_state->infoframes.enable &
654              intel_hdmi_infoframe_enable(type)) == 0)
655                 return;
656
657         intel_dig_port->read_infoframe(encoder, crtc_state,
658                                        type, buffer, sizeof(buffer));
659
660         /* Fill the 'hole' (see big comment above) at position 3 */
661         memmove(&buffer[1], &buffer[0], 3);
662
663         /* see comment above for the reason for this offset */
664         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
665         if (ret) {
666                 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type);
667                 return;
668         }
669
670         if (frame->any.type != type)
671                 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
672                               frame->any.type, type);
673 }
674
675 static bool
676 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
677                                  struct intel_crtc_state *crtc_state,
678                                  struct drm_connector_state *conn_state)
679 {
680         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
681         const struct drm_display_mode *adjusted_mode =
682                 &crtc_state->base.adjusted_mode;
683         struct drm_connector *connector = conn_state->connector;
684         int ret;
685
686         if (!crtc_state->has_infoframe)
687                 return true;
688
689         crtc_state->infoframes.enable |=
690                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
691
692         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
693                                                        adjusted_mode);
694         if (ret)
695                 return false;
696
697         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
698                 frame->colorspace = HDMI_COLORSPACE_YUV420;
699         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
700                 frame->colorspace = HDMI_COLORSPACE_YUV444;
701         else
702                 frame->colorspace = HDMI_COLORSPACE_RGB;
703
704         drm_hdmi_avi_infoframe_quant_range(frame, connector,
705                                            adjusted_mode,
706                                            crtc_state->limited_color_range ?
707                                            HDMI_QUANTIZATION_RANGE_LIMITED :
708                                            HDMI_QUANTIZATION_RANGE_FULL);
709
710         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
711
712         /* TODO: handle pixel repetition for YCBCR420 outputs */
713
714         ret = hdmi_avi_infoframe_check(frame);
715         if (WARN_ON(ret))
716                 return false;
717
718         return true;
719 }
720
721 static bool
722 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
723                                  struct intel_crtc_state *crtc_state,
724                                  struct drm_connector_state *conn_state)
725 {
726         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
727         int ret;
728
729         if (!crtc_state->has_infoframe)
730                 return true;
731
732         crtc_state->infoframes.enable |=
733                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
734
735         ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
736         if (WARN_ON(ret))
737                 return false;
738
739         frame->sdi = HDMI_SPD_SDI_PC;
740
741         ret = hdmi_spd_infoframe_check(frame);
742         if (WARN_ON(ret))
743                 return false;
744
745         return true;
746 }
747
748 static bool
749 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
750                                   struct intel_crtc_state *crtc_state,
751                                   struct drm_connector_state *conn_state)
752 {
753         struct hdmi_vendor_infoframe *frame =
754                 &crtc_state->infoframes.hdmi.vendor.hdmi;
755         const struct drm_display_info *info =
756                 &conn_state->connector->display_info;
757         int ret;
758
759         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
760                 return true;
761
762         crtc_state->infoframes.enable |=
763                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
764
765         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
766                                                           conn_state->connector,
767                                                           &crtc_state->base.adjusted_mode);
768         if (WARN_ON(ret))
769                 return false;
770
771         ret = hdmi_vendor_infoframe_check(frame);
772         if (WARN_ON(ret))
773                 return false;
774
775         return true;
776 }
777
778 static void g4x_set_infoframes(struct intel_encoder *encoder,
779                                bool enable,
780                                const struct intel_crtc_state *crtc_state,
781                                const struct drm_connector_state *conn_state)
782 {
783         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
784         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
785         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
786         i915_reg_t reg = VIDEO_DIP_CTL;
787         u32 val = I915_READ(reg);
788         u32 port = VIDEO_DIP_PORT(encoder->port);
789
790         assert_hdmi_port_disabled(intel_hdmi);
791
792         /* If the registers were not initialized yet, they might be zeroes,
793          * which means we're selecting the AVI DIP and we're setting its
794          * frequency to once. This seems to really confuse the HW and make
795          * things stop working (the register spec says the AVI always needs to
796          * be sent every VSync). So here we avoid writing to the register more
797          * than we need and also explicitly select the AVI DIP and explicitly
798          * set its frequency to every VSync. Avoiding to write it twice seems to
799          * be enough to solve the problem, but being defensive shouldn't hurt us
800          * either. */
801         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
802
803         if (!enable) {
804                 if (!(val & VIDEO_DIP_ENABLE))
805                         return;
806                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
807                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
808                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
809                         return;
810                 }
811                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
812                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
813                 I915_WRITE(reg, val);
814                 POSTING_READ(reg);
815                 return;
816         }
817
818         if (port != (val & VIDEO_DIP_PORT_MASK)) {
819                 if (val & VIDEO_DIP_ENABLE) {
820                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
821                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
822                         return;
823                 }
824                 val &= ~VIDEO_DIP_PORT_MASK;
825                 val |= port;
826         }
827
828         val |= VIDEO_DIP_ENABLE;
829         val &= ~(VIDEO_DIP_ENABLE_AVI |
830                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
831
832         I915_WRITE(reg, val);
833         POSTING_READ(reg);
834
835         intel_write_infoframe(encoder, crtc_state,
836                               HDMI_INFOFRAME_TYPE_AVI,
837                               &crtc_state->infoframes.avi);
838         intel_write_infoframe(encoder, crtc_state,
839                               HDMI_INFOFRAME_TYPE_SPD,
840                               &crtc_state->infoframes.spd);
841         intel_write_infoframe(encoder, crtc_state,
842                               HDMI_INFOFRAME_TYPE_VENDOR,
843                               &crtc_state->infoframes.hdmi);
844 }
845
846 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
847 {
848         struct drm_connector *connector = conn_state->connector;
849
850         /*
851          * HDMI cloning is only supported on g4x which doesn't
852          * support deep color or GCP infoframes anyway so no
853          * need to worry about multiple HDMI sinks here.
854          */
855
856         return connector->display_info.bpc > 8;
857 }
858
859 /*
860  * Determine if default_phase=1 can be indicated in the GCP infoframe.
861  *
862  * From HDMI specification 1.4a:
863  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
864  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
865  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
866  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
867  *   phase of 0
868  */
869 static bool gcp_default_phase_possible(int pipe_bpp,
870                                        const struct drm_display_mode *mode)
871 {
872         unsigned int pixels_per_group;
873
874         switch (pipe_bpp) {
875         case 30:
876                 /* 4 pixels in 5 clocks */
877                 pixels_per_group = 4;
878                 break;
879         case 36:
880                 /* 2 pixels in 3 clocks */
881                 pixels_per_group = 2;
882                 break;
883         case 48:
884                 /* 1 pixel in 2 clocks */
885                 pixels_per_group = 1;
886                 break;
887         default:
888                 /* phase information not relevant for 8bpc */
889                 return false;
890         }
891
892         return mode->crtc_hdisplay % pixels_per_group == 0 &&
893                 mode->crtc_htotal % pixels_per_group == 0 &&
894                 mode->crtc_hblank_start % pixels_per_group == 0 &&
895                 mode->crtc_hblank_end % pixels_per_group == 0 &&
896                 mode->crtc_hsync_start % pixels_per_group == 0 &&
897                 mode->crtc_hsync_end % pixels_per_group == 0 &&
898                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
899                  mode->crtc_htotal/2 % pixels_per_group == 0);
900 }
901
902 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
903                                          const struct intel_crtc_state *crtc_state,
904                                          const struct drm_connector_state *conn_state)
905 {
906         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
907         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
908         i915_reg_t reg;
909
910         if ((crtc_state->infoframes.enable &
911              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
912                 return false;
913
914         if (HAS_DDI(dev_priv))
915                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
916         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
917                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
918         else if (HAS_PCH_SPLIT(dev_priv))
919                 reg = TVIDEO_DIP_GCP(crtc->pipe);
920         else
921                 return false;
922
923         I915_WRITE(reg, crtc_state->infoframes.gcp);
924
925         return true;
926 }
927
928 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
929                                    struct intel_crtc_state *crtc_state)
930 {
931         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
932         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
933         i915_reg_t reg;
934
935         if ((crtc_state->infoframes.enable &
936              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
937                 return;
938
939         if (HAS_DDI(dev_priv))
940                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
941         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
942                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
943         else if (HAS_PCH_SPLIT(dev_priv))
944                 reg = TVIDEO_DIP_GCP(crtc->pipe);
945         else
946                 return;
947
948         crtc_state->infoframes.gcp = I915_READ(reg);
949 }
950
951 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
952                                              struct intel_crtc_state *crtc_state,
953                                              struct drm_connector_state *conn_state)
954 {
955         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
956
957         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
958                 return;
959
960         crtc_state->infoframes.enable |=
961                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
962
963         /* Indicate color depth whenever the sink supports deep color */
964         if (hdmi_sink_is_deep_color(conn_state))
965                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
966
967         /* Enable default_phase whenever the display mode is suitably aligned */
968         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
969                                        &crtc_state->base.adjusted_mode))
970                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
971 }
972
973 static void ibx_set_infoframes(struct intel_encoder *encoder,
974                                bool enable,
975                                const struct intel_crtc_state *crtc_state,
976                                const struct drm_connector_state *conn_state)
977 {
978         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
980         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
981         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
982         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
983         u32 val = I915_READ(reg);
984         u32 port = VIDEO_DIP_PORT(encoder->port);
985
986         assert_hdmi_port_disabled(intel_hdmi);
987
988         /* See the big comment in g4x_set_infoframes() */
989         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
990
991         if (!enable) {
992                 if (!(val & VIDEO_DIP_ENABLE))
993                         return;
994                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
995                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
996                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
997                 I915_WRITE(reg, val);
998                 POSTING_READ(reg);
999                 return;
1000         }
1001
1002         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1003                 WARN(val & VIDEO_DIP_ENABLE,
1004                      "DIP already enabled on port %c\n",
1005                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1006                 val &= ~VIDEO_DIP_PORT_MASK;
1007                 val |= port;
1008         }
1009
1010         val |= VIDEO_DIP_ENABLE;
1011         val &= ~(VIDEO_DIP_ENABLE_AVI |
1012                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1013                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1014
1015         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1016                 val |= VIDEO_DIP_ENABLE_GCP;
1017
1018         I915_WRITE(reg, val);
1019         POSTING_READ(reg);
1020
1021         intel_write_infoframe(encoder, crtc_state,
1022                               HDMI_INFOFRAME_TYPE_AVI,
1023                               &crtc_state->infoframes.avi);
1024         intel_write_infoframe(encoder, crtc_state,
1025                               HDMI_INFOFRAME_TYPE_SPD,
1026                               &crtc_state->infoframes.spd);
1027         intel_write_infoframe(encoder, crtc_state,
1028                               HDMI_INFOFRAME_TYPE_VENDOR,
1029                               &crtc_state->infoframes.hdmi);
1030 }
1031
1032 static void cpt_set_infoframes(struct intel_encoder *encoder,
1033                                bool enable,
1034                                const struct intel_crtc_state *crtc_state,
1035                                const struct drm_connector_state *conn_state)
1036 {
1037         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1039         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1040         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1041         u32 val = I915_READ(reg);
1042
1043         assert_hdmi_port_disabled(intel_hdmi);
1044
1045         /* See the big comment in g4x_set_infoframes() */
1046         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1047
1048         if (!enable) {
1049                 if (!(val & VIDEO_DIP_ENABLE))
1050                         return;
1051                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1052                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1053                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1054                 I915_WRITE(reg, val);
1055                 POSTING_READ(reg);
1056                 return;
1057         }
1058
1059         /* Set both together, unset both together: see the spec. */
1060         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1061         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1062                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1063
1064         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1065                 val |= VIDEO_DIP_ENABLE_GCP;
1066
1067         I915_WRITE(reg, val);
1068         POSTING_READ(reg);
1069
1070         intel_write_infoframe(encoder, crtc_state,
1071                               HDMI_INFOFRAME_TYPE_AVI,
1072                               &crtc_state->infoframes.avi);
1073         intel_write_infoframe(encoder, crtc_state,
1074                               HDMI_INFOFRAME_TYPE_SPD,
1075                               &crtc_state->infoframes.spd);
1076         intel_write_infoframe(encoder, crtc_state,
1077                               HDMI_INFOFRAME_TYPE_VENDOR,
1078                               &crtc_state->infoframes.hdmi);
1079 }
1080
1081 static void vlv_set_infoframes(struct intel_encoder *encoder,
1082                                bool enable,
1083                                const struct intel_crtc_state *crtc_state,
1084                                const struct drm_connector_state *conn_state)
1085 {
1086         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1088         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1089         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1090         u32 val = I915_READ(reg);
1091         u32 port = VIDEO_DIP_PORT(encoder->port);
1092
1093         assert_hdmi_port_disabled(intel_hdmi);
1094
1095         /* See the big comment in g4x_set_infoframes() */
1096         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1097
1098         if (!enable) {
1099                 if (!(val & VIDEO_DIP_ENABLE))
1100                         return;
1101                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1102                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1103                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1104                 I915_WRITE(reg, val);
1105                 POSTING_READ(reg);
1106                 return;
1107         }
1108
1109         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1110                 WARN(val & VIDEO_DIP_ENABLE,
1111                      "DIP already enabled on port %c\n",
1112                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1113                 val &= ~VIDEO_DIP_PORT_MASK;
1114                 val |= port;
1115         }
1116
1117         val |= VIDEO_DIP_ENABLE;
1118         val &= ~(VIDEO_DIP_ENABLE_AVI |
1119                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1120                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1121
1122         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1123                 val |= VIDEO_DIP_ENABLE_GCP;
1124
1125         I915_WRITE(reg, val);
1126         POSTING_READ(reg);
1127
1128         intel_write_infoframe(encoder, crtc_state,
1129                               HDMI_INFOFRAME_TYPE_AVI,
1130                               &crtc_state->infoframes.avi);
1131         intel_write_infoframe(encoder, crtc_state,
1132                               HDMI_INFOFRAME_TYPE_SPD,
1133                               &crtc_state->infoframes.spd);
1134         intel_write_infoframe(encoder, crtc_state,
1135                               HDMI_INFOFRAME_TYPE_VENDOR,
1136                               &crtc_state->infoframes.hdmi);
1137 }
1138
1139 static void hsw_set_infoframes(struct intel_encoder *encoder,
1140                                bool enable,
1141                                const struct intel_crtc_state *crtc_state,
1142                                const struct drm_connector_state *conn_state)
1143 {
1144         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1145         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1146         u32 val = I915_READ(reg);
1147
1148         assert_hdmi_transcoder_func_disabled(dev_priv,
1149                                              crtc_state->cpu_transcoder);
1150
1151         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1152                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1153                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
1154
1155         if (!enable) {
1156                 I915_WRITE(reg, val);
1157                 POSTING_READ(reg);
1158                 return;
1159         }
1160
1161         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1162                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1163
1164         I915_WRITE(reg, val);
1165         POSTING_READ(reg);
1166
1167         intel_write_infoframe(encoder, crtc_state,
1168                               HDMI_INFOFRAME_TYPE_AVI,
1169                               &crtc_state->infoframes.avi);
1170         intel_write_infoframe(encoder, crtc_state,
1171                               HDMI_INFOFRAME_TYPE_SPD,
1172                               &crtc_state->infoframes.spd);
1173         intel_write_infoframe(encoder, crtc_state,
1174                               HDMI_INFOFRAME_TYPE_VENDOR,
1175                               &crtc_state->infoframes.hdmi);
1176 }
1177
1178 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1179 {
1180         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1181         struct i2c_adapter *adapter =
1182                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1183
1184         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1185                 return;
1186
1187         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1188                       enable ? "Enabling" : "Disabling");
1189
1190         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1191                                          adapter, enable);
1192 }
1193
1194 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
1195                                 unsigned int offset, void *buffer, size_t size)
1196 {
1197         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1198         struct drm_i915_private *dev_priv =
1199                 intel_dig_port->base.base.dev->dev_private;
1200         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1201                                                               hdmi->ddc_bus);
1202         int ret;
1203         u8 start = offset & 0xff;
1204         struct i2c_msg msgs[] = {
1205                 {
1206                         .addr = DRM_HDCP_DDC_ADDR,
1207                         .flags = 0,
1208                         .len = 1,
1209                         .buf = &start,
1210                 },
1211                 {
1212                         .addr = DRM_HDCP_DDC_ADDR,
1213                         .flags = I2C_M_RD,
1214                         .len = size,
1215                         .buf = buffer
1216                 }
1217         };
1218         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1219         if (ret == ARRAY_SIZE(msgs))
1220                 return 0;
1221         return ret >= 0 ? -EIO : ret;
1222 }
1223
1224 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
1225                                  unsigned int offset, void *buffer, size_t size)
1226 {
1227         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1228         struct drm_i915_private *dev_priv =
1229                 intel_dig_port->base.base.dev->dev_private;
1230         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1231                                                               hdmi->ddc_bus);
1232         int ret;
1233         u8 *write_buf;
1234         struct i2c_msg msg;
1235
1236         write_buf = kzalloc(size + 1, GFP_KERNEL);
1237         if (!write_buf)
1238                 return -ENOMEM;
1239
1240         write_buf[0] = offset & 0xff;
1241         memcpy(&write_buf[1], buffer, size);
1242
1243         msg.addr = DRM_HDCP_DDC_ADDR;
1244         msg.flags = 0,
1245         msg.len = size + 1,
1246         msg.buf = write_buf;
1247
1248         ret = i2c_transfer(adapter, &msg, 1);
1249         if (ret == 1)
1250                 ret = 0;
1251         else if (ret >= 0)
1252                 ret = -EIO;
1253
1254         kfree(write_buf);
1255         return ret;
1256 }
1257
1258 static
1259 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
1260                                   u8 *an)
1261 {
1262         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1263         struct drm_i915_private *dev_priv =
1264                 intel_dig_port->base.base.dev->dev_private;
1265         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1266                                                               hdmi->ddc_bus);
1267         int ret;
1268
1269         ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
1270                                     DRM_HDCP_AN_LEN);
1271         if (ret) {
1272                 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
1273                 return ret;
1274         }
1275
1276         ret = intel_gmbus_output_aksv(adapter);
1277         if (ret < 0) {
1278                 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
1279                 return ret;
1280         }
1281         return 0;
1282 }
1283
1284 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
1285                                      u8 *bksv)
1286 {
1287         int ret;
1288         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1289                                    DRM_HDCP_KSV_LEN);
1290         if (ret)
1291                 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1292         return ret;
1293 }
1294
1295 static
1296 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1297                                  u8 *bstatus)
1298 {
1299         int ret;
1300         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1301                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1302         if (ret)
1303                 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1304         return ret;
1305 }
1306
1307 static
1308 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1309                                      bool *repeater_present)
1310 {
1311         int ret;
1312         u8 val;
1313
1314         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1315         if (ret) {
1316                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1317                 return ret;
1318         }
1319         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1320         return 0;
1321 }
1322
1323 static
1324 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1325                                   u8 *ri_prime)
1326 {
1327         int ret;
1328         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1329                                    ri_prime, DRM_HDCP_RI_LEN);
1330         if (ret)
1331                 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1332         return ret;
1333 }
1334
1335 static
1336 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1337                                    bool *ksv_ready)
1338 {
1339         int ret;
1340         u8 val;
1341
1342         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1343         if (ret) {
1344                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1345                 return ret;
1346         }
1347         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1348         return 0;
1349 }
1350
1351 static
1352 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1353                                   int num_downstream, u8 *ksv_fifo)
1354 {
1355         int ret;
1356         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1357                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1358         if (ret) {
1359                 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1360                 return ret;
1361         }
1362         return 0;
1363 }
1364
1365 static
1366 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1367                                       int i, u32 *part)
1368 {
1369         int ret;
1370
1371         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1372                 return -EINVAL;
1373
1374         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1375                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1376         if (ret)
1377                 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1378         return ret;
1379 }
1380
1381 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1382 {
1383         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1384         struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
1385         struct drm_crtc *crtc = connector->base.state->crtc;
1386         struct intel_crtc *intel_crtc = container_of(crtc,
1387                                                      struct intel_crtc, base);
1388         u32 scanline;
1389         int ret;
1390
1391         for (;;) {
1392                 scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
1393                 if (scanline > 100 && scanline < 200)
1394                         break;
1395                 usleep_range(25, 50);
1396         }
1397
1398         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
1399         if (ret) {
1400                 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
1401                 return ret;
1402         }
1403         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
1404         if (ret) {
1405                 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
1406                 return ret;
1407         }
1408
1409         return 0;
1410 }
1411
1412 static
1413 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1414                                       bool enable)
1415 {
1416         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1417         struct intel_connector *connector = hdmi->attached_connector;
1418         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1419         int ret;
1420
1421         if (!enable)
1422                 usleep_range(6, 60); /* Bspec says >= 6us */
1423
1424         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1425         if (ret) {
1426                 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1427                           enable ? "Enable" : "Disable", ret);
1428                 return ret;
1429         }
1430
1431         /*
1432          * WA: To fix incorrect positioning of the window of
1433          * opportunity and enc_en signalling in KABYLAKE.
1434          */
1435         if (IS_KABYLAKE(dev_priv) && enable)
1436                 return kbl_repositioning_enc_en_signal(connector);
1437
1438         return 0;
1439 }
1440
1441 static
1442 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1443 {
1444         struct drm_i915_private *dev_priv =
1445                 intel_dig_port->base.base.dev->dev_private;
1446         enum port port = intel_dig_port->base.port;
1447         int ret;
1448         union {
1449                 u32 reg;
1450                 u8 shim[DRM_HDCP_RI_LEN];
1451         } ri;
1452
1453         ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1454         if (ret)
1455                 return false;
1456
1457         I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1458
1459         /* Wait for Ri prime match */
1460         if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1461                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1462                 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1463                           I915_READ(PORT_HDCP_STATUS(port)));
1464                 return false;
1465         }
1466         return true;
1467 }
1468
1469 static struct hdcp2_hdmi_msg_data {
1470         u8 msg_id;
1471         u32 timeout;
1472         u32 timeout2;
1473         } hdcp2_msg_data[] = {
1474                 {HDCP_2_2_AKE_INIT, 0, 0},
1475                 {HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0},
1476                 {HDCP_2_2_AKE_NO_STORED_KM, 0, 0},
1477                 {HDCP_2_2_AKE_STORED_KM, 0, 0},
1478                 {HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
1479                                 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS},
1480                 {HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS,
1481                                 0},
1482                 {HDCP_2_2_LC_INIT, 0, 0},
1483                 {HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0},
1484                 {HDCP_2_2_SKE_SEND_EKS, 0, 0},
1485                 {HDCP_2_2_REP_SEND_RECVID_LIST,
1486                                 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0},
1487                 {HDCP_2_2_REP_SEND_ACK, 0, 0},
1488                 {HDCP_2_2_REP_STREAM_MANAGE, 0, 0},
1489                 {HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS,
1490                                 0},
1491         };
1492
1493 static
1494 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
1495                                     u8 *rx_status)
1496 {
1497         return intel_hdmi_hdcp_read(intel_dig_port,
1498                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1499                                     rx_status,
1500                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1501 }
1502
1503 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1504 {
1505         int i;
1506
1507         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
1508                 if (hdcp2_msg_data[i].msg_id == msg_id &&
1509                     (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
1510                         return hdcp2_msg_data[i].timeout;
1511                 else if (hdcp2_msg_data[i].msg_id == msg_id)
1512                         return hdcp2_msg_data[i].timeout2;
1513
1514         return -EINVAL;
1515 }
1516
1517 static inline
1518 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
1519                                   u8 msg_id, bool *msg_ready,
1520                                   ssize_t *msg_sz)
1521 {
1522         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1523         int ret;
1524
1525         ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
1526         if (ret < 0) {
1527                 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
1528                 return ret;
1529         }
1530
1531         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1532                   rx_status[0]);
1533
1534         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1535                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1536                              *msg_sz);
1537         else
1538                 *msg_ready = *msg_sz;
1539
1540         return 0;
1541 }
1542
1543 static ssize_t
1544 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
1545                               u8 msg_id, bool paired)
1546 {
1547         bool msg_ready = false;
1548         int timeout, ret;
1549         ssize_t msg_sz = 0;
1550
1551         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1552         if (timeout < 0)
1553                 return timeout;
1554
1555         ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
1556                                                              msg_id, &msg_ready,
1557                                                              &msg_sz),
1558                          !ret && msg_ready && msg_sz, timeout * 1000,
1559                          1000, 5 * 1000);
1560         if (ret)
1561                 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1562                               msg_id, ret, timeout);
1563
1564         return ret ? ret : msg_sz;
1565 }
1566
1567 static
1568 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
1569                                void *buf, size_t size)
1570 {
1571         unsigned int offset;
1572
1573         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1574         return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
1575 }
1576
1577 static
1578 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
1579                               u8 msg_id, void *buf, size_t size)
1580 {
1581         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1582         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1583         unsigned int offset;
1584         ssize_t ret;
1585
1586         ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
1587                                             hdcp->is_paired);
1588         if (ret < 0)
1589                 return ret;
1590
1591         /*
1592          * Available msg size should be equal to or lesser than the
1593          * available buffer.
1594          */
1595         if (ret > size) {
1596                 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1597                               ret, size);
1598                 return -1;
1599         }
1600
1601         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1602         ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
1603         if (ret)
1604                 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
1605
1606         return ret;
1607 }
1608
1609 static
1610 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
1611 {
1612         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1613         int ret;
1614
1615         ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
1616         if (ret)
1617                 return ret;
1618
1619         /*
1620          * Re-auth request and Link Integrity Failures are represented by
1621          * same bit. i.e reauth_req.
1622          */
1623         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1624                 ret = HDCP_REAUTH_REQUEST;
1625         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1626                 ret = HDCP_TOPOLOGY_CHANGE;
1627
1628         return ret;
1629 }
1630
1631 static
1632 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
1633                              bool *capable)
1634 {
1635         u8 hdcp2_version;
1636         int ret;
1637
1638         *capable = false;
1639         ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1640                                    &hdcp2_version, sizeof(hdcp2_version));
1641         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1642                 *capable = true;
1643
1644         return ret;
1645 }
1646
1647 static inline
1648 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
1649 {
1650         return HDCP_PROTOCOL_HDMI;
1651 }
1652
1653 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1654         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1655         .read_bksv = intel_hdmi_hdcp_read_bksv,
1656         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1657         .repeater_present = intel_hdmi_hdcp_repeater_present,
1658         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1659         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1660         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1661         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1662         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1663         .check_link = intel_hdmi_hdcp_check_link,
1664         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1665         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1666         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1667         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1668         .protocol = HDCP_PROTOCOL_HDMI,
1669 };
1670
1671 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1672                                const struct intel_crtc_state *crtc_state)
1673 {
1674         struct drm_device *dev = encoder->base.dev;
1675         struct drm_i915_private *dev_priv = to_i915(dev);
1676         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1677         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1678         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1679         u32 hdmi_val;
1680
1681         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1682
1683         hdmi_val = SDVO_ENCODING_HDMI;
1684         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1685                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1686         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1687                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1688         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1689                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1690
1691         if (crtc_state->pipe_bpp > 24)
1692                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1693         else
1694                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1695
1696         if (crtc_state->has_hdmi_sink)
1697                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1698
1699         if (HAS_PCH_CPT(dev_priv))
1700                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1701         else if (IS_CHERRYVIEW(dev_priv))
1702                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1703         else
1704                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1705
1706         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1707         POSTING_READ(intel_hdmi->hdmi_reg);
1708 }
1709
1710 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1711                                     enum pipe *pipe)
1712 {
1713         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1714         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1715         intel_wakeref_t wakeref;
1716         bool ret;
1717
1718         wakeref = intel_display_power_get_if_enabled(dev_priv,
1719                                                      encoder->power_domain);
1720         if (!wakeref)
1721                 return false;
1722
1723         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1724
1725         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1726
1727         return ret;
1728 }
1729
1730 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1731                                   struct intel_crtc_state *pipe_config)
1732 {
1733         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1734         struct drm_device *dev = encoder->base.dev;
1735         struct drm_i915_private *dev_priv = to_i915(dev);
1736         u32 tmp, flags = 0;
1737         int dotclock;
1738
1739         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1740
1741         tmp = I915_READ(intel_hdmi->hdmi_reg);
1742
1743         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1744                 flags |= DRM_MODE_FLAG_PHSYNC;
1745         else
1746                 flags |= DRM_MODE_FLAG_NHSYNC;
1747
1748         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1749                 flags |= DRM_MODE_FLAG_PVSYNC;
1750         else
1751                 flags |= DRM_MODE_FLAG_NVSYNC;
1752
1753         if (tmp & HDMI_MODE_SELECT_HDMI)
1754                 pipe_config->has_hdmi_sink = true;
1755
1756         pipe_config->infoframes.enable |=
1757                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1758
1759         if (pipe_config->infoframes.enable)
1760                 pipe_config->has_infoframe = true;
1761
1762         if (tmp & SDVO_AUDIO_ENABLE)
1763                 pipe_config->has_audio = true;
1764
1765         if (!HAS_PCH_SPLIT(dev_priv) &&
1766             tmp & HDMI_COLOR_RANGE_16_235)
1767                 pipe_config->limited_color_range = true;
1768
1769         pipe_config->base.adjusted_mode.flags |= flags;
1770
1771         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1772                 dotclock = pipe_config->port_clock * 2 / 3;
1773         else
1774                 dotclock = pipe_config->port_clock;
1775
1776         if (pipe_config->pixel_multiplier)
1777                 dotclock /= pipe_config->pixel_multiplier;
1778
1779         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1780
1781         pipe_config->lane_count = 4;
1782
1783         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1784
1785         intel_read_infoframe(encoder, pipe_config,
1786                              HDMI_INFOFRAME_TYPE_AVI,
1787                              &pipe_config->infoframes.avi);
1788         intel_read_infoframe(encoder, pipe_config,
1789                              HDMI_INFOFRAME_TYPE_SPD,
1790                              &pipe_config->infoframes.spd);
1791         intel_read_infoframe(encoder, pipe_config,
1792                              HDMI_INFOFRAME_TYPE_VENDOR,
1793                              &pipe_config->infoframes.hdmi);
1794 }
1795
1796 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1797                                     const struct intel_crtc_state *pipe_config,
1798                                     const struct drm_connector_state *conn_state)
1799 {
1800         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1801
1802         WARN_ON(!pipe_config->has_hdmi_sink);
1803         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1804                          pipe_name(crtc->pipe));
1805         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1806 }
1807
1808 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1809                             const struct intel_crtc_state *pipe_config,
1810                             const struct drm_connector_state *conn_state)
1811 {
1812         struct drm_device *dev = encoder->base.dev;
1813         struct drm_i915_private *dev_priv = to_i915(dev);
1814         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1815         u32 temp;
1816
1817         temp = I915_READ(intel_hdmi->hdmi_reg);
1818
1819         temp |= SDVO_ENABLE;
1820         if (pipe_config->has_audio)
1821                 temp |= SDVO_AUDIO_ENABLE;
1822
1823         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1824         POSTING_READ(intel_hdmi->hdmi_reg);
1825
1826         if (pipe_config->has_audio)
1827                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1828 }
1829
1830 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1831                             const struct intel_crtc_state *pipe_config,
1832                             const struct drm_connector_state *conn_state)
1833 {
1834         struct drm_device *dev = encoder->base.dev;
1835         struct drm_i915_private *dev_priv = to_i915(dev);
1836         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1837         u32 temp;
1838
1839         temp = I915_READ(intel_hdmi->hdmi_reg);
1840
1841         temp |= SDVO_ENABLE;
1842         if (pipe_config->has_audio)
1843                 temp |= SDVO_AUDIO_ENABLE;
1844
1845         /*
1846          * HW workaround, need to write this twice for issue
1847          * that may result in first write getting masked.
1848          */
1849         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1850         POSTING_READ(intel_hdmi->hdmi_reg);
1851         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1852         POSTING_READ(intel_hdmi->hdmi_reg);
1853
1854         /*
1855          * HW workaround, need to toggle enable bit off and on
1856          * for 12bpc with pixel repeat.
1857          *
1858          * FIXME: BSpec says this should be done at the end of
1859          * of the modeset sequence, so not sure if this isn't too soon.
1860          */
1861         if (pipe_config->pipe_bpp > 24 &&
1862             pipe_config->pixel_multiplier > 1) {
1863                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1864                 POSTING_READ(intel_hdmi->hdmi_reg);
1865
1866                 /*
1867                  * HW workaround, need to write this twice for issue
1868                  * that may result in first write getting masked.
1869                  */
1870                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1871                 POSTING_READ(intel_hdmi->hdmi_reg);
1872                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1873                 POSTING_READ(intel_hdmi->hdmi_reg);
1874         }
1875
1876         if (pipe_config->has_audio)
1877                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1878 }
1879
1880 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1881                             const struct intel_crtc_state *pipe_config,
1882                             const struct drm_connector_state *conn_state)
1883 {
1884         struct drm_device *dev = encoder->base.dev;
1885         struct drm_i915_private *dev_priv = to_i915(dev);
1886         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1887         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1888         enum pipe pipe = crtc->pipe;
1889         u32 temp;
1890
1891         temp = I915_READ(intel_hdmi->hdmi_reg);
1892
1893         temp |= SDVO_ENABLE;
1894         if (pipe_config->has_audio)
1895                 temp |= SDVO_AUDIO_ENABLE;
1896
1897         /*
1898          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1899          *
1900          * The procedure for 12bpc is as follows:
1901          * 1. disable HDMI clock gating
1902          * 2. enable HDMI with 8bpc
1903          * 3. enable HDMI with 12bpc
1904          * 4. enable HDMI clock gating
1905          */
1906
1907         if (pipe_config->pipe_bpp > 24) {
1908                 I915_WRITE(TRANS_CHICKEN1(pipe),
1909                            I915_READ(TRANS_CHICKEN1(pipe)) |
1910                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1911
1912                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1913                 temp |= SDVO_COLOR_FORMAT_8bpc;
1914         }
1915
1916         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1917         POSTING_READ(intel_hdmi->hdmi_reg);
1918
1919         if (pipe_config->pipe_bpp > 24) {
1920                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1921                 temp |= HDMI_COLOR_FORMAT_12bpc;
1922
1923                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1924                 POSTING_READ(intel_hdmi->hdmi_reg);
1925
1926                 I915_WRITE(TRANS_CHICKEN1(pipe),
1927                            I915_READ(TRANS_CHICKEN1(pipe)) &
1928                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1929         }
1930
1931         if (pipe_config->has_audio)
1932                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1933 }
1934
1935 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1936                             const struct intel_crtc_state *pipe_config,
1937                             const struct drm_connector_state *conn_state)
1938 {
1939 }
1940
1941 static void intel_disable_hdmi(struct intel_encoder *encoder,
1942                                const struct intel_crtc_state *old_crtc_state,
1943                                const struct drm_connector_state *old_conn_state)
1944 {
1945         struct drm_device *dev = encoder->base.dev;
1946         struct drm_i915_private *dev_priv = to_i915(dev);
1947         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1948         struct intel_digital_port *intel_dig_port =
1949                 hdmi_to_dig_port(intel_hdmi);
1950         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1951         u32 temp;
1952
1953         temp = I915_READ(intel_hdmi->hdmi_reg);
1954
1955         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1956         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1957         POSTING_READ(intel_hdmi->hdmi_reg);
1958
1959         /*
1960          * HW workaround for IBX, we need to move the port
1961          * to transcoder A after disabling it to allow the
1962          * matching DP port to be enabled on transcoder A.
1963          */
1964         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1965                 /*
1966                  * We get CPU/PCH FIFO underruns on the other pipe when
1967                  * doing the workaround. Sweep them under the rug.
1968                  */
1969                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1970                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1971
1972                 temp &= ~SDVO_PIPE_SEL_MASK;
1973                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1974                 /*
1975                  * HW workaround, need to write this twice for issue
1976                  * that may result in first write getting masked.
1977                  */
1978                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1979                 POSTING_READ(intel_hdmi->hdmi_reg);
1980                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1981                 POSTING_READ(intel_hdmi->hdmi_reg);
1982
1983                 temp &= ~SDVO_ENABLE;
1984                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1985                 POSTING_READ(intel_hdmi->hdmi_reg);
1986
1987                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1988                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1989                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1990         }
1991
1992         intel_dig_port->set_infoframes(encoder,
1993                                        false,
1994                                        old_crtc_state, old_conn_state);
1995
1996         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1997 }
1998
1999 static void g4x_disable_hdmi(struct intel_encoder *encoder,
2000                              const struct intel_crtc_state *old_crtc_state,
2001                              const struct drm_connector_state *old_conn_state)
2002 {
2003         if (old_crtc_state->has_audio)
2004                 intel_audio_codec_disable(encoder,
2005                                           old_crtc_state, old_conn_state);
2006
2007         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2008 }
2009
2010 static void pch_disable_hdmi(struct intel_encoder *encoder,
2011                              const struct intel_crtc_state *old_crtc_state,
2012                              const struct drm_connector_state *old_conn_state)
2013 {
2014         if (old_crtc_state->has_audio)
2015                 intel_audio_codec_disable(encoder,
2016                                           old_crtc_state, old_conn_state);
2017 }
2018
2019 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
2020                                   const struct intel_crtc_state *old_crtc_state,
2021                                   const struct drm_connector_state *old_conn_state)
2022 {
2023         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2024 }
2025
2026 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2027 {
2028         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2029         const struct ddi_vbt_port_info *info =
2030                 &dev_priv->vbt.ddi_port_info[encoder->port];
2031         int max_tmds_clock;
2032
2033         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2034                 max_tmds_clock = 594000;
2035         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2036                 max_tmds_clock = 300000;
2037         else if (INTEL_GEN(dev_priv) >= 5)
2038                 max_tmds_clock = 225000;
2039         else
2040                 max_tmds_clock = 165000;
2041
2042         if (info->max_tmds_clock)
2043                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
2044
2045         return max_tmds_clock;
2046 }
2047
2048 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2049                                  bool respect_downstream_limits,
2050                                  bool force_dvi)
2051 {
2052         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2053         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2054
2055         if (respect_downstream_limits) {
2056                 struct intel_connector *connector = hdmi->attached_connector;
2057                 const struct drm_display_info *info = &connector->base.display_info;
2058
2059                 if (hdmi->dp_dual_mode.max_tmds_clock)
2060                         max_tmds_clock = min(max_tmds_clock,
2061                                              hdmi->dp_dual_mode.max_tmds_clock);
2062
2063                 if (info->max_tmds_clock)
2064                         max_tmds_clock = min(max_tmds_clock,
2065                                              info->max_tmds_clock);
2066                 else if (!hdmi->has_hdmi_sink || force_dvi)
2067                         max_tmds_clock = min(max_tmds_clock, 165000);
2068         }
2069
2070         return max_tmds_clock;
2071 }
2072
2073 static enum drm_mode_status
2074 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2075                       int clock, bool respect_downstream_limits,
2076                       bool force_dvi)
2077 {
2078         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2079
2080         if (clock < 25000)
2081                 return MODE_CLOCK_LOW;
2082         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
2083                 return MODE_CLOCK_HIGH;
2084
2085         /* BXT DPLL can't generate 223-240 MHz */
2086         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2087                 return MODE_CLOCK_RANGE;
2088
2089         /* CHV DPLL can't generate 216-240 MHz */
2090         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2091                 return MODE_CLOCK_RANGE;
2092
2093         return MODE_OK;
2094 }
2095
2096 static enum drm_mode_status
2097 intel_hdmi_mode_valid(struct drm_connector *connector,
2098                       struct drm_display_mode *mode)
2099 {
2100         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2101         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2102         struct drm_i915_private *dev_priv = to_i915(dev);
2103         enum drm_mode_status status;
2104         int clock;
2105         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2106         bool force_dvi =
2107                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
2108
2109         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2110                 return MODE_NO_DBLESCAN;
2111
2112         clock = mode->clock;
2113
2114         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2115                 clock *= 2;
2116
2117         if (clock > max_dotclk)
2118                 return MODE_CLOCK_HIGH;
2119
2120         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2121                 clock *= 2;
2122
2123         if (drm_mode_is_420_only(&connector->display_info, mode))
2124                 clock /= 2;
2125
2126         /* check if we can do 8bpc */
2127         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
2128
2129         if (hdmi->has_hdmi_sink && !force_dvi) {
2130                 /* if we can't do 8bpc we may still be able to do 12bpc */
2131                 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2132                         status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2133                                                        true, force_dvi);
2134
2135                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2136                 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2137                         status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2138                                                        true, force_dvi);
2139         }
2140
2141         return status;
2142 }
2143
2144 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2145                                      int bpc)
2146 {
2147         struct drm_i915_private *dev_priv =
2148                 to_i915(crtc_state->base.crtc->dev);
2149         struct drm_atomic_state *state = crtc_state->base.state;
2150         struct drm_connector_state *connector_state;
2151         struct drm_connector *connector;
2152         const struct drm_display_mode *adjusted_mode =
2153                 &crtc_state->base.adjusted_mode;
2154         int i;
2155
2156         if (HAS_GMCH(dev_priv))
2157                 return false;
2158
2159         if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2160                 return false;
2161
2162         if (crtc_state->pipe_bpp <= 8*3)
2163                 return false;
2164
2165         if (!crtc_state->has_hdmi_sink)
2166                 return false;
2167
2168         /*
2169          * HDMI deep color affects the clocks, so it's only possible
2170          * when not cloning with other encoder types.
2171          */
2172         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2173                 return false;
2174
2175         for_each_new_connector_in_state(state, connector, connector_state, i) {
2176                 const struct drm_display_info *info = &connector->display_info;
2177
2178                 if (connector_state->crtc != crtc_state->base.crtc)
2179                         continue;
2180
2181                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2182                         const struct drm_hdmi_info *hdmi = &info->hdmi;
2183
2184                         if (bpc == 12 && !(hdmi->y420_dc_modes &
2185                                            DRM_EDID_YCBCR420_DC_36))
2186                                 return false;
2187                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
2188                                                 DRM_EDID_YCBCR420_DC_30))
2189                                 return false;
2190                 } else {
2191                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2192                                            DRM_EDID_HDMI_DC_36))
2193                                 return false;
2194                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2195                                                 DRM_EDID_HDMI_DC_30))
2196                                 return false;
2197                 }
2198         }
2199
2200         /* Display WA #1139: glk */
2201         if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
2202             adjusted_mode->htotal > 5460)
2203                 return false;
2204
2205         /* Display Wa_1405510057:icl */
2206         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2207             bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
2208             (adjusted_mode->crtc_hblank_end -
2209              adjusted_mode->crtc_hblank_start) % 8 == 2)
2210                 return false;
2211
2212         return true;
2213 }
2214
2215 static bool
2216 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
2217                            struct intel_crtc_state *config,
2218                            int *clock_12bpc, int *clock_10bpc,
2219                            int *clock_8bpc)
2220 {
2221         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
2222
2223         if (!connector->ycbcr_420_allowed) {
2224                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2225                 return false;
2226         }
2227
2228         /* YCBCR420 TMDS rate requirement is half the pixel clock */
2229         config->port_clock /= 2;
2230         *clock_12bpc /= 2;
2231         *clock_10bpc /= 2;
2232         *clock_8bpc /= 2;
2233         config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2234
2235         /* YCBCR 420 output conversion needs a scaler */
2236         if (skl_update_scaler_crtc(config)) {
2237                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2238                 return false;
2239         }
2240
2241         intel_pch_panel_fitting(intel_crtc, config,
2242                                 DRM_MODE_SCALE_FULLSCREEN);
2243
2244         return true;
2245 }
2246
2247 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2248                               struct intel_crtc_state *pipe_config,
2249                               struct drm_connector_state *conn_state)
2250 {
2251         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2252         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2253         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2254         struct drm_connector *connector = conn_state->connector;
2255         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2256         struct intel_digital_connector_state *intel_conn_state =
2257                 to_intel_digital_connector_state(conn_state);
2258         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
2259         int clock_10bpc = clock_8bpc * 5 / 4;
2260         int clock_12bpc = clock_8bpc * 3 / 2;
2261         int desired_bpp;
2262         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
2263
2264         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2265                 return -EINVAL;
2266
2267         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2268         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
2269
2270         if (pipe_config->has_hdmi_sink)
2271                 pipe_config->has_infoframe = true;
2272
2273         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2274                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2275                 pipe_config->limited_color_range =
2276                         pipe_config->has_hdmi_sink &&
2277                         drm_default_rgb_quant_range(adjusted_mode) ==
2278                         HDMI_QUANTIZATION_RANGE_LIMITED;
2279         } else {
2280                 pipe_config->limited_color_range =
2281                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2282         }
2283
2284         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
2285                 pipe_config->pixel_multiplier = 2;
2286                 clock_8bpc *= 2;
2287                 clock_10bpc *= 2;
2288                 clock_12bpc *= 2;
2289         }
2290
2291         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
2292                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
2293                                                 &clock_12bpc, &clock_10bpc,
2294                                                 &clock_8bpc)) {
2295                         DRM_ERROR("Can't support YCBCR420 output\n");
2296                         return -EINVAL;
2297                 }
2298         }
2299
2300         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2301                 pipe_config->has_pch_encoder = true;
2302
2303         if (pipe_config->has_hdmi_sink) {
2304                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2305                         pipe_config->has_audio = intel_hdmi->has_audio;
2306                 else
2307                         pipe_config->has_audio =
2308                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2309         }
2310
2311         /*
2312          * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
2313          * to check that the higher clock still fits within limits.
2314          */
2315         if (hdmi_deep_color_possible(pipe_config, 12) &&
2316             hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
2317                                   true, force_dvi) == MODE_OK) {
2318                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
2319                 desired_bpp = 12*3;
2320
2321                 /* Need to adjust the port link by 1.5x for 12bpc. */
2322                 pipe_config->port_clock = clock_12bpc;
2323         } else if (hdmi_deep_color_possible(pipe_config, 10) &&
2324                    hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
2325                                          true, force_dvi) == MODE_OK) {
2326                 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
2327                 desired_bpp = 10 * 3;
2328
2329                 /* Need to adjust the port link by 1.25x for 10bpc. */
2330                 pipe_config->port_clock = clock_10bpc;
2331         } else {
2332                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
2333                 desired_bpp = 8*3;
2334
2335                 pipe_config->port_clock = clock_8bpc;
2336         }
2337
2338         if (!pipe_config->bw_constrained) {
2339                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
2340                 pipe_config->pipe_bpp = desired_bpp;
2341         }
2342
2343         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
2344                                   false, force_dvi) != MODE_OK) {
2345                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
2346                 return -EINVAL;
2347         }
2348
2349         /* Set user selected PAR to incoming mode's member */
2350         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
2351
2352         pipe_config->lane_count = 4;
2353
2354         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2355                                            IS_GEMINILAKE(dev_priv))) {
2356                 if (scdc->scrambling.low_rates)
2357                         pipe_config->hdmi_scrambling = true;
2358
2359                 if (pipe_config->port_clock > 340000) {
2360                         pipe_config->hdmi_scrambling = true;
2361                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2362                 }
2363         }
2364
2365         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state);
2366
2367         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2368                 DRM_DEBUG_KMS("bad AVI infoframe\n");
2369                 return -EINVAL;
2370         }
2371
2372         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2373                 DRM_DEBUG_KMS("bad SPD infoframe\n");
2374                 return -EINVAL;
2375         }
2376
2377         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2378                 DRM_DEBUG_KMS("bad HDMI infoframe\n");
2379                 return -EINVAL;
2380         }
2381
2382         return 0;
2383 }
2384
2385 static void
2386 intel_hdmi_unset_edid(struct drm_connector *connector)
2387 {
2388         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2389
2390         intel_hdmi->has_hdmi_sink = false;
2391         intel_hdmi->has_audio = false;
2392
2393         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2394         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2395
2396         kfree(to_intel_connector(connector)->detect_edid);
2397         to_intel_connector(connector)->detect_edid = NULL;
2398 }
2399
2400 static void
2401 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2402 {
2403         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2404         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2405         enum port port = hdmi_to_dig_port(hdmi)->base.port;
2406         struct i2c_adapter *adapter =
2407                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2408         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2409
2410         /*
2411          * Type 1 DVI adaptors are not required to implement any
2412          * registers, so we can't always detect their presence.
2413          * Ideally we should be able to check the state of the
2414          * CONFIG1 pin, but no such luck on our hardware.
2415          *
2416          * The only method left to us is to check the VBT to see
2417          * if the port is a dual mode capable DP port. But let's
2418          * only do that when we sucesfully read the EDID, to avoid
2419          * confusing log messages about DP dual mode adaptors when
2420          * there's nothing connected to the port.
2421          */
2422         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2423                 /* An overridden EDID imply that we want this port for testing.
2424                  * Make sure not to set limits for that port.
2425                  */
2426                 if (has_edid && !connector->override_edid &&
2427                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2428                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2429                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2430                 } else {
2431                         type = DRM_DP_DUAL_MODE_NONE;
2432                 }
2433         }
2434
2435         if (type == DRM_DP_DUAL_MODE_NONE)
2436                 return;
2437
2438         hdmi->dp_dual_mode.type = type;
2439         hdmi->dp_dual_mode.max_tmds_clock =
2440                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2441
2442         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2443                       drm_dp_get_dual_mode_type_name(type),
2444                       hdmi->dp_dual_mode.max_tmds_clock);
2445 }
2446
2447 static bool
2448 intel_hdmi_set_edid(struct drm_connector *connector)
2449 {
2450         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2451         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2452         intel_wakeref_t wakeref;
2453         struct edid *edid;
2454         bool connected = false;
2455         struct i2c_adapter *i2c;
2456
2457         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2458
2459         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2460
2461         edid = drm_get_edid(connector, i2c);
2462
2463         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2464                 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2465                 intel_gmbus_force_bit(i2c, true);
2466                 edid = drm_get_edid(connector, i2c);
2467                 intel_gmbus_force_bit(i2c, false);
2468         }
2469
2470         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2471
2472         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2473
2474         to_intel_connector(connector)->detect_edid = edid;
2475         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2476                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2477                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2478
2479                 connected = true;
2480         }
2481
2482         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2483
2484         return connected;
2485 }
2486
2487 static enum drm_connector_status
2488 intel_hdmi_detect(struct drm_connector *connector, bool force)
2489 {
2490         enum drm_connector_status status = connector_status_disconnected;
2491         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2492         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2493         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2494         intel_wakeref_t wakeref;
2495
2496         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2497                       connector->base.id, connector->name);
2498
2499         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2500
2501         if (INTEL_GEN(dev_priv) >= 11 &&
2502             !intel_digital_port_connected(encoder))
2503                 goto out;
2504
2505         intel_hdmi_unset_edid(connector);
2506
2507         if (intel_hdmi_set_edid(connector))
2508                 status = connector_status_connected;
2509
2510 out:
2511         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2512
2513         if (status != connector_status_connected)
2514                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2515
2516         return status;
2517 }
2518
2519 static void
2520 intel_hdmi_force(struct drm_connector *connector)
2521 {
2522         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2523                       connector->base.id, connector->name);
2524
2525         intel_hdmi_unset_edid(connector);
2526
2527         if (connector->status != connector_status_connected)
2528                 return;
2529
2530         intel_hdmi_set_edid(connector);
2531 }
2532
2533 static int intel_hdmi_get_modes(struct drm_connector *connector)
2534 {
2535         struct edid *edid;
2536
2537         edid = to_intel_connector(connector)->detect_edid;
2538         if (edid == NULL)
2539                 return 0;
2540
2541         return intel_connector_update_modes(connector, edid);
2542 }
2543
2544 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
2545                                   const struct intel_crtc_state *pipe_config,
2546                                   const struct drm_connector_state *conn_state)
2547 {
2548         struct intel_digital_port *intel_dig_port =
2549                 enc_to_dig_port(&encoder->base);
2550
2551         intel_hdmi_prepare(encoder, pipe_config);
2552
2553         intel_dig_port->set_infoframes(encoder,
2554                                        pipe_config->has_infoframe,
2555                                        pipe_config, conn_state);
2556 }
2557
2558 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2559                                 const struct intel_crtc_state *pipe_config,
2560                                 const struct drm_connector_state *conn_state)
2561 {
2562         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2563         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2564
2565         vlv_phy_pre_encoder_enable(encoder, pipe_config);
2566
2567         /* HDMI 1.0V-2dB */
2568         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2569                                  0x2b247878);
2570
2571         dport->set_infoframes(encoder,
2572                               pipe_config->has_infoframe,
2573                               pipe_config, conn_state);
2574
2575         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2576
2577         vlv_wait_port_ready(dev_priv, dport, 0x0);
2578 }
2579
2580 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2581                                     const struct intel_crtc_state *pipe_config,
2582                                     const struct drm_connector_state *conn_state)
2583 {
2584         intel_hdmi_prepare(encoder, pipe_config);
2585
2586         vlv_phy_pre_pll_enable(encoder, pipe_config);
2587 }
2588
2589 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2590                                     const struct intel_crtc_state *pipe_config,
2591                                     const struct drm_connector_state *conn_state)
2592 {
2593         intel_hdmi_prepare(encoder, pipe_config);
2594
2595         chv_phy_pre_pll_enable(encoder, pipe_config);
2596 }
2597
2598 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2599                                       const struct intel_crtc_state *old_crtc_state,
2600                                       const struct drm_connector_state *old_conn_state)
2601 {
2602         chv_phy_post_pll_disable(encoder, old_crtc_state);
2603 }
2604
2605 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2606                                   const struct intel_crtc_state *old_crtc_state,
2607                                   const struct drm_connector_state *old_conn_state)
2608 {
2609         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2610         vlv_phy_reset_lanes(encoder, old_crtc_state);
2611 }
2612
2613 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2614                                   const struct intel_crtc_state *old_crtc_state,
2615                                   const struct drm_connector_state *old_conn_state)
2616 {
2617         struct drm_device *dev = encoder->base.dev;
2618         struct drm_i915_private *dev_priv = to_i915(dev);
2619
2620         mutex_lock(&dev_priv->sb_lock);
2621
2622         /* Assert data lane reset */
2623         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2624
2625         mutex_unlock(&dev_priv->sb_lock);
2626 }
2627
2628 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2629                                 const struct intel_crtc_state *pipe_config,
2630                                 const struct drm_connector_state *conn_state)
2631 {
2632         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2633         struct drm_device *dev = encoder->base.dev;
2634         struct drm_i915_private *dev_priv = to_i915(dev);
2635
2636         chv_phy_pre_encoder_enable(encoder, pipe_config);
2637
2638         /* FIXME: Program the support xxx V-dB */
2639         /* Use 800mV-0dB */
2640         chv_set_phy_signal_level(encoder, 128, 102, false);
2641
2642         dport->set_infoframes(encoder,
2643                               pipe_config->has_infoframe,
2644                               pipe_config, conn_state);
2645
2646         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2647
2648         vlv_wait_port_ready(dev_priv, dport, 0x0);
2649
2650         /* Second common lane will stay alive on its own now */
2651         chv_phy_release_cl2_override(encoder);
2652 }
2653
2654 static int
2655 intel_hdmi_connector_register(struct drm_connector *connector)
2656 {
2657         int ret;
2658
2659         ret = intel_connector_register(connector);
2660         if (ret)
2661                 return ret;
2662
2663         i915_debugfs_connector_add(connector);
2664
2665         return ret;
2666 }
2667
2668 static void intel_hdmi_destroy(struct drm_connector *connector)
2669 {
2670         if (intel_attached_hdmi(connector)->cec_notifier)
2671                 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2672
2673         intel_connector_destroy(connector);
2674 }
2675
2676 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2677         .detect = intel_hdmi_detect,
2678         .force = intel_hdmi_force,
2679         .fill_modes = drm_helper_probe_single_connector_modes,
2680         .atomic_get_property = intel_digital_connector_atomic_get_property,
2681         .atomic_set_property = intel_digital_connector_atomic_set_property,
2682         .late_register = intel_hdmi_connector_register,
2683         .early_unregister = intel_connector_unregister,
2684         .destroy = intel_hdmi_destroy,
2685         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2686         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2687 };
2688
2689 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2690         .get_modes = intel_hdmi_get_modes,
2691         .mode_valid = intel_hdmi_mode_valid,
2692         .atomic_check = intel_digital_connector_atomic_check,
2693 };
2694
2695 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2696         .destroy = intel_encoder_destroy,
2697 };
2698
2699 static void
2700 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2701 {
2702         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2703
2704         intel_attach_force_audio_property(connector);
2705         intel_attach_broadcast_rgb_property(connector);
2706         intel_attach_aspect_ratio_property(connector);
2707         drm_connector_attach_content_type_property(connector);
2708         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2709
2710         if (!HAS_GMCH(dev_priv))
2711                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2712 }
2713
2714 /*
2715  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2716  * @encoder: intel_encoder
2717  * @connector: drm_connector
2718  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2719  *  or reset the high tmds clock ratio for scrambling
2720  * @scrambling: bool to Indicate if the function needs to set or reset
2721  *  sink scrambling
2722  *
2723  * This function handles scrambling on HDMI 2.0 capable sinks.
2724  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2725  * it enables scrambling. This should be called before enabling the HDMI
2726  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2727  * detect a scrambled clock within 100 ms.
2728  *
2729  * Returns:
2730  * True on success, false on failure.
2731  */
2732 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2733                                        struct drm_connector *connector,
2734                                        bool high_tmds_clock_ratio,
2735                                        bool scrambling)
2736 {
2737         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2738         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2739         struct drm_scrambling *sink_scrambling =
2740                 &connector->display_info.hdmi.scdc.scrambling;
2741         struct i2c_adapter *adapter =
2742                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2743
2744         if (!sink_scrambling->supported)
2745                 return true;
2746
2747         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2748                       connector->base.id, connector->name,
2749                       yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2750
2751         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2752         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2753                                                   high_tmds_clock_ratio) &&
2754                 drm_scdc_set_scrambling(adapter, scrambling);
2755 }
2756
2757 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2758 {
2759         u8 ddc_pin;
2760
2761         switch (port) {
2762         case PORT_B:
2763                 ddc_pin = GMBUS_PIN_DPB;
2764                 break;
2765         case PORT_C:
2766                 ddc_pin = GMBUS_PIN_DPC;
2767                 break;
2768         case PORT_D:
2769                 ddc_pin = GMBUS_PIN_DPD_CHV;
2770                 break;
2771         default:
2772                 MISSING_CASE(port);
2773                 ddc_pin = GMBUS_PIN_DPB;
2774                 break;
2775         }
2776         return ddc_pin;
2777 }
2778
2779 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2780 {
2781         u8 ddc_pin;
2782
2783         switch (port) {
2784         case PORT_B:
2785                 ddc_pin = GMBUS_PIN_1_BXT;
2786                 break;
2787         case PORT_C:
2788                 ddc_pin = GMBUS_PIN_2_BXT;
2789                 break;
2790         default:
2791                 MISSING_CASE(port);
2792                 ddc_pin = GMBUS_PIN_1_BXT;
2793                 break;
2794         }
2795         return ddc_pin;
2796 }
2797
2798 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2799                               enum port port)
2800 {
2801         u8 ddc_pin;
2802
2803         switch (port) {
2804         case PORT_B:
2805                 ddc_pin = GMBUS_PIN_1_BXT;
2806                 break;
2807         case PORT_C:
2808                 ddc_pin = GMBUS_PIN_2_BXT;
2809                 break;
2810         case PORT_D:
2811                 ddc_pin = GMBUS_PIN_4_CNP;
2812                 break;
2813         case PORT_F:
2814                 ddc_pin = GMBUS_PIN_3_BXT;
2815                 break;
2816         default:
2817                 MISSING_CASE(port);
2818                 ddc_pin = GMBUS_PIN_1_BXT;
2819                 break;
2820         }
2821         return ddc_pin;
2822 }
2823
2824 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2825 {
2826         u8 ddc_pin;
2827
2828         switch (port) {
2829         case PORT_A:
2830                 ddc_pin = GMBUS_PIN_1_BXT;
2831                 break;
2832         case PORT_B:
2833                 ddc_pin = GMBUS_PIN_2_BXT;
2834                 break;
2835         case PORT_C:
2836                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2837                 break;
2838         case PORT_D:
2839                 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2840                 break;
2841         case PORT_E:
2842                 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2843                 break;
2844         case PORT_F:
2845                 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2846                 break;
2847         default:
2848                 MISSING_CASE(port);
2849                 ddc_pin = GMBUS_PIN_2_BXT;
2850                 break;
2851         }
2852         return ddc_pin;
2853 }
2854
2855 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2856                               enum port port)
2857 {
2858         u8 ddc_pin;
2859
2860         switch (port) {
2861         case PORT_B:
2862                 ddc_pin = GMBUS_PIN_DPB;
2863                 break;
2864         case PORT_C:
2865                 ddc_pin = GMBUS_PIN_DPC;
2866                 break;
2867         case PORT_D:
2868                 ddc_pin = GMBUS_PIN_DPD;
2869                 break;
2870         default:
2871                 MISSING_CASE(port);
2872                 ddc_pin = GMBUS_PIN_DPB;
2873                 break;
2874         }
2875         return ddc_pin;
2876 }
2877
2878 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2879                              enum port port)
2880 {
2881         const struct ddi_vbt_port_info *info =
2882                 &dev_priv->vbt.ddi_port_info[port];
2883         u8 ddc_pin;
2884
2885         if (info->alternate_ddc_pin) {
2886                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2887                               info->alternate_ddc_pin, port_name(port));
2888                 return info->alternate_ddc_pin;
2889         }
2890
2891         if (HAS_PCH_ICP(dev_priv))
2892                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2893         else if (HAS_PCH_CNP(dev_priv))
2894                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2895         else if (IS_GEN9_LP(dev_priv))
2896                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2897         else if (IS_CHERRYVIEW(dev_priv))
2898                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2899         else
2900                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2901
2902         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2903                       ddc_pin, port_name(port));
2904
2905         return ddc_pin;
2906 }
2907
2908 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2909 {
2910         struct drm_i915_private *dev_priv =
2911                 to_i915(intel_dig_port->base.base.dev);
2912
2913         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2914                 intel_dig_port->write_infoframe = vlv_write_infoframe;
2915                 intel_dig_port->read_infoframe = vlv_read_infoframe;
2916                 intel_dig_port->set_infoframes = vlv_set_infoframes;
2917                 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
2918         } else if (IS_G4X(dev_priv)) {
2919                 intel_dig_port->write_infoframe = g4x_write_infoframe;
2920                 intel_dig_port->read_infoframe = g4x_read_infoframe;
2921                 intel_dig_port->set_infoframes = g4x_set_infoframes;
2922                 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
2923         } else if (HAS_DDI(dev_priv)) {
2924                 if (intel_dig_port->lspcon.active) {
2925                         intel_dig_port->write_infoframe = lspcon_write_infoframe;
2926                         intel_dig_port->read_infoframe = lspcon_read_infoframe;
2927                         intel_dig_port->set_infoframes = lspcon_set_infoframes;
2928                         intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2929                 } else {
2930                         intel_dig_port->write_infoframe = hsw_write_infoframe;
2931                         intel_dig_port->read_infoframe = hsw_read_infoframe;
2932                         intel_dig_port->set_infoframes = hsw_set_infoframes;
2933                         intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
2934                 }
2935         } else if (HAS_PCH_IBX(dev_priv)) {
2936                 intel_dig_port->write_infoframe = ibx_write_infoframe;
2937                 intel_dig_port->read_infoframe = ibx_read_infoframe;
2938                 intel_dig_port->set_infoframes = ibx_set_infoframes;
2939                 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
2940         } else {
2941                 intel_dig_port->write_infoframe = cpt_write_infoframe;
2942                 intel_dig_port->read_infoframe = cpt_read_infoframe;
2943                 intel_dig_port->set_infoframes = cpt_set_infoframes;
2944                 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
2945         }
2946 }
2947
2948 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2949                                struct intel_connector *intel_connector)
2950 {
2951         struct drm_connector *connector = &intel_connector->base;
2952         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2953         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2954         struct drm_device *dev = intel_encoder->base.dev;
2955         struct drm_i915_private *dev_priv = to_i915(dev);
2956         enum port port = intel_encoder->port;
2957
2958         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2959                       port_name(port));
2960
2961         if (WARN(intel_dig_port->max_lanes < 4,
2962                  "Not enough lanes (%d) for HDMI on port %c\n",
2963                  intel_dig_port->max_lanes, port_name(port)))
2964                 return;
2965
2966         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2967                            DRM_MODE_CONNECTOR_HDMIA);
2968         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2969
2970         connector->interlace_allowed = 1;
2971         connector->doublescan_allowed = 0;
2972         connector->stereo_allowed = 1;
2973
2974         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2975                 connector->ycbcr_420_allowed = true;
2976
2977         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2978
2979         if (WARN_ON(port == PORT_A))
2980                 return;
2981         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2982
2983         if (HAS_DDI(dev_priv))
2984                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2985         else
2986                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2987
2988         intel_hdmi_add_properties(intel_hdmi, connector);
2989
2990         intel_connector_attach_encoder(intel_connector, intel_encoder);
2991         intel_hdmi->attached_connector = intel_connector;
2992
2993         if (is_hdcp_supported(dev_priv, port)) {
2994                 int ret = intel_hdcp_init(intel_connector,
2995                                           &intel_hdmi_hdcp_shim);
2996                 if (ret)
2997                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
2998         }
2999
3000         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3001          * 0xd.  Failure to do so will result in spurious interrupts being
3002          * generated on the port when a cable is not attached.
3003          */
3004         if (IS_G45(dev_priv)) {
3005                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3006                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3007         }
3008
3009         intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
3010                                                          port_identifier(port));
3011         if (!intel_hdmi->cec_notifier)
3012                 DRM_DEBUG_KMS("CEC notifier get failed\n");
3013 }
3014
3015 void intel_hdmi_init(struct drm_i915_private *dev_priv,
3016                      i915_reg_t hdmi_reg, enum port port)
3017 {
3018         struct intel_digital_port *intel_dig_port;
3019         struct intel_encoder *intel_encoder;
3020         struct intel_connector *intel_connector;
3021
3022         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3023         if (!intel_dig_port)
3024                 return;
3025
3026         intel_connector = intel_connector_alloc();
3027         if (!intel_connector) {
3028                 kfree(intel_dig_port);
3029                 return;
3030         }
3031
3032         intel_encoder = &intel_dig_port->base;
3033
3034         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3035                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3036                          "HDMI %c", port_name(port));
3037
3038         intel_encoder->hotplug = intel_encoder_hotplug;
3039         intel_encoder->compute_config = intel_hdmi_compute_config;
3040         if (HAS_PCH_SPLIT(dev_priv)) {
3041                 intel_encoder->disable = pch_disable_hdmi;
3042                 intel_encoder->post_disable = pch_post_disable_hdmi;
3043         } else {
3044                 intel_encoder->disable = g4x_disable_hdmi;
3045         }
3046         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3047         intel_encoder->get_config = intel_hdmi_get_config;
3048         if (IS_CHERRYVIEW(dev_priv)) {
3049                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3050                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3051                 intel_encoder->enable = vlv_enable_hdmi;
3052                 intel_encoder->post_disable = chv_hdmi_post_disable;
3053                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3054         } else if (IS_VALLEYVIEW(dev_priv)) {
3055                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3056                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3057                 intel_encoder->enable = vlv_enable_hdmi;
3058                 intel_encoder->post_disable = vlv_hdmi_post_disable;
3059         } else {
3060                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3061                 if (HAS_PCH_CPT(dev_priv))
3062                         intel_encoder->enable = cpt_enable_hdmi;
3063                 else if (HAS_PCH_IBX(dev_priv))
3064                         intel_encoder->enable = ibx_enable_hdmi;
3065                 else
3066                         intel_encoder->enable = g4x_enable_hdmi;
3067         }
3068
3069         intel_encoder->type = INTEL_OUTPUT_HDMI;
3070         intel_encoder->power_domain = intel_port_to_power_domain(port);
3071         intel_encoder->port = port;
3072         if (IS_CHERRYVIEW(dev_priv)) {
3073                 if (port == PORT_D)
3074                         intel_encoder->crtc_mask = 1 << 2;
3075                 else
3076                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
3077         } else {
3078                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3079         }
3080         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3081         /*
3082          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3083          * to work on real hardware. And since g4x can send infoframes to
3084          * only one port anyway, nothing is lost by allowing it.
3085          */
3086         if (IS_G4X(dev_priv))
3087                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3088
3089         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
3090         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3091         intel_dig_port->max_lanes = 4;
3092
3093         intel_infoframe_init(intel_dig_port);
3094
3095         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3096         intel_hdmi_init_connector(intel_dig_port, intel_connector);
3097 }