drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return HAS_FBC(dev_priv);
  47 }
  48
  49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
  50 {
  51         return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
  52 }
  53
  54 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
  55 {
  56         return INTEL_GEN(dev_priv) < 4;
  57 }
  58
  59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  60 {
  61         return INTEL_GEN(dev_priv) <= 3;
  62 }
  63
  64 /*
  65  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  66  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  67  * origin so the x and y offsets can actually fit the registers. As a
  68  * consequence, the fence doesn't really start exactly at the display plane
  69  * address we program because it starts at the real start of the buffer, so we
  70  * have to take this into consideration here.
  71  */
  72 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
  73 {
  74         return crtc->base.y - crtc->adjusted_y;
  75 }
  76
  77 /*
  78  * For SKL+, the plane source size used by the hardware is based on the value we
  79  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  80  * we wrote to PIPESRC.
  81  */
  82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  83                                             int *width, int *height)
  84 {
  85         if (width)
  86                 *width = cache->plane.src_w;
  87         if (height)
  88                 *height = cache->plane.src_h;
  89 }
  90
  91 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  92                                         struct intel_fbc_state_cache *cache)
  93 {
  94         int lines;
  95
  96         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  97         if (INTEL_GEN(dev_priv) == 7)
  98                 lines = min(lines, 2048);
  99         else if (INTEL_GEN(dev_priv) >= 8)
 100                 lines = min(lines, 2560);
 101
 102         /* Hardware needs the full buffer stride, not just the active area. */
 103         return lines * cache->fb.stride;
 104 }
 105
 106 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
 107 {
 108         u32 fbc_ctl;
 109
 110         /* Disable compression */
 111         fbc_ctl = I915_READ(FBC_CONTROL);
 112         if ((fbc_ctl & FBC_CTL_EN) == 0)
 113                 return;
 114
 115         fbc_ctl &= ~FBC_CTL_EN;
 116         I915_WRITE(FBC_CONTROL, fbc_ctl);
 117
 118         /* Wait for compressing bit to clear */
 119         if (intel_wait_for_register(dev_priv,
 120                                     FBC_STATUS, FBC_STAT_COMPRESSING, 0,
 121                                     10)) {
 122                 DRM_DEBUG_KMS("FBC idle timed out\n");
 123                 return;
 124         }
 125 }
 126
 127 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 128 {
 129         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 130         int cfb_pitch;
 131         int i;
 132         u32 fbc_ctl;
 133
 134         /* Note: fbc.threshold == 1 for i8xx */
 135         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 136         if (params->fb.stride < cfb_pitch)
 137                 cfb_pitch = params->fb.stride;
 138
 139         /* FBC_CTL wants 32B or 64B units */
 140         if (IS_GEN2(dev_priv))
 141                 cfb_pitch = (cfb_pitch / 32) - 1;
 142         else
 143                 cfb_pitch = (cfb_pitch / 64) - 1;
 144
 145         /* Clear old tags */
 146         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 147                 I915_WRITE(FBC_TAG(i), 0);
 148
 149         if (IS_GEN4(dev_priv)) {
 150                 u32 fbc_ctl2;
 151
 152                 /* Set it up... */
 153                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 154                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
 155                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 156                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 157         }
 158
 159         /* enable it... */
 160         fbc_ctl = I915_READ(FBC_CONTROL);
 161         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 162         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 163         if (IS_I945GM(dev_priv))
 164                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 165         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 166         fbc_ctl |= params->vma->fence->id;
 167         I915_WRITE(FBC_CONTROL, fbc_ctl);
 168 }
 169
 170 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 171 {
 172         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 173 }
 174
 175 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 176 {
 177         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 178         u32 dpfc_ctl;
 179
 180         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
 181         if (params->fb.format->cpp[0] == 2)
 182                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 183         else
 184                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 185
 186         if (params->vma->fence) {
 187                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
 188                 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 189         } else {
 190                 I915_WRITE(DPFC_FENCE_YOFF, 0);
 191         }
 192
 193         /* enable it... */
 194         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 195 }
 196
 197 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 198 {
 199         u32 dpfc_ctl;
 200
 201         /* Disable compression */
 202         dpfc_ctl = I915_READ(DPFC_CONTROL);
 203         if (dpfc_ctl & DPFC_CTL_EN) {
 204                 dpfc_ctl &= ~DPFC_CTL_EN;
 205                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 206         }
 207 }
 208
 209 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 210 {
 211         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 212 }
 213
 214 /* This function forces a CFB recompression through the nuke operation. */
 215 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 216 {
 217         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 218         POSTING_READ(MSG_FBC_REND_STATE);
 219 }
 220
 221 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 222 {
 223         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 224         u32 dpfc_ctl;
 225         int threshold = dev_priv->fbc.threshold;
 226
 227         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
 228         if (params->fb.format->cpp[0] == 2)
 229                 threshold++;
 230
 231         switch (threshold) {
 232         case 4:
 233         case 3:
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 235                 break;
 236         case 2:
 237                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 238                 break;
 239         case 1:
 240                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 241                 break;
 242         }
 243
 244         if (params->vma->fence) {
 245                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 246                 if (IS_GEN5(dev_priv))
 247                         dpfc_ctl |= params->vma->fence->id;
 248                 if (IS_GEN6(dev_priv)) {
 249                         I915_WRITE(SNB_DPFC_CTL_SA,
 250                                    SNB_CPU_FENCE_ENABLE |
 251                                    params->vma->fence->id);
 252                         I915_WRITE(DPFC_CPU_FENCE_OFFSET,
 253                                    params->crtc.fence_y_offset);
 254                 }
 255         } else {
 256                 if (IS_GEN6(dev_priv)) {
 257                         I915_WRITE(SNB_DPFC_CTL_SA, 0);
 258                         I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 259                 }
 260         }
 261
 262         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 263         I915_WRITE(ILK_FBC_RT_BASE,
 264                    i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
 265         /* enable it... */
 266         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 267
 268         intel_fbc_recompress(dev_priv);
 269 }
 270
 271 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 272 {
 273         u32 dpfc_ctl;
 274
 275         /* Disable compression */
 276         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 277         if (dpfc_ctl & DPFC_CTL_EN) {
 278                 dpfc_ctl &= ~DPFC_CTL_EN;
 279                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 280         }
 281 }
 282
 283 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 284 {
 285         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 286 }
 287
 288 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 289 {
 290         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 291         u32 dpfc_ctl;
 292         int threshold = dev_priv->fbc.threshold;
 293
 294         dpfc_ctl = 0;
 295         if (IS_IVYBRIDGE(dev_priv))
 296                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
 297
 298         if (params->fb.format->cpp[0] == 2)
 299                 threshold++;
 300
 301         switch (threshold) {
 302         case 4:
 303         case 3:
 304                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 305                 break;
 306         case 2:
 307                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 308                 break;
 309         case 1:
 310                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 311                 break;
 312         }
 313
 314         if (params->vma->fence) {
 315                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 316                 I915_WRITE(SNB_DPFC_CTL_SA,
 317                            SNB_CPU_FENCE_ENABLE |
 318                            params->vma->fence->id);
 319                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 320         } else {
 321                 I915_WRITE(SNB_DPFC_CTL_SA,0);
 322                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 323         }
 324
 325         if (dev_priv->fbc.false_color)
 326                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 327
 328         if (IS_IVYBRIDGE(dev_priv)) {
 329                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 330                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 331                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 332                            ILK_FBCQ_DIS);
 333         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 334                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 335                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 336                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 337                            HSW_FBCQ_DIS);
 338         }
 339
 340         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 341
 342         intel_fbc_recompress(dev_priv);
 343 }
 344
 345 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 346 {
 347         if (INTEL_GEN(dev_priv) >= 5)
 348                 return ilk_fbc_is_active(dev_priv);
 349         else if (IS_GM45(dev_priv))
 350                 return g4x_fbc_is_active(dev_priv);
 351         else
 352                 return i8xx_fbc_is_active(dev_priv);
 353 }
 354
 355 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 356 {
 357         struct intel_fbc *fbc = &dev_priv->fbc;
 358
 359         fbc->active = true;
 360
 361         if (INTEL_GEN(dev_priv) >= 7)
 362                 gen7_fbc_activate(dev_priv);
 363         else if (INTEL_GEN(dev_priv) >= 5)
 364                 ilk_fbc_activate(dev_priv);
 365         else if (IS_GM45(dev_priv))
 366                 g4x_fbc_activate(dev_priv);
 367         else
 368                 i8xx_fbc_activate(dev_priv);
 369 }
 370
 371 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 372 {
 373         struct intel_fbc *fbc = &dev_priv->fbc;
 374
 375         fbc->active = false;
 376
 377         if (INTEL_GEN(dev_priv) >= 5)
 378                 ilk_fbc_deactivate(dev_priv);
 379         else if (IS_GM45(dev_priv))
 380                 g4x_fbc_deactivate(dev_priv);
 381         else
 382                 i8xx_fbc_deactivate(dev_priv);
 383 }
 384
 385 /**
 386  * intel_fbc_is_active - Is FBC active?
 387  * @dev_priv: i915 device instance
 388  *
 389  * This function is used to verify the current state of FBC.
 390  *
 391  * FIXME: This should be tracked in the plane config eventually
 392  * instead of queried at runtime for most callers.
 393  */
 394 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 395 {
 396         return dev_priv->fbc.active;
 397 }
 398
 399 static void intel_fbc_work_fn(struct work_struct *__work)
 400 {
 401         struct drm_i915_private *dev_priv =
 402                 container_of(__work, struct drm_i915_private, fbc.work.work);
 403         struct intel_fbc *fbc = &dev_priv->fbc;
 404         struct intel_fbc_work *work = &fbc->work;
 405         struct intel_crtc *crtc = fbc->crtc;
 406         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
 407
 408         if (drm_crtc_vblank_get(&crtc->base)) {
 409                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 410                           pipe_name(crtc->pipe));
 411
 412                 mutex_lock(&fbc->lock);
 413                 work->scheduled = false;
 414                 mutex_unlock(&fbc->lock);
 415                 return;
 416         }
 417
 418 retry:
 419         /* Delay the actual enabling to let pageflipping cease and the
 420          * display to settle before starting the compression. Note that
 421          * this delay also serves a second purpose: it allows for a
 422          * vblank to pass after disabling the FBC before we attempt
 423          * to modify the control registers.
 424          *
 425          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 426          *
 427          * It is also worth mentioning that since work->scheduled_vblank can be
 428          * updated multiple times by the other threads, hitting the timeout is
 429          * not an error condition. We'll just end up hitting the "goto retry"
 430          * case below.
 431          */
 432         wait_event_timeout(vblank->queue,
 433                 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
 434                 msecs_to_jiffies(50));
 435
 436         mutex_lock(&fbc->lock);
 437
 438         /* Were we cancelled? */
 439         if (!work->scheduled)
 440                 goto out;
 441
 442         /* Were we delayed again while this function was sleeping? */
 443         if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
 444                 mutex_unlock(&fbc->lock);
 445                 goto retry;
 446         }
 447
 448         intel_fbc_hw_activate(dev_priv);
 449
 450         work->scheduled = false;
 451
 452 out:
 453         mutex_unlock(&fbc->lock);
 454         drm_crtc_vblank_put(&crtc->base);
 455 }
 456
 457 static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
 458 {
 459         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 460         struct intel_fbc *fbc = &dev_priv->fbc;
 461         struct intel_fbc_work *work = &fbc->work;
 462
 463         WARN_ON(!mutex_is_locked(&fbc->lock));
 464         if (WARN_ON(!fbc->enabled))
 465                 return;
 466
 467         if (drm_crtc_vblank_get(&crtc->base)) {
 468                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 469                           pipe_name(crtc->pipe));
 470                 return;
 471         }
 472
 473         /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
 474          * this function since we're not releasing fbc.lock, so it won't have an
 475          * opportunity to grab it to discover that it was cancelled. So we just
 476          * update the expected jiffy count. */
 477         work->scheduled = true;
 478         work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
 479         drm_crtc_vblank_put(&crtc->base);
 480
 481         schedule_work(&work->work);
 482 }
 483
 484 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
 485 {
 486         struct intel_fbc *fbc = &dev_priv->fbc;
 487
 488         WARN_ON(!mutex_is_locked(&fbc->lock));
 489
 490         /* Calling cancel_work() here won't help due to the fact that the work
 491          * function grabs fbc->lock. Just set scheduled to false so the work
 492          * function can know it was cancelled. */
 493         fbc->work.scheduled = false;
 494
 495         if (fbc->active)
 496                 intel_fbc_hw_deactivate(dev_priv);
 497 }
 498
 499 static bool multiple_pipes_ok(struct intel_crtc *crtc,
 500                               struct intel_plane_state *plane_state)
 501 {
 502         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 503         struct intel_fbc *fbc = &dev_priv->fbc;
 504         enum pipe pipe = crtc->pipe;
 505
 506         /* Don't even bother tracking anything we don't need. */
 507         if (!no_fbc_on_multiple_pipes(dev_priv))
 508                 return true;
 509
 510         if (plane_state->base.visible)
 511                 fbc->visible_pipes_mask |= (1 << pipe);
 512         else
 513                 fbc->visible_pipes_mask &= ~(1 << pipe);
 514
 515         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 516 }
 517
 518 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 519                                       struct drm_mm_node *node,
 520                                       int size,
 521                                       int fb_cpp)
 522 {
 523         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 524         int compression_threshold = 1;
 525         int ret;
 526         u64 end;
 527
 528         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 529          * reserved range size, so it always assumes the maximum (8mb) is used.
 530          * If we enable FBC using a CFB on that memory range we'll get FIFO
 531          * underruns, even if that range is not reserved by the BIOS. */
 532         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 533                 end = ggtt->stolen_size - 8 * 1024 * 1024;
 534         else
 535                 end = U64_MAX;
 536
 537         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 538          * code changes, this code needs to change as well.
 539          *
 540          * The enable_fbc code will attempt to use one of our 2 compression
 541          * thresholds, therefore, in that case, we only have 1 resort.
 542          */
 543
 544         /* Try to over-allocate to reduce reallocations and fragmentation. */
 545         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 546                                                    4096, 0, end);
 547         if (ret == 0)
 548                 return compression_threshold;
 549
 550 again:
 551         /* HW's ability to limit the CFB is 1:4 */
 552         if (compression_threshold > 4 ||
 553             (fb_cpp == 2 && compression_threshold == 2))
 554                 return 0;
 555
 556         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 557                                                    4096, 0, end);
 558         if (ret && INTEL_GEN(dev_priv) <= 4) {
 559                 return 0;
 560         } else if (ret) {
 561                 compression_threshold <<= 1;
 562                 goto again;
 563         } else {
 564                 return compression_threshold;
 565         }
 566 }
 567
 568 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 569 {
 570         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 571         struct intel_fbc *fbc = &dev_priv->fbc;
 572         struct drm_mm_node *uninitialized_var(compressed_llb);
 573         int size, fb_cpp, ret;
 574
 575         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 576
 577         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 578         fb_cpp = fbc->state_cache.fb.format->cpp[0];
 579
 580         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 581                                          size, fb_cpp);
 582         if (!ret)
 583                 goto err_llb;
 584         else if (ret > 1) {
 585                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 586
 587         }
 588
 589         fbc->threshold = ret;
 590
 591         if (INTEL_GEN(dev_priv) >= 5)
 592                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 593         else if (IS_GM45(dev_priv)) {
 594                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 595         } else {
 596                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 597                 if (!compressed_llb)
 598                         goto err_fb;
 599
 600                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 601                                                   4096, 4096);
 602                 if (ret)
 603                         goto err_fb;
 604
 605                 fbc->compressed_llb = compressed_llb;
 606
 607                 I915_WRITE(FBC_CFB_BASE,
 608                            dev_priv->mm.stolen_base + fbc->compressed_fb.start);
 609                 I915_WRITE(FBC_LL_BASE,
 610                            dev_priv->mm.stolen_base + compressed_llb->start);
 611         }
 612
 613         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 614                       fbc->compressed_fb.size, fbc->threshold);
 615
 616         return 0;
 617
 618 err_fb:
 619         kfree(compressed_llb);
 620         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 621 err_llb:
 622         if (drm_mm_initialized(&dev_priv->mm.stolen))
 623                 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 624         return -ENOSPC;
 625 }
 626
 627 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 628 {
 629         struct intel_fbc *fbc = &dev_priv->fbc;
 630
 631         if (drm_mm_node_allocated(&fbc->compressed_fb))
 632                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 633
 634         if (fbc->compressed_llb) {
 635                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 636                 kfree(fbc->compressed_llb);
 637         }
 638 }
 639
 640 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 641 {
 642         struct intel_fbc *fbc = &dev_priv->fbc;
 643
 644         if (!fbc_supported(dev_priv))
 645                 return;
 646
 647         mutex_lock(&fbc->lock);
 648         __intel_fbc_cleanup_cfb(dev_priv);
 649         mutex_unlock(&fbc->lock);
 650 }
 651
 652 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 653                             unsigned int stride)
 654 {
 655         /* These should have been caught earlier. */
 656         WARN_ON(stride < 512);
 657         WARN_ON((stride & (64 - 1)) != 0);
 658
 659         /* Below are the additional FBC restrictions. */
 660
 661         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 662                 return stride == 4096 || stride == 8192;
 663
 664         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 665                 return false;
 666
 667         if (stride > 16384)
 668                 return false;
 669
 670         return true;
 671 }
 672
 673 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 674                                   uint32_t pixel_format)
 675 {
 676         switch (pixel_format) {
 677         case DRM_FORMAT_XRGB8888:
 678         case DRM_FORMAT_XBGR8888:
 679                 return true;
 680         case DRM_FORMAT_XRGB1555:
 681         case DRM_FORMAT_RGB565:
 682                 /* 16bpp not supported on gen2 */
 683                 if (IS_GEN2(dev_priv))
 684                         return false;
 685                 /* WaFbcOnly1to1Ratio:ctg */
 686                 if (IS_G4X(dev_priv))
 687                         return false;
 688                 return true;
 689         default:
 690                 return false;
 691         }
 692 }
 693
 694 /*
 695  * For some reason, the hardware tracking starts looking at whatever we
 696  * programmed as the display plane base address register. It does not look at
 697  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 698  * variables instead of just looking at the pipe/plane size.
 699  */
 700 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 701 {
 702         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 703         struct intel_fbc *fbc = &dev_priv->fbc;
 704         unsigned int effective_w, effective_h, max_w, max_h;
 705
 706         if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 707                 max_w = 4096;
 708                 max_h = 4096;
 709         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 710                 max_w = 4096;
 711                 max_h = 2048;
 712         } else {
 713                 max_w = 2048;
 714                 max_h = 1536;
 715         }
 716
 717         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 718                                         &effective_h);
 719         effective_w += crtc->adjusted_x;
 720         effective_h += crtc->adjusted_y;
 721
 722         return effective_w <= max_w && effective_h <= max_h;
 723 }
 724
 725 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 726                                          struct intel_crtc_state *crtc_state,
 727                                          struct intel_plane_state *plane_state)
 728 {
 729         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 730         struct intel_fbc *fbc = &dev_priv->fbc;
 731         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 732         struct drm_framebuffer *fb = plane_state->base.fb;
 733
 734         cache->vma = NULL;
 735
 736         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 737         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 738                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 739
 740         cache->plane.rotation = plane_state->base.rotation;
 741         /*
 742          * Src coordinates are already rotated by 270 degrees for
 743          * the 90/270 degree plane rotation cases (to match the
 744          * GTT mapping), hence no need to account for rotation here.
 745          */
 746         cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 747         cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 748         cache->plane.visible = plane_state->base.visible;
 749
 750         if (!cache->plane.visible)
 751                 return;
 752
 753         cache->fb.format = fb->format;
 754         cache->fb.stride = fb->pitches[0];
 755
 756         cache->vma = plane_state->vma;
 757 }
 758
 759 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 760 {
 761         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 762         struct intel_fbc *fbc = &dev_priv->fbc;
 763         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 764
 765         /* We don't need to use a state cache here since this information is
 766          * global for all CRTC.
 767          */
 768         if (fbc->underrun_detected) {
 769                 fbc->no_fbc_reason = "underrun detected";
 770                 return false;
 771         }
 772
 773         if (!cache->vma) {
 774                 fbc->no_fbc_reason = "primary plane not visible";
 775                 return false;
 776         }
 777
 778         if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
 779             (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
 780                 fbc->no_fbc_reason = "incompatible mode";
 781                 return false;
 782         }
 783
 784         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 785                 fbc->no_fbc_reason = "mode too large for compression";
 786                 return false;
 787         }
 788
 789         /* The use of a CPU fence is mandatory in order to detect writes
 790          * by the CPU to the scanout and trigger updates to the FBC.
 791          *
 792          * Note that is possible for a tiled surface to be unmappable (and
 793          * so have no fence associated with it) due to aperture constaints
 794          * at the time of pinning.
 795          */
 796         if (!cache->vma->fence) {
 797                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 798                 return false;
 799         }
 800         if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 801             cache->plane.rotation != DRM_MODE_ROTATE_0) {
 802                 fbc->no_fbc_reason = "rotation unsupported";
 803                 return false;
 804         }
 805
 806         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 807                 fbc->no_fbc_reason = "framebuffer stride not supported";
 808                 return false;
 809         }
 810
 811         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 812                 fbc->no_fbc_reason = "pixel format is invalid";
 813                 return false;
 814         }
 815
 816         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 817         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 818             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 819                 fbc->no_fbc_reason = "pixel rate is too big";
 820                 return false;
 821         }
 822
 823         /* It is possible for the required CFB size change without a
 824          * crtc->disable + crtc->enable since it is possible to change the
 825          * stride without triggering a full modeset. Since we try to
 826          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 827          * if this happens, but if we exceed the current CFB size we'll have to
 828          * disable FBC. Notice that it would be possible to disable FBC, wait
 829          * for a frame, free the stolen node, then try to reenable FBC in case
 830          * we didn't get any invalidate/deactivate calls, but this would require
 831          * a lot of tracking just for a specific case. If we conclude it's an
 832          * important case, we can implement it later. */
 833         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 834             fbc->compressed_fb.size * fbc->threshold) {
 835                 fbc->no_fbc_reason = "CFB requirements changed";
 836                 return false;
 837         }
 838
 839         return true;
 840 }
 841
 842 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 843 {
 844         struct intel_fbc *fbc = &dev_priv->fbc;
 845
 846         if (intel_vgpu_active(dev_priv)) {
 847                 fbc->no_fbc_reason = "VGPU is active";
 848                 return false;
 849         }
 850
 851         if (!i915.enable_fbc) {
 852                 fbc->no_fbc_reason = "disabled per module param or by default";
 853                 return false;
 854         }
 855
 856         if (fbc->underrun_detected) {
 857                 fbc->no_fbc_reason = "underrun detected";
 858                 return false;
 859         }
 860
 861         return true;
 862 }
 863
 864 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 865                                      struct intel_fbc_reg_params *params)
 866 {
 867         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 868         struct intel_fbc *fbc = &dev_priv->fbc;
 869         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 870
 871         /* Since all our fields are integer types, use memset here so the
 872          * comparison function can rely on memcmp because the padding will be
 873          * zero. */
 874         memset(params, 0, sizeof(*params));
 875
 876         params->vma = cache->vma;
 877
 878         params->crtc.pipe = crtc->pipe;
 879         params->crtc.plane = crtc->plane;
 880         params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
 881
 882         params->fb.format = cache->fb.format;
 883         params->fb.stride = cache->fb.stride;
 884
 885         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 886 }
 887
 888 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
 889                                        struct intel_fbc_reg_params *params2)
 890 {
 891         /* We can use this since intel_fbc_get_reg_params() does a memset. */
 892         return memcmp(params1, params2, sizeof(*params1)) == 0;
 893 }
 894
 895 void intel_fbc_pre_update(struct intel_crtc *crtc,
 896                           struct intel_crtc_state *crtc_state,
 897                           struct intel_plane_state *plane_state)
 898 {
 899         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 900         struct intel_fbc *fbc = &dev_priv->fbc;
 901
 902         if (!fbc_supported(dev_priv))
 903                 return;
 904
 905         mutex_lock(&fbc->lock);
 906
 907         if (!multiple_pipes_ok(crtc, plane_state)) {
 908                 fbc->no_fbc_reason = "more than one pipe active";
 909                 goto deactivate;
 910         }
 911
 912         if (!fbc->enabled || fbc->crtc != crtc)
 913                 goto unlock;
 914
 915         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 916
 917 deactivate:
 918         intel_fbc_deactivate(dev_priv);
 919 unlock:
 920         mutex_unlock(&fbc->lock);
 921 }
 922
 923 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 924 {
 925         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 926         struct intel_fbc *fbc = &dev_priv->fbc;
 927         struct intel_fbc_reg_params old_params;
 928
 929         WARN_ON(!mutex_is_locked(&fbc->lock));
 930
 931         if (!fbc->enabled || fbc->crtc != crtc)
 932                 return;
 933
 934         if (!intel_fbc_can_activate(crtc)) {
 935                 WARN_ON(fbc->active);
 936                 return;
 937         }
 938
 939         old_params = fbc->params;
 940         intel_fbc_get_reg_params(crtc, &fbc->params);
 941
 942         /* If the scanout has not changed, don't modify the FBC settings.
 943          * Note that we make the fundamental assumption that the fb->obj
 944          * cannot be unpinned (and have its GTT offset and fence revoked)
 945          * without first being decoupled from the scanout and FBC disabled.
 946          */
 947         if (fbc->active &&
 948             intel_fbc_reg_params_equal(&old_params, &fbc->params))
 949                 return;
 950
 951         intel_fbc_deactivate(dev_priv);
 952         intel_fbc_schedule_activation(crtc);
 953         fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
 954 }
 955
 956 void intel_fbc_post_update(struct intel_crtc *crtc)
 957 {
 958         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 959         struct intel_fbc *fbc = &dev_priv->fbc;
 960
 961         if (!fbc_supported(dev_priv))
 962                 return;
 963
 964         mutex_lock(&fbc->lock);
 965         __intel_fbc_post_update(crtc);
 966         mutex_unlock(&fbc->lock);
 967 }
 968
 969 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
 970 {
 971         if (fbc->enabled)
 972                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
 973         else
 974                 return fbc->possible_framebuffer_bits;
 975 }
 976
 977 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 978                           unsigned int frontbuffer_bits,
 979                           enum fb_op_origin origin)
 980 {
 981         struct intel_fbc *fbc = &dev_priv->fbc;
 982
 983         if (!fbc_supported(dev_priv))
 984                 return;
 985
 986         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 987                 return;
 988
 989         mutex_lock(&fbc->lock);
 990
 991         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
 992
 993         if (fbc->enabled && fbc->busy_bits)
 994                 intel_fbc_deactivate(dev_priv);
 995
 996         mutex_unlock(&fbc->lock);
 997 }
 998
 999 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1000                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1001 {
1002         struct intel_fbc *fbc = &dev_priv->fbc;
1003
1004         if (!fbc_supported(dev_priv))
1005                 return;
1006
1007         mutex_lock(&fbc->lock);
1008
1009         fbc->busy_bits &= ~frontbuffer_bits;
1010
1011         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1012                 goto out;
1013
1014         if (!fbc->busy_bits && fbc->enabled &&
1015             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1016                 if (fbc->active)
1017                         intel_fbc_recompress(dev_priv);
1018                 else
1019                         __intel_fbc_post_update(fbc->crtc);
1020         }
1021
1022 out:
1023         mutex_unlock(&fbc->lock);
1024 }
1025
1026 /**
1027  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1028  * @dev_priv: i915 device instance
1029  * @state: the atomic state structure
1030  *
1031  * This function looks at the proposed state for CRTCs and planes, then chooses
1032  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1033  * true.
1034  *
1035  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1036  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1037  */
1038 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1039                            struct drm_atomic_state *state)
1040 {
1041         struct intel_fbc *fbc = &dev_priv->fbc;
1042         struct drm_plane *plane;
1043         struct drm_plane_state *plane_state;
1044         bool crtc_chosen = false;
1045         int i;
1046
1047         mutex_lock(&fbc->lock);
1048
1049         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1050         if (fbc->crtc &&
1051             !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base))
1052                 goto out;
1053
1054         if (!intel_fbc_can_enable(dev_priv))
1055                 goto out;
1056
1057         /* Simply choose the first CRTC that is compatible and has a visible
1058          * plane. We could go for fancier schemes such as checking the plane
1059          * size, but this would just affect the few platforms that don't tie FBC
1060          * to pipe or plane A. */
1061         for_each_new_plane_in_state(state, plane, plane_state, i) {
1062                 struct intel_plane_state *intel_plane_state =
1063                         to_intel_plane_state(plane_state);
1064                 struct intel_crtc_state *intel_crtc_state;
1065                 struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc);
1066
1067                 if (!intel_plane_state->base.visible)
1068                         continue;
1069
1070                 if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
1071                         continue;
1072
1073                 if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
1074                         continue;
1075
1076                 intel_crtc_state = to_intel_crtc_state(
1077                         drm_atomic_get_existing_crtc_state(state, &crtc->base));
1078
1079                 intel_crtc_state->enable_fbc = true;
1080                 crtc_chosen = true;
1081                 break;
1082         }
1083
1084         if (!crtc_chosen)
1085                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1086
1087 out:
1088         mutex_unlock(&fbc->lock);
1089 }
1090
1091 /**
1092  * intel_fbc_enable: tries to enable FBC on the CRTC
1093  * @crtc: the CRTC
1094  * @crtc_state: corresponding &drm_crtc_state for @crtc
1095  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1096  *
1097  * This function checks if the given CRTC was chosen for FBC, then enables it if
1098  * possible. Notice that it doesn't activate FBC. It is valid to call
1099  * intel_fbc_enable multiple times for the same pipe without an
1100  * intel_fbc_disable in the middle, as long as it is deactivated.
1101  */
1102 void intel_fbc_enable(struct intel_crtc *crtc,
1103                       struct intel_crtc_state *crtc_state,
1104                       struct intel_plane_state *plane_state)
1105 {
1106         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1107         struct intel_fbc *fbc = &dev_priv->fbc;
1108
1109         if (!fbc_supported(dev_priv))
1110                 return;
1111
1112         mutex_lock(&fbc->lock);
1113
1114         if (fbc->enabled) {
1115                 WARN_ON(fbc->crtc == NULL);
1116                 if (fbc->crtc == crtc) {
1117                         WARN_ON(!crtc_state->enable_fbc);
1118                         WARN_ON(fbc->active);
1119                 }
1120                 goto out;
1121         }
1122
1123         if (!crtc_state->enable_fbc)
1124                 goto out;
1125
1126         WARN_ON(fbc->active);
1127         WARN_ON(fbc->crtc != NULL);
1128
1129         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1130         if (intel_fbc_alloc_cfb(crtc)) {
1131                 fbc->no_fbc_reason = "not enough stolen memory";
1132                 goto out;
1133         }
1134
1135         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1136         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1137
1138         fbc->enabled = true;
1139         fbc->crtc = crtc;
1140 out:
1141         mutex_unlock(&fbc->lock);
1142 }
1143
1144 /**
1145  * __intel_fbc_disable - disable FBC
1146  * @dev_priv: i915 device instance
1147  *
1148  * This is the low level function that actually disables FBC. Callers should
1149  * grab the FBC lock.
1150  */
1151 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1152 {
1153         struct intel_fbc *fbc = &dev_priv->fbc;
1154         struct intel_crtc *crtc = fbc->crtc;
1155
1156         WARN_ON(!mutex_is_locked(&fbc->lock));
1157         WARN_ON(!fbc->enabled);
1158         WARN_ON(fbc->active);
1159         WARN_ON(crtc->active);
1160
1161         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1162
1163         __intel_fbc_cleanup_cfb(dev_priv);
1164
1165         fbc->enabled = false;
1166         fbc->crtc = NULL;
1167 }
1168
1169 /**
1170  * intel_fbc_disable - disable FBC if it's associated with crtc
1171  * @crtc: the CRTC
1172  *
1173  * This function disables FBC if it's associated with the provided CRTC.
1174  */
1175 void intel_fbc_disable(struct intel_crtc *crtc)
1176 {
1177         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1178         struct intel_fbc *fbc = &dev_priv->fbc;
1179
1180         if (!fbc_supported(dev_priv))
1181                 return;
1182
1183         mutex_lock(&fbc->lock);
1184         if (fbc->crtc == crtc)
1185                 __intel_fbc_disable(dev_priv);
1186         mutex_unlock(&fbc->lock);
1187
1188         cancel_work_sync(&fbc->work.work);
1189 }
1190
1191 /**
1192  * intel_fbc_global_disable - globally disable FBC
1193  * @dev_priv: i915 device instance
1194  *
1195  * This function disables FBC regardless of which CRTC is associated with it.
1196  */
1197 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1198 {
1199         struct intel_fbc *fbc = &dev_priv->fbc;
1200
1201         if (!fbc_supported(dev_priv))
1202                 return;
1203
1204         mutex_lock(&fbc->lock);
1205         if (fbc->enabled)
1206                 __intel_fbc_disable(dev_priv);
1207         mutex_unlock(&fbc->lock);
1208
1209         cancel_work_sync(&fbc->work.work);
1210 }
1211
1212 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1213 {
1214         struct drm_i915_private *dev_priv =
1215                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1216         struct intel_fbc *fbc = &dev_priv->fbc;
1217
1218         mutex_lock(&fbc->lock);
1219
1220         /* Maybe we were scheduled twice. */
1221         if (fbc->underrun_detected || !fbc->enabled)
1222                 goto out;
1223
1224         DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1225         fbc->underrun_detected = true;
1226
1227         intel_fbc_deactivate(dev_priv);
1228 out:
1229         mutex_unlock(&fbc->lock);
1230 }
1231
1232 /**
1233  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1234  * @dev_priv: i915 device instance
1235  *
1236  * Without FBC, most underruns are harmless and don't really cause too many
1237  * problems, except for an annoying message on dmesg. With FBC, underruns can
1238  * become black screens or even worse, especially when paired with bad
1239  * watermarks. So in order for us to be on the safe side, completely disable FBC
1240  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1241  * already suggests that watermarks may be bad, so try to be as safe as
1242  * possible.
1243  *
1244  * This function is called from the IRQ handler.
1245  */
1246 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1247 {
1248         struct intel_fbc *fbc = &dev_priv->fbc;
1249
1250         if (!fbc_supported(dev_priv))
1251                 return;
1252
1253         /* There's no guarantee that underrun_detected won't be set to true
1254          * right after this check and before the work is scheduled, but that's
1255          * not a problem since we'll check it again under the work function
1256          * while FBC is locked. This check here is just to prevent us from
1257          * unnecessarily scheduling the work, and it relies on the fact that we
1258          * never switch underrun_detect back to false after it's true. */
1259         if (READ_ONCE(fbc->underrun_detected))
1260                 return;
1261
1262         schedule_work(&fbc->underrun_work);
1263 }
1264
1265 /**
1266  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1267  * @dev_priv: i915 device instance
1268  *
1269  * The FBC code needs to track CRTC visibility since the older platforms can't
1270  * have FBC enabled while multiple pipes are used. This function does the
1271  * initial setup at driver load to make sure FBC is matching the real hardware.
1272  */
1273 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1274 {
1275         struct intel_crtc *crtc;
1276
1277         /* Don't even bother tracking anything if we don't need. */
1278         if (!no_fbc_on_multiple_pipes(dev_priv))
1279                 return;
1280
1281         for_each_intel_crtc(&dev_priv->drm, crtc)
1282                 if (intel_crtc_active(crtc) &&
1283                     crtc->base.primary->state->visible)
1284                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1285 }
1286
1287 /*
1288  * The DDX driver changes its behavior depending on the value it reads from
1289  * i915.enable_fbc, so sanitize it by translating the default value into either
1290  * 0 or 1 in order to allow it to know what's going on.
1291  *
1292  * Notice that this is done at driver initialization and we still allow user
1293  * space to change the value during runtime without sanitizing it again. IGT
1294  * relies on being able to change i915.enable_fbc at runtime.
1295  */
1296 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1297 {
1298         if (i915.enable_fbc >= 0)
1299                 return !!i915.enable_fbc;
1300
1301         if (!HAS_FBC(dev_priv))
1302                 return 0;
1303
1304         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1305                 return 1;
1306
1307         return 0;
1308 }
1309
1310 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1311 {
1312         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1313         if (intel_vtd_active() &&
1314             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1315                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1316                 return true;
1317         }
1318
1319         return false;
1320 }
1321
1322 /**
1323  * intel_fbc_init - Initialize FBC
1324  * @dev_priv: the i915 device
1325  *
1326  * This function might be called during PM init process.
1327  */
1328 void intel_fbc_init(struct drm_i915_private *dev_priv)
1329 {
1330         struct intel_fbc *fbc = &dev_priv->fbc;
1331         enum pipe pipe;
1332
1333         INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
1334         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1335         mutex_init(&fbc->lock);
1336         fbc->enabled = false;
1337         fbc->active = false;
1338         fbc->work.scheduled = false;
1339
1340         if (need_fbc_vtd_wa(dev_priv))
1341                 mkwrite_device_info(dev_priv)->has_fbc = false;
1342
1343         i915.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1344         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);
1345
1346         if (!HAS_FBC(dev_priv)) {
1347                 fbc->no_fbc_reason = "unsupported by this chipset";
1348                 return;
1349         }
1350
1351         for_each_pipe(dev_priv, pipe) {
1352                 fbc->possible_framebuffer_bits |=
1353                                 INTEL_FRONTBUFFER_PRIMARY(pipe);
1354
1355                 if (fbc_on_pipe_a_only(dev_priv))
1356                         break;
1357         }
1358
1359         /* This value was pulled out of someone's hat */
1360         if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1361                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1362
1363         /* We still don't have any sort of hardware state readout for FBC, so
1364          * deactivate it in case the BIOS activated it to make sure software
1365          * matches the hardware state. */
1366         if (intel_fbc_hw_is_active(dev_priv))
1367                 intel_fbc_hw_deactivate(dev_priv);
1368 }