drivers/gpu/drm/i915/intel_engine_cs.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "i915_drv.h"
  26 #include "intel_ringbuffer.h"
  27 #include "intel_lrc.h"
  28
  29 static const struct engine_info {
  30         const char *name;
  31         unsigned exec_id;
  32         enum intel_engine_hw_id hw_id;
  33         u32 mmio_base;
  34         unsigned irq_shift;
  35         int (*init_legacy)(struct intel_engine_cs *engine);
  36         int (*init_execlists)(struct intel_engine_cs *engine);
  37 } intel_engines[] = {
  38         [RCS] = {
  39                 .name = "render ring",
  40                 .exec_id = I915_EXEC_RENDER,
  41                 .hw_id = RCS_HW,
  42                 .mmio_base = RENDER_RING_BASE,
  43                 .irq_shift = GEN8_RCS_IRQ_SHIFT,
  44                 .init_execlists = logical_render_ring_init,
  45                 .init_legacy = intel_init_render_ring_buffer,
  46         },
  47         [BCS] = {
  48                 .name = "blitter ring",
  49                 .exec_id = I915_EXEC_BLT,
  50                 .hw_id = BCS_HW,
  51                 .mmio_base = BLT_RING_BASE,
  52                 .irq_shift = GEN8_BCS_IRQ_SHIFT,
  53                 .init_execlists = logical_xcs_ring_init,
  54                 .init_legacy = intel_init_blt_ring_buffer,
  55         },
  56         [VCS] = {
  57                 .name = "bsd ring",
  58                 .exec_id = I915_EXEC_BSD,
  59                 .hw_id = VCS_HW,
  60                 .mmio_base = GEN6_BSD_RING_BASE,
  61                 .irq_shift = GEN8_VCS1_IRQ_SHIFT,
  62                 .init_execlists = logical_xcs_ring_init,
  63                 .init_legacy = intel_init_bsd_ring_buffer,
  64         },
  65         [VCS2] = {
  66                 .name = "bsd2 ring",
  67                 .exec_id = I915_EXEC_BSD,
  68                 .hw_id = VCS2_HW,
  69                 .mmio_base = GEN8_BSD2_RING_BASE,
  70                 .irq_shift = GEN8_VCS2_IRQ_SHIFT,
  71                 .init_execlists = logical_xcs_ring_init,
  72                 .init_legacy = intel_init_bsd2_ring_buffer,
  73         },
  74         [VECS] = {
  75                 .name = "video enhancement ring",
  76                 .exec_id = I915_EXEC_VEBOX,
  77                 .hw_id = VECS_HW,
  78                 .mmio_base = VEBOX_RING_BASE,
  79                 .irq_shift = GEN8_VECS_IRQ_SHIFT,
  80                 .init_execlists = logical_xcs_ring_init,
  81                 .init_legacy = intel_init_vebox_ring_buffer,
  82         },
  83 };
  84
  85 static int
  86 intel_engine_setup(struct drm_i915_private *dev_priv,
  87                    enum intel_engine_id id)
  88 {
  89         const struct engine_info *info = &intel_engines[id];
  90         struct intel_engine_cs *engine;
  91
  92         GEM_BUG_ON(dev_priv->engine[id]);
  93         engine = kzalloc(sizeof(*engine), GFP_KERNEL);
  94         if (!engine)
  95                 return -ENOMEM;
  96
  97         engine->id = id;
  98         engine->i915 = dev_priv;
  99         engine->name = info->name;
 100         engine->exec_id = info->exec_id;
 101         engine->hw_id = engine->guc_id = info->hw_id;
 102         engine->mmio_base = info->mmio_base;
 103         engine->irq_shift = info->irq_shift;
 104
 105         /* Nothing to do here, execute in order of dependencies */
 106         engine->schedule = NULL;
 107
 108         ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
 109
 110         dev_priv->engine[id] = engine;
 111         return 0;
 112 }
 113
 114 /**
 115  * intel_engines_init() - allocate, populate and init the Engine Command Streamers
 116  * @dev_priv: i915 device private
 117  *
 118  * Return: non-zero if the initialization failed.
 119  */
 120 int intel_engines_init(struct drm_i915_private *dev_priv)
 121 {
 122         struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
 123         unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
 124         unsigned int mask = 0;
 125         int (*init)(struct intel_engine_cs *engine);
 126         struct intel_engine_cs *engine;
 127         enum intel_engine_id id;
 128         unsigned int i;
 129         int ret;
 130
 131         WARN_ON(ring_mask == 0);
 132         WARN_ON(ring_mask &
 133                 GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
 134
 135         for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
 136                 if (!HAS_ENGINE(dev_priv, i))
 137                         continue;
 138
 139                 if (i915.enable_execlists)
 140                         init = intel_engines[i].init_execlists;
 141                 else
 142                         init = intel_engines[i].init_legacy;
 143
 144                 if (!init)
 145                         continue;
 146
 147                 ret = intel_engine_setup(dev_priv, i);
 148                 if (ret)
 149                         goto cleanup;
 150
 151                 ret = init(dev_priv->engine[i]);
 152                 if (ret)
 153                         goto cleanup;
 154
 155                 mask |= ENGINE_MASK(i);
 156         }
 157
 158         /*
 159          * Catch failures to update intel_engines table when the new engines
 160          * are added to the driver by a warning and disabling the forgotten
 161          * engines.
 162          */
 163         if (WARN_ON(mask != ring_mask))
 164                 device_info->ring_mask = mask;
 165
 166         device_info->num_rings = hweight32(mask);
 167
 168         return 0;
 169
 170 cleanup:
 171         for_each_engine(engine, dev_priv, id) {
 172                 if (i915.enable_execlists)
 173                         intel_logical_ring_cleanup(engine);
 174                 else
 175                         intel_engine_cleanup(engine);
 176         }
 177
 178         return ret;
 179 }
 180
 181 void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
 182 {
 183         struct drm_i915_private *dev_priv = engine->i915;
 184
 185         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
 186          * so long as the semaphore value in the register/page is greater
 187          * than the sync value), so whenever we reset the seqno,
 188          * so long as we reset the tracking semaphore value to 0, it will
 189          * always be before the next request's seqno. If we don't reset
 190          * the semaphore value, then when the seqno moves backwards all
 191          * future waits will complete instantly (causing rendering corruption).
 192          */
 193         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
 194                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
 195                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
 196                 if (HAS_VEBOX(dev_priv))
 197                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
 198         }
 199         if (dev_priv->semaphore) {
 200                 struct page *page = i915_vma_first_page(dev_priv->semaphore);
 201                 void *semaphores;
 202
 203                 /* Semaphores are in noncoherent memory, flush to be safe */
 204                 semaphores = kmap(page);
 205                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
 206                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
 207                 drm_clflush_virt_range(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
 208                                        I915_NUM_ENGINES * gen8_semaphore_seqno_size);
 209                 kunmap(page);
 210         }
 211
 212         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
 213         if (engine->irq_seqno_barrier)
 214                 engine->irq_seqno_barrier(engine);
 215
 216         GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request));
 217         engine->timeline->last_submitted_seqno = seqno;
 218
 219         engine->hangcheck.seqno = seqno;
 220
 221         /* After manually advancing the seqno, fake the interrupt in case
 222          * there are any waiters for that seqno.
 223          */
 224         intel_engine_wakeup(engine);
 225 }
 226
 227 static void intel_engine_init_timeline(struct intel_engine_cs *engine)
 228 {
 229         engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
 230 }
 231
 232 /**
 233  * intel_engines_setup_common - setup engine state not requiring hw access
 234  * @engine: Engine to setup.
 235  *
 236  * Initializes @engine@ structure members shared between legacy and execlists
 237  * submission modes which do not require hardware access.
 238  *
 239  * Typically done early in the submission mode specific engine setup stage.
 240  */
 241 void intel_engine_setup_common(struct intel_engine_cs *engine)
 242 {
 243         engine->execlist_queue = RB_ROOT;
 244         engine->execlist_first = NULL;
 245
 246         intel_engine_init_timeline(engine);
 247         intel_engine_init_hangcheck(engine);
 248         i915_gem_batch_pool_init(engine, &engine->batch_pool);
 249
 250         intel_engine_init_cmd_parser(engine);
 251 }
 252
 253 int intel_engine_create_scratch(struct intel_engine_cs *engine, int size)
 254 {
 255         struct drm_i915_gem_object *obj;
 256         struct i915_vma *vma;
 257         int ret;
 258
 259         WARN_ON(engine->scratch);
 260
 261         obj = i915_gem_object_create_stolen(engine->i915, size);
 262         if (!obj)
 263                 obj = i915_gem_object_create_internal(engine->i915, size);
 264         if (IS_ERR(obj)) {
 265                 DRM_ERROR("Failed to allocate scratch page\n");
 266                 return PTR_ERR(obj);
 267         }
 268
 269         vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
 270         if (IS_ERR(vma)) {
 271                 ret = PTR_ERR(vma);
 272                 goto err_unref;
 273         }
 274
 275         ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH);
 276         if (ret)
 277                 goto err_unref;
 278
 279         engine->scratch = vma;
 280         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 281                          engine->name, i915_ggtt_offset(vma));
 282         return 0;
 283
 284 err_unref:
 285         i915_gem_object_put(obj);
 286         return ret;
 287 }
 288
 289 static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
 290 {
 291         i915_vma_unpin_and_release(&engine->scratch);
 292 }
 293
 294 /**
 295  * intel_engines_init_common - initialize cengine state which might require hw access
 296  * @engine: Engine to initialize.
 297  *
 298  * Initializes @engine@ structure members shared between legacy and execlists
 299  * submission modes which do require hardware access.
 300  *
 301  * Typcally done at later stages of submission mode specific engine setup.
 302  *
 303  * Returns zero on success or an error code on failure.
 304  */
 305 int intel_engine_init_common(struct intel_engine_cs *engine)
 306 {
 307         int ret;
 308
 309         /* We may need to do things with the shrinker which
 310          * require us to immediately switch back to the default
 311          * context. This can cause a problem as pinning the
 312          * default context also requires GTT space which may not
 313          * be available. To avoid this we always pin the default
 314          * context.
 315          */
 316         ret = engine->context_pin(engine, engine->i915->kernel_context);
 317         if (ret)
 318                 return ret;
 319
 320         ret = intel_engine_init_breadcrumbs(engine);
 321         if (ret)
 322                 goto err_unpin;
 323
 324         ret = i915_gem_render_state_init(engine);
 325         if (ret)
 326                 goto err_unpin;
 327
 328         return 0;
 329
 330 err_unpin:
 331         engine->context_unpin(engine, engine->i915->kernel_context);
 332         return ret;
 333 }
 334
 335 /**
 336  * intel_engines_cleanup_common - cleans up the engine state created by
 337  *                                the common initiailizers.
 338  * @engine: Engine to cleanup.
 339  *
 340  * This cleans up everything created by the common helpers.
 341  */
 342 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 343 {
 344         intel_engine_cleanup_scratch(engine);
 345
 346         i915_gem_render_state_fini(engine);
 347         intel_engine_fini_breadcrumbs(engine);
 348         intel_engine_cleanup_cmd_parser(engine);
 349         i915_gem_batch_pool_fini(&engine->batch_pool);
 350
 351         engine->context_unpin(engine, engine->i915->kernel_context);
 352 }
 353
 354 u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
 355 {
 356         struct drm_i915_private *dev_priv = engine->i915;
 357         u64 acthd;
 358
 359         if (INTEL_GEN(dev_priv) >= 8)
 360                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 361                                          RING_ACTHD_UDW(engine->mmio_base));
 362         else if (INTEL_GEN(dev_priv) >= 4)
 363                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 364         else
 365                 acthd = I915_READ(ACTHD);
 366
 367         return acthd;
 368 }
 369
 370 u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine)
 371 {
 372         struct drm_i915_private *dev_priv = engine->i915;
 373         u64 bbaddr;
 374
 375         if (INTEL_GEN(dev_priv) >= 8)
 376                 bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
 377                                           RING_BBADDR_UDW(engine->mmio_base));
 378         else
 379                 bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
 380
 381         return bbaddr;
 382 }
 383
 384 const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
 385 {
 386         switch (type) {
 387         case I915_CACHE_NONE: return " uncached";
 388         case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
 389         case I915_CACHE_L3_LLC: return " L3+LLC";
 390         case I915_CACHE_WT: return " WT";
 391         default: return "";
 392         }
 393 }
 394
 395 static inline uint32_t
 396 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 397                   int subslice, i915_reg_t reg)
 398 {
 399         uint32_t mcr;
 400         uint32_t ret;
 401         enum forcewake_domains fw_domains;
 402
 403         fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
 404                                                     FW_REG_READ);
 405         fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
 406                                                      GEN8_MCR_SELECTOR,
 407                                                      FW_REG_READ | FW_REG_WRITE);
 408
 409         spin_lock_irq(&dev_priv->uncore.lock);
 410         intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 411
 412         mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
 413         /*
 414          * The HW expects the slice and sublice selectors to be reset to 0
 415          * after reading out the registers.
 416          */
 417         WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
 418         mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
 419         mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
 420         I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 421
 422         ret = I915_READ_FW(reg);
 423
 424         mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
 425         I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 426
 427         intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
 428         spin_unlock_irq(&dev_priv->uncore.lock);
 429
 430         return ret;
 431 }
 432
 433 /* NB: please notice the memset */
 434 void intel_engine_get_instdone(struct intel_engine_cs *engine,
 435                                struct intel_instdone *instdone)
 436 {
 437         struct drm_i915_private *dev_priv = engine->i915;
 438         u32 mmio_base = engine->mmio_base;
 439         int slice;
 440         int subslice;
 441
 442         memset(instdone, 0, sizeof(*instdone));
 443
 444         switch (INTEL_GEN(dev_priv)) {
 445         default:
 446                 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
 447
 448                 if (engine->id != RCS)
 449                         break;
 450
 451                 instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
 452                 for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
 453                         instdone->sampler[slice][subslice] =
 454                                 read_subslice_reg(dev_priv, slice, subslice,
 455                                                   GEN7_SAMPLER_INSTDONE);
 456                         instdone->row[slice][subslice] =
 457                                 read_subslice_reg(dev_priv, slice, subslice,
 458                                                   GEN7_ROW_INSTDONE);
 459                 }
 460                 break;
 461         case 7:
 462                 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
 463
 464                 if (engine->id != RCS)
 465                         break;
 466
 467                 instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
 468                 instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);
 469                 instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);
 470
 471                 break;
 472         case 6:
 473         case 5:
 474         case 4:
 475                 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
 476
 477                 if (engine->id == RCS)
 478                         /* HACK: Using the wrong struct member */
 479                         instdone->slice_common = I915_READ(GEN4_INSTDONE1);
 480                 break;
 481         case 3:
 482         case 2:
 483                 instdone->instdone = I915_READ(GEN2_INSTDONE);
 484                 break;
 485         }
 486 }