drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_mipi_dsi.h>
  32 #include <linux/slab.h>
  33 #include <linux/gpio/consumer.h>
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36 #include "intel_dsi.h"
  37
  38 /* return pixels in terms of txbyteclkhs */
  39 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  40                        u16 burst_mode_ratio)
  41 {
  42         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  43                                          8 * 100), lane_count);
  44 }
  45
  46 /* return pixels equvalent to txbyteclkhs */
  47 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  48                         u16 burst_mode_ratio)
  49 {
  50         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  51                                                 (bpp * burst_mode_ratio));
  52 }
  53
  54 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  55 {
  56         /* It just so happens the VBT matches register contents. */
  57         switch (fmt) {
  58         case VID_MODE_FORMAT_RGB888:
  59                 return MIPI_DSI_FMT_RGB888;
  60         case VID_MODE_FORMAT_RGB666:
  61                 return MIPI_DSI_FMT_RGB666;
  62         case VID_MODE_FORMAT_RGB666_PACKED:
  63                 return MIPI_DSI_FMT_RGB666_PACKED;
  64         case VID_MODE_FORMAT_RGB565:
  65                 return MIPI_DSI_FMT_RGB565;
  66         default:
  67                 MISSING_CASE(fmt);
  68                 return MIPI_DSI_FMT_RGB666;
  69         }
  70 }
  71
  72 void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  73 {
  74         struct drm_encoder *encoder = &intel_dsi->base.base;
  75         struct drm_device *dev = encoder->dev;
  76         struct drm_i915_private *dev_priv = to_i915(dev);
  77         u32 mask;
  78
  79         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  80                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  81
  82         if (intel_wait_for_register(dev_priv,
  83                                     MIPI_GEN_FIFO_STAT(port), mask, mask,
  84                                     100))
  85                 DRM_ERROR("DPI FIFOs are not empty\n");
  86 }
  87
  88 static void write_data(struct drm_i915_private *dev_priv,
  89                        i915_reg_t reg,
  90                        const u8 *data, u32 len)
  91 {
  92         u32 i, j;
  93
  94         for (i = 0; i < len; i += 4) {
  95                 u32 val = 0;
  96
  97                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  98                         val |= *data++ << 8 * j;
  99
 100                 I915_WRITE(reg, val);
 101         }
 102 }
 103
 104 static void read_data(struct drm_i915_private *dev_priv,
 105                       i915_reg_t reg,
 106                       u8 *data, u32 len)
 107 {
 108         u32 i, j;
 109
 110         for (i = 0; i < len; i += 4) {
 111                 u32 val = I915_READ(reg);
 112
 113                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 114                         *data++ = val >> 8 * j;
 115         }
 116 }
 117
 118 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 119                                        const struct mipi_dsi_msg *msg)
 120 {
 121         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 122         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 123         struct drm_i915_private *dev_priv = to_i915(dev);
 124         enum port port = intel_dsi_host->port;
 125         struct mipi_dsi_packet packet;
 126         ssize_t ret;
 127         const u8 *header, *data;
 128         i915_reg_t data_reg, ctrl_reg;
 129         u32 data_mask, ctrl_mask;
 130
 131         ret = mipi_dsi_create_packet(&packet, msg);
 132         if (ret < 0)
 133                 return ret;
 134
 135         header = packet.header;
 136         data = packet.payload;
 137
 138         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 139                 data_reg = MIPI_LP_GEN_DATA(port);
 140                 data_mask = LP_DATA_FIFO_FULL;
 141                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 142                 ctrl_mask = LP_CTRL_FIFO_FULL;
 143         } else {
 144                 data_reg = MIPI_HS_GEN_DATA(port);
 145                 data_mask = HS_DATA_FIFO_FULL;
 146                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 147                 ctrl_mask = HS_CTRL_FIFO_FULL;
 148         }
 149
 150         /* note: this is never true for reads */
 151         if (packet.payload_length) {
 152                 if (intel_wait_for_register(dev_priv,
 153                                             MIPI_GEN_FIFO_STAT(port),
 154                                             data_mask, 0,
 155                                             50))
 156                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 157
 158                 write_data(dev_priv, data_reg, packet.payload,
 159                            packet.payload_length);
 160         }
 161
 162         if (msg->rx_len) {
 163                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 164         }
 165
 166         if (intel_wait_for_register(dev_priv,
 167                                     MIPI_GEN_FIFO_STAT(port),
 168                                     ctrl_mask, 0,
 169                                     50)) {
 170                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 171         }
 172
 173         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 174
 175         /* ->rx_len is set only for reads */
 176         if (msg->rx_len) {
 177                 data_mask = GEN_READ_DATA_AVAIL;
 178                 if (intel_wait_for_register(dev_priv,
 179                                             MIPI_INTR_STAT(port),
 180                                             data_mask, data_mask,
 181                                             50))
 182                         DRM_ERROR("Timeout waiting for read data.\n");
 183
 184                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 185         }
 186
 187         /* XXX: fix for reads and writes */
 188         return 4 + packet.payload_length;
 189 }
 190
 191 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 192                                  struct mipi_dsi_device *dsi)
 193 {
 194         return 0;
 195 }
 196
 197 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 198                                  struct mipi_dsi_device *dsi)
 199 {
 200         return 0;
 201 }
 202
 203 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 204         .attach = intel_dsi_host_attach,
 205         .detach = intel_dsi_host_detach,
 206         .transfer = intel_dsi_host_transfer,
 207 };
 208
 209 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 210                                                   enum port port)
 211 {
 212         struct intel_dsi_host *host;
 213         struct mipi_dsi_device *device;
 214
 215         host = kzalloc(sizeof(*host), GFP_KERNEL);
 216         if (!host)
 217                 return NULL;
 218
 219         host->base.ops = &intel_dsi_host_ops;
 220         host->intel_dsi = intel_dsi;
 221         host->port = port;
 222
 223         /*
 224          * We should call mipi_dsi_host_register(&host->base) here, but we don't
 225          * have a host->dev, and we don't have OF stuff either. So just use the
 226          * dsi framework as a library and hope for the best. Create the dsi
 227          * devices by ourselves here too. Need to be careful though, because we
 228          * don't initialize any of the driver model devices here.
 229          */
 230         device = kzalloc(sizeof(*device), GFP_KERNEL);
 231         if (!device) {
 232                 kfree(host);
 233                 return NULL;
 234         }
 235
 236         device->host = &host->base;
 237         host->device = device;
 238
 239         return host;
 240 }
 241
 242 /*
 243  * send a video mode command
 244  *
 245  * XXX: commands with data in MIPI_DPI_DATA?
 246  */
 247 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 248                         enum port port)
 249 {
 250         struct drm_encoder *encoder = &intel_dsi->base.base;
 251         struct drm_device *dev = encoder->dev;
 252         struct drm_i915_private *dev_priv = to_i915(dev);
 253         u32 mask;
 254
 255         /* XXX: pipe, hs */
 256         if (hs)
 257                 cmd &= ~DPI_LP_MODE;
 258         else
 259                 cmd |= DPI_LP_MODE;
 260
 261         /* clear bit */
 262         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 263
 264         /* XXX: old code skips write if control unchanged */
 265         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 266                 DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd);
 267
 268         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 269
 270         mask = SPL_PKT_SENT_INTERRUPT;
 271         if (intel_wait_for_register(dev_priv,
 272                                     MIPI_INTR_STAT(port), mask, mask,
 273                                     100))
 274                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 275
 276         return 0;
 277 }
 278
 279 static void band_gap_reset(struct drm_i915_private *dev_priv)
 280 {
 281         mutex_lock(&dev_priv->sb_lock);
 282
 283         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 284         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 285         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 286         udelay(150);
 287         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 288         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 289
 290         mutex_unlock(&dev_priv->sb_lock);
 291 }
 292
 293 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
 294 {
 295         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
 296 }
 297
 298 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
 299 {
 300         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
 301 }
 302
 303 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 304                                      struct intel_crtc_state *pipe_config,
 305                                      struct drm_connector_state *conn_state)
 306 {
 307         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 308         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 309                                                    base);
 310         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 311         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 312         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 313         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 314         int ret;
 315
 316         DRM_DEBUG_KMS("\n");
 317
 318         if (fixed_mode) {
 319                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 320
 321                 if (HAS_GMCH_DISPLAY(dev_priv))
 322                         intel_gmch_panel_fitting(crtc, pipe_config,
 323                                                  conn_state->scaling_mode);
 324                 else
 325                         intel_pch_panel_fitting(crtc, pipe_config,
 326                                                 conn_state->scaling_mode);
 327         }
 328
 329         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 330                 return false;
 331
 332         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 333         adjusted_mode->flags = 0;
 334
 335         if (IS_GEN9_LP(dev_priv)) {
 336                 /* Enable Frame time stamp based scanline reporting */
 337                 adjusted_mode->private_flags |=
 338                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
 339
 340                 /* Dual link goes to DSI transcoder A. */
 341                 if (intel_dsi->ports == BIT(PORT_C))
 342                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 343                 else
 344                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 345         }
 346
 347         ret = intel_compute_dsi_pll(encoder, pipe_config);
 348         if (ret)
 349                 return false;
 350
 351         pipe_config->clock_set = true;
 352
 353         return true;
 354 }
 355
 356 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 357 {
 358         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 359         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 360         enum port port;
 361         u32 tmp;
 362         bool cold_boot = false;
 363
 364         /* Set the MIPI mode
 365          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 366          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 367          */
 368         for_each_dsi_port(port, intel_dsi->ports) {
 369                 tmp = I915_READ(MIPI_CTRL(port));
 370                 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
 371         }
 372
 373         /* Put the IO into reset */
 374         tmp = I915_READ(MIPI_CTRL(PORT_A));
 375         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 376         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 377
 378         /* Program LP Wake */
 379         for_each_dsi_port(port, intel_dsi->ports) {
 380                 tmp = I915_READ(MIPI_CTRL(port));
 381                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
 382                         tmp &= ~GLK_LP_WAKE;
 383                 else
 384                         tmp |= GLK_LP_WAKE;
 385                 I915_WRITE(MIPI_CTRL(port), tmp);
 386         }
 387
 388         /* Wait for Pwr ACK */
 389         for_each_dsi_port(port, intel_dsi->ports) {
 390                 if (intel_wait_for_register(dev_priv,
 391                                 MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
 392                                 GLK_MIPIIO_PORT_POWERED, 20))
 393                         DRM_ERROR("MIPIO port is powergated\n");
 394         }
 395
 396         /* Check for cold boot scenario */
 397         for_each_dsi_port(port, intel_dsi->ports) {
 398                 cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &
 399                                                         DEVICE_READY);
 400         }
 401
 402         return cold_boot;
 403 }
 404
 405 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 406 {
 407         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 408         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 409         enum port port;
 410         u32 val;
 411
 412         /* Wait for MIPI PHY status bit to set */
 413         for_each_dsi_port(port, intel_dsi->ports) {
 414                 if (intel_wait_for_register(dev_priv,
 415                                 MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
 416                                 GLK_PHY_STATUS_PORT_READY, 20))
 417                         DRM_ERROR("PHY is not ON\n");
 418         }
 419
 420         /* Get IO out of reset */
 421         val = I915_READ(MIPI_CTRL(PORT_A));
 422         I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
 423
 424         /* Get IO out of Low power state*/
 425         for_each_dsi_port(port, intel_dsi->ports) {
 426                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 427                         val = I915_READ(MIPI_DEVICE_READY(port));
 428                         val &= ~ULPS_STATE_MASK;
 429                         val |= DEVICE_READY;
 430                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 431                         usleep_range(10, 15);
 432                 } else {
 433                         /* Enter ULPS */
 434                         val = I915_READ(MIPI_DEVICE_READY(port));
 435                         val &= ~ULPS_STATE_MASK;
 436                         val |= (ULPS_STATE_ENTER | DEVICE_READY);
 437                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 438
 439                         /* Wait for ULPS active */
 440                         if (intel_wait_for_register(dev_priv,
 441                                 MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
 442                                 DRM_ERROR("ULPS not active\n");
 443
 444                         /* Exit ULPS */
 445                         val = I915_READ(MIPI_DEVICE_READY(port));
 446                         val &= ~ULPS_STATE_MASK;
 447                         val |= (ULPS_STATE_EXIT | DEVICE_READY);
 448                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 449
 450                         /* Enter Normal Mode */
 451                         val = I915_READ(MIPI_DEVICE_READY(port));
 452                         val &= ~ULPS_STATE_MASK;
 453                         val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 454                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 455
 456                         val = I915_READ(MIPI_CTRL(port));
 457                         val &= ~GLK_LP_WAKE;
 458                         I915_WRITE(MIPI_CTRL(port), val);
 459                 }
 460         }
 461
 462         /* Wait for Stop state */
 463         for_each_dsi_port(port, intel_dsi->ports) {
 464                 if (intel_wait_for_register(dev_priv,
 465                                 MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
 466                                 GLK_DATA_LANE_STOP_STATE, 20))
 467                         DRM_ERROR("Date lane not in STOP state\n");
 468         }
 469
 470         /* Wait for AFE LATCH */
 471         for_each_dsi_port(port, intel_dsi->ports) {
 472                 if (intel_wait_for_register(dev_priv,
 473                                 BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
 474                                 AFE_LATCHOUT, 20))
 475                         DRM_ERROR("D-PHY not entering LP-11 state\n");
 476         }
 477 }
 478
 479 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 480 {
 481         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 482         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 483         enum port port;
 484         u32 val;
 485
 486         DRM_DEBUG_KMS("\n");
 487
 488         /* Enable MIPI PHY transparent latch */
 489         for_each_dsi_port(port, intel_dsi->ports) {
 490                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 491                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 492                 usleep_range(2000, 2500);
 493         }
 494
 495         /* Clear ULPS and set device ready */
 496         for_each_dsi_port(port, intel_dsi->ports) {
 497                 val = I915_READ(MIPI_DEVICE_READY(port));
 498                 val &= ~ULPS_STATE_MASK;
 499                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 500                 usleep_range(2000, 2500);
 501                 val |= DEVICE_READY;
 502                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 503         }
 504 }
 505
 506 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 507 {
 508         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 509         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 510         enum port port;
 511         u32 val;
 512
 513         DRM_DEBUG_KMS("\n");
 514
 515         mutex_lock(&dev_priv->sb_lock);
 516         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 517          * needed everytime after power gate */
 518         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 519         mutex_unlock(&dev_priv->sb_lock);
 520
 521         /* bandgap reset is needed after everytime we do power gate */
 522         band_gap_reset(dev_priv);
 523
 524         for_each_dsi_port(port, intel_dsi->ports) {
 525
 526                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 527                 usleep_range(2500, 3000);
 528
 529                 /* Enable MIPI PHY transparent latch
 530                  * Common bit for both MIPI Port A & MIPI Port C
 531                  * No similar bit in MIPI Port C reg
 532                  */
 533                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 534                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 535                 usleep_range(1000, 1500);
 536
 537                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 538                 usleep_range(2500, 3000);
 539
 540                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 541                 usleep_range(2500, 3000);
 542         }
 543 }
 544
 545 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 546 {
 547         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 548
 549         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 550                 vlv_dsi_device_ready(encoder);
 551         else if (IS_BROXTON(dev_priv))
 552                 bxt_dsi_device_ready(encoder);
 553         else if (IS_GEMINILAKE(dev_priv))
 554                 glk_dsi_device_ready(encoder);
 555 }
 556
 557 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 558 {
 559         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 560         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 561         enum port port;
 562         u32 val;
 563
 564         /* Enter ULPS */
 565         for_each_dsi_port(port, intel_dsi->ports) {
 566                 val = I915_READ(MIPI_DEVICE_READY(port));
 567                 val &= ~ULPS_STATE_MASK;
 568                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 569                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 570         }
 571
 572         /* Wait for MIPI PHY status bit to unset */
 573         for_each_dsi_port(port, intel_dsi->ports) {
 574                 if (intel_wait_for_register(dev_priv,
 575                                             MIPI_CTRL(port),
 576                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 577                         DRM_ERROR("PHY is not turning OFF\n");
 578         }
 579
 580         /* Wait for Pwr ACK bit to unset */
 581         for_each_dsi_port(port, intel_dsi->ports) {
 582                 if (intel_wait_for_register(dev_priv,
 583                                             MIPI_CTRL(port),
 584                                             GLK_MIPIIO_PORT_POWERED, 0, 20))
 585                         DRM_ERROR("MIPI IO Port is not powergated\n");
 586         }
 587 }
 588
 589 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 590 {
 591         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 592         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 593         enum port port;
 594         u32 tmp;
 595
 596         /* Put the IO into reset */
 597         tmp = I915_READ(MIPI_CTRL(PORT_A));
 598         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 599         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 600
 601         /* Wait for MIPI PHY status bit to unset */
 602         for_each_dsi_port(port, intel_dsi->ports) {
 603                 if (intel_wait_for_register(dev_priv,
 604                                             MIPI_CTRL(port),
 605                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 606                         DRM_ERROR("PHY is not turning OFF\n");
 607         }
 608
 609         /* Clear MIPI mode */
 610         for_each_dsi_port(port, intel_dsi->ports) {
 611                 tmp = I915_READ(MIPI_CTRL(port));
 612                 tmp &= ~GLK_MIPIIO_ENABLE;
 613                 I915_WRITE(MIPI_CTRL(port), tmp);
 614         }
 615 }
 616
 617 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 618 {
 619         glk_dsi_enter_low_power_mode(encoder);
 620         glk_dsi_disable_mipi_io(encoder);
 621 }
 622
 623 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 624 {
 625         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 626         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 627         enum port port;
 628
 629         DRM_DEBUG_KMS("\n");
 630         for_each_dsi_port(port, intel_dsi->ports) {
 631                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 632                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 633                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 634                 u32 val;
 635
 636                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 637                                                         ULPS_STATE_ENTER);
 638                 usleep_range(2000, 2500);
 639
 640                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 641                                                         ULPS_STATE_EXIT);
 642                 usleep_range(2000, 2500);
 643
 644                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 645                                                         ULPS_STATE_ENTER);
 646                 usleep_range(2000, 2500);
 647
 648                 /*
 649                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 650                  * Port A only. MIPI Port C has no similar bit for checking.
 651                  */
 652                 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
 653                     intel_wait_for_register(dev_priv,
 654                                             port_ctrl, AFE_LATCHOUT, 0,
 655                                             30))
 656                         DRM_ERROR("DSI LP not going Low\n");
 657
 658                 /* Disable MIPI PHY transparent latch */
 659                 val = I915_READ(port_ctrl);
 660                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 661                 usleep_range(1000, 1500);
 662
 663                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 664                 usleep_range(2000, 2500);
 665         }
 666 }
 667
 668 static void intel_dsi_port_enable(struct intel_encoder *encoder,
 669                                   const struct intel_crtc_state *crtc_state)
 670 {
 671         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 672         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 673         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 674         enum port port;
 675
 676         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 677                 u32 temp;
 678                 if (IS_GEN9_LP(dev_priv)) {
 679                         for_each_dsi_port(port, intel_dsi->ports) {
 680                                 temp = I915_READ(MIPI_CTRL(port));
 681                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 682                                         intel_dsi->pixel_overlap <<
 683                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 684                                 I915_WRITE(MIPI_CTRL(port), temp);
 685                         }
 686                 } else {
 687                         temp = I915_READ(VLV_CHICKEN_3);
 688                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 689                                         intel_dsi->pixel_overlap <<
 690                                         PIXEL_OVERLAP_CNT_SHIFT;
 691                         I915_WRITE(VLV_CHICKEN_3, temp);
 692                 }
 693         }
 694
 695         for_each_dsi_port(port, intel_dsi->ports) {
 696                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 697                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 698                 u32 temp;
 699
 700                 temp = I915_READ(port_ctrl);
 701
 702                 temp &= ~LANE_CONFIGURATION_MASK;
 703                 temp &= ~DUAL_LINK_MODE_MASK;
 704
 705                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 706                         temp |= (intel_dsi->dual_link - 1)
 707                                                 << DUAL_LINK_MODE_SHIFT;
 708                         if (IS_BROXTON(dev_priv))
 709                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 710                         else
 711                                 temp |= crtc->pipe ?
 712                                         LANE_CONFIGURATION_DUAL_LINK_B :
 713                                         LANE_CONFIGURATION_DUAL_LINK_A;
 714                 }
 715                 /* assert ip_tg_enable signal */
 716                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 717                 POSTING_READ(port_ctrl);
 718         }
 719 }
 720
 721 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 722 {
 723         struct drm_device *dev = encoder->base.dev;
 724         struct drm_i915_private *dev_priv = to_i915(dev);
 725         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 726         enum port port;
 727
 728         for_each_dsi_port(port, intel_dsi->ports) {
 729                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 730                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 731                 u32 temp;
 732
 733                 /* de-assert ip_tg_enable signal */
 734                 temp = I915_READ(port_ctrl);
 735                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 736                 POSTING_READ(port_ctrl);
 737         }
 738 }
 739
 740 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 741                               const struct intel_crtc_state *pipe_config);
 742 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 743
 744 static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
 745 {
 746         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 747
 748         /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
 749         if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
 750                 return;
 751
 752         msleep(msec);
 753 }
 754
 755 /*
 756  * Panel enable/disable sequences from the VBT spec.
 757  *
 758  * Note the spec has AssertReset / DeassertReset swapped from their
 759  * usual naming. We use the normal names to avoid confusion (so below
 760  * they are swapped compared to the spec).
 761  *
 762  * Steps starting with MIPI refer to VBT sequences, note that for v2
 763  * VBTs several steps which have a VBT in v2 are expected to be handled
 764  * directly by the driver, by directly driving gpios for example.
 765  *
 766  * v2 video mode seq         v3 video mode seq         command mode seq
 767  * - power on                - MIPIPanelPowerOn        - power on
 768  * - wait t1+t2                                        - wait t1+t2
 769  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 770  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 771  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 772  *                                                     - MIPITearOn
 773  *                                                     - MIPIDisplayOn
 774  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 775  * - MIPIDisplayOn           - MIPIDisplayOn
 776  * - wait t5                                           - wait t5
 777  * - backlight on            - MIPIBacklightOn         - backlight on
 778  * ...                       ...                       ... issue mem cmds ...
 779  * - backlight off           - MIPIBacklightOff        - backlight off
 780  * - wait t6                                           - wait t6
 781  * - MIPIDisplayOff
 782  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 783  *                                                     - MIPITearOff
 784  *                           - MIPIDisplayOff          - MIPIDisplayOff
 785  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 786  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 787  * - wait t3                                           - wait t3
 788  * - power off               - MIPIPanelPowerOff       - power off
 789  * - wait t4                                           - wait t4
 790  */
 791
 792 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 793                                  const struct intel_crtc_state *pipe_config,
 794                                  const struct drm_connector_state *conn_state)
 795 {
 796         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 797         struct drm_crtc *crtc = pipe_config->base.crtc;
 798         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 800         int pipe = intel_crtc->pipe;
 801         enum port port;
 802         u32 val;
 803         bool glk_cold_boot = false;
 804
 805         DRM_DEBUG_KMS("\n");
 806
 807         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 808
 809         /*
 810          * The BIOS may leave the PLL in a wonky state where it doesn't
 811          * lock. It needs to be fully powered down to fix it.
 812          */
 813         intel_disable_dsi_pll(encoder);
 814         intel_enable_dsi_pll(encoder, pipe_config);
 815
 816         if (IS_BROXTON(dev_priv)) {
 817                 /* Add MIPI IO reset programming for modeset */
 818                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 819                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 820                                         val | MIPIO_RST_CTRL);
 821
 822                 /* Power up DSI regulator */
 823                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 824                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 825         }
 826
 827         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 828                 u32 val;
 829
 830                 /* Disable DPOunit clock gating, can stall pipe */
 831                 val = I915_READ(DSPCLK_GATE_D);
 832                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 833                 I915_WRITE(DSPCLK_GATE_D, val);
 834         }
 835
 836         if (!IS_GEMINILAKE(dev_priv))
 837                 intel_dsi_prepare(encoder, pipe_config);
 838
 839         /* Power on, try both CRC pmic gpio and VBT */
 840         if (intel_dsi->gpio_panel)
 841                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 842         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 843         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 844
 845         /* Deassert reset */
 846         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 847
 848         if (IS_GEMINILAKE(dev_priv)) {
 849                 glk_cold_boot = glk_dsi_enable_io(encoder);
 850
 851                 /* Prepare port in cold boot(s3/s4) scenario */
 852                 if (glk_cold_boot)
 853                         intel_dsi_prepare(encoder, pipe_config);
 854         }
 855
 856         /* Put device in ready state (LP-11) */
 857         intel_dsi_device_ready(encoder);
 858
 859         /* Prepare port in normal boot scenario */
 860         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 861                 intel_dsi_prepare(encoder, pipe_config);
 862
 863         /* Send initialization commands in LP mode */
 864         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 865
 866         /* Enable port in pre-enable phase itself because as per hw team
 867          * recommendation, port should be enabled befor plane & pipe */
 868         if (is_cmd_mode(intel_dsi)) {
 869                 for_each_dsi_port(port, intel_dsi->ports)
 870                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 871                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 872                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 873         } else {
 874                 msleep(20); /* XXX */
 875                 for_each_dsi_port(port, intel_dsi->ports)
 876                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 877                 intel_dsi_msleep(intel_dsi, 100);
 878
 879                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 880
 881                 intel_dsi_port_enable(encoder, pipe_config);
 882         }
 883
 884         intel_panel_enable_backlight(pipe_config, conn_state);
 885         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 886 }
 887
 888 /*
 889  * DSI port enable has to be done before pipe and plane enable, so we do it in
 890  * the pre_enable hook.
 891  */
 892 static void intel_dsi_enable_nop(struct intel_encoder *encoder,
 893                                  const struct intel_crtc_state *pipe_config,
 894                                  const struct drm_connector_state *conn_state)
 895 {
 896         DRM_DEBUG_KMS("\n");
 897 }
 898
 899 /*
 900  * DSI port disable has to be done after pipe and plane disable, so we do it in
 901  * the post_disable hook.
 902  */
 903 static void intel_dsi_disable(struct intel_encoder *encoder,
 904                               const struct intel_crtc_state *old_crtc_state,
 905                               const struct drm_connector_state *old_conn_state)
 906 {
 907         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 908         enum port port;
 909
 910         DRM_DEBUG_KMS("\n");
 911
 912         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 913         intel_panel_disable_backlight(old_conn_state);
 914
 915         /*
 916          * According to the spec we should send SHUTDOWN before
 917          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 918          * has shown that the v3 sequence works for v2 VBTs too
 919          */
 920         if (is_vid_mode(intel_dsi)) {
 921                 /* Send Shutdown command to the panel in LP mode */
 922                 for_each_dsi_port(port, intel_dsi->ports)
 923                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 924                 msleep(10);
 925         }
 926 }
 927
 928 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 929 {
 930         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 931
 932         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
 933             IS_BROXTON(dev_priv))
 934                 vlv_dsi_clear_device_ready(encoder);
 935         else if (IS_GEMINILAKE(dev_priv))
 936                 glk_dsi_clear_device_ready(encoder);
 937 }
 938
 939 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 940                                    const struct intel_crtc_state *pipe_config,
 941                                    const struct drm_connector_state *conn_state)
 942 {
 943         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 944         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 945         enum port port;
 946         u32 val;
 947
 948         DRM_DEBUG_KMS("\n");
 949
 950         if (is_vid_mode(intel_dsi)) {
 951                 for_each_dsi_port(port, intel_dsi->ports)
 952                         wait_for_dsi_fifo_empty(intel_dsi, port);
 953
 954                 intel_dsi_port_disable(encoder);
 955                 usleep_range(2000, 5000);
 956         }
 957
 958         intel_dsi_unprepare(encoder);
 959
 960         /*
 961          * if disable packets are sent before sending shutdown packet then in
 962          * some next enable sequence send turn on packet error is observed
 963          */
 964         if (is_cmd_mode(intel_dsi))
 965                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 966         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 967
 968         /* Transition to LP-00 */
 969         intel_dsi_clear_device_ready(encoder);
 970
 971         if (IS_BROXTON(dev_priv)) {
 972                 /* Power down DSI regulator to save power */
 973                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 974                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
 975
 976                 /* Add MIPI IO reset programming for modeset */
 977                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 978                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 979                                 val & ~MIPIO_RST_CTRL);
 980         }
 981
 982         intel_disable_dsi_pll(encoder);
 983
 984         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 985                 u32 val;
 986
 987                 val = I915_READ(DSPCLK_GATE_D);
 988                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 989                 I915_WRITE(DSPCLK_GATE_D, val);
 990         }
 991
 992         /* Assert reset */
 993         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 994
 995         /* Power off, try both CRC pmic gpio and VBT */
 996         intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
 997         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 998         if (intel_dsi->gpio_panel)
 999                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
1000
1001         /*
1002          * FIXME As we do with eDP, just make a note of the time here
1003          * and perform the wait before the next panel power on.
1004          */
1005         intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
1006 }
1007
1008 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
1009                                    enum pipe *pipe)
1010 {
1011         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1012         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1013         enum port port;
1014         bool active = false;
1015
1016         DRM_DEBUG_KMS("\n");
1017
1018         if (!intel_display_power_get_if_enabled(dev_priv,
1019                                                 encoder->power_domain))
1020                 return false;
1021
1022         /*
1023          * On Broxton the PLL needs to be enabled with a valid divider
1024          * configuration, otherwise accessing DSI registers will hang the
1025          * machine. See BSpec North Display Engine registers/MIPI[BXT].
1026          */
1027         if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
1028                 goto out_put_power;
1029
1030         /* XXX: this only works for one DSI output */
1031         for_each_dsi_port(port, intel_dsi->ports) {
1032                 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
1033                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
1034                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
1035
1036                 /*
1037                  * Due to some hardware limitations on VLV/CHV, the DPI enable
1038                  * bit in port C control register does not get set. As a
1039                  * workaround, check pipe B conf instead.
1040                  */
1041                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1042                     port == PORT_C)
1043                         enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1044
1045                 /* Try command mode if video mode not enabled */
1046                 if (!enabled) {
1047                         u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
1048                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1049                 }
1050
1051                 if (!enabled)
1052                         continue;
1053
1054                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1055                         continue;
1056
1057                 if (IS_GEN9_LP(dev_priv)) {
1058                         u32 tmp = I915_READ(MIPI_CTRL(port));
1059                         tmp &= BXT_PIPE_SELECT_MASK;
1060                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1061
1062                         if (WARN_ON(tmp > PIPE_C))
1063                                 continue;
1064
1065                         *pipe = tmp;
1066                 } else {
1067                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1068                 }
1069
1070                 active = true;
1071                 break;
1072         }
1073
1074 out_put_power:
1075         intel_display_power_put(dev_priv, encoder->power_domain);
1076
1077         return active;
1078 }
1079
1080 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1081                                     struct intel_crtc_state *pipe_config)
1082 {
1083         struct drm_device *dev = encoder->base.dev;
1084         struct drm_i915_private *dev_priv = to_i915(dev);
1085         struct drm_display_mode *adjusted_mode =
1086                                         &pipe_config->base.adjusted_mode;
1087         struct drm_display_mode *adjusted_mode_sw;
1088         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1089         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1090         unsigned int lane_count = intel_dsi->lane_count;
1091         unsigned int bpp, fmt;
1092         enum port port;
1093         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1094         u16 hfp_sw, hsync_sw, hbp_sw;
1095         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1096                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1097
1098         /* FIXME: hw readout should not depend on SW state */
1099         adjusted_mode_sw = &crtc->config->base.adjusted_mode;
1100
1101         /*
1102          * Atleast one port is active as encoder->get_config called only if
1103          * encoder->get_hw_state() returns true.
1104          */
1105         for_each_dsi_port(port, intel_dsi->ports) {
1106                 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1107                         break;
1108         }
1109
1110         fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1111         pipe_config->pipe_bpp =
1112                         mipi_dsi_pixel_format_to_bpp(
1113                                 pixel_format_from_register_bits(fmt));
1114         bpp = pipe_config->pipe_bpp;
1115
1116         /* Enable Frame time stamo based scanline reporting */
1117         adjusted_mode->private_flags |=
1118                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1119
1120         /* In terms of pixels */
1121         adjusted_mode->crtc_hdisplay =
1122                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1123         adjusted_mode->crtc_vdisplay =
1124                                 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1125         adjusted_mode->crtc_vtotal =
1126                                 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1127
1128         hactive = adjusted_mode->crtc_hdisplay;
1129         hfp = I915_READ(MIPI_HFP_COUNT(port));
1130
1131         /*
1132          * Meaningful for video mode non-burst sync pulse mode only,
1133          * can be zero for non-burst sync events and burst modes
1134          */
1135         hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1136         hbp = I915_READ(MIPI_HBP_COUNT(port));
1137
1138         /* harizontal values are in terms of high speed byte clock */
1139         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1140                                                 intel_dsi->burst_mode_ratio);
1141         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1142                                                 intel_dsi->burst_mode_ratio);
1143         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1144                                                 intel_dsi->burst_mode_ratio);
1145
1146         if (intel_dsi->dual_link) {
1147                 hfp *= 2;
1148                 hsync *= 2;
1149                 hbp *= 2;
1150         }
1151
1152         /* vertical values are in terms of lines */
1153         vfp = I915_READ(MIPI_VFP_COUNT(port));
1154         vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1155         vbp = I915_READ(MIPI_VBP_COUNT(port));
1156
1157         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1158         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1159         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1160         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1161         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1162
1163         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1164         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1165         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1166         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1167
1168         /*
1169          * In BXT DSI there is no regs programmed with few horizontal timings
1170          * in Pixels but txbyteclkhs.. So retrieval process adds some
1171          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1172          * Actually here for the given adjusted_mode, we are calculating the
1173          * value programmed to the port and then back to the horizontal timing
1174          * param in pixels. This is the expected value, including roundup errors
1175          * And if that is same as retrieved value from port, then
1176          * (HW state) adjusted_mode's horizontal timings are corrected to
1177          * match with SW state to nullify the errors.
1178          */
1179         /* Calculating the value programmed to the Port register */
1180         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1181                                         adjusted_mode_sw->crtc_hdisplay;
1182         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1183                                         adjusted_mode_sw->crtc_hsync_start;
1184         hbp_sw = adjusted_mode_sw->crtc_htotal -
1185                                         adjusted_mode_sw->crtc_hsync_end;
1186
1187         if (intel_dsi->dual_link) {
1188                 hfp_sw /= 2;
1189                 hsync_sw /= 2;
1190                 hbp_sw /= 2;
1191         }
1192
1193         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1194                                                 intel_dsi->burst_mode_ratio);
1195         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1196                             intel_dsi->burst_mode_ratio);
1197         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1198                                                 intel_dsi->burst_mode_ratio);
1199
1200         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1201         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1202                                                 intel_dsi->burst_mode_ratio);
1203         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1204                                                 intel_dsi->burst_mode_ratio);
1205         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1206                                                 intel_dsi->burst_mode_ratio);
1207
1208         if (intel_dsi->dual_link) {
1209                 hfp_sw *= 2;
1210                 hsync_sw *= 2;
1211                 hbp_sw *= 2;
1212         }
1213
1214         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1215                                                         hsync_sw + hbp_sw;
1216         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1217         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1218         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1219         crtc_hblank_end_sw = crtc_htotal_sw;
1220
1221         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1222                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1223
1224         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1225                 adjusted_mode->crtc_hsync_start =
1226                                         adjusted_mode_sw->crtc_hsync_start;
1227
1228         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1229                 adjusted_mode->crtc_hsync_end =
1230                                         adjusted_mode_sw->crtc_hsync_end;
1231
1232         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1233                 adjusted_mode->crtc_hblank_start =
1234                                         adjusted_mode_sw->crtc_hblank_start;
1235
1236         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1237                 adjusted_mode->crtc_hblank_end =
1238                                         adjusted_mode_sw->crtc_hblank_end;
1239 }
1240
1241 static void intel_dsi_get_config(struct intel_encoder *encoder,
1242                                  struct intel_crtc_state *pipe_config)
1243 {
1244         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1245         u32 pclk;
1246         DRM_DEBUG_KMS("\n");
1247
1248         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1249
1250         if (IS_GEN9_LP(dev_priv))
1251                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1252
1253         pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
1254                                   pipe_config);
1255         if (!pclk)
1256                 return;
1257
1258         pipe_config->base.adjusted_mode.crtc_clock = pclk;
1259         pipe_config->port_clock = pclk;
1260 }
1261
1262 static enum drm_mode_status
1263 intel_dsi_mode_valid(struct drm_connector *connector,
1264                      struct drm_display_mode *mode)
1265 {
1266         struct intel_connector *intel_connector = to_intel_connector(connector);
1267         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
1268         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1269
1270         DRM_DEBUG_KMS("\n");
1271
1272         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1273                 return MODE_NO_DBLESCAN;
1274
1275         if (fixed_mode) {
1276                 if (mode->hdisplay > fixed_mode->hdisplay)
1277                         return MODE_PANEL;
1278                 if (mode->vdisplay > fixed_mode->vdisplay)
1279                         return MODE_PANEL;
1280                 if (fixed_mode->clock > max_dotclk)
1281                         return MODE_CLOCK_HIGH;
1282         }
1283
1284         return MODE_OK;
1285 }
1286
1287 /* return txclkesc cycles in terms of divider and duration in us */
1288 static u16 txclkesc(u32 divider, unsigned int us)
1289 {
1290         switch (divider) {
1291         case ESCAPE_CLOCK_DIVIDER_1:
1292         default:
1293                 return 20 * us;
1294         case ESCAPE_CLOCK_DIVIDER_2:
1295                 return 10 * us;
1296         case ESCAPE_CLOCK_DIVIDER_4:
1297                 return 5 * us;
1298         }
1299 }
1300
1301 static void set_dsi_timings(struct drm_encoder *encoder,
1302                             const struct drm_display_mode *adjusted_mode)
1303 {
1304         struct drm_device *dev = encoder->dev;
1305         struct drm_i915_private *dev_priv = to_i915(dev);
1306         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1307         enum port port;
1308         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1309         unsigned int lane_count = intel_dsi->lane_count;
1310
1311         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1312
1313         hactive = adjusted_mode->crtc_hdisplay;
1314         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1315         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1316         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1317
1318         if (intel_dsi->dual_link) {
1319                 hactive /= 2;
1320                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1321                         hactive += intel_dsi->pixel_overlap;
1322                 hfp /= 2;
1323                 hsync /= 2;
1324                 hbp /= 2;
1325         }
1326
1327         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1328         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1329         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1330
1331         /* horizontal values are in terms of high speed byte clock */
1332         hactive = txbyteclkhs(hactive, bpp, lane_count,
1333                               intel_dsi->burst_mode_ratio);
1334         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1335         hsync = txbyteclkhs(hsync, bpp, lane_count,
1336                             intel_dsi->burst_mode_ratio);
1337         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1338
1339         for_each_dsi_port(port, intel_dsi->ports) {
1340                 if (IS_GEN9_LP(dev_priv)) {
1341                         /*
1342                          * Program hdisplay and vdisplay on MIPI transcoder.
1343                          * This is different from calculated hactive and
1344                          * vactive, as they are calculated per channel basis,
1345                          * whereas these values should be based on resolution.
1346                          */
1347                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1348                                    adjusted_mode->crtc_hdisplay);
1349                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1350                                    adjusted_mode->crtc_vdisplay);
1351                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1352                                    adjusted_mode->crtc_vtotal);
1353                 }
1354
1355                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1356                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1357
1358                 /* meaningful for video mode non-burst sync pulse mode only,
1359                  * can be zero for non-burst sync events and burst modes */
1360                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1361                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1362
1363                 /* vertical values are in terms of lines */
1364                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1365                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1366                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1367         }
1368 }
1369
1370 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1371 {
1372         switch (fmt) {
1373         case MIPI_DSI_FMT_RGB888:
1374                 return VID_MODE_FORMAT_RGB888;
1375         case MIPI_DSI_FMT_RGB666:
1376                 return VID_MODE_FORMAT_RGB666;
1377         case MIPI_DSI_FMT_RGB666_PACKED:
1378                 return VID_MODE_FORMAT_RGB666_PACKED;
1379         case MIPI_DSI_FMT_RGB565:
1380                 return VID_MODE_FORMAT_RGB565;
1381         default:
1382                 MISSING_CASE(fmt);
1383                 return VID_MODE_FORMAT_RGB666;
1384         }
1385 }
1386
1387 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1388                               const struct intel_crtc_state *pipe_config)
1389 {
1390         struct drm_encoder *encoder = &intel_encoder->base;
1391         struct drm_device *dev = encoder->dev;
1392         struct drm_i915_private *dev_priv = to_i915(dev);
1393         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1394         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1395         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1396         enum port port;
1397         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1398         u32 val, tmp;
1399         u16 mode_hdisplay;
1400
1401         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1402
1403         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1404
1405         if (intel_dsi->dual_link) {
1406                 mode_hdisplay /= 2;
1407                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1408                         mode_hdisplay += intel_dsi->pixel_overlap;
1409         }
1410
1411         for_each_dsi_port(port, intel_dsi->ports) {
1412                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1413                         /*
1414                          * escape clock divider, 20MHz, shared for A and C.
1415                          * device ready must be off when doing this! txclkesc?
1416                          */
1417                         tmp = I915_READ(MIPI_CTRL(PORT_A));
1418                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1419                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1420                                         ESCAPE_CLOCK_DIVIDER_1);
1421
1422                         /* read request priority is per pipe */
1423                         tmp = I915_READ(MIPI_CTRL(port));
1424                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1425                         I915_WRITE(MIPI_CTRL(port), tmp |
1426                                         READ_REQUEST_PRIORITY_HIGH);
1427                 } else if (IS_GEN9_LP(dev_priv)) {
1428                         enum pipe pipe = intel_crtc->pipe;
1429
1430                         tmp = I915_READ(MIPI_CTRL(port));
1431                         tmp &= ~BXT_PIPE_SELECT_MASK;
1432
1433                         tmp |= BXT_PIPE_SELECT(pipe);
1434                         I915_WRITE(MIPI_CTRL(port), tmp);
1435                 }
1436
1437                 /* XXX: why here, why like this? handling in irq handler?! */
1438                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1439                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1440
1441                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1442
1443                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1444                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1445                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1446         }
1447
1448         set_dsi_timings(encoder, adjusted_mode);
1449
1450         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1451         if (is_cmd_mode(intel_dsi)) {
1452                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1453                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1454         } else {
1455                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1456                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1457         }
1458
1459         tmp = 0;
1460         if (intel_dsi->eotp_pkt == 0)
1461                 tmp |= EOT_DISABLE;
1462         if (intel_dsi->clock_stop)
1463                 tmp |= CLOCKSTOP;
1464
1465         if (IS_GEN9_LP(dev_priv)) {
1466                 tmp |= BXT_DPHY_DEFEATURE_EN;
1467                 if (!is_cmd_mode(intel_dsi))
1468                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1469         }
1470
1471         for_each_dsi_port(port, intel_dsi->ports) {
1472                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1473
1474                 /* timeouts for recovery. one frame IIUC. if counter expires,
1475                  * EOT and stop state. */
1476
1477                 /*
1478                  * In burst mode, value greater than one DPI line Time in byte
1479                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1480                  * said value is recommended.
1481                  *
1482                  * In non-burst mode, Value greater than one DPI frame time in
1483                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1484                  * said value is recommended.
1485                  *
1486                  * In DBI only mode, value greater than one DBI frame time in
1487                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1488                  * said value is recommended.
1489                  */
1490
1491                 if (is_vid_mode(intel_dsi) &&
1492                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1493                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1494                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1495                                             intel_dsi->lane_count,
1496                                             intel_dsi->burst_mode_ratio) + 1);
1497                 } else {
1498                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1499                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
1500                                             adjusted_mode->crtc_htotal,
1501                                             bpp, intel_dsi->lane_count,
1502                                             intel_dsi->burst_mode_ratio) + 1);
1503                 }
1504                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1505                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1506                                                 intel_dsi->turn_arnd_val);
1507                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1508                                                 intel_dsi->rst_timer_val);
1509
1510                 /* dphy stuff */
1511
1512                 /* in terms of low power clock */
1513                 I915_WRITE(MIPI_INIT_COUNT(port),
1514                                 txclkesc(intel_dsi->escape_clk_div, 100));
1515
1516                 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1517                         /*
1518                          * BXT spec says write MIPI_INIT_COUNT for
1519                          * both the ports, even if only one is
1520                          * getting used. So write the other port
1521                          * if not in dual link mode.
1522                          */
1523                         I915_WRITE(MIPI_INIT_COUNT(port ==
1524                                                 PORT_A ? PORT_C : PORT_A),
1525                                         intel_dsi->init_count);
1526                 }
1527
1528                 /* recovery disables */
1529                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1530
1531                 /* in terms of low power clock */
1532                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1533
1534                 /* in terms of txbyteclkhs. actual high to low switch +
1535                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1536                  *
1537                  * XXX: write MIPI_STOP_STATE_STALL?
1538                  */
1539                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1540                                                 intel_dsi->hs_to_lp_count);
1541
1542                 /* XXX: low power clock equivalence in terms of byte clock.
1543                  * the number of byte clocks occupied in one low power clock.
1544                  * based on txbyteclkhs and txclkesc.
1545                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1546                  * ) / 105.???
1547                  */
1548                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1549
1550                 if (IS_GEMINILAKE(dev_priv)) {
1551                         I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1552                                         intel_dsi->lp_byte_clk);
1553                         /* Shadow of DPHY reg */
1554                         I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1555                                         intel_dsi->dphy_reg);
1556                 }
1557
1558                 /* the bw essential for transmitting 16 long packets containing
1559                  * 252 bytes meant for dcs write memory command is programmed in
1560                  * this register in terms of byte clocks. based on dsi transfer
1561                  * rate and the number of lanes configured the time taken to
1562                  * transmit 16 long packets in a dsi stream varies. */
1563                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1564
1565                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1566                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1567                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1568
1569                 if (is_vid_mode(intel_dsi))
1570                         /* Some panels might have resolution which is not a
1571                          * multiple of 64 like 1366 x 768. Enable RANDOM
1572                          * resolution support for such panels by default */
1573                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1574                                 intel_dsi->video_frmt_cfg_bits |
1575                                 intel_dsi->video_mode_format |
1576                                 IP_TG_CONFIG |
1577                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1578         }
1579 }
1580
1581 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1582 {
1583         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1584         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1585         enum port port;
1586         u32 val;
1587
1588         if (!IS_GEMINILAKE(dev_priv)) {
1589                 for_each_dsi_port(port, intel_dsi->ports) {
1590                         /* Panel commands can be sent when clock is in LP11 */
1591                         I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1592
1593                         intel_dsi_reset_clocks(encoder, port);
1594                         I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1595
1596                         val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1597                         val &= ~VID_MODE_FORMAT_MASK;
1598                         I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1599
1600                         I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1601                 }
1602         }
1603 }
1604
1605 static int intel_dsi_get_modes(struct drm_connector *connector)
1606 {
1607         struct intel_connector *intel_connector = to_intel_connector(connector);
1608         struct drm_display_mode *mode;
1609
1610         DRM_DEBUG_KMS("\n");
1611
1612         if (!intel_connector->panel.fixed_mode) {
1613                 DRM_DEBUG_KMS("no fixed mode\n");
1614                 return 0;
1615         }
1616
1617         mode = drm_mode_duplicate(connector->dev,
1618                                   intel_connector->panel.fixed_mode);
1619         if (!mode) {
1620                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1621                 return 0;
1622         }
1623
1624         drm_mode_probed_add(connector, mode);
1625         return 1;
1626 }
1627
1628 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1629 {
1630         struct intel_connector *intel_connector = to_intel_connector(connector);
1631
1632         DRM_DEBUG_KMS("\n");
1633         intel_panel_fini(&intel_connector->panel);
1634         drm_connector_cleanup(connector);
1635         kfree(connector);
1636 }
1637
1638 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1639 {
1640         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1641
1642         /* dispose of the gpios */
1643         if (intel_dsi->gpio_panel)
1644                 gpiod_put(intel_dsi->gpio_panel);
1645
1646         intel_encoder_destroy(encoder);
1647 }
1648
1649 static const struct drm_encoder_funcs intel_dsi_funcs = {
1650         .destroy = intel_dsi_encoder_destroy,
1651 };
1652
1653 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1654         .get_modes = intel_dsi_get_modes,
1655         .mode_valid = intel_dsi_mode_valid,
1656         .atomic_check = intel_digital_connector_atomic_check,
1657 };
1658
1659 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1660         .late_register = intel_connector_register,
1661         .early_unregister = intel_connector_unregister,
1662         .destroy = intel_dsi_connector_destroy,
1663         .fill_modes = drm_helper_probe_single_connector_modes,
1664         .atomic_get_property = intel_digital_connector_atomic_get_property,
1665         .atomic_set_property = intel_digital_connector_atomic_set_property,
1666         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1667         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1668 };
1669
1670 static int intel_dsi_get_panel_orientation(struct intel_connector *connector)
1671 {
1672         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1673         int orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
1674         enum i9xx_plane_id plane;
1675         u32 val;
1676
1677         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1678                 if (connector->encoder->crtc_mask == BIT(PIPE_B))
1679                         plane = PLANE_B;
1680                 else
1681                         plane = PLANE_A;
1682
1683                 val = I915_READ(DSPCNTR(plane));
1684                 if (val & DISPPLANE_ROTATE_180)
1685                         orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
1686         }
1687
1688         return orientation;
1689 }
1690
1691 static void intel_dsi_add_properties(struct intel_connector *connector)
1692 {
1693         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1694
1695         if (connector->panel.fixed_mode) {
1696                 u32 allowed_scalers;
1697
1698                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1699                 if (!HAS_GMCH_DISPLAY(dev_priv))
1700                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1701
1702                 drm_connector_attach_scaling_mode_property(&connector->base,
1703                                                                 allowed_scalers);
1704
1705                 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1706
1707                 connector->base.display_info.panel_orientation =
1708                         intel_dsi_get_panel_orientation(connector);
1709                 drm_connector_init_panel_orientation_property(
1710                                 &connector->base,
1711                                 connector->panel.fixed_mode->hdisplay,
1712                                 connector->panel.fixed_mode->vdisplay);
1713         }
1714 }
1715
1716 void intel_dsi_init(struct drm_i915_private *dev_priv)
1717 {
1718         struct drm_device *dev = &dev_priv->drm;
1719         struct intel_dsi *intel_dsi;
1720         struct intel_encoder *intel_encoder;
1721         struct drm_encoder *encoder;
1722         struct intel_connector *intel_connector;
1723         struct drm_connector *connector;
1724         struct drm_display_mode *scan, *fixed_mode = NULL;
1725         enum port port;
1726
1727         DRM_DEBUG_KMS("\n");
1728
1729         /* There is no detection method for MIPI so rely on VBT */
1730         if (!intel_bios_is_dsi_present(dev_priv, &port))
1731                 return;
1732
1733         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1734                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1735         } else if (IS_GEN9_LP(dev_priv)) {
1736                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1737         } else {
1738                 DRM_ERROR("Unsupported Mipi device to reg base");
1739                 return;
1740         }
1741
1742         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1743         if (!intel_dsi)
1744                 return;
1745
1746         intel_connector = intel_connector_alloc();
1747         if (!intel_connector) {
1748                 kfree(intel_dsi);
1749                 return;
1750         }
1751
1752         intel_encoder = &intel_dsi->base;
1753         encoder = &intel_encoder->base;
1754         intel_dsi->attached_connector = intel_connector;
1755
1756         connector = &intel_connector->base;
1757
1758         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1759                          "DSI %c", port_name(port));
1760
1761         intel_encoder->compute_config = intel_dsi_compute_config;
1762         intel_encoder->pre_enable = intel_dsi_pre_enable;
1763         intel_encoder->enable = intel_dsi_enable_nop;
1764         intel_encoder->disable = intel_dsi_disable;
1765         intel_encoder->post_disable = intel_dsi_post_disable;
1766         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1767         intel_encoder->get_config = intel_dsi_get_config;
1768
1769         intel_connector->get_hw_state = intel_connector_get_hw_state;
1770
1771         intel_encoder->port = port;
1772
1773         /*
1774          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1775          * port C. BXT isn't limited like this.
1776          */
1777         if (IS_GEN9_LP(dev_priv))
1778                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1779         else if (port == PORT_A)
1780                 intel_encoder->crtc_mask = BIT(PIPE_A);
1781         else
1782                 intel_encoder->crtc_mask = BIT(PIPE_B);
1783
1784         if (dev_priv->vbt.dsi.config->dual_link)
1785                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1786         else
1787                 intel_dsi->ports = BIT(port);
1788
1789         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1790         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1791
1792         /* Create a DSI host (and a device) for each port. */
1793         for_each_dsi_port(port, intel_dsi->ports) {
1794                 struct intel_dsi_host *host;
1795
1796                 host = intel_dsi_host_init(intel_dsi, port);
1797                 if (!host)
1798                         goto err;
1799
1800                 intel_dsi->dsi_hosts[port] = host;
1801         }
1802
1803         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1804                 DRM_DEBUG_KMS("no device found\n");
1805                 goto err;
1806         }
1807
1808         /*
1809          * In case of BYT with CRC PMIC, we need to use GPIO for
1810          * Panel control.
1811          */
1812         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1813             (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
1814                 intel_dsi->gpio_panel =
1815                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1816
1817                 if (IS_ERR(intel_dsi->gpio_panel)) {
1818                         DRM_ERROR("Failed to own gpio for panel control\n");
1819                         intel_dsi->gpio_panel = NULL;
1820                 }
1821         }
1822
1823         intel_encoder->type = INTEL_OUTPUT_DSI;
1824         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1825         intel_encoder->cloneable = 0;
1826         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1827                            DRM_MODE_CONNECTOR_DSI);
1828
1829         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1830
1831         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1832         connector->interlace_allowed = false;
1833         connector->doublescan_allowed = false;
1834
1835         intel_connector_attach_encoder(intel_connector, intel_encoder);
1836
1837         mutex_lock(&dev->mode_config.mutex);
1838         intel_dsi_vbt_get_modes(intel_dsi);
1839         list_for_each_entry(scan, &connector->probed_modes, head) {
1840                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1841                         fixed_mode = drm_mode_duplicate(dev, scan);
1842                         break;
1843                 }
1844         }
1845         mutex_unlock(&dev->mode_config.mutex);
1846
1847         if (!fixed_mode) {
1848                 DRM_DEBUG_KMS("no fixed mode\n");
1849                 goto err;
1850         }
1851
1852         connector->display_info.width_mm = fixed_mode->width_mm;
1853         connector->display_info.height_mm = fixed_mode->height_mm;
1854
1855         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1856         intel_panel_setup_backlight(connector, INVALID_PIPE);
1857
1858         intel_dsi_add_properties(intel_connector);
1859
1860         return;
1861
1862 err:
1863         drm_encoder_cleanup(&intel_encoder->base);
1864         kfree(intel_dsi);
1865         kfree(intel_connector);
1866 }