drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__;                                                      \
  56         for (;;) {                                                      \
  57                 bool expired__ = time_after(jiffies, timeout__);        \
  58                 if (COND) {                                             \
  59                         ret__ = 0;                                      \
  60                         break;                                          \
  61                 }                                                       \
  62                 if (expired__) {                                        \
  63                         ret__ = -ETIMEDOUT;                             \
  64                         break;                                          \
  65                 }                                                       \
  66                 if ((W) && drm_can_sleep()) {                           \
  67                         usleep_range((W), (W)*2);                       \
  68                 } else {                                                \
  69                         cpu_relax();                                    \
  70                 }                                                       \
  71         }                                                               \
  72         ret__;                                                          \
  73 })
  74
  75 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  76
  77 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  78 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  79 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  80 #else
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  82 #endif
  83
  84 #define _wait_for_atomic(COND, US, ATOMIC) \
  85 ({ \
  86         int cpu, ret, timeout = (US) * 1000; \
  87         u64 base; \
  88         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  89         BUILD_BUG_ON((US) > 50000); \
  90         if (!(ATOMIC)) { \
  91                 preempt_disable(); \
  92                 cpu = smp_processor_id(); \
  93         } \
  94         base = local_clock(); \
  95         for (;;) { \
  96                 u64 now = local_clock(); \
  97                 if (!(ATOMIC)) \
  98                         preempt_enable(); \
  99                 if (COND) { \
 100                         ret = 0; \
 101                         break; \
 102                 } \
 103                 if (now - base >= timeout) { \
 104                         ret = -ETIMEDOUT; \
 105                         break; \
 106                 } \
 107                 cpu_relax(); \
 108                 if (!(ATOMIC)) { \
 109                         preempt_disable(); \
 110                         if (unlikely(cpu != smp_processor_id())) { \
 111                                 timeout -= now - base; \
 112                                 cpu = smp_processor_id(); \
 113                                 base = local_clock(); \
 114                         } \
 115                 } \
 116         } \
 117         ret; \
 118 })
 119
 120 #define wait_for_us(COND, US) \
 121 ({ \
 122         int ret__; \
 123         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 124         if ((US) > 10) \
 125                 ret__ = _wait_for((COND), (US), 10); \
 126         else \
 127                 ret__ = _wait_for_atomic((COND), (US), 0); \
 128         ret__; \
 129 })
 130
 131 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 132 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 133
 134 #define KHz(x) (1000 * (x))
 135 #define MHz(x) KHz(1000 * (x))
 136
 137 /*
 138  * Display related stuff
 139  */
 140
 141 /* store information about an Ixxx DVO */
 142 /* The i830->i865 use multiple DVOs with multiple i2cs */
 143 /* the i915, i945 have a single sDVO i2c bus - which is different */
 144 #define MAX_OUTPUTS 6
 145 /* maximum connectors per crtcs in the mode set */
 146
 147 /* Maximum cursor sizes */
 148 #define GEN2_CURSOR_WIDTH 64
 149 #define GEN2_CURSOR_HEIGHT 64
 150 #define MAX_CURSOR_WIDTH 256
 151 #define MAX_CURSOR_HEIGHT 256
 152
 153 #define INTEL_I2C_BUS_DVO 1
 154 #define INTEL_I2C_BUS_SDVO 2
 155
 156 /* these are outputs from the chip - integrated only
 157    external chips are via DVO or SDVO output */
 158 enum intel_output_type {
 159         INTEL_OUTPUT_UNUSED = 0,
 160         INTEL_OUTPUT_ANALOG = 1,
 161         INTEL_OUTPUT_DVO = 2,
 162         INTEL_OUTPUT_SDVO = 3,
 163         INTEL_OUTPUT_LVDS = 4,
 164         INTEL_OUTPUT_TVOUT = 5,
 165         INTEL_OUTPUT_HDMI = 6,
 166         INTEL_OUTPUT_DP = 7,
 167         INTEL_OUTPUT_EDP = 8,
 168         INTEL_OUTPUT_DSI = 9,
 169         INTEL_OUTPUT_UNKNOWN = 10,
 170         INTEL_OUTPUT_DP_MST = 11,
 171 };
 172
 173 #define INTEL_DVO_CHIP_NONE 0
 174 #define INTEL_DVO_CHIP_LVDS 1
 175 #define INTEL_DVO_CHIP_TMDS 2
 176 #define INTEL_DVO_CHIP_TVOUT 4
 177
 178 #define INTEL_DSI_VIDEO_MODE    0
 179 #define INTEL_DSI_COMMAND_MODE  1
 180
 181 struct intel_framebuffer {
 182         struct drm_framebuffer base;
 183         struct drm_i915_gem_object *obj;
 184         struct intel_rotation_info rot_info;
 185
 186         /* for each plane in the normal GTT view */
 187         struct {
 188                 unsigned int x, y;
 189         } normal[2];
 190         /* for each plane in the rotated GTT view */
 191         struct {
 192                 unsigned int x, y;
 193                 unsigned int pitch; /* pixels */
 194         } rotated[2];
 195 };
 196
 197 struct intel_fbdev {
 198         struct drm_fb_helper helper;
 199         struct intel_framebuffer *fb;
 200         struct i915_vma *vma;
 201         async_cookie_t cookie;
 202         int preferred_bpp;
 203 };
 204
 205 struct intel_encoder {
 206         struct drm_encoder base;
 207
 208         enum intel_output_type type;
 209         unsigned int cloneable;
 210         void (*hot_plug)(struct intel_encoder *);
 211         bool (*compute_config)(struct intel_encoder *,
 212                                struct intel_crtc_state *,
 213                                struct drm_connector_state *);
 214         void (*pre_pll_enable)(struct intel_encoder *,
 215                                struct intel_crtc_state *,
 216                                struct drm_connector_state *);
 217         void (*pre_enable)(struct intel_encoder *,
 218                            struct intel_crtc_state *,
 219                            struct drm_connector_state *);
 220         void (*enable)(struct intel_encoder *,
 221                        struct intel_crtc_state *,
 222                        struct drm_connector_state *);
 223         void (*disable)(struct intel_encoder *,
 224                         struct intel_crtc_state *,
 225                         struct drm_connector_state *);
 226         void (*post_disable)(struct intel_encoder *,
 227                              struct intel_crtc_state *,
 228                              struct drm_connector_state *);
 229         void (*post_pll_disable)(struct intel_encoder *,
 230                                  struct intel_crtc_state *,
 231                                  struct drm_connector_state *);
 232         /* Read out the current hw state of this connector, returning true if
 233          * the encoder is active. If the encoder is enabled it also set the pipe
 234          * it is connected to in the pipe parameter. */
 235         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 236         /* Reconstructs the equivalent mode flags for the current hardware
 237          * state. This must be called _after_ display->get_pipe_config has
 238          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 239          * be set correctly before calling this function. */
 240         void (*get_config)(struct intel_encoder *,
 241                            struct intel_crtc_state *pipe_config);
 242         /*
 243          * Called during system suspend after all pending requests for the
 244          * encoder are flushed (for example for DP AUX transactions) and
 245          * device interrupts are disabled.
 246          */
 247         void (*suspend)(struct intel_encoder *);
 248         int crtc_mask;
 249         enum hpd_pin hpd_pin;
 250 };
 251
 252 struct intel_panel {
 253         struct drm_display_mode *fixed_mode;
 254         struct drm_display_mode *downclock_mode;
 255         int fitting_mode;
 256
 257         /* backlight */
 258         struct {
 259                 bool present;
 260                 u32 level;
 261                 u32 min;
 262                 u32 max;
 263                 bool enabled;
 264                 bool combination_mode;  /* gen 2/4 only */
 265                 bool active_low_pwm;
 266                 bool alternate_pwm_increment;   /* lpt+ */
 267
 268                 /* PWM chip */
 269                 bool util_pin_active_low;       /* bxt+ */
 270                 u8 controller;          /* bxt+ only */
 271                 struct pwm_device *pwm;
 272
 273                 struct backlight_device *device;
 274
 275                 /* Connector and platform specific backlight functions */
 276                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 277                 uint32_t (*get)(struct intel_connector *connector);
 278                 void (*set)(struct intel_connector *connector, uint32_t level);
 279                 void (*disable)(struct intel_connector *connector);
 280                 void (*enable)(struct intel_connector *connector);
 281                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 282                                       uint32_t hz);
 283                 void (*power)(struct intel_connector *, bool enable);
 284         } backlight;
 285 };
 286
 287 struct intel_connector {
 288         struct drm_connector base;
 289         /*
 290          * The fixed encoder this connector is connected to.
 291          */
 292         struct intel_encoder *encoder;
 293
 294         /* Reads out the current hw, returning true if the connector is enabled
 295          * and active (i.e. dpms ON state). */
 296         bool (*get_hw_state)(struct intel_connector *);
 297
 298         /* Panel info for eDP and LVDS */
 299         struct intel_panel panel;
 300
 301         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 302         struct edid *edid;
 303         struct edid *detect_edid;
 304
 305         /* since POLL and HPD connectors may use the same HPD line keep the native
 306            state of connector->polled in case hotplug storm detection changes it */
 307         u8 polled;
 308
 309         void *port; /* store this opaque as its illegal to dereference it */
 310
 311         struct intel_dp *mst_port;
 312 };
 313
 314 struct dpll {
 315         /* given values */
 316         int n;
 317         int m1, m2;
 318         int p1, p2;
 319         /* derived values */
 320         int     dot;
 321         int     vco;
 322         int     m;
 323         int     p;
 324 };
 325
 326 struct intel_atomic_state {
 327         struct drm_atomic_state base;
 328
 329         unsigned int cdclk;
 330
 331         /*
 332          * Calculated device cdclk, can be different from cdclk
 333          * only when all crtc's are DPMS off.
 334          */
 335         unsigned int dev_cdclk;
 336
 337         bool dpll_set, modeset;
 338
 339         /*
 340          * Does this transaction change the pipes that are active?  This mask
 341          * tracks which CRTC's have changed their active state at the end of
 342          * the transaction (not counting the temporary disable during modesets).
 343          * This mask should only be non-zero when intel_state->modeset is true,
 344          * but the converse is not necessarily true; simply changing a mode may
 345          * not flip the final active status of any CRTC's
 346          */
 347         unsigned int active_pipe_changes;
 348
 349         unsigned int active_crtcs;
 350         unsigned int min_pixclk[I915_MAX_PIPES];
 351
 352         /* SKL/KBL Only */
 353         unsigned int cdclk_pll_vco;
 354
 355         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 356
 357         /*
 358          * Current watermarks can't be trusted during hardware readout, so
 359          * don't bother calculating intermediate watermarks.
 360          */
 361         bool skip_intermediate_wm;
 362
 363         /* Gen9+ only */
 364         struct skl_wm_values wm_results;
 365 };
 366
 367 struct intel_plane_state {
 368         struct drm_plane_state base;
 369         struct drm_rect clip;
 370
 371         struct {
 372                 u32 offset;
 373                 int x, y;
 374         } main;
 375         struct {
 376                 u32 offset;
 377                 int x, y;
 378         } aux;
 379
 380         /*
 381          * scaler_id
 382          *    = -1 : not using a scaler
 383          *    >=  0 : using a scalers
 384          *
 385          * plane requiring a scaler:
 386          *   - During check_plane, its bit is set in
 387          *     crtc_state->scaler_state.scaler_users by calling helper function
 388          *     update_scaler_plane.
 389          *   - scaler_id indicates the scaler it got assigned.
 390          *
 391          * plane doesn't require a scaler:
 392          *   - this can happen when scaling is no more required or plane simply
 393          *     got disabled.
 394          *   - During check_plane, corresponding bit is reset in
 395          *     crtc_state->scaler_state.scaler_users by calling helper function
 396          *     update_scaler_plane.
 397          */
 398         int scaler_id;
 399
 400         struct drm_intel_sprite_colorkey ckey;
 401
 402         /* async flip related structures */
 403         struct drm_i915_gem_request *wait_req;
 404 };
 405
 406 struct intel_initial_plane_config {
 407         struct intel_framebuffer *fb;
 408         unsigned int tiling;
 409         int size;
 410         u32 base;
 411 };
 412
 413 #define SKL_MIN_SRC_W 8
 414 #define SKL_MAX_SRC_W 4096
 415 #define SKL_MIN_SRC_H 8
 416 #define SKL_MAX_SRC_H 4096
 417 #define SKL_MIN_DST_W 8
 418 #define SKL_MAX_DST_W 4096
 419 #define SKL_MIN_DST_H 8
 420 #define SKL_MAX_DST_H 4096
 421
 422 struct intel_scaler {
 423         int in_use;
 424         uint32_t mode;
 425 };
 426
 427 struct intel_crtc_scaler_state {
 428 #define SKL_NUM_SCALERS 2
 429         struct intel_scaler scalers[SKL_NUM_SCALERS];
 430
 431         /*
 432          * scaler_users: keeps track of users requesting scalers on this crtc.
 433          *
 434          *     If a bit is set, a user is using a scaler.
 435          *     Here user can be a plane or crtc as defined below:
 436          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 437          *       bit 31    - crtc
 438          *
 439          * Instead of creating a new index to cover planes and crtc, using
 440          * existing drm_plane_index for planes which is well less than 31
 441          * planes and bit 31 for crtc. This should be fine to cover all
 442          * our platforms.
 443          *
 444          * intel_atomic_setup_scalers will setup available scalers to users
 445          * requesting scalers. It will gracefully fail if request exceeds
 446          * avilability.
 447          */
 448 #define SKL_CRTC_INDEX 31
 449         unsigned scaler_users;
 450
 451         /* scaler used by crtc for panel fitting purpose */
 452         int scaler_id;
 453 };
 454
 455 /* drm_mode->private_flags */
 456 #define I915_MODE_FLAG_INHERITED 1
 457
 458 struct intel_pipe_wm {
 459         struct intel_wm_level wm[5];
 460         struct intel_wm_level raw_wm[5];
 461         uint32_t linetime;
 462         bool fbc_wm_enabled;
 463         bool pipe_enabled;
 464         bool sprites_enabled;
 465         bool sprites_scaled;
 466 };
 467
 468 struct skl_pipe_wm {
 469         struct skl_wm_level wm[8];
 470         struct skl_wm_level trans_wm;
 471         uint32_t linetime;
 472 };
 473
 474 struct intel_crtc_wm_state {
 475         union {
 476                 struct {
 477                         /*
 478                          * Intermediate watermarks; these can be
 479                          * programmed immediately since they satisfy
 480                          * both the current configuration we're
 481                          * switching away from and the new
 482                          * configuration we're switching to.
 483                          */
 484                         struct intel_pipe_wm intermediate;
 485
 486                         /*
 487                          * Optimal watermarks, programmed post-vblank
 488                          * when this state is committed.
 489                          */
 490                         struct intel_pipe_wm optimal;
 491                 } ilk;
 492
 493                 struct {
 494                         /* gen9+ only needs 1-step wm programming */
 495                         struct skl_pipe_wm optimal;
 496
 497                         /* cached plane data rate */
 498                         unsigned plane_data_rate[I915_MAX_PLANES];
 499                         unsigned plane_y_data_rate[I915_MAX_PLANES];
 500
 501                         /* minimum block allocation */
 502                         uint16_t minimum_blocks[I915_MAX_PLANES];
 503                         uint16_t minimum_y_blocks[I915_MAX_PLANES];
 504                 } skl;
 505         };
 506
 507         /*
 508          * Platforms with two-step watermark programming will need to
 509          * update watermark programming post-vblank to switch from the
 510          * safe intermediate watermarks to the optimal final
 511          * watermarks.
 512          */
 513         bool need_postvbl_update;
 514 };
 515
 516 struct intel_crtc_state {
 517         struct drm_crtc_state base;
 518
 519         /**
 520          * quirks - bitfield with hw state readout quirks
 521          *
 522          * For various reasons the hw state readout code might not be able to
 523          * completely faithfully read out the current state. These cases are
 524          * tracked with quirk flags so that fastboot and state checker can act
 525          * accordingly.
 526          */
 527 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 528         unsigned long quirks;
 529
 530         unsigned fb_bits; /* framebuffers to flip */
 531         bool update_pipe; /* can a fast modeset be performed? */
 532         bool disable_cxsr;
 533         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 534         bool fb_changed; /* fb on any of the planes is changed */
 535
 536         /* Pipe source size (ie. panel fitter input size)
 537          * All planes will be positioned inside this space,
 538          * and get clipped at the edges. */
 539         int pipe_src_w, pipe_src_h;
 540
 541         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 542          * between pch encoders and cpu encoders. */
 543         bool has_pch_encoder;
 544
 545         /* Are we sending infoframes on the attached port */
 546         bool has_infoframe;
 547
 548         /* CPU Transcoder for the pipe. Currently this can only differ from the
 549          * pipe on Haswell and later (where we have a special eDP transcoder)
 550          * and Broxton (where we have special DSI transcoders). */
 551         enum transcoder cpu_transcoder;
 552
 553         /*
 554          * Use reduced/limited/broadcast rbg range, compressing from the full
 555          * range fed into the crtcs.
 556          */
 557         bool limited_color_range;
 558
 559         /* Bitmask of encoder types (enum intel_output_type)
 560          * driven by the pipe.
 561          */
 562         unsigned int output_types;
 563
 564         /* Whether we should send NULL infoframes. Required for audio. */
 565         bool has_hdmi_sink;
 566
 567         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 568          * has_dp_encoder is set. */
 569         bool has_audio;
 570
 571         /*
 572          * Enable dithering, used when the selected pipe bpp doesn't match the
 573          * plane bpp.
 574          */
 575         bool dither;
 576
 577         /* Controls for the clock computation, to override various stages. */
 578         bool clock_set;
 579
 580         /* SDVO TV has a bunch of special case. To make multifunction encoders
 581          * work correctly, we need to track this at runtime.*/
 582         bool sdvo_tv_clock;
 583
 584         /*
 585          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 586          * required. This is set in the 2nd loop of calling encoder's
 587          * ->compute_config if the first pick doesn't work out.
 588          */
 589         bool bw_constrained;
 590
 591         /* Settings for the intel dpll used on pretty much everything but
 592          * haswell. */
 593         struct dpll dpll;
 594
 595         /* Selected dpll when shared or NULL. */
 596         struct intel_shared_dpll *shared_dpll;
 597
 598         /* Actual register state of the dpll, for shared dpll cross-checking. */
 599         struct intel_dpll_hw_state dpll_hw_state;
 600
 601         /* DSI PLL registers */
 602         struct {
 603                 u32 ctrl, div;
 604         } dsi_pll;
 605
 606         int pipe_bpp;
 607         struct intel_link_m_n dp_m_n;
 608
 609         /* m2_n2 for eDP downclock */
 610         struct intel_link_m_n dp_m2_n2;
 611         bool has_drrs;
 612
 613         /*
 614          * Frequence the dpll for the port should run at. Differs from the
 615          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 616          * already multiplied by pixel_multiplier.
 617          */
 618         int port_clock;
 619
 620         /* Used by SDVO (and if we ever fix it, HDMI). */
 621         unsigned pixel_multiplier;
 622
 623         uint8_t lane_count;
 624
 625         /*
 626          * Used by platforms having DP/HDMI PHY with programmable lane
 627          * latency optimization.
 628          */
 629         uint8_t lane_lat_optim_mask;
 630
 631         /* Panel fitter controls for gen2-gen4 + VLV */
 632         struct {
 633                 u32 control;
 634                 u32 pgm_ratios;
 635                 u32 lvds_border_bits;
 636         } gmch_pfit;
 637
 638         /* Panel fitter placement and size for Ironlake+ */
 639         struct {
 640                 u32 pos;
 641                 u32 size;
 642                 bool enabled;
 643                 bool force_thru;
 644         } pch_pfit;
 645
 646         /* FDI configuration, only valid if has_pch_encoder is set. */
 647         int fdi_lanes;
 648         struct intel_link_m_n fdi_m_n;
 649
 650         bool ips_enabled;
 651
 652         bool enable_fbc;
 653
 654         bool double_wide;
 655
 656         bool dp_encoder_is_mst;
 657         int pbn;
 658
 659         struct intel_crtc_scaler_state scaler_state;
 660
 661         /* w/a for waiting 2 vblanks during crtc enable */
 662         enum pipe hsw_workaround_pipe;
 663
 664         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 665         bool disable_lp_wm;
 666
 667         struct intel_crtc_wm_state wm;
 668
 669         /* Gamma mode programmed on the pipe */
 670         uint32_t gamma_mode;
 671 };
 672
 673 struct vlv_wm_state {
 674         struct vlv_pipe_wm wm[3];
 675         struct vlv_sr_wm sr[3];
 676         uint8_t num_active_planes;
 677         uint8_t num_levels;
 678         uint8_t level;
 679         bool cxsr;
 680 };
 681
 682 struct intel_crtc {
 683         struct drm_crtc base;
 684         enum pipe pipe;
 685         enum plane plane;
 686         u8 lut_r[256], lut_g[256], lut_b[256];
 687         /*
 688          * Whether the crtc and the connected output pipeline is active. Implies
 689          * that crtc->enabled is set, i.e. the current mode configuration has
 690          * some outputs connected to this crtc.
 691          */
 692         bool active;
 693         unsigned long enabled_power_domains;
 694         bool lowfreq_avail;
 695         struct intel_overlay *overlay;
 696         struct intel_flip_work *flip_work;
 697
 698         atomic_t unpin_work_count;
 699
 700         /* Display surface base address adjustement for pageflips. Note that on
 701          * gen4+ this only adjusts up to a tile, offsets within a tile are
 702          * handled in the hw itself (with the TILEOFF register). */
 703         u32 dspaddr_offset;
 704         int adjusted_x;
 705         int adjusted_y;
 706
 707         uint32_t cursor_addr;
 708         uint32_t cursor_cntl;
 709         uint32_t cursor_size;
 710         uint32_t cursor_base;
 711
 712         struct intel_crtc_state *config;
 713
 714         /* global reset count when the last flip was submitted */
 715         unsigned int reset_count;
 716
 717         /* Access to these should be protected by dev_priv->irq_lock. */
 718         bool cpu_fifo_underrun_disabled;
 719         bool pch_fifo_underrun_disabled;
 720
 721         /* per-pipe watermark state */
 722         struct {
 723                 /* watermarks currently being used  */
 724                 union {
 725                         struct intel_pipe_wm ilk;
 726                         struct skl_pipe_wm skl;
 727                 } active;
 728
 729                 /* allow CxSR on this pipe */
 730                 bool cxsr_allowed;
 731         } wm;
 732
 733         int scanline_offset;
 734
 735         struct {
 736                 unsigned start_vbl_count;
 737                 ktime_t start_vbl_time;
 738                 int min_vbl, max_vbl;
 739                 int scanline_start;
 740         } debug;
 741
 742         /* scalers available on this crtc */
 743         int num_scalers;
 744
 745         struct vlv_wm_state wm_state;
 746 };
 747
 748 struct intel_plane_wm_parameters {
 749         uint32_t horiz_pixels;
 750         uint32_t vert_pixels;
 751         /*
 752          *   For packed pixel formats:
 753          *     bytes_per_pixel - holds bytes per pixel
 754          *   For planar pixel formats:
 755          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 756          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 757          */
 758         uint8_t bytes_per_pixel;
 759         uint8_t y_bytes_per_pixel;
 760         bool enabled;
 761         bool scaled;
 762         u64 tiling;
 763         unsigned int rotation;
 764         uint16_t fifo_size;
 765 };
 766
 767 struct intel_plane {
 768         struct drm_plane base;
 769         int plane;
 770         enum pipe pipe;
 771         bool can_scale;
 772         int max_downscale;
 773         uint32_t frontbuffer_bit;
 774
 775         /* Since we need to change the watermarks before/after
 776          * enabling/disabling the planes, we need to store the parameters here
 777          * as the other pieces of the struct may not reflect the values we want
 778          * for the watermark calculations. Currently only Haswell uses this.
 779          */
 780         struct intel_plane_wm_parameters wm;
 781
 782         /*
 783          * NOTE: Do not place new plane state fields here (e.g., when adding
 784          * new plane properties).  New runtime state should now be placed in
 785          * the intel_plane_state structure and accessed via plane_state.
 786          */
 787
 788         void (*update_plane)(struct drm_plane *plane,
 789                              const struct intel_crtc_state *crtc_state,
 790                              const struct intel_plane_state *plane_state);
 791         void (*disable_plane)(struct drm_plane *plane,
 792                               struct drm_crtc *crtc);
 793         int (*check_plane)(struct drm_plane *plane,
 794                            struct intel_crtc_state *crtc_state,
 795                            struct intel_plane_state *state);
 796 };
 797
 798 struct intel_watermark_params {
 799         unsigned long fifo_size;
 800         unsigned long max_wm;
 801         unsigned long default_wm;
 802         unsigned long guard_size;
 803         unsigned long cacheline_size;
 804 };
 805
 806 struct cxsr_latency {
 807         int is_desktop;
 808         int is_ddr3;
 809         unsigned long fsb_freq;
 810         unsigned long mem_freq;
 811         unsigned long display_sr;
 812         unsigned long display_hpll_disable;
 813         unsigned long cursor_sr;
 814         unsigned long cursor_hpll_disable;
 815 };
 816
 817 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 818 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 819 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 820 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 821 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 822 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 823 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 824 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 825 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 826
 827 struct intel_hdmi {
 828         i915_reg_t hdmi_reg;
 829         int ddc_bus;
 830         struct {
 831                 enum drm_dp_dual_mode_type type;
 832                 int max_tmds_clock;
 833         } dp_dual_mode;
 834         bool limited_color_range;
 835         bool color_range_auto;
 836         bool has_hdmi_sink;
 837         bool has_audio;
 838         enum hdmi_force_audio force_audio;
 839         bool rgb_quant_range_selectable;
 840         enum hdmi_picture_aspect aspect_ratio;
 841         struct intel_connector *attached_connector;
 842         void (*write_infoframe)(struct drm_encoder *encoder,
 843                                 enum hdmi_infoframe_type type,
 844                                 const void *frame, ssize_t len);
 845         void (*set_infoframes)(struct drm_encoder *encoder,
 846                                bool enable,
 847                                const struct drm_display_mode *adjusted_mode);
 848         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 849                                   const struct intel_crtc_state *pipe_config);
 850 };
 851
 852 struct intel_dp_mst_encoder;
 853 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 854
 855 /*
 856  * enum link_m_n_set:
 857  *      When platform provides two set of M_N registers for dp, we can
 858  *      program them and switch between them incase of DRRS.
 859  *      But When only one such register is provided, we have to program the
 860  *      required divider value on that registers itself based on the DRRS state.
 861  *
 862  * M1_N1        : Program dp_m_n on M1_N1 registers
 863  *                        dp_m2_n2 on M2_N2 registers (If supported)
 864  *
 865  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 866  *                        M2_N2 registers are not supported
 867  */
 868
 869 enum link_m_n_set {
 870         /* Sets the m1_n1 and m2_n2 */
 871         M1_N1 = 0,
 872         M2_N2
 873 };
 874
 875 struct intel_dp {
 876         i915_reg_t output_reg;
 877         i915_reg_t aux_ch_ctl_reg;
 878         i915_reg_t aux_ch_data_reg[5];
 879         uint32_t DP;
 880         int link_rate;
 881         uint8_t lane_count;
 882         uint8_t sink_count;
 883         bool link_mst;
 884         bool has_audio;
 885         bool detect_done;
 886         bool channel_eq_status;
 887         enum hdmi_force_audio force_audio;
 888         bool limited_color_range;
 889         bool color_range_auto;
 890         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 891         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 892         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 893         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 894         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 895         uint8_t num_sink_rates;
 896         int sink_rates[DP_MAX_SUPPORTED_RATES];
 897         struct drm_dp_aux aux;
 898         uint8_t train_set[4];
 899         int panel_power_up_delay;
 900         int panel_power_down_delay;
 901         int panel_power_cycle_delay;
 902         int backlight_on_delay;
 903         int backlight_off_delay;
 904         struct delayed_work panel_vdd_work;
 905         bool want_panel_vdd;
 906         unsigned long last_power_on;
 907         unsigned long last_backlight_off;
 908         ktime_t panel_power_off_time;
 909
 910         struct notifier_block edp_notifier;
 911
 912         /*
 913          * Pipe whose power sequencer is currently locked into
 914          * this port. Only relevant on VLV/CHV.
 915          */
 916         enum pipe pps_pipe;
 917         /*
 918          * Set if the sequencer may be reset due to a power transition,
 919          * requiring a reinitialization. Only relevant on BXT.
 920          */
 921         bool pps_reset;
 922         struct edp_power_seq pps_delays;
 923
 924         bool can_mst; /* this port supports mst */
 925         bool is_mst;
 926         int active_mst_links;
 927         /* connector directly attached - won't be use for modeset in mst world */
 928         struct intel_connector *attached_connector;
 929
 930         /* mst connector list */
 931         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 932         struct drm_dp_mst_topology_mgr mst_mgr;
 933
 934         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 935         /*
 936          * This function returns the value we have to program the AUX_CTL
 937          * register with to kick off an AUX transaction.
 938          */
 939         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 940                                      bool has_aux_irq,
 941                                      int send_bytes,
 942                                      uint32_t aux_clock_divider);
 943
 944         /* This is called before a link training is starterd */
 945         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 946
 947         /* Displayport compliance testing */
 948         unsigned long compliance_test_type;
 949         unsigned long compliance_test_data;
 950         bool compliance_test_active;
 951 };
 952
 953 struct intel_digital_port {
 954         struct intel_encoder base;
 955         enum port port;
 956         u32 saved_port_bits;
 957         struct intel_dp dp;
 958         struct intel_hdmi hdmi;
 959         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 960         bool release_cl2_override;
 961         uint8_t max_lanes;
 962         /* for communication with audio component; protected by av_mutex */
 963         const struct drm_connector *audio_connector;
 964 };
 965
 966 struct intel_dp_mst_encoder {
 967         struct intel_encoder base;
 968         enum pipe pipe;
 969         struct intel_digital_port *primary;
 970         struct intel_connector *connector;
 971 };
 972
 973 static inline enum dpio_channel
 974 vlv_dport_to_channel(struct intel_digital_port *dport)
 975 {
 976         switch (dport->port) {
 977         case PORT_B:
 978         case PORT_D:
 979                 return DPIO_CH0;
 980         case PORT_C:
 981                 return DPIO_CH1;
 982         default:
 983                 BUG();
 984         }
 985 }
 986
 987 static inline enum dpio_phy
 988 vlv_dport_to_phy(struct intel_digital_port *dport)
 989 {
 990         switch (dport->port) {
 991         case PORT_B:
 992         case PORT_C:
 993                 return DPIO_PHY0;
 994         case PORT_D:
 995                 return DPIO_PHY1;
 996         default:
 997                 BUG();
 998         }
 999 }
1000
1001 static inline enum dpio_channel
1002 vlv_pipe_to_channel(enum pipe pipe)
1003 {
1004         switch (pipe) {
1005         case PIPE_A:
1006         case PIPE_C:
1007                 return DPIO_CH0;
1008         case PIPE_B:
1009                 return DPIO_CH1;
1010         default:
1011                 BUG();
1012         }
1013 }
1014
1015 static inline struct drm_crtc *
1016 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
1017 {
1018         struct drm_i915_private *dev_priv = to_i915(dev);
1019         return dev_priv->pipe_to_crtc_mapping[pipe];
1020 }
1021
1022 static inline struct drm_crtc *
1023 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
1024 {
1025         struct drm_i915_private *dev_priv = to_i915(dev);
1026         return dev_priv->plane_to_crtc_mapping[plane];
1027 }
1028
1029 struct intel_flip_work {
1030         struct work_struct unpin_work;
1031         struct work_struct mmio_work;
1032
1033         struct drm_crtc *crtc;
1034         struct drm_framebuffer *old_fb;
1035         struct drm_i915_gem_object *pending_flip_obj;
1036         struct drm_pending_vblank_event *event;
1037         atomic_t pending;
1038         u32 flip_count;
1039         u32 gtt_offset;
1040         struct drm_i915_gem_request *flip_queued_req;
1041         u32 flip_queued_vblank;
1042         u32 flip_ready_vblank;
1043         unsigned int rotation;
1044 };
1045
1046 struct intel_load_detect_pipe {
1047         struct drm_atomic_state *restore_state;
1048 };
1049
1050 static inline struct intel_encoder *
1051 intel_attached_encoder(struct drm_connector *connector)
1052 {
1053         return to_intel_connector(connector)->encoder;
1054 }
1055
1056 static inline struct intel_digital_port *
1057 enc_to_dig_port(struct drm_encoder *encoder)
1058 {
1059         return container_of(encoder, struct intel_digital_port, base.base);
1060 }
1061
1062 static inline struct intel_dp_mst_encoder *
1063 enc_to_mst(struct drm_encoder *encoder)
1064 {
1065         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1066 }
1067
1068 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1069 {
1070         return &enc_to_dig_port(encoder)->dp;
1071 }
1072
1073 static inline struct intel_digital_port *
1074 dp_to_dig_port(struct intel_dp *intel_dp)
1075 {
1076         return container_of(intel_dp, struct intel_digital_port, dp);
1077 }
1078
1079 static inline struct intel_digital_port *
1080 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1081 {
1082         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1083 }
1084
1085 /*
1086  * Returns the number of planes for this pipe, ie the number of sprites + 1
1087  * (primary plane). This doesn't count the cursor plane then.
1088  */
1089 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1090 {
1091         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1092 }
1093
1094 /* intel_fifo_underrun.c */
1095 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1096                                            enum pipe pipe, bool enable);
1097 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1098                                            enum transcoder pch_transcoder,
1099                                            bool enable);
1100 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1101                                          enum pipe pipe);
1102 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1103                                          enum transcoder pch_transcoder);
1104 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1105 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1106
1107 /* i915_irq.c */
1108 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1109 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1110 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1111 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1112 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1113 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1114 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1115 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1116 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1117 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1118 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1119 {
1120         /*
1121          * We only use drm_irq_uninstall() at unload and VT switch, so
1122          * this is the only thing we need to check.
1123          */
1124         return dev_priv->pm.irqs_enabled;
1125 }
1126
1127 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1128 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1129                                      unsigned int pipe_mask);
1130 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1131                                      unsigned int pipe_mask);
1132
1133 /* intel_crt.c */
1134 void intel_crt_init(struct drm_device *dev);
1135 void intel_crt_reset(struct drm_encoder *encoder);
1136
1137 /* intel_ddi.c */
1138 void intel_ddi_clk_select(struct intel_encoder *encoder,
1139                           struct intel_shared_dpll *pll);
1140 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1141                                 struct intel_crtc_state *old_crtc_state,
1142                                 struct drm_connector_state *old_conn_state);
1143 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1144 void hsw_fdi_link_train(struct drm_crtc *crtc);
1145 void intel_ddi_init(struct drm_device *dev, enum port port);
1146 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1147 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1148 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1149 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1150                                        enum transcoder cpu_transcoder);
1151 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1152 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1153 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1154                           struct intel_crtc_state *crtc_state);
1155 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1156 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1157 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1158 void intel_ddi_get_config(struct intel_encoder *encoder,
1159                           struct intel_crtc_state *pipe_config);
1160 struct intel_encoder *
1161 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1162
1163 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1164 void intel_ddi_clock_get(struct intel_encoder *encoder,
1165                          struct intel_crtc_state *pipe_config);
1166 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1167 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1168 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1169                                                   int clock);
1170 unsigned int intel_fb_align_height(struct drm_device *dev,
1171                                    unsigned int height,
1172                                    uint32_t pixel_format,
1173                                    uint64_t fb_format_modifier);
1174 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1175                               uint64_t fb_modifier, uint32_t pixel_format);
1176
1177 /* intel_audio.c */
1178 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1179 void intel_audio_codec_enable(struct intel_encoder *encoder);
1180 void intel_audio_codec_disable(struct intel_encoder *encoder);
1181 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1182 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1183
1184 /* intel_display.c */
1185 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1186 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1187 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1188                       const char *name, u32 reg, int ref_freq);
1189 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1190 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1191 extern const struct drm_plane_funcs intel_plane_funcs;
1192 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1193 unsigned int intel_fb_xy_to_linear(int x, int y,
1194                                    const struct intel_plane_state *state,
1195                                    int plane);
1196 void intel_add_fb_offsets(int *x, int *y,
1197                           const struct intel_plane_state *state, int plane);
1198 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1199 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1200 void intel_mark_busy(struct drm_i915_private *dev_priv);
1201 void intel_mark_idle(struct drm_i915_private *dev_priv);
1202 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1203 int intel_display_suspend(struct drm_device *dev);
1204 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1205 void intel_encoder_destroy(struct drm_encoder *encoder);
1206 int intel_connector_init(struct intel_connector *);
1207 struct intel_connector *intel_connector_alloc(void);
1208 bool intel_connector_get_hw_state(struct intel_connector *connector);
1209 void intel_connector_attach_encoder(struct intel_connector *connector,
1210                                     struct intel_encoder *encoder);
1211 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1212                                              struct drm_crtc *crtc);
1213 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1214 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1215                                 struct drm_file *file_priv);
1216 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1217                                              enum pipe pipe);
1218 static inline bool
1219 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1220                     enum intel_output_type type)
1221 {
1222         return crtc_state->output_types & (1 << type);
1223 }
1224 static inline bool
1225 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1226 {
1227         return crtc_state->output_types &
1228                 ((1 << INTEL_OUTPUT_DP) |
1229                  (1 << INTEL_OUTPUT_DP_MST) |
1230                  (1 << INTEL_OUTPUT_EDP));
1231 }
1232 static inline void
1233 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1234 {
1235         drm_wait_one_vblank(dev, pipe);
1236 }
1237 static inline void
1238 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1239 {
1240         const struct intel_crtc *crtc =
1241                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1242
1243         if (crtc->active)
1244                 intel_wait_for_vblank(dev, pipe);
1245 }
1246
1247 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1248
1249 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1250 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1251                          struct intel_digital_port *dport,
1252                          unsigned int expected_mask);
1253 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1254                                 struct drm_display_mode *mode,
1255                                 struct intel_load_detect_pipe *old,
1256                                 struct drm_modeset_acquire_ctx *ctx);
1257 void intel_release_load_detect_pipe(struct drm_connector *connector,
1258                                     struct intel_load_detect_pipe *old,
1259                                     struct drm_modeset_acquire_ctx *ctx);
1260 struct i915_vma *
1261 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1262 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1263 struct drm_framebuffer *
1264 __intel_framebuffer_create(struct drm_device *dev,
1265                            struct drm_mode_fb_cmd2 *mode_cmd,
1266                            struct drm_i915_gem_object *obj);
1267 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1268 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1269 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1270 int intel_prepare_plane_fb(struct drm_plane *plane,
1271                            struct drm_plane_state *new_state);
1272 void intel_cleanup_plane_fb(struct drm_plane *plane,
1273                             struct drm_plane_state *old_state);
1274 int intel_plane_atomic_get_property(struct drm_plane *plane,
1275                                     const struct drm_plane_state *state,
1276                                     struct drm_property *property,
1277                                     uint64_t *val);
1278 int intel_plane_atomic_set_property(struct drm_plane *plane,
1279                                     struct drm_plane_state *state,
1280                                     struct drm_property *property,
1281                                     uint64_t val);
1282 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1283                                     struct drm_plane_state *plane_state);
1284
1285 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1286                                uint64_t fb_modifier, unsigned int cpp);
1287
1288 static inline bool
1289 intel_rotation_90_or_270(unsigned int rotation)
1290 {
1291         return rotation & (DRM_ROTATE_90 | DRM_ROTATE_270);
1292 }
1293
1294 void intel_create_rotation_property(struct drm_device *dev,
1295                                         struct intel_plane *plane);
1296
1297 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1298                                     enum pipe pipe);
1299
1300 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1301                      const struct dpll *dpll);
1302 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1303 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1304
1305 /* modesetting asserts */
1306 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1307                            enum pipe pipe);
1308 void assert_pll(struct drm_i915_private *dev_priv,
1309                 enum pipe pipe, bool state);
1310 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1311 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1312 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1313 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1314 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1315 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1316                        enum pipe pipe, bool state);
1317 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1318 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1319 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1320 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1321 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1322 u32 intel_compute_tile_offset(int *x, int *y,
1323                               const struct intel_plane_state *state, int plane);
1324 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1325 void intel_finish_reset(struct drm_i915_private *dev_priv);
1326 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1327 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1328 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1329 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1330 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1331 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1332 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1333                             enum dpio_phy phy);
1334 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1335                               enum dpio_phy phy);
1336 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1337 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1338 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1339 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1340 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1341 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1342 unsigned int skl_cdclk_get_vco(unsigned int freq);
1343 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1344 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1345 void intel_dp_get_m_n(struct intel_crtc *crtc,
1346                       struct intel_crtc_state *pipe_config);
1347 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1348 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1349 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1350                         struct dpll *best_clock);
1351 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1352
1353 bool intel_crtc_active(struct drm_crtc *crtc);
1354 void hsw_enable_ips(struct intel_crtc *crtc);
1355 void hsw_disable_ips(struct intel_crtc *crtc);
1356 enum intel_display_power_domain
1357 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1358 enum intel_display_power_domain
1359 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1360 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1361                                  struct intel_crtc_state *pipe_config);
1362
1363 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1364 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1365
1366 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1367
1368 u32 skl_plane_ctl_format(uint32_t pixel_format);
1369 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1370 u32 skl_plane_ctl_rotation(unsigned int rotation);
1371 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1372                      unsigned int rotation);
1373 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1374
1375 /* intel_csr.c */
1376 void intel_csr_ucode_init(struct drm_i915_private *);
1377 void intel_csr_load_program(struct drm_i915_private *);
1378 void intel_csr_ucode_fini(struct drm_i915_private *);
1379 void intel_csr_ucode_suspend(struct drm_i915_private *);
1380 void intel_csr_ucode_resume(struct drm_i915_private *);
1381
1382 /* intel_dp.c */
1383 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1384 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1385                              struct intel_connector *intel_connector);
1386 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1387                               int link_rate, uint8_t lane_count,
1388                               bool link_mst);
1389 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1390 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1391 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1392 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1393 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1394 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1395 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1396 bool intel_dp_compute_config(struct intel_encoder *encoder,
1397                              struct intel_crtc_state *pipe_config,
1398                              struct drm_connector_state *conn_state);
1399 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1400 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1401                                   bool long_hpd);
1402 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1403 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1404 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1405 void intel_edp_panel_on(struct intel_dp *intel_dp);
1406 void intel_edp_panel_off(struct intel_dp *intel_dp);
1407 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1408 void intel_dp_mst_suspend(struct drm_device *dev);
1409 void intel_dp_mst_resume(struct drm_device *dev);
1410 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1411 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1412 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1413 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1414 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1415 void intel_plane_destroy(struct drm_plane *plane);
1416 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1417                            struct intel_crtc_state *crtc_state);
1418 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1419                            struct intel_crtc_state *crtc_state);
1420 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1421                                unsigned int frontbuffer_bits);
1422 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1423                           unsigned int frontbuffer_bits);
1424
1425 void
1426 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1427                                        uint8_t dp_train_pat);
1428 void
1429 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1430 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1431 uint8_t
1432 intel_dp_voltage_max(struct intel_dp *intel_dp);
1433 uint8_t
1434 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1435 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1436                            uint8_t *link_bw, uint8_t *rate_select);
1437 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1438 bool
1439 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1440
1441 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1442 {
1443         return ~((1 << lane_count) - 1) & 0xf;
1444 }
1445
1446 /* intel_dp_aux_backlight.c */
1447 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1448
1449 /* intel_dp_mst.c */
1450 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1451 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1452 /* intel_dsi.c */
1453 void intel_dsi_init(struct drm_device *dev);
1454
1455 /* intel_dsi_dcs_backlight.c */
1456 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1457
1458 /* intel_dvo.c */
1459 void intel_dvo_init(struct drm_device *dev);
1460 /* intel_hotplug.c */
1461 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1462
1463
1464 /* legacy fbdev emulation in intel_fbdev.c */
1465 #ifdef CONFIG_DRM_FBDEV_EMULATION
1466 extern int intel_fbdev_init(struct drm_device *dev);
1467 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1468 extern void intel_fbdev_fini(struct drm_device *dev);
1469 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1470 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1471 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1472 #else
1473 static inline int intel_fbdev_init(struct drm_device *dev)
1474 {
1475         return 0;
1476 }
1477
1478 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1479 {
1480 }
1481
1482 static inline void intel_fbdev_fini(struct drm_device *dev)
1483 {
1484 }
1485
1486 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1487 {
1488 }
1489
1490 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1491 {
1492 }
1493 #endif
1494
1495 /* intel_fbc.c */
1496 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1497                            struct drm_atomic_state *state);
1498 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1499 void intel_fbc_pre_update(struct intel_crtc *crtc,
1500                           struct intel_crtc_state *crtc_state,
1501                           struct intel_plane_state *plane_state);
1502 void intel_fbc_post_update(struct intel_crtc *crtc);
1503 void intel_fbc_init(struct drm_i915_private *dev_priv);
1504 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1505 void intel_fbc_enable(struct intel_crtc *crtc,
1506                       struct intel_crtc_state *crtc_state,
1507                       struct intel_plane_state *plane_state);
1508 void intel_fbc_disable(struct intel_crtc *crtc);
1509 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1510 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1511                           unsigned int frontbuffer_bits,
1512                           enum fb_op_origin origin);
1513 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1514                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1515 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1516
1517 /* intel_hdmi.c */
1518 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1519 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1520                                struct intel_connector *intel_connector);
1521 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1522 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1523                                struct intel_crtc_state *pipe_config,
1524                                struct drm_connector_state *conn_state);
1525 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1526
1527
1528 /* intel_lvds.c */
1529 void intel_lvds_init(struct drm_device *dev);
1530 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1531 bool intel_is_dual_link_lvds(struct drm_device *dev);
1532
1533
1534 /* intel_modes.c */
1535 int intel_connector_update_modes(struct drm_connector *connector,
1536                                  struct edid *edid);
1537 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1538 void intel_attach_force_audio_property(struct drm_connector *connector);
1539 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1540 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1541
1542
1543 /* intel_overlay.c */
1544 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1545 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1546 int intel_overlay_switch_off(struct intel_overlay *overlay);
1547 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1548                                   struct drm_file *file_priv);
1549 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1550                               struct drm_file *file_priv);
1551 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1552
1553
1554 /* intel_panel.c */
1555 int intel_panel_init(struct intel_panel *panel,
1556                      struct drm_display_mode *fixed_mode,
1557                      struct drm_display_mode *downclock_mode);
1558 void intel_panel_fini(struct intel_panel *panel);
1559 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1560                             struct drm_display_mode *adjusted_mode);
1561 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1562                              struct intel_crtc_state *pipe_config,
1563                              int fitting_mode);
1564 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1565                               struct intel_crtc_state *pipe_config,
1566                               int fitting_mode);
1567 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1568                                     u32 level, u32 max);
1569 int intel_panel_setup_backlight(struct drm_connector *connector,
1570                                 enum pipe pipe);
1571 void intel_panel_enable_backlight(struct intel_connector *connector);
1572 void intel_panel_disable_backlight(struct intel_connector *connector);
1573 void intel_panel_destroy_backlight(struct drm_connector *connector);
1574 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1575 extern struct drm_display_mode *intel_find_panel_downclock(
1576                                 struct drm_device *dev,
1577                                 struct drm_display_mode *fixed_mode,
1578                                 struct drm_connector *connector);
1579
1580 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1581 int intel_backlight_device_register(struct intel_connector *connector);
1582 void intel_backlight_device_unregister(struct intel_connector *connector);
1583 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1584 static int intel_backlight_device_register(struct intel_connector *connector)
1585 {
1586         return 0;
1587 }
1588 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1589 {
1590 }
1591 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1592
1593
1594 /* intel_psr.c */
1595 void intel_psr_enable(struct intel_dp *intel_dp);
1596 void intel_psr_disable(struct intel_dp *intel_dp);
1597 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1598                           unsigned frontbuffer_bits);
1599 void intel_psr_flush(struct drm_i915_private *dev_priv,
1600                      unsigned frontbuffer_bits,
1601                      enum fb_op_origin origin);
1602 void intel_psr_init(struct drm_device *dev);
1603 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1604                                    unsigned frontbuffer_bits);
1605
1606 /* intel_runtime_pm.c */
1607 int intel_power_domains_init(struct drm_i915_private *);
1608 void intel_power_domains_fini(struct drm_i915_private *);
1609 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1610 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1611 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1612 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1613 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1614 const char *
1615 intel_display_power_domain_str(enum intel_display_power_domain domain);
1616
1617 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1618                                     enum intel_display_power_domain domain);
1619 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1620                                       enum intel_display_power_domain domain);
1621 void intel_display_power_get(struct drm_i915_private *dev_priv,
1622                              enum intel_display_power_domain domain);
1623 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1624                                         enum intel_display_power_domain domain);
1625 void intel_display_power_put(struct drm_i915_private *dev_priv,
1626                              enum intel_display_power_domain domain);
1627
1628 static inline void
1629 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1630 {
1631         WARN_ONCE(dev_priv->pm.suspended,
1632                   "Device suspended during HW access\n");
1633 }
1634
1635 static inline void
1636 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1637 {
1638         assert_rpm_device_not_suspended(dev_priv);
1639         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1640          * too much noise. */
1641         if (!atomic_read(&dev_priv->pm.wakeref_count))
1642                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1643 }
1644
1645 static inline int
1646 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1647 {
1648         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1649
1650         assert_rpm_wakelock_held(dev_priv);
1651
1652         return seq;
1653 }
1654
1655 static inline void
1656 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1657 {
1658         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1659                   "HW access outside of RPM atomic section\n");
1660 }
1661
1662 /**
1663  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1664  * @dev_priv: i915 device instance
1665  *
1666  * This function disable asserts that check if we hold an RPM wakelock
1667  * reference, while keeping the device-not-suspended checks still enabled.
1668  * It's meant to be used only in special circumstances where our rule about
1669  * the wakelock refcount wrt. the device power state doesn't hold. According
1670  * to this rule at any point where we access the HW or want to keep the HW in
1671  * an active state we must hold an RPM wakelock reference acquired via one of
1672  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1673  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1674  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1675  * users should avoid using this function.
1676  *
1677  * Any calls to this function must have a symmetric call to
1678  * enable_rpm_wakeref_asserts().
1679  */
1680 static inline void
1681 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1682 {
1683         atomic_inc(&dev_priv->pm.wakeref_count);
1684 }
1685
1686 /**
1687  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1688  * @dev_priv: i915 device instance
1689  *
1690  * This function re-enables the RPM assert checks after disabling them with
1691  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1692  * circumstances otherwise its use should be avoided.
1693  *
1694  * Any calls to this function must have a symmetric call to
1695  * disable_rpm_wakeref_asserts().
1696  */
1697 static inline void
1698 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1699 {
1700         atomic_dec(&dev_priv->pm.wakeref_count);
1701 }
1702
1703 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1704 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1705 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1706 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1707
1708 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1709
1710 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1711                              bool override, unsigned int mask);
1712 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1713                           enum dpio_channel ch, bool override);
1714
1715
1716 /* intel_pm.c */
1717 void intel_init_clock_gating(struct drm_device *dev);
1718 void intel_suspend_hw(struct drm_device *dev);
1719 int ilk_wm_max_level(const struct drm_device *dev);
1720 void intel_update_watermarks(struct drm_crtc *crtc);
1721 void intel_init_pm(struct drm_device *dev);
1722 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1723 void intel_pm_setup(struct drm_device *dev);
1724 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1725 void intel_gpu_ips_teardown(void);
1726 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1727 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1728 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1729 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1730 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1731 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1732 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1733 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1734 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1735 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1736 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1737                     struct intel_rps_client *rps,
1738                     unsigned long submitted);
1739 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1740 void vlv_wm_get_hw_state(struct drm_device *dev);
1741 void ilk_wm_get_hw_state(struct drm_device *dev);
1742 void skl_wm_get_hw_state(struct drm_device *dev);
1743 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1744                           struct skl_ddb_allocation *ddb /* out */);
1745 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1746 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1747 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1748 bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
1749                                const struct skl_ddb_allocation *new,
1750                                enum pipe pipe);
1751 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
1752                                  const struct skl_ddb_allocation *old,
1753                                  const struct skl_ddb_allocation *new,
1754                                  enum pipe pipe);
1755 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
1756                          const struct skl_wm_values *wm);
1757 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
1758                         const struct skl_wm_values *wm,
1759                         int plane);
1760 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1761 bool ilk_disable_lp_wm(struct drm_device *dev);
1762 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1763 static inline int intel_enable_rc6(void)
1764 {
1765         return i915.enable_rc6;
1766 }
1767
1768 /* intel_sdvo.c */
1769 bool intel_sdvo_init(struct drm_device *dev,
1770                      i915_reg_t reg, enum port port);
1771
1772
1773 /* intel_sprite.c */
1774 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1775                              int usecs);
1776 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1777 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1778                               struct drm_file *file_priv);
1779 void intel_pipe_update_start(struct intel_crtc *crtc);
1780 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1781
1782 /* intel_tv.c */
1783 void intel_tv_init(struct drm_device *dev);
1784
1785 /* intel_atomic.c */
1786 int intel_connector_atomic_get_property(struct drm_connector *connector,
1787                                         const struct drm_connector_state *state,
1788                                         struct drm_property *property,
1789                                         uint64_t *val);
1790 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1791 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1792                                struct drm_crtc_state *state);
1793 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1794 void intel_atomic_state_clear(struct drm_atomic_state *);
1795 struct intel_shared_dpll_config *
1796 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1797
1798 static inline struct intel_crtc_state *
1799 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1800                             struct intel_crtc *crtc)
1801 {
1802         struct drm_crtc_state *crtc_state;
1803         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1804         if (IS_ERR(crtc_state))
1805                 return ERR_CAST(crtc_state);
1806
1807         return to_intel_crtc_state(crtc_state);
1808 }
1809
1810 static inline struct intel_plane_state *
1811 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1812                                       struct intel_plane *plane)
1813 {
1814         struct drm_plane_state *plane_state;
1815
1816         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1817
1818         return to_intel_plane_state(plane_state);
1819 }
1820
1821 int intel_atomic_setup_scalers(struct drm_device *dev,
1822         struct intel_crtc *intel_crtc,
1823         struct intel_crtc_state *crtc_state);
1824
1825 /* intel_atomic_plane.c */
1826 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1827 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1828 void intel_plane_destroy_state(struct drm_plane *plane,
1829                                struct drm_plane_state *state);
1830 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1831
1832 /* intel_color.c */
1833 void intel_color_init(struct drm_crtc *crtc);
1834 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1835 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1836 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1837
1838 #endif /* __INTEL_DRV_H__ */