f8dc84b2d2d3443dcd47232f013bddb4ae9731f8
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_drv.h
1 /*
2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright (c) 2007-2008 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23  * IN THE SOFTWARE.
24  */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
33 #include "i915_drv.h"
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
42 #include <media/cec-notifier.h>
43
44 /**
45  * __wait_for - magic wait macro
46  *
47  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
48  * important that we check the condition again after having timed out, since the
49  * timeout could be due to preemption or similar and we've never had a chance to
50  * check the condition before the timeout.
51  */
52 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
53         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
54         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
55         int ret__;                                                      \
56         might_sleep();                                                  \
57         for (;;) {                                                      \
58                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
59                 OP;                                                     \
60                 /* Guarantee COND check prior to timeout */             \
61                 barrier();                                              \
62                 if (COND) {                                             \
63                         ret__ = 0;                                      \
64                         break;                                          \
65                 }                                                       \
66                 if (expired__) {                                        \
67                         ret__ = -ETIMEDOUT;                             \
68                         break;                                          \
69                 }                                                       \
70                 usleep_range(wait__, wait__ * 2);                       \
71                 if (wait__ < (Wmax))                                    \
72                         wait__ <<= 1;                                   \
73         }                                                               \
74         ret__;                                                          \
75 })
76
77 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
78                                                    (Wmax))
79 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
80
81 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
82 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
84 #else
85 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
86 #endif
87
88 #define _wait_for_atomic(COND, US, ATOMIC) \
89 ({ \
90         int cpu, ret, timeout = (US) * 1000; \
91         u64 base; \
92         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
93         if (!(ATOMIC)) { \
94                 preempt_disable(); \
95                 cpu = smp_processor_id(); \
96         } \
97         base = local_clock(); \
98         for (;;) { \
99                 u64 now = local_clock(); \
100                 if (!(ATOMIC)) \
101                         preempt_enable(); \
102                 /* Guarantee COND check prior to timeout */ \
103                 barrier(); \
104                 if (COND) { \
105                         ret = 0; \
106                         break; \
107                 } \
108                 if (now - base >= timeout) { \
109                         ret = -ETIMEDOUT; \
110                         break; \
111                 } \
112                 cpu_relax(); \
113                 if (!(ATOMIC)) { \
114                         preempt_disable(); \
115                         if (unlikely(cpu != smp_processor_id())) { \
116                                 timeout -= now - base; \
117                                 cpu = smp_processor_id(); \
118                                 base = local_clock(); \
119                         } \
120                 } \
121         } \
122         ret; \
123 })
124
125 #define wait_for_us(COND, US) \
126 ({ \
127         int ret__; \
128         BUILD_BUG_ON(!__builtin_constant_p(US)); \
129         if ((US) > 10) \
130                 ret__ = _wait_for((COND), (US), 10, 10); \
131         else \
132                 ret__ = _wait_for_atomic((COND), (US), 0); \
133         ret__; \
134 })
135
136 #define wait_for_atomic_us(COND, US) \
137 ({ \
138         BUILD_BUG_ON(!__builtin_constant_p(US)); \
139         BUILD_BUG_ON((US) > 50000); \
140         _wait_for_atomic((COND), (US), 1); \
141 })
142
143 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
144
145 #define KHz(x) (1000 * (x))
146 #define MHz(x) KHz(1000 * (x))
147
148 #define KBps(x) (1000 * (x))
149 #define MBps(x) KBps(1000 * (x))
150 #define GBps(x) ((u64)1000 * MBps((x)))
151
152 /*
153  * Display related stuff
154  */
155
156 /* store information about an Ixxx DVO */
157 /* The i830->i865 use multiple DVOs with multiple i2cs */
158 /* the i915, i945 have a single sDVO i2c bus - which is different */
159 #define MAX_OUTPUTS 6
160 /* maximum connectors per crtcs in the mode set */
161
162 #define INTEL_I2C_BUS_DVO 1
163 #define INTEL_I2C_BUS_SDVO 2
164
165 /* these are outputs from the chip - integrated only
166    external chips are via DVO or SDVO output */
167 enum intel_output_type {
168         INTEL_OUTPUT_UNUSED = 0,
169         INTEL_OUTPUT_ANALOG = 1,
170         INTEL_OUTPUT_DVO = 2,
171         INTEL_OUTPUT_SDVO = 3,
172         INTEL_OUTPUT_LVDS = 4,
173         INTEL_OUTPUT_TVOUT = 5,
174         INTEL_OUTPUT_HDMI = 6,
175         INTEL_OUTPUT_DP = 7,
176         INTEL_OUTPUT_EDP = 8,
177         INTEL_OUTPUT_DSI = 9,
178         INTEL_OUTPUT_DDI = 10,
179         INTEL_OUTPUT_DP_MST = 11,
180 };
181
182 #define INTEL_DVO_CHIP_NONE 0
183 #define INTEL_DVO_CHIP_LVDS 1
184 #define INTEL_DVO_CHIP_TMDS 2
185 #define INTEL_DVO_CHIP_TVOUT 4
186
187 #define INTEL_DSI_VIDEO_MODE    0
188 #define INTEL_DSI_COMMAND_MODE  1
189
190 struct intel_framebuffer {
191         struct drm_framebuffer base;
192         struct intel_rotation_info rot_info;
193
194         /* for each plane in the normal GTT view */
195         struct {
196                 unsigned int x, y;
197         } normal[2];
198         /* for each plane in the rotated GTT view */
199         struct {
200                 unsigned int x, y;
201                 unsigned int pitch; /* pixels */
202         } rotated[2];
203 };
204
205 struct intel_fbdev {
206         struct drm_fb_helper helper;
207         struct intel_framebuffer *fb;
208         struct i915_vma *vma;
209         unsigned long vma_flags;
210         async_cookie_t cookie;
211         int preferred_bpp;
212 };
213
214 struct intel_encoder {
215         struct drm_encoder base;
216
217         enum intel_output_type type;
218         enum port port;
219         unsigned int cloneable;
220         bool (*hotplug)(struct intel_encoder *encoder,
221                         struct intel_connector *connector);
222         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
223                                                       struct intel_crtc_state *,
224                                                       struct drm_connector_state *);
225         bool (*compute_config)(struct intel_encoder *,
226                                struct intel_crtc_state *,
227                                struct drm_connector_state *);
228         void (*pre_pll_enable)(struct intel_encoder *,
229                                const struct intel_crtc_state *,
230                                const struct drm_connector_state *);
231         void (*pre_enable)(struct intel_encoder *,
232                            const struct intel_crtc_state *,
233                            const struct drm_connector_state *);
234         void (*enable)(struct intel_encoder *,
235                        const struct intel_crtc_state *,
236                        const struct drm_connector_state *);
237         void (*disable)(struct intel_encoder *,
238                         const struct intel_crtc_state *,
239                         const struct drm_connector_state *);
240         void (*post_disable)(struct intel_encoder *,
241                              const struct intel_crtc_state *,
242                              const struct drm_connector_state *);
243         void (*post_pll_disable)(struct intel_encoder *,
244                                  const struct intel_crtc_state *,
245                                  const struct drm_connector_state *);
246         /* Read out the current hw state of this connector, returning true if
247          * the encoder is active. If the encoder is enabled it also set the pipe
248          * it is connected to in the pipe parameter. */
249         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
250         /* Reconstructs the equivalent mode flags for the current hardware
251          * state. This must be called _after_ display->get_pipe_config has
252          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
253          * be set correctly before calling this function. */
254         void (*get_config)(struct intel_encoder *,
255                            struct intel_crtc_state *pipe_config);
256         /* Returns a mask of power domains that need to be referenced as part
257          * of the hardware state readout code. */
258         u64 (*get_power_domains)(struct intel_encoder *encoder,
259                                  struct intel_crtc_state *crtc_state);
260         /*
261          * Called during system suspend after all pending requests for the
262          * encoder are flushed (for example for DP AUX transactions) and
263          * device interrupts are disabled.
264          */
265         void (*suspend)(struct intel_encoder *);
266         int crtc_mask;
267         enum hpd_pin hpd_pin;
268         enum intel_display_power_domain power_domain;
269         /* for communication with audio component; protected by av_mutex */
270         const struct drm_connector *audio_connector;
271 };
272
273 struct intel_panel {
274         struct drm_display_mode *fixed_mode;
275         struct drm_display_mode *downclock_mode;
276
277         /* backlight */
278         struct {
279                 bool present;
280                 u32 level;
281                 u32 min;
282                 u32 max;
283                 bool enabled;
284                 bool combination_mode;  /* gen 2/4 only */
285                 bool active_low_pwm;
286                 bool alternate_pwm_increment;   /* lpt+ */
287
288                 /* PWM chip */
289                 bool util_pin_active_low;       /* bxt+ */
290                 u8 controller;          /* bxt+ only */
291                 struct pwm_device *pwm;
292
293                 struct backlight_device *device;
294
295                 /* Connector and platform specific backlight functions */
296                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
297                 uint32_t (*get)(struct intel_connector *connector);
298                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
299                 void (*disable)(const struct drm_connector_state *conn_state);
300                 void (*enable)(const struct intel_crtc_state *crtc_state,
301                                const struct drm_connector_state *conn_state);
302                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
303                                       uint32_t hz);
304                 void (*power)(struct intel_connector *, bool enable);
305         } backlight;
306 };
307
308 struct intel_digital_port;
309
310 /*
311  * This structure serves as a translation layer between the generic HDCP code
312  * and the bus-specific code. What that means is that HDCP over HDMI differs
313  * from HDCP over DP, so to account for these differences, we need to
314  * communicate with the receiver through this shim.
315  *
316  * For completeness, the 2 buses differ in the following ways:
317  *      - DP AUX vs. DDC
318  *              HDCP registers on the receiver are set via DP AUX for DP, and
319  *              they are set via DDC for HDMI.
320  *      - Receiver register offsets
321  *              The offsets of the registers are different for DP vs. HDMI
322  *      - Receiver register masks/offsets
323  *              For instance, the ready bit for the KSV fifo is in a different
324  *              place on DP vs HDMI
325  *      - Receiver register names
326  *              Seriously. In the DP spec, the 16-bit register containing
327  *              downstream information is called BINFO, on HDMI it's called
328  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
329  *              with a completely different definition.
330  *      - KSV FIFO
331  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
332  *              be read 3 keys at a time
333  *      - Aksv output
334  *              Since Aksv is hidden in hardware, there's different procedures
335  *              to send it over DP AUX vs DDC
336  */
337 struct intel_hdcp_shim {
338         /* Outputs the transmitter's An and Aksv values to the receiver. */
339         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
340
341         /* Reads the receiver's key selection vector */
342         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
343
344         /*
345          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
346          * definitions are the same in the respective specs, but the names are
347          * different. Call it BSTATUS since that's the name the HDMI spec
348          * uses and it was there first.
349          */
350         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
351                             u8 *bstatus);
352
353         /* Determines whether a repeater is present downstream */
354         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
355                                 bool *repeater_present);
356
357         /* Reads the receiver's Ri' value */
358         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
359
360         /* Determines if the receiver's KSV FIFO is ready for consumption */
361         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
362                               bool *ksv_ready);
363
364         /* Reads the ksv fifo for num_downstream devices */
365         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
366                              int num_downstream, u8 *ksv_fifo);
367
368         /* Reads a 32-bit part of V' from the receiver */
369         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
370                                  int i, u32 *part);
371
372         /* Enables HDCP signalling on the port */
373         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
374                                  bool enable);
375
376         /* Ensures the link is still protected */
377         bool (*check_link)(struct intel_digital_port *intel_dig_port);
378
379         /* Detects panel's hdcp capability. This is optional for HDMI. */
380         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
381                             bool *hdcp_capable);
382 };
383
384 struct intel_connector {
385         struct drm_connector base;
386         /*
387          * The fixed encoder this connector is connected to.
388          */
389         struct intel_encoder *encoder;
390
391         /* ACPI device id for ACPI and driver cooperation */
392         u32 acpi_device_id;
393
394         /* Reads out the current hw, returning true if the connector is enabled
395          * and active (i.e. dpms ON state). */
396         bool (*get_hw_state)(struct intel_connector *);
397
398         /* Panel info for eDP and LVDS */
399         struct intel_panel panel;
400
401         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
402         struct edid *edid;
403         struct edid *detect_edid;
404
405         /* since POLL and HPD connectors may use the same HPD line keep the native
406            state of connector->polled in case hotplug storm detection changes it */
407         u8 polled;
408
409         void *port; /* store this opaque as its illegal to dereference it */
410
411         struct intel_dp *mst_port;
412
413         /* Work struct to schedule a uevent on link train failure */
414         struct work_struct modeset_retry_work;
415
416         const struct intel_hdcp_shim *hdcp_shim;
417         struct mutex hdcp_mutex;
418         uint64_t hdcp_value; /* protected by hdcp_mutex */
419         struct delayed_work hdcp_check_work;
420         struct work_struct hdcp_prop_work;
421 };
422
423 struct intel_digital_connector_state {
424         struct drm_connector_state base;
425
426         enum hdmi_force_audio force_audio;
427         int broadcast_rgb;
428 };
429
430 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
431
432 struct dpll {
433         /* given values */
434         int n;
435         int m1, m2;
436         int p1, p2;
437         /* derived values */
438         int     dot;
439         int     vco;
440         int     m;
441         int     p;
442 };
443
444 struct intel_atomic_state {
445         struct drm_atomic_state base;
446
447         struct {
448                 /*
449                  * Logical state of cdclk (used for all scaling, watermark,
450                  * etc. calculations and checks). This is computed as if all
451                  * enabled crtcs were active.
452                  */
453                 struct intel_cdclk_state logical;
454
455                 /*
456                  * Actual state of cdclk, can be different from the logical
457                  * state only when all crtc's are DPMS off.
458                  */
459                 struct intel_cdclk_state actual;
460         } cdclk;
461
462         bool dpll_set, modeset;
463
464         /*
465          * Does this transaction change the pipes that are active?  This mask
466          * tracks which CRTC's have changed their active state at the end of
467          * the transaction (not counting the temporary disable during modesets).
468          * This mask should only be non-zero when intel_state->modeset is true,
469          * but the converse is not necessarily true; simply changing a mode may
470          * not flip the final active status of any CRTC's
471          */
472         unsigned int active_pipe_changes;
473
474         unsigned int active_crtcs;
475         /* minimum acceptable cdclk for each pipe */
476         int min_cdclk[I915_MAX_PIPES];
477         /* minimum acceptable voltage level for each pipe */
478         u8 min_voltage_level[I915_MAX_PIPES];
479
480         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
481
482         /*
483          * Current watermarks can't be trusted during hardware readout, so
484          * don't bother calculating intermediate watermarks.
485          */
486         bool skip_intermediate_wm;
487
488         bool rps_interactive;
489
490         /* Gen9+ only */
491         struct skl_ddb_values wm_results;
492
493         struct i915_sw_fence commit_ready;
494
495         struct llist_node freed;
496 };
497
498 struct intel_plane_state {
499         struct drm_plane_state base;
500         struct i915_ggtt_view view;
501         struct i915_vma *vma;
502         unsigned long flags;
503 #define PLANE_HAS_FENCE BIT(0)
504
505         struct {
506                 u32 offset;
507                 /*
508                  * Plane stride in:
509                  * bytes for 0/180 degree rotation
510                  * pixels for 90/270 degree rotation
511                  */
512                 u32 stride;
513                 int x, y;
514         } color_plane[2];
515
516         /* plane control register */
517         u32 ctl;
518
519         /* plane color control register */
520         u32 color_ctl;
521
522         /*
523          * scaler_id
524          *    = -1 : not using a scaler
525          *    >=  0 : using a scalers
526          *
527          * plane requiring a scaler:
528          *   - During check_plane, its bit is set in
529          *     crtc_state->scaler_state.scaler_users by calling helper function
530          *     update_scaler_plane.
531          *   - scaler_id indicates the scaler it got assigned.
532          *
533          * plane doesn't require a scaler:
534          *   - this can happen when scaling is no more required or plane simply
535          *     got disabled.
536          *   - During check_plane, corresponding bit is reset in
537          *     crtc_state->scaler_state.scaler_users by calling helper function
538          *     update_scaler_plane.
539          */
540         int scaler_id;
541
542         struct drm_intel_sprite_colorkey ckey;
543 };
544
545 struct intel_initial_plane_config {
546         struct intel_framebuffer *fb;
547         unsigned int tiling;
548         int size;
549         u32 base;
550 };
551
552 #define SKL_MIN_SRC_W 8
553 #define SKL_MAX_SRC_W 4096
554 #define SKL_MIN_SRC_H 8
555 #define SKL_MAX_SRC_H 4096
556 #define SKL_MIN_DST_W 8
557 #define SKL_MAX_DST_W 4096
558 #define SKL_MIN_DST_H 8
559 #define SKL_MAX_DST_H 4096
560 #define ICL_MAX_SRC_W 5120
561 #define ICL_MAX_SRC_H 4096
562 #define ICL_MAX_DST_W 5120
563 #define ICL_MAX_DST_H 4096
564 #define SKL_MIN_YUV_420_SRC_W 16
565 #define SKL_MIN_YUV_420_SRC_H 16
566
567 struct intel_scaler {
568         int in_use;
569         uint32_t mode;
570 };
571
572 struct intel_crtc_scaler_state {
573 #define SKL_NUM_SCALERS 2
574         struct intel_scaler scalers[SKL_NUM_SCALERS];
575
576         /*
577          * scaler_users: keeps track of users requesting scalers on this crtc.
578          *
579          *     If a bit is set, a user is using a scaler.
580          *     Here user can be a plane or crtc as defined below:
581          *       bits 0-30 - plane (bit position is index from drm_plane_index)
582          *       bit 31    - crtc
583          *
584          * Instead of creating a new index to cover planes and crtc, using
585          * existing drm_plane_index for planes which is well less than 31
586          * planes and bit 31 for crtc. This should be fine to cover all
587          * our platforms.
588          *
589          * intel_atomic_setup_scalers will setup available scalers to users
590          * requesting scalers. It will gracefully fail if request exceeds
591          * avilability.
592          */
593 #define SKL_CRTC_INDEX 31
594         unsigned scaler_users;
595
596         /* scaler used by crtc for panel fitting purpose */
597         int scaler_id;
598 };
599
600 /* drm_mode->private_flags */
601 #define I915_MODE_FLAG_INHERITED 1
602 /* Flag to get scanline using frame time stamps */
603 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
604
605 struct intel_pipe_wm {
606         struct intel_wm_level wm[5];
607         uint32_t linetime;
608         bool fbc_wm_enabled;
609         bool pipe_enabled;
610         bool sprites_enabled;
611         bool sprites_scaled;
612 };
613
614 struct skl_plane_wm {
615         struct skl_wm_level wm[8];
616         struct skl_wm_level uv_wm[8];
617         struct skl_wm_level trans_wm;
618         bool is_planar;
619 };
620
621 struct skl_pipe_wm {
622         struct skl_plane_wm planes[I915_MAX_PLANES];
623         uint32_t linetime;
624 };
625
626 enum vlv_wm_level {
627         VLV_WM_LEVEL_PM2,
628         VLV_WM_LEVEL_PM5,
629         VLV_WM_LEVEL_DDR_DVFS,
630         NUM_VLV_WM_LEVELS,
631 };
632
633 struct vlv_wm_state {
634         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
635         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
636         uint8_t num_levels;
637         bool cxsr;
638 };
639
640 struct vlv_fifo_state {
641         u16 plane[I915_MAX_PLANES];
642 };
643
644 enum g4x_wm_level {
645         G4X_WM_LEVEL_NORMAL,
646         G4X_WM_LEVEL_SR,
647         G4X_WM_LEVEL_HPLL,
648         NUM_G4X_WM_LEVELS,
649 };
650
651 struct g4x_wm_state {
652         struct g4x_pipe_wm wm;
653         struct g4x_sr_wm sr;
654         struct g4x_sr_wm hpll;
655         bool cxsr;
656         bool hpll_en;
657         bool fbc_en;
658 };
659
660 struct intel_crtc_wm_state {
661         union {
662                 struct {
663                         /*
664                          * Intermediate watermarks; these can be
665                          * programmed immediately since they satisfy
666                          * both the current configuration we're
667                          * switching away from and the new
668                          * configuration we're switching to.
669                          */
670                         struct intel_pipe_wm intermediate;
671
672                         /*
673                          * Optimal watermarks, programmed post-vblank
674                          * when this state is committed.
675                          */
676                         struct intel_pipe_wm optimal;
677                 } ilk;
678
679                 struct {
680                         /* gen9+ only needs 1-step wm programming */
681                         struct skl_pipe_wm optimal;
682                         struct skl_ddb_entry ddb;
683                 } skl;
684
685                 struct {
686                         /* "raw" watermarks (not inverted) */
687                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
688                         /* intermediate watermarks (inverted) */
689                         struct vlv_wm_state intermediate;
690                         /* optimal watermarks (inverted) */
691                         struct vlv_wm_state optimal;
692                         /* display FIFO split */
693                         struct vlv_fifo_state fifo_state;
694                 } vlv;
695
696                 struct {
697                         /* "raw" watermarks */
698                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
699                         /* intermediate watermarks */
700                         struct g4x_wm_state intermediate;
701                         /* optimal watermarks */
702                         struct g4x_wm_state optimal;
703                 } g4x;
704         };
705
706         /*
707          * Platforms with two-step watermark programming will need to
708          * update watermark programming post-vblank to switch from the
709          * safe intermediate watermarks to the optimal final
710          * watermarks.
711          */
712         bool need_postvbl_update;
713 };
714
715 struct intel_crtc_state {
716         struct drm_crtc_state base;
717
718         /**
719          * quirks - bitfield with hw state readout quirks
720          *
721          * For various reasons the hw state readout code might not be able to
722          * completely faithfully read out the current state. These cases are
723          * tracked with quirk flags so that fastboot and state checker can act
724          * accordingly.
725          */
726 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
727         unsigned long quirks;
728
729         unsigned fb_bits; /* framebuffers to flip */
730         bool update_pipe; /* can a fast modeset be performed? */
731         bool disable_cxsr;
732         bool update_wm_pre, update_wm_post; /* watermarks are updated */
733         bool fb_changed; /* fb on any of the planes is changed */
734         bool fifo_changed; /* FIFO split is changed */
735
736         /* Pipe source size (ie. panel fitter input size)
737          * All planes will be positioned inside this space,
738          * and get clipped at the edges. */
739         int pipe_src_w, pipe_src_h;
740
741         /*
742          * Pipe pixel rate, adjusted for
743          * panel fitter/pipe scaler downscaling.
744          */
745         unsigned int pixel_rate;
746
747         /* Whether to set up the PCH/FDI. Note that we never allow sharing
748          * between pch encoders and cpu encoders. */
749         bool has_pch_encoder;
750
751         /* Are we sending infoframes on the attached port */
752         bool has_infoframe;
753
754         /* CPU Transcoder for the pipe. Currently this can only differ from the
755          * pipe on Haswell and later (where we have a special eDP transcoder)
756          * and Broxton (where we have special DSI transcoders). */
757         enum transcoder cpu_transcoder;
758
759         /*
760          * Use reduced/limited/broadcast rbg range, compressing from the full
761          * range fed into the crtcs.
762          */
763         bool limited_color_range;
764
765         /* Bitmask of encoder types (enum intel_output_type)
766          * driven by the pipe.
767          */
768         unsigned int output_types;
769
770         /* Whether we should send NULL infoframes. Required for audio. */
771         bool has_hdmi_sink;
772
773         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
774          * has_dp_encoder is set. */
775         bool has_audio;
776
777         /*
778          * Enable dithering, used when the selected pipe bpp doesn't match the
779          * plane bpp.
780          */
781         bool dither;
782
783         /*
784          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
785          * compliance video pattern tests.
786          * Disable dither only if it is a compliance test request for
787          * 18bpp.
788          */
789         bool dither_force_disable;
790
791         /* Controls for the clock computation, to override various stages. */
792         bool clock_set;
793
794         /* SDVO TV has a bunch of special case. To make multifunction encoders
795          * work correctly, we need to track this at runtime.*/
796         bool sdvo_tv_clock;
797
798         /*
799          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
800          * required. This is set in the 2nd loop of calling encoder's
801          * ->compute_config if the first pick doesn't work out.
802          */
803         bool bw_constrained;
804
805         /* Settings for the intel dpll used on pretty much everything but
806          * haswell. */
807         struct dpll dpll;
808
809         /* Selected dpll when shared or NULL. */
810         struct intel_shared_dpll *shared_dpll;
811
812         /* Actual register state of the dpll, for shared dpll cross-checking. */
813         struct intel_dpll_hw_state dpll_hw_state;
814
815         /* DSI PLL registers */
816         struct {
817                 u32 ctrl, div;
818         } dsi_pll;
819
820         int pipe_bpp;
821         struct intel_link_m_n dp_m_n;
822
823         /* m2_n2 for eDP downclock */
824         struct intel_link_m_n dp_m2_n2;
825         bool has_drrs;
826
827         bool has_psr;
828         bool has_psr2;
829
830         /*
831          * Frequence the dpll for the port should run at. Differs from the
832          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
833          * already multiplied by pixel_multiplier.
834          */
835         int port_clock;
836
837         /* Used by SDVO (and if we ever fix it, HDMI). */
838         unsigned pixel_multiplier;
839
840         uint8_t lane_count;
841
842         /*
843          * Used by platforms having DP/HDMI PHY with programmable lane
844          * latency optimization.
845          */
846         uint8_t lane_lat_optim_mask;
847
848         /* minimum acceptable voltage level */
849         u8 min_voltage_level;
850
851         /* Panel fitter controls for gen2-gen4 + VLV */
852         struct {
853                 u32 control;
854                 u32 pgm_ratios;
855                 u32 lvds_border_bits;
856         } gmch_pfit;
857
858         /* Panel fitter placement and size for Ironlake+ */
859         struct {
860                 u32 pos;
861                 u32 size;
862                 bool enabled;
863                 bool force_thru;
864         } pch_pfit;
865
866         /* FDI configuration, only valid if has_pch_encoder is set. */
867         int fdi_lanes;
868         struct intel_link_m_n fdi_m_n;
869
870         bool ips_enabled;
871         bool ips_force_disable;
872
873         bool enable_fbc;
874
875         bool double_wide;
876
877         int pbn;
878
879         struct intel_crtc_scaler_state scaler_state;
880
881         /* w/a for waiting 2 vblanks during crtc enable */
882         enum pipe hsw_workaround_pipe;
883
884         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
885         bool disable_lp_wm;
886
887         struct intel_crtc_wm_state wm;
888
889         /* Gamma mode programmed on the pipe */
890         uint32_t gamma_mode;
891
892         /* bitmask of visible planes (enum plane_id) */
893         u8 active_planes;
894         u8 nv12_planes;
895
896         /* HDMI scrambling status */
897         bool hdmi_scrambling;
898
899         /* HDMI High TMDS char rate ratio */
900         bool hdmi_high_tmds_clock_ratio;
901
902         /* output format is YCBCR 4:2:0 */
903         bool ycbcr420;
904 };
905
906 struct intel_crtc {
907         struct drm_crtc base;
908         enum pipe pipe;
909         /*
910          * Whether the crtc and the connected output pipeline is active. Implies
911          * that crtc->enabled is set, i.e. the current mode configuration has
912          * some outputs connected to this crtc.
913          */
914         bool active;
915         u8 plane_ids_mask;
916         unsigned long long enabled_power_domains;
917         struct intel_overlay *overlay;
918
919         struct intel_crtc_state *config;
920
921         /* global reset count when the last flip was submitted */
922         unsigned int reset_count;
923
924         /* Access to these should be protected by dev_priv->irq_lock. */
925         bool cpu_fifo_underrun_disabled;
926         bool pch_fifo_underrun_disabled;
927
928         /* per-pipe watermark state */
929         struct {
930                 /* watermarks currently being used  */
931                 union {
932                         struct intel_pipe_wm ilk;
933                         struct vlv_wm_state vlv;
934                         struct g4x_wm_state g4x;
935                 } active;
936         } wm;
937
938         int scanline_offset;
939
940         struct {
941                 unsigned start_vbl_count;
942                 ktime_t start_vbl_time;
943                 int min_vbl, max_vbl;
944                 int scanline_start;
945         } debug;
946
947         /* scalers available on this crtc */
948         int num_scalers;
949 };
950
951 struct intel_plane {
952         struct drm_plane base;
953         enum i9xx_plane_id i9xx_plane;
954         enum plane_id id;
955         enum pipe pipe;
956         bool has_fbc;
957         bool has_ccs;
958         uint32_t frontbuffer_bit;
959
960         struct {
961                 u32 base, cntl, size;
962         } cursor;
963
964         /*
965          * NOTE: Do not place new plane state fields here (e.g., when adding
966          * new plane properties).  New runtime state should now be placed in
967          * the intel_plane_state structure and accessed via plane_state.
968          */
969
970         unsigned int (*max_stride)(struct intel_plane *plane,
971                                    u32 pixel_format, u64 modifier,
972                                    unsigned int rotation);
973         void (*update_plane)(struct intel_plane *plane,
974                              const struct intel_crtc_state *crtc_state,
975                              const struct intel_plane_state *plane_state);
976         void (*disable_plane)(struct intel_plane *plane,
977                               struct intel_crtc *crtc);
978         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
979         int (*check_plane)(struct intel_crtc_state *crtc_state,
980                            struct intel_plane_state *plane_state);
981 };
982
983 struct intel_watermark_params {
984         u16 fifo_size;
985         u16 max_wm;
986         u8 default_wm;
987         u8 guard_size;
988         u8 cacheline_size;
989 };
990
991 struct cxsr_latency {
992         bool is_desktop : 1;
993         bool is_ddr3 : 1;
994         u16 fsb_freq;
995         u16 mem_freq;
996         u16 display_sr;
997         u16 display_hpll_disable;
998         u16 cursor_sr;
999         u16 cursor_hpll_disable;
1000 };
1001
1002 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1003 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1004 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1005 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1006 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1007 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1008 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1009 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1010 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1011
1012 struct intel_hdmi {
1013         i915_reg_t hdmi_reg;
1014         int ddc_bus;
1015         struct {
1016                 enum drm_dp_dual_mode_type type;
1017                 int max_tmds_clock;
1018         } dp_dual_mode;
1019         bool has_hdmi_sink;
1020         bool has_audio;
1021         bool rgb_quant_range_selectable;
1022         struct intel_connector *attached_connector;
1023         struct cec_notifier *cec_notifier;
1024 };
1025
1026 struct intel_dp_mst_encoder;
1027 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1028
1029 /*
1030  * enum link_m_n_set:
1031  *      When platform provides two set of M_N registers for dp, we can
1032  *      program them and switch between them incase of DRRS.
1033  *      But When only one such register is provided, we have to program the
1034  *      required divider value on that registers itself based on the DRRS state.
1035  *
1036  * M1_N1        : Program dp_m_n on M1_N1 registers
1037  *                        dp_m2_n2 on M2_N2 registers (If supported)
1038  *
1039  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1040  *                        M2_N2 registers are not supported
1041  */
1042
1043 enum link_m_n_set {
1044         /* Sets the m1_n1 and m2_n2 */
1045         M1_N1 = 0,
1046         M2_N2
1047 };
1048
1049 struct intel_dp_compliance_data {
1050         unsigned long edid;
1051         uint8_t video_pattern;
1052         uint16_t hdisplay, vdisplay;
1053         uint8_t bpc;
1054 };
1055
1056 struct intel_dp_compliance {
1057         unsigned long test_type;
1058         struct intel_dp_compliance_data test_data;
1059         bool test_active;
1060         int test_link_rate;
1061         u8 test_lane_count;
1062 };
1063
1064 struct intel_dp {
1065         i915_reg_t output_reg;
1066         uint32_t DP;
1067         int link_rate;
1068         uint8_t lane_count;
1069         uint8_t sink_count;
1070         bool link_mst;
1071         bool link_trained;
1072         bool has_audio;
1073         bool detect_done;
1074         bool reset_link_params;
1075         enum aux_ch aux_ch;
1076         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1077         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1078         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1079         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1080         /* source rates */
1081         int num_source_rates;
1082         const int *source_rates;
1083         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1084         int num_sink_rates;
1085         int sink_rates[DP_MAX_SUPPORTED_RATES];
1086         bool use_rate_select;
1087         /* intersection of source and sink rates */
1088         int num_common_rates;
1089         int common_rates[DP_MAX_SUPPORTED_RATES];
1090         /* Max lane count for the current link */
1091         int max_link_lane_count;
1092         /* Max rate for the current link */
1093         int max_link_rate;
1094         /* sink or branch descriptor */
1095         struct drm_dp_desc desc;
1096         struct drm_dp_aux aux;
1097         enum intel_display_power_domain aux_power_domain;
1098         uint8_t train_set[4];
1099         int panel_power_up_delay;
1100         int panel_power_down_delay;
1101         int panel_power_cycle_delay;
1102         int backlight_on_delay;
1103         int backlight_off_delay;
1104         struct delayed_work panel_vdd_work;
1105         bool want_panel_vdd;
1106         unsigned long last_power_on;
1107         unsigned long last_backlight_off;
1108         ktime_t panel_power_off_time;
1109
1110         struct notifier_block edp_notifier;
1111
1112         /*
1113          * Pipe whose power sequencer is currently locked into
1114          * this port. Only relevant on VLV/CHV.
1115          */
1116         enum pipe pps_pipe;
1117         /*
1118          * Pipe currently driving the port. Used for preventing
1119          * the use of the PPS for any pipe currentrly driving
1120          * external DP as that will mess things up on VLV.
1121          */
1122         enum pipe active_pipe;
1123         /*
1124          * Set if the sequencer may be reset due to a power transition,
1125          * requiring a reinitialization. Only relevant on BXT.
1126          */
1127         bool pps_reset;
1128         struct edp_power_seq pps_delays;
1129
1130         bool can_mst; /* this port supports mst */
1131         bool is_mst;
1132         int active_mst_links;
1133         /* connector directly attached - won't be use for modeset in mst world */
1134         struct intel_connector *attached_connector;
1135
1136         /* mst connector list */
1137         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1138         struct drm_dp_mst_topology_mgr mst_mgr;
1139
1140         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1141         /*
1142          * This function returns the value we have to program the AUX_CTL
1143          * register with to kick off an AUX transaction.
1144          */
1145         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1146                                      int send_bytes,
1147                                      uint32_t aux_clock_divider);
1148
1149         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1150         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1151
1152         /* This is called before a link training is starterd */
1153         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1154
1155         /* Displayport compliance testing */
1156         struct intel_dp_compliance compliance;
1157 };
1158
1159 struct intel_lspcon {
1160         bool active;
1161         enum drm_lspcon_mode mode;
1162 };
1163
1164 struct intel_digital_port {
1165         struct intel_encoder base;
1166         u32 saved_port_bits;
1167         struct intel_dp dp;
1168         struct intel_hdmi hdmi;
1169         struct intel_lspcon lspcon;
1170         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1171         bool release_cl2_override;
1172         uint8_t max_lanes;
1173         enum intel_display_power_domain ddi_io_power_domain;
1174         enum tc_port_type tc_type;
1175
1176         void (*write_infoframe)(struct drm_encoder *encoder,
1177                                 const struct intel_crtc_state *crtc_state,
1178                                 unsigned int type,
1179                                 const void *frame, ssize_t len);
1180         void (*set_infoframes)(struct drm_encoder *encoder,
1181                                bool enable,
1182                                const struct intel_crtc_state *crtc_state,
1183                                const struct drm_connector_state *conn_state);
1184         bool (*infoframe_enabled)(struct drm_encoder *encoder,
1185                                   const struct intel_crtc_state *pipe_config);
1186 };
1187
1188 struct intel_dp_mst_encoder {
1189         struct intel_encoder base;
1190         enum pipe pipe;
1191         struct intel_digital_port *primary;
1192         struct intel_connector *connector;
1193 };
1194
1195 static inline enum dpio_channel
1196 vlv_dport_to_channel(struct intel_digital_port *dport)
1197 {
1198         switch (dport->base.port) {
1199         case PORT_B:
1200         case PORT_D:
1201                 return DPIO_CH0;
1202         case PORT_C:
1203                 return DPIO_CH1;
1204         default:
1205                 BUG();
1206         }
1207 }
1208
1209 static inline enum dpio_phy
1210 vlv_dport_to_phy(struct intel_digital_port *dport)
1211 {
1212         switch (dport->base.port) {
1213         case PORT_B:
1214         case PORT_C:
1215                 return DPIO_PHY0;
1216         case PORT_D:
1217                 return DPIO_PHY1;
1218         default:
1219                 BUG();
1220         }
1221 }
1222
1223 static inline enum dpio_channel
1224 vlv_pipe_to_channel(enum pipe pipe)
1225 {
1226         switch (pipe) {
1227         case PIPE_A:
1228         case PIPE_C:
1229                 return DPIO_CH0;
1230         case PIPE_B:
1231                 return DPIO_CH1;
1232         default:
1233                 BUG();
1234         }
1235 }
1236
1237 static inline struct intel_crtc *
1238 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1239 {
1240         return dev_priv->pipe_to_crtc_mapping[pipe];
1241 }
1242
1243 static inline struct intel_crtc *
1244 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1245 {
1246         return dev_priv->plane_to_crtc_mapping[plane];
1247 }
1248
1249 struct intel_load_detect_pipe {
1250         struct drm_atomic_state *restore_state;
1251 };
1252
1253 static inline struct intel_encoder *
1254 intel_attached_encoder(struct drm_connector *connector)
1255 {
1256         return to_intel_connector(connector)->encoder;
1257 }
1258
1259 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1260 {
1261         switch (encoder->type) {
1262         case INTEL_OUTPUT_DDI:
1263         case INTEL_OUTPUT_DP:
1264         case INTEL_OUTPUT_EDP:
1265         case INTEL_OUTPUT_HDMI:
1266                 return true;
1267         default:
1268                 return false;
1269         }
1270 }
1271
1272 static inline struct intel_digital_port *
1273 enc_to_dig_port(struct drm_encoder *encoder)
1274 {
1275         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1276
1277         if (intel_encoder_is_dig_port(intel_encoder))
1278                 return container_of(encoder, struct intel_digital_port,
1279                                     base.base);
1280         else
1281                 return NULL;
1282 }
1283
1284 static inline struct intel_dp_mst_encoder *
1285 enc_to_mst(struct drm_encoder *encoder)
1286 {
1287         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1288 }
1289
1290 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1291 {
1292         return &enc_to_dig_port(encoder)->dp;
1293 }
1294
1295 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1296 {
1297         switch (encoder->type) {
1298         case INTEL_OUTPUT_DP:
1299         case INTEL_OUTPUT_EDP:
1300                 return true;
1301         case INTEL_OUTPUT_DDI:
1302                 /* Skip pure HDMI/DVI DDI encoders */
1303                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1304         default:
1305                 return false;
1306         }
1307 }
1308
1309 static inline struct intel_digital_port *
1310 dp_to_dig_port(struct intel_dp *intel_dp)
1311 {
1312         return container_of(intel_dp, struct intel_digital_port, dp);
1313 }
1314
1315 static inline struct intel_lspcon *
1316 dp_to_lspcon(struct intel_dp *intel_dp)
1317 {
1318         return &dp_to_dig_port(intel_dp)->lspcon;
1319 }
1320
1321 static inline struct drm_i915_private *
1322 dp_to_i915(struct intel_dp *intel_dp)
1323 {
1324         return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1325 }
1326
1327 static inline struct intel_digital_port *
1328 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1329 {
1330         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1331 }
1332
1333 static inline struct intel_plane_state *
1334 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1335                                  struct intel_plane *plane)
1336 {
1337         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1338                                                                    &plane->base));
1339 }
1340
1341 static inline struct intel_crtc_state *
1342 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1343                                 struct intel_crtc *crtc)
1344 {
1345         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1346                                                                  &crtc->base));
1347 }
1348
1349 static inline struct intel_crtc_state *
1350 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1351                                 struct intel_crtc *crtc)
1352 {
1353         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1354                                                                  &crtc->base));
1355 }
1356
1357 /* intel_fifo_underrun.c */
1358 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1359                                            enum pipe pipe, bool enable);
1360 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1361                                            enum pipe pch_transcoder,
1362                                            bool enable);
1363 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1364                                          enum pipe pipe);
1365 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1366                                          enum pipe pch_transcoder);
1367 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1368 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1369
1370 /* i915_irq.c */
1371 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1372 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1373 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1374 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1375 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1376 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1377 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1378 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1379
1380 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1381                                             u32 mask)
1382 {
1383         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1384 }
1385
1386 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1387 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1388 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1389 {
1390         /*
1391          * We only use drm_irq_uninstall() at unload and VT switch, so
1392          * this is the only thing we need to check.
1393          */
1394         return dev_priv->runtime_pm.irqs_enabled;
1395 }
1396
1397 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1398 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1399                                      u8 pipe_mask);
1400 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1401                                      u8 pipe_mask);
1402 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1403 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1404 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1405
1406 /* intel_crt.c */
1407 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1408                             i915_reg_t adpa_reg, enum pipe *pipe);
1409 void intel_crt_init(struct drm_i915_private *dev_priv);
1410 void intel_crt_reset(struct drm_encoder *encoder);
1411
1412 /* intel_ddi.c */
1413 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1414                                 const struct intel_crtc_state *old_crtc_state,
1415                                 const struct drm_connector_state *old_conn_state);
1416 void hsw_fdi_link_train(struct intel_crtc *crtc,
1417                         const struct intel_crtc_state *crtc_state);
1418 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1419 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1420 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1421 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1422 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1423 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1424 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1425 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1426 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1427 void intel_ddi_get_config(struct intel_encoder *encoder,
1428                           struct intel_crtc_state *pipe_config);
1429
1430 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1431                                     bool state);
1432 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1433                                          struct intel_crtc_state *crtc_state);
1434 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1435 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1436 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1437 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1438                                  u8 voltage_swing);
1439 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1440                                      bool enable);
1441 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1442                            struct intel_crtc_state *crtc_state,
1443                            struct drm_atomic_state *old_state);
1444 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1445                              struct intel_crtc_state *crtc_state,
1446                              struct drm_atomic_state *old_state);
1447
1448 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1449                                    int color_plane, unsigned int height);
1450
1451 /* intel_audio.c */
1452 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1453 void intel_audio_codec_enable(struct intel_encoder *encoder,
1454                               const struct intel_crtc_state *crtc_state,
1455                               const struct drm_connector_state *conn_state);
1456 void intel_audio_codec_disable(struct intel_encoder *encoder,
1457                                const struct intel_crtc_state *old_crtc_state,
1458                                const struct drm_connector_state *old_conn_state);
1459 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1460 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1461 void intel_audio_init(struct drm_i915_private *dev_priv);
1462 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1463
1464 /* intel_cdclk.c */
1465 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1466 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1467 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1468 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1469 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1470 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1471 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1472 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1473 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1474 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1475 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1476 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1477 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1478 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1479                                const struct intel_cdclk_state *b);
1480 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1481                          const struct intel_cdclk_state *b);
1482 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1483                      const struct intel_cdclk_state *cdclk_state);
1484 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1485                             const char *context);
1486
1487 /* intel_display.c */
1488 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1489 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1490 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1491 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1492 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1493 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1494                       const char *name, u32 reg, int ref_freq);
1495 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1496                            const char *name, u32 reg);
1497 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1498 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1499 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1500 unsigned int intel_fb_xy_to_linear(int x, int y,
1501                                    const struct intel_plane_state *state,
1502                                    int plane);
1503 void intel_add_fb_offsets(int *x, int *y,
1504                           const struct intel_plane_state *state, int plane);
1505 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1506 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1507 void intel_mark_busy(struct drm_i915_private *dev_priv);
1508 void intel_mark_idle(struct drm_i915_private *dev_priv);
1509 int intel_display_suspend(struct drm_device *dev);
1510 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1511 void intel_encoder_destroy(struct drm_encoder *encoder);
1512 int intel_connector_init(struct intel_connector *);
1513 struct intel_connector *intel_connector_alloc(void);
1514 void intel_connector_free(struct intel_connector *connector);
1515 bool intel_connector_get_hw_state(struct intel_connector *connector);
1516 void intel_connector_attach_encoder(struct intel_connector *connector,
1517                                     struct intel_encoder *encoder);
1518 struct drm_display_mode *
1519 intel_encoder_current_mode(struct intel_encoder *encoder);
1520 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1521 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1522 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1523                               enum port port);
1524
1525 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1526 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1527                                       struct drm_file *file_priv);
1528 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1529                                              enum pipe pipe);
1530 static inline bool
1531 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1532                     enum intel_output_type type)
1533 {
1534         return crtc_state->output_types & (1 << type);
1535 }
1536 static inline bool
1537 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1538 {
1539         return crtc_state->output_types &
1540                 ((1 << INTEL_OUTPUT_DP) |
1541                  (1 << INTEL_OUTPUT_DP_MST) |
1542                  (1 << INTEL_OUTPUT_EDP));
1543 }
1544 static inline void
1545 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1546 {
1547         drm_wait_one_vblank(&dev_priv->drm, pipe);
1548 }
1549 static inline void
1550 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1551 {
1552         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1553
1554         if (crtc->active)
1555                 intel_wait_for_vblank(dev_priv, pipe);
1556 }
1557
1558 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1559
1560 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1561 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1562                          struct intel_digital_port *dport,
1563                          unsigned int expected_mask);
1564 int intel_get_load_detect_pipe(struct drm_connector *connector,
1565                                const struct drm_display_mode *mode,
1566                                struct intel_load_detect_pipe *old,
1567                                struct drm_modeset_acquire_ctx *ctx);
1568 void intel_release_load_detect_pipe(struct drm_connector *connector,
1569                                     struct intel_load_detect_pipe *old,
1570                                     struct drm_modeset_acquire_ctx *ctx);
1571 struct i915_vma *
1572 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1573                            const struct i915_ggtt_view *view,
1574                            bool uses_fence,
1575                            unsigned long *out_flags);
1576 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1577 struct drm_framebuffer *
1578 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1579                          struct drm_mode_fb_cmd2 *mode_cmd);
1580 int intel_prepare_plane_fb(struct drm_plane *plane,
1581                            struct drm_plane_state *new_state);
1582 void intel_cleanup_plane_fb(struct drm_plane *plane,
1583                             struct drm_plane_state *old_state);
1584 int intel_plane_atomic_get_property(struct drm_plane *plane,
1585                                     const struct drm_plane_state *state,
1586                                     struct drm_property *property,
1587                                     uint64_t *val);
1588 int intel_plane_atomic_set_property(struct drm_plane *plane,
1589                                     struct drm_plane_state *state,
1590                                     struct drm_property *property,
1591                                     uint64_t val);
1592 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1593                                     struct drm_crtc_state *crtc_state,
1594                                     const struct intel_plane_state *old_plane_state,
1595                                     struct drm_plane_state *plane_state);
1596
1597 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1598                                     enum pipe pipe);
1599
1600 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1601                      const struct dpll *dpll);
1602 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1603 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1604
1605 /* modesetting asserts */
1606 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1607                            enum pipe pipe);
1608 void assert_pll(struct drm_i915_private *dev_priv,
1609                 enum pipe pipe, bool state);
1610 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1611 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1612 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1613 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1614 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1615 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1616                        enum pipe pipe, bool state);
1617 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1618 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1619 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1620 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1621 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1622 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1623 void intel_finish_reset(struct drm_i915_private *dev_priv);
1624 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1625 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1626 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1627 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1628 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1629 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1630 unsigned int skl_cdclk_get_vco(unsigned int freq);
1631 void intel_dp_get_m_n(struct intel_crtc *crtc,
1632                       struct intel_crtc_state *pipe_config);
1633 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1634 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1635 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1636                         struct dpll *best_clock);
1637 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1638
1639 bool intel_crtc_active(struct intel_crtc *crtc);
1640 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1641 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1642 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1643 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1644 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1645                                  struct intel_crtc_state *pipe_config);
1646 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1647                                   struct intel_crtc_state *crtc_state);
1648
1649 u16 skl_scaler_calc_phase(int sub, bool chroma_center);
1650 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1651 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1652                   u32 pixel_format);
1653
1654 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1655 {
1656         return i915_ggtt_offset(state->vma);
1657 }
1658
1659 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1660                         const struct intel_plane_state *plane_state);
1661 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1662                   const struct intel_plane_state *plane_state);
1663 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1664 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1665                      int plane);
1666 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1667 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1668 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1669 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1670                                    u32 pixel_format, u64 modifier,
1671                                    unsigned int rotation);
1672
1673 /* intel_csr.c */
1674 void intel_csr_ucode_init(struct drm_i915_private *);
1675 void intel_csr_load_program(struct drm_i915_private *);
1676 void intel_csr_ucode_fini(struct drm_i915_private *);
1677 void intel_csr_ucode_suspend(struct drm_i915_private *);
1678 void intel_csr_ucode_resume(struct drm_i915_private *);
1679
1680 /* intel_dp.c */
1681 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1682                            i915_reg_t dp_reg, enum port port,
1683                            enum pipe *pipe);
1684 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1685                    enum port port);
1686 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1687                              struct intel_connector *intel_connector);
1688 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1689                               int link_rate, uint8_t lane_count,
1690                               bool link_mst);
1691 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1692                                             int link_rate, uint8_t lane_count);
1693 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1694 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1695 int intel_dp_retrain_link(struct intel_encoder *encoder,
1696                           struct drm_modeset_acquire_ctx *ctx);
1697 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1698 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1699 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1700 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1701 bool intel_dp_compute_config(struct intel_encoder *encoder,
1702                              struct intel_crtc_state *pipe_config,
1703                              struct drm_connector_state *conn_state);
1704 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1705 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1706 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1707                                   bool long_hpd);
1708 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1709                             const struct drm_connector_state *conn_state);
1710 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1711 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1712 void intel_edp_panel_on(struct intel_dp *intel_dp);
1713 void intel_edp_panel_off(struct intel_dp *intel_dp);
1714 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1715 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1716 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1717 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1718 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1719 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1720 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1721 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1722 void intel_plane_destroy(struct drm_plane *plane);
1723 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1724                            const struct intel_crtc_state *crtc_state);
1725 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1726                             const struct intel_crtc_state *crtc_state);
1727 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1728                                unsigned int frontbuffer_bits);
1729 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1730                           unsigned int frontbuffer_bits);
1731 void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
1732 void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port);
1733 void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port);
1734
1735 void
1736 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1737                                        uint8_t dp_train_pat);
1738 void
1739 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1740 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1741 uint8_t
1742 intel_dp_voltage_max(struct intel_dp *intel_dp);
1743 uint8_t
1744 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1745 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1746                            uint8_t *link_bw, uint8_t *rate_select);
1747 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1748 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1749 bool
1750 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1751
1752 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1753 {
1754         return ~((1 << lane_count) - 1) & 0xf;
1755 }
1756
1757 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1758 int intel_dp_link_required(int pixel_clock, int bpp);
1759 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1760 bool intel_digital_port_connected(struct intel_encoder *encoder);
1761
1762 /* intel_dp_aux_backlight.c */
1763 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1764
1765 /* intel_dp_mst.c */
1766 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1767 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1768 /* vlv_dsi.c */
1769 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1770
1771 /* intel_dsi_dcs_backlight.c */
1772 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1773
1774 /* intel_dvo.c */
1775 void intel_dvo_init(struct drm_i915_private *dev_priv);
1776 /* intel_hotplug.c */
1777 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1778 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1779                            struct intel_connector *connector);
1780
1781 /* legacy fbdev emulation in intel_fbdev.c */
1782 #ifdef CONFIG_DRM_FBDEV_EMULATION
1783 extern int intel_fbdev_init(struct drm_device *dev);
1784 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1785 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1786 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1787 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1788 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1789 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1790 #else
1791 static inline int intel_fbdev_init(struct drm_device *dev)
1792 {
1793         return 0;
1794 }
1795
1796 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1797 {
1798 }
1799
1800 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1801 {
1802 }
1803
1804 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1805 {
1806 }
1807
1808 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1809 {
1810 }
1811
1812 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1813 {
1814 }
1815
1816 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1817 {
1818 }
1819 #endif
1820
1821 /* intel_fbc.c */
1822 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1823                            struct intel_atomic_state *state);
1824 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1825 void intel_fbc_pre_update(struct intel_crtc *crtc,
1826                           struct intel_crtc_state *crtc_state,
1827                           struct intel_plane_state *plane_state);
1828 void intel_fbc_post_update(struct intel_crtc *crtc);
1829 void intel_fbc_init(struct drm_i915_private *dev_priv);
1830 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1831 void intel_fbc_enable(struct intel_crtc *crtc,
1832                       struct intel_crtc_state *crtc_state,
1833                       struct intel_plane_state *plane_state);
1834 void intel_fbc_disable(struct intel_crtc *crtc);
1835 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1836 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1837                           unsigned int frontbuffer_bits,
1838                           enum fb_op_origin origin);
1839 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1840                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1841 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1842 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1843 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1844
1845 /* intel_hdmi.c */
1846 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1847                      enum port port);
1848 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1849                                struct intel_connector *intel_connector);
1850 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1851 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1852                                struct intel_crtc_state *pipe_config,
1853                                struct drm_connector_state *conn_state);
1854 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1855                                        struct drm_connector *connector,
1856                                        bool high_tmds_clock_ratio,
1857                                        bool scrambling);
1858 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1859 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1860
1861
1862 /* intel_lvds.c */
1863 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1864                              i915_reg_t lvds_reg, enum pipe *pipe);
1865 void intel_lvds_init(struct drm_i915_private *dev_priv);
1866 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1867 bool intel_is_dual_link_lvds(struct drm_device *dev);
1868
1869
1870 /* intel_modes.c */
1871 int intel_connector_update_modes(struct drm_connector *connector,
1872                                  struct edid *edid);
1873 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1874 void intel_attach_force_audio_property(struct drm_connector *connector);
1875 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1876 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1877
1878
1879 /* intel_overlay.c */
1880 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1881 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1882 int intel_overlay_switch_off(struct intel_overlay *overlay);
1883 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1884                                   struct drm_file *file_priv);
1885 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1886                               struct drm_file *file_priv);
1887 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1888
1889
1890 /* intel_panel.c */
1891 int intel_panel_init(struct intel_panel *panel,
1892                      struct drm_display_mode *fixed_mode,
1893                      struct drm_display_mode *downclock_mode);
1894 void intel_panel_fini(struct intel_panel *panel);
1895 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1896                             struct drm_display_mode *adjusted_mode);
1897 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1898                              struct intel_crtc_state *pipe_config,
1899                              int fitting_mode);
1900 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1901                               struct intel_crtc_state *pipe_config,
1902                               int fitting_mode);
1903 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1904                                     u32 level, u32 max);
1905 int intel_panel_setup_backlight(struct drm_connector *connector,
1906                                 enum pipe pipe);
1907 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1908                                   const struct drm_connector_state *conn_state);
1909 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1910 void intel_panel_destroy_backlight(struct drm_connector *connector);
1911 extern struct drm_display_mode *intel_find_panel_downclock(
1912                                 struct drm_i915_private *dev_priv,
1913                                 struct drm_display_mode *fixed_mode,
1914                                 struct drm_connector *connector);
1915
1916 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1917 int intel_backlight_device_register(struct intel_connector *connector);
1918 void intel_backlight_device_unregister(struct intel_connector *connector);
1919 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1920 static inline int intel_backlight_device_register(struct intel_connector *connector)
1921 {
1922         return 0;
1923 }
1924 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1925 {
1926 }
1927 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1928
1929 /* intel_hdcp.c */
1930 void intel_hdcp_atomic_check(struct drm_connector *connector,
1931                              struct drm_connector_state *old_state,
1932                              struct drm_connector_state *new_state);
1933 int intel_hdcp_init(struct intel_connector *connector,
1934                     const struct intel_hdcp_shim *hdcp_shim);
1935 int intel_hdcp_enable(struct intel_connector *connector);
1936 int intel_hdcp_disable(struct intel_connector *connector);
1937 int intel_hdcp_check_link(struct intel_connector *connector);
1938 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1939
1940 /* intel_psr.c */
1941 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1942 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
1943 void intel_psr_enable(struct intel_dp *intel_dp,
1944                       const struct intel_crtc_state *crtc_state);
1945 void intel_psr_disable(struct intel_dp *intel_dp,
1946                       const struct intel_crtc_state *old_crtc_state);
1947 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
1948                                struct drm_modeset_acquire_ctx *ctx,
1949                                u64 value);
1950 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1951                           unsigned frontbuffer_bits,
1952                           enum fb_op_origin origin);
1953 void intel_psr_flush(struct drm_i915_private *dev_priv,
1954                      unsigned frontbuffer_bits,
1955                      enum fb_op_origin origin);
1956 void intel_psr_init(struct drm_i915_private *dev_priv);
1957 void intel_psr_compute_config(struct intel_dp *intel_dp,
1958                               struct intel_crtc_state *crtc_state);
1959 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
1960 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
1961 void intel_psr_short_pulse(struct intel_dp *intel_dp);
1962 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
1963                             u32 *out_value);
1964
1965 /* intel_runtime_pm.c */
1966 int intel_power_domains_init(struct drm_i915_private *);
1967 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
1968 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1969 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
1970 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
1971 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
1972
1973 enum i915_drm_suspend_mode {
1974         I915_DRM_SUSPEND_IDLE,
1975         I915_DRM_SUSPEND_MEM,
1976         I915_DRM_SUSPEND_HIBERNATE,
1977 };
1978
1979 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
1980                                  enum i915_drm_suspend_mode);
1981 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
1982 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1983 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1984 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1985 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
1986 const char *
1987 intel_display_power_domain_str(enum intel_display_power_domain domain);
1988
1989 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1990                                     enum intel_display_power_domain domain);
1991 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1992                                       enum intel_display_power_domain domain);
1993 void intel_display_power_get(struct drm_i915_private *dev_priv,
1994                              enum intel_display_power_domain domain);
1995 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1996                                         enum intel_display_power_domain domain);
1997 void intel_display_power_put(struct drm_i915_private *dev_priv,
1998                              enum intel_display_power_domain domain);
1999 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2000                             u8 req_slices);
2001
2002 static inline void
2003 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
2004 {
2005         WARN_ONCE(dev_priv->runtime_pm.suspended,
2006                   "Device suspended during HW access\n");
2007 }
2008
2009 static inline void
2010 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
2011 {
2012         assert_rpm_device_not_suspended(dev_priv);
2013         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
2014                   "RPM wakelock ref not held during HW access");
2015 }
2016
2017 /**
2018  * disable_rpm_wakeref_asserts - disable the RPM assert checks
2019  * @dev_priv: i915 device instance
2020  *
2021  * This function disable asserts that check if we hold an RPM wakelock
2022  * reference, while keeping the device-not-suspended checks still enabled.
2023  * It's meant to be used only in special circumstances where our rule about
2024  * the wakelock refcount wrt. the device power state doesn't hold. According
2025  * to this rule at any point where we access the HW or want to keep the HW in
2026  * an active state we must hold an RPM wakelock reference acquired via one of
2027  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2028  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2029  * forcewake release timer, and the GPU RPS and hangcheck works. All other
2030  * users should avoid using this function.
2031  *
2032  * Any calls to this function must have a symmetric call to
2033  * enable_rpm_wakeref_asserts().
2034  */
2035 static inline void
2036 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2037 {
2038         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2039 }
2040
2041 /**
2042  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2043  * @dev_priv: i915 device instance
2044  *
2045  * This function re-enables the RPM assert checks after disabling them with
2046  * disable_rpm_wakeref_asserts. It's meant to be used only in special
2047  * circumstances otherwise its use should be avoided.
2048  *
2049  * Any calls to this function must have a symmetric call to
2050  * disable_rpm_wakeref_asserts().
2051  */
2052 static inline void
2053 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2054 {
2055         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2056 }
2057
2058 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2059 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2060 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2061 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2062
2063 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2064                              bool override, unsigned int mask);
2065 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2066                           enum dpio_channel ch, bool override);
2067
2068
2069 /* intel_pm.c */
2070 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2071 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2072 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2073 void intel_update_watermarks(struct intel_crtc *crtc);
2074 void intel_init_pm(struct drm_i915_private *dev_priv);
2075 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2076 void intel_pm_setup(struct drm_i915_private *dev_priv);
2077 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2078 void intel_gpu_ips_teardown(void);
2079 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2080 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2081 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2082 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2083 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2084 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2085 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2086 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2087 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2088 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2089 void g4x_wm_get_hw_state(struct drm_device *dev);
2090 void vlv_wm_get_hw_state(struct drm_device *dev);
2091 void ilk_wm_get_hw_state(struct drm_device *dev);
2092 void skl_wm_get_hw_state(struct drm_device *dev);
2093 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2094                           struct skl_ddb_allocation *ddb /* out */);
2095 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2096                               struct skl_pipe_wm *out);
2097 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2098 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2099 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2100 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2101 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2102 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2103                          const struct skl_wm_level *l2);
2104 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2105                                  const struct skl_ddb_entry **entries,
2106                                  const struct skl_ddb_entry *ddb,
2107                                  int ignore);
2108 bool ilk_disable_lp_wm(struct drm_device *dev);
2109 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2110                                   struct intel_crtc_state *cstate);
2111 void intel_init_ipc(struct drm_i915_private *dev_priv);
2112 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2113
2114 /* intel_sdvo.c */
2115 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2116                              i915_reg_t sdvo_reg, enum pipe *pipe);
2117 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2118                      i915_reg_t reg, enum port port);
2119
2120
2121 /* intel_sprite.c */
2122 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2123                              int usecs);
2124 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2125                                               enum pipe pipe, int plane);
2126 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2127                                     struct drm_file *file_priv);
2128 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2129 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2130 void skl_update_plane(struct intel_plane *plane,
2131                       const struct intel_crtc_state *crtc_state,
2132                       const struct intel_plane_state *plane_state);
2133 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2134 bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe);
2135 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2136                        enum pipe pipe, enum plane_id plane_id);
2137 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2138                           enum pipe pipe, enum plane_id plane_id);
2139 unsigned int skl_plane_max_stride(struct intel_plane *plane,
2140                                   u32 pixel_format, u64 modifier,
2141                                   unsigned int rotation);
2142 int skl_plane_check(struct intel_crtc_state *crtc_state,
2143                     struct intel_plane_state *plane_state);
2144 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2145 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2146 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2147
2148 /* intel_tv.c */
2149 void intel_tv_init(struct drm_i915_private *dev_priv);
2150
2151 /* intel_atomic.c */
2152 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2153                                                 const struct drm_connector_state *state,
2154                                                 struct drm_property *property,
2155                                                 uint64_t *val);
2156 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2157                                                 struct drm_connector_state *state,
2158                                                 struct drm_property *property,
2159                                                 uint64_t val);
2160 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2161                                          struct drm_connector_state *new_state);
2162 struct drm_connector_state *
2163 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2164
2165 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2166 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2167                                struct drm_crtc_state *state);
2168 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2169 void intel_atomic_state_clear(struct drm_atomic_state *);
2170
2171 static inline struct intel_crtc_state *
2172 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2173                             struct intel_crtc *crtc)
2174 {
2175         struct drm_crtc_state *crtc_state;
2176         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2177         if (IS_ERR(crtc_state))
2178                 return ERR_CAST(crtc_state);
2179
2180         return to_intel_crtc_state(crtc_state);
2181 }
2182
2183 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2184                                struct intel_crtc *intel_crtc,
2185                                struct intel_crtc_state *crtc_state);
2186
2187 /* intel_atomic_plane.c */
2188 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2189 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2190 void intel_plane_destroy_state(struct drm_plane *plane,
2191                                struct drm_plane_state *state);
2192 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2193 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2194                                         struct intel_crtc_state *crtc_state,
2195                                         const struct intel_plane_state *old_plane_state,
2196                                         struct intel_plane_state *intel_state);
2197
2198 /* intel_color.c */
2199 void intel_color_init(struct drm_crtc *crtc);
2200 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2201 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2202 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2203
2204 /* intel_lspcon.c */
2205 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2206 void lspcon_resume(struct intel_lspcon *lspcon);
2207 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2208
2209 /* intel_pipe_crc.c */
2210 #ifdef CONFIG_DEBUG_FS
2211 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2212 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2213                                  const char *source_name, size_t *values_cnt);
2214 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2215                                               size_t *count);
2216 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2217 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2218 #else
2219 #define intel_crtc_set_crc_source NULL
2220 #define intel_crtc_verify_crc_source NULL
2221 #define intel_crtc_get_crc_sources NULL
2222 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2223 {
2224 }
2225
2226 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2227 {
2228 }
2229 #endif
2230 #endif /* __INTEL_DRV_H__ */