drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42 #include <media/cec-notifier.h>
  43
  44 /**
  45  * __wait_for - magic wait macro
  46  *
  47  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  48  * important that we check the condition again after having timed out, since the
  49  * timeout could be due to preemption or similar and we've never had a chance to
  50  * check the condition before the timeout.
  51  */
  52 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  53         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  54         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  55         int ret__;                                                      \
  56         might_sleep();                                                  \
  57         for (;;) {                                                      \
  58                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  59                 OP;                                                     \
  60                 /* Guarantee COND check prior to timeout */             \
  61                 barrier();                                              \
  62                 if (COND) {                                             \
  63                         ret__ = 0;                                      \
  64                         break;                                          \
  65                 }                                                       \
  66                 if (expired__) {                                        \
  67                         ret__ = -ETIMEDOUT;                             \
  68                         break;                                          \
  69                 }                                                       \
  70                 usleep_range(wait__, wait__ * 2);                       \
  71                 if (wait__ < (Wmax))                                    \
  72                         wait__ <<= 1;                                   \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  78                                                    (Wmax))
  79 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  80
  81 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  82 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  84 #else
  85 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  86 #endif
  87
  88 #define _wait_for_atomic(COND, US, ATOMIC) \
  89 ({ \
  90         int cpu, ret, timeout = (US) * 1000; \
  91         u64 base; \
  92         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  93         if (!(ATOMIC)) { \
  94                 preempt_disable(); \
  95                 cpu = smp_processor_id(); \
  96         } \
  97         base = local_clock(); \
  98         for (;;) { \
  99                 u64 now = local_clock(); \
 100                 if (!(ATOMIC)) \
 101                         preempt_enable(); \
 102                 /* Guarantee COND check prior to timeout */ \
 103                 barrier(); \
 104                 if (COND) { \
 105                         ret = 0; \
 106                         break; \
 107                 } \
 108                 if (now - base >= timeout) { \
 109                         ret = -ETIMEDOUT; \
 110                         break; \
 111                 } \
 112                 cpu_relax(); \
 113                 if (!(ATOMIC)) { \
 114                         preempt_disable(); \
 115                         if (unlikely(cpu != smp_processor_id())) { \
 116                                 timeout -= now - base; \
 117                                 cpu = smp_processor_id(); \
 118                                 base = local_clock(); \
 119                         } \
 120                 } \
 121         } \
 122         ret; \
 123 })
 124
 125 #define wait_for_us(COND, US) \
 126 ({ \
 127         int ret__; \
 128         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 129         if ((US) > 10) \
 130                 ret__ = _wait_for((COND), (US), 10, 10); \
 131         else \
 132                 ret__ = _wait_for_atomic((COND), (US), 0); \
 133         ret__; \
 134 })
 135
 136 #define wait_for_atomic_us(COND, US) \
 137 ({ \
 138         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 139         BUILD_BUG_ON((US) > 50000); \
 140         _wait_for_atomic((COND), (US), 1); \
 141 })
 142
 143 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 144
 145 #define KHz(x) (1000 * (x))
 146 #define MHz(x) KHz(1000 * (x))
 147
 148 #define KBps(x) (1000 * (x))
 149 #define MBps(x) KBps(1000 * (x))
 150 #define GBps(x) ((u64)1000 * MBps((x)))
 151
 152 /*
 153  * Display related stuff
 154  */
 155
 156 /* store information about an Ixxx DVO */
 157 /* The i830->i865 use multiple DVOs with multiple i2cs */
 158 /* the i915, i945 have a single sDVO i2c bus - which is different */
 159 #define MAX_OUTPUTS 6
 160 /* maximum connectors per crtcs in the mode set */
 161
 162 #define INTEL_I2C_BUS_DVO 1
 163 #define INTEL_I2C_BUS_SDVO 2
 164
 165 /* these are outputs from the chip - integrated only
 166    external chips are via DVO or SDVO output */
 167 enum intel_output_type {
 168         INTEL_OUTPUT_UNUSED = 0,
 169         INTEL_OUTPUT_ANALOG = 1,
 170         INTEL_OUTPUT_DVO = 2,
 171         INTEL_OUTPUT_SDVO = 3,
 172         INTEL_OUTPUT_LVDS = 4,
 173         INTEL_OUTPUT_TVOUT = 5,
 174         INTEL_OUTPUT_HDMI = 6,
 175         INTEL_OUTPUT_DP = 7,
 176         INTEL_OUTPUT_EDP = 8,
 177         INTEL_OUTPUT_DSI = 9,
 178         INTEL_OUTPUT_DDI = 10,
 179         INTEL_OUTPUT_DP_MST = 11,
 180 };
 181
 182 #define INTEL_DVO_CHIP_NONE 0
 183 #define INTEL_DVO_CHIP_LVDS 1
 184 #define INTEL_DVO_CHIP_TMDS 2
 185 #define INTEL_DVO_CHIP_TVOUT 4
 186
 187 #define INTEL_DSI_VIDEO_MODE    0
 188 #define INTEL_DSI_COMMAND_MODE  1
 189
 190 struct intel_framebuffer {
 191         struct drm_framebuffer base;
 192         struct intel_rotation_info rot_info;
 193
 194         /* for each plane in the normal GTT view */
 195         struct {
 196                 unsigned int x, y;
 197         } normal[2];
 198         /* for each plane in the rotated GTT view */
 199         struct {
 200                 unsigned int x, y;
 201                 unsigned int pitch; /* pixels */
 202         } rotated[2];
 203 };
 204
 205 struct intel_fbdev {
 206         struct drm_fb_helper helper;
 207         struct intel_framebuffer *fb;
 208         struct i915_vma *vma;
 209         unsigned long vma_flags;
 210         async_cookie_t cookie;
 211         int preferred_bpp;
 212
 213         /* Whether or not fbdev hpd processing is temporarily suspended */
 214         bool hpd_suspended : 1;
 215         /* Set when a hotplug was received while HPD processing was
 216          * suspended
 217          */
 218         bool hpd_waiting : 1;
 219
 220         /* Protects hpd_suspended */
 221         struct mutex hpd_lock;
 222 };
 223
 224 struct intel_encoder {
 225         struct drm_encoder base;
 226
 227         enum intel_output_type type;
 228         enum port port;
 229         unsigned int cloneable;
 230         bool (*hotplug)(struct intel_encoder *encoder,
 231                         struct intel_connector *connector);
 232         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 233                                                       struct intel_crtc_state *,
 234                                                       struct drm_connector_state *);
 235         bool (*compute_config)(struct intel_encoder *,
 236                                struct intel_crtc_state *,
 237                                struct drm_connector_state *);
 238         void (*pre_pll_enable)(struct intel_encoder *,
 239                                const struct intel_crtc_state *,
 240                                const struct drm_connector_state *);
 241         void (*pre_enable)(struct intel_encoder *,
 242                            const struct intel_crtc_state *,
 243                            const struct drm_connector_state *);
 244         void (*enable)(struct intel_encoder *,
 245                        const struct intel_crtc_state *,
 246                        const struct drm_connector_state *);
 247         void (*disable)(struct intel_encoder *,
 248                         const struct intel_crtc_state *,
 249                         const struct drm_connector_state *);
 250         void (*post_disable)(struct intel_encoder *,
 251                              const struct intel_crtc_state *,
 252                              const struct drm_connector_state *);
 253         void (*post_pll_disable)(struct intel_encoder *,
 254                                  const struct intel_crtc_state *,
 255                                  const struct drm_connector_state *);
 256         /* Read out the current hw state of this connector, returning true if
 257          * the encoder is active. If the encoder is enabled it also set the pipe
 258          * it is connected to in the pipe parameter. */
 259         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 260         /* Reconstructs the equivalent mode flags for the current hardware
 261          * state. This must be called _after_ display->get_pipe_config has
 262          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 263          * be set correctly before calling this function. */
 264         void (*get_config)(struct intel_encoder *,
 265                            struct intel_crtc_state *pipe_config);
 266         /* Returns a mask of power domains that need to be referenced as part
 267          * of the hardware state readout code. */
 268         u64 (*get_power_domains)(struct intel_encoder *encoder,
 269                                  struct intel_crtc_state *crtc_state);
 270         /*
 271          * Called during system suspend after all pending requests for the
 272          * encoder are flushed (for example for DP AUX transactions) and
 273          * device interrupts are disabled.
 274          */
 275         void (*suspend)(struct intel_encoder *);
 276         int crtc_mask;
 277         enum hpd_pin hpd_pin;
 278         enum intel_display_power_domain power_domain;
 279         /* for communication with audio component; protected by av_mutex */
 280         const struct drm_connector *audio_connector;
 281 };
 282
 283 struct intel_panel {
 284         struct drm_display_mode *fixed_mode;
 285         struct drm_display_mode *downclock_mode;
 286
 287         /* backlight */
 288         struct {
 289                 bool present;
 290                 u32 level;
 291                 u32 min;
 292                 u32 max;
 293                 bool enabled;
 294                 bool combination_mode;  /* gen 2/4 only */
 295                 bool active_low_pwm;
 296                 bool alternate_pwm_increment;   /* lpt+ */
 297
 298                 /* PWM chip */
 299                 bool util_pin_active_low;       /* bxt+ */
 300                 u8 controller;          /* bxt+ only */
 301                 struct pwm_device *pwm;
 302
 303                 struct backlight_device *device;
 304
 305                 /* Connector and platform specific backlight functions */
 306                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 307                 uint32_t (*get)(struct intel_connector *connector);
 308                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 309                 void (*disable)(const struct drm_connector_state *conn_state);
 310                 void (*enable)(const struct intel_crtc_state *crtc_state,
 311                                const struct drm_connector_state *conn_state);
 312                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 313                                       uint32_t hz);
 314                 void (*power)(struct intel_connector *, bool enable);
 315         } backlight;
 316 };
 317
 318 struct intel_digital_port;
 319
 320 /*
 321  * This structure serves as a translation layer between the generic HDCP code
 322  * and the bus-specific code. What that means is that HDCP over HDMI differs
 323  * from HDCP over DP, so to account for these differences, we need to
 324  * communicate with the receiver through this shim.
 325  *
 326  * For completeness, the 2 buses differ in the following ways:
 327  *      - DP AUX vs. DDC
 328  *              HDCP registers on the receiver are set via DP AUX for DP, and
 329  *              they are set via DDC for HDMI.
 330  *      - Receiver register offsets
 331  *              The offsets of the registers are different for DP vs. HDMI
 332  *      - Receiver register masks/offsets
 333  *              For instance, the ready bit for the KSV fifo is in a different
 334  *              place on DP vs HDMI
 335  *      - Receiver register names
 336  *              Seriously. In the DP spec, the 16-bit register containing
 337  *              downstream information is called BINFO, on HDMI it's called
 338  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 339  *              with a completely different definition.
 340  *      - KSV FIFO
 341  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 342  *              be read 3 keys at a time
 343  *      - Aksv output
 344  *              Since Aksv is hidden in hardware, there's different procedures
 345  *              to send it over DP AUX vs DDC
 346  */
 347 struct intel_hdcp_shim {
 348         /* Outputs the transmitter's An and Aksv values to the receiver. */
 349         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 350
 351         /* Reads the receiver's key selection vector */
 352         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 353
 354         /*
 355          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 356          * definitions are the same in the respective specs, but the names are
 357          * different. Call it BSTATUS since that's the name the HDMI spec
 358          * uses and it was there first.
 359          */
 360         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 361                             u8 *bstatus);
 362
 363         /* Determines whether a repeater is present downstream */
 364         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 365                                 bool *repeater_present);
 366
 367         /* Reads the receiver's Ri' value */
 368         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 369
 370         /* Determines if the receiver's KSV FIFO is ready for consumption */
 371         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 372                               bool *ksv_ready);
 373
 374         /* Reads the ksv fifo for num_downstream devices */
 375         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 376                              int num_downstream, u8 *ksv_fifo);
 377
 378         /* Reads a 32-bit part of V' from the receiver */
 379         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 380                                  int i, u32 *part);
 381
 382         /* Enables HDCP signalling on the port */
 383         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 384                                  bool enable);
 385
 386         /* Ensures the link is still protected */
 387         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 388
 389         /* Detects panel's hdcp capability. This is optional for HDMI. */
 390         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 391                             bool *hdcp_capable);
 392 };
 393
 394 struct intel_hdcp {
 395         const struct intel_hdcp_shim *shim;
 396         /* Mutex for hdcp state of the connector */
 397         struct mutex mutex;
 398         u64 value;
 399         struct delayed_work check_work;
 400         struct work_struct prop_work;
 401 };
 402
 403 struct intel_connector {
 404         struct drm_connector base;
 405         /*
 406          * The fixed encoder this connector is connected to.
 407          */
 408         struct intel_encoder *encoder;
 409
 410         /* ACPI device id for ACPI and driver cooperation */
 411         u32 acpi_device_id;
 412
 413         /* Reads out the current hw, returning true if the connector is enabled
 414          * and active (i.e. dpms ON state). */
 415         bool (*get_hw_state)(struct intel_connector *);
 416
 417         /* Panel info for eDP and LVDS */
 418         struct intel_panel panel;
 419
 420         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 421         struct edid *edid;
 422         struct edid *detect_edid;
 423
 424         /* since POLL and HPD connectors may use the same HPD line keep the native
 425            state of connector->polled in case hotplug storm detection changes it */
 426         u8 polled;
 427
 428         void *port; /* store this opaque as its illegal to dereference it */
 429
 430         struct intel_dp *mst_port;
 431
 432         /* Work struct to schedule a uevent on link train failure */
 433         struct work_struct modeset_retry_work;
 434
 435         struct intel_hdcp hdcp;
 436 };
 437
 438 struct intel_digital_connector_state {
 439         struct drm_connector_state base;
 440
 441         enum hdmi_force_audio force_audio;
 442         int broadcast_rgb;
 443 };
 444
 445 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 446
 447 struct dpll {
 448         /* given values */
 449         int n;
 450         int m1, m2;
 451         int p1, p2;
 452         /* derived values */
 453         int     dot;
 454         int     vco;
 455         int     m;
 456         int     p;
 457 };
 458
 459 struct intel_atomic_state {
 460         struct drm_atomic_state base;
 461
 462         struct {
 463                 /*
 464                  * Logical state of cdclk (used for all scaling, watermark,
 465                  * etc. calculations and checks). This is computed as if all
 466                  * enabled crtcs were active.
 467                  */
 468                 struct intel_cdclk_state logical;
 469
 470                 /*
 471                  * Actual state of cdclk, can be different from the logical
 472                  * state only when all crtc's are DPMS off.
 473                  */
 474                 struct intel_cdclk_state actual;
 475         } cdclk;
 476
 477         bool dpll_set, modeset;
 478
 479         /*
 480          * Does this transaction change the pipes that are active?  This mask
 481          * tracks which CRTC's have changed their active state at the end of
 482          * the transaction (not counting the temporary disable during modesets).
 483          * This mask should only be non-zero when intel_state->modeset is true,
 484          * but the converse is not necessarily true; simply changing a mode may
 485          * not flip the final active status of any CRTC's
 486          */
 487         unsigned int active_pipe_changes;
 488
 489         unsigned int active_crtcs;
 490         /* minimum acceptable cdclk for each pipe */
 491         int min_cdclk[I915_MAX_PIPES];
 492         /* minimum acceptable voltage level for each pipe */
 493         u8 min_voltage_level[I915_MAX_PIPES];
 494
 495         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 496
 497         /*
 498          * Current watermarks can't be trusted during hardware readout, so
 499          * don't bother calculating intermediate watermarks.
 500          */
 501         bool skip_intermediate_wm;
 502
 503         bool rps_interactive;
 504
 505         /* Gen9+ only */
 506         struct skl_ddb_values wm_results;
 507
 508         struct i915_sw_fence commit_ready;
 509
 510         struct llist_node freed;
 511 };
 512
 513 struct intel_plane_state {
 514         struct drm_plane_state base;
 515         struct i915_ggtt_view view;
 516         struct i915_vma *vma;
 517         unsigned long flags;
 518 #define PLANE_HAS_FENCE BIT(0)
 519
 520         struct {
 521                 u32 offset;
 522                 /*
 523                  * Plane stride in:
 524                  * bytes for 0/180 degree rotation
 525                  * pixels for 90/270 degree rotation
 526                  */
 527                 u32 stride;
 528                 int x, y;
 529         } color_plane[2];
 530
 531         /* plane control register */
 532         u32 ctl;
 533
 534         /* plane color control register */
 535         u32 color_ctl;
 536
 537         /*
 538          * scaler_id
 539          *    = -1 : not using a scaler
 540          *    >=  0 : using a scalers
 541          *
 542          * plane requiring a scaler:
 543          *   - During check_plane, its bit is set in
 544          *     crtc_state->scaler_state.scaler_users by calling helper function
 545          *     update_scaler_plane.
 546          *   - scaler_id indicates the scaler it got assigned.
 547          *
 548          * plane doesn't require a scaler:
 549          *   - this can happen when scaling is no more required or plane simply
 550          *     got disabled.
 551          *   - During check_plane, corresponding bit is reset in
 552          *     crtc_state->scaler_state.scaler_users by calling helper function
 553          *     update_scaler_plane.
 554          */
 555         int scaler_id;
 556
 557         /*
 558          * linked_plane:
 559          *
 560          * ICL planar formats require 2 planes that are updated as pairs.
 561          * This member is used to make sure the other plane is also updated
 562          * when required, and for update_slave() to find the correct
 563          * plane_state to pass as argument.
 564          */
 565         struct intel_plane *linked_plane;
 566
 567         /*
 568          * slave:
 569          * If set don't update use the linked plane's state for updating
 570          * this plane during atomic commit with the update_slave() callback.
 571          *
 572          * It's also used by the watermark code to ignore wm calculations on
 573          * this plane. They're calculated by the linked plane's wm code.
 574          */
 575         u32 slave;
 576
 577         struct drm_intel_sprite_colorkey ckey;
 578 };
 579
 580 struct intel_initial_plane_config {
 581         struct intel_framebuffer *fb;
 582         unsigned int tiling;
 583         int size;
 584         u32 base;
 585         u8 rotation;
 586 };
 587
 588 #define SKL_MIN_SRC_W 8
 589 #define SKL_MAX_SRC_W 4096
 590 #define SKL_MIN_SRC_H 8
 591 #define SKL_MAX_SRC_H 4096
 592 #define SKL_MIN_DST_W 8
 593 #define SKL_MAX_DST_W 4096
 594 #define SKL_MIN_DST_H 8
 595 #define SKL_MAX_DST_H 4096
 596 #define ICL_MAX_SRC_W 5120
 597 #define ICL_MAX_SRC_H 4096
 598 #define ICL_MAX_DST_W 5120
 599 #define ICL_MAX_DST_H 4096
 600 #define SKL_MIN_YUV_420_SRC_W 16
 601 #define SKL_MIN_YUV_420_SRC_H 16
 602
 603 struct intel_scaler {
 604         int in_use;
 605         uint32_t mode;
 606 };
 607
 608 struct intel_crtc_scaler_state {
 609 #define SKL_NUM_SCALERS 2
 610         struct intel_scaler scalers[SKL_NUM_SCALERS];
 611
 612         /*
 613          * scaler_users: keeps track of users requesting scalers on this crtc.
 614          *
 615          *     If a bit is set, a user is using a scaler.
 616          *     Here user can be a plane or crtc as defined below:
 617          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 618          *       bit 31    - crtc
 619          *
 620          * Instead of creating a new index to cover planes and crtc, using
 621          * existing drm_plane_index for planes which is well less than 31
 622          * planes and bit 31 for crtc. This should be fine to cover all
 623          * our platforms.
 624          *
 625          * intel_atomic_setup_scalers will setup available scalers to users
 626          * requesting scalers. It will gracefully fail if request exceeds
 627          * avilability.
 628          */
 629 #define SKL_CRTC_INDEX 31
 630         unsigned scaler_users;
 631
 632         /* scaler used by crtc for panel fitting purpose */
 633         int scaler_id;
 634 };
 635
 636 /* drm_mode->private_flags */
 637 #define I915_MODE_FLAG_INHERITED 1
 638 /* Flag to get scanline using frame time stamps */
 639 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 640
 641 struct intel_pipe_wm {
 642         struct intel_wm_level wm[5];
 643         uint32_t linetime;
 644         bool fbc_wm_enabled;
 645         bool pipe_enabled;
 646         bool sprites_enabled;
 647         bool sprites_scaled;
 648 };
 649
 650 struct skl_plane_wm {
 651         struct skl_wm_level wm[8];
 652         struct skl_wm_level uv_wm[8];
 653         struct skl_wm_level trans_wm;
 654         bool is_planar;
 655 };
 656
 657 struct skl_pipe_wm {
 658         struct skl_plane_wm planes[I915_MAX_PLANES];
 659         uint32_t linetime;
 660 };
 661
 662 enum vlv_wm_level {
 663         VLV_WM_LEVEL_PM2,
 664         VLV_WM_LEVEL_PM5,
 665         VLV_WM_LEVEL_DDR_DVFS,
 666         NUM_VLV_WM_LEVELS,
 667 };
 668
 669 struct vlv_wm_state {
 670         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 671         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 672         uint8_t num_levels;
 673         bool cxsr;
 674 };
 675
 676 struct vlv_fifo_state {
 677         u16 plane[I915_MAX_PLANES];
 678 };
 679
 680 enum g4x_wm_level {
 681         G4X_WM_LEVEL_NORMAL,
 682         G4X_WM_LEVEL_SR,
 683         G4X_WM_LEVEL_HPLL,
 684         NUM_G4X_WM_LEVELS,
 685 };
 686
 687 struct g4x_wm_state {
 688         struct g4x_pipe_wm wm;
 689         struct g4x_sr_wm sr;
 690         struct g4x_sr_wm hpll;
 691         bool cxsr;
 692         bool hpll_en;
 693         bool fbc_en;
 694 };
 695
 696 struct intel_crtc_wm_state {
 697         union {
 698                 struct {
 699                         /*
 700                          * Intermediate watermarks; these can be
 701                          * programmed immediately since they satisfy
 702                          * both the current configuration we're
 703                          * switching away from and the new
 704                          * configuration we're switching to.
 705                          */
 706                         struct intel_pipe_wm intermediate;
 707
 708                         /*
 709                          * Optimal watermarks, programmed post-vblank
 710                          * when this state is committed.
 711                          */
 712                         struct intel_pipe_wm optimal;
 713                 } ilk;
 714
 715                 struct {
 716                         /* gen9+ only needs 1-step wm programming */
 717                         struct skl_pipe_wm optimal;
 718                         struct skl_ddb_entry ddb;
 719                         struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
 720                         struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
 721                 } skl;
 722
 723                 struct {
 724                         /* "raw" watermarks (not inverted) */
 725                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 726                         /* intermediate watermarks (inverted) */
 727                         struct vlv_wm_state intermediate;
 728                         /* optimal watermarks (inverted) */
 729                         struct vlv_wm_state optimal;
 730                         /* display FIFO split */
 731                         struct vlv_fifo_state fifo_state;
 732                 } vlv;
 733
 734                 struct {
 735                         /* "raw" watermarks */
 736                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 737                         /* intermediate watermarks */
 738                         struct g4x_wm_state intermediate;
 739                         /* optimal watermarks */
 740                         struct g4x_wm_state optimal;
 741                 } g4x;
 742         };
 743
 744         /*
 745          * Platforms with two-step watermark programming will need to
 746          * update watermark programming post-vblank to switch from the
 747          * safe intermediate watermarks to the optimal final
 748          * watermarks.
 749          */
 750         bool need_postvbl_update;
 751 };
 752
 753 enum intel_output_format {
 754         INTEL_OUTPUT_FORMAT_INVALID,
 755         INTEL_OUTPUT_FORMAT_RGB,
 756         INTEL_OUTPUT_FORMAT_YCBCR420,
 757         INTEL_OUTPUT_FORMAT_YCBCR444,
 758 };
 759
 760 struct intel_crtc_state {
 761         struct drm_crtc_state base;
 762
 763         /**
 764          * quirks - bitfield with hw state readout quirks
 765          *
 766          * For various reasons the hw state readout code might not be able to
 767          * completely faithfully read out the current state. These cases are
 768          * tracked with quirk flags so that fastboot and state checker can act
 769          * accordingly.
 770          */
 771 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 772         unsigned long quirks;
 773
 774         unsigned fb_bits; /* framebuffers to flip */
 775         bool update_pipe; /* can a fast modeset be performed? */
 776         bool disable_cxsr;
 777         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 778         bool fb_changed; /* fb on any of the planes is changed */
 779         bool fifo_changed; /* FIFO split is changed */
 780
 781         /* Pipe source size (ie. panel fitter input size)
 782          * All planes will be positioned inside this space,
 783          * and get clipped at the edges. */
 784         int pipe_src_w, pipe_src_h;
 785
 786         /*
 787          * Pipe pixel rate, adjusted for
 788          * panel fitter/pipe scaler downscaling.
 789          */
 790         unsigned int pixel_rate;
 791
 792         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 793          * between pch encoders and cpu encoders. */
 794         bool has_pch_encoder;
 795
 796         /* Are we sending infoframes on the attached port */
 797         bool has_infoframe;
 798
 799         /* CPU Transcoder for the pipe. Currently this can only differ from the
 800          * pipe on Haswell and later (where we have a special eDP transcoder)
 801          * and Broxton (where we have special DSI transcoders). */
 802         enum transcoder cpu_transcoder;
 803
 804         /*
 805          * Use reduced/limited/broadcast rbg range, compressing from the full
 806          * range fed into the crtcs.
 807          */
 808         bool limited_color_range;
 809
 810         /* Bitmask of encoder types (enum intel_output_type)
 811          * driven by the pipe.
 812          */
 813         unsigned int output_types;
 814
 815         /* Whether we should send NULL infoframes. Required for audio. */
 816         bool has_hdmi_sink;
 817
 818         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 819          * has_dp_encoder is set. */
 820         bool has_audio;
 821
 822         /*
 823          * Enable dithering, used when the selected pipe bpp doesn't match the
 824          * plane bpp.
 825          */
 826         bool dither;
 827
 828         /*
 829          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 830          * compliance video pattern tests.
 831          * Disable dither only if it is a compliance test request for
 832          * 18bpp.
 833          */
 834         bool dither_force_disable;
 835
 836         /* Controls for the clock computation, to override various stages. */
 837         bool clock_set;
 838
 839         /* SDVO TV has a bunch of special case. To make multifunction encoders
 840          * work correctly, we need to track this at runtime.*/
 841         bool sdvo_tv_clock;
 842
 843         /*
 844          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 845          * required. This is set in the 2nd loop of calling encoder's
 846          * ->compute_config if the first pick doesn't work out.
 847          */
 848         bool bw_constrained;
 849
 850         /* Settings for the intel dpll used on pretty much everything but
 851          * haswell. */
 852         struct dpll dpll;
 853
 854         /* Selected dpll when shared or NULL. */
 855         struct intel_shared_dpll *shared_dpll;
 856
 857         /* Actual register state of the dpll, for shared dpll cross-checking. */
 858         struct intel_dpll_hw_state dpll_hw_state;
 859
 860         /* DSI PLL registers */
 861         struct {
 862                 u32 ctrl, div;
 863         } dsi_pll;
 864
 865         int pipe_bpp;
 866         struct intel_link_m_n dp_m_n;
 867
 868         /* m2_n2 for eDP downclock */
 869         struct intel_link_m_n dp_m2_n2;
 870         bool has_drrs;
 871
 872         bool has_psr;
 873         bool has_psr2;
 874
 875         /*
 876          * Frequence the dpll for the port should run at. Differs from the
 877          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 878          * already multiplied by pixel_multiplier.
 879          */
 880         int port_clock;
 881
 882         /* Used by SDVO (and if we ever fix it, HDMI). */
 883         unsigned pixel_multiplier;
 884
 885         uint8_t lane_count;
 886
 887         /*
 888          * Used by platforms having DP/HDMI PHY with programmable lane
 889          * latency optimization.
 890          */
 891         uint8_t lane_lat_optim_mask;
 892
 893         /* minimum acceptable voltage level */
 894         u8 min_voltage_level;
 895
 896         /* Panel fitter controls for gen2-gen4 + VLV */
 897         struct {
 898                 u32 control;
 899                 u32 pgm_ratios;
 900                 u32 lvds_border_bits;
 901         } gmch_pfit;
 902
 903         /* Panel fitter placement and size for Ironlake+ */
 904         struct {
 905                 u32 pos;
 906                 u32 size;
 907                 bool enabled;
 908                 bool force_thru;
 909         } pch_pfit;
 910
 911         /* FDI configuration, only valid if has_pch_encoder is set. */
 912         int fdi_lanes;
 913         struct intel_link_m_n fdi_m_n;
 914
 915         bool ips_enabled;
 916         bool ips_force_disable;
 917
 918         bool enable_fbc;
 919
 920         bool double_wide;
 921
 922         int pbn;
 923
 924         struct intel_crtc_scaler_state scaler_state;
 925
 926         /* w/a for waiting 2 vblanks during crtc enable */
 927         enum pipe hsw_workaround_pipe;
 928
 929         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 930         bool disable_lp_wm;
 931
 932         struct intel_crtc_wm_state wm;
 933
 934         /* Gamma mode programmed on the pipe */
 935         uint32_t gamma_mode;
 936
 937         /* bitmask of visible planes (enum plane_id) */
 938         u8 active_planes;
 939         u8 nv12_planes;
 940
 941         /* bitmask of planes that will be updated during the commit */
 942         u8 update_planes;
 943
 944         /* HDMI scrambling status */
 945         bool hdmi_scrambling;
 946
 947         /* HDMI High TMDS char rate ratio */
 948         bool hdmi_high_tmds_clock_ratio;
 949
 950         /* Output format RGB/YCBCR etc */
 951         enum intel_output_format output_format;
 952
 953         /* Output down scaling is done in LSPCON device */
 954         bool lspcon_downsampling;
 955
 956         /* Display Stream compression state */
 957         struct {
 958                 bool compression_enable;
 959                 bool dsc_split;
 960                 u16 compressed_bpp;
 961                 u8 slice_count;
 962         } dsc_params;
 963         struct drm_dsc_config dp_dsc_cfg;
 964
 965         /* Forward Error correction State */
 966         bool fec_enable;
 967 };
 968
 969 struct intel_crtc {
 970         struct drm_crtc base;
 971         enum pipe pipe;
 972         /*
 973          * Whether the crtc and the connected output pipeline is active. Implies
 974          * that crtc->enabled is set, i.e. the current mode configuration has
 975          * some outputs connected to this crtc.
 976          */
 977         bool active;
 978         u8 plane_ids_mask;
 979         unsigned long long enabled_power_domains;
 980         struct intel_overlay *overlay;
 981
 982         struct intel_crtc_state *config;
 983
 984         /* global reset count when the last flip was submitted */
 985         unsigned int reset_count;
 986
 987         /* Access to these should be protected by dev_priv->irq_lock. */
 988         bool cpu_fifo_underrun_disabled;
 989         bool pch_fifo_underrun_disabled;
 990
 991         /* per-pipe watermark state */
 992         struct {
 993                 /* watermarks currently being used  */
 994                 union {
 995                         struct intel_pipe_wm ilk;
 996                         struct vlv_wm_state vlv;
 997                         struct g4x_wm_state g4x;
 998                 } active;
 999         } wm;
1000
1001         int scanline_offset;
1002
1003         struct {
1004                 unsigned start_vbl_count;
1005                 ktime_t start_vbl_time;
1006                 int min_vbl, max_vbl;
1007                 int scanline_start;
1008         } debug;
1009
1010         /* scalers available on this crtc */
1011         int num_scalers;
1012 };
1013
1014 struct intel_plane {
1015         struct drm_plane base;
1016         enum i9xx_plane_id i9xx_plane;
1017         enum plane_id id;
1018         enum pipe pipe;
1019         bool has_fbc;
1020         bool has_ccs;
1021         uint32_t frontbuffer_bit;
1022
1023         struct {
1024                 u32 base, cntl, size;
1025         } cursor;
1026
1027         /*
1028          * NOTE: Do not place new plane state fields here (e.g., when adding
1029          * new plane properties).  New runtime state should now be placed in
1030          * the intel_plane_state structure and accessed via plane_state.
1031          */
1032
1033         unsigned int (*max_stride)(struct intel_plane *plane,
1034                                    u32 pixel_format, u64 modifier,
1035                                    unsigned int rotation);
1036         void (*update_plane)(struct intel_plane *plane,
1037                              const struct intel_crtc_state *crtc_state,
1038                              const struct intel_plane_state *plane_state);
1039         void (*update_slave)(struct intel_plane *plane,
1040                              const struct intel_crtc_state *crtc_state,
1041                              const struct intel_plane_state *plane_state);
1042         void (*disable_plane)(struct intel_plane *plane,
1043                               const struct intel_crtc_state *crtc_state);
1044         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1045         int (*check_plane)(struct intel_crtc_state *crtc_state,
1046                            struct intel_plane_state *plane_state);
1047 };
1048
1049 struct intel_watermark_params {
1050         u16 fifo_size;
1051         u16 max_wm;
1052         u8 default_wm;
1053         u8 guard_size;
1054         u8 cacheline_size;
1055 };
1056
1057 struct cxsr_latency {
1058         bool is_desktop : 1;
1059         bool is_ddr3 : 1;
1060         u16 fsb_freq;
1061         u16 mem_freq;
1062         u16 display_sr;
1063         u16 display_hpll_disable;
1064         u16 cursor_sr;
1065         u16 cursor_hpll_disable;
1066 };
1067
1068 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1069 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1070 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1071 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1072 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1073 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1074 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1075 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1076 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1077
1078 struct intel_hdmi {
1079         i915_reg_t hdmi_reg;
1080         int ddc_bus;
1081         struct {
1082                 enum drm_dp_dual_mode_type type;
1083                 int max_tmds_clock;
1084         } dp_dual_mode;
1085         bool has_hdmi_sink;
1086         bool has_audio;
1087         bool rgb_quant_range_selectable;
1088         struct intel_connector *attached_connector;
1089         struct cec_notifier *cec_notifier;
1090 };
1091
1092 struct intel_dp_mst_encoder;
1093 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1094
1095 /*
1096  * enum link_m_n_set:
1097  *      When platform provides two set of M_N registers for dp, we can
1098  *      program them and switch between them incase of DRRS.
1099  *      But When only one such register is provided, we have to program the
1100  *      required divider value on that registers itself based on the DRRS state.
1101  *
1102  * M1_N1        : Program dp_m_n on M1_N1 registers
1103  *                        dp_m2_n2 on M2_N2 registers (If supported)
1104  *
1105  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1106  *                        M2_N2 registers are not supported
1107  */
1108
1109 enum link_m_n_set {
1110         /* Sets the m1_n1 and m2_n2 */
1111         M1_N1 = 0,
1112         M2_N2
1113 };
1114
1115 struct intel_dp_compliance_data {
1116         unsigned long edid;
1117         uint8_t video_pattern;
1118         uint16_t hdisplay, vdisplay;
1119         uint8_t bpc;
1120 };
1121
1122 struct intel_dp_compliance {
1123         unsigned long test_type;
1124         struct intel_dp_compliance_data test_data;
1125         bool test_active;
1126         int test_link_rate;
1127         u8 test_lane_count;
1128 };
1129
1130 struct intel_dp {
1131         i915_reg_t output_reg;
1132         uint32_t DP;
1133         int link_rate;
1134         uint8_t lane_count;
1135         uint8_t sink_count;
1136         bool link_mst;
1137         bool link_trained;
1138         bool has_audio;
1139         bool reset_link_params;
1140         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1141         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1142         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1143         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1144         u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1145         u8 fec_capable;
1146         /* source rates */
1147         int num_source_rates;
1148         const int *source_rates;
1149         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1150         int num_sink_rates;
1151         int sink_rates[DP_MAX_SUPPORTED_RATES];
1152         bool use_rate_select;
1153         /* intersection of source and sink rates */
1154         int num_common_rates;
1155         int common_rates[DP_MAX_SUPPORTED_RATES];
1156         /* Max lane count for the current link */
1157         int max_link_lane_count;
1158         /* Max rate for the current link */
1159         int max_link_rate;
1160         /* sink or branch descriptor */
1161         struct drm_dp_desc desc;
1162         struct drm_dp_aux aux;
1163         uint8_t train_set[4];
1164         int panel_power_up_delay;
1165         int panel_power_down_delay;
1166         int panel_power_cycle_delay;
1167         int backlight_on_delay;
1168         int backlight_off_delay;
1169         struct delayed_work panel_vdd_work;
1170         bool want_panel_vdd;
1171         unsigned long last_power_on;
1172         unsigned long last_backlight_off;
1173         ktime_t panel_power_off_time;
1174
1175         struct notifier_block edp_notifier;
1176
1177         /*
1178          * Pipe whose power sequencer is currently locked into
1179          * this port. Only relevant on VLV/CHV.
1180          */
1181         enum pipe pps_pipe;
1182         /*
1183          * Pipe currently driving the port. Used for preventing
1184          * the use of the PPS for any pipe currentrly driving
1185          * external DP as that will mess things up on VLV.
1186          */
1187         enum pipe active_pipe;
1188         /*
1189          * Set if the sequencer may be reset due to a power transition,
1190          * requiring a reinitialization. Only relevant on BXT.
1191          */
1192         bool pps_reset;
1193         struct edp_power_seq pps_delays;
1194
1195         bool can_mst; /* this port supports mst */
1196         bool is_mst;
1197         int active_mst_links;
1198         /* connector directly attached - won't be use for modeset in mst world */
1199         struct intel_connector *attached_connector;
1200
1201         /* mst connector list */
1202         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1203         struct drm_dp_mst_topology_mgr mst_mgr;
1204
1205         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1206         /*
1207          * This function returns the value we have to program the AUX_CTL
1208          * register with to kick off an AUX transaction.
1209          */
1210         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1211                                      int send_bytes,
1212                                      uint32_t aux_clock_divider);
1213
1214         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1215         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1216
1217         /* This is called before a link training is starterd */
1218         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1219
1220         /* Displayport compliance testing */
1221         struct intel_dp_compliance compliance;
1222 };
1223
1224 enum lspcon_vendor {
1225         LSPCON_VENDOR_MCA,
1226         LSPCON_VENDOR_PARADE
1227 };
1228
1229 struct intel_lspcon {
1230         bool active;
1231         enum drm_lspcon_mode mode;
1232         enum lspcon_vendor vendor;
1233 };
1234
1235 struct intel_digital_port {
1236         struct intel_encoder base;
1237         u32 saved_port_bits;
1238         struct intel_dp dp;
1239         struct intel_hdmi hdmi;
1240         struct intel_lspcon lspcon;
1241         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1242         bool release_cl2_override;
1243         uint8_t max_lanes;
1244         /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1245         enum aux_ch aux_ch;
1246         enum intel_display_power_domain ddi_io_power_domain;
1247         enum tc_port_type tc_type;
1248
1249         void (*write_infoframe)(struct intel_encoder *encoder,
1250                                 const struct intel_crtc_state *crtc_state,
1251                                 unsigned int type,
1252                                 const void *frame, ssize_t len);
1253         void (*set_infoframes)(struct intel_encoder *encoder,
1254                                bool enable,
1255                                const struct intel_crtc_state *crtc_state,
1256                                const struct drm_connector_state *conn_state);
1257         bool (*infoframe_enabled)(struct intel_encoder *encoder,
1258                                   const struct intel_crtc_state *pipe_config);
1259 };
1260
1261 struct intel_dp_mst_encoder {
1262         struct intel_encoder base;
1263         enum pipe pipe;
1264         struct intel_digital_port *primary;
1265         struct intel_connector *connector;
1266 };
1267
1268 static inline enum dpio_channel
1269 vlv_dport_to_channel(struct intel_digital_port *dport)
1270 {
1271         switch (dport->base.port) {
1272         case PORT_B:
1273         case PORT_D:
1274                 return DPIO_CH0;
1275         case PORT_C:
1276                 return DPIO_CH1;
1277         default:
1278                 BUG();
1279         }
1280 }
1281
1282 static inline enum dpio_phy
1283 vlv_dport_to_phy(struct intel_digital_port *dport)
1284 {
1285         switch (dport->base.port) {
1286         case PORT_B:
1287         case PORT_C:
1288                 return DPIO_PHY0;
1289         case PORT_D:
1290                 return DPIO_PHY1;
1291         default:
1292                 BUG();
1293         }
1294 }
1295
1296 static inline enum dpio_channel
1297 vlv_pipe_to_channel(enum pipe pipe)
1298 {
1299         switch (pipe) {
1300         case PIPE_A:
1301         case PIPE_C:
1302                 return DPIO_CH0;
1303         case PIPE_B:
1304                 return DPIO_CH1;
1305         default:
1306                 BUG();
1307         }
1308 }
1309
1310 static inline struct intel_crtc *
1311 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1312 {
1313         return dev_priv->pipe_to_crtc_mapping[pipe];
1314 }
1315
1316 static inline struct intel_crtc *
1317 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1318 {
1319         return dev_priv->plane_to_crtc_mapping[plane];
1320 }
1321
1322 struct intel_load_detect_pipe {
1323         struct drm_atomic_state *restore_state;
1324 };
1325
1326 static inline struct intel_encoder *
1327 intel_attached_encoder(struct drm_connector *connector)
1328 {
1329         return to_intel_connector(connector)->encoder;
1330 }
1331
1332 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1333 {
1334         switch (encoder->type) {
1335         case INTEL_OUTPUT_DDI:
1336         case INTEL_OUTPUT_DP:
1337         case INTEL_OUTPUT_EDP:
1338         case INTEL_OUTPUT_HDMI:
1339                 return true;
1340         default:
1341                 return false;
1342         }
1343 }
1344
1345 static inline struct intel_digital_port *
1346 enc_to_dig_port(struct drm_encoder *encoder)
1347 {
1348         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1349
1350         if (intel_encoder_is_dig_port(intel_encoder))
1351                 return container_of(encoder, struct intel_digital_port,
1352                                     base.base);
1353         else
1354                 return NULL;
1355 }
1356
1357 static inline struct intel_digital_port *
1358 conn_to_dig_port(struct intel_connector *connector)
1359 {
1360         return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1361 }
1362
1363 static inline struct intel_dp_mst_encoder *
1364 enc_to_mst(struct drm_encoder *encoder)
1365 {
1366         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1367 }
1368
1369 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1370 {
1371         return &enc_to_dig_port(encoder)->dp;
1372 }
1373
1374 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1375 {
1376         switch (encoder->type) {
1377         case INTEL_OUTPUT_DP:
1378         case INTEL_OUTPUT_EDP:
1379                 return true;
1380         case INTEL_OUTPUT_DDI:
1381                 /* Skip pure HDMI/DVI DDI encoders */
1382                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1383         default:
1384                 return false;
1385         }
1386 }
1387
1388 static inline struct intel_lspcon *
1389 enc_to_intel_lspcon(struct drm_encoder *encoder)
1390 {
1391         return &enc_to_dig_port(encoder)->lspcon;
1392 }
1393
1394 static inline struct intel_digital_port *
1395 dp_to_dig_port(struct intel_dp *intel_dp)
1396 {
1397         return container_of(intel_dp, struct intel_digital_port, dp);
1398 }
1399
1400 static inline struct intel_lspcon *
1401 dp_to_lspcon(struct intel_dp *intel_dp)
1402 {
1403         return &dp_to_dig_port(intel_dp)->lspcon;
1404 }
1405
1406 static inline struct drm_i915_private *
1407 dp_to_i915(struct intel_dp *intel_dp)
1408 {
1409         return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1410 }
1411
1412 static inline struct intel_digital_port *
1413 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1414 {
1415         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1416 }
1417
1418 static inline struct intel_plane_state *
1419 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1420                                  struct intel_plane *plane)
1421 {
1422         struct drm_plane_state *ret =
1423                 drm_atomic_get_plane_state(&state->base, &plane->base);
1424
1425         if (IS_ERR(ret))
1426                 return ERR_CAST(ret);
1427
1428         return to_intel_plane_state(ret);
1429 }
1430
1431 static inline struct intel_plane_state *
1432 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1433                                  struct intel_plane *plane)
1434 {
1435         return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1436                                                                    &plane->base));
1437 }
1438
1439 static inline struct intel_plane_state *
1440 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1441                                  struct intel_plane *plane)
1442 {
1443         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1444                                                                    &plane->base));
1445 }
1446
1447 static inline struct intel_crtc_state *
1448 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1449                                 struct intel_crtc *crtc)
1450 {
1451         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1452                                                                  &crtc->base));
1453 }
1454
1455 static inline struct intel_crtc_state *
1456 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1457                                 struct intel_crtc *crtc)
1458 {
1459         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1460                                                                  &crtc->base));
1461 }
1462
1463 /* intel_fifo_underrun.c */
1464 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1465                                            enum pipe pipe, bool enable);
1466 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1467                                            enum pipe pch_transcoder,
1468                                            bool enable);
1469 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1470                                          enum pipe pipe);
1471 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1472                                          enum pipe pch_transcoder);
1473 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1474 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1475
1476 /* i915_irq.c */
1477 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1478 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1479 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1480 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1481 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1482 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1483 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1484 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1485
1486 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1487                                             u32 mask)
1488 {
1489         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1490 }
1491
1492 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1493 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1494 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1495 {
1496         /*
1497          * We only use drm_irq_uninstall() at unload and VT switch, so
1498          * this is the only thing we need to check.
1499          */
1500         return dev_priv->runtime_pm.irqs_enabled;
1501 }
1502
1503 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1504 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1505                                      u8 pipe_mask);
1506 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1507                                      u8 pipe_mask);
1508 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1509 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1510 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1511
1512 /* intel_crt.c */
1513 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1514                             i915_reg_t adpa_reg, enum pipe *pipe);
1515 void intel_crt_init(struct drm_i915_private *dev_priv);
1516 void intel_crt_reset(struct drm_encoder *encoder);
1517
1518 /* intel_ddi.c */
1519 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1520                                 const struct intel_crtc_state *old_crtc_state,
1521                                 const struct drm_connector_state *old_conn_state);
1522 void hsw_fdi_link_train(struct intel_crtc *crtc,
1523                         const struct intel_crtc_state *crtc_state);
1524 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1525 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1526 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1527 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1528 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1529 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1530 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1531 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1532 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1533 void intel_ddi_get_config(struct intel_encoder *encoder,
1534                           struct intel_crtc_state *pipe_config);
1535
1536 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1537                                     bool state);
1538 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1539                                          struct intel_crtc_state *crtc_state);
1540 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1541 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1542 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1543 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1544                                  u8 voltage_swing);
1545 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1546                                      bool enable);
1547 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
1548 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1549                         enum intel_dpll_id pll_id);
1550
1551 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1552                                    int color_plane, unsigned int height);
1553
1554 /* intel_audio.c */
1555 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1556 void intel_audio_codec_enable(struct intel_encoder *encoder,
1557                               const struct intel_crtc_state *crtc_state,
1558                               const struct drm_connector_state *conn_state);
1559 void intel_audio_codec_disable(struct intel_encoder *encoder,
1560                                const struct intel_crtc_state *old_crtc_state,
1561                                const struct drm_connector_state *old_conn_state);
1562 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1563 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1564 void intel_audio_init(struct drm_i915_private *dev_priv);
1565 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1566
1567 /* intel_cdclk.c */
1568 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1569 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1570 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1571 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1572 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1573 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1574 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1575 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1576 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1577 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1578 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1579 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1580 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1581 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1582                                const struct intel_cdclk_state *b);
1583 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1584                          const struct intel_cdclk_state *b);
1585 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1586                      const struct intel_cdclk_state *cdclk_state);
1587 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1588                             const char *context);
1589
1590 /* intel_display.c */
1591 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1592 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1593 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1594 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1595 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1596                       const char *name, u32 reg, int ref_freq);
1597 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1598                            const char *name, u32 reg);
1599 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1600 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1601 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1602 unsigned int intel_fb_xy_to_linear(int x, int y,
1603                                    const struct intel_plane_state *state,
1604                                    int plane);
1605 void intel_add_fb_offsets(int *x, int *y,
1606                           const struct intel_plane_state *state, int plane);
1607 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1608 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1609 void intel_mark_busy(struct drm_i915_private *dev_priv);
1610 void intel_mark_idle(struct drm_i915_private *dev_priv);
1611 int intel_display_suspend(struct drm_device *dev);
1612 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1613 void intel_encoder_destroy(struct drm_encoder *encoder);
1614 struct drm_display_mode *
1615 intel_encoder_current_mode(struct intel_encoder *encoder);
1616 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1617 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1618 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1619                               enum port port);
1620 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1621                                       struct drm_file *file_priv);
1622 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1623                                              enum pipe pipe);
1624 static inline bool
1625 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1626                     enum intel_output_type type)
1627 {
1628         return crtc_state->output_types & (1 << type);
1629 }
1630 static inline bool
1631 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1632 {
1633         return crtc_state->output_types &
1634                 ((1 << INTEL_OUTPUT_DP) |
1635                  (1 << INTEL_OUTPUT_DP_MST) |
1636                  (1 << INTEL_OUTPUT_EDP));
1637 }
1638 static inline void
1639 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1640 {
1641         drm_wait_one_vblank(&dev_priv->drm, pipe);
1642 }
1643 static inline void
1644 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1645 {
1646         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1647
1648         if (crtc->active)
1649                 intel_wait_for_vblank(dev_priv, pipe);
1650 }
1651
1652 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1653
1654 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1655 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1656                          struct intel_digital_port *dport,
1657                          unsigned int expected_mask);
1658 int intel_get_load_detect_pipe(struct drm_connector *connector,
1659                                const struct drm_display_mode *mode,
1660                                struct intel_load_detect_pipe *old,
1661                                struct drm_modeset_acquire_ctx *ctx);
1662 void intel_release_load_detect_pipe(struct drm_connector *connector,
1663                                     struct intel_load_detect_pipe *old,
1664                                     struct drm_modeset_acquire_ctx *ctx);
1665 struct i915_vma *
1666 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1667                            const struct i915_ggtt_view *view,
1668                            bool uses_fence,
1669                            unsigned long *out_flags);
1670 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1671 struct drm_framebuffer *
1672 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1673                          struct drm_mode_fb_cmd2 *mode_cmd);
1674 int intel_prepare_plane_fb(struct drm_plane *plane,
1675                            struct drm_plane_state *new_state);
1676 void intel_cleanup_plane_fb(struct drm_plane *plane,
1677                             struct drm_plane_state *old_state);
1678 int intel_plane_atomic_get_property(struct drm_plane *plane,
1679                                     const struct drm_plane_state *state,
1680                                     struct drm_property *property,
1681                                     uint64_t *val);
1682 int intel_plane_atomic_set_property(struct drm_plane *plane,
1683                                     struct drm_plane_state *state,
1684                                     struct drm_property *property,
1685                                     uint64_t val);
1686 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1687                                     struct drm_crtc_state *crtc_state,
1688                                     const struct intel_plane_state *old_plane_state,
1689                                     struct drm_plane_state *plane_state);
1690
1691 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1692                                     enum pipe pipe);
1693
1694 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1695                      const struct dpll *dpll);
1696 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1697 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1698
1699 /* modesetting asserts */
1700 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1701                            enum pipe pipe);
1702 void assert_pll(struct drm_i915_private *dev_priv,
1703                 enum pipe pipe, bool state);
1704 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1705 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1706 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1707 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1708 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1709 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1710                        enum pipe pipe, bool state);
1711 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1712 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1713 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1714 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1715 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1716 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1717 void intel_finish_reset(struct drm_i915_private *dev_priv);
1718 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1719 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1720 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1721 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1722 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1723 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1724 unsigned int skl_cdclk_get_vco(unsigned int freq);
1725 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1726 void intel_dp_get_m_n(struct intel_crtc *crtc,
1727                       struct intel_crtc_state *pipe_config);
1728 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1729                       enum link_m_n_set m_n);
1730 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1731 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1732                         struct dpll *best_clock);
1733 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1734
1735 bool intel_crtc_active(struct intel_crtc *crtc);
1736 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1737 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1738 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1739 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1740 enum intel_display_power_domain
1741 intel_aux_power_domain(struct intel_digital_port *dig_port);
1742 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1743                                  struct intel_crtc_state *pipe_config);
1744 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1745                                   struct intel_crtc_state *crtc_state);
1746
1747 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1748 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1749 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1750                   u32 pixel_format);
1751
1752 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1753 {
1754         return i915_ggtt_offset(state->vma);
1755 }
1756
1757 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1758                         const struct intel_plane_state *plane_state);
1759 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1760                   const struct intel_plane_state *plane_state);
1761 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1762 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1763                      int plane);
1764 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1765 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1766 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1767 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1768                                    u32 pixel_format, u64 modifier,
1769                                    unsigned int rotation);
1770
1771 /* intel_connector.c */
1772 int intel_connector_init(struct intel_connector *connector);
1773 struct intel_connector *intel_connector_alloc(void);
1774 void intel_connector_free(struct intel_connector *connector);
1775 void intel_connector_destroy(struct drm_connector *connector);
1776 int intel_connector_register(struct drm_connector *connector);
1777 void intel_connector_unregister(struct drm_connector *connector);
1778 void intel_connector_attach_encoder(struct intel_connector *connector,
1779                                     struct intel_encoder *encoder);
1780 bool intel_connector_get_hw_state(struct intel_connector *connector);
1781 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1782 int intel_connector_update_modes(struct drm_connector *connector,
1783                                  struct edid *edid);
1784 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1785 void intel_attach_force_audio_property(struct drm_connector *connector);
1786 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1787 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1788
1789 /* intel_csr.c */
1790 void intel_csr_ucode_init(struct drm_i915_private *);
1791 void intel_csr_load_program(struct drm_i915_private *);
1792 void intel_csr_ucode_fini(struct drm_i915_private *);
1793 void intel_csr_ucode_suspend(struct drm_i915_private *);
1794 void intel_csr_ucode_resume(struct drm_i915_private *);
1795
1796 /* intel_dp.c */
1797 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1798                            i915_reg_t dp_reg, enum port port,
1799                            enum pipe *pipe);
1800 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1801                    enum port port);
1802 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1803                              struct intel_connector *intel_connector);
1804 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1805                               int link_rate, uint8_t lane_count,
1806                               bool link_mst);
1807 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1808                                             int link_rate, uint8_t lane_count);
1809 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1810 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1811 int intel_dp_retrain_link(struct intel_encoder *encoder,
1812                           struct drm_modeset_acquire_ctx *ctx);
1813 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1814 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1815                                            const struct intel_crtc_state *crtc_state,
1816                                            bool enable);
1817 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1818 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1819 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1820 bool intel_dp_compute_config(struct intel_encoder *encoder,
1821                              struct intel_crtc_state *pipe_config,
1822                              struct drm_connector_state *conn_state);
1823 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1824 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1825 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1826                                   bool long_hpd);
1827 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1828                             const struct drm_connector_state *conn_state);
1829 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1830 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1831 void intel_edp_panel_on(struct intel_dp *intel_dp);
1832 void intel_edp_panel_off(struct intel_dp *intel_dp);
1833 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1834 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1835 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1836 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1837 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1838 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1839 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1840 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1841 void intel_plane_destroy(struct drm_plane *plane);
1842 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1843                            const struct intel_crtc_state *crtc_state);
1844 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1845                             const struct intel_crtc_state *crtc_state);
1846 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1847                                unsigned int frontbuffer_bits);
1848 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1849                           unsigned int frontbuffer_bits);
1850
1851 void
1852 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1853                                        uint8_t dp_train_pat);
1854 void
1855 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1856 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1857 uint8_t
1858 intel_dp_voltage_max(struct intel_dp *intel_dp);
1859 uint8_t
1860 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1861 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1862                            uint8_t *link_bw, uint8_t *rate_select);
1863 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1864 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1865 bool
1866 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1867 uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
1868                                      int mode_clock, int mode_hdisplay);
1869 uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
1870                                      int mode_hdisplay);
1871
1872 /* intel_vdsc.c */
1873 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
1874                                 struct intel_crtc_state *pipe_config);
1875 enum intel_display_power_domain
1876 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
1877
1878 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1879 {
1880         return ~((1 << lane_count) - 1) & 0xf;
1881 }
1882
1883 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1884 int intel_dp_link_required(int pixel_clock, int bpp);
1885 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1886 bool intel_digital_port_connected(struct intel_encoder *encoder);
1887
1888 /* intel_dp_aux_backlight.c */
1889 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1890
1891 /* intel_dp_mst.c */
1892 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1893 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1894 /* vlv_dsi.c */
1895 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1896
1897 /* icl_dsi.c */
1898 void icl_dsi_init(struct drm_i915_private *dev_priv);
1899
1900 /* intel_dsi_dcs_backlight.c */
1901 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1902
1903 /* intel_dvo.c */
1904 void intel_dvo_init(struct drm_i915_private *dev_priv);
1905 /* intel_hotplug.c */
1906 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1907 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1908                            struct intel_connector *connector);
1909
1910 /* legacy fbdev emulation in intel_fbdev.c */
1911 #ifdef CONFIG_DRM_FBDEV_EMULATION
1912 extern int intel_fbdev_init(struct drm_device *dev);
1913 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1914 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1915 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1916 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1917 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1918 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1919 #else
1920 static inline int intel_fbdev_init(struct drm_device *dev)
1921 {
1922         return 0;
1923 }
1924
1925 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1926 {
1927 }
1928
1929 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1930 {
1931 }
1932
1933 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1934 {
1935 }
1936
1937 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1938 {
1939 }
1940
1941 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1942 {
1943 }
1944
1945 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1946 {
1947 }
1948 #endif
1949
1950 /* intel_fbc.c */
1951 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1952                            struct intel_atomic_state *state);
1953 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1954 void intel_fbc_pre_update(struct intel_crtc *crtc,
1955                           struct intel_crtc_state *crtc_state,
1956                           struct intel_plane_state *plane_state);
1957 void intel_fbc_post_update(struct intel_crtc *crtc);
1958 void intel_fbc_init(struct drm_i915_private *dev_priv);
1959 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1960 void intel_fbc_enable(struct intel_crtc *crtc,
1961                       struct intel_crtc_state *crtc_state,
1962                       struct intel_plane_state *plane_state);
1963 void intel_fbc_disable(struct intel_crtc *crtc);
1964 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1965 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1966                           unsigned int frontbuffer_bits,
1967                           enum fb_op_origin origin);
1968 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1969                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1970 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1971 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1972 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1973
1974 /* intel_hdmi.c */
1975 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1976                      enum port port);
1977 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1978                                struct intel_connector *intel_connector);
1979 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1980 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1981                                struct intel_crtc_state *pipe_config,
1982                                struct drm_connector_state *conn_state);
1983 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1984                                        struct drm_connector *connector,
1985                                        bool high_tmds_clock_ratio,
1986                                        bool scrambling);
1987 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1988 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1989
1990 /* intel_lvds.c */
1991 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1992                              i915_reg_t lvds_reg, enum pipe *pipe);
1993 void intel_lvds_init(struct drm_i915_private *dev_priv);
1994 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1995 bool intel_is_dual_link_lvds(struct drm_device *dev);
1996
1997 /* intel_overlay.c */
1998 void intel_overlay_setup(struct drm_i915_private *dev_priv);
1999 void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
2000 int intel_overlay_switch_off(struct intel_overlay *overlay);
2001 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
2002                                   struct drm_file *file_priv);
2003 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
2004                               struct drm_file *file_priv);
2005 void intel_overlay_reset(struct drm_i915_private *dev_priv);
2006
2007
2008 /* intel_panel.c */
2009 int intel_panel_init(struct intel_panel *panel,
2010                      struct drm_display_mode *fixed_mode,
2011                      struct drm_display_mode *downclock_mode);
2012 void intel_panel_fini(struct intel_panel *panel);
2013 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
2014                             struct drm_display_mode *adjusted_mode);
2015 void intel_pch_panel_fitting(struct intel_crtc *crtc,
2016                              struct intel_crtc_state *pipe_config,
2017                              int fitting_mode);
2018 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
2019                               struct intel_crtc_state *pipe_config,
2020                               int fitting_mode);
2021 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
2022                                     u32 level, u32 max);
2023 int intel_panel_setup_backlight(struct drm_connector *connector,
2024                                 enum pipe pipe);
2025 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
2026                                   const struct drm_connector_state *conn_state);
2027 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
2028 extern struct drm_display_mode *intel_find_panel_downclock(
2029                                 struct drm_i915_private *dev_priv,
2030                                 struct drm_display_mode *fixed_mode,
2031                                 struct drm_connector *connector);
2032
2033 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
2034 int intel_backlight_device_register(struct intel_connector *connector);
2035 void intel_backlight_device_unregister(struct intel_connector *connector);
2036 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2037 static inline int intel_backlight_device_register(struct intel_connector *connector)
2038 {
2039         return 0;
2040 }
2041 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
2042 {
2043 }
2044 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2045
2046 /* intel_hdcp.c */
2047 void intel_hdcp_atomic_check(struct drm_connector *connector,
2048                              struct drm_connector_state *old_state,
2049                              struct drm_connector_state *new_state);
2050 int intel_hdcp_init(struct intel_connector *connector,
2051                     const struct intel_hdcp_shim *hdcp_shim);
2052 int intel_hdcp_enable(struct intel_connector *connector);
2053 int intel_hdcp_disable(struct intel_connector *connector);
2054 int intel_hdcp_check_link(struct intel_connector *connector);
2055 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2056 bool intel_hdcp_capable(struct intel_connector *connector);
2057
2058 /* intel_psr.c */
2059 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2060 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2061 void intel_psr_enable(struct intel_dp *intel_dp,
2062                       const struct intel_crtc_state *crtc_state);
2063 void intel_psr_disable(struct intel_dp *intel_dp,
2064                       const struct intel_crtc_state *old_crtc_state);
2065 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
2066                                struct drm_modeset_acquire_ctx *ctx,
2067                                u64 value);
2068 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2069                           unsigned frontbuffer_bits,
2070                           enum fb_op_origin origin);
2071 void intel_psr_flush(struct drm_i915_private *dev_priv,
2072                      unsigned frontbuffer_bits,
2073                      enum fb_op_origin origin);
2074 void intel_psr_init(struct drm_i915_private *dev_priv);
2075 void intel_psr_compute_config(struct intel_dp *intel_dp,
2076                               struct intel_crtc_state *crtc_state);
2077 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2078 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2079 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2080 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2081                             u32 *out_value);
2082 bool intel_psr_enabled(struct intel_dp *intel_dp);
2083
2084 /* intel_quirks.c */
2085 void intel_init_quirks(struct drm_i915_private *dev_priv);
2086
2087 /* intel_runtime_pm.c */
2088 int intel_power_domains_init(struct drm_i915_private *);
2089 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2090 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2091 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2092 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2093 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
2094 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2095 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2096
2097 enum i915_drm_suspend_mode {
2098         I915_DRM_SUSPEND_IDLE,
2099         I915_DRM_SUSPEND_MEM,
2100         I915_DRM_SUSPEND_HIBERNATE,
2101 };
2102
2103 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2104                                  enum i915_drm_suspend_mode);
2105 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2106 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2107 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2108 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2109 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2110 const char *
2111 intel_display_power_domain_str(enum intel_display_power_domain domain);
2112
2113 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2114                                     enum intel_display_power_domain domain);
2115 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2116                                       enum intel_display_power_domain domain);
2117 void intel_display_power_get(struct drm_i915_private *dev_priv,
2118                              enum intel_display_power_domain domain);
2119 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2120                                         enum intel_display_power_domain domain);
2121 void intel_display_power_put(struct drm_i915_private *dev_priv,
2122                              enum intel_display_power_domain domain);
2123 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2124                             u8 req_slices);
2125
2126 static inline void
2127 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
2128 {
2129         WARN_ONCE(dev_priv->runtime_pm.suspended,
2130                   "Device suspended during HW access\n");
2131 }
2132
2133 static inline void
2134 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
2135 {
2136         assert_rpm_device_not_suspended(dev_priv);
2137         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
2138                   "RPM wakelock ref not held during HW access");
2139 }
2140
2141 /**
2142  * disable_rpm_wakeref_asserts - disable the RPM assert checks
2143  * @dev_priv: i915 device instance
2144  *
2145  * This function disable asserts that check if we hold an RPM wakelock
2146  * reference, while keeping the device-not-suspended checks still enabled.
2147  * It's meant to be used only in special circumstances where our rule about
2148  * the wakelock refcount wrt. the device power state doesn't hold. According
2149  * to this rule at any point where we access the HW or want to keep the HW in
2150  * an active state we must hold an RPM wakelock reference acquired via one of
2151  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2152  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2153  * forcewake release timer, and the GPU RPS and hangcheck works. All other
2154  * users should avoid using this function.
2155  *
2156  * Any calls to this function must have a symmetric call to
2157  * enable_rpm_wakeref_asserts().
2158  */
2159 static inline void
2160 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2161 {
2162         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2163 }
2164
2165 /**
2166  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2167  * @dev_priv: i915 device instance
2168  *
2169  * This function re-enables the RPM assert checks after disabling them with
2170  * disable_rpm_wakeref_asserts. It's meant to be used only in special
2171  * circumstances otherwise its use should be avoided.
2172  *
2173  * Any calls to this function must have a symmetric call to
2174  * disable_rpm_wakeref_asserts().
2175  */
2176 static inline void
2177 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2178 {
2179         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2180 }
2181
2182 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2183 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2184 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2185 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2186
2187 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2188                              bool override, unsigned int mask);
2189 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2190                           enum dpio_channel ch, bool override);
2191
2192
2193 /* intel_pm.c */
2194 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2195 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2196 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2197 void intel_update_watermarks(struct intel_crtc *crtc);
2198 void intel_init_pm(struct drm_i915_private *dev_priv);
2199 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2200 void intel_pm_setup(struct drm_i915_private *dev_priv);
2201 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2202 void intel_gpu_ips_teardown(void);
2203 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2204 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2205 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2206 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2207 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2208 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2209 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2210 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2211 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2212 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2213 void g4x_wm_get_hw_state(struct drm_device *dev);
2214 void vlv_wm_get_hw_state(struct drm_device *dev);
2215 void ilk_wm_get_hw_state(struct drm_device *dev);
2216 void skl_wm_get_hw_state(struct drm_device *dev);
2217 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
2218                                struct skl_ddb_entry *ddb_y,
2219                                struct skl_ddb_entry *ddb_uv);
2220 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2221                           struct skl_ddb_allocation *ddb /* out */);
2222 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2223                               struct skl_pipe_wm *out);
2224 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2225 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2226 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2227 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2228 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2229 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2230                          const struct skl_wm_level *l2);
2231 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
2232                                  const struct skl_ddb_entry entries[],
2233                                  int num_entries, int ignore_idx);
2234 void skl_write_plane_wm(struct intel_plane *plane,
2235                         const struct intel_crtc_state *crtc_state);
2236 void skl_write_cursor_wm(struct intel_plane *plane,
2237                          const struct intel_crtc_state *crtc_state);
2238 bool ilk_disable_lp_wm(struct drm_device *dev);
2239 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2240                                   struct intel_crtc_state *cstate);
2241 void intel_init_ipc(struct drm_i915_private *dev_priv);
2242 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2243
2244 /* intel_sdvo.c */
2245 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2246                              i915_reg_t sdvo_reg, enum pipe *pipe);
2247 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2248                      i915_reg_t reg, enum port port);
2249
2250
2251 /* intel_sprite.c */
2252 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2253                              int usecs);
2254 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2255                                               enum pipe pipe, int plane);
2256 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2257                                     struct drm_file *file_priv);
2258 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2259 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2260 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2261 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2262 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2263 struct intel_plane *
2264 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2265                            enum pipe pipe, enum plane_id plane_id);
2266
2267 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2268 {
2269         /* Don't need to do a gen check, these planes are only available on gen11 */
2270         if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2271                 return true;
2272
2273         return false;
2274 }
2275
2276 static inline bool icl_is_hdr_plane(struct intel_plane *plane)
2277 {
2278         if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
2279                 return false;
2280
2281         return plane->id < PLANE_SPRITE2;
2282 }
2283
2284 /* intel_tv.c */
2285 void intel_tv_init(struct drm_i915_private *dev_priv);
2286
2287 /* intel_atomic.c */
2288 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2289                                                 const struct drm_connector_state *state,
2290                                                 struct drm_property *property,
2291                                                 uint64_t *val);
2292 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2293                                                 struct drm_connector_state *state,
2294                                                 struct drm_property *property,
2295                                                 uint64_t val);
2296 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2297                                          struct drm_connector_state *new_state);
2298 struct drm_connector_state *
2299 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2300
2301 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2302 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2303                                struct drm_crtc_state *state);
2304 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2305 void intel_atomic_state_clear(struct drm_atomic_state *);
2306
2307 static inline struct intel_crtc_state *
2308 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2309                             struct intel_crtc *crtc)
2310 {
2311         struct drm_crtc_state *crtc_state;
2312         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2313         if (IS_ERR(crtc_state))
2314                 return ERR_CAST(crtc_state);
2315
2316         return to_intel_crtc_state(crtc_state);
2317 }
2318
2319 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2320                                struct intel_crtc *intel_crtc,
2321                                struct intel_crtc_state *crtc_state);
2322
2323 /* intel_atomic_plane.c */
2324 struct intel_plane *intel_plane_alloc(void);
2325 void intel_plane_free(struct intel_plane *plane);
2326 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2327 void intel_plane_destroy_state(struct drm_plane *plane,
2328                                struct drm_plane_state *state);
2329 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2330 void skl_update_planes_on_crtc(struct intel_atomic_state *state,
2331                                struct intel_crtc *crtc);
2332 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
2333                                 struct intel_crtc *crtc);
2334 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2335                                         struct intel_crtc_state *crtc_state,
2336                                         const struct intel_plane_state *old_plane_state,
2337                                         struct intel_plane_state *intel_state);
2338
2339 /* intel_color.c */
2340 void intel_color_init(struct drm_crtc *crtc);
2341 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2342 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2343 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2344
2345 /* intel_lspcon.c */
2346 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2347 void lspcon_resume(struct intel_lspcon *lspcon);
2348 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2349 void lspcon_write_infoframe(struct intel_encoder *encoder,
2350                             const struct intel_crtc_state *crtc_state,
2351                             unsigned int type,
2352                             const void *buf, ssize_t len);
2353 void lspcon_set_infoframes(struct intel_encoder *encoder,
2354                            bool enable,
2355                            const struct intel_crtc_state *crtc_state,
2356                            const struct drm_connector_state *conn_state);
2357 bool lspcon_infoframe_enabled(struct intel_encoder *encoder,
2358                               const struct intel_crtc_state *pipe_config);
2359 void lspcon_ycbcr420_config(struct drm_connector *connector,
2360                             struct intel_crtc_state *crtc_state);
2361
2362 /* intel_pipe_crc.c */
2363 #ifdef CONFIG_DEBUG_FS
2364 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2365 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2366                                  const char *source_name, size_t *values_cnt);
2367 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2368                                               size_t *count);
2369 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2370 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2371 #else
2372 #define intel_crtc_set_crc_source NULL
2373 #define intel_crtc_verify_crc_source NULL
2374 #define intel_crtc_get_crc_sources NULL
2375 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2376 {
2377 }
2378
2379 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2380 {
2381 }
2382 #endif
2383 #endif /* __INTEL_DRV_H__ */