Merge tag 'drm-intel-next-2019-01-10' of git://anongit.freedesktop.org/drm/drm-intel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_drv.h
1 /*
2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright (c) 2007-2008 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23  * IN THE SOFTWARE.
24  */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
33 #include "i915_drv.h"
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
42 #include <media/cec-notifier.h>
43
44 /**
45  * __wait_for - magic wait macro
46  *
47  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
48  * important that we check the condition again after having timed out, since the
49  * timeout could be due to preemption or similar and we've never had a chance to
50  * check the condition before the timeout.
51  */
52 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
53         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
54         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
55         int ret__;                                                      \
56         might_sleep();                                                  \
57         for (;;) {                                                      \
58                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
59                 OP;                                                     \
60                 /* Guarantee COND check prior to timeout */             \
61                 barrier();                                              \
62                 if (COND) {                                             \
63                         ret__ = 0;                                      \
64                         break;                                          \
65                 }                                                       \
66                 if (expired__) {                                        \
67                         ret__ = -ETIMEDOUT;                             \
68                         break;                                          \
69                 }                                                       \
70                 usleep_range(wait__, wait__ * 2);                       \
71                 if (wait__ < (Wmax))                                    \
72                         wait__ <<= 1;                                   \
73         }                                                               \
74         ret__;                                                          \
75 })
76
77 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
78                                                    (Wmax))
79 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
80
81 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
82 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
84 #else
85 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
86 #endif
87
88 #define _wait_for_atomic(COND, US, ATOMIC) \
89 ({ \
90         int cpu, ret, timeout = (US) * 1000; \
91         u64 base; \
92         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
93         if (!(ATOMIC)) { \
94                 preempt_disable(); \
95                 cpu = smp_processor_id(); \
96         } \
97         base = local_clock(); \
98         for (;;) { \
99                 u64 now = local_clock(); \
100                 if (!(ATOMIC)) \
101                         preempt_enable(); \
102                 /* Guarantee COND check prior to timeout */ \
103                 barrier(); \
104                 if (COND) { \
105                         ret = 0; \
106                         break; \
107                 } \
108                 if (now - base >= timeout) { \
109                         ret = -ETIMEDOUT; \
110                         break; \
111                 } \
112                 cpu_relax(); \
113                 if (!(ATOMIC)) { \
114                         preempt_disable(); \
115                         if (unlikely(cpu != smp_processor_id())) { \
116                                 timeout -= now - base; \
117                                 cpu = smp_processor_id(); \
118                                 base = local_clock(); \
119                         } \
120                 } \
121         } \
122         ret; \
123 })
124
125 #define wait_for_us(COND, US) \
126 ({ \
127         int ret__; \
128         BUILD_BUG_ON(!__builtin_constant_p(US)); \
129         if ((US) > 10) \
130                 ret__ = _wait_for((COND), (US), 10, 10); \
131         else \
132                 ret__ = _wait_for_atomic((COND), (US), 0); \
133         ret__; \
134 })
135
136 #define wait_for_atomic_us(COND, US) \
137 ({ \
138         BUILD_BUG_ON(!__builtin_constant_p(US)); \
139         BUILD_BUG_ON((US) > 50000); \
140         _wait_for_atomic((COND), (US), 1); \
141 })
142
143 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
144
145 #define KHz(x) (1000 * (x))
146 #define MHz(x) KHz(1000 * (x))
147
148 #define KBps(x) (1000 * (x))
149 #define MBps(x) KBps(1000 * (x))
150 #define GBps(x) ((u64)1000 * MBps((x)))
151
152 /*
153  * Display related stuff
154  */
155
156 /* store information about an Ixxx DVO */
157 /* The i830->i865 use multiple DVOs with multiple i2cs */
158 /* the i915, i945 have a single sDVO i2c bus - which is different */
159 #define MAX_OUTPUTS 6
160 /* maximum connectors per crtcs in the mode set */
161
162 #define INTEL_I2C_BUS_DVO 1
163 #define INTEL_I2C_BUS_SDVO 2
164
165 /* these are outputs from the chip - integrated only
166    external chips are via DVO or SDVO output */
167 enum intel_output_type {
168         INTEL_OUTPUT_UNUSED = 0,
169         INTEL_OUTPUT_ANALOG = 1,
170         INTEL_OUTPUT_DVO = 2,
171         INTEL_OUTPUT_SDVO = 3,
172         INTEL_OUTPUT_LVDS = 4,
173         INTEL_OUTPUT_TVOUT = 5,
174         INTEL_OUTPUT_HDMI = 6,
175         INTEL_OUTPUT_DP = 7,
176         INTEL_OUTPUT_EDP = 8,
177         INTEL_OUTPUT_DSI = 9,
178         INTEL_OUTPUT_DDI = 10,
179         INTEL_OUTPUT_DP_MST = 11,
180 };
181
182 #define INTEL_DVO_CHIP_NONE 0
183 #define INTEL_DVO_CHIP_LVDS 1
184 #define INTEL_DVO_CHIP_TMDS 2
185 #define INTEL_DVO_CHIP_TVOUT 4
186
187 #define INTEL_DSI_VIDEO_MODE    0
188 #define INTEL_DSI_COMMAND_MODE  1
189
190 struct intel_framebuffer {
191         struct drm_framebuffer base;
192         struct intel_rotation_info rot_info;
193
194         /* for each plane in the normal GTT view */
195         struct {
196                 unsigned int x, y;
197         } normal[2];
198         /* for each plane in the rotated GTT view */
199         struct {
200                 unsigned int x, y;
201                 unsigned int pitch; /* pixels */
202         } rotated[2];
203 };
204
205 struct intel_fbdev {
206         struct drm_fb_helper helper;
207         struct intel_framebuffer *fb;
208         struct i915_vma *vma;
209         unsigned long vma_flags;
210         async_cookie_t cookie;
211         int preferred_bpp;
212 };
213
214 struct intel_encoder {
215         struct drm_encoder base;
216
217         enum intel_output_type type;
218         enum port port;
219         unsigned int cloneable;
220         bool (*hotplug)(struct intel_encoder *encoder,
221                         struct intel_connector *connector);
222         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
223                                                       struct intel_crtc_state *,
224                                                       struct drm_connector_state *);
225         int (*compute_config)(struct intel_encoder *,
226                               struct intel_crtc_state *,
227                               struct drm_connector_state *);
228         void (*pre_pll_enable)(struct intel_encoder *,
229                                const struct intel_crtc_state *,
230                                const struct drm_connector_state *);
231         void (*pre_enable)(struct intel_encoder *,
232                            const struct intel_crtc_state *,
233                            const struct drm_connector_state *);
234         void (*enable)(struct intel_encoder *,
235                        const struct intel_crtc_state *,
236                        const struct drm_connector_state *);
237         void (*disable)(struct intel_encoder *,
238                         const struct intel_crtc_state *,
239                         const struct drm_connector_state *);
240         void (*post_disable)(struct intel_encoder *,
241                              const struct intel_crtc_state *,
242                              const struct drm_connector_state *);
243         void (*post_pll_disable)(struct intel_encoder *,
244                                  const struct intel_crtc_state *,
245                                  const struct drm_connector_state *);
246         void (*update_pipe)(struct intel_encoder *,
247                             const struct intel_crtc_state *,
248                             const struct drm_connector_state *);
249         /* Read out the current hw state of this connector, returning true if
250          * the encoder is active. If the encoder is enabled it also set the pipe
251          * it is connected to in the pipe parameter. */
252         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
253         /* Reconstructs the equivalent mode flags for the current hardware
254          * state. This must be called _after_ display->get_pipe_config has
255          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
256          * be set correctly before calling this function. */
257         void (*get_config)(struct intel_encoder *,
258                            struct intel_crtc_state *pipe_config);
259         /* Returns a mask of power domains that need to be referenced as part
260          * of the hardware state readout code. */
261         u64 (*get_power_domains)(struct intel_encoder *encoder,
262                                  struct intel_crtc_state *crtc_state);
263         /*
264          * Called during system suspend after all pending requests for the
265          * encoder are flushed (for example for DP AUX transactions) and
266          * device interrupts are disabled.
267          */
268         void (*suspend)(struct intel_encoder *);
269         int crtc_mask;
270         enum hpd_pin hpd_pin;
271         enum intel_display_power_domain power_domain;
272         /* for communication with audio component; protected by av_mutex */
273         const struct drm_connector *audio_connector;
274 };
275
276 struct intel_panel {
277         struct drm_display_mode *fixed_mode;
278         struct drm_display_mode *downclock_mode;
279
280         /* backlight */
281         struct {
282                 bool present;
283                 u32 level;
284                 u32 min;
285                 u32 max;
286                 bool enabled;
287                 bool combination_mode;  /* gen 2/4 only */
288                 bool active_low_pwm;
289                 bool alternate_pwm_increment;   /* lpt+ */
290
291                 /* PWM chip */
292                 bool util_pin_active_low;       /* bxt+ */
293                 u8 controller;          /* bxt+ only */
294                 struct pwm_device *pwm;
295
296                 struct backlight_device *device;
297
298                 /* Connector and platform specific backlight functions */
299                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
300                 uint32_t (*get)(struct intel_connector *connector);
301                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
302                 void (*disable)(const struct drm_connector_state *conn_state);
303                 void (*enable)(const struct intel_crtc_state *crtc_state,
304                                const struct drm_connector_state *conn_state);
305                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
306                                       uint32_t hz);
307                 void (*power)(struct intel_connector *, bool enable);
308         } backlight;
309 };
310
311 struct intel_digital_port;
312
313 /*
314  * This structure serves as a translation layer between the generic HDCP code
315  * and the bus-specific code. What that means is that HDCP over HDMI differs
316  * from HDCP over DP, so to account for these differences, we need to
317  * communicate with the receiver through this shim.
318  *
319  * For completeness, the 2 buses differ in the following ways:
320  *      - DP AUX vs. DDC
321  *              HDCP registers on the receiver are set via DP AUX for DP, and
322  *              they are set via DDC for HDMI.
323  *      - Receiver register offsets
324  *              The offsets of the registers are different for DP vs. HDMI
325  *      - Receiver register masks/offsets
326  *              For instance, the ready bit for the KSV fifo is in a different
327  *              place on DP vs HDMI
328  *      - Receiver register names
329  *              Seriously. In the DP spec, the 16-bit register containing
330  *              downstream information is called BINFO, on HDMI it's called
331  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
332  *              with a completely different definition.
333  *      - KSV FIFO
334  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
335  *              be read 3 keys at a time
336  *      - Aksv output
337  *              Since Aksv is hidden in hardware, there's different procedures
338  *              to send it over DP AUX vs DDC
339  */
340 struct intel_hdcp_shim {
341         /* Outputs the transmitter's An and Aksv values to the receiver. */
342         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
343
344         /* Reads the receiver's key selection vector */
345         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
346
347         /*
348          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
349          * definitions are the same in the respective specs, but the names are
350          * different. Call it BSTATUS since that's the name the HDMI spec
351          * uses and it was there first.
352          */
353         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
354                             u8 *bstatus);
355
356         /* Determines whether a repeater is present downstream */
357         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
358                                 bool *repeater_present);
359
360         /* Reads the receiver's Ri' value */
361         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
362
363         /* Determines if the receiver's KSV FIFO is ready for consumption */
364         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
365                               bool *ksv_ready);
366
367         /* Reads the ksv fifo for num_downstream devices */
368         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
369                              int num_downstream, u8 *ksv_fifo);
370
371         /* Reads a 32-bit part of V' from the receiver */
372         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
373                                  int i, u32 *part);
374
375         /* Enables HDCP signalling on the port */
376         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
377                                  bool enable);
378
379         /* Ensures the link is still protected */
380         bool (*check_link)(struct intel_digital_port *intel_dig_port);
381
382         /* Detects panel's hdcp capability. This is optional for HDMI. */
383         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
384                             bool *hdcp_capable);
385 };
386
387 struct intel_hdcp {
388         const struct intel_hdcp_shim *shim;
389         /* Mutex for hdcp state of the connector */
390         struct mutex mutex;
391         u64 value;
392         struct delayed_work check_work;
393         struct work_struct prop_work;
394 };
395
396 struct intel_connector {
397         struct drm_connector base;
398         /*
399          * The fixed encoder this connector is connected to.
400          */
401         struct intel_encoder *encoder;
402
403         /* ACPI device id for ACPI and driver cooperation */
404         u32 acpi_device_id;
405
406         /* Reads out the current hw, returning true if the connector is enabled
407          * and active (i.e. dpms ON state). */
408         bool (*get_hw_state)(struct intel_connector *);
409
410         /* Panel info for eDP and LVDS */
411         struct intel_panel panel;
412
413         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
414         struct edid *edid;
415         struct edid *detect_edid;
416
417         /* since POLL and HPD connectors may use the same HPD line keep the native
418            state of connector->polled in case hotplug storm detection changes it */
419         u8 polled;
420
421         void *port; /* store this opaque as its illegal to dereference it */
422
423         struct intel_dp *mst_port;
424
425         /* Work struct to schedule a uevent on link train failure */
426         struct work_struct modeset_retry_work;
427
428         struct intel_hdcp hdcp;
429 };
430
431 struct intel_digital_connector_state {
432         struct drm_connector_state base;
433
434         enum hdmi_force_audio force_audio;
435         int broadcast_rgb;
436 };
437
438 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
439
440 struct dpll {
441         /* given values */
442         int n;
443         int m1, m2;
444         int p1, p2;
445         /* derived values */
446         int     dot;
447         int     vco;
448         int     m;
449         int     p;
450 };
451
452 struct intel_atomic_state {
453         struct drm_atomic_state base;
454
455         struct {
456                 /*
457                  * Logical state of cdclk (used for all scaling, watermark,
458                  * etc. calculations and checks). This is computed as if all
459                  * enabled crtcs were active.
460                  */
461                 struct intel_cdclk_state logical;
462
463                 /*
464                  * Actual state of cdclk, can be different from the logical
465                  * state only when all crtc's are DPMS off.
466                  */
467                 struct intel_cdclk_state actual;
468         } cdclk;
469
470         bool dpll_set, modeset;
471
472         /*
473          * Does this transaction change the pipes that are active?  This mask
474          * tracks which CRTC's have changed their active state at the end of
475          * the transaction (not counting the temporary disable during modesets).
476          * This mask should only be non-zero when intel_state->modeset is true,
477          * but the converse is not necessarily true; simply changing a mode may
478          * not flip the final active status of any CRTC's
479          */
480         unsigned int active_pipe_changes;
481
482         unsigned int active_crtcs;
483         /* minimum acceptable cdclk for each pipe */
484         int min_cdclk[I915_MAX_PIPES];
485         /* minimum acceptable voltage level for each pipe */
486         u8 min_voltage_level[I915_MAX_PIPES];
487
488         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
489
490         /*
491          * Current watermarks can't be trusted during hardware readout, so
492          * don't bother calculating intermediate watermarks.
493          */
494         bool skip_intermediate_wm;
495
496         bool rps_interactive;
497
498         /* Gen9+ only */
499         struct skl_ddb_values wm_results;
500
501         struct i915_sw_fence commit_ready;
502
503         struct llist_node freed;
504 };
505
506 struct intel_plane_state {
507         struct drm_plane_state base;
508         struct i915_ggtt_view view;
509         struct i915_vma *vma;
510         unsigned long flags;
511 #define PLANE_HAS_FENCE BIT(0)
512
513         struct {
514                 u32 offset;
515                 /*
516                  * Plane stride in:
517                  * bytes for 0/180 degree rotation
518                  * pixels for 90/270 degree rotation
519                  */
520                 u32 stride;
521                 int x, y;
522         } color_plane[2];
523
524         /* plane control register */
525         u32 ctl;
526
527         /* plane color control register */
528         u32 color_ctl;
529
530         /*
531          * scaler_id
532          *    = -1 : not using a scaler
533          *    >=  0 : using a scalers
534          *
535          * plane requiring a scaler:
536          *   - During check_plane, its bit is set in
537          *     crtc_state->scaler_state.scaler_users by calling helper function
538          *     update_scaler_plane.
539          *   - scaler_id indicates the scaler it got assigned.
540          *
541          * plane doesn't require a scaler:
542          *   - this can happen when scaling is no more required or plane simply
543          *     got disabled.
544          *   - During check_plane, corresponding bit is reset in
545          *     crtc_state->scaler_state.scaler_users by calling helper function
546          *     update_scaler_plane.
547          */
548         int scaler_id;
549
550         /*
551          * linked_plane:
552          *
553          * ICL planar formats require 2 planes that are updated as pairs.
554          * This member is used to make sure the other plane is also updated
555          * when required, and for update_slave() to find the correct
556          * plane_state to pass as argument.
557          */
558         struct intel_plane *linked_plane;
559
560         /*
561          * slave:
562          * If set don't update use the linked plane's state for updating
563          * this plane during atomic commit with the update_slave() callback.
564          *
565          * It's also used by the watermark code to ignore wm calculations on
566          * this plane. They're calculated by the linked plane's wm code.
567          */
568         u32 slave;
569
570         struct drm_intel_sprite_colorkey ckey;
571 };
572
573 struct intel_initial_plane_config {
574         struct intel_framebuffer *fb;
575         unsigned int tiling;
576         int size;
577         u32 base;
578         u8 rotation;
579 };
580
581 #define SKL_MIN_SRC_W 8
582 #define SKL_MAX_SRC_W 4096
583 #define SKL_MIN_SRC_H 8
584 #define SKL_MAX_SRC_H 4096
585 #define SKL_MIN_DST_W 8
586 #define SKL_MAX_DST_W 4096
587 #define SKL_MIN_DST_H 8
588 #define SKL_MAX_DST_H 4096
589 #define ICL_MAX_SRC_W 5120
590 #define ICL_MAX_SRC_H 4096
591 #define ICL_MAX_DST_W 5120
592 #define ICL_MAX_DST_H 4096
593 #define SKL_MIN_YUV_420_SRC_W 16
594 #define SKL_MIN_YUV_420_SRC_H 16
595
596 struct intel_scaler {
597         int in_use;
598         uint32_t mode;
599 };
600
601 struct intel_crtc_scaler_state {
602 #define SKL_NUM_SCALERS 2
603         struct intel_scaler scalers[SKL_NUM_SCALERS];
604
605         /*
606          * scaler_users: keeps track of users requesting scalers on this crtc.
607          *
608          *     If a bit is set, a user is using a scaler.
609          *     Here user can be a plane or crtc as defined below:
610          *       bits 0-30 - plane (bit position is index from drm_plane_index)
611          *       bit 31    - crtc
612          *
613          * Instead of creating a new index to cover planes and crtc, using
614          * existing drm_plane_index for planes which is well less than 31
615          * planes and bit 31 for crtc. This should be fine to cover all
616          * our platforms.
617          *
618          * intel_atomic_setup_scalers will setup available scalers to users
619          * requesting scalers. It will gracefully fail if request exceeds
620          * avilability.
621          */
622 #define SKL_CRTC_INDEX 31
623         unsigned scaler_users;
624
625         /* scaler used by crtc for panel fitting purpose */
626         int scaler_id;
627 };
628
629 /* drm_mode->private_flags */
630 #define I915_MODE_FLAG_INHERITED 1
631 /* Flag to get scanline using frame time stamps */
632 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
633
634 struct intel_pipe_wm {
635         struct intel_wm_level wm[5];
636         uint32_t linetime;
637         bool fbc_wm_enabled;
638         bool pipe_enabled;
639         bool sprites_enabled;
640         bool sprites_scaled;
641 };
642
643 struct skl_plane_wm {
644         struct skl_wm_level wm[8];
645         struct skl_wm_level uv_wm[8];
646         struct skl_wm_level trans_wm;
647         bool is_planar;
648 };
649
650 struct skl_pipe_wm {
651         struct skl_plane_wm planes[I915_MAX_PLANES];
652         uint32_t linetime;
653 };
654
655 enum vlv_wm_level {
656         VLV_WM_LEVEL_PM2,
657         VLV_WM_LEVEL_PM5,
658         VLV_WM_LEVEL_DDR_DVFS,
659         NUM_VLV_WM_LEVELS,
660 };
661
662 struct vlv_wm_state {
663         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
664         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
665         uint8_t num_levels;
666         bool cxsr;
667 };
668
669 struct vlv_fifo_state {
670         u16 plane[I915_MAX_PLANES];
671 };
672
673 enum g4x_wm_level {
674         G4X_WM_LEVEL_NORMAL,
675         G4X_WM_LEVEL_SR,
676         G4X_WM_LEVEL_HPLL,
677         NUM_G4X_WM_LEVELS,
678 };
679
680 struct g4x_wm_state {
681         struct g4x_pipe_wm wm;
682         struct g4x_sr_wm sr;
683         struct g4x_sr_wm hpll;
684         bool cxsr;
685         bool hpll_en;
686         bool fbc_en;
687 };
688
689 struct intel_crtc_wm_state {
690         union {
691                 struct {
692                         /*
693                          * Intermediate watermarks; these can be
694                          * programmed immediately since they satisfy
695                          * both the current configuration we're
696                          * switching away from and the new
697                          * configuration we're switching to.
698                          */
699                         struct intel_pipe_wm intermediate;
700
701                         /*
702                          * Optimal watermarks, programmed post-vblank
703                          * when this state is committed.
704                          */
705                         struct intel_pipe_wm optimal;
706                 } ilk;
707
708                 struct {
709                         /* gen9+ only needs 1-step wm programming */
710                         struct skl_pipe_wm optimal;
711                         struct skl_ddb_entry ddb;
712                         struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
713                         struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
714                 } skl;
715
716                 struct {
717                         /* "raw" watermarks (not inverted) */
718                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
719                         /* intermediate watermarks (inverted) */
720                         struct vlv_wm_state intermediate;
721                         /* optimal watermarks (inverted) */
722                         struct vlv_wm_state optimal;
723                         /* display FIFO split */
724                         struct vlv_fifo_state fifo_state;
725                 } vlv;
726
727                 struct {
728                         /* "raw" watermarks */
729                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
730                         /* intermediate watermarks */
731                         struct g4x_wm_state intermediate;
732                         /* optimal watermarks */
733                         struct g4x_wm_state optimal;
734                 } g4x;
735         };
736
737         /*
738          * Platforms with two-step watermark programming will need to
739          * update watermark programming post-vblank to switch from the
740          * safe intermediate watermarks to the optimal final
741          * watermarks.
742          */
743         bool need_postvbl_update;
744 };
745
746 enum intel_output_format {
747         INTEL_OUTPUT_FORMAT_INVALID,
748         INTEL_OUTPUT_FORMAT_RGB,
749         INTEL_OUTPUT_FORMAT_YCBCR420,
750         INTEL_OUTPUT_FORMAT_YCBCR444,
751 };
752
753 struct intel_crtc_state {
754         struct drm_crtc_state base;
755
756         /**
757          * quirks - bitfield with hw state readout quirks
758          *
759          * For various reasons the hw state readout code might not be able to
760          * completely faithfully read out the current state. These cases are
761          * tracked with quirk flags so that fastboot and state checker can act
762          * accordingly.
763          */
764 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
765         unsigned long quirks;
766
767         unsigned fb_bits; /* framebuffers to flip */
768         bool update_pipe; /* can a fast modeset be performed? */
769         bool disable_cxsr;
770         bool update_wm_pre, update_wm_post; /* watermarks are updated */
771         bool fb_changed; /* fb on any of the planes is changed */
772         bool fifo_changed; /* FIFO split is changed */
773
774         /* Pipe source size (ie. panel fitter input size)
775          * All planes will be positioned inside this space,
776          * and get clipped at the edges. */
777         int pipe_src_w, pipe_src_h;
778
779         /*
780          * Pipe pixel rate, adjusted for
781          * panel fitter/pipe scaler downscaling.
782          */
783         unsigned int pixel_rate;
784
785         /* Whether to set up the PCH/FDI. Note that we never allow sharing
786          * between pch encoders and cpu encoders. */
787         bool has_pch_encoder;
788
789         /* Are we sending infoframes on the attached port */
790         bool has_infoframe;
791
792         /* CPU Transcoder for the pipe. Currently this can only differ from the
793          * pipe on Haswell and later (where we have a special eDP transcoder)
794          * and Broxton (where we have special DSI transcoders). */
795         enum transcoder cpu_transcoder;
796
797         /*
798          * Use reduced/limited/broadcast rbg range, compressing from the full
799          * range fed into the crtcs.
800          */
801         bool limited_color_range;
802
803         /* Bitmask of encoder types (enum intel_output_type)
804          * driven by the pipe.
805          */
806         unsigned int output_types;
807
808         /* Whether we should send NULL infoframes. Required for audio. */
809         bool has_hdmi_sink;
810
811         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
812          * has_dp_encoder is set. */
813         bool has_audio;
814
815         /*
816          * Enable dithering, used when the selected pipe bpp doesn't match the
817          * plane bpp.
818          */
819         bool dither;
820
821         /*
822          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
823          * compliance video pattern tests.
824          * Disable dither only if it is a compliance test request for
825          * 18bpp.
826          */
827         bool dither_force_disable;
828
829         /* Controls for the clock computation, to override various stages. */
830         bool clock_set;
831
832         /* SDVO TV has a bunch of special case. To make multifunction encoders
833          * work correctly, we need to track this at runtime.*/
834         bool sdvo_tv_clock;
835
836         /*
837          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
838          * required. This is set in the 2nd loop of calling encoder's
839          * ->compute_config if the first pick doesn't work out.
840          */
841         bool bw_constrained;
842
843         /* Settings for the intel dpll used on pretty much everything but
844          * haswell. */
845         struct dpll dpll;
846
847         /* Selected dpll when shared or NULL. */
848         struct intel_shared_dpll *shared_dpll;
849
850         /* Actual register state of the dpll, for shared dpll cross-checking. */
851         struct intel_dpll_hw_state dpll_hw_state;
852
853         /* DSI PLL registers */
854         struct {
855                 u32 ctrl, div;
856         } dsi_pll;
857
858         int pipe_bpp;
859         struct intel_link_m_n dp_m_n;
860
861         /* m2_n2 for eDP downclock */
862         struct intel_link_m_n dp_m2_n2;
863         bool has_drrs;
864
865         bool has_psr;
866         bool has_psr2;
867
868         /*
869          * Frequence the dpll for the port should run at. Differs from the
870          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
871          * already multiplied by pixel_multiplier.
872          */
873         int port_clock;
874
875         /* Used by SDVO (and if we ever fix it, HDMI). */
876         unsigned pixel_multiplier;
877
878         uint8_t lane_count;
879
880         /*
881          * Used by platforms having DP/HDMI PHY with programmable lane
882          * latency optimization.
883          */
884         uint8_t lane_lat_optim_mask;
885
886         /* minimum acceptable voltage level */
887         u8 min_voltage_level;
888
889         /* Panel fitter controls for gen2-gen4 + VLV */
890         struct {
891                 u32 control;
892                 u32 pgm_ratios;
893                 u32 lvds_border_bits;
894         } gmch_pfit;
895
896         /* Panel fitter placement and size for Ironlake+ */
897         struct {
898                 u32 pos;
899                 u32 size;
900                 bool enabled;
901                 bool force_thru;
902         } pch_pfit;
903
904         /* FDI configuration, only valid if has_pch_encoder is set. */
905         int fdi_lanes;
906         struct intel_link_m_n fdi_m_n;
907
908         bool ips_enabled;
909         bool ips_force_disable;
910
911         bool enable_fbc;
912
913         bool double_wide;
914
915         int pbn;
916
917         struct intel_crtc_scaler_state scaler_state;
918
919         /* w/a for waiting 2 vblanks during crtc enable */
920         enum pipe hsw_workaround_pipe;
921
922         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
923         bool disable_lp_wm;
924
925         struct intel_crtc_wm_state wm;
926
927         /* Gamma mode programmed on the pipe */
928         uint32_t gamma_mode;
929
930         /* bitmask of visible planes (enum plane_id) */
931         u8 active_planes;
932         u8 nv12_planes;
933
934         /* bitmask of planes that will be updated during the commit */
935         u8 update_planes;
936
937         /* HDMI scrambling status */
938         bool hdmi_scrambling;
939
940         /* HDMI High TMDS char rate ratio */
941         bool hdmi_high_tmds_clock_ratio;
942
943         /* Output format RGB/YCBCR etc */
944         enum intel_output_format output_format;
945
946         /* Output down scaling is done in LSPCON device */
947         bool lspcon_downsampling;
948
949         /* Display Stream compression state */
950         struct {
951                 bool compression_enable;
952                 bool dsc_split;
953                 u16 compressed_bpp;
954                 u8 slice_count;
955         } dsc_params;
956         struct drm_dsc_config dp_dsc_cfg;
957
958         /* Forward Error correction State */
959         bool fec_enable;
960 };
961
962 struct intel_crtc {
963         struct drm_crtc base;
964         enum pipe pipe;
965         /*
966          * Whether the crtc and the connected output pipeline is active. Implies
967          * that crtc->enabled is set, i.e. the current mode configuration has
968          * some outputs connected to this crtc.
969          */
970         bool active;
971         u8 plane_ids_mask;
972         unsigned long long enabled_power_domains;
973         struct intel_overlay *overlay;
974
975         struct intel_crtc_state *config;
976
977         /* global reset count when the last flip was submitted */
978         unsigned int reset_count;
979
980         /* Access to these should be protected by dev_priv->irq_lock. */
981         bool cpu_fifo_underrun_disabled;
982         bool pch_fifo_underrun_disabled;
983
984         /* per-pipe watermark state */
985         struct {
986                 /* watermarks currently being used  */
987                 union {
988                         struct intel_pipe_wm ilk;
989                         struct vlv_wm_state vlv;
990                         struct g4x_wm_state g4x;
991                 } active;
992         } wm;
993
994         int scanline_offset;
995
996         struct {
997                 unsigned start_vbl_count;
998                 ktime_t start_vbl_time;
999                 int min_vbl, max_vbl;
1000                 int scanline_start;
1001         } debug;
1002
1003         /* scalers available on this crtc */
1004         int num_scalers;
1005 };
1006
1007 struct intel_plane {
1008         struct drm_plane base;
1009         enum i9xx_plane_id i9xx_plane;
1010         enum plane_id id;
1011         enum pipe pipe;
1012         bool has_fbc;
1013         bool has_ccs;
1014         uint32_t frontbuffer_bit;
1015
1016         struct {
1017                 u32 base, cntl, size;
1018         } cursor;
1019
1020         /*
1021          * NOTE: Do not place new plane state fields here (e.g., when adding
1022          * new plane properties).  New runtime state should now be placed in
1023          * the intel_plane_state structure and accessed via plane_state.
1024          */
1025
1026         unsigned int (*max_stride)(struct intel_plane *plane,
1027                                    u32 pixel_format, u64 modifier,
1028                                    unsigned int rotation);
1029         void (*update_plane)(struct intel_plane *plane,
1030                              const struct intel_crtc_state *crtc_state,
1031                              const struct intel_plane_state *plane_state);
1032         void (*update_slave)(struct intel_plane *plane,
1033                              const struct intel_crtc_state *crtc_state,
1034                              const struct intel_plane_state *plane_state);
1035         void (*disable_plane)(struct intel_plane *plane,
1036                               const struct intel_crtc_state *crtc_state);
1037         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1038         int (*check_plane)(struct intel_crtc_state *crtc_state,
1039                            struct intel_plane_state *plane_state);
1040 };
1041
1042 struct intel_watermark_params {
1043         u16 fifo_size;
1044         u16 max_wm;
1045         u8 default_wm;
1046         u8 guard_size;
1047         u8 cacheline_size;
1048 };
1049
1050 struct cxsr_latency {
1051         bool is_desktop : 1;
1052         bool is_ddr3 : 1;
1053         u16 fsb_freq;
1054         u16 mem_freq;
1055         u16 display_sr;
1056         u16 display_hpll_disable;
1057         u16 cursor_sr;
1058         u16 cursor_hpll_disable;
1059 };
1060
1061 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1062 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1063 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1064 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1065 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1066 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1067 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1068 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1069 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1070
1071 struct intel_hdmi {
1072         i915_reg_t hdmi_reg;
1073         int ddc_bus;
1074         struct {
1075                 enum drm_dp_dual_mode_type type;
1076                 int max_tmds_clock;
1077         } dp_dual_mode;
1078         bool has_hdmi_sink;
1079         bool has_audio;
1080         struct intel_connector *attached_connector;
1081         struct cec_notifier *cec_notifier;
1082 };
1083
1084 struct intel_dp_mst_encoder;
1085 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1086
1087 /*
1088  * enum link_m_n_set:
1089  *      When platform provides two set of M_N registers for dp, we can
1090  *      program them and switch between them incase of DRRS.
1091  *      But When only one such register is provided, we have to program the
1092  *      required divider value on that registers itself based on the DRRS state.
1093  *
1094  * M1_N1        : Program dp_m_n on M1_N1 registers
1095  *                        dp_m2_n2 on M2_N2 registers (If supported)
1096  *
1097  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1098  *                        M2_N2 registers are not supported
1099  */
1100
1101 enum link_m_n_set {
1102         /* Sets the m1_n1 and m2_n2 */
1103         M1_N1 = 0,
1104         M2_N2
1105 };
1106
1107 struct intel_dp_compliance_data {
1108         unsigned long edid;
1109         uint8_t video_pattern;
1110         uint16_t hdisplay, vdisplay;
1111         uint8_t bpc;
1112 };
1113
1114 struct intel_dp_compliance {
1115         unsigned long test_type;
1116         struct intel_dp_compliance_data test_data;
1117         bool test_active;
1118         int test_link_rate;
1119         u8 test_lane_count;
1120 };
1121
1122 struct intel_dp {
1123         i915_reg_t output_reg;
1124         uint32_t DP;
1125         int link_rate;
1126         uint8_t lane_count;
1127         uint8_t sink_count;
1128         bool link_mst;
1129         bool link_trained;
1130         bool has_audio;
1131         bool reset_link_params;
1132         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1133         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1134         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1135         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1136         u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1137         u8 fec_capable;
1138         /* source rates */
1139         int num_source_rates;
1140         const int *source_rates;
1141         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1142         int num_sink_rates;
1143         int sink_rates[DP_MAX_SUPPORTED_RATES];
1144         bool use_rate_select;
1145         /* intersection of source and sink rates */
1146         int num_common_rates;
1147         int common_rates[DP_MAX_SUPPORTED_RATES];
1148         /* Max lane count for the current link */
1149         int max_link_lane_count;
1150         /* Max rate for the current link */
1151         int max_link_rate;
1152         /* sink or branch descriptor */
1153         struct drm_dp_desc desc;
1154         struct drm_dp_aux aux;
1155         uint8_t train_set[4];
1156         int panel_power_up_delay;
1157         int panel_power_down_delay;
1158         int panel_power_cycle_delay;
1159         int backlight_on_delay;
1160         int backlight_off_delay;
1161         struct delayed_work panel_vdd_work;
1162         bool want_panel_vdd;
1163         unsigned long last_power_on;
1164         unsigned long last_backlight_off;
1165         ktime_t panel_power_off_time;
1166
1167         struct notifier_block edp_notifier;
1168
1169         /*
1170          * Pipe whose power sequencer is currently locked into
1171          * this port. Only relevant on VLV/CHV.
1172          */
1173         enum pipe pps_pipe;
1174         /*
1175          * Pipe currently driving the port. Used for preventing
1176          * the use of the PPS for any pipe currentrly driving
1177          * external DP as that will mess things up on VLV.
1178          */
1179         enum pipe active_pipe;
1180         /*
1181          * Set if the sequencer may be reset due to a power transition,
1182          * requiring a reinitialization. Only relevant on BXT.
1183          */
1184         bool pps_reset;
1185         struct edp_power_seq pps_delays;
1186
1187         bool can_mst; /* this port supports mst */
1188         bool is_mst;
1189         int active_mst_links;
1190         /* connector directly attached - won't be use for modeset in mst world */
1191         struct intel_connector *attached_connector;
1192
1193         /* mst connector list */
1194         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1195         struct drm_dp_mst_topology_mgr mst_mgr;
1196
1197         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1198         /*
1199          * This function returns the value we have to program the AUX_CTL
1200          * register with to kick off an AUX transaction.
1201          */
1202         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1203                                      int send_bytes,
1204                                      uint32_t aux_clock_divider);
1205
1206         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1207         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1208
1209         /* This is called before a link training is starterd */
1210         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1211
1212         /* Displayport compliance testing */
1213         struct intel_dp_compliance compliance;
1214
1215         /* Display stream compression testing */
1216         bool force_dsc_en;
1217 };
1218
1219 enum lspcon_vendor {
1220         LSPCON_VENDOR_MCA,
1221         LSPCON_VENDOR_PARADE
1222 };
1223
1224 struct intel_lspcon {
1225         bool active;
1226         enum drm_lspcon_mode mode;
1227         enum lspcon_vendor vendor;
1228 };
1229
1230 struct intel_digital_port {
1231         struct intel_encoder base;
1232         u32 saved_port_bits;
1233         struct intel_dp dp;
1234         struct intel_hdmi hdmi;
1235         struct intel_lspcon lspcon;
1236         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1237         bool release_cl2_override;
1238         uint8_t max_lanes;
1239         /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1240         enum aux_ch aux_ch;
1241         enum intel_display_power_domain ddi_io_power_domain;
1242         bool tc_legacy_port:1;
1243         enum tc_port_type tc_type;
1244
1245         void (*write_infoframe)(struct intel_encoder *encoder,
1246                                 const struct intel_crtc_state *crtc_state,
1247                                 unsigned int type,
1248                                 const void *frame, ssize_t len);
1249         void (*set_infoframes)(struct intel_encoder *encoder,
1250                                bool enable,
1251                                const struct intel_crtc_state *crtc_state,
1252                                const struct drm_connector_state *conn_state);
1253         bool (*infoframe_enabled)(struct intel_encoder *encoder,
1254                                   const struct intel_crtc_state *pipe_config);
1255 };
1256
1257 struct intel_dp_mst_encoder {
1258         struct intel_encoder base;
1259         enum pipe pipe;
1260         struct intel_digital_port *primary;
1261         struct intel_connector *connector;
1262 };
1263
1264 static inline enum dpio_channel
1265 vlv_dport_to_channel(struct intel_digital_port *dport)
1266 {
1267         switch (dport->base.port) {
1268         case PORT_B:
1269         case PORT_D:
1270                 return DPIO_CH0;
1271         case PORT_C:
1272                 return DPIO_CH1;
1273         default:
1274                 BUG();
1275         }
1276 }
1277
1278 static inline enum dpio_phy
1279 vlv_dport_to_phy(struct intel_digital_port *dport)
1280 {
1281         switch (dport->base.port) {
1282         case PORT_B:
1283         case PORT_C:
1284                 return DPIO_PHY0;
1285         case PORT_D:
1286                 return DPIO_PHY1;
1287         default:
1288                 BUG();
1289         }
1290 }
1291
1292 static inline enum dpio_channel
1293 vlv_pipe_to_channel(enum pipe pipe)
1294 {
1295         switch (pipe) {
1296         case PIPE_A:
1297         case PIPE_C:
1298                 return DPIO_CH0;
1299         case PIPE_B:
1300                 return DPIO_CH1;
1301         default:
1302                 BUG();
1303         }
1304 }
1305
1306 static inline struct intel_crtc *
1307 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1308 {
1309         return dev_priv->pipe_to_crtc_mapping[pipe];
1310 }
1311
1312 static inline struct intel_crtc *
1313 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1314 {
1315         return dev_priv->plane_to_crtc_mapping[plane];
1316 }
1317
1318 struct intel_load_detect_pipe {
1319         struct drm_atomic_state *restore_state;
1320 };
1321
1322 static inline struct intel_encoder *
1323 intel_attached_encoder(struct drm_connector *connector)
1324 {
1325         return to_intel_connector(connector)->encoder;
1326 }
1327
1328 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1329 {
1330         switch (encoder->type) {
1331         case INTEL_OUTPUT_DDI:
1332         case INTEL_OUTPUT_DP:
1333         case INTEL_OUTPUT_EDP:
1334         case INTEL_OUTPUT_HDMI:
1335                 return true;
1336         default:
1337                 return false;
1338         }
1339 }
1340
1341 static inline struct intel_digital_port *
1342 enc_to_dig_port(struct drm_encoder *encoder)
1343 {
1344         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1345
1346         if (intel_encoder_is_dig_port(intel_encoder))
1347                 return container_of(encoder, struct intel_digital_port,
1348                                     base.base);
1349         else
1350                 return NULL;
1351 }
1352
1353 static inline struct intel_digital_port *
1354 conn_to_dig_port(struct intel_connector *connector)
1355 {
1356         return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1357 }
1358
1359 static inline struct intel_dp_mst_encoder *
1360 enc_to_mst(struct drm_encoder *encoder)
1361 {
1362         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1363 }
1364
1365 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1366 {
1367         return &enc_to_dig_port(encoder)->dp;
1368 }
1369
1370 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1371 {
1372         switch (encoder->type) {
1373         case INTEL_OUTPUT_DP:
1374         case INTEL_OUTPUT_EDP:
1375                 return true;
1376         case INTEL_OUTPUT_DDI:
1377                 /* Skip pure HDMI/DVI DDI encoders */
1378                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1379         default:
1380                 return false;
1381         }
1382 }
1383
1384 static inline struct intel_lspcon *
1385 enc_to_intel_lspcon(struct drm_encoder *encoder)
1386 {
1387         return &enc_to_dig_port(encoder)->lspcon;
1388 }
1389
1390 static inline struct intel_digital_port *
1391 dp_to_dig_port(struct intel_dp *intel_dp)
1392 {
1393         return container_of(intel_dp, struct intel_digital_port, dp);
1394 }
1395
1396 static inline struct intel_lspcon *
1397 dp_to_lspcon(struct intel_dp *intel_dp)
1398 {
1399         return &dp_to_dig_port(intel_dp)->lspcon;
1400 }
1401
1402 static inline struct drm_i915_private *
1403 dp_to_i915(struct intel_dp *intel_dp)
1404 {
1405         return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1406 }
1407
1408 static inline struct intel_digital_port *
1409 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1410 {
1411         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1412 }
1413
1414 static inline struct intel_plane_state *
1415 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1416                                  struct intel_plane *plane)
1417 {
1418         struct drm_plane_state *ret =
1419                 drm_atomic_get_plane_state(&state->base, &plane->base);
1420
1421         if (IS_ERR(ret))
1422                 return ERR_CAST(ret);
1423
1424         return to_intel_plane_state(ret);
1425 }
1426
1427 static inline struct intel_plane_state *
1428 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1429                                  struct intel_plane *plane)
1430 {
1431         return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1432                                                                    &plane->base));
1433 }
1434
1435 static inline struct intel_plane_state *
1436 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1437                                  struct intel_plane *plane)
1438 {
1439         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1440                                                                    &plane->base));
1441 }
1442
1443 static inline struct intel_crtc_state *
1444 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1445                                 struct intel_crtc *crtc)
1446 {
1447         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1448                                                                  &crtc->base));
1449 }
1450
1451 static inline struct intel_crtc_state *
1452 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1453                                 struct intel_crtc *crtc)
1454 {
1455         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1456                                                                  &crtc->base));
1457 }
1458
1459 /* intel_fifo_underrun.c */
1460 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1461                                            enum pipe pipe, bool enable);
1462 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1463                                            enum pipe pch_transcoder,
1464                                            bool enable);
1465 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1466                                          enum pipe pipe);
1467 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1468                                          enum pipe pch_transcoder);
1469 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1470 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1471
1472 /* i915_irq.c */
1473 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1474 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1475 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1476 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1477 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1478 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1479 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1480 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1481
1482 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1483                                             u32 mask)
1484 {
1485         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1486 }
1487
1488 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1489 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1490 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1491 {
1492         /*
1493          * We only use drm_irq_uninstall() at unload and VT switch, so
1494          * this is the only thing we need to check.
1495          */
1496         return dev_priv->runtime_pm.irqs_enabled;
1497 }
1498
1499 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1500 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1501                                      u8 pipe_mask);
1502 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1503                                      u8 pipe_mask);
1504 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1505 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1506 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1507
1508 /* intel_crt.c */
1509 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1510                             i915_reg_t adpa_reg, enum pipe *pipe);
1511 void intel_crt_init(struct drm_i915_private *dev_priv);
1512 void intel_crt_reset(struct drm_encoder *encoder);
1513
1514 /* intel_ddi.c */
1515 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1516                                 const struct intel_crtc_state *old_crtc_state,
1517                                 const struct drm_connector_state *old_conn_state);
1518 void hsw_fdi_link_train(struct intel_crtc *crtc,
1519                         const struct intel_crtc_state *crtc_state);
1520 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1521 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1522 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1523 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1524 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1525 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1526 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1527 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1528 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1529 void intel_ddi_get_config(struct intel_encoder *encoder,
1530                           struct intel_crtc_state *pipe_config);
1531
1532 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1533                                     bool state);
1534 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1535                                          struct intel_crtc_state *crtc_state);
1536 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1537 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1538 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1539 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1540                                  u8 voltage_swing);
1541 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1542                                      bool enable);
1543 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
1544 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1545                         enum intel_dpll_id pll_id);
1546
1547 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1548                                    int color_plane, unsigned int height);
1549
1550 /* intel_audio.c */
1551 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1552 void intel_audio_codec_enable(struct intel_encoder *encoder,
1553                               const struct intel_crtc_state *crtc_state,
1554                               const struct drm_connector_state *conn_state);
1555 void intel_audio_codec_disable(struct intel_encoder *encoder,
1556                                const struct intel_crtc_state *old_crtc_state,
1557                                const struct drm_connector_state *old_conn_state);
1558 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1559 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1560 void intel_audio_init(struct drm_i915_private *dev_priv);
1561 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1562
1563 /* intel_cdclk.c */
1564 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1565 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1566 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1567 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1568 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1569 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1570 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1571 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1572 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1573 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1574 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1575 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1576 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1577 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1578                                const struct intel_cdclk_state *b);
1579 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1580                          const struct intel_cdclk_state *b);
1581 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1582                      const struct intel_cdclk_state *cdclk_state);
1583 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1584                             const char *context);
1585
1586 /* intel_display.c */
1587 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1588 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1589 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1590 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1591 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1592                       const char *name, u32 reg, int ref_freq);
1593 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1594                            const char *name, u32 reg);
1595 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1596 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1597 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1598 unsigned int intel_fb_xy_to_linear(int x, int y,
1599                                    const struct intel_plane_state *state,
1600                                    int plane);
1601 void intel_add_fb_offsets(int *x, int *y,
1602                           const struct intel_plane_state *state, int plane);
1603 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1604 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1605 void intel_mark_busy(struct drm_i915_private *dev_priv);
1606 void intel_mark_idle(struct drm_i915_private *dev_priv);
1607 int intel_display_suspend(struct drm_device *dev);
1608 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1609 void intel_encoder_destroy(struct drm_encoder *encoder);
1610 struct drm_display_mode *
1611 intel_encoder_current_mode(struct intel_encoder *encoder);
1612 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1613 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1614 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1615                               enum port port);
1616 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1617                                       struct drm_file *file_priv);
1618 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1619                                              enum pipe pipe);
1620 static inline bool
1621 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1622                     enum intel_output_type type)
1623 {
1624         return crtc_state->output_types & (1 << type);
1625 }
1626 static inline bool
1627 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1628 {
1629         return crtc_state->output_types &
1630                 ((1 << INTEL_OUTPUT_DP) |
1631                  (1 << INTEL_OUTPUT_DP_MST) |
1632                  (1 << INTEL_OUTPUT_EDP));
1633 }
1634 static inline void
1635 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1636 {
1637         drm_wait_one_vblank(&dev_priv->drm, pipe);
1638 }
1639 static inline void
1640 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1641 {
1642         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1643
1644         if (crtc->active)
1645                 intel_wait_for_vblank(dev_priv, pipe);
1646 }
1647
1648 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1649
1650 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1651 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1652                          struct intel_digital_port *dport,
1653                          unsigned int expected_mask);
1654 int intel_get_load_detect_pipe(struct drm_connector *connector,
1655                                const struct drm_display_mode *mode,
1656                                struct intel_load_detect_pipe *old,
1657                                struct drm_modeset_acquire_ctx *ctx);
1658 void intel_release_load_detect_pipe(struct drm_connector *connector,
1659                                     struct intel_load_detect_pipe *old,
1660                                     struct drm_modeset_acquire_ctx *ctx);
1661 struct i915_vma *
1662 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1663                            const struct i915_ggtt_view *view,
1664                            bool uses_fence,
1665                            unsigned long *out_flags);
1666 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1667 struct drm_framebuffer *
1668 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1669                          struct drm_mode_fb_cmd2 *mode_cmd);
1670 int intel_prepare_plane_fb(struct drm_plane *plane,
1671                            struct drm_plane_state *new_state);
1672 void intel_cleanup_plane_fb(struct drm_plane *plane,
1673                             struct drm_plane_state *old_state);
1674 int intel_plane_atomic_get_property(struct drm_plane *plane,
1675                                     const struct drm_plane_state *state,
1676                                     struct drm_property *property,
1677                                     uint64_t *val);
1678 int intel_plane_atomic_set_property(struct drm_plane *plane,
1679                                     struct drm_plane_state *state,
1680                                     struct drm_property *property,
1681                                     uint64_t val);
1682 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1683                                     struct drm_crtc_state *crtc_state,
1684                                     const struct intel_plane_state *old_plane_state,
1685                                     struct drm_plane_state *plane_state);
1686
1687 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1688                                     enum pipe pipe);
1689
1690 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1691                      const struct dpll *dpll);
1692 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1693 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1694
1695 /* modesetting asserts */
1696 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1697                            enum pipe pipe);
1698 void assert_pll(struct drm_i915_private *dev_priv,
1699                 enum pipe pipe, bool state);
1700 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1701 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1702 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1703 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1704 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1705 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1706                        enum pipe pipe, bool state);
1707 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1708 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1709 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1710 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1711 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1712 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1713 void intel_finish_reset(struct drm_i915_private *dev_priv);
1714 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1715 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1716 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1717 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1718 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1719 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1720 unsigned int skl_cdclk_get_vco(unsigned int freq);
1721 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1722 void intel_dp_get_m_n(struct intel_crtc *crtc,
1723                       struct intel_crtc_state *pipe_config);
1724 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1725                       enum link_m_n_set m_n);
1726 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1727 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1728                         struct dpll *best_clock);
1729 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1730
1731 bool intel_crtc_active(struct intel_crtc *crtc);
1732 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1733 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1734 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1735 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1736 enum intel_display_power_domain
1737 intel_aux_power_domain(struct intel_digital_port *dig_port);
1738 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1739                                  struct intel_crtc_state *pipe_config);
1740 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1741                                   struct intel_crtc_state *crtc_state);
1742
1743 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1744 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1745 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1746                   u32 pixel_format);
1747
1748 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1749 {
1750         return i915_ggtt_offset(state->vma);
1751 }
1752
1753 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1754                         const struct intel_plane_state *plane_state);
1755 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1756                   const struct intel_plane_state *plane_state);
1757 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1758 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1759                      int plane);
1760 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1761 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1762 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1763 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1764                                    u32 pixel_format, u64 modifier,
1765                                    unsigned int rotation);
1766
1767 /* intel_connector.c */
1768 int intel_connector_init(struct intel_connector *connector);
1769 struct intel_connector *intel_connector_alloc(void);
1770 void intel_connector_free(struct intel_connector *connector);
1771 void intel_connector_destroy(struct drm_connector *connector);
1772 int intel_connector_register(struct drm_connector *connector);
1773 void intel_connector_unregister(struct drm_connector *connector);
1774 void intel_connector_attach_encoder(struct intel_connector *connector,
1775                                     struct intel_encoder *encoder);
1776 bool intel_connector_get_hw_state(struct intel_connector *connector);
1777 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1778 int intel_connector_update_modes(struct drm_connector *connector,
1779                                  struct edid *edid);
1780 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1781 void intel_attach_force_audio_property(struct drm_connector *connector);
1782 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1783 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1784
1785 /* intel_csr.c */
1786 void intel_csr_ucode_init(struct drm_i915_private *);
1787 void intel_csr_load_program(struct drm_i915_private *);
1788 void intel_csr_ucode_fini(struct drm_i915_private *);
1789 void intel_csr_ucode_suspend(struct drm_i915_private *);
1790 void intel_csr_ucode_resume(struct drm_i915_private *);
1791
1792 /* intel_dp.c */
1793 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1794                            i915_reg_t dp_reg, enum port port,
1795                            enum pipe *pipe);
1796 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1797                    enum port port);
1798 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1799                              struct intel_connector *intel_connector);
1800 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1801                               int link_rate, uint8_t lane_count,
1802                               bool link_mst);
1803 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1804                                             int link_rate, uint8_t lane_count);
1805 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1806 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1807 int intel_dp_retrain_link(struct intel_encoder *encoder,
1808                           struct drm_modeset_acquire_ctx *ctx);
1809 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1810 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1811                                            const struct intel_crtc_state *crtc_state,
1812                                            bool enable);
1813 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1814 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1815 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
1816 int intel_dp_compute_config(struct intel_encoder *encoder,
1817                             struct intel_crtc_state *pipe_config,
1818                             struct drm_connector_state *conn_state);
1819 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1820 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1821 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1822                                   bool long_hpd);
1823 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1824                             const struct drm_connector_state *conn_state);
1825 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1826 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1827 void intel_edp_panel_on(struct intel_dp *intel_dp);
1828 void intel_edp_panel_off(struct intel_dp *intel_dp);
1829 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1830 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1831 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1832 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1833 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1834 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1835 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1836 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1837 void intel_plane_destroy(struct drm_plane *plane);
1838 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1839                            const struct intel_crtc_state *crtc_state);
1840 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1841                             const struct intel_crtc_state *crtc_state);
1842 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1843                                unsigned int frontbuffer_bits);
1844 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1845                           unsigned int frontbuffer_bits);
1846
1847 void
1848 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1849                                        uint8_t dp_train_pat);
1850 void
1851 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1852 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1853 uint8_t
1854 intel_dp_voltage_max(struct intel_dp *intel_dp);
1855 uint8_t
1856 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1857 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1858                            uint8_t *link_bw, uint8_t *rate_select);
1859 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1860 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1861 bool
1862 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1863 uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
1864                                      int mode_clock, int mode_hdisplay);
1865 uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
1866                                      int mode_hdisplay);
1867
1868 /* intel_vdsc.c */
1869 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
1870                                 struct intel_crtc_state *pipe_config);
1871 enum intel_display_power_domain
1872 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
1873
1874 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1875 {
1876         return ~((1 << lane_count) - 1) & 0xf;
1877 }
1878
1879 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1880 int intel_dp_link_required(int pixel_clock, int bpp);
1881 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1882 bool intel_digital_port_connected(struct intel_encoder *encoder);
1883 void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
1884                            struct intel_digital_port *dig_port);
1885
1886 /* intel_dp_aux_backlight.c */
1887 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1888
1889 /* intel_dp_mst.c */
1890 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1891 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1892 /* vlv_dsi.c */
1893 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1894
1895 /* icl_dsi.c */
1896 void icl_dsi_init(struct drm_i915_private *dev_priv);
1897
1898 /* intel_dsi_dcs_backlight.c */
1899 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1900
1901 /* intel_dvo.c */
1902 void intel_dvo_init(struct drm_i915_private *dev_priv);
1903 /* intel_hotplug.c */
1904 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1905 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1906                            struct intel_connector *connector);
1907
1908 /* legacy fbdev emulation in intel_fbdev.c */
1909 #ifdef CONFIG_DRM_FBDEV_EMULATION
1910 extern int intel_fbdev_init(struct drm_device *dev);
1911 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1912 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1913 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1914 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1915 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1916 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1917 #else
1918 static inline int intel_fbdev_init(struct drm_device *dev)
1919 {
1920         return 0;
1921 }
1922
1923 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1924 {
1925 }
1926
1927 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1928 {
1929 }
1930
1931 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1932 {
1933 }
1934
1935 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1936 {
1937 }
1938
1939 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1940 {
1941 }
1942
1943 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1944 {
1945 }
1946 #endif
1947
1948 /* intel_fbc.c */
1949 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1950                            struct intel_atomic_state *state);
1951 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1952 void intel_fbc_pre_update(struct intel_crtc *crtc,
1953                           struct intel_crtc_state *crtc_state,
1954                           struct intel_plane_state *plane_state);
1955 void intel_fbc_post_update(struct intel_crtc *crtc);
1956 void intel_fbc_init(struct drm_i915_private *dev_priv);
1957 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1958 void intel_fbc_enable(struct intel_crtc *crtc,
1959                       struct intel_crtc_state *crtc_state,
1960                       struct intel_plane_state *plane_state);
1961 void intel_fbc_disable(struct intel_crtc *crtc);
1962 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1963 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1964                           unsigned int frontbuffer_bits,
1965                           enum fb_op_origin origin);
1966 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1967                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1968 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1969 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1970 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1971
1972 /* intel_hdmi.c */
1973 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1974                      enum port port);
1975 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1976                                struct intel_connector *intel_connector);
1977 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1978 int intel_hdmi_compute_config(struct intel_encoder *encoder,
1979                               struct intel_crtc_state *pipe_config,
1980                               struct drm_connector_state *conn_state);
1981 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1982                                        struct drm_connector *connector,
1983                                        bool high_tmds_clock_ratio,
1984                                        bool scrambling);
1985 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1986 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1987
1988 /* intel_lvds.c */
1989 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1990                              i915_reg_t lvds_reg, enum pipe *pipe);
1991 void intel_lvds_init(struct drm_i915_private *dev_priv);
1992 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1993 bool intel_is_dual_link_lvds(struct drm_device *dev);
1994
1995 /* intel_overlay.c */
1996 void intel_overlay_setup(struct drm_i915_private *dev_priv);
1997 void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
1998 int intel_overlay_switch_off(struct intel_overlay *overlay);
1999 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
2000                                   struct drm_file *file_priv);
2001 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
2002                               struct drm_file *file_priv);
2003 void intel_overlay_reset(struct drm_i915_private *dev_priv);
2004
2005
2006 /* intel_panel.c */
2007 int intel_panel_init(struct intel_panel *panel,
2008                      struct drm_display_mode *fixed_mode,
2009                      struct drm_display_mode *downclock_mode);
2010 void intel_panel_fini(struct intel_panel *panel);
2011 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
2012                             struct drm_display_mode *adjusted_mode);
2013 void intel_pch_panel_fitting(struct intel_crtc *crtc,
2014                              struct intel_crtc_state *pipe_config,
2015                              int fitting_mode);
2016 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
2017                               struct intel_crtc_state *pipe_config,
2018                               int fitting_mode);
2019 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
2020                                     u32 level, u32 max);
2021 int intel_panel_setup_backlight(struct drm_connector *connector,
2022                                 enum pipe pipe);
2023 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
2024                                   const struct drm_connector_state *conn_state);
2025 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
2026 extern struct drm_display_mode *intel_find_panel_downclock(
2027                                 struct drm_i915_private *dev_priv,
2028                                 struct drm_display_mode *fixed_mode,
2029                                 struct drm_connector *connector);
2030
2031 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
2032 int intel_backlight_device_register(struct intel_connector *connector);
2033 void intel_backlight_device_unregister(struct intel_connector *connector);
2034 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2035 static inline int intel_backlight_device_register(struct intel_connector *connector)
2036 {
2037         return 0;
2038 }
2039 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
2040 {
2041 }
2042 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2043
2044 /* intel_hdcp.c */
2045 void intel_hdcp_atomic_check(struct drm_connector *connector,
2046                              struct drm_connector_state *old_state,
2047                              struct drm_connector_state *new_state);
2048 int intel_hdcp_init(struct intel_connector *connector,
2049                     const struct intel_hdcp_shim *hdcp_shim);
2050 int intel_hdcp_enable(struct intel_connector *connector);
2051 int intel_hdcp_disable(struct intel_connector *connector);
2052 int intel_hdcp_check_link(struct intel_connector *connector);
2053 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2054 bool intel_hdcp_capable(struct intel_connector *connector);
2055
2056 /* intel_psr.c */
2057 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2058 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2059 void intel_psr_enable(struct intel_dp *intel_dp,
2060                       const struct intel_crtc_state *crtc_state);
2061 void intel_psr_disable(struct intel_dp *intel_dp,
2062                       const struct intel_crtc_state *old_crtc_state);
2063 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
2064                                struct drm_modeset_acquire_ctx *ctx,
2065                                u64 value);
2066 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2067                           unsigned frontbuffer_bits,
2068                           enum fb_op_origin origin);
2069 void intel_psr_flush(struct drm_i915_private *dev_priv,
2070                      unsigned frontbuffer_bits,
2071                      enum fb_op_origin origin);
2072 void intel_psr_init(struct drm_i915_private *dev_priv);
2073 void intel_psr_compute_config(struct intel_dp *intel_dp,
2074                               struct intel_crtc_state *crtc_state);
2075 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2076 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2077 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2078 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2079                             u32 *out_value);
2080 bool intel_psr_enabled(struct intel_dp *intel_dp);
2081
2082 /* intel_quirks.c */
2083 void intel_init_quirks(struct drm_i915_private *dev_priv);
2084
2085 /* intel_runtime_pm.c */
2086 int intel_power_domains_init(struct drm_i915_private *);
2087 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2088 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2089 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2090 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2091 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
2092 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2093 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2094
2095 enum i915_drm_suspend_mode {
2096         I915_DRM_SUSPEND_IDLE,
2097         I915_DRM_SUSPEND_MEM,
2098         I915_DRM_SUSPEND_HIBERNATE,
2099 };
2100
2101 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2102                                  enum i915_drm_suspend_mode);
2103 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2104 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2105 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2106 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2107 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2108 const char *
2109 intel_display_power_domain_str(enum intel_display_power_domain domain);
2110
2111 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2112                                     enum intel_display_power_domain domain);
2113 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2114                                       enum intel_display_power_domain domain);
2115 void intel_display_power_get(struct drm_i915_private *dev_priv,
2116                              enum intel_display_power_domain domain);
2117 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2118                                         enum intel_display_power_domain domain);
2119 void intel_display_power_put(struct drm_i915_private *dev_priv,
2120                              enum intel_display_power_domain domain);
2121 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2122                             u8 req_slices);
2123
2124 static inline void
2125 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
2126 {
2127         WARN_ONCE(dev_priv->runtime_pm.suspended,
2128                   "Device suspended during HW access\n");
2129 }
2130
2131 static inline void
2132 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
2133 {
2134         assert_rpm_device_not_suspended(dev_priv);
2135         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
2136                   "RPM wakelock ref not held during HW access");
2137 }
2138
2139 /**
2140  * disable_rpm_wakeref_asserts - disable the RPM assert checks
2141  * @dev_priv: i915 device instance
2142  *
2143  * This function disable asserts that check if we hold an RPM wakelock
2144  * reference, while keeping the device-not-suspended checks still enabled.
2145  * It's meant to be used only in special circumstances where our rule about
2146  * the wakelock refcount wrt. the device power state doesn't hold. According
2147  * to this rule at any point where we access the HW or want to keep the HW in
2148  * an active state we must hold an RPM wakelock reference acquired via one of
2149  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2150  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2151  * forcewake release timer, and the GPU RPS and hangcheck works. All other
2152  * users should avoid using this function.
2153  *
2154  * Any calls to this function must have a symmetric call to
2155  * enable_rpm_wakeref_asserts().
2156  */
2157 static inline void
2158 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2159 {
2160         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2161 }
2162
2163 /**
2164  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2165  * @dev_priv: i915 device instance
2166  *
2167  * This function re-enables the RPM assert checks after disabling them with
2168  * disable_rpm_wakeref_asserts. It's meant to be used only in special
2169  * circumstances otherwise its use should be avoided.
2170  *
2171  * Any calls to this function must have a symmetric call to
2172  * disable_rpm_wakeref_asserts().
2173  */
2174 static inline void
2175 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2176 {
2177         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2178 }
2179
2180 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2181 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2182 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2183 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2184
2185 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2186                              bool override, unsigned int mask);
2187 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2188                           enum dpio_channel ch, bool override);
2189
2190
2191 /* intel_pm.c */
2192 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2193 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2194 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2195 void intel_update_watermarks(struct intel_crtc *crtc);
2196 void intel_init_pm(struct drm_i915_private *dev_priv);
2197 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2198 void intel_pm_setup(struct drm_i915_private *dev_priv);
2199 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2200 void intel_gpu_ips_teardown(void);
2201 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2202 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2203 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2204 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2205 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2206 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2207 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2208 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2209 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2210 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2211 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
2212 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
2213 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
2214 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
2215 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
2216                                struct skl_ddb_entry *ddb_y,
2217                                struct skl_ddb_entry *ddb_uv);
2218 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2219                           struct skl_ddb_allocation *ddb /* out */);
2220 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
2221                               struct skl_pipe_wm *out);
2222 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2223 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2224 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2225 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2226 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2227 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2228                          const struct skl_wm_level *l2);
2229 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
2230                                  const struct skl_ddb_entry entries[],
2231                                  int num_entries, int ignore_idx);
2232 void skl_write_plane_wm(struct intel_plane *plane,
2233                         const struct intel_crtc_state *crtc_state);
2234 void skl_write_cursor_wm(struct intel_plane *plane,
2235                          const struct intel_crtc_state *crtc_state);
2236 bool ilk_disable_lp_wm(struct drm_device *dev);
2237 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2238                                   struct intel_crtc_state *cstate);
2239 void intel_init_ipc(struct drm_i915_private *dev_priv);
2240 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2241
2242 /* intel_sdvo.c */
2243 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2244                              i915_reg_t sdvo_reg, enum pipe *pipe);
2245 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2246                      i915_reg_t reg, enum port port);
2247
2248
2249 /* intel_sprite.c */
2250 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2251                              int usecs);
2252 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2253                                               enum pipe pipe, int plane);
2254 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2255                                     struct drm_file *file_priv);
2256 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2257 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2258 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2259 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2260 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2261 struct intel_plane *
2262 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2263                            enum pipe pipe, enum plane_id plane_id);
2264
2265 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2266 {
2267         /* Don't need to do a gen check, these planes are only available on gen11 */
2268         if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2269                 return true;
2270
2271         return false;
2272 }
2273
2274 static inline bool icl_is_hdr_plane(struct intel_plane *plane)
2275 {
2276         if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
2277                 return false;
2278
2279         return plane->id < PLANE_SPRITE2;
2280 }
2281
2282 /* intel_tv.c */
2283 void intel_tv_init(struct drm_i915_private *dev_priv);
2284
2285 /* intel_atomic.c */
2286 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2287                                                 const struct drm_connector_state *state,
2288                                                 struct drm_property *property,
2289                                                 uint64_t *val);
2290 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2291                                                 struct drm_connector_state *state,
2292                                                 struct drm_property *property,
2293                                                 uint64_t val);
2294 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2295                                          struct drm_connector_state *new_state);
2296 struct drm_connector_state *
2297 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2298
2299 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2300 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2301                                struct drm_crtc_state *state);
2302 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2303 void intel_atomic_state_clear(struct drm_atomic_state *);
2304
2305 static inline struct intel_crtc_state *
2306 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2307                             struct intel_crtc *crtc)
2308 {
2309         struct drm_crtc_state *crtc_state;
2310         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2311         if (IS_ERR(crtc_state))
2312                 return ERR_CAST(crtc_state);
2313
2314         return to_intel_crtc_state(crtc_state);
2315 }
2316
2317 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2318                                struct intel_crtc *intel_crtc,
2319                                struct intel_crtc_state *crtc_state);
2320
2321 /* intel_atomic_plane.c */
2322 struct intel_plane *intel_plane_alloc(void);
2323 void intel_plane_free(struct intel_plane *plane);
2324 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2325 void intel_plane_destroy_state(struct drm_plane *plane,
2326                                struct drm_plane_state *state);
2327 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2328 void skl_update_planes_on_crtc(struct intel_atomic_state *state,
2329                                struct intel_crtc *crtc);
2330 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
2331                                 struct intel_crtc *crtc);
2332 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2333                                         struct intel_crtc_state *crtc_state,
2334                                         const struct intel_plane_state *old_plane_state,
2335                                         struct intel_plane_state *intel_state);
2336
2337 /* intel_color.c */
2338 void intel_color_init(struct intel_crtc *crtc);
2339 int intel_color_check(struct intel_crtc_state *crtc_state);
2340 void intel_color_set_csc(struct intel_crtc_state *crtc_state);
2341 void intel_color_load_luts(struct intel_crtc_state *crtc_state);
2342
2343 /* intel_lspcon.c */
2344 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2345 void lspcon_resume(struct intel_lspcon *lspcon);
2346 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2347 void lspcon_write_infoframe(struct intel_encoder *encoder,
2348                             const struct intel_crtc_state *crtc_state,
2349                             unsigned int type,
2350                             const void *buf, ssize_t len);
2351 void lspcon_set_infoframes(struct intel_encoder *encoder,
2352                            bool enable,
2353                            const struct intel_crtc_state *crtc_state,
2354                            const struct drm_connector_state *conn_state);
2355 bool lspcon_infoframe_enabled(struct intel_encoder *encoder,
2356                               const struct intel_crtc_state *pipe_config);
2357 void lspcon_ycbcr420_config(struct drm_connector *connector,
2358                             struct intel_crtc_state *crtc_state);
2359
2360 /* intel_pipe_crc.c */
2361 #ifdef CONFIG_DEBUG_FS
2362 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2363 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2364                                  const char *source_name, size_t *values_cnt);
2365 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2366                                               size_t *count);
2367 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2368 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2369 #else
2370 #define intel_crtc_set_crc_source NULL
2371 #define intel_crtc_verify_crc_source NULL
2372 #define intel_crtc_get_crc_sources NULL
2373 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2374 {
2375 }
2376
2377 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2378 {
2379 }
2380 #endif
2381 #endif /* __INTEL_DRV_H__ */