drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <linux/stackdepot.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_probe_helper.h>
  41 #include <drm/drm_rect.h>
  42 #include <drm/drm_vblank.h>
  43 #include <drm/drm_atomic.h>
  44 #include <drm/i915_mei_hdcp_interface.h>
  45 #include <media/cec-notifier.h>
  46
  47 struct drm_printer;
  48
  49 /**
  50  * __wait_for - magic wait macro
  51  *
  52  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  53  * important that we check the condition again after having timed out, since the
  54  * timeout could be due to preemption or similar and we've never had a chance to
  55  * check the condition before the timeout.
  56  */
  57 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  58         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  59         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  60         int ret__;                                                      \
  61         might_sleep();                                                  \
  62         for (;;) {                                                      \
  63                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  64                 OP;                                                     \
  65                 /* Guarantee COND check prior to timeout */             \
  66                 barrier();                                              \
  67                 if (COND) {                                             \
  68                         ret__ = 0;                                      \
  69                         break;                                          \
  70                 }                                                       \
  71                 if (expired__) {                                        \
  72                         ret__ = -ETIMEDOUT;                             \
  73                         break;                                          \
  74                 }                                                       \
  75                 usleep_range(wait__, wait__ * 2);                       \
  76                 if (wait__ < (Wmax))                                    \
  77                         wait__ <<= 1;                                   \
  78         }                                                               \
  79         ret__;                                                          \
  80 })
  81
  82 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  83                                                    (Wmax))
  84 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  85
  86 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  87 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  88 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  89 #else
  90 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  91 #endif
  92
  93 #define _wait_for_atomic(COND, US, ATOMIC) \
  94 ({ \
  95         int cpu, ret, timeout = (US) * 1000; \
  96         u64 base; \
  97         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  98         if (!(ATOMIC)) { \
  99                 preempt_disable(); \
 100                 cpu = smp_processor_id(); \
 101         } \
 102         base = local_clock(); \
 103         for (;;) { \
 104                 u64 now = local_clock(); \
 105                 if (!(ATOMIC)) \
 106                         preempt_enable(); \
 107                 /* Guarantee COND check prior to timeout */ \
 108                 barrier(); \
 109                 if (COND) { \
 110                         ret = 0; \
 111                         break; \
 112                 } \
 113                 if (now - base >= timeout) { \
 114                         ret = -ETIMEDOUT; \
 115                         break; \
 116                 } \
 117                 cpu_relax(); \
 118                 if (!(ATOMIC)) { \
 119                         preempt_disable(); \
 120                         if (unlikely(cpu != smp_processor_id())) { \
 121                                 timeout -= now - base; \
 122                                 cpu = smp_processor_id(); \
 123                                 base = local_clock(); \
 124                         } \
 125                 } \
 126         } \
 127         ret; \
 128 })
 129
 130 #define wait_for_us(COND, US) \
 131 ({ \
 132         int ret__; \
 133         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 134         if ((US) > 10) \
 135                 ret__ = _wait_for((COND), (US), 10, 10); \
 136         else \
 137                 ret__ = _wait_for_atomic((COND), (US), 0); \
 138         ret__; \
 139 })
 140
 141 #define wait_for_atomic_us(COND, US) \
 142 ({ \
 143         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 144         BUILD_BUG_ON((US) > 50000); \
 145         _wait_for_atomic((COND), (US), 1); \
 146 })
 147
 148 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 149
 150 #define KHz(x) (1000 * (x))
 151 #define MHz(x) KHz(1000 * (x))
 152
 153 #define KBps(x) (1000 * (x))
 154 #define MBps(x) KBps(1000 * (x))
 155 #define GBps(x) ((u64)1000 * MBps((x)))
 156
 157 /*
 158  * Display related stuff
 159  */
 160
 161 /* store information about an Ixxx DVO */
 162 /* The i830->i865 use multiple DVOs with multiple i2cs */
 163 /* the i915, i945 have a single sDVO i2c bus - which is different */
 164 #define MAX_OUTPUTS 6
 165 /* maximum connectors per crtcs in the mode set */
 166
 167 #define INTEL_I2C_BUS_DVO 1
 168 #define INTEL_I2C_BUS_SDVO 2
 169
 170 /* these are outputs from the chip - integrated only
 171    external chips are via DVO or SDVO output */
 172 enum intel_output_type {
 173         INTEL_OUTPUT_UNUSED = 0,
 174         INTEL_OUTPUT_ANALOG = 1,
 175         INTEL_OUTPUT_DVO = 2,
 176         INTEL_OUTPUT_SDVO = 3,
 177         INTEL_OUTPUT_LVDS = 4,
 178         INTEL_OUTPUT_TVOUT = 5,
 179         INTEL_OUTPUT_HDMI = 6,
 180         INTEL_OUTPUT_DP = 7,
 181         INTEL_OUTPUT_EDP = 8,
 182         INTEL_OUTPUT_DSI = 9,
 183         INTEL_OUTPUT_DDI = 10,
 184         INTEL_OUTPUT_DP_MST = 11,
 185 };
 186
 187 #define INTEL_DVO_CHIP_NONE 0
 188 #define INTEL_DVO_CHIP_LVDS 1
 189 #define INTEL_DVO_CHIP_TMDS 2
 190 #define INTEL_DVO_CHIP_TVOUT 4
 191
 192 #define INTEL_DSI_VIDEO_MODE    0
 193 #define INTEL_DSI_COMMAND_MODE  1
 194
 195 struct intel_framebuffer {
 196         struct drm_framebuffer base;
 197         struct intel_rotation_info rot_info;
 198
 199         /* for each plane in the normal GTT view */
 200         struct {
 201                 unsigned int x, y;
 202         } normal[2];
 203         /* for each plane in the rotated GTT view */
 204         struct {
 205                 unsigned int x, y;
 206                 unsigned int pitch; /* pixels */
 207         } rotated[2];
 208 };
 209
 210 struct intel_fbdev {
 211         struct drm_fb_helper helper;
 212         struct intel_framebuffer *fb;
 213         struct i915_vma *vma;
 214         unsigned long vma_flags;
 215         async_cookie_t cookie;
 216         int preferred_bpp;
 217
 218         /* Whether or not fbdev hpd processing is temporarily suspended */
 219         bool hpd_suspended : 1;
 220         /* Set when a hotplug was received while HPD processing was
 221          * suspended
 222          */
 223         bool hpd_waiting : 1;
 224
 225         /* Protects hpd_suspended */
 226         struct mutex hpd_lock;
 227 };
 228
 229 struct intel_encoder {
 230         struct drm_encoder base;
 231
 232         enum intel_output_type type;
 233         enum port port;
 234         unsigned int cloneable;
 235         bool (*hotplug)(struct intel_encoder *encoder,
 236                         struct intel_connector *connector);
 237         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 238                                                       struct intel_crtc_state *,
 239                                                       struct drm_connector_state *);
 240         int (*compute_config)(struct intel_encoder *,
 241                               struct intel_crtc_state *,
 242                               struct drm_connector_state *);
 243         void (*pre_pll_enable)(struct intel_encoder *,
 244                                const struct intel_crtc_state *,
 245                                const struct drm_connector_state *);
 246         void (*pre_enable)(struct intel_encoder *,
 247                            const struct intel_crtc_state *,
 248                            const struct drm_connector_state *);
 249         void (*enable)(struct intel_encoder *,
 250                        const struct intel_crtc_state *,
 251                        const struct drm_connector_state *);
 252         void (*disable)(struct intel_encoder *,
 253                         const struct intel_crtc_state *,
 254                         const struct drm_connector_state *);
 255         void (*post_disable)(struct intel_encoder *,
 256                              const struct intel_crtc_state *,
 257                              const struct drm_connector_state *);
 258         void (*post_pll_disable)(struct intel_encoder *,
 259                                  const struct intel_crtc_state *,
 260                                  const struct drm_connector_state *);
 261         void (*update_pipe)(struct intel_encoder *,
 262                             const struct intel_crtc_state *,
 263                             const struct drm_connector_state *);
 264         /* Read out the current hw state of this connector, returning true if
 265          * the encoder is active. If the encoder is enabled it also set the pipe
 266          * it is connected to in the pipe parameter. */
 267         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 268         /* Reconstructs the equivalent mode flags for the current hardware
 269          * state. This must be called _after_ display->get_pipe_config has
 270          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 271          * be set correctly before calling this function. */
 272         void (*get_config)(struct intel_encoder *,
 273                            struct intel_crtc_state *pipe_config);
 274         /* Returns a mask of power domains that need to be referenced as part
 275          * of the hardware state readout code. */
 276         u64 (*get_power_domains)(struct intel_encoder *encoder,
 277                                  struct intel_crtc_state *crtc_state);
 278         /*
 279          * Called during system suspend after all pending requests for the
 280          * encoder are flushed (for example for DP AUX transactions) and
 281          * device interrupts are disabled.
 282          */
 283         void (*suspend)(struct intel_encoder *);
 284         int crtc_mask;
 285         enum hpd_pin hpd_pin;
 286         enum intel_display_power_domain power_domain;
 287         /* for communication with audio component; protected by av_mutex */
 288         const struct drm_connector *audio_connector;
 289 };
 290
 291 struct intel_panel {
 292         struct drm_display_mode *fixed_mode;
 293         struct drm_display_mode *downclock_mode;
 294
 295         /* backlight */
 296         struct {
 297                 bool present;
 298                 u32 level;
 299                 u32 min;
 300                 u32 max;
 301                 bool enabled;
 302                 bool combination_mode;  /* gen 2/4 only */
 303                 bool active_low_pwm;
 304                 bool alternate_pwm_increment;   /* lpt+ */
 305
 306                 /* PWM chip */
 307                 bool util_pin_active_low;       /* bxt+ */
 308                 u8 controller;          /* bxt+ only */
 309                 struct pwm_device *pwm;
 310
 311                 struct backlight_device *device;
 312
 313                 /* Connector and platform specific backlight functions */
 314                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 315                 u32 (*get)(struct intel_connector *connector);
 316                 void (*set)(const struct drm_connector_state *conn_state, u32 level);
 317                 void (*disable)(const struct drm_connector_state *conn_state);
 318                 void (*enable)(const struct intel_crtc_state *crtc_state,
 319                                const struct drm_connector_state *conn_state);
 320                 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
 321                 void (*power)(struct intel_connector *, bool enable);
 322         } backlight;
 323 };
 324
 325 struct intel_digital_port;
 326
 327 /*
 328  * This structure serves as a translation layer between the generic HDCP code
 329  * and the bus-specific code. What that means is that HDCP over HDMI differs
 330  * from HDCP over DP, so to account for these differences, we need to
 331  * communicate with the receiver through this shim.
 332  *
 333  * For completeness, the 2 buses differ in the following ways:
 334  *      - DP AUX vs. DDC
 335  *              HDCP registers on the receiver are set via DP AUX for DP, and
 336  *              they are set via DDC for HDMI.
 337  *      - Receiver register offsets
 338  *              The offsets of the registers are different for DP vs. HDMI
 339  *      - Receiver register masks/offsets
 340  *              For instance, the ready bit for the KSV fifo is in a different
 341  *              place on DP vs HDMI
 342  *      - Receiver register names
 343  *              Seriously. In the DP spec, the 16-bit register containing
 344  *              downstream information is called BINFO, on HDMI it's called
 345  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 346  *              with a completely different definition.
 347  *      - KSV FIFO
 348  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 349  *              be read 3 keys at a time
 350  *      - Aksv output
 351  *              Since Aksv is hidden in hardware, there's different procedures
 352  *              to send it over DP AUX vs DDC
 353  */
 354 struct intel_hdcp_shim {
 355         /* Outputs the transmitter's An and Aksv values to the receiver. */
 356         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 357
 358         /* Reads the receiver's key selection vector */
 359         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 360
 361         /*
 362          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 363          * definitions are the same in the respective specs, but the names are
 364          * different. Call it BSTATUS since that's the name the HDMI spec
 365          * uses and it was there first.
 366          */
 367         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 368                             u8 *bstatus);
 369
 370         /* Determines whether a repeater is present downstream */
 371         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 372                                 bool *repeater_present);
 373
 374         /* Reads the receiver's Ri' value */
 375         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 376
 377         /* Determines if the receiver's KSV FIFO is ready for consumption */
 378         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 379                               bool *ksv_ready);
 380
 381         /* Reads the ksv fifo for num_downstream devices */
 382         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 383                              int num_downstream, u8 *ksv_fifo);
 384
 385         /* Reads a 32-bit part of V' from the receiver */
 386         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 387                                  int i, u32 *part);
 388
 389         /* Enables HDCP signalling on the port */
 390         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 391                                  bool enable);
 392
 393         /* Ensures the link is still protected */
 394         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 395
 396         /* Detects panel's hdcp capability. This is optional for HDMI. */
 397         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 398                             bool *hdcp_capable);
 399
 400         /* HDCP adaptation(DP/HDMI) required on the port */
 401         enum hdcp_wired_protocol protocol;
 402
 403         /* Detects whether sink is HDCP2.2 capable */
 404         int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
 405                                 bool *capable);
 406
 407         /* Write HDCP2.2 messages */
 408         int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
 409                              void *buf, size_t size);
 410
 411         /* Read HDCP2.2 messages */
 412         int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
 413                             u8 msg_id, void *buf, size_t size);
 414
 415         /*
 416          * Implementation of DP HDCP2.2 Errata for the communication of stream
 417          * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
 418          * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
 419          */
 420         int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
 421                                   bool is_repeater, u8 type);
 422 };
 423
 424 struct intel_hdcp {
 425         const struct intel_hdcp_shim *shim;
 426         /* Mutex for hdcp state of the connector */
 427         struct mutex mutex;
 428         u64 value;
 429         struct delayed_work check_work;
 430         struct work_struct prop_work;
 431
 432         /* HDCP1.4 Encryption status */
 433         bool hdcp_encrypted;
 434
 435         /* HDCP2.2 related definitions */
 436         /* Flag indicates whether this connector supports HDCP2.2 or not. */
 437         bool hdcp2_supported;
 438
 439         /* HDCP2.2 Encryption status */
 440         bool hdcp2_encrypted;
 441
 442         /*
 443          * Content Stream Type defined by content owner. TYPE0(0x0) content can
 444          * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
 445          * content can flow only through a link protected by HDCP2.2.
 446          */
 447         u8 content_type;
 448         struct hdcp_port_data port_data;
 449
 450         bool is_paired;
 451         bool is_repeater;
 452
 453         /*
 454          * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
 455          * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
 456          * When it rolls over re-auth has to be triggered.
 457          */
 458         u32 seq_num_v;
 459
 460         /*
 461          * Count of RepeaterAuth_Stream_Manage msg propagated.
 462          * Initialized to 0 on AKE_INIT. Incremented after every successful
 463          * transmission of RepeaterAuth_Stream_Manage message. When it rolls
 464          * over re-Auth has to be triggered.
 465          */
 466         u32 seq_num_m;
 467 };
 468
 469 struct intel_connector {
 470         struct drm_connector base;
 471         /*
 472          * The fixed encoder this connector is connected to.
 473          */
 474         struct intel_encoder *encoder;
 475
 476         /* ACPI device id for ACPI and driver cooperation */
 477         u32 acpi_device_id;
 478
 479         /* Reads out the current hw, returning true if the connector is enabled
 480          * and active (i.e. dpms ON state). */
 481         bool (*get_hw_state)(struct intel_connector *);
 482
 483         /* Panel info for eDP and LVDS */
 484         struct intel_panel panel;
 485
 486         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 487         struct edid *edid;
 488         struct edid *detect_edid;
 489
 490         /* since POLL and HPD connectors may use the same HPD line keep the native
 491            state of connector->polled in case hotplug storm detection changes it */
 492         u8 polled;
 493
 494         void *port; /* store this opaque as its illegal to dereference it */
 495
 496         struct intel_dp *mst_port;
 497
 498         /* Work struct to schedule a uevent on link train failure */
 499         struct work_struct modeset_retry_work;
 500
 501         struct intel_hdcp hdcp;
 502 };
 503
 504 struct intel_digital_connector_state {
 505         struct drm_connector_state base;
 506
 507         enum hdmi_force_audio force_audio;
 508         int broadcast_rgb;
 509 };
 510
 511 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 512
 513 struct dpll {
 514         /* given values */
 515         int n;
 516         int m1, m2;
 517         int p1, p2;
 518         /* derived values */
 519         int     dot;
 520         int     vco;
 521         int     m;
 522         int     p;
 523 };
 524
 525 struct intel_atomic_state {
 526         struct drm_atomic_state base;
 527
 528         struct {
 529                 /*
 530                  * Logical state of cdclk (used for all scaling, watermark,
 531                  * etc. calculations and checks). This is computed as if all
 532                  * enabled crtcs were active.
 533                  */
 534                 struct intel_cdclk_state logical;
 535
 536                 /*
 537                  * Actual state of cdclk, can be different from the logical
 538                  * state only when all crtc's are DPMS off.
 539                  */
 540                 struct intel_cdclk_state actual;
 541         } cdclk;
 542
 543         bool dpll_set, modeset;
 544
 545         /*
 546          * Does this transaction change the pipes that are active?  This mask
 547          * tracks which CRTC's have changed their active state at the end of
 548          * the transaction (not counting the temporary disable during modesets).
 549          * This mask should only be non-zero when intel_state->modeset is true,
 550          * but the converse is not necessarily true; simply changing a mode may
 551          * not flip the final active status of any CRTC's
 552          */
 553         unsigned int active_pipe_changes;
 554
 555         unsigned int active_crtcs;
 556         /* minimum acceptable cdclk for each pipe */
 557         int min_cdclk[I915_MAX_PIPES];
 558         /* minimum acceptable voltage level for each pipe */
 559         u8 min_voltage_level[I915_MAX_PIPES];
 560
 561         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 562
 563         /*
 564          * Current watermarks can't be trusted during hardware readout, so
 565          * don't bother calculating intermediate watermarks.
 566          */
 567         bool skip_intermediate_wm;
 568
 569         bool rps_interactive;
 570
 571         /* Gen9+ only */
 572         struct skl_ddb_values wm_results;
 573
 574         struct i915_sw_fence commit_ready;
 575
 576         struct llist_node freed;
 577 };
 578
 579 struct intel_plane_state {
 580         struct drm_plane_state base;
 581         struct i915_ggtt_view view;
 582         struct i915_vma *vma;
 583         unsigned long flags;
 584 #define PLANE_HAS_FENCE BIT(0)
 585
 586         struct {
 587                 u32 offset;
 588                 /*
 589                  * Plane stride in:
 590                  * bytes for 0/180 degree rotation
 591                  * pixels for 90/270 degree rotation
 592                  */
 593                 u32 stride;
 594                 int x, y;
 595         } color_plane[2];
 596
 597         /* plane control register */
 598         u32 ctl;
 599
 600         /* plane color control register */
 601         u32 color_ctl;
 602
 603         /*
 604          * scaler_id
 605          *    = -1 : not using a scaler
 606          *    >=  0 : using a scalers
 607          *
 608          * plane requiring a scaler:
 609          *   - During check_plane, its bit is set in
 610          *     crtc_state->scaler_state.scaler_users by calling helper function
 611          *     update_scaler_plane.
 612          *   - scaler_id indicates the scaler it got assigned.
 613          *
 614          * plane doesn't require a scaler:
 615          *   - this can happen when scaling is no more required or plane simply
 616          *     got disabled.
 617          *   - During check_plane, corresponding bit is reset in
 618          *     crtc_state->scaler_state.scaler_users by calling helper function
 619          *     update_scaler_plane.
 620          */
 621         int scaler_id;
 622
 623         /*
 624          * linked_plane:
 625          *
 626          * ICL planar formats require 2 planes that are updated as pairs.
 627          * This member is used to make sure the other plane is also updated
 628          * when required, and for update_slave() to find the correct
 629          * plane_state to pass as argument.
 630          */
 631         struct intel_plane *linked_plane;
 632
 633         /*
 634          * slave:
 635          * If set don't update use the linked plane's state for updating
 636          * this plane during atomic commit with the update_slave() callback.
 637          *
 638          * It's also used by the watermark code to ignore wm calculations on
 639          * this plane. They're calculated by the linked plane's wm code.
 640          */
 641         u32 slave;
 642
 643         struct drm_intel_sprite_colorkey ckey;
 644 };
 645
 646 struct intel_initial_plane_config {
 647         struct intel_framebuffer *fb;
 648         unsigned int tiling;
 649         int size;
 650         u32 base;
 651         u8 rotation;
 652 };
 653
 654 #define SKL_MIN_SRC_W 8
 655 #define SKL_MAX_SRC_W 4096
 656 #define SKL_MIN_SRC_H 8
 657 #define SKL_MAX_SRC_H 4096
 658 #define SKL_MIN_DST_W 8
 659 #define SKL_MAX_DST_W 4096
 660 #define SKL_MIN_DST_H 8
 661 #define SKL_MAX_DST_H 4096
 662 #define ICL_MAX_SRC_W 5120
 663 #define ICL_MAX_SRC_H 4096
 664 #define ICL_MAX_DST_W 5120
 665 #define ICL_MAX_DST_H 4096
 666 #define SKL_MIN_YUV_420_SRC_W 16
 667 #define SKL_MIN_YUV_420_SRC_H 16
 668
 669 struct intel_scaler {
 670         int in_use;
 671         u32 mode;
 672 };
 673
 674 struct intel_crtc_scaler_state {
 675 #define SKL_NUM_SCALERS 2
 676         struct intel_scaler scalers[SKL_NUM_SCALERS];
 677
 678         /*
 679          * scaler_users: keeps track of users requesting scalers on this crtc.
 680          *
 681          *     If a bit is set, a user is using a scaler.
 682          *     Here user can be a plane or crtc as defined below:
 683          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 684          *       bit 31    - crtc
 685          *
 686          * Instead of creating a new index to cover planes and crtc, using
 687          * existing drm_plane_index for planes which is well less than 31
 688          * planes and bit 31 for crtc. This should be fine to cover all
 689          * our platforms.
 690          *
 691          * intel_atomic_setup_scalers will setup available scalers to users
 692          * requesting scalers. It will gracefully fail if request exceeds
 693          * avilability.
 694          */
 695 #define SKL_CRTC_INDEX 31
 696         unsigned scaler_users;
 697
 698         /* scaler used by crtc for panel fitting purpose */
 699         int scaler_id;
 700 };
 701
 702 /* drm_mode->private_flags */
 703 #define I915_MODE_FLAG_INHERITED (1<<0)
 704 /* Flag to get scanline using frame time stamps */
 705 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 706 /* Flag to use the scanline counter instead of the pixel counter */
 707 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
 708
 709 struct intel_pipe_wm {
 710         struct intel_wm_level wm[5];
 711         u32 linetime;
 712         bool fbc_wm_enabled;
 713         bool pipe_enabled;
 714         bool sprites_enabled;
 715         bool sprites_scaled;
 716 };
 717
 718 struct skl_plane_wm {
 719         struct skl_wm_level wm[8];
 720         struct skl_wm_level uv_wm[8];
 721         struct skl_wm_level trans_wm;
 722         bool is_planar;
 723 };
 724
 725 struct skl_pipe_wm {
 726         struct skl_plane_wm planes[I915_MAX_PLANES];
 727         u32 linetime;
 728 };
 729
 730 enum vlv_wm_level {
 731         VLV_WM_LEVEL_PM2,
 732         VLV_WM_LEVEL_PM5,
 733         VLV_WM_LEVEL_DDR_DVFS,
 734         NUM_VLV_WM_LEVELS,
 735 };
 736
 737 struct vlv_wm_state {
 738         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 739         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 740         u8 num_levels;
 741         bool cxsr;
 742 };
 743
 744 struct vlv_fifo_state {
 745         u16 plane[I915_MAX_PLANES];
 746 };
 747
 748 enum g4x_wm_level {
 749         G4X_WM_LEVEL_NORMAL,
 750         G4X_WM_LEVEL_SR,
 751         G4X_WM_LEVEL_HPLL,
 752         NUM_G4X_WM_LEVELS,
 753 };
 754
 755 struct g4x_wm_state {
 756         struct g4x_pipe_wm wm;
 757         struct g4x_sr_wm sr;
 758         struct g4x_sr_wm hpll;
 759         bool cxsr;
 760         bool hpll_en;
 761         bool fbc_en;
 762 };
 763
 764 struct intel_crtc_wm_state {
 765         union {
 766                 struct {
 767                         /*
 768                          * Intermediate watermarks; these can be
 769                          * programmed immediately since they satisfy
 770                          * both the current configuration we're
 771                          * switching away from and the new
 772                          * configuration we're switching to.
 773                          */
 774                         struct intel_pipe_wm intermediate;
 775
 776                         /*
 777                          * Optimal watermarks, programmed post-vblank
 778                          * when this state is committed.
 779                          */
 780                         struct intel_pipe_wm optimal;
 781                 } ilk;
 782
 783                 struct {
 784                         /* gen9+ only needs 1-step wm programming */
 785                         struct skl_pipe_wm optimal;
 786                         struct skl_ddb_entry ddb;
 787                         struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
 788                         struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
 789                 } skl;
 790
 791                 struct {
 792                         /* "raw" watermarks (not inverted) */
 793                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 794                         /* intermediate watermarks (inverted) */
 795                         struct vlv_wm_state intermediate;
 796                         /* optimal watermarks (inverted) */
 797                         struct vlv_wm_state optimal;
 798                         /* display FIFO split */
 799                         struct vlv_fifo_state fifo_state;
 800                 } vlv;
 801
 802                 struct {
 803                         /* "raw" watermarks */
 804                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 805                         /* intermediate watermarks */
 806                         struct g4x_wm_state intermediate;
 807                         /* optimal watermarks */
 808                         struct g4x_wm_state optimal;
 809                 } g4x;
 810         };
 811
 812         /*
 813          * Platforms with two-step watermark programming will need to
 814          * update watermark programming post-vblank to switch from the
 815          * safe intermediate watermarks to the optimal final
 816          * watermarks.
 817          */
 818         bool need_postvbl_update;
 819 };
 820
 821 enum intel_output_format {
 822         INTEL_OUTPUT_FORMAT_INVALID,
 823         INTEL_OUTPUT_FORMAT_RGB,
 824         INTEL_OUTPUT_FORMAT_YCBCR420,
 825         INTEL_OUTPUT_FORMAT_YCBCR444,
 826 };
 827
 828 struct intel_crtc_state {
 829         struct drm_crtc_state base;
 830
 831         /**
 832          * quirks - bitfield with hw state readout quirks
 833          *
 834          * For various reasons the hw state readout code might not be able to
 835          * completely faithfully read out the current state. These cases are
 836          * tracked with quirk flags so that fastboot and state checker can act
 837          * accordingly.
 838          */
 839 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 840         unsigned long quirks;
 841
 842         unsigned fb_bits; /* framebuffers to flip */
 843         bool update_pipe; /* can a fast modeset be performed? */
 844         bool disable_cxsr;
 845         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 846         bool fb_changed; /* fb on any of the planes is changed */
 847         bool fifo_changed; /* FIFO split is changed */
 848
 849         /* Pipe source size (ie. panel fitter input size)
 850          * All planes will be positioned inside this space,
 851          * and get clipped at the edges. */
 852         int pipe_src_w, pipe_src_h;
 853
 854         /*
 855          * Pipe pixel rate, adjusted for
 856          * panel fitter/pipe scaler downscaling.
 857          */
 858         unsigned int pixel_rate;
 859
 860         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 861          * between pch encoders and cpu encoders. */
 862         bool has_pch_encoder;
 863
 864         /* Are we sending infoframes on the attached port */
 865         bool has_infoframe;
 866
 867         /* CPU Transcoder for the pipe. Currently this can only differ from the
 868          * pipe on Haswell and later (where we have a special eDP transcoder)
 869          * and Broxton (where we have special DSI transcoders). */
 870         enum transcoder cpu_transcoder;
 871
 872         /*
 873          * Use reduced/limited/broadcast rbg range, compressing from the full
 874          * range fed into the crtcs.
 875          */
 876         bool limited_color_range;
 877
 878         /* Bitmask of encoder types (enum intel_output_type)
 879          * driven by the pipe.
 880          */
 881         unsigned int output_types;
 882
 883         /* Whether we should send NULL infoframes. Required for audio. */
 884         bool has_hdmi_sink;
 885
 886         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 887          * has_dp_encoder is set. */
 888         bool has_audio;
 889
 890         /*
 891          * Enable dithering, used when the selected pipe bpp doesn't match the
 892          * plane bpp.
 893          */
 894         bool dither;
 895
 896         /*
 897          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 898          * compliance video pattern tests.
 899          * Disable dither only if it is a compliance test request for
 900          * 18bpp.
 901          */
 902         bool dither_force_disable;
 903
 904         /* Controls for the clock computation, to override various stages. */
 905         bool clock_set;
 906
 907         /* SDVO TV has a bunch of special case. To make multifunction encoders
 908          * work correctly, we need to track this at runtime.*/
 909         bool sdvo_tv_clock;
 910
 911         /*
 912          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 913          * required. This is set in the 2nd loop of calling encoder's
 914          * ->compute_config if the first pick doesn't work out.
 915          */
 916         bool bw_constrained;
 917
 918         /* Settings for the intel dpll used on pretty much everything but
 919          * haswell. */
 920         struct dpll dpll;
 921
 922         /* Selected dpll when shared or NULL. */
 923         struct intel_shared_dpll *shared_dpll;
 924
 925         /* Actual register state of the dpll, for shared dpll cross-checking. */
 926         struct intel_dpll_hw_state dpll_hw_state;
 927
 928         /* DSI PLL registers */
 929         struct {
 930                 u32 ctrl, div;
 931         } dsi_pll;
 932
 933         int pipe_bpp;
 934         struct intel_link_m_n dp_m_n;
 935
 936         /* m2_n2 for eDP downclock */
 937         struct intel_link_m_n dp_m2_n2;
 938         bool has_drrs;
 939
 940         bool has_psr;
 941         bool has_psr2;
 942
 943         /*
 944          * Frequence the dpll for the port should run at. Differs from the
 945          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 946          * already multiplied by pixel_multiplier.
 947          */
 948         int port_clock;
 949
 950         /* Used by SDVO (and if we ever fix it, HDMI). */
 951         unsigned pixel_multiplier;
 952
 953         u8 lane_count;
 954
 955         /*
 956          * Used by platforms having DP/HDMI PHY with programmable lane
 957          * latency optimization.
 958          */
 959         u8 lane_lat_optim_mask;
 960
 961         /* minimum acceptable voltage level */
 962         u8 min_voltage_level;
 963
 964         /* Panel fitter controls for gen2-gen4 + VLV */
 965         struct {
 966                 u32 control;
 967                 u32 pgm_ratios;
 968                 u32 lvds_border_bits;
 969         } gmch_pfit;
 970
 971         /* Panel fitter placement and size for Ironlake+ */
 972         struct {
 973                 u32 pos;
 974                 u32 size;
 975                 bool enabled;
 976                 bool force_thru;
 977         } pch_pfit;
 978
 979         /* FDI configuration, only valid if has_pch_encoder is set. */
 980         int fdi_lanes;
 981         struct intel_link_m_n fdi_m_n;
 982
 983         bool ips_enabled;
 984         bool ips_force_disable;
 985
 986         bool enable_fbc;
 987
 988         bool double_wide;
 989
 990         int pbn;
 991
 992         struct intel_crtc_scaler_state scaler_state;
 993
 994         /* w/a for waiting 2 vblanks during crtc enable */
 995         enum pipe hsw_workaround_pipe;
 996
 997         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 998         bool disable_lp_wm;
 999
1000         struct intel_crtc_wm_state wm;
1001
1002         /* Gamma mode programmed on the pipe */
1003         u32 gamma_mode;
1004
1005         /* CSC mode programmed on the pipe */
1006         u32 csc_mode;
1007
1008         /* bitmask of visible planes (enum plane_id) */
1009         u8 active_planes;
1010         u8 nv12_planes;
1011         u8 c8_planes;
1012
1013         /* bitmask of planes that will be updated during the commit */
1014         u8 update_planes;
1015
1016         /* HDMI scrambling status */
1017         bool hdmi_scrambling;
1018
1019         /* HDMI High TMDS char rate ratio */
1020         bool hdmi_high_tmds_clock_ratio;
1021
1022         /* Output format RGB/YCBCR etc */
1023         enum intel_output_format output_format;
1024
1025         /* Output down scaling is done in LSPCON device */
1026         bool lspcon_downsampling;
1027
1028         /* enable pipe gamma? */
1029         bool gamma_enable;
1030
1031         /* enable pipe csc? */
1032         bool csc_enable;
1033
1034         /* Display Stream compression state */
1035         struct {
1036                 bool compression_enable;
1037                 bool dsc_split;
1038                 u16 compressed_bpp;
1039                 u8 slice_count;
1040         } dsc_params;
1041         struct drm_dsc_config dp_dsc_cfg;
1042
1043         /* Forward Error correction State */
1044         bool fec_enable;
1045 };
1046
1047 struct intel_crtc {
1048         struct drm_crtc base;
1049         enum pipe pipe;
1050         /*
1051          * Whether the crtc and the connected output pipeline is active. Implies
1052          * that crtc->enabled is set, i.e. the current mode configuration has
1053          * some outputs connected to this crtc.
1054          */
1055         bool active;
1056         u8 plane_ids_mask;
1057         unsigned long long enabled_power_domains;
1058         struct intel_overlay *overlay;
1059
1060         struct intel_crtc_state *config;
1061
1062         /* Access to these should be protected by dev_priv->irq_lock. */
1063         bool cpu_fifo_underrun_disabled;
1064         bool pch_fifo_underrun_disabled;
1065
1066         /* per-pipe watermark state */
1067         struct {
1068                 /* watermarks currently being used  */
1069                 union {
1070                         struct intel_pipe_wm ilk;
1071                         struct vlv_wm_state vlv;
1072                         struct g4x_wm_state g4x;
1073                 } active;
1074         } wm;
1075
1076         int scanline_offset;
1077
1078         struct {
1079                 unsigned start_vbl_count;
1080                 ktime_t start_vbl_time;
1081                 int min_vbl, max_vbl;
1082                 int scanline_start;
1083         } debug;
1084
1085         /* scalers available on this crtc */
1086         int num_scalers;
1087 };
1088
1089 struct intel_plane {
1090         struct drm_plane base;
1091         enum i9xx_plane_id i9xx_plane;
1092         enum plane_id id;
1093         enum pipe pipe;
1094         bool has_fbc;
1095         bool has_ccs;
1096         u32 frontbuffer_bit;
1097
1098         struct {
1099                 u32 base, cntl, size;
1100         } cursor;
1101
1102         /*
1103          * NOTE: Do not place new plane state fields here (e.g., when adding
1104          * new plane properties).  New runtime state should now be placed in
1105          * the intel_plane_state structure and accessed via plane_state.
1106          */
1107
1108         unsigned int (*max_stride)(struct intel_plane *plane,
1109                                    u32 pixel_format, u64 modifier,
1110                                    unsigned int rotation);
1111         void (*update_plane)(struct intel_plane *plane,
1112                              const struct intel_crtc_state *crtc_state,
1113                              const struct intel_plane_state *plane_state);
1114         void (*update_slave)(struct intel_plane *plane,
1115                              const struct intel_crtc_state *crtc_state,
1116                              const struct intel_plane_state *plane_state);
1117         void (*disable_plane)(struct intel_plane *plane,
1118                               const struct intel_crtc_state *crtc_state);
1119         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1120         int (*check_plane)(struct intel_crtc_state *crtc_state,
1121                            struct intel_plane_state *plane_state);
1122 };
1123
1124 struct intel_watermark_params {
1125         u16 fifo_size;
1126         u16 max_wm;
1127         u8 default_wm;
1128         u8 guard_size;
1129         u8 cacheline_size;
1130 };
1131
1132 struct cxsr_latency {
1133         bool is_desktop : 1;
1134         bool is_ddr3 : 1;
1135         u16 fsb_freq;
1136         u16 mem_freq;
1137         u16 display_sr;
1138         u16 display_hpll_disable;
1139         u16 cursor_sr;
1140         u16 cursor_hpll_disable;
1141 };
1142
1143 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1144 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1145 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1146 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1147 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1148 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1149 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1150 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1151 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1152
1153 struct intel_hdmi {
1154         i915_reg_t hdmi_reg;
1155         int ddc_bus;
1156         struct {
1157                 enum drm_dp_dual_mode_type type;
1158                 int max_tmds_clock;
1159         } dp_dual_mode;
1160         bool has_hdmi_sink;
1161         bool has_audio;
1162         struct intel_connector *attached_connector;
1163         struct cec_notifier *cec_notifier;
1164 };
1165
1166 struct intel_dp_mst_encoder;
1167 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1168
1169 /*
1170  * enum link_m_n_set:
1171  *      When platform provides two set of M_N registers for dp, we can
1172  *      program them and switch between them incase of DRRS.
1173  *      But When only one such register is provided, we have to program the
1174  *      required divider value on that registers itself based on the DRRS state.
1175  *
1176  * M1_N1        : Program dp_m_n on M1_N1 registers
1177  *                        dp_m2_n2 on M2_N2 registers (If supported)
1178  *
1179  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1180  *                        M2_N2 registers are not supported
1181  */
1182
1183 enum link_m_n_set {
1184         /* Sets the m1_n1 and m2_n2 */
1185         M1_N1 = 0,
1186         M2_N2
1187 };
1188
1189 struct intel_dp_compliance_data {
1190         unsigned long edid;
1191         u8 video_pattern;
1192         u16 hdisplay, vdisplay;
1193         u8 bpc;
1194 };
1195
1196 struct intel_dp_compliance {
1197         unsigned long test_type;
1198         struct intel_dp_compliance_data test_data;
1199         bool test_active;
1200         int test_link_rate;
1201         u8 test_lane_count;
1202 };
1203
1204 struct intel_dp {
1205         i915_reg_t output_reg;
1206         u32 DP;
1207         int link_rate;
1208         u8 lane_count;
1209         u8 sink_count;
1210         bool link_mst;
1211         bool link_trained;
1212         bool has_audio;
1213         bool reset_link_params;
1214         u8 dpcd[DP_RECEIVER_CAP_SIZE];
1215         u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1216         u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1217         u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1218         u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1219         u8 fec_capable;
1220         /* source rates */
1221         int num_source_rates;
1222         const int *source_rates;
1223         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1224         int num_sink_rates;
1225         int sink_rates[DP_MAX_SUPPORTED_RATES];
1226         bool use_rate_select;
1227         /* intersection of source and sink rates */
1228         int num_common_rates;
1229         int common_rates[DP_MAX_SUPPORTED_RATES];
1230         /* Max lane count for the current link */
1231         int max_link_lane_count;
1232         /* Max rate for the current link */
1233         int max_link_rate;
1234         /* sink or branch descriptor */
1235         struct drm_dp_desc desc;
1236         struct drm_dp_aux aux;
1237         u8 train_set[4];
1238         int panel_power_up_delay;
1239         int panel_power_down_delay;
1240         int panel_power_cycle_delay;
1241         int backlight_on_delay;
1242         int backlight_off_delay;
1243         struct delayed_work panel_vdd_work;
1244         bool want_panel_vdd;
1245         unsigned long last_power_on;
1246         unsigned long last_backlight_off;
1247         ktime_t panel_power_off_time;
1248
1249         struct notifier_block edp_notifier;
1250
1251         /*
1252          * Pipe whose power sequencer is currently locked into
1253          * this port. Only relevant on VLV/CHV.
1254          */
1255         enum pipe pps_pipe;
1256         /*
1257          * Pipe currently driving the port. Used for preventing
1258          * the use of the PPS for any pipe currentrly driving
1259          * external DP as that will mess things up on VLV.
1260          */
1261         enum pipe active_pipe;
1262         /*
1263          * Set if the sequencer may be reset due to a power transition,
1264          * requiring a reinitialization. Only relevant on BXT.
1265          */
1266         bool pps_reset;
1267         struct edp_power_seq pps_delays;
1268
1269         bool can_mst; /* this port supports mst */
1270         bool is_mst;
1271         int active_mst_links;
1272         /* connector directly attached - won't be use for modeset in mst world */
1273         struct intel_connector *attached_connector;
1274
1275         /* mst connector list */
1276         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1277         struct drm_dp_mst_topology_mgr mst_mgr;
1278
1279         u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1280         /*
1281          * This function returns the value we have to program the AUX_CTL
1282          * register with to kick off an AUX transaction.
1283          */
1284         u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1285                                 u32 aux_clock_divider);
1286
1287         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1288         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1289
1290         /* This is called before a link training is starterd */
1291         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1292
1293         /* Displayport compliance testing */
1294         struct intel_dp_compliance compliance;
1295
1296         /* Display stream compression testing */
1297         bool force_dsc_en;
1298 };
1299
1300 enum lspcon_vendor {
1301         LSPCON_VENDOR_MCA,
1302         LSPCON_VENDOR_PARADE
1303 };
1304
1305 struct intel_lspcon {
1306         bool active;
1307         enum drm_lspcon_mode mode;
1308         enum lspcon_vendor vendor;
1309 };
1310
1311 struct intel_digital_port {
1312         struct intel_encoder base;
1313         u32 saved_port_bits;
1314         struct intel_dp dp;
1315         struct intel_hdmi hdmi;
1316         struct intel_lspcon lspcon;
1317         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1318         bool release_cl2_override;
1319         u8 max_lanes;
1320         /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1321         enum aux_ch aux_ch;
1322         enum intel_display_power_domain ddi_io_power_domain;
1323         bool tc_legacy_port:1;
1324         enum tc_port_type tc_type;
1325
1326         void (*write_infoframe)(struct intel_encoder *encoder,
1327                                 const struct intel_crtc_state *crtc_state,
1328                                 unsigned int type,
1329                                 const void *frame, ssize_t len);
1330         void (*set_infoframes)(struct intel_encoder *encoder,
1331                                bool enable,
1332                                const struct intel_crtc_state *crtc_state,
1333                                const struct drm_connector_state *conn_state);
1334         bool (*infoframe_enabled)(struct intel_encoder *encoder,
1335                                   const struct intel_crtc_state *pipe_config);
1336 };
1337
1338 struct intel_dp_mst_encoder {
1339         struct intel_encoder base;
1340         enum pipe pipe;
1341         struct intel_digital_port *primary;
1342         struct intel_connector *connector;
1343 };
1344
1345 static inline enum dpio_channel
1346 vlv_dport_to_channel(struct intel_digital_port *dport)
1347 {
1348         switch (dport->base.port) {
1349         case PORT_B:
1350         case PORT_D:
1351                 return DPIO_CH0;
1352         case PORT_C:
1353                 return DPIO_CH1;
1354         default:
1355                 BUG();
1356         }
1357 }
1358
1359 static inline enum dpio_phy
1360 vlv_dport_to_phy(struct intel_digital_port *dport)
1361 {
1362         switch (dport->base.port) {
1363         case PORT_B:
1364         case PORT_C:
1365                 return DPIO_PHY0;
1366         case PORT_D:
1367                 return DPIO_PHY1;
1368         default:
1369                 BUG();
1370         }
1371 }
1372
1373 static inline enum dpio_channel
1374 vlv_pipe_to_channel(enum pipe pipe)
1375 {
1376         switch (pipe) {
1377         case PIPE_A:
1378         case PIPE_C:
1379                 return DPIO_CH0;
1380         case PIPE_B:
1381                 return DPIO_CH1;
1382         default:
1383                 BUG();
1384         }
1385 }
1386
1387 static inline struct intel_crtc *
1388 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1389 {
1390         return dev_priv->pipe_to_crtc_mapping[pipe];
1391 }
1392
1393 static inline struct intel_crtc *
1394 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1395 {
1396         return dev_priv->plane_to_crtc_mapping[plane];
1397 }
1398
1399 struct intel_load_detect_pipe {
1400         struct drm_atomic_state *restore_state;
1401 };
1402
1403 static inline struct intel_encoder *
1404 intel_attached_encoder(struct drm_connector *connector)
1405 {
1406         return to_intel_connector(connector)->encoder;
1407 }
1408
1409 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1410 {
1411         switch (encoder->type) {
1412         case INTEL_OUTPUT_DDI:
1413         case INTEL_OUTPUT_DP:
1414         case INTEL_OUTPUT_EDP:
1415         case INTEL_OUTPUT_HDMI:
1416                 return true;
1417         default:
1418                 return false;
1419         }
1420 }
1421
1422 static inline struct intel_digital_port *
1423 enc_to_dig_port(struct drm_encoder *encoder)
1424 {
1425         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1426
1427         if (intel_encoder_is_dig_port(intel_encoder))
1428                 return container_of(encoder, struct intel_digital_port,
1429                                     base.base);
1430         else
1431                 return NULL;
1432 }
1433
1434 static inline struct intel_digital_port *
1435 conn_to_dig_port(struct intel_connector *connector)
1436 {
1437         return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1438 }
1439
1440 static inline struct intel_dp_mst_encoder *
1441 enc_to_mst(struct drm_encoder *encoder)
1442 {
1443         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1444 }
1445
1446 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1447 {
1448         return &enc_to_dig_port(encoder)->dp;
1449 }
1450
1451 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1452 {
1453         switch (encoder->type) {
1454         case INTEL_OUTPUT_DP:
1455         case INTEL_OUTPUT_EDP:
1456                 return true;
1457         case INTEL_OUTPUT_DDI:
1458                 /* Skip pure HDMI/DVI DDI encoders */
1459                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1460         default:
1461                 return false;
1462         }
1463 }
1464
1465 static inline struct intel_lspcon *
1466 enc_to_intel_lspcon(struct drm_encoder *encoder)
1467 {
1468         return &enc_to_dig_port(encoder)->lspcon;
1469 }
1470
1471 static inline struct intel_digital_port *
1472 dp_to_dig_port(struct intel_dp *intel_dp)
1473 {
1474         return container_of(intel_dp, struct intel_digital_port, dp);
1475 }
1476
1477 static inline struct intel_lspcon *
1478 dp_to_lspcon(struct intel_dp *intel_dp)
1479 {
1480         return &dp_to_dig_port(intel_dp)->lspcon;
1481 }
1482
1483 static inline struct drm_i915_private *
1484 dp_to_i915(struct intel_dp *intel_dp)
1485 {
1486         return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1487 }
1488
1489 static inline struct intel_digital_port *
1490 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1491 {
1492         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1493 }
1494
1495 static inline struct intel_plane_state *
1496 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1497                                  struct intel_plane *plane)
1498 {
1499         struct drm_plane_state *ret =
1500                 drm_atomic_get_plane_state(&state->base, &plane->base);
1501
1502         if (IS_ERR(ret))
1503                 return ERR_CAST(ret);
1504
1505         return to_intel_plane_state(ret);
1506 }
1507
1508 static inline struct intel_plane_state *
1509 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1510                                  struct intel_plane *plane)
1511 {
1512         return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1513                                                                    &plane->base));
1514 }
1515
1516 static inline struct intel_plane_state *
1517 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1518                                  struct intel_plane *plane)
1519 {
1520         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1521                                                                    &plane->base));
1522 }
1523
1524 static inline struct intel_crtc_state *
1525 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1526                                 struct intel_crtc *crtc)
1527 {
1528         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1529                                                                  &crtc->base));
1530 }
1531
1532 static inline struct intel_crtc_state *
1533 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1534                                 struct intel_crtc *crtc)
1535 {
1536         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1537                                                                  &crtc->base));
1538 }
1539
1540 /* intel_fifo_underrun.c */
1541 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1542                                            enum pipe pipe, bool enable);
1543 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1544                                            enum pipe pch_transcoder,
1545                                            bool enable);
1546 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1547                                          enum pipe pipe);
1548 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1549                                          enum pipe pch_transcoder);
1550 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1551 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1552
1553 /* i915_irq.c */
1554 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1555 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1556 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1557 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1558 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1559 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1560 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1561 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1562
1563 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1564                                             u32 mask)
1565 {
1566         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1567 }
1568
1569 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1570 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1571 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1572 {
1573         /*
1574          * We only use drm_irq_uninstall() at unload and VT switch, so
1575          * this is the only thing we need to check.
1576          */
1577         return dev_priv->runtime_pm.irqs_enabled;
1578 }
1579
1580 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1581 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1582                                      u8 pipe_mask);
1583 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1584                                      u8 pipe_mask);
1585 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1586 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1587 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1588
1589 /* intel_crt.c */
1590 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1591                             i915_reg_t adpa_reg, enum pipe *pipe);
1592 void intel_crt_init(struct drm_i915_private *dev_priv);
1593 void intel_crt_reset(struct drm_encoder *encoder);
1594
1595 /* intel_ddi.c */
1596 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1597                                 const struct intel_crtc_state *old_crtc_state,
1598                                 const struct drm_connector_state *old_conn_state);
1599 void hsw_fdi_link_train(struct intel_crtc *crtc,
1600                         const struct intel_crtc_state *crtc_state);
1601 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1602 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1603 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1604 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1605 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1606 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1607 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1608 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1609 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1610 void intel_ddi_get_config(struct intel_encoder *encoder,
1611                           struct intel_crtc_state *pipe_config);
1612
1613 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1614                                     bool state);
1615 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1616                                          struct intel_crtc_state *crtc_state);
1617 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1618 u32 ddi_signal_levels(struct intel_dp *intel_dp);
1619 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1620 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1621                                  u8 voltage_swing);
1622 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1623                                      bool enable);
1624 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
1625 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1626                         enum intel_dpll_id pll_id);
1627
1628 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1629                                    int color_plane, unsigned int height);
1630
1631 /* intel_audio.c */
1632 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1633 void intel_audio_codec_enable(struct intel_encoder *encoder,
1634                               const struct intel_crtc_state *crtc_state,
1635                               const struct drm_connector_state *conn_state);
1636 void intel_audio_codec_disable(struct intel_encoder *encoder,
1637                                const struct intel_crtc_state *old_crtc_state,
1638                                const struct drm_connector_state *old_conn_state);
1639 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1640 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1641 void intel_audio_init(struct drm_i915_private *dev_priv);
1642 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1643
1644 /* intel_cdclk.c */
1645 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1646 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1647 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1648 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1649 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1650 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1651 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1652 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1653 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1654 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1655 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1656 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1657 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1658 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1659                                const struct intel_cdclk_state *b);
1660 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1661                          const struct intel_cdclk_state *b);
1662 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1663                      const struct intel_cdclk_state *cdclk_state);
1664 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1665                             const char *context);
1666
1667 /* intel_display.c */
1668 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1669 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1670 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1671 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1672 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1673                       const char *name, u32 reg, int ref_freq);
1674 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1675                            const char *name, u32 reg);
1676 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1677 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1678 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1679 unsigned int intel_fb_xy_to_linear(int x, int y,
1680                                    const struct intel_plane_state *state,
1681                                    int plane);
1682 void intel_add_fb_offsets(int *x, int *y,
1683                           const struct intel_plane_state *state, int plane);
1684 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1685 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1686 void intel_mark_busy(struct drm_i915_private *dev_priv);
1687 void intel_mark_idle(struct drm_i915_private *dev_priv);
1688 int intel_display_suspend(struct drm_device *dev);
1689 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1690 void intel_encoder_destroy(struct drm_encoder *encoder);
1691 struct drm_display_mode *
1692 intel_encoder_current_mode(struct intel_encoder *encoder);
1693 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1694 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1695 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1696                               enum port port);
1697 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1698                                       struct drm_file *file_priv);
1699 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1700                                              enum pipe pipe);
1701 static inline bool
1702 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1703                     enum intel_output_type type)
1704 {
1705         return crtc_state->output_types & (1 << type);
1706 }
1707 static inline bool
1708 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1709 {
1710         return crtc_state->output_types &
1711                 ((1 << INTEL_OUTPUT_DP) |
1712                  (1 << INTEL_OUTPUT_DP_MST) |
1713                  (1 << INTEL_OUTPUT_EDP));
1714 }
1715 static inline void
1716 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1717 {
1718         drm_wait_one_vblank(&dev_priv->drm, pipe);
1719 }
1720 static inline void
1721 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1722 {
1723         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1724
1725         if (crtc->active)
1726                 intel_wait_for_vblank(dev_priv, pipe);
1727 }
1728
1729 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1730
1731 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1732 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1733                          struct intel_digital_port *dport,
1734                          unsigned int expected_mask);
1735 int intel_get_load_detect_pipe(struct drm_connector *connector,
1736                                const struct drm_display_mode *mode,
1737                                struct intel_load_detect_pipe *old,
1738                                struct drm_modeset_acquire_ctx *ctx);
1739 void intel_release_load_detect_pipe(struct drm_connector *connector,
1740                                     struct intel_load_detect_pipe *old,
1741                                     struct drm_modeset_acquire_ctx *ctx);
1742 struct i915_vma *
1743 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1744                            const struct i915_ggtt_view *view,
1745                            bool uses_fence,
1746                            unsigned long *out_flags);
1747 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1748 struct drm_framebuffer *
1749 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1750                          struct drm_mode_fb_cmd2 *mode_cmd);
1751 int intel_prepare_plane_fb(struct drm_plane *plane,
1752                            struct drm_plane_state *new_state);
1753 void intel_cleanup_plane_fb(struct drm_plane *plane,
1754                             struct drm_plane_state *old_state);
1755 int intel_plane_atomic_get_property(struct drm_plane *plane,
1756                                     const struct drm_plane_state *state,
1757                                     struct drm_property *property,
1758                                     u64 *val);
1759 int intel_plane_atomic_set_property(struct drm_plane *plane,
1760                                     struct drm_plane_state *state,
1761                                     struct drm_property *property,
1762                                     u64 val);
1763 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1764                                     struct drm_crtc_state *crtc_state,
1765                                     const struct intel_plane_state *old_plane_state,
1766                                     struct drm_plane_state *plane_state);
1767
1768 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1769                                     enum pipe pipe);
1770
1771 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1772                      const struct dpll *dpll);
1773 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1774 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1775
1776 /* modesetting asserts */
1777 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1778                            enum pipe pipe);
1779 void assert_pll(struct drm_i915_private *dev_priv,
1780                 enum pipe pipe, bool state);
1781 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1782 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1783 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1784 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1785 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1786 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1787                        enum pipe pipe, bool state);
1788 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1789 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1790 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1791 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1792 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1793 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1794 void intel_finish_reset(struct drm_i915_private *dev_priv);
1795 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1796 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1797 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1798 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1799 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1800 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1801 unsigned int skl_cdclk_get_vco(unsigned int freq);
1802 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1803 void intel_dp_get_m_n(struct intel_crtc *crtc,
1804                       struct intel_crtc_state *pipe_config);
1805 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1806                       enum link_m_n_set m_n);
1807 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1808 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1809                         struct dpll *best_clock);
1810 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1811
1812 bool intel_crtc_active(struct intel_crtc *crtc);
1813 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1814 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1815 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1816 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1817 enum intel_display_power_domain
1818 intel_aux_power_domain(struct intel_digital_port *dig_port);
1819 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1820                                  struct intel_crtc_state *pipe_config);
1821 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1822                                   struct intel_crtc_state *crtc_state);
1823
1824 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1825 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1826 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1827                   u32 pixel_format);
1828
1829 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1830 {
1831         return i915_ggtt_offset(state->vma);
1832 }
1833
1834 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1835                         const struct intel_plane_state *plane_state);
1836 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
1837 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1838                   const struct intel_plane_state *plane_state);
1839 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
1840 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1841                      int plane);
1842 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1843 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1844 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1845 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1846                                    u32 pixel_format, u64 modifier,
1847                                    unsigned int rotation);
1848
1849 /* intel_connector.c */
1850 int intel_connector_init(struct intel_connector *connector);
1851 struct intel_connector *intel_connector_alloc(void);
1852 void intel_connector_free(struct intel_connector *connector);
1853 void intel_connector_destroy(struct drm_connector *connector);
1854 int intel_connector_register(struct drm_connector *connector);
1855 void intel_connector_unregister(struct drm_connector *connector);
1856 void intel_connector_attach_encoder(struct intel_connector *connector,
1857                                     struct intel_encoder *encoder);
1858 bool intel_connector_get_hw_state(struct intel_connector *connector);
1859 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1860 int intel_connector_update_modes(struct drm_connector *connector,
1861                                  struct edid *edid);
1862 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1863 void intel_attach_force_audio_property(struct drm_connector *connector);
1864 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1865 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1866
1867 /* intel_csr.c */
1868 void intel_csr_ucode_init(struct drm_i915_private *);
1869 void intel_csr_load_program(struct drm_i915_private *);
1870 void intel_csr_ucode_fini(struct drm_i915_private *);
1871 void intel_csr_ucode_suspend(struct drm_i915_private *);
1872 void intel_csr_ucode_resume(struct drm_i915_private *);
1873
1874 /* intel_dp.c */
1875 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1876                            i915_reg_t dp_reg, enum port port,
1877                            enum pipe *pipe);
1878 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1879                    enum port port);
1880 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1881                              struct intel_connector *intel_connector);
1882 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1883                               int link_rate, u8 lane_count,
1884                               bool link_mst);
1885 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1886                                             int link_rate, u8 lane_count);
1887 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1888 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1889 int intel_dp_retrain_link(struct intel_encoder *encoder,
1890                           struct drm_modeset_acquire_ctx *ctx);
1891 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1892 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1893                                            const struct intel_crtc_state *crtc_state,
1894                                            bool enable);
1895 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1896 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1897 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
1898 int intel_dp_compute_config(struct intel_encoder *encoder,
1899                             struct intel_crtc_state *pipe_config,
1900                             struct drm_connector_state *conn_state);
1901 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1902 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1903 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1904                                   bool long_hpd);
1905 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1906                             const struct drm_connector_state *conn_state);
1907 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1908 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1909 void intel_edp_panel_on(struct intel_dp *intel_dp);
1910 void intel_edp_panel_off(struct intel_dp *intel_dp);
1911 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1912 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1913 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1914 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1915 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1916 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1917 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1918 u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
1919 void intel_plane_destroy(struct drm_plane *plane);
1920 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1921                            const struct intel_crtc_state *crtc_state);
1922 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1923                             const struct intel_crtc_state *crtc_state);
1924 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1925                                unsigned int frontbuffer_bits);
1926 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1927                           unsigned int frontbuffer_bits);
1928
1929 void
1930 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1931                                        u8 dp_train_pat);
1932 void
1933 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1934 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1935 u8
1936 intel_dp_voltage_max(struct intel_dp *intel_dp);
1937 u8
1938 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
1939 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1940                            u8 *link_bw, u8 *rate_select);
1941 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1942 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1943 bool
1944 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]);
1945 u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
1946                                 int mode_clock, int mode_hdisplay);
1947 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
1948                                 int mode_hdisplay);
1949
1950 /* intel_vdsc.c */
1951 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
1952                                 struct intel_crtc_state *pipe_config);
1953 enum intel_display_power_domain
1954 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
1955
1956 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1957 {
1958         return ~((1 << lane_count) - 1) & 0xf;
1959 }
1960
1961 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1962 int intel_dp_link_required(int pixel_clock, int bpp);
1963 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1964 bool intel_digital_port_connected(struct intel_encoder *encoder);
1965 void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
1966                            struct intel_digital_port *dig_port);
1967
1968 /* intel_dp_aux_backlight.c */
1969 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1970
1971 /* intel_dp_mst.c */
1972 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1973 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1974 /* vlv_dsi.c */
1975 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1976
1977 /* icl_dsi.c */
1978 void icl_dsi_init(struct drm_i915_private *dev_priv);
1979
1980 /* intel_dsi_dcs_backlight.c */
1981 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1982
1983 /* intel_dvo.c */
1984 void intel_dvo_init(struct drm_i915_private *dev_priv);
1985 /* intel_hotplug.c */
1986 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1987 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1988                            struct intel_connector *connector);
1989
1990 /* legacy fbdev emulation in intel_fbdev.c */
1991 #ifdef CONFIG_DRM_FBDEV_EMULATION
1992 extern int intel_fbdev_init(struct drm_device *dev);
1993 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1994 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1995 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1996 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1997 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1998 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1999 #else
2000 static inline int intel_fbdev_init(struct drm_device *dev)
2001 {
2002         return 0;
2003 }
2004
2005 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
2006 {
2007 }
2008
2009 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
2010 {
2011 }
2012
2013 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
2014 {
2015 }
2016
2017 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
2018 {
2019 }
2020
2021 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
2022 {
2023 }
2024
2025 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
2026 {
2027 }
2028 #endif
2029
2030 /* intel_fbc.c */
2031 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
2032                            struct intel_atomic_state *state);
2033 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
2034 void intel_fbc_pre_update(struct intel_crtc *crtc,
2035                           struct intel_crtc_state *crtc_state,
2036                           struct intel_plane_state *plane_state);
2037 void intel_fbc_post_update(struct intel_crtc *crtc);
2038 void intel_fbc_init(struct drm_i915_private *dev_priv);
2039 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
2040 void intel_fbc_enable(struct intel_crtc *crtc,
2041                       struct intel_crtc_state *crtc_state,
2042                       struct intel_plane_state *plane_state);
2043 void intel_fbc_disable(struct intel_crtc *crtc);
2044 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
2045 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
2046                           unsigned int frontbuffer_bits,
2047                           enum fb_op_origin origin);
2048 void intel_fbc_flush(struct drm_i915_private *dev_priv,
2049                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
2050 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
2051 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
2052 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
2053
2054 /* intel_hdmi.c */
2055 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
2056                      enum port port);
2057 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2058                                struct intel_connector *intel_connector);
2059 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
2060 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2061                               struct intel_crtc_state *pipe_config,
2062                               struct drm_connector_state *conn_state);
2063 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2064                                        struct drm_connector *connector,
2065                                        bool high_tmds_clock_ratio,
2066                                        bool scrambling);
2067 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
2068 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
2069
2070 /* intel_lvds.c */
2071 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
2072                              i915_reg_t lvds_reg, enum pipe *pipe);
2073 void intel_lvds_init(struct drm_i915_private *dev_priv);
2074 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
2075 bool intel_is_dual_link_lvds(struct drm_device *dev);
2076
2077 /* intel_overlay.c */
2078 void intel_overlay_setup(struct drm_i915_private *dev_priv);
2079 void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
2080 int intel_overlay_switch_off(struct intel_overlay *overlay);
2081 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
2082                                   struct drm_file *file_priv);
2083 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
2084                               struct drm_file *file_priv);
2085 void intel_overlay_reset(struct drm_i915_private *dev_priv);
2086
2087
2088 /* intel_panel.c */
2089 int intel_panel_init(struct intel_panel *panel,
2090                      struct drm_display_mode *fixed_mode,
2091                      struct drm_display_mode *downclock_mode);
2092 void intel_panel_fini(struct intel_panel *panel);
2093 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
2094                             struct drm_display_mode *adjusted_mode);
2095 void intel_pch_panel_fitting(struct intel_crtc *crtc,
2096                              struct intel_crtc_state *pipe_config,
2097                              int fitting_mode);
2098 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
2099                               struct intel_crtc_state *pipe_config,
2100                               int fitting_mode);
2101 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
2102                                     u32 level, u32 max);
2103 int intel_panel_setup_backlight(struct drm_connector *connector,
2104                                 enum pipe pipe);
2105 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
2106                                   const struct drm_connector_state *conn_state);
2107 void intel_panel_update_backlight(struct intel_encoder *encoder,
2108                                   const struct intel_crtc_state *crtc_state,
2109                                   const struct drm_connector_state *conn_state);
2110 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
2111 extern struct drm_display_mode *intel_find_panel_downclock(
2112                                 struct drm_i915_private *dev_priv,
2113                                 struct drm_display_mode *fixed_mode,
2114                                 struct drm_connector *connector);
2115
2116 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
2117 int intel_backlight_device_register(struct intel_connector *connector);
2118 void intel_backlight_device_unregister(struct intel_connector *connector);
2119 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2120 static inline int intel_backlight_device_register(struct intel_connector *connector)
2121 {
2122         return 0;
2123 }
2124 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
2125 {
2126 }
2127 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2128
2129 /* intel_hdcp.c */
2130 void intel_hdcp_atomic_check(struct drm_connector *connector,
2131                              struct drm_connector_state *old_state,
2132                              struct drm_connector_state *new_state);
2133 int intel_hdcp_init(struct intel_connector *connector,
2134                     const struct intel_hdcp_shim *hdcp_shim);
2135 int intel_hdcp_enable(struct intel_connector *connector);
2136 int intel_hdcp_disable(struct intel_connector *connector);
2137 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2138 bool intel_hdcp_capable(struct intel_connector *connector);
2139 void intel_hdcp_component_init(struct drm_i915_private *dev_priv);
2140 void intel_hdcp_component_fini(struct drm_i915_private *dev_priv);
2141 void intel_hdcp_cleanup(struct intel_connector *connector);
2142 void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
2143
2144 /* intel_psr.c */
2145 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2146 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2147 void intel_psr_enable(struct intel_dp *intel_dp,
2148                       const struct intel_crtc_state *crtc_state);
2149 void intel_psr_disable(struct intel_dp *intel_dp,
2150                       const struct intel_crtc_state *old_crtc_state);
2151 void intel_psr_update(struct intel_dp *intel_dp,
2152                       const struct intel_crtc_state *crtc_state);
2153 int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);
2154 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2155                           unsigned frontbuffer_bits,
2156                           enum fb_op_origin origin);
2157 void intel_psr_flush(struct drm_i915_private *dev_priv,
2158                      unsigned frontbuffer_bits,
2159                      enum fb_op_origin origin);
2160 void intel_psr_init(struct drm_i915_private *dev_priv);
2161 void intel_psr_compute_config(struct intel_dp *intel_dp,
2162                               struct intel_crtc_state *crtc_state);
2163 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2164 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2165 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2166 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2167                             u32 *out_value);
2168 bool intel_psr_enabled(struct intel_dp *intel_dp);
2169
2170 /* intel_quirks.c */
2171 void intel_init_quirks(struct drm_i915_private *dev_priv);
2172
2173 /* intel_runtime_pm.c */
2174 void intel_runtime_pm_init_early(struct drm_i915_private *dev_priv);
2175 int intel_power_domains_init(struct drm_i915_private *);
2176 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2177 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2178 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2179 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2180 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
2181 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2182 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2183
2184 enum i915_drm_suspend_mode {
2185         I915_DRM_SUSPEND_IDLE,
2186         I915_DRM_SUSPEND_MEM,
2187         I915_DRM_SUSPEND_HIBERNATE,
2188 };
2189
2190 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2191                                  enum i915_drm_suspend_mode);
2192 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2193 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2194 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2195 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2196 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2197 void intel_runtime_pm_cleanup(struct drm_i915_private *dev_priv);
2198 const char *
2199 intel_display_power_domain_str(enum intel_display_power_domain domain);
2200
2201 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2202                                     enum intel_display_power_domain domain);
2203 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2204                                       enum intel_display_power_domain domain);
2205 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
2206                                         enum intel_display_power_domain domain);
2207 intel_wakeref_t
2208 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2209                                    enum intel_display_power_domain domain);
2210 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
2211                                        enum intel_display_power_domain domain);
2212 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2213 void intel_display_power_put(struct drm_i915_private *dev_priv,
2214                              enum intel_display_power_domain domain,
2215                              intel_wakeref_t wakeref);
2216 #else
2217 #define intel_display_power_put(i915, domain, wakeref) \
2218         intel_display_power_put_unchecked(i915, domain)
2219 #endif
2220 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2221                             u8 req_slices);
2222
2223 static inline void
2224 assert_rpm_device_not_suspended(struct drm_i915_private *i915)
2225 {
2226         WARN_ONCE(i915->runtime_pm.suspended,
2227                   "Device suspended during HW access\n");
2228 }
2229
2230 static inline void
2231 assert_rpm_wakelock_held(struct drm_i915_private *i915)
2232 {
2233         assert_rpm_device_not_suspended(i915);
2234         WARN_ONCE(!atomic_read(&i915->runtime_pm.wakeref_count),
2235                   "RPM wakelock ref not held during HW access");
2236 }
2237
2238 /**
2239  * disable_rpm_wakeref_asserts - disable the RPM assert checks
2240  * @i915: i915 device instance
2241  *
2242  * This function disable asserts that check if we hold an RPM wakelock
2243  * reference, while keeping the device-not-suspended checks still enabled.
2244  * It's meant to be used only in special circumstances where our rule about
2245  * the wakelock refcount wrt. the device power state doesn't hold. According
2246  * to this rule at any point where we access the HW or want to keep the HW in
2247  * an active state we must hold an RPM wakelock reference acquired via one of
2248  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2249  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2250  * forcewake release timer, and the GPU RPS and hangcheck works. All other
2251  * users should avoid using this function.
2252  *
2253  * Any calls to this function must have a symmetric call to
2254  * enable_rpm_wakeref_asserts().
2255  */
2256 static inline void
2257 disable_rpm_wakeref_asserts(struct drm_i915_private *i915)
2258 {
2259         atomic_inc(&i915->runtime_pm.wakeref_count);
2260 }
2261
2262 /**
2263  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2264  * @i915: i915 device instance
2265  *
2266  * This function re-enables the RPM assert checks after disabling them with
2267  * disable_rpm_wakeref_asserts. It's meant to be used only in special
2268  * circumstances otherwise its use should be avoided.
2269  *
2270  * Any calls to this function must have a symmetric call to
2271  * disable_rpm_wakeref_asserts().
2272  */
2273 static inline void
2274 enable_rpm_wakeref_asserts(struct drm_i915_private *i915)
2275 {
2276         atomic_dec(&i915->runtime_pm.wakeref_count);
2277 }
2278
2279 intel_wakeref_t intel_runtime_pm_get(struct drm_i915_private *i915);
2280 intel_wakeref_t intel_runtime_pm_get_if_in_use(struct drm_i915_private *i915);
2281 intel_wakeref_t intel_runtime_pm_get_noresume(struct drm_i915_private *i915);
2282
2283 #define with_intel_runtime_pm(i915, wf) \
2284         for ((wf) = intel_runtime_pm_get(i915); (wf); \
2285              intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2286
2287 #define with_intel_runtime_pm_if_in_use(i915, wf) \
2288         for ((wf) = intel_runtime_pm_get_if_in_use(i915); (wf); \
2289              intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2290
2291 void intel_runtime_pm_put_unchecked(struct drm_i915_private *i915);
2292 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2293 void intel_runtime_pm_put(struct drm_i915_private *i915, intel_wakeref_t wref);
2294 #else
2295 #define intel_runtime_pm_put(i915, wref) intel_runtime_pm_put_unchecked(i915)
2296 #endif
2297
2298 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2299 void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
2300                                     struct drm_printer *p);
2301 #else
2302 static inline void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
2303                                                   struct drm_printer *p)
2304 {
2305 }
2306 #endif
2307
2308 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2309                              bool override, unsigned int mask);
2310 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2311                           enum dpio_channel ch, bool override);
2312
2313
2314 /* intel_pm.c */
2315 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2316 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2317 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2318 void intel_update_watermarks(struct intel_crtc *crtc);
2319 void intel_init_pm(struct drm_i915_private *dev_priv);
2320 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2321 void intel_pm_setup(struct drm_i915_private *dev_priv);
2322 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2323 void intel_gpu_ips_teardown(void);
2324 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2325 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2326 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2327 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2328 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2329 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2330 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2331 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2332 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2333 void gen6_rps_boost(struct i915_request *rq);
2334 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
2335 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
2336 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
2337 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
2338 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
2339                                struct skl_ddb_entry *ddb_y,
2340                                struct skl_ddb_entry *ddb_uv);
2341 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2342                           struct skl_ddb_allocation *ddb /* out */);
2343 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
2344                               struct skl_pipe_wm *out);
2345 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2346 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2347 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2348 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2349 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2350 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2351                          const struct skl_wm_level *l2);
2352 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
2353                                  const struct skl_ddb_entry entries[],
2354                                  int num_entries, int ignore_idx);
2355 void skl_write_plane_wm(struct intel_plane *plane,
2356                         const struct intel_crtc_state *crtc_state);
2357 void skl_write_cursor_wm(struct intel_plane *plane,
2358                          const struct intel_crtc_state *crtc_state);
2359 bool ilk_disable_lp_wm(struct drm_device *dev);
2360 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2361                                   struct intel_crtc_state *cstate);
2362 void intel_init_ipc(struct drm_i915_private *dev_priv);
2363 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2364
2365 /* intel_sdvo.c */
2366 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2367                              i915_reg_t sdvo_reg, enum pipe *pipe);
2368 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2369                      i915_reg_t reg, enum port port);
2370
2371
2372 /* intel_sprite.c */
2373 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2374                              int usecs);
2375 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2376                                               enum pipe pipe, int plane);
2377 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2378                                     struct drm_file *file_priv);
2379 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2380 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2381 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2382 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2383 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2384 struct intel_plane *
2385 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2386                            enum pipe pipe, enum plane_id plane_id);
2387
2388 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2389 {
2390         /* Don't need to do a gen check, these planes are only available on gen11 */
2391         if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2392                 return true;
2393
2394         return false;
2395 }
2396
2397 static inline bool icl_is_hdr_plane(struct intel_plane *plane)
2398 {
2399         if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
2400                 return false;
2401
2402         return plane->id < PLANE_SPRITE2;
2403 }
2404
2405 /* intel_tv.c */
2406 void intel_tv_init(struct drm_i915_private *dev_priv);
2407
2408 /* intel_atomic.c */
2409 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2410                                                 const struct drm_connector_state *state,
2411                                                 struct drm_property *property,
2412                                                 u64 *val);
2413 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2414                                                 struct drm_connector_state *state,
2415                                                 struct drm_property *property,
2416                                                 u64 val);
2417 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2418                                          struct drm_connector_state *new_state);
2419 struct drm_connector_state *
2420 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2421
2422 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2423 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2424                                struct drm_crtc_state *state);
2425 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2426 void intel_atomic_state_clear(struct drm_atomic_state *);
2427
2428 static inline struct intel_crtc_state *
2429 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2430                             struct intel_crtc *crtc)
2431 {
2432         struct drm_crtc_state *crtc_state;
2433         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2434         if (IS_ERR(crtc_state))
2435                 return ERR_CAST(crtc_state);
2436
2437         return to_intel_crtc_state(crtc_state);
2438 }
2439
2440 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2441                                struct intel_crtc *intel_crtc,
2442                                struct intel_crtc_state *crtc_state);
2443
2444 /* intel_atomic_plane.c */
2445 void intel_update_plane(struct intel_plane *plane,
2446                         const struct intel_crtc_state *crtc_state,
2447                         const struct intel_plane_state *plane_state);
2448 void intel_update_slave(struct intel_plane *plane,
2449                         const struct intel_crtc_state *crtc_state,
2450                         const struct intel_plane_state *plane_state);
2451 void intel_disable_plane(struct intel_plane *plane,
2452                          const struct intel_crtc_state *crtc_state);
2453 struct intel_plane *intel_plane_alloc(void);
2454 void intel_plane_free(struct intel_plane *plane);
2455 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2456 void intel_plane_destroy_state(struct drm_plane *plane,
2457                                struct drm_plane_state *state);
2458 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2459 void skl_update_planes_on_crtc(struct intel_atomic_state *state,
2460                                struct intel_crtc *crtc);
2461 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
2462                                 struct intel_crtc *crtc);
2463 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2464                                         struct intel_crtc_state *crtc_state,
2465                                         const struct intel_plane_state *old_plane_state,
2466                                         struct intel_plane_state *intel_state);
2467
2468 /* intel_color.c */
2469 void intel_color_init(struct intel_crtc *crtc);
2470 int intel_color_check(struct intel_crtc_state *crtc_state);
2471 void intel_color_commit(const struct intel_crtc_state *crtc_state);
2472 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
2473
2474 /* intel_lspcon.c */
2475 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2476 void lspcon_resume(struct intel_lspcon *lspcon);
2477 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2478 void lspcon_write_infoframe(struct intel_encoder *encoder,
2479                             const struct intel_crtc_state *crtc_state,
2480                             unsigned int type,
2481                             const void *buf, ssize_t len);
2482 void lspcon_set_infoframes(struct intel_encoder *encoder,
2483                            bool enable,
2484                            const struct intel_crtc_state *crtc_state,
2485                            const struct drm_connector_state *conn_state);
2486 bool lspcon_infoframe_enabled(struct intel_encoder *encoder,
2487                               const struct intel_crtc_state *pipe_config);
2488 void lspcon_ycbcr420_config(struct drm_connector *connector,
2489                             struct intel_crtc_state *crtc_state);
2490
2491 /* intel_pipe_crc.c */
2492 #ifdef CONFIG_DEBUG_FS
2493 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2494 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2495                                  const char *source_name, size_t *values_cnt);
2496 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2497                                               size_t *count);
2498 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2499 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2500 #else
2501 #define intel_crtc_set_crc_source NULL
2502 #define intel_crtc_verify_crc_source NULL
2503 #define intel_crtc_get_crc_sources NULL
2504 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2505 {
2506 }
2507
2508 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2509 {
2510 }
2511 #endif
2512 #endif /* __INTEL_DRV_H__ */