Merge tag 'drm-intel-next-2019-03-20' of git://anongit.freedesktop.org/drm/drm-intel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_drv.h
1 /*
2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright (c) 2007-2008 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23  * IN THE SOFTWARE.
24  */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <linux/stackdepot.h>
33 #include <drm/i915_drm.h>
34 #include "i915_drv.h"
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_rect.h>
42 #include <drm/drm_vblank.h>
43 #include <drm/drm_atomic.h>
44 #include <drm/i915_mei_hdcp_interface.h>
45 #include <media/cec-notifier.h>
46
47 struct drm_printer;
48
49 /**
50  * __wait_for - magic wait macro
51  *
52  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
53  * important that we check the condition again after having timed out, since the
54  * timeout could be due to preemption or similar and we've never had a chance to
55  * check the condition before the timeout.
56  */
57 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
58         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
59         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
60         int ret__;                                                      \
61         might_sleep();                                                  \
62         for (;;) {                                                      \
63                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
64                 OP;                                                     \
65                 /* Guarantee COND check prior to timeout */             \
66                 barrier();                                              \
67                 if (COND) {                                             \
68                         ret__ = 0;                                      \
69                         break;                                          \
70                 }                                                       \
71                 if (expired__) {                                        \
72                         ret__ = -ETIMEDOUT;                             \
73                         break;                                          \
74                 }                                                       \
75                 usleep_range(wait__, wait__ * 2);                       \
76                 if (wait__ < (Wmax))                                    \
77                         wait__ <<= 1;                                   \
78         }                                                               \
79         ret__;                                                          \
80 })
81
82 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
83                                                    (Wmax))
84 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
85
86 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
87 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
88 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
89 #else
90 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
91 #endif
92
93 #define _wait_for_atomic(COND, US, ATOMIC) \
94 ({ \
95         int cpu, ret, timeout = (US) * 1000; \
96         u64 base; \
97         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
98         if (!(ATOMIC)) { \
99                 preempt_disable(); \
100                 cpu = smp_processor_id(); \
101         } \
102         base = local_clock(); \
103         for (;;) { \
104                 u64 now = local_clock(); \
105                 if (!(ATOMIC)) \
106                         preempt_enable(); \
107                 /* Guarantee COND check prior to timeout */ \
108                 barrier(); \
109                 if (COND) { \
110                         ret = 0; \
111                         break; \
112                 } \
113                 if (now - base >= timeout) { \
114                         ret = -ETIMEDOUT; \
115                         break; \
116                 } \
117                 cpu_relax(); \
118                 if (!(ATOMIC)) { \
119                         preempt_disable(); \
120                         if (unlikely(cpu != smp_processor_id())) { \
121                                 timeout -= now - base; \
122                                 cpu = smp_processor_id(); \
123                                 base = local_clock(); \
124                         } \
125                 } \
126         } \
127         ret; \
128 })
129
130 #define wait_for_us(COND, US) \
131 ({ \
132         int ret__; \
133         BUILD_BUG_ON(!__builtin_constant_p(US)); \
134         if ((US) > 10) \
135                 ret__ = _wait_for((COND), (US), 10, 10); \
136         else \
137                 ret__ = _wait_for_atomic((COND), (US), 0); \
138         ret__; \
139 })
140
141 #define wait_for_atomic_us(COND, US) \
142 ({ \
143         BUILD_BUG_ON(!__builtin_constant_p(US)); \
144         BUILD_BUG_ON((US) > 50000); \
145         _wait_for_atomic((COND), (US), 1); \
146 })
147
148 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
149
150 #define KHz(x) (1000 * (x))
151 #define MHz(x) KHz(1000 * (x))
152
153 #define KBps(x) (1000 * (x))
154 #define MBps(x) KBps(1000 * (x))
155 #define GBps(x) ((u64)1000 * MBps((x)))
156
157 /*
158  * Display related stuff
159  */
160
161 /* store information about an Ixxx DVO */
162 /* The i830->i865 use multiple DVOs with multiple i2cs */
163 /* the i915, i945 have a single sDVO i2c bus - which is different */
164 #define MAX_OUTPUTS 6
165 /* maximum connectors per crtcs in the mode set */
166
167 #define INTEL_I2C_BUS_DVO 1
168 #define INTEL_I2C_BUS_SDVO 2
169
170 /* these are outputs from the chip - integrated only
171    external chips are via DVO or SDVO output */
172 enum intel_output_type {
173         INTEL_OUTPUT_UNUSED = 0,
174         INTEL_OUTPUT_ANALOG = 1,
175         INTEL_OUTPUT_DVO = 2,
176         INTEL_OUTPUT_SDVO = 3,
177         INTEL_OUTPUT_LVDS = 4,
178         INTEL_OUTPUT_TVOUT = 5,
179         INTEL_OUTPUT_HDMI = 6,
180         INTEL_OUTPUT_DP = 7,
181         INTEL_OUTPUT_EDP = 8,
182         INTEL_OUTPUT_DSI = 9,
183         INTEL_OUTPUT_DDI = 10,
184         INTEL_OUTPUT_DP_MST = 11,
185 };
186
187 #define INTEL_DVO_CHIP_NONE 0
188 #define INTEL_DVO_CHIP_LVDS 1
189 #define INTEL_DVO_CHIP_TMDS 2
190 #define INTEL_DVO_CHIP_TVOUT 4
191
192 #define INTEL_DSI_VIDEO_MODE    0
193 #define INTEL_DSI_COMMAND_MODE  1
194
195 struct intel_framebuffer {
196         struct drm_framebuffer base;
197         struct intel_rotation_info rot_info;
198
199         /* for each plane in the normal GTT view */
200         struct {
201                 unsigned int x, y;
202         } normal[2];
203         /* for each plane in the rotated GTT view */
204         struct {
205                 unsigned int x, y;
206                 unsigned int pitch; /* pixels */
207         } rotated[2];
208 };
209
210 struct intel_fbdev {
211         struct drm_fb_helper helper;
212         struct intel_framebuffer *fb;
213         struct i915_vma *vma;
214         unsigned long vma_flags;
215         async_cookie_t cookie;
216         int preferred_bpp;
217
218         /* Whether or not fbdev hpd processing is temporarily suspended */
219         bool hpd_suspended : 1;
220         /* Set when a hotplug was received while HPD processing was
221          * suspended
222          */
223         bool hpd_waiting : 1;
224
225         /* Protects hpd_suspended */
226         struct mutex hpd_lock;
227 };
228
229 struct intel_encoder {
230         struct drm_encoder base;
231
232         enum intel_output_type type;
233         enum port port;
234         unsigned int cloneable;
235         bool (*hotplug)(struct intel_encoder *encoder,
236                         struct intel_connector *connector);
237         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
238                                                       struct intel_crtc_state *,
239                                                       struct drm_connector_state *);
240         int (*compute_config)(struct intel_encoder *,
241                               struct intel_crtc_state *,
242                               struct drm_connector_state *);
243         void (*pre_pll_enable)(struct intel_encoder *,
244                                const struct intel_crtc_state *,
245                                const struct drm_connector_state *);
246         void (*pre_enable)(struct intel_encoder *,
247                            const struct intel_crtc_state *,
248                            const struct drm_connector_state *);
249         void (*enable)(struct intel_encoder *,
250                        const struct intel_crtc_state *,
251                        const struct drm_connector_state *);
252         void (*disable)(struct intel_encoder *,
253                         const struct intel_crtc_state *,
254                         const struct drm_connector_state *);
255         void (*post_disable)(struct intel_encoder *,
256                              const struct intel_crtc_state *,
257                              const struct drm_connector_state *);
258         void (*post_pll_disable)(struct intel_encoder *,
259                                  const struct intel_crtc_state *,
260                                  const struct drm_connector_state *);
261         void (*update_pipe)(struct intel_encoder *,
262                             const struct intel_crtc_state *,
263                             const struct drm_connector_state *);
264         /* Read out the current hw state of this connector, returning true if
265          * the encoder is active. If the encoder is enabled it also set the pipe
266          * it is connected to in the pipe parameter. */
267         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
268         /* Reconstructs the equivalent mode flags for the current hardware
269          * state. This must be called _after_ display->get_pipe_config has
270          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
271          * be set correctly before calling this function. */
272         void (*get_config)(struct intel_encoder *,
273                            struct intel_crtc_state *pipe_config);
274         /* Returns a mask of power domains that need to be referenced as part
275          * of the hardware state readout code. */
276         u64 (*get_power_domains)(struct intel_encoder *encoder,
277                                  struct intel_crtc_state *crtc_state);
278         /*
279          * Called during system suspend after all pending requests for the
280          * encoder are flushed (for example for DP AUX transactions) and
281          * device interrupts are disabled.
282          */
283         void (*suspend)(struct intel_encoder *);
284         int crtc_mask;
285         enum hpd_pin hpd_pin;
286         enum intel_display_power_domain power_domain;
287         /* for communication with audio component; protected by av_mutex */
288         const struct drm_connector *audio_connector;
289 };
290
291 struct intel_panel {
292         struct drm_display_mode *fixed_mode;
293         struct drm_display_mode *downclock_mode;
294
295         /* backlight */
296         struct {
297                 bool present;
298                 u32 level;
299                 u32 min;
300                 u32 max;
301                 bool enabled;
302                 bool combination_mode;  /* gen 2/4 only */
303                 bool active_low_pwm;
304                 bool alternate_pwm_increment;   /* lpt+ */
305
306                 /* PWM chip */
307                 bool util_pin_active_low;       /* bxt+ */
308                 u8 controller;          /* bxt+ only */
309                 struct pwm_device *pwm;
310
311                 struct backlight_device *device;
312
313                 /* Connector and platform specific backlight functions */
314                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
315                 u32 (*get)(struct intel_connector *connector);
316                 void (*set)(const struct drm_connector_state *conn_state, u32 level);
317                 void (*disable)(const struct drm_connector_state *conn_state);
318                 void (*enable)(const struct intel_crtc_state *crtc_state,
319                                const struct drm_connector_state *conn_state);
320                 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
321                 void (*power)(struct intel_connector *, bool enable);
322         } backlight;
323 };
324
325 struct intel_digital_port;
326
327 enum check_link_response {
328         HDCP_LINK_PROTECTED     = 0,
329         HDCP_TOPOLOGY_CHANGE,
330         HDCP_LINK_INTEGRITY_FAILURE,
331         HDCP_REAUTH_REQUEST
332 };
333
334 /*
335  * This structure serves as a translation layer between the generic HDCP code
336  * and the bus-specific code. What that means is that HDCP over HDMI differs
337  * from HDCP over DP, so to account for these differences, we need to
338  * communicate with the receiver through this shim.
339  *
340  * For completeness, the 2 buses differ in the following ways:
341  *      - DP AUX vs. DDC
342  *              HDCP registers on the receiver are set via DP AUX for DP, and
343  *              they are set via DDC for HDMI.
344  *      - Receiver register offsets
345  *              The offsets of the registers are different for DP vs. HDMI
346  *      - Receiver register masks/offsets
347  *              For instance, the ready bit for the KSV fifo is in a different
348  *              place on DP vs HDMI
349  *      - Receiver register names
350  *              Seriously. In the DP spec, the 16-bit register containing
351  *              downstream information is called BINFO, on HDMI it's called
352  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
353  *              with a completely different definition.
354  *      - KSV FIFO
355  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
356  *              be read 3 keys at a time
357  *      - Aksv output
358  *              Since Aksv is hidden in hardware, there's different procedures
359  *              to send it over DP AUX vs DDC
360  */
361 struct intel_hdcp_shim {
362         /* Outputs the transmitter's An and Aksv values to the receiver. */
363         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
364
365         /* Reads the receiver's key selection vector */
366         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
367
368         /*
369          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
370          * definitions are the same in the respective specs, but the names are
371          * different. Call it BSTATUS since that's the name the HDMI spec
372          * uses and it was there first.
373          */
374         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
375                             u8 *bstatus);
376
377         /* Determines whether a repeater is present downstream */
378         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
379                                 bool *repeater_present);
380
381         /* Reads the receiver's Ri' value */
382         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
383
384         /* Determines if the receiver's KSV FIFO is ready for consumption */
385         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
386                               bool *ksv_ready);
387
388         /* Reads the ksv fifo for num_downstream devices */
389         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
390                              int num_downstream, u8 *ksv_fifo);
391
392         /* Reads a 32-bit part of V' from the receiver */
393         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
394                                  int i, u32 *part);
395
396         /* Enables HDCP signalling on the port */
397         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
398                                  bool enable);
399
400         /* Ensures the link is still protected */
401         bool (*check_link)(struct intel_digital_port *intel_dig_port);
402
403         /* Detects panel's hdcp capability. This is optional for HDMI. */
404         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
405                             bool *hdcp_capable);
406
407         /* HDCP adaptation(DP/HDMI) required on the port */
408         enum hdcp_wired_protocol protocol;
409
410         /* Detects whether sink is HDCP2.2 capable */
411         int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
412                                 bool *capable);
413
414         /* Write HDCP2.2 messages */
415         int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
416                              void *buf, size_t size);
417
418         /* Read HDCP2.2 messages */
419         int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
420                             u8 msg_id, void *buf, size_t size);
421
422         /*
423          * Implementation of DP HDCP2.2 Errata for the communication of stream
424          * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
425          * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
426          */
427         int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
428                                   bool is_repeater, u8 type);
429
430         /* HDCP2.2 Link Integrity Check */
431         int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
432 };
433
434 struct intel_hdcp {
435         const struct intel_hdcp_shim *shim;
436         /* Mutex for hdcp state of the connector */
437         struct mutex mutex;
438         u64 value;
439         struct delayed_work check_work;
440         struct work_struct prop_work;
441
442         /* HDCP1.4 Encryption status */
443         bool hdcp_encrypted;
444
445         /* HDCP2.2 related definitions */
446         /* Flag indicates whether this connector supports HDCP2.2 or not. */
447         bool hdcp2_supported;
448
449         /* HDCP2.2 Encryption status */
450         bool hdcp2_encrypted;
451
452         /*
453          * Content Stream Type defined by content owner. TYPE0(0x0) content can
454          * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
455          * content can flow only through a link protected by HDCP2.2.
456          */
457         u8 content_type;
458         struct hdcp_port_data port_data;
459
460         bool is_paired;
461         bool is_repeater;
462
463         /*
464          * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
465          * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
466          * When it rolls over re-auth has to be triggered.
467          */
468         u32 seq_num_v;
469
470         /*
471          * Count of RepeaterAuth_Stream_Manage msg propagated.
472          * Initialized to 0 on AKE_INIT. Incremented after every successful
473          * transmission of RepeaterAuth_Stream_Manage message. When it rolls
474          * over re-Auth has to be triggered.
475          */
476         u32 seq_num_m;
477
478         /*
479          * Work queue to signal the CP_IRQ. Used for the waiters to read the
480          * available information from HDCP DP sink.
481          */
482         wait_queue_head_t cp_irq_queue;
483         atomic_t cp_irq_count;
484         int cp_irq_count_cached;
485 };
486
487 struct intel_connector {
488         struct drm_connector base;
489         /*
490          * The fixed encoder this connector is connected to.
491          */
492         struct intel_encoder *encoder;
493
494         /* ACPI device id for ACPI and driver cooperation */
495         u32 acpi_device_id;
496
497         /* Reads out the current hw, returning true if the connector is enabled
498          * and active (i.e. dpms ON state). */
499         bool (*get_hw_state)(struct intel_connector *);
500
501         /* Panel info for eDP and LVDS */
502         struct intel_panel panel;
503
504         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
505         struct edid *edid;
506         struct edid *detect_edid;
507
508         /* since POLL and HPD connectors may use the same HPD line keep the native
509            state of connector->polled in case hotplug storm detection changes it */
510         u8 polled;
511
512         void *port; /* store this opaque as its illegal to dereference it */
513
514         struct intel_dp *mst_port;
515
516         /* Work struct to schedule a uevent on link train failure */
517         struct work_struct modeset_retry_work;
518
519         struct intel_hdcp hdcp;
520 };
521
522 struct intel_digital_connector_state {
523         struct drm_connector_state base;
524
525         enum hdmi_force_audio force_audio;
526         int broadcast_rgb;
527 };
528
529 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
530
531 struct dpll {
532         /* given values */
533         int n;
534         int m1, m2;
535         int p1, p2;
536         /* derived values */
537         int     dot;
538         int     vco;
539         int     m;
540         int     p;
541 };
542
543 struct intel_atomic_state {
544         struct drm_atomic_state base;
545
546         struct {
547                 /*
548                  * Logical state of cdclk (used for all scaling, watermark,
549                  * etc. calculations and checks). This is computed as if all
550                  * enabled crtcs were active.
551                  */
552                 struct intel_cdclk_state logical;
553
554                 /*
555                  * Actual state of cdclk, can be different from the logical
556                  * state only when all crtc's are DPMS off.
557                  */
558                 struct intel_cdclk_state actual;
559         } cdclk;
560
561         bool dpll_set, modeset;
562
563         /*
564          * Does this transaction change the pipes that are active?  This mask
565          * tracks which CRTC's have changed their active state at the end of
566          * the transaction (not counting the temporary disable during modesets).
567          * This mask should only be non-zero when intel_state->modeset is true,
568          * but the converse is not necessarily true; simply changing a mode may
569          * not flip the final active status of any CRTC's
570          */
571         unsigned int active_pipe_changes;
572
573         unsigned int active_crtcs;
574         /* minimum acceptable cdclk for each pipe */
575         int min_cdclk[I915_MAX_PIPES];
576         /* minimum acceptable voltage level for each pipe */
577         u8 min_voltage_level[I915_MAX_PIPES];
578
579         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
580
581         /*
582          * Current watermarks can't be trusted during hardware readout, so
583          * don't bother calculating intermediate watermarks.
584          */
585         bool skip_intermediate_wm;
586
587         bool rps_interactive;
588
589         /* Gen9+ only */
590         struct skl_ddb_values wm_results;
591
592         struct i915_sw_fence commit_ready;
593
594         struct llist_node freed;
595 };
596
597 struct intel_plane_state {
598         struct drm_plane_state base;
599         struct i915_ggtt_view view;
600         struct i915_vma *vma;
601         unsigned long flags;
602 #define PLANE_HAS_FENCE BIT(0)
603
604         struct {
605                 u32 offset;
606                 /*
607                  * Plane stride in:
608                  * bytes for 0/180 degree rotation
609                  * pixels for 90/270 degree rotation
610                  */
611                 u32 stride;
612                 int x, y;
613         } color_plane[2];
614
615         /* plane control register */
616         u32 ctl;
617
618         /* plane color control register */
619         u32 color_ctl;
620
621         /*
622          * scaler_id
623          *    = -1 : not using a scaler
624          *    >=  0 : using a scalers
625          *
626          * plane requiring a scaler:
627          *   - During check_plane, its bit is set in
628          *     crtc_state->scaler_state.scaler_users by calling helper function
629          *     update_scaler_plane.
630          *   - scaler_id indicates the scaler it got assigned.
631          *
632          * plane doesn't require a scaler:
633          *   - this can happen when scaling is no more required or plane simply
634          *     got disabled.
635          *   - During check_plane, corresponding bit is reset in
636          *     crtc_state->scaler_state.scaler_users by calling helper function
637          *     update_scaler_plane.
638          */
639         int scaler_id;
640
641         /*
642          * linked_plane:
643          *
644          * ICL planar formats require 2 planes that are updated as pairs.
645          * This member is used to make sure the other plane is also updated
646          * when required, and for update_slave() to find the correct
647          * plane_state to pass as argument.
648          */
649         struct intel_plane *linked_plane;
650
651         /*
652          * slave:
653          * If set don't update use the linked plane's state for updating
654          * this plane during atomic commit with the update_slave() callback.
655          *
656          * It's also used by the watermark code to ignore wm calculations on
657          * this plane. They're calculated by the linked plane's wm code.
658          */
659         u32 slave;
660
661         struct drm_intel_sprite_colorkey ckey;
662 };
663
664 struct intel_initial_plane_config {
665         struct intel_framebuffer *fb;
666         unsigned int tiling;
667         int size;
668         u32 base;
669         u8 rotation;
670 };
671
672 #define SKL_MIN_SRC_W 8
673 #define SKL_MAX_SRC_W 4096
674 #define SKL_MIN_SRC_H 8
675 #define SKL_MAX_SRC_H 4096
676 #define SKL_MIN_DST_W 8
677 #define SKL_MAX_DST_W 4096
678 #define SKL_MIN_DST_H 8
679 #define SKL_MAX_DST_H 4096
680 #define ICL_MAX_SRC_W 5120
681 #define ICL_MAX_SRC_H 4096
682 #define ICL_MAX_DST_W 5120
683 #define ICL_MAX_DST_H 4096
684 #define SKL_MIN_YUV_420_SRC_W 16
685 #define SKL_MIN_YUV_420_SRC_H 16
686
687 struct intel_scaler {
688         int in_use;
689         u32 mode;
690 };
691
692 struct intel_crtc_scaler_state {
693 #define SKL_NUM_SCALERS 2
694         struct intel_scaler scalers[SKL_NUM_SCALERS];
695
696         /*
697          * scaler_users: keeps track of users requesting scalers on this crtc.
698          *
699          *     If a bit is set, a user is using a scaler.
700          *     Here user can be a plane or crtc as defined below:
701          *       bits 0-30 - plane (bit position is index from drm_plane_index)
702          *       bit 31    - crtc
703          *
704          * Instead of creating a new index to cover planes and crtc, using
705          * existing drm_plane_index for planes which is well less than 31
706          * planes and bit 31 for crtc. This should be fine to cover all
707          * our platforms.
708          *
709          * intel_atomic_setup_scalers will setup available scalers to users
710          * requesting scalers. It will gracefully fail if request exceeds
711          * avilability.
712          */
713 #define SKL_CRTC_INDEX 31
714         unsigned scaler_users;
715
716         /* scaler used by crtc for panel fitting purpose */
717         int scaler_id;
718 };
719
720 /* drm_mode->private_flags */
721 #define I915_MODE_FLAG_INHERITED (1<<0)
722 /* Flag to get scanline using frame time stamps */
723 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
724 /* Flag to use the scanline counter instead of the pixel counter */
725 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
726
727 struct intel_pipe_wm {
728         struct intel_wm_level wm[5];
729         u32 linetime;
730         bool fbc_wm_enabled;
731         bool pipe_enabled;
732         bool sprites_enabled;
733         bool sprites_scaled;
734 };
735
736 struct skl_plane_wm {
737         struct skl_wm_level wm[8];
738         struct skl_wm_level uv_wm[8];
739         struct skl_wm_level trans_wm;
740         bool is_planar;
741 };
742
743 struct skl_pipe_wm {
744         struct skl_plane_wm planes[I915_MAX_PLANES];
745         u32 linetime;
746 };
747
748 enum vlv_wm_level {
749         VLV_WM_LEVEL_PM2,
750         VLV_WM_LEVEL_PM5,
751         VLV_WM_LEVEL_DDR_DVFS,
752         NUM_VLV_WM_LEVELS,
753 };
754
755 struct vlv_wm_state {
756         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
757         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
758         u8 num_levels;
759         bool cxsr;
760 };
761
762 struct vlv_fifo_state {
763         u16 plane[I915_MAX_PLANES];
764 };
765
766 enum g4x_wm_level {
767         G4X_WM_LEVEL_NORMAL,
768         G4X_WM_LEVEL_SR,
769         G4X_WM_LEVEL_HPLL,
770         NUM_G4X_WM_LEVELS,
771 };
772
773 struct g4x_wm_state {
774         struct g4x_pipe_wm wm;
775         struct g4x_sr_wm sr;
776         struct g4x_sr_wm hpll;
777         bool cxsr;
778         bool hpll_en;
779         bool fbc_en;
780 };
781
782 struct intel_crtc_wm_state {
783         union {
784                 struct {
785                         /*
786                          * Intermediate watermarks; these can be
787                          * programmed immediately since they satisfy
788                          * both the current configuration we're
789                          * switching away from and the new
790                          * configuration we're switching to.
791                          */
792                         struct intel_pipe_wm intermediate;
793
794                         /*
795                          * Optimal watermarks, programmed post-vblank
796                          * when this state is committed.
797                          */
798                         struct intel_pipe_wm optimal;
799                 } ilk;
800
801                 struct {
802                         /* gen9+ only needs 1-step wm programming */
803                         struct skl_pipe_wm optimal;
804                         struct skl_ddb_entry ddb;
805                         struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
806                         struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
807                 } skl;
808
809                 struct {
810                         /* "raw" watermarks (not inverted) */
811                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
812                         /* intermediate watermarks (inverted) */
813                         struct vlv_wm_state intermediate;
814                         /* optimal watermarks (inverted) */
815                         struct vlv_wm_state optimal;
816                         /* display FIFO split */
817                         struct vlv_fifo_state fifo_state;
818                 } vlv;
819
820                 struct {
821                         /* "raw" watermarks */
822                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
823                         /* intermediate watermarks */
824                         struct g4x_wm_state intermediate;
825                         /* optimal watermarks */
826                         struct g4x_wm_state optimal;
827                 } g4x;
828         };
829
830         /*
831          * Platforms with two-step watermark programming will need to
832          * update watermark programming post-vblank to switch from the
833          * safe intermediate watermarks to the optimal final
834          * watermarks.
835          */
836         bool need_postvbl_update;
837 };
838
839 enum intel_output_format {
840         INTEL_OUTPUT_FORMAT_INVALID,
841         INTEL_OUTPUT_FORMAT_RGB,
842         INTEL_OUTPUT_FORMAT_YCBCR420,
843         INTEL_OUTPUT_FORMAT_YCBCR444,
844 };
845
846 struct intel_crtc_state {
847         struct drm_crtc_state base;
848
849         /**
850          * quirks - bitfield with hw state readout quirks
851          *
852          * For various reasons the hw state readout code might not be able to
853          * completely faithfully read out the current state. These cases are
854          * tracked with quirk flags so that fastboot and state checker can act
855          * accordingly.
856          */
857 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
858         unsigned long quirks;
859
860         unsigned fb_bits; /* framebuffers to flip */
861         bool update_pipe; /* can a fast modeset be performed? */
862         bool disable_cxsr;
863         bool update_wm_pre, update_wm_post; /* watermarks are updated */
864         bool fb_changed; /* fb on any of the planes is changed */
865         bool fifo_changed; /* FIFO split is changed */
866
867         /* Pipe source size (ie. panel fitter input size)
868          * All planes will be positioned inside this space,
869          * and get clipped at the edges. */
870         int pipe_src_w, pipe_src_h;
871
872         /*
873          * Pipe pixel rate, adjusted for
874          * panel fitter/pipe scaler downscaling.
875          */
876         unsigned int pixel_rate;
877
878         /* Whether to set up the PCH/FDI. Note that we never allow sharing
879          * between pch encoders and cpu encoders. */
880         bool has_pch_encoder;
881
882         /* Are we sending infoframes on the attached port */
883         bool has_infoframe;
884
885         /* CPU Transcoder for the pipe. Currently this can only differ from the
886          * pipe on Haswell and later (where we have a special eDP transcoder)
887          * and Broxton (where we have special DSI transcoders). */
888         enum transcoder cpu_transcoder;
889
890         /*
891          * Use reduced/limited/broadcast rbg range, compressing from the full
892          * range fed into the crtcs.
893          */
894         bool limited_color_range;
895
896         /* Bitmask of encoder types (enum intel_output_type)
897          * driven by the pipe.
898          */
899         unsigned int output_types;
900
901         /* Whether we should send NULL infoframes. Required for audio. */
902         bool has_hdmi_sink;
903
904         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
905          * has_dp_encoder is set. */
906         bool has_audio;
907
908         /*
909          * Enable dithering, used when the selected pipe bpp doesn't match the
910          * plane bpp.
911          */
912         bool dither;
913
914         /*
915          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
916          * compliance video pattern tests.
917          * Disable dither only if it is a compliance test request for
918          * 18bpp.
919          */
920         bool dither_force_disable;
921
922         /* Controls for the clock computation, to override various stages. */
923         bool clock_set;
924
925         /* SDVO TV has a bunch of special case. To make multifunction encoders
926          * work correctly, we need to track this at runtime.*/
927         bool sdvo_tv_clock;
928
929         /*
930          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
931          * required. This is set in the 2nd loop of calling encoder's
932          * ->compute_config if the first pick doesn't work out.
933          */
934         bool bw_constrained;
935
936         /* Settings for the intel dpll used on pretty much everything but
937          * haswell. */
938         struct dpll dpll;
939
940         /* Selected dpll when shared or NULL. */
941         struct intel_shared_dpll *shared_dpll;
942
943         /* Actual register state of the dpll, for shared dpll cross-checking. */
944         struct intel_dpll_hw_state dpll_hw_state;
945
946         /* DSI PLL registers */
947         struct {
948                 u32 ctrl, div;
949         } dsi_pll;
950
951         int pipe_bpp;
952         struct intel_link_m_n dp_m_n;
953
954         /* m2_n2 for eDP downclock */
955         struct intel_link_m_n dp_m2_n2;
956         bool has_drrs;
957
958         bool has_psr;
959         bool has_psr2;
960
961         /*
962          * Frequence the dpll for the port should run at. Differs from the
963          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
964          * already multiplied by pixel_multiplier.
965          */
966         int port_clock;
967
968         /* Used by SDVO (and if we ever fix it, HDMI). */
969         unsigned pixel_multiplier;
970
971         u8 lane_count;
972
973         /*
974          * Used by platforms having DP/HDMI PHY with programmable lane
975          * latency optimization.
976          */
977         u8 lane_lat_optim_mask;
978
979         /* minimum acceptable voltage level */
980         u8 min_voltage_level;
981
982         /* Panel fitter controls for gen2-gen4 + VLV */
983         struct {
984                 u32 control;
985                 u32 pgm_ratios;
986                 u32 lvds_border_bits;
987         } gmch_pfit;
988
989         /* Panel fitter placement and size for Ironlake+ */
990         struct {
991                 u32 pos;
992                 u32 size;
993                 bool enabled;
994                 bool force_thru;
995         } pch_pfit;
996
997         /* FDI configuration, only valid if has_pch_encoder is set. */
998         int fdi_lanes;
999         struct intel_link_m_n fdi_m_n;
1000
1001         bool ips_enabled;
1002
1003         bool crc_enabled;
1004
1005         bool enable_fbc;
1006
1007         bool double_wide;
1008
1009         int pbn;
1010
1011         struct intel_crtc_scaler_state scaler_state;
1012
1013         /* w/a for waiting 2 vblanks during crtc enable */
1014         enum pipe hsw_workaround_pipe;
1015
1016         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1017         bool disable_lp_wm;
1018
1019         struct intel_crtc_wm_state wm;
1020
1021         /* Gamma mode programmed on the pipe */
1022         u32 gamma_mode;
1023
1024         union {
1025                 /* CSC mode programmed on the pipe */
1026                 u32 csc_mode;
1027
1028                 /* CHV CGM mode */
1029                 u32 cgm_mode;
1030         };
1031
1032         /* bitmask of visible planes (enum plane_id) */
1033         u8 active_planes;
1034         u8 nv12_planes;
1035         u8 c8_planes;
1036
1037         /* bitmask of planes that will be updated during the commit */
1038         u8 update_planes;
1039
1040         struct {
1041                 u32 enable;
1042                 u32 gcp;
1043                 union hdmi_infoframe avi;
1044                 union hdmi_infoframe spd;
1045                 union hdmi_infoframe hdmi;
1046         } infoframes;
1047
1048         /* HDMI scrambling status */
1049         bool hdmi_scrambling;
1050
1051         /* HDMI High TMDS char rate ratio */
1052         bool hdmi_high_tmds_clock_ratio;
1053
1054         /* Output format RGB/YCBCR etc */
1055         enum intel_output_format output_format;
1056
1057         /* Output down scaling is done in LSPCON device */
1058         bool lspcon_downsampling;
1059
1060         /* enable pipe gamma? */
1061         bool gamma_enable;
1062
1063         /* enable pipe csc? */
1064         bool csc_enable;
1065
1066         /* Display Stream compression state */
1067         struct {
1068                 bool compression_enable;
1069                 bool dsc_split;
1070                 u16 compressed_bpp;
1071                 u8 slice_count;
1072         } dsc_params;
1073         struct drm_dsc_config dp_dsc_cfg;
1074
1075         /* Forward Error correction State */
1076         bool fec_enable;
1077 };
1078
1079 struct intel_crtc {
1080         struct drm_crtc base;
1081         enum pipe pipe;
1082         /*
1083          * Whether the crtc and the connected output pipeline is active. Implies
1084          * that crtc->enabled is set, i.e. the current mode configuration has
1085          * some outputs connected to this crtc.
1086          */
1087         bool active;
1088         u8 plane_ids_mask;
1089         unsigned long long enabled_power_domains;
1090         struct intel_overlay *overlay;
1091
1092         struct intel_crtc_state *config;
1093
1094         /* Access to these should be protected by dev_priv->irq_lock. */
1095         bool cpu_fifo_underrun_disabled;
1096         bool pch_fifo_underrun_disabled;
1097
1098         /* per-pipe watermark state */
1099         struct {
1100                 /* watermarks currently being used  */
1101                 union {
1102                         struct intel_pipe_wm ilk;
1103                         struct vlv_wm_state vlv;
1104                         struct g4x_wm_state g4x;
1105                 } active;
1106         } wm;
1107
1108         int scanline_offset;
1109
1110         struct {
1111                 unsigned start_vbl_count;
1112                 ktime_t start_vbl_time;
1113                 int min_vbl, max_vbl;
1114                 int scanline_start;
1115         } debug;
1116
1117         /* scalers available on this crtc */
1118         int num_scalers;
1119 };
1120
1121 struct intel_plane {
1122         struct drm_plane base;
1123         enum i9xx_plane_id i9xx_plane;
1124         enum plane_id id;
1125         enum pipe pipe;
1126         bool has_fbc;
1127         bool has_ccs;
1128         u32 frontbuffer_bit;
1129
1130         struct {
1131                 u32 base, cntl, size;
1132         } cursor;
1133
1134         /*
1135          * NOTE: Do not place new plane state fields here (e.g., when adding
1136          * new plane properties).  New runtime state should now be placed in
1137          * the intel_plane_state structure and accessed via plane_state.
1138          */
1139
1140         unsigned int (*max_stride)(struct intel_plane *plane,
1141                                    u32 pixel_format, u64 modifier,
1142                                    unsigned int rotation);
1143         void (*update_plane)(struct intel_plane *plane,
1144                              const struct intel_crtc_state *crtc_state,
1145                              const struct intel_plane_state *plane_state);
1146         void (*update_slave)(struct intel_plane *plane,
1147                              const struct intel_crtc_state *crtc_state,
1148                              const struct intel_plane_state *plane_state);
1149         void (*disable_plane)(struct intel_plane *plane,
1150                               const struct intel_crtc_state *crtc_state);
1151         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1152         int (*check_plane)(struct intel_crtc_state *crtc_state,
1153                            struct intel_plane_state *plane_state);
1154 };
1155
1156 struct intel_watermark_params {
1157         u16 fifo_size;
1158         u16 max_wm;
1159         u8 default_wm;
1160         u8 guard_size;
1161         u8 cacheline_size;
1162 };
1163
1164 struct cxsr_latency {
1165         bool is_desktop : 1;
1166         bool is_ddr3 : 1;
1167         u16 fsb_freq;
1168         u16 mem_freq;
1169         u16 display_sr;
1170         u16 display_hpll_disable;
1171         u16 cursor_sr;
1172         u16 cursor_hpll_disable;
1173 };
1174
1175 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1176 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1177 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1178 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1179 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1180 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1181 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1182 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1183 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1184
1185 struct intel_hdmi {
1186         i915_reg_t hdmi_reg;
1187         int ddc_bus;
1188         struct {
1189                 enum drm_dp_dual_mode_type type;
1190                 int max_tmds_clock;
1191         } dp_dual_mode;
1192         bool has_hdmi_sink;
1193         bool has_audio;
1194         struct intel_connector *attached_connector;
1195         struct cec_notifier *cec_notifier;
1196 };
1197
1198 struct intel_dp_mst_encoder;
1199 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1200
1201 /*
1202  * enum link_m_n_set:
1203  *      When platform provides two set of M_N registers for dp, we can
1204  *      program them and switch between them incase of DRRS.
1205  *      But When only one such register is provided, we have to program the
1206  *      required divider value on that registers itself based on the DRRS state.
1207  *
1208  * M1_N1        : Program dp_m_n on M1_N1 registers
1209  *                        dp_m2_n2 on M2_N2 registers (If supported)
1210  *
1211  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1212  *                        M2_N2 registers are not supported
1213  */
1214
1215 enum link_m_n_set {
1216         /* Sets the m1_n1 and m2_n2 */
1217         M1_N1 = 0,
1218         M2_N2
1219 };
1220
1221 struct intel_dp_compliance_data {
1222         unsigned long edid;
1223         u8 video_pattern;
1224         u16 hdisplay, vdisplay;
1225         u8 bpc;
1226 };
1227
1228 struct intel_dp_compliance {
1229         unsigned long test_type;
1230         struct intel_dp_compliance_data test_data;
1231         bool test_active;
1232         int test_link_rate;
1233         u8 test_lane_count;
1234 };
1235
1236 struct intel_dp {
1237         i915_reg_t output_reg;
1238         u32 DP;
1239         int link_rate;
1240         u8 lane_count;
1241         u8 sink_count;
1242         bool link_mst;
1243         bool link_trained;
1244         bool has_audio;
1245         bool reset_link_params;
1246         u8 dpcd[DP_RECEIVER_CAP_SIZE];
1247         u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1248         u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1249         u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1250         u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1251         u8 fec_capable;
1252         /* source rates */
1253         int num_source_rates;
1254         const int *source_rates;
1255         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1256         int num_sink_rates;
1257         int sink_rates[DP_MAX_SUPPORTED_RATES];
1258         bool use_rate_select;
1259         /* intersection of source and sink rates */
1260         int num_common_rates;
1261         int common_rates[DP_MAX_SUPPORTED_RATES];
1262         /* Max lane count for the current link */
1263         int max_link_lane_count;
1264         /* Max rate for the current link */
1265         int max_link_rate;
1266         /* sink or branch descriptor */
1267         struct drm_dp_desc desc;
1268         struct drm_dp_aux aux;
1269         u8 train_set[4];
1270         int panel_power_up_delay;
1271         int panel_power_down_delay;
1272         int panel_power_cycle_delay;
1273         int backlight_on_delay;
1274         int backlight_off_delay;
1275         struct delayed_work panel_vdd_work;
1276         bool want_panel_vdd;
1277         unsigned long last_power_on;
1278         unsigned long last_backlight_off;
1279         ktime_t panel_power_off_time;
1280
1281         struct notifier_block edp_notifier;
1282
1283         /*
1284          * Pipe whose power sequencer is currently locked into
1285          * this port. Only relevant on VLV/CHV.
1286          */
1287         enum pipe pps_pipe;
1288         /*
1289          * Pipe currently driving the port. Used for preventing
1290          * the use of the PPS for any pipe currentrly driving
1291          * external DP as that will mess things up on VLV.
1292          */
1293         enum pipe active_pipe;
1294         /*
1295          * Set if the sequencer may be reset due to a power transition,
1296          * requiring a reinitialization. Only relevant on BXT.
1297          */
1298         bool pps_reset;
1299         struct edp_power_seq pps_delays;
1300
1301         bool can_mst; /* this port supports mst */
1302         bool is_mst;
1303         int active_mst_links;
1304         /* connector directly attached - won't be use for modeset in mst world */
1305         struct intel_connector *attached_connector;
1306
1307         /* mst connector list */
1308         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1309         struct drm_dp_mst_topology_mgr mst_mgr;
1310
1311         u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1312         /*
1313          * This function returns the value we have to program the AUX_CTL
1314          * register with to kick off an AUX transaction.
1315          */
1316         u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1317                                 u32 aux_clock_divider);
1318
1319         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1320         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1321
1322         /* This is called before a link training is starterd */
1323         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1324
1325         /* Displayport compliance testing */
1326         struct intel_dp_compliance compliance;
1327
1328         /* Display stream compression testing */
1329         bool force_dsc_en;
1330 };
1331
1332 enum lspcon_vendor {
1333         LSPCON_VENDOR_MCA,
1334         LSPCON_VENDOR_PARADE
1335 };
1336
1337 struct intel_lspcon {
1338         bool active;
1339         enum drm_lspcon_mode mode;
1340         enum lspcon_vendor vendor;
1341 };
1342
1343 struct intel_digital_port {
1344         struct intel_encoder base;
1345         u32 saved_port_bits;
1346         struct intel_dp dp;
1347         struct intel_hdmi hdmi;
1348         struct intel_lspcon lspcon;
1349         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1350         bool release_cl2_override;
1351         u8 max_lanes;
1352         /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1353         enum aux_ch aux_ch;
1354         enum intel_display_power_domain ddi_io_power_domain;
1355         bool tc_legacy_port:1;
1356         enum tc_port_type tc_type;
1357
1358         void (*write_infoframe)(struct intel_encoder *encoder,
1359                                 const struct intel_crtc_state *crtc_state,
1360                                 unsigned int type,
1361                                 const void *frame, ssize_t len);
1362         void (*read_infoframe)(struct intel_encoder *encoder,
1363                                const struct intel_crtc_state *crtc_state,
1364                                unsigned int type,
1365                                void *frame, ssize_t len);
1366         void (*set_infoframes)(struct intel_encoder *encoder,
1367                                bool enable,
1368                                const struct intel_crtc_state *crtc_state,
1369                                const struct drm_connector_state *conn_state);
1370         u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1371                                   const struct intel_crtc_state *pipe_config);
1372 };
1373
1374 struct intel_dp_mst_encoder {
1375         struct intel_encoder base;
1376         enum pipe pipe;
1377         struct intel_digital_port *primary;
1378         struct intel_connector *connector;
1379 };
1380
1381 static inline enum dpio_channel
1382 vlv_dport_to_channel(struct intel_digital_port *dport)
1383 {
1384         switch (dport->base.port) {
1385         case PORT_B:
1386         case PORT_D:
1387                 return DPIO_CH0;
1388         case PORT_C:
1389                 return DPIO_CH1;
1390         default:
1391                 BUG();
1392         }
1393 }
1394
1395 static inline enum dpio_phy
1396 vlv_dport_to_phy(struct intel_digital_port *dport)
1397 {
1398         switch (dport->base.port) {
1399         case PORT_B:
1400         case PORT_C:
1401                 return DPIO_PHY0;
1402         case PORT_D:
1403                 return DPIO_PHY1;
1404         default:
1405                 BUG();
1406         }
1407 }
1408
1409 static inline enum dpio_channel
1410 vlv_pipe_to_channel(enum pipe pipe)
1411 {
1412         switch (pipe) {
1413         case PIPE_A:
1414         case PIPE_C:
1415                 return DPIO_CH0;
1416         case PIPE_B:
1417                 return DPIO_CH1;
1418         default:
1419                 BUG();
1420         }
1421 }
1422
1423 static inline struct intel_crtc *
1424 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1425 {
1426         return dev_priv->pipe_to_crtc_mapping[pipe];
1427 }
1428
1429 static inline struct intel_crtc *
1430 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1431 {
1432         return dev_priv->plane_to_crtc_mapping[plane];
1433 }
1434
1435 struct intel_load_detect_pipe {
1436         struct drm_atomic_state *restore_state;
1437 };
1438
1439 static inline struct intel_encoder *
1440 intel_attached_encoder(struct drm_connector *connector)
1441 {
1442         return to_intel_connector(connector)->encoder;
1443 }
1444
1445 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1446 {
1447         switch (encoder->type) {
1448         case INTEL_OUTPUT_DDI:
1449         case INTEL_OUTPUT_DP:
1450         case INTEL_OUTPUT_EDP:
1451         case INTEL_OUTPUT_HDMI:
1452                 return true;
1453         default:
1454                 return false;
1455         }
1456 }
1457
1458 static inline struct intel_digital_port *
1459 enc_to_dig_port(struct drm_encoder *encoder)
1460 {
1461         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1462
1463         if (intel_encoder_is_dig_port(intel_encoder))
1464                 return container_of(encoder, struct intel_digital_port,
1465                                     base.base);
1466         else
1467                 return NULL;
1468 }
1469
1470 static inline struct intel_digital_port *
1471 conn_to_dig_port(struct intel_connector *connector)
1472 {
1473         return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1474 }
1475
1476 static inline struct intel_dp_mst_encoder *
1477 enc_to_mst(struct drm_encoder *encoder)
1478 {
1479         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1480 }
1481
1482 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1483 {
1484         return &enc_to_dig_port(encoder)->dp;
1485 }
1486
1487 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1488 {
1489         switch (encoder->type) {
1490         case INTEL_OUTPUT_DP:
1491         case INTEL_OUTPUT_EDP:
1492                 return true;
1493         case INTEL_OUTPUT_DDI:
1494                 /* Skip pure HDMI/DVI DDI encoders */
1495                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1496         default:
1497                 return false;
1498         }
1499 }
1500
1501 static inline struct intel_lspcon *
1502 enc_to_intel_lspcon(struct drm_encoder *encoder)
1503 {
1504         return &enc_to_dig_port(encoder)->lspcon;
1505 }
1506
1507 static inline struct intel_digital_port *
1508 dp_to_dig_port(struct intel_dp *intel_dp)
1509 {
1510         return container_of(intel_dp, struct intel_digital_port, dp);
1511 }
1512
1513 static inline struct intel_lspcon *
1514 dp_to_lspcon(struct intel_dp *intel_dp)
1515 {
1516         return &dp_to_dig_port(intel_dp)->lspcon;
1517 }
1518
1519 static inline struct drm_i915_private *
1520 dp_to_i915(struct intel_dp *intel_dp)
1521 {
1522         return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1523 }
1524
1525 static inline struct intel_digital_port *
1526 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1527 {
1528         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1529 }
1530
1531 static inline struct intel_plane_state *
1532 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1533                                  struct intel_plane *plane)
1534 {
1535         struct drm_plane_state *ret =
1536                 drm_atomic_get_plane_state(&state->base, &plane->base);
1537
1538         if (IS_ERR(ret))
1539                 return ERR_CAST(ret);
1540
1541         return to_intel_plane_state(ret);
1542 }
1543
1544 static inline struct intel_plane_state *
1545 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1546                                  struct intel_plane *plane)
1547 {
1548         return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1549                                                                    &plane->base));
1550 }
1551
1552 static inline struct intel_plane_state *
1553 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1554                                  struct intel_plane *plane)
1555 {
1556         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1557                                                                    &plane->base));
1558 }
1559
1560 static inline struct intel_crtc_state *
1561 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1562                                 struct intel_crtc *crtc)
1563 {
1564         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1565                                                                  &crtc->base));
1566 }
1567
1568 static inline struct intel_crtc_state *
1569 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1570                                 struct intel_crtc *crtc)
1571 {
1572         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1573                                                                  &crtc->base));
1574 }
1575
1576 /* intel_fifo_underrun.c */
1577 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1578                                            enum pipe pipe, bool enable);
1579 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1580                                            enum pipe pch_transcoder,
1581                                            bool enable);
1582 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1583                                          enum pipe pipe);
1584 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1585                                          enum pipe pch_transcoder);
1586 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1587 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1588
1589 /* i915_irq.c */
1590 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1591 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1592 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1593 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1594 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1595 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1596 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1597 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1598
1599 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1600                                             u32 mask)
1601 {
1602         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1603 }
1604
1605 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1606 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1607 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1608 {
1609         /*
1610          * We only use drm_irq_uninstall() at unload and VT switch, so
1611          * this is the only thing we need to check.
1612          */
1613         return dev_priv->runtime_pm.irqs_enabled;
1614 }
1615
1616 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1617 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1618                                      u8 pipe_mask);
1619 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1620                                      u8 pipe_mask);
1621 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1622 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1623 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1624
1625 /* intel_crt.c */
1626 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1627                             i915_reg_t adpa_reg, enum pipe *pipe);
1628 void intel_crt_init(struct drm_i915_private *dev_priv);
1629 void intel_crt_reset(struct drm_encoder *encoder);
1630
1631 /* intel_ddi.c */
1632 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1633                                 const struct intel_crtc_state *old_crtc_state,
1634                                 const struct drm_connector_state *old_conn_state);
1635 void hsw_fdi_link_train(struct intel_crtc *crtc,
1636                         const struct intel_crtc_state *crtc_state);
1637 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1638 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1639 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1640 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1641 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1642 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1643 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1644 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1645 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1646 void intel_ddi_get_config(struct intel_encoder *encoder,
1647                           struct intel_crtc_state *pipe_config);
1648
1649 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1650                                     bool state);
1651 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1652                                          struct intel_crtc_state *crtc_state);
1653 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1654 u32 ddi_signal_levels(struct intel_dp *intel_dp);
1655 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1656 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1657                                  u8 voltage_swing);
1658 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1659                                      bool enable);
1660 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
1661 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1662                         enum intel_dpll_id pll_id);
1663
1664 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1665                                    int color_plane, unsigned int height);
1666
1667 /* intel_audio.c */
1668 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1669 void intel_audio_codec_enable(struct intel_encoder *encoder,
1670                               const struct intel_crtc_state *crtc_state,
1671                               const struct drm_connector_state *conn_state);
1672 void intel_audio_codec_disable(struct intel_encoder *encoder,
1673                                const struct intel_crtc_state *old_crtc_state,
1674                                const struct drm_connector_state *old_conn_state);
1675 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1676 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1677 void intel_audio_init(struct drm_i915_private *dev_priv);
1678 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1679
1680 /* intel_cdclk.c */
1681 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1682 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1683 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1684 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1685 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1686 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1687 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1688 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1689 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1690 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1691 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1692 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1693 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1694 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1695                                const struct intel_cdclk_state *b);
1696 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1697                          const struct intel_cdclk_state *b);
1698 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1699                      const struct intel_cdclk_state *cdclk_state);
1700 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1701                             const char *context);
1702
1703 /* intel_display.c */
1704 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1705 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1706 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1707 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1708 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1709                       const char *name, u32 reg, int ref_freq);
1710 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1711                            const char *name, u32 reg);
1712 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1713 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1714 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1715 unsigned int intel_fb_xy_to_linear(int x, int y,
1716                                    const struct intel_plane_state *state,
1717                                    int plane);
1718 void intel_add_fb_offsets(int *x, int *y,
1719                           const struct intel_plane_state *state, int plane);
1720 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1721 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1722 void intel_mark_busy(struct drm_i915_private *dev_priv);
1723 void intel_mark_idle(struct drm_i915_private *dev_priv);
1724 int intel_display_suspend(struct drm_device *dev);
1725 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1726 void intel_encoder_destroy(struct drm_encoder *encoder);
1727 struct drm_display_mode *
1728 intel_encoder_current_mode(struct intel_encoder *encoder);
1729 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1730 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1731 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1732                               enum port port);
1733 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1734                                       struct drm_file *file_priv);
1735 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1736                                              enum pipe pipe);
1737 static inline bool
1738 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1739                     enum intel_output_type type)
1740 {
1741         return crtc_state->output_types & (1 << type);
1742 }
1743 static inline bool
1744 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1745 {
1746         return crtc_state->output_types &
1747                 ((1 << INTEL_OUTPUT_DP) |
1748                  (1 << INTEL_OUTPUT_DP_MST) |
1749                  (1 << INTEL_OUTPUT_EDP));
1750 }
1751 static inline void
1752 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1753 {
1754         drm_wait_one_vblank(&dev_priv->drm, pipe);
1755 }
1756 static inline void
1757 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1758 {
1759         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1760
1761         if (crtc->active)
1762                 intel_wait_for_vblank(dev_priv, pipe);
1763 }
1764
1765 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1766
1767 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1768 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1769                          struct intel_digital_port *dport,
1770                          unsigned int expected_mask);
1771 int intel_get_load_detect_pipe(struct drm_connector *connector,
1772                                const struct drm_display_mode *mode,
1773                                struct intel_load_detect_pipe *old,
1774                                struct drm_modeset_acquire_ctx *ctx);
1775 void intel_release_load_detect_pipe(struct drm_connector *connector,
1776                                     struct intel_load_detect_pipe *old,
1777                                     struct drm_modeset_acquire_ctx *ctx);
1778 struct i915_vma *
1779 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1780                            const struct i915_ggtt_view *view,
1781                            bool uses_fence,
1782                            unsigned long *out_flags);
1783 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1784 struct drm_framebuffer *
1785 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1786                          struct drm_mode_fb_cmd2 *mode_cmd);
1787 int intel_prepare_plane_fb(struct drm_plane *plane,
1788                            struct drm_plane_state *new_state);
1789 void intel_cleanup_plane_fb(struct drm_plane *plane,
1790                             struct drm_plane_state *old_state);
1791 int intel_plane_atomic_get_property(struct drm_plane *plane,
1792                                     const struct drm_plane_state *state,
1793                                     struct drm_property *property,
1794                                     u64 *val);
1795 int intel_plane_atomic_set_property(struct drm_plane *plane,
1796                                     struct drm_plane_state *state,
1797                                     struct drm_property *property,
1798                                     u64 val);
1799 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1800                                     struct drm_crtc_state *crtc_state,
1801                                     const struct intel_plane_state *old_plane_state,
1802                                     struct drm_plane_state *plane_state);
1803
1804 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1805                                     enum pipe pipe);
1806
1807 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1808                      const struct dpll *dpll);
1809 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1810 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1811
1812 /* modesetting asserts */
1813 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1814                            enum pipe pipe);
1815 void assert_pll(struct drm_i915_private *dev_priv,
1816                 enum pipe pipe, bool state);
1817 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1818 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1819 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1820 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1821 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1822 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1823                        enum pipe pipe, bool state);
1824 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1825 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1826 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1827 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1828 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1829 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1830 void intel_finish_reset(struct drm_i915_private *dev_priv);
1831 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1832 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1833 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1834 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1835 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1836 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1837 unsigned int skl_cdclk_get_vco(unsigned int freq);
1838 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1839 void intel_dp_get_m_n(struct intel_crtc *crtc,
1840                       struct intel_crtc_state *pipe_config);
1841 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1842                       enum link_m_n_set m_n);
1843 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1844 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1845                         struct dpll *best_clock);
1846 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1847
1848 bool intel_crtc_active(struct intel_crtc *crtc);
1849 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1850 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1851 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1852 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1853 enum intel_display_power_domain
1854 intel_aux_power_domain(struct intel_digital_port *dig_port);
1855 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1856                                  struct intel_crtc_state *pipe_config);
1857 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1858                                   struct intel_crtc_state *crtc_state);
1859
1860 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1861 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1862 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1863                   u32 pixel_format);
1864
1865 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1866 {
1867         return i915_ggtt_offset(state->vma);
1868 }
1869
1870 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1871                         const struct intel_plane_state *plane_state);
1872 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
1873 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1874                   const struct intel_plane_state *plane_state);
1875 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
1876 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1877                      int plane);
1878 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1879 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1880 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1881 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1882                                    u32 pixel_format, u64 modifier,
1883                                    unsigned int rotation);
1884
1885 /* intel_connector.c */
1886 int intel_connector_init(struct intel_connector *connector);
1887 struct intel_connector *intel_connector_alloc(void);
1888 void intel_connector_free(struct intel_connector *connector);
1889 void intel_connector_destroy(struct drm_connector *connector);
1890 int intel_connector_register(struct drm_connector *connector);
1891 void intel_connector_unregister(struct drm_connector *connector);
1892 void intel_connector_attach_encoder(struct intel_connector *connector,
1893                                     struct intel_encoder *encoder);
1894 bool intel_connector_get_hw_state(struct intel_connector *connector);
1895 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1896 int intel_connector_update_modes(struct drm_connector *connector,
1897                                  struct edid *edid);
1898 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1899 void intel_attach_force_audio_property(struct drm_connector *connector);
1900 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1901 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1902 void intel_attach_colorspace_property(struct drm_connector *connector);
1903
1904 /* intel_csr.c */
1905 void intel_csr_ucode_init(struct drm_i915_private *);
1906 void intel_csr_load_program(struct drm_i915_private *);
1907 void intel_csr_ucode_fini(struct drm_i915_private *);
1908 void intel_csr_ucode_suspend(struct drm_i915_private *);
1909 void intel_csr_ucode_resume(struct drm_i915_private *);
1910
1911 /* intel_dp.c */
1912 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1913                            i915_reg_t dp_reg, enum port port,
1914                            enum pipe *pipe);
1915 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1916                    enum port port);
1917 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1918                              struct intel_connector *intel_connector);
1919 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1920                               int link_rate, u8 lane_count,
1921                               bool link_mst);
1922 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1923                                             int link_rate, u8 lane_count);
1924 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1925 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1926 int intel_dp_retrain_link(struct intel_encoder *encoder,
1927                           struct drm_modeset_acquire_ctx *ctx);
1928 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1929 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1930                                            const struct intel_crtc_state *crtc_state,
1931                                            bool enable);
1932 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1933 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1934 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
1935 int intel_dp_compute_config(struct intel_encoder *encoder,
1936                             struct intel_crtc_state *pipe_config,
1937                             struct drm_connector_state *conn_state);
1938 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1939 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1940 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1941                                   bool long_hpd);
1942 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1943                             const struct drm_connector_state *conn_state);
1944 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1945 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1946 void intel_edp_panel_on(struct intel_dp *intel_dp);
1947 void intel_edp_panel_off(struct intel_dp *intel_dp);
1948 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1949 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1950 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1951 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1952 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1953 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1954 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1955 u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
1956 void intel_plane_destroy(struct drm_plane *plane);
1957 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1958                            const struct intel_crtc_state *crtc_state);
1959 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1960                             const struct intel_crtc_state *crtc_state);
1961 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1962                                unsigned int frontbuffer_bits);
1963 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1964                           unsigned int frontbuffer_bits);
1965
1966 void
1967 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1968                                        u8 dp_train_pat);
1969 void
1970 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1971 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1972 u8
1973 intel_dp_voltage_max(struct intel_dp *intel_dp);
1974 u8
1975 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
1976 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1977                            u8 *link_bw, u8 *rate_select);
1978 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1979 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1980 bool
1981 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]);
1982 u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
1983                                 int mode_clock, int mode_hdisplay);
1984 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
1985                                 int mode_hdisplay);
1986
1987 /* intel_vdsc.c */
1988 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
1989                                 struct intel_crtc_state *pipe_config);
1990 enum intel_display_power_domain
1991 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
1992
1993 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1994 {
1995         return ~((1 << lane_count) - 1) & 0xf;
1996 }
1997
1998 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1999 int intel_dp_link_required(int pixel_clock, int bpp);
2000 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
2001 bool intel_digital_port_connected(struct intel_encoder *encoder);
2002 void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
2003                            struct intel_digital_port *dig_port);
2004
2005 /* intel_dp_aux_backlight.c */
2006 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
2007
2008 /* intel_dp_mst.c */
2009 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
2010 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
2011 /* vlv_dsi.c */
2012 void vlv_dsi_init(struct drm_i915_private *dev_priv);
2013
2014 /* icl_dsi.c */
2015 void icl_dsi_init(struct drm_i915_private *dev_priv);
2016
2017 /* intel_dsi_dcs_backlight.c */
2018 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
2019
2020 /* intel_dvo.c */
2021 void intel_dvo_init(struct drm_i915_private *dev_priv);
2022 /* intel_hotplug.c */
2023 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
2024 bool intel_encoder_hotplug(struct intel_encoder *encoder,
2025                            struct intel_connector *connector);
2026
2027 /* legacy fbdev emulation in intel_fbdev.c */
2028 #ifdef CONFIG_DRM_FBDEV_EMULATION
2029 extern int intel_fbdev_init(struct drm_device *dev);
2030 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
2031 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
2032 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
2033 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
2034 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
2035 extern void intel_fbdev_restore_mode(struct drm_device *dev);
2036 #else
2037 static inline int intel_fbdev_init(struct drm_device *dev)
2038 {
2039         return 0;
2040 }
2041
2042 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
2043 {
2044 }
2045
2046 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
2047 {
2048 }
2049
2050 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
2051 {
2052 }
2053
2054 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
2055 {
2056 }
2057
2058 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
2059 {
2060 }
2061
2062 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
2063 {
2064 }
2065 #endif
2066
2067 /* intel_fbc.c */
2068 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
2069                            struct intel_atomic_state *state);
2070 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
2071 void intel_fbc_pre_update(struct intel_crtc *crtc,
2072                           struct intel_crtc_state *crtc_state,
2073                           struct intel_plane_state *plane_state);
2074 void intel_fbc_post_update(struct intel_crtc *crtc);
2075 void intel_fbc_init(struct drm_i915_private *dev_priv);
2076 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
2077 void intel_fbc_enable(struct intel_crtc *crtc,
2078                       struct intel_crtc_state *crtc_state,
2079                       struct intel_plane_state *plane_state);
2080 void intel_fbc_disable(struct intel_crtc *crtc);
2081 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
2082 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
2083                           unsigned int frontbuffer_bits,
2084                           enum fb_op_origin origin);
2085 void intel_fbc_flush(struct drm_i915_private *dev_priv,
2086                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
2087 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
2088 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
2089 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
2090
2091 /* intel_hdmi.c */
2092 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
2093                      enum port port);
2094 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2095                                struct intel_connector *intel_connector);
2096 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
2097 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2098                               struct intel_crtc_state *pipe_config,
2099                               struct drm_connector_state *conn_state);
2100 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2101                                        struct drm_connector *connector,
2102                                        bool high_tmds_clock_ratio,
2103                                        bool scrambling);
2104 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
2105 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
2106 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
2107                                   const struct intel_crtc_state *crtc_state);
2108 u32 intel_hdmi_infoframe_enable(unsigned int type);
2109 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
2110                                    struct intel_crtc_state *crtc_state);
2111 void intel_read_infoframe(struct intel_encoder *encoder,
2112                           const struct intel_crtc_state *crtc_state,
2113                           enum hdmi_infoframe_type type,
2114                           union hdmi_infoframe *frame);
2115
2116 /* intel_lvds.c */
2117 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
2118                              i915_reg_t lvds_reg, enum pipe *pipe);
2119 void intel_lvds_init(struct drm_i915_private *dev_priv);
2120 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv);
2121 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv);
2122
2123 /* intel_overlay.c */
2124 void intel_overlay_setup(struct drm_i915_private *dev_priv);
2125 void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
2126 int intel_overlay_switch_off(struct intel_overlay *overlay);
2127 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
2128                                   struct drm_file *file_priv);
2129 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
2130                               struct drm_file *file_priv);
2131 void intel_overlay_reset(struct drm_i915_private *dev_priv);
2132
2133
2134 /* intel_panel.c */
2135 int intel_panel_init(struct intel_panel *panel,
2136                      struct drm_display_mode *fixed_mode,
2137                      struct drm_display_mode *downclock_mode);
2138 void intel_panel_fini(struct intel_panel *panel);
2139 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
2140                             struct drm_display_mode *adjusted_mode);
2141 void intel_pch_panel_fitting(struct intel_crtc *crtc,
2142                              struct intel_crtc_state *pipe_config,
2143                              int fitting_mode);
2144 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
2145                               struct intel_crtc_state *pipe_config,
2146                               int fitting_mode);
2147 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
2148                                     u32 level, u32 max);
2149 int intel_panel_setup_backlight(struct drm_connector *connector,
2150                                 enum pipe pipe);
2151 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
2152                                   const struct drm_connector_state *conn_state);
2153 void intel_panel_update_backlight(struct intel_encoder *encoder,
2154                                   const struct intel_crtc_state *crtc_state,
2155                                   const struct drm_connector_state *conn_state);
2156 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
2157 extern struct drm_display_mode *intel_find_panel_downclock(
2158                                 struct drm_i915_private *dev_priv,
2159                                 struct drm_display_mode *fixed_mode,
2160                                 struct drm_connector *connector);
2161
2162 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
2163 int intel_backlight_device_register(struct intel_connector *connector);
2164 void intel_backlight_device_unregister(struct intel_connector *connector);
2165 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2166 static inline int intel_backlight_device_register(struct intel_connector *connector)
2167 {
2168         return 0;
2169 }
2170 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
2171 {
2172 }
2173 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2174
2175 /* intel_hdcp.c */
2176 void intel_hdcp_atomic_check(struct drm_connector *connector,
2177                              struct drm_connector_state *old_state,
2178                              struct drm_connector_state *new_state);
2179 int intel_hdcp_init(struct intel_connector *connector,
2180                     const struct intel_hdcp_shim *hdcp_shim);
2181 int intel_hdcp_enable(struct intel_connector *connector);
2182 int intel_hdcp_disable(struct intel_connector *connector);
2183 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2184 bool intel_hdcp_capable(struct intel_connector *connector);
2185 void intel_hdcp_component_init(struct drm_i915_private *dev_priv);
2186 void intel_hdcp_component_fini(struct drm_i915_private *dev_priv);
2187 void intel_hdcp_cleanup(struct intel_connector *connector);
2188 void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
2189
2190 /* intel_psr.c */
2191 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2192 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2193 void intel_psr_enable(struct intel_dp *intel_dp,
2194                       const struct intel_crtc_state *crtc_state);
2195 void intel_psr_disable(struct intel_dp *intel_dp,
2196                       const struct intel_crtc_state *old_crtc_state);
2197 void intel_psr_update(struct intel_dp *intel_dp,
2198                       const struct intel_crtc_state *crtc_state);
2199 int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);
2200 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2201                           unsigned frontbuffer_bits,
2202                           enum fb_op_origin origin);
2203 void intel_psr_flush(struct drm_i915_private *dev_priv,
2204                      unsigned frontbuffer_bits,
2205                      enum fb_op_origin origin);
2206 void intel_psr_init(struct drm_i915_private *dev_priv);
2207 void intel_psr_compute_config(struct intel_dp *intel_dp,
2208                               struct intel_crtc_state *crtc_state);
2209 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2210 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2211 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2212 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2213                             u32 *out_value);
2214 bool intel_psr_enabled(struct intel_dp *intel_dp);
2215
2216 /* intel_quirks.c */
2217 void intel_init_quirks(struct drm_i915_private *dev_priv);
2218
2219 /* intel_runtime_pm.c */
2220 void intel_runtime_pm_init_early(struct drm_i915_private *dev_priv);
2221 int intel_power_domains_init(struct drm_i915_private *);
2222 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2223 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2224 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2225 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2226 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
2227 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2228 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2229
2230 enum i915_drm_suspend_mode {
2231         I915_DRM_SUSPEND_IDLE,
2232         I915_DRM_SUSPEND_MEM,
2233         I915_DRM_SUSPEND_HIBERNATE,
2234 };
2235
2236 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2237                                  enum i915_drm_suspend_mode);
2238 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2239 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2240 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2241 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2242 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2243 void intel_runtime_pm_cleanup(struct drm_i915_private *dev_priv);
2244 const char *
2245 intel_display_power_domain_str(enum intel_display_power_domain domain);
2246
2247 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2248                                     enum intel_display_power_domain domain);
2249 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2250                                       enum intel_display_power_domain domain);
2251 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
2252                                         enum intel_display_power_domain domain);
2253 intel_wakeref_t
2254 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2255                                    enum intel_display_power_domain domain);
2256 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
2257                                        enum intel_display_power_domain domain);
2258 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2259 void intel_display_power_put(struct drm_i915_private *dev_priv,
2260                              enum intel_display_power_domain domain,
2261                              intel_wakeref_t wakeref);
2262 #else
2263 #define intel_display_power_put(i915, domain, wakeref) \
2264         intel_display_power_put_unchecked(i915, domain)
2265 #endif
2266 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2267                             u8 req_slices);
2268
2269 static inline void
2270 assert_rpm_device_not_suspended(struct drm_i915_private *i915)
2271 {
2272         WARN_ONCE(i915->runtime_pm.suspended,
2273                   "Device suspended during HW access\n");
2274 }
2275
2276 static inline void
2277 assert_rpm_wakelock_held(struct drm_i915_private *i915)
2278 {
2279         assert_rpm_device_not_suspended(i915);
2280         WARN_ONCE(!atomic_read(&i915->runtime_pm.wakeref_count),
2281                   "RPM wakelock ref not held during HW access");
2282 }
2283
2284 /**
2285  * disable_rpm_wakeref_asserts - disable the RPM assert checks
2286  * @i915: i915 device instance
2287  *
2288  * This function disable asserts that check if we hold an RPM wakelock
2289  * reference, while keeping the device-not-suspended checks still enabled.
2290  * It's meant to be used only in special circumstances where our rule about
2291  * the wakelock refcount wrt. the device power state doesn't hold. According
2292  * to this rule at any point where we access the HW or want to keep the HW in
2293  * an active state we must hold an RPM wakelock reference acquired via one of
2294  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2295  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2296  * forcewake release timer, and the GPU RPS and hangcheck works. All other
2297  * users should avoid using this function.
2298  *
2299  * Any calls to this function must have a symmetric call to
2300  * enable_rpm_wakeref_asserts().
2301  */
2302 static inline void
2303 disable_rpm_wakeref_asserts(struct drm_i915_private *i915)
2304 {
2305         atomic_inc(&i915->runtime_pm.wakeref_count);
2306 }
2307
2308 /**
2309  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2310  * @i915: i915 device instance
2311  *
2312  * This function re-enables the RPM assert checks after disabling them with
2313  * disable_rpm_wakeref_asserts. It's meant to be used only in special
2314  * circumstances otherwise its use should be avoided.
2315  *
2316  * Any calls to this function must have a symmetric call to
2317  * disable_rpm_wakeref_asserts().
2318  */
2319 static inline void
2320 enable_rpm_wakeref_asserts(struct drm_i915_private *i915)
2321 {
2322         atomic_dec(&i915->runtime_pm.wakeref_count);
2323 }
2324
2325 intel_wakeref_t intel_runtime_pm_get(struct drm_i915_private *i915);
2326 intel_wakeref_t intel_runtime_pm_get_if_in_use(struct drm_i915_private *i915);
2327 intel_wakeref_t intel_runtime_pm_get_noresume(struct drm_i915_private *i915);
2328
2329 #define with_intel_runtime_pm(i915, wf) \
2330         for ((wf) = intel_runtime_pm_get(i915); (wf); \
2331              intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2332
2333 #define with_intel_runtime_pm_if_in_use(i915, wf) \
2334         for ((wf) = intel_runtime_pm_get_if_in_use(i915); (wf); \
2335              intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2336
2337 void intel_runtime_pm_put_unchecked(struct drm_i915_private *i915);
2338 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2339 void intel_runtime_pm_put(struct drm_i915_private *i915, intel_wakeref_t wref);
2340 #else
2341 #define intel_runtime_pm_put(i915, wref) intel_runtime_pm_put_unchecked(i915)
2342 #endif
2343
2344 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2345 void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
2346                                     struct drm_printer *p);
2347 #else
2348 static inline void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
2349                                                   struct drm_printer *p)
2350 {
2351 }
2352 #endif
2353
2354 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2355                              bool override, unsigned int mask);
2356 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2357                           enum dpio_channel ch, bool override);
2358
2359
2360 /* intel_pm.c */
2361 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2362 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2363 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2364 void intel_update_watermarks(struct intel_crtc *crtc);
2365 void intel_init_pm(struct drm_i915_private *dev_priv);
2366 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2367 void intel_pm_setup(struct drm_i915_private *dev_priv);
2368 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2369 void intel_gpu_ips_teardown(void);
2370 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2371 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2372 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2373 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2374 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2375 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2376 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2377 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2378 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2379 void gen6_rps_boost(struct i915_request *rq);
2380 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
2381 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
2382 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
2383 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
2384 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
2385                                struct skl_ddb_entry *ddb_y,
2386                                struct skl_ddb_entry *ddb_uv);
2387 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2388                           struct skl_ddb_allocation *ddb /* out */);
2389 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
2390                               struct skl_pipe_wm *out);
2391 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2392 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2393 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2394 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2395 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2396 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2397                          const struct skl_wm_level *l2);
2398 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
2399                                  const struct skl_ddb_entry entries[],
2400                                  int num_entries, int ignore_idx);
2401 void skl_write_plane_wm(struct intel_plane *plane,
2402                         const struct intel_crtc_state *crtc_state);
2403 void skl_write_cursor_wm(struct intel_plane *plane,
2404                          const struct intel_crtc_state *crtc_state);
2405 bool ilk_disable_lp_wm(struct drm_device *dev);
2406 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2407                                   struct intel_crtc_state *cstate);
2408 void intel_init_ipc(struct drm_i915_private *dev_priv);
2409 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2410
2411 /* intel_sdvo.c */
2412 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2413                              i915_reg_t sdvo_reg, enum pipe *pipe);
2414 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2415                      i915_reg_t reg, enum port port);
2416
2417
2418 /* intel_sprite.c */
2419 bool is_planar_yuv_format(u32 pixelformat);
2420 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2421                              int usecs);
2422 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2423                                               enum pipe pipe, int plane);
2424 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2425                                     struct drm_file *file_priv);
2426 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2427 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2428 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2429 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2430 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2431 struct intel_plane *
2432 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2433                            enum pipe pipe, enum plane_id plane_id);
2434
2435 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2436 {
2437         /* Don't need to do a gen check, these planes are only available on gen11 */
2438         if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2439                 return true;
2440
2441         return false;
2442 }
2443
2444 static inline bool icl_is_hdr_plane(struct drm_i915_private *dev_priv,
2445                                     enum plane_id plane_id)
2446 {
2447         if (INTEL_GEN(dev_priv) < 11)
2448                 return false;
2449
2450         return plane_id < PLANE_SPRITE2;
2451 }
2452
2453 /* intel_tv.c */
2454 void intel_tv_init(struct drm_i915_private *dev_priv);
2455
2456 /* intel_atomic.c */
2457 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2458                                                 const struct drm_connector_state *state,
2459                                                 struct drm_property *property,
2460                                                 u64 *val);
2461 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2462                                                 struct drm_connector_state *state,
2463                                                 struct drm_property *property,
2464                                                 u64 val);
2465 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2466                                          struct drm_connector_state *new_state);
2467 struct drm_connector_state *
2468 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2469
2470 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2471 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2472                                struct drm_crtc_state *state);
2473 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2474 void intel_atomic_state_clear(struct drm_atomic_state *);
2475
2476 static inline struct intel_crtc_state *
2477 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2478                             struct intel_crtc *crtc)
2479 {
2480         struct drm_crtc_state *crtc_state;
2481         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2482         if (IS_ERR(crtc_state))
2483                 return ERR_CAST(crtc_state);
2484
2485         return to_intel_crtc_state(crtc_state);
2486 }
2487
2488 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2489                                struct intel_crtc *intel_crtc,
2490                                struct intel_crtc_state *crtc_state);
2491
2492 /* intel_atomic_plane.c */
2493 void intel_update_plane(struct intel_plane *plane,
2494                         const struct intel_crtc_state *crtc_state,
2495                         const struct intel_plane_state *plane_state);
2496 void intel_update_slave(struct intel_plane *plane,
2497                         const struct intel_crtc_state *crtc_state,
2498                         const struct intel_plane_state *plane_state);
2499 void intel_disable_plane(struct intel_plane *plane,
2500                          const struct intel_crtc_state *crtc_state);
2501 struct intel_plane *intel_plane_alloc(void);
2502 void intel_plane_free(struct intel_plane *plane);
2503 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2504 void intel_plane_destroy_state(struct drm_plane *plane,
2505                                struct drm_plane_state *state);
2506 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2507 void skl_update_planes_on_crtc(struct intel_atomic_state *state,
2508                                struct intel_crtc *crtc);
2509 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
2510                                 struct intel_crtc *crtc);
2511 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2512                                         struct intel_crtc_state *crtc_state,
2513                                         const struct intel_plane_state *old_plane_state,
2514                                         struct intel_plane_state *intel_state);
2515
2516 /* intel_color.c */
2517 void intel_color_init(struct intel_crtc *crtc);
2518 int intel_color_check(struct intel_crtc_state *crtc_state);
2519 void intel_color_commit(const struct intel_crtc_state *crtc_state);
2520 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
2521
2522 /* intel_lspcon.c */
2523 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2524 void lspcon_resume(struct intel_lspcon *lspcon);
2525 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2526 void lspcon_write_infoframe(struct intel_encoder *encoder,
2527                             const struct intel_crtc_state *crtc_state,
2528                             unsigned int type,
2529                             const void *buf, ssize_t len);
2530 void lspcon_read_infoframe(struct intel_encoder *encoder,
2531                            const struct intel_crtc_state *crtc_state,
2532                            unsigned int type,
2533                            void *frame, ssize_t len);
2534 void lspcon_set_infoframes(struct intel_encoder *encoder,
2535                            bool enable,
2536                            const struct intel_crtc_state *crtc_state,
2537                            const struct drm_connector_state *conn_state);
2538 u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
2539                               const struct intel_crtc_state *pipe_config);
2540 void lspcon_ycbcr420_config(struct drm_connector *connector,
2541                             struct intel_crtc_state *crtc_state);
2542
2543 /* intel_pipe_crc.c */
2544 #ifdef CONFIG_DEBUG_FS
2545 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2546 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2547                                  const char *source_name, size_t *values_cnt);
2548 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2549                                               size_t *count);
2550 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2551 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2552 #else
2553 #define intel_crtc_set_crc_source NULL
2554 #define intel_crtc_verify_crc_source NULL
2555 #define intel_crtc_get_crc_sources NULL
2556 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2557 {
2558 }
2559
2560 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2561 {
2562 }
2563 #endif
2564 #endif /* __INTEL_DRV_H__ */