drivers/gpu/drm/i915/intel_dp_link_training.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_drv.h"
  25
  26 static void
  27 intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
  28 {
  29
  30         DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
  31                       link_status[0], link_status[1], link_status[2],
  32                       link_status[3], link_status[4], link_status[5]);
  33 }
  34
  35 static void
  36 intel_get_adjust_train(struct intel_dp *intel_dp,
  37                        const u8 link_status[DP_LINK_STATUS_SIZE])
  38 {
  39         u8 v = 0;
  40         u8 p = 0;
  41         int lane;
  42         u8 voltage_max;
  43         u8 preemph_max;
  44
  45         for (lane = 0; lane < intel_dp->lane_count; lane++) {
  46                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
  47                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
  48
  49                 if (this_v > v)
  50                         v = this_v;
  51                 if (this_p > p)
  52                         p = this_p;
  53         }
  54
  55         voltage_max = intel_dp_voltage_max(intel_dp);
  56         if (v >= voltage_max)
  57                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
  58
  59         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
  60         if (p >= preemph_max)
  61                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  62
  63         for (lane = 0; lane < 4; lane++)
  64                 intel_dp->train_set[lane] = v | p;
  65 }
  66
  67 static bool
  68 intel_dp_set_link_train(struct intel_dp *intel_dp,
  69                         u8 dp_train_pat)
  70 {
  71         u8 buf[sizeof(intel_dp->train_set) + 1];
  72         int ret, len;
  73
  74         intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
  75
  76         buf[0] = dp_train_pat;
  77         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
  78             DP_TRAINING_PATTERN_DISABLE) {
  79                 /* don't write DP_TRAINING_LANEx_SET on disable */
  80                 len = 1;
  81         } else {
  82                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
  83                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
  84                 len = intel_dp->lane_count + 1;
  85         }
  86
  87         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
  88                                 buf, len);
  89
  90         return ret == len;
  91 }
  92
  93 static bool
  94 intel_dp_reset_link_train(struct intel_dp *intel_dp,
  95                         u8 dp_train_pat)
  96 {
  97         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
  98         intel_dp_set_signal_levels(intel_dp);
  99         return intel_dp_set_link_train(intel_dp, dp_train_pat);
 100 }
 101
 102 static bool
 103 intel_dp_update_link_train(struct intel_dp *intel_dp)
 104 {
 105         int ret;
 106
 107         intel_dp_set_signal_levels(intel_dp);
 108
 109         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
 110                                 intel_dp->train_set, intel_dp->lane_count);
 111
 112         return ret == intel_dp->lane_count;
 113 }
 114
 115 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
 116 {
 117         int lane;
 118
 119         for (lane = 0; lane < intel_dp->lane_count; lane++)
 120                 if ((intel_dp->train_set[lane] &
 121                      DP_TRAIN_MAX_SWING_REACHED) == 0)
 122                         return false;
 123
 124         return true;
 125 }
 126
 127 /* Enable corresponding port and start training pattern 1 */
 128 static bool
 129 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 130 {
 131         u8 voltage;
 132         int voltage_tries, cr_tries, max_cr_tries;
 133         bool max_vswing_reached = false;
 134         u8 link_config[2];
 135         u8 link_bw, rate_select;
 136
 137         if (intel_dp->prepare_link_retrain)
 138                 intel_dp->prepare_link_retrain(intel_dp);
 139
 140         intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
 141                               &link_bw, &rate_select);
 142
 143         if (link_bw)
 144                 DRM_DEBUG_KMS("Using LINK_BW_SET value %02x\n", link_bw);
 145         else
 146                 DRM_DEBUG_KMS("Using LINK_RATE_SET value %02x\n", rate_select);
 147
 148         /* Write the link configuration data */
 149         link_config[0] = link_bw;
 150         link_config[1] = intel_dp->lane_count;
 151         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 152                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 153         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
 154
 155         /* eDP 1.4 rate select method. */
 156         if (!link_bw)
 157                 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
 158                                   &rate_select, 1);
 159
 160         link_config[0] = 0;
 161         link_config[1] = DP_SET_ANSI_8B10B;
 162         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
 163
 164         intel_dp->DP |= DP_PORT_EN;
 165
 166         /* clock recovery */
 167         if (!intel_dp_reset_link_train(intel_dp,
 168                                        DP_TRAINING_PATTERN_1 |
 169                                        DP_LINK_SCRAMBLING_DISABLE)) {
 170                 DRM_ERROR("failed to enable link training\n");
 171                 return false;
 172         }
 173
 174         /*
 175          * The DP 1.4 spec defines the max clock recovery retries value
 176          * as 10 but for pre-DP 1.4 devices we set a very tolerant
 177          * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
 178          * x 5 identical voltage retries). Since the previous specs didn't
 179          * define a limit and created the possibility of an infinite loop
 180          * we want to prevent any sync from triggering that corner case.
 181          */
 182         if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 183                 max_cr_tries = 10;
 184         else
 185                 max_cr_tries = 80;
 186
 187         voltage_tries = 1;
 188         for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
 189                 u8 link_status[DP_LINK_STATUS_SIZE];
 190
 191                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
 192
 193                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
 194                         DRM_ERROR("failed to get link status\n");
 195                         return false;
 196                 }
 197
 198                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 199                         DRM_DEBUG_KMS("clock recovery OK\n");
 200                         return true;
 201                 }
 202
 203                 if (voltage_tries == 5) {
 204                         DRM_DEBUG_KMS("Same voltage tried 5 times\n");
 205                         return false;
 206                 }
 207
 208                 if (max_vswing_reached) {
 209                         DRM_DEBUG_KMS("Max Voltage Swing reached\n");
 210                         return false;
 211                 }
 212
 213                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 214
 215                 /* Update training set as requested by target */
 216                 intel_get_adjust_train(intel_dp, link_status);
 217                 if (!intel_dp_update_link_train(intel_dp)) {
 218                         DRM_ERROR("failed to update link training\n");
 219                         return false;
 220                 }
 221
 222                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
 223                     voltage)
 224                         ++voltage_tries;
 225                 else
 226                         voltage_tries = 1;
 227
 228                 if (intel_dp_link_max_vswing_reached(intel_dp))
 229                         max_vswing_reached = true;
 230
 231         }
 232         DRM_ERROR("Failed clock recovery %d times, giving up!\n", max_cr_tries);
 233         return false;
 234 }
 235
 236 /*
 237  * Pick training pattern for channel equalization. Training pattern 4 for HBR3
 238  * or for 1.4 devices that support it, training Pattern 3 for HBR2
 239  * or 1.2 devices that support it, Training Pattern 2 otherwise.
 240  */
 241 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 242 {
 243         bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 244
 245         /*
 246          * Intel platforms that support HBR3 also support TPS4. It is mandatory
 247          * for all downstream devices that support HBR3. There are no known eDP
 248          * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
 249          * specification.
 250          */
 251         source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
 252         sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
 253         if (source_tps4 && sink_tps4) {
 254                 return DP_TRAINING_PATTERN_4;
 255         } else if (intel_dp->link_rate == 810000) {
 256                 if (!source_tps4)
 257                         DRM_DEBUG_KMS("8.1 Gbps link rate without source HBR3/TPS4 support\n");
 258                 if (!sink_tps4)
 259                         DRM_DEBUG_KMS("8.1 Gbps link rate without sink TPS4 support\n");
 260         }
 261         /*
 262          * Intel platforms that support HBR2 also support TPS3. TPS3 support is
 263          * also mandatory for downstream devices that support HBR2. However, not
 264          * all sinks follow the spec.
 265          */
 266         source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
 267         sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
 268         if (source_tps3 && sink_tps3) {
 269                 return  DP_TRAINING_PATTERN_3;
 270         } else if (intel_dp->link_rate >= 540000) {
 271                 if (!source_tps3)
 272                         DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
 273                 if (!sink_tps3)
 274                         DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
 275         }
 276
 277         return DP_TRAINING_PATTERN_2;
 278 }
 279
 280 static bool
 281 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 282 {
 283         int tries;
 284         u32 training_pattern;
 285         u8 link_status[DP_LINK_STATUS_SIZE];
 286         bool channel_eq = false;
 287
 288         training_pattern = intel_dp_training_pattern(intel_dp);
 289         /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
 290         if (training_pattern != DP_TRAINING_PATTERN_4)
 291                 training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
 292
 293         /* channel equalization */
 294         if (!intel_dp_set_link_train(intel_dp,
 295                                      training_pattern)) {
 296                 DRM_ERROR("failed to start channel equalization\n");
 297                 return false;
 298         }
 299
 300         for (tries = 0; tries < 5; tries++) {
 301
 302                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
 303                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
 304                         DRM_ERROR("failed to get link status\n");
 305                         break;
 306                 }
 307
 308                 /* Make sure clock is still ok */
 309                 if (!drm_dp_clock_recovery_ok(link_status,
 310                                               intel_dp->lane_count)) {
 311                         intel_dp_dump_link_status(link_status);
 312                         DRM_DEBUG_KMS("Clock recovery check failed, cannot "
 313                                       "continue channel equalization\n");
 314                         break;
 315                 }
 316
 317                 if (drm_dp_channel_eq_ok(link_status,
 318                                          intel_dp->lane_count)) {
 319                         channel_eq = true;
 320                         DRM_DEBUG_KMS("Channel EQ done. DP Training "
 321                                       "successful\n");
 322                         break;
 323                 }
 324
 325                 /* Update training set as requested by target */
 326                 intel_get_adjust_train(intel_dp, link_status);
 327                 if (!intel_dp_update_link_train(intel_dp)) {
 328                         DRM_ERROR("failed to update link training\n");
 329                         break;
 330                 }
 331         }
 332
 333         /* Try 5 times, else fail and try at lower BW */
 334         if (tries == 5) {
 335                 intel_dp_dump_link_status(link_status);
 336                 DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
 337         }
 338
 339         intel_dp_set_idle_link_train(intel_dp);
 340
 341         return channel_eq;
 342
 343 }
 344
 345 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
 346 {
 347         intel_dp->link_trained = true;
 348
 349         intel_dp_set_link_train(intel_dp,
 350                                 DP_TRAINING_PATTERN_DISABLE);
 351 }
 352
 353 void
 354 intel_dp_start_link_train(struct intel_dp *intel_dp)
 355 {
 356         struct intel_connector *intel_connector = intel_dp->attached_connector;
 357
 358         if (!intel_dp_link_training_clock_recovery(intel_dp))
 359                 goto failure_handling;
 360         if (!intel_dp_link_training_channel_equalization(intel_dp))
 361                 goto failure_handling;
 362
 363         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
 364                       intel_connector->base.base.id,
 365                       intel_connector->base.name,
 366                       intel_dp->link_rate, intel_dp->lane_count);
 367         return;
 368
 369  failure_handling:
 370         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
 371                       intel_connector->base.base.id,
 372                       intel_connector->base.name,
 373                       intel_dp->link_rate, intel_dp->lane_count);
 374         if (!intel_dp_get_link_train_fallback_values(intel_dp,
 375                                                      intel_dp->link_rate,
 376                                                      intel_dp->lane_count))
 377                 /* Schedule a Hotplug Uevent to userspace to start modeset */
 378                 schedule_work(&intel_connector->modeset_retry_work);
 379         return;
 380 }