drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 struct dp_link_dpll {
  44         int link_bw;
  45         struct dpll dpll;
  46 };
  47
  48 static const struct dp_link_dpll gen4_dpll[] = {
  49         { DP_LINK_BW_1_62,
  50                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  51         { DP_LINK_BW_2_7,
  52                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  53 };
  54
  55 static const struct dp_link_dpll pch_dpll[] = {
  56         { DP_LINK_BW_1_62,
  57                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  58         { DP_LINK_BW_2_7,
  59                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  60 };
  61
  62 static const struct dp_link_dpll vlv_dpll[] = {
  63         { DP_LINK_BW_1_62,
  64                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  65         { DP_LINK_BW_2_7,
  66                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  67 };
  68
  69 /*
  70  * CHV supports eDP 1.4 that have  more link rates.
  71  * Below only provides the fixed rate but exclude variable rate.
  72  */
  73 static const struct dp_link_dpll chv_dpll[] = {
  74         /*
  75          * CHV requires to program fractional division for m2.
  76          * m2 is stored in fixed point format using formula below
  77          * (m2_int << 22) | m2_fraction
  78          */
  79         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  80                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  81         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  83         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  84                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  85 };
  86
  87 /**
  88  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  89  * @intel_dp: DP struct
  90  *
  91  * If a CPU or PCH DP output is attached to an eDP panel, this function
  92  * will return true, and false otherwise.
  93  */
  94 static bool is_edp(struct intel_dp *intel_dp)
  95 {
  96         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  97
  98         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  99 }
 100
 101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 102 {
 103         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 104
 105         return intel_dig_port->base.base.dev;
 106 }
 107
 108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 109 {
 110         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 111 }
 112
 113 static void intel_dp_link_down(struct intel_dp *intel_dp);
 114 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
 115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 116
 117 int
 118 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 119 {
 120         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 121         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 122
 123         switch (max_link_bw) {
 124         case DP_LINK_BW_1_62:
 125         case DP_LINK_BW_2_7:
 126                 break;
 127         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 128                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 129                      INTEL_INFO(dev)->gen >= 8) &&
 130                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 131                         max_link_bw = DP_LINK_BW_5_4;
 132                 else
 133                         max_link_bw = DP_LINK_BW_2_7;
 134                 break;
 135         default:
 136                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 137                      max_link_bw);
 138                 max_link_bw = DP_LINK_BW_1_62;
 139                 break;
 140         }
 141         return max_link_bw;
 142 }
 143
 144 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 145 {
 146         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 147         struct drm_device *dev = intel_dig_port->base.base.dev;
 148         u8 source_max, sink_max;
 149
 150         source_max = 4;
 151         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 152             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 153                 source_max = 2;
 154
 155         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 156
 157         return min(source_max, sink_max);
 158 }
 159
 160 /*
 161  * The units on the numbers in the next two are... bizarre.  Examples will
 162  * make it clearer; this one parallels an example in the eDP spec.
 163  *
 164  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 165  *
 166  *     270000 * 1 * 8 / 10 == 216000
 167  *
 168  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 169  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 170  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 171  * 119000.  At 18bpp that's 2142000 kilobits per second.
 172  *
 173  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 174  * get the result in decakilobits instead of kilobits.
 175  */
 176
 177 static int
 178 intel_dp_link_required(int pixel_clock, int bpp)
 179 {
 180         return (pixel_clock * bpp + 9) / 10;
 181 }
 182
 183 static int
 184 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 185 {
 186         return (max_link_clock * max_lanes * 8) / 10;
 187 }
 188
 189 static enum drm_mode_status
 190 intel_dp_mode_valid(struct drm_connector *connector,
 191                     struct drm_display_mode *mode)
 192 {
 193         struct intel_dp *intel_dp = intel_attached_dp(connector);
 194         struct intel_connector *intel_connector = to_intel_connector(connector);
 195         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 196         int target_clock = mode->clock;
 197         int max_rate, mode_rate, max_lanes, max_link_clock;
 198
 199         if (is_edp(intel_dp) && fixed_mode) {
 200                 if (mode->hdisplay > fixed_mode->hdisplay)
 201                         return MODE_PANEL;
 202
 203                 if (mode->vdisplay > fixed_mode->vdisplay)
 204                         return MODE_PANEL;
 205
 206                 target_clock = fixed_mode->clock;
 207         }
 208
 209         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 210         max_lanes = intel_dp_max_lane_count(intel_dp);
 211
 212         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 213         mode_rate = intel_dp_link_required(target_clock, 18);
 214
 215         if (mode_rate > max_rate)
 216                 return MODE_CLOCK_HIGH;
 217
 218         if (mode->clock < 10000)
 219                 return MODE_CLOCK_LOW;
 220
 221         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 222                 return MODE_H_ILLEGAL;
 223
 224         return MODE_OK;
 225 }
 226
 227 static uint32_t
 228 pack_aux(uint8_t *src, int src_bytes)
 229 {
 230         int     i;
 231         uint32_t v = 0;
 232
 233         if (src_bytes > 4)
 234                 src_bytes = 4;
 235         for (i = 0; i < src_bytes; i++)
 236                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 237         return v;
 238 }
 239
 240 static void
 241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 242 {
 243         int i;
 244         if (dst_bytes > 4)
 245                 dst_bytes = 4;
 246         for (i = 0; i < dst_bytes; i++)
 247                 dst[i] = src >> ((3-i) * 8);
 248 }
 249
 250 /* hrawclock is 1/4 the FSB frequency */
 251 static int
 252 intel_hrawclk(struct drm_device *dev)
 253 {
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         uint32_t clkcfg;
 256
 257         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 258         if (IS_VALLEYVIEW(dev))
 259                 return 200;
 260
 261         clkcfg = I915_READ(CLKCFG);
 262         switch (clkcfg & CLKCFG_FSB_MASK) {
 263         case CLKCFG_FSB_400:
 264                 return 100;
 265         case CLKCFG_FSB_533:
 266                 return 133;
 267         case CLKCFG_FSB_667:
 268                 return 166;
 269         case CLKCFG_FSB_800:
 270                 return 200;
 271         case CLKCFG_FSB_1067:
 272                 return 266;
 273         case CLKCFG_FSB_1333:
 274                 return 333;
 275         /* these two are just a guess; one of them might be right */
 276         case CLKCFG_FSB_1600:
 277         case CLKCFG_FSB_1600_ALT:
 278                 return 400;
 279         default:
 280                 return 133;
 281         }
 282 }
 283
 284 static void
 285 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 286                                     struct intel_dp *intel_dp,
 287                                     struct edp_power_seq *out);
 288 static void
 289 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 290                                               struct intel_dp *intel_dp,
 291                                               struct edp_power_seq *out);
 292
 293 static enum pipe
 294 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 295 {
 296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 297         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 298         struct drm_device *dev = intel_dig_port->base.base.dev;
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         enum port port = intel_dig_port->port;
 301         enum pipe pipe;
 302
 303         /* modeset should have pipe */
 304         if (crtc)
 305                 return to_intel_crtc(crtc)->pipe;
 306
 307         /* init time, try to find a pipe with this port selected */
 308         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 309                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 310                         PANEL_PORT_SELECT_MASK;
 311                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 312                         return pipe;
 313                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 314                         return pipe;
 315         }
 316
 317         /* shrug */
 318         return PIPE_A;
 319 }
 320
 321 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 322 {
 323         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 324
 325         if (HAS_PCH_SPLIT(dev))
 326                 return PCH_PP_CONTROL;
 327         else
 328                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 329 }
 330
 331 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 332 {
 333         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 334
 335         if (HAS_PCH_SPLIT(dev))
 336                 return PCH_PP_STATUS;
 337         else
 338                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 339 }
 340
 341 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 342    This function only applicable when panel PM state is not to be tracked */
 343 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 344                               void *unused)
 345 {
 346         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 347                                                  edp_notifier);
 348         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350         u32 pp_div;
 351         u32 pp_ctrl_reg, pp_div_reg;
 352         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 353
 354         if (!is_edp(intel_dp) || code != SYS_RESTART)
 355                 return 0;
 356
 357         if (IS_VALLEYVIEW(dev)) {
 358                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 359                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 360                 pp_div = I915_READ(pp_div_reg);
 361                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 362
 363                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 364                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 365                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 366                 msleep(intel_dp->panel_power_cycle_delay);
 367         }
 368
 369         return 0;
 370 }
 371
 372 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 373 {
 374         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376
 377         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 378 }
 379
 380 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 381 {
 382         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 383         struct drm_i915_private *dev_priv = dev->dev_private;
 384         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 385         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 386         enum intel_display_power_domain power_domain;
 387
 388         power_domain = intel_display_port_power_domain(intel_encoder);
 389         return intel_display_power_enabled(dev_priv, power_domain) &&
 390                (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 391 }
 392
 393 static void
 394 intel_dp_check_edp(struct intel_dp *intel_dp)
 395 {
 396         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 397         struct drm_i915_private *dev_priv = dev->dev_private;
 398
 399         if (!is_edp(intel_dp))
 400                 return;
 401
 402         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 403                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 404                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 405                               I915_READ(_pp_stat_reg(intel_dp)),
 406                               I915_READ(_pp_ctrl_reg(intel_dp)));
 407         }
 408 }
 409
 410 static uint32_t
 411 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 412 {
 413         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 414         struct drm_device *dev = intel_dig_port->base.base.dev;
 415         struct drm_i915_private *dev_priv = dev->dev_private;
 416         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 417         uint32_t status;
 418         bool done;
 419
 420 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 421         if (has_aux_irq)
 422                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 423                                           msecs_to_jiffies_timeout(10));
 424         else
 425                 done = wait_for_atomic(C, 10) == 0;
 426         if (!done)
 427                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 428                           has_aux_irq);
 429 #undef C
 430
 431         return status;
 432 }
 433
 434 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 435 {
 436         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 437         struct drm_device *dev = intel_dig_port->base.base.dev;
 438
 439         /*
 440          * The clock divider is based off the hrawclk, and would like to run at
 441          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 442          */
 443         return index ? 0 : intel_hrawclk(dev) / 2;
 444 }
 445
 446 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 447 {
 448         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 449         struct drm_device *dev = intel_dig_port->base.base.dev;
 450
 451         if (index)
 452                 return 0;
 453
 454         if (intel_dig_port->port == PORT_A) {
 455                 if (IS_GEN6(dev) || IS_GEN7(dev))
 456                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 457                 else
 458                         return 225; /* eDP input clock at 450Mhz */
 459         } else {
 460                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 461         }
 462 }
 463
 464 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 465 {
 466         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 467         struct drm_device *dev = intel_dig_port->base.base.dev;
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         if (intel_dig_port->port == PORT_A) {
 471                 if (index)
 472                         return 0;
 473                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 474         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 475                 /* Workaround for non-ULT HSW */
 476                 switch (index) {
 477                 case 0: return 63;
 478                 case 1: return 72;
 479                 default: return 0;
 480                 }
 481         } else  {
 482                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 483         }
 484 }
 485
 486 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 487 {
 488         return index ? 0 : 100;
 489 }
 490
 491 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 492                                       bool has_aux_irq,
 493                                       int send_bytes,
 494                                       uint32_t aux_clock_divider)
 495 {
 496         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 497         struct drm_device *dev = intel_dig_port->base.base.dev;
 498         uint32_t precharge, timeout;
 499
 500         if (IS_GEN6(dev))
 501                 precharge = 3;
 502         else
 503                 precharge = 5;
 504
 505         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 506                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 507         else
 508                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 509
 510         return DP_AUX_CH_CTL_SEND_BUSY |
 511                DP_AUX_CH_CTL_DONE |
 512                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 513                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 514                timeout |
 515                DP_AUX_CH_CTL_RECEIVE_ERROR |
 516                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 517                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 518                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 519 }
 520
 521 static int
 522 intel_dp_aux_ch(struct intel_dp *intel_dp,
 523                 uint8_t *send, int send_bytes,
 524                 uint8_t *recv, int recv_size)
 525 {
 526         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 527         struct drm_device *dev = intel_dig_port->base.base.dev;
 528         struct drm_i915_private *dev_priv = dev->dev_private;
 529         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 530         uint32_t ch_data = ch_ctl + 4;
 531         uint32_t aux_clock_divider;
 532         int i, ret, recv_bytes;
 533         uint32_t status;
 534         int try, clock = 0;
 535         bool has_aux_irq = HAS_AUX_IRQ(dev);
 536         bool vdd;
 537
 538         vdd = _edp_panel_vdd_on(intel_dp);
 539
 540         /* dp aux is extremely sensitive to irq latency, hence request the
 541          * lowest possible wakeup latency and so prevent the cpu from going into
 542          * deep sleep states.
 543          */
 544         pm_qos_update_request(&dev_priv->pm_qos, 0);
 545
 546         intel_dp_check_edp(intel_dp);
 547
 548         intel_aux_display_runtime_get(dev_priv);
 549
 550         /* Try to wait for any previous AUX channel activity */
 551         for (try = 0; try < 3; try++) {
 552                 status = I915_READ_NOTRACE(ch_ctl);
 553                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 554                         break;
 555                 msleep(1);
 556         }
 557
 558         if (try == 3) {
 559                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 560                      I915_READ(ch_ctl));
 561                 ret = -EBUSY;
 562                 goto out;
 563         }
 564
 565         /* Only 5 data registers! */
 566         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 567                 ret = -E2BIG;
 568                 goto out;
 569         }
 570
 571         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 572                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 573                                                           has_aux_irq,
 574                                                           send_bytes,
 575                                                           aux_clock_divider);
 576
 577                 /* Must try at least 3 times according to DP spec */
 578                 for (try = 0; try < 5; try++) {
 579                         /* Load the send data into the aux channel data registers */
 580                         for (i = 0; i < send_bytes; i += 4)
 581                                 I915_WRITE(ch_data + i,
 582                                            pack_aux(send + i, send_bytes - i));
 583
 584                         /* Send the command and wait for it to complete */
 585                         I915_WRITE(ch_ctl, send_ctl);
 586
 587                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 588
 589                         /* Clear done status and any errors */
 590                         I915_WRITE(ch_ctl,
 591                                    status |
 592                                    DP_AUX_CH_CTL_DONE |
 593                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 594                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 595
 596                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 597                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 598                                 continue;
 599                         if (status & DP_AUX_CH_CTL_DONE)
 600                                 break;
 601                 }
 602                 if (status & DP_AUX_CH_CTL_DONE)
 603                         break;
 604         }
 605
 606         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 607                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 608                 ret = -EBUSY;
 609                 goto out;
 610         }
 611
 612         /* Check for timeout or receive error.
 613          * Timeouts occur when the sink is not connected
 614          */
 615         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 616                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 617                 ret = -EIO;
 618                 goto out;
 619         }
 620
 621         /* Timeouts occur when the device isn't connected, so they're
 622          * "normal" -- don't fill the kernel log with these */
 623         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 624                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 625                 ret = -ETIMEDOUT;
 626                 goto out;
 627         }
 628
 629         /* Unload any bytes sent back from the other side */
 630         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 631                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 632         if (recv_bytes > recv_size)
 633                 recv_bytes = recv_size;
 634
 635         for (i = 0; i < recv_bytes; i += 4)
 636                 unpack_aux(I915_READ(ch_data + i),
 637                            recv + i, recv_bytes - i);
 638
 639         ret = recv_bytes;
 640 out:
 641         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 642         intel_aux_display_runtime_put(dev_priv);
 643
 644         if (vdd)
 645                 edp_panel_vdd_off(intel_dp, false);
 646
 647         return ret;
 648 }
 649
 650 #define BARE_ADDRESS_SIZE       3
 651 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 652 static ssize_t
 653 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 654 {
 655         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 656         uint8_t txbuf[20], rxbuf[20];
 657         size_t txsize, rxsize;
 658         int ret;
 659
 660         txbuf[0] = msg->request << 4;
 661         txbuf[1] = msg->address >> 8;
 662         txbuf[2] = msg->address & 0xff;
 663         txbuf[3] = msg->size - 1;
 664
 665         switch (msg->request & ~DP_AUX_I2C_MOT) {
 666         case DP_AUX_NATIVE_WRITE:
 667         case DP_AUX_I2C_WRITE:
 668                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 669                 rxsize = 1;
 670
 671                 if (WARN_ON(txsize > 20))
 672                         return -E2BIG;
 673
 674                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 675
 676                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 677                 if (ret > 0) {
 678                         msg->reply = rxbuf[0] >> 4;
 679
 680                         /* Return payload size. */
 681                         ret = msg->size;
 682                 }
 683                 break;
 684
 685         case DP_AUX_NATIVE_READ:
 686         case DP_AUX_I2C_READ:
 687                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 688                 rxsize = msg->size + 1;
 689
 690                 if (WARN_ON(rxsize > 20))
 691                         return -E2BIG;
 692
 693                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 694                 if (ret > 0) {
 695                         msg->reply = rxbuf[0] >> 4;
 696                         /*
 697                          * Assume happy day, and copy the data. The caller is
 698                          * expected to check msg->reply before touching it.
 699                          *
 700                          * Return payload size.
 701                          */
 702                         ret--;
 703                         memcpy(msg->buffer, rxbuf + 1, ret);
 704                 }
 705                 break;
 706
 707         default:
 708                 ret = -EINVAL;
 709                 break;
 710         }
 711
 712         return ret;
 713 }
 714
 715 static void
 716 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 717 {
 718         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 719         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 720         enum port port = intel_dig_port->port;
 721         const char *name = NULL;
 722         int ret;
 723
 724         switch (port) {
 725         case PORT_A:
 726                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 727                 name = "DPDDC-A";
 728                 break;
 729         case PORT_B:
 730                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 731                 name = "DPDDC-B";
 732                 break;
 733         case PORT_C:
 734                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 735                 name = "DPDDC-C";
 736                 break;
 737         case PORT_D:
 738                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 739                 name = "DPDDC-D";
 740                 break;
 741         default:
 742                 BUG();
 743         }
 744
 745         if (!HAS_DDI(dev))
 746                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 747
 748         intel_dp->aux.name = name;
 749         intel_dp->aux.dev = dev->dev;
 750         intel_dp->aux.transfer = intel_dp_aux_transfer;
 751
 752         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 753                       connector->base.kdev->kobj.name);
 754
 755         ret = drm_dp_aux_register(&intel_dp->aux);
 756         if (ret < 0) {
 757                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
 758                           name, ret);
 759                 return;
 760         }
 761
 762         ret = sysfs_create_link(&connector->base.kdev->kobj,
 763                                 &intel_dp->aux.ddc.dev.kobj,
 764                                 intel_dp->aux.ddc.dev.kobj.name);
 765         if (ret < 0) {
 766                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
 767                 drm_dp_aux_unregister(&intel_dp->aux);
 768         }
 769 }
 770
 771 static void
 772 intel_dp_connector_unregister(struct intel_connector *intel_connector)
 773 {
 774         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
 775
 776         if (!intel_connector->mst_port)
 777                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
 778                                   intel_dp->aux.ddc.dev.kobj.name);
 779         intel_connector_unregister(intel_connector);
 780 }
 781
 782 static void
 783 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
 784 {
 785         switch (link_bw) {
 786         case DP_LINK_BW_1_62:
 787                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 788                 break;
 789         case DP_LINK_BW_2_7:
 790                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 791                 break;
 792         case DP_LINK_BW_5_4:
 793                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 794                 break;
 795         }
 796 }
 797
 798 static void
 799 intel_dp_set_clock(struct intel_encoder *encoder,
 800                    struct intel_crtc_config *pipe_config, int link_bw)
 801 {
 802         struct drm_device *dev = encoder->base.dev;
 803         const struct dp_link_dpll *divisor = NULL;
 804         int i, count = 0;
 805
 806         if (IS_G4X(dev)) {
 807                 divisor = gen4_dpll;
 808                 count = ARRAY_SIZE(gen4_dpll);
 809         } else if (HAS_PCH_SPLIT(dev)) {
 810                 divisor = pch_dpll;
 811                 count = ARRAY_SIZE(pch_dpll);
 812         } else if (IS_CHERRYVIEW(dev)) {
 813                 divisor = chv_dpll;
 814                 count = ARRAY_SIZE(chv_dpll);
 815         } else if (IS_VALLEYVIEW(dev)) {
 816                 divisor = vlv_dpll;
 817                 count = ARRAY_SIZE(vlv_dpll);
 818         }
 819
 820         if (divisor && count) {
 821                 for (i = 0; i < count; i++) {
 822                         if (link_bw == divisor[i].link_bw) {
 823                                 pipe_config->dpll = divisor[i].dpll;
 824                                 pipe_config->clock_set = true;
 825                                 break;
 826                         }
 827                 }
 828         }
 829 }
 830
 831 static void
 832 intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
 833 {
 834         struct drm_device *dev = crtc->base.dev;
 835         struct drm_i915_private *dev_priv = dev->dev_private;
 836         enum transcoder transcoder = crtc->config.cpu_transcoder;
 837
 838         I915_WRITE(PIPE_DATA_M2(transcoder),
 839                 TU_SIZE(m_n->tu) | m_n->gmch_m);
 840         I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
 841         I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
 842         I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
 843 }
 844
 845 bool
 846 intel_dp_compute_config(struct intel_encoder *encoder,
 847                         struct intel_crtc_config *pipe_config)
 848 {
 849         struct drm_device *dev = encoder->base.dev;
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 852         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 853         enum port port = dp_to_dig_port(intel_dp)->port;
 854         struct intel_crtc *intel_crtc = encoder->new_crtc;
 855         struct intel_connector *intel_connector = intel_dp->attached_connector;
 856         int lane_count, clock;
 857         int min_lane_count = 1;
 858         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 859         /* Conveniently, the link BW constants become indices with a shift...*/
 860         int min_clock = 0;
 861         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 862         int bpp, mode_rate;
 863         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 864         int link_avail, link_clock;
 865
 866         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 867                 pipe_config->has_pch_encoder = true;
 868
 869         pipe_config->has_dp_encoder = true;
 870         pipe_config->has_audio = intel_dp->has_audio;
 871
 872         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 873                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 874                                        adjusted_mode);
 875                 if (!HAS_PCH_SPLIT(dev))
 876                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 877                                                  intel_connector->panel.fitting_mode);
 878                 else
 879                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 880                                                 intel_connector->panel.fitting_mode);
 881         }
 882
 883         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 884                 return false;
 885
 886         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 887                       "max bw %02x pixel clock %iKHz\n",
 888                       max_lane_count, bws[max_clock],
 889                       adjusted_mode->crtc_clock);
 890
 891         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 892          * bpc in between. */
 893         bpp = pipe_config->pipe_bpp;
 894         if (is_edp(intel_dp)) {
 895                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
 896                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 897                                       dev_priv->vbt.edp_bpp);
 898                         bpp = dev_priv->vbt.edp_bpp;
 899                 }
 900
 901                 if (IS_BROADWELL(dev)) {
 902                         /* Yes, it's an ugly hack. */
 903                         min_lane_count = max_lane_count;
 904                         DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
 905                                       min_lane_count);
 906                 } else if (dev_priv->vbt.edp_lanes) {
 907                         min_lane_count = min(dev_priv->vbt.edp_lanes,
 908                                              max_lane_count);
 909                         DRM_DEBUG_KMS("using min %u lanes per VBT\n",
 910                                       min_lane_count);
 911                 }
 912
 913                 if (dev_priv->vbt.edp_rate) {
 914                         min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
 915                         DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
 916                                       bws[min_clock]);
 917                 }
 918         }
 919
 920         for (; bpp >= 6*3; bpp -= 2*3) {
 921                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 922                                                    bpp);
 923
 924                 for (clock = min_clock; clock <= max_clock; clock++) {
 925                         for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
 926                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 927                                 link_avail = intel_dp_max_data_rate(link_clock,
 928                                                                     lane_count);
 929
 930                                 if (mode_rate <= link_avail) {
 931                                         goto found;
 932                                 }
 933                         }
 934                 }
 935         }
 936
 937         return false;
 938
 939 found:
 940         if (intel_dp->color_range_auto) {
 941                 /*
 942                  * See:
 943                  * CEA-861-E - 5.1 Default Encoding Parameters
 944                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 945                  */
 946                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 947                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 948                 else
 949                         intel_dp->color_range = 0;
 950         }
 951
 952         if (intel_dp->color_range)
 953                 pipe_config->limited_color_range = true;
 954
 955         intel_dp->link_bw = bws[clock];
 956         intel_dp->lane_count = lane_count;
 957         pipe_config->pipe_bpp = bpp;
 958         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 959
 960         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 961                       intel_dp->link_bw, intel_dp->lane_count,
 962                       pipe_config->port_clock, bpp);
 963         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 964                       mode_rate, link_avail);
 965
 966         intel_link_compute_m_n(bpp, lane_count,
 967                                adjusted_mode->crtc_clock,
 968                                pipe_config->port_clock,
 969                                &pipe_config->dp_m_n);
 970
 971         if (intel_connector->panel.downclock_mode != NULL &&
 972                 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
 973                         intel_link_compute_m_n(bpp, lane_count,
 974                                 intel_connector->panel.downclock_mode->clock,
 975                                 pipe_config->port_clock,
 976                                 &pipe_config->dp_m2_n2);
 977         }
 978
 979         if (HAS_DDI(dev))
 980                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
 981         else
 982                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 983
 984         return true;
 985 }
 986
 987 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 988 {
 989         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 990         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 991         struct drm_device *dev = crtc->base.dev;
 992         struct drm_i915_private *dev_priv = dev->dev_private;
 993         u32 dpa_ctl;
 994
 995         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 996         dpa_ctl = I915_READ(DP_A);
 997         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 998
 999         if (crtc->config.port_clock == 162000) {
1000                 /* For a long time we've carried around a ILK-DevA w/a for the
1001                  * 160MHz clock. If we're really unlucky, it's still required.
1002                  */
1003                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1004                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1005                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1006         } else {
1007                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1008                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1009         }
1010
1011         I915_WRITE(DP_A, dpa_ctl);
1012
1013         POSTING_READ(DP_A);
1014         udelay(500);
1015 }
1016
1017 static void intel_dp_prepare(struct intel_encoder *encoder)
1018 {
1019         struct drm_device *dev = encoder->base.dev;
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1022         enum port port = dp_to_dig_port(intel_dp)->port;
1023         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1024         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1025
1026         /*
1027          * There are four kinds of DP registers:
1028          *
1029          *      IBX PCH
1030          *      SNB CPU
1031          *      IVB CPU
1032          *      CPT PCH
1033          *
1034          * IBX PCH and CPU are the same for almost everything,
1035          * except that the CPU DP PLL is configured in this
1036          * register
1037          *
1038          * CPT PCH is quite different, having many bits moved
1039          * to the TRANS_DP_CTL register instead. That
1040          * configuration happens (oddly) in ironlake_pch_enable
1041          */
1042
1043         /* Preserve the BIOS-computed detected bit. This is
1044          * supposed to be read-only.
1045          */
1046         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1047
1048         /* Handle DP bits in common between all three register formats */
1049         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1050         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1051
1052         if (crtc->config.has_audio) {
1053                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1054                                  pipe_name(crtc->pipe));
1055                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1056                 intel_write_eld(&encoder->base, adjusted_mode);
1057         }
1058
1059         /* Split out the IBX/CPU vs CPT settings */
1060
1061         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1062                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1063                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1064                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1065                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1066                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1067
1068                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1069                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1070
1071                 intel_dp->DP |= crtc->pipe << 29;
1072         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1073                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1074                         intel_dp->DP |= intel_dp->color_range;
1075
1076                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1077                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1078                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1079                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1080                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1081
1082                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1083                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1084
1085                 if (!IS_CHERRYVIEW(dev)) {
1086                         if (crtc->pipe == 1)
1087                                 intel_dp->DP |= DP_PIPEB_SELECT;
1088                 } else {
1089                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1090                 }
1091         } else {
1092                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1093         }
1094 }
1095
1096 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1097 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1098
1099 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1100 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1101
1102 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1103 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1104
1105 static void wait_panel_status(struct intel_dp *intel_dp,
1106                                        u32 mask,
1107                                        u32 value)
1108 {
1109         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         u32 pp_stat_reg, pp_ctrl_reg;
1112
1113         pp_stat_reg = _pp_stat_reg(intel_dp);
1114         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1115
1116         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1117                         mask, value,
1118                         I915_READ(pp_stat_reg),
1119                         I915_READ(pp_ctrl_reg));
1120
1121         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1122                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1123                                 I915_READ(pp_stat_reg),
1124                                 I915_READ(pp_ctrl_reg));
1125         }
1126
1127         DRM_DEBUG_KMS("Wait complete\n");
1128 }
1129
1130 static void wait_panel_on(struct intel_dp *intel_dp)
1131 {
1132         DRM_DEBUG_KMS("Wait for panel power on\n");
1133         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1134 }
1135
1136 static void wait_panel_off(struct intel_dp *intel_dp)
1137 {
1138         DRM_DEBUG_KMS("Wait for panel power off time\n");
1139         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1140 }
1141
1142 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1143 {
1144         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1145
1146         /* When we disable the VDD override bit last we have to do the manual
1147          * wait. */
1148         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1149                                        intel_dp->panel_power_cycle_delay);
1150
1151         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1152 }
1153
1154 static void wait_backlight_on(struct intel_dp *intel_dp)
1155 {
1156         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1157                                        intel_dp->backlight_on_delay);
1158 }
1159
1160 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1161 {
1162         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1163                                        intel_dp->backlight_off_delay);
1164 }
1165
1166 /* Read the current pp_control value, unlocking the register if it
1167  * is locked
1168  */
1169
1170 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1171 {
1172         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1173         struct drm_i915_private *dev_priv = dev->dev_private;
1174         u32 control;
1175
1176         control = I915_READ(_pp_ctrl_reg(intel_dp));
1177         control &= ~PANEL_UNLOCK_MASK;
1178         control |= PANEL_UNLOCK_REGS;
1179         return control;
1180 }
1181
1182 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1183 {
1184         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1185         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1186         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1187         struct drm_i915_private *dev_priv = dev->dev_private;
1188         enum intel_display_power_domain power_domain;
1189         u32 pp;
1190         u32 pp_stat_reg, pp_ctrl_reg;
1191         bool need_to_disable = !intel_dp->want_panel_vdd;
1192
1193         if (!is_edp(intel_dp))
1194                 return false;
1195
1196         intel_dp->want_panel_vdd = true;
1197
1198         if (edp_have_panel_vdd(intel_dp))
1199                 return need_to_disable;
1200
1201         power_domain = intel_display_port_power_domain(intel_encoder);
1202         intel_display_power_get(dev_priv, power_domain);
1203
1204         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1205
1206         if (!edp_have_panel_power(intel_dp))
1207                 wait_panel_power_cycle(intel_dp);
1208
1209         pp = ironlake_get_pp_control(intel_dp);
1210         pp |= EDP_FORCE_VDD;
1211
1212         pp_stat_reg = _pp_stat_reg(intel_dp);
1213         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1214
1215         I915_WRITE(pp_ctrl_reg, pp);
1216         POSTING_READ(pp_ctrl_reg);
1217         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1218                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1219         /*
1220          * If the panel wasn't on, delay before accessing aux channel
1221          */
1222         if (!edp_have_panel_power(intel_dp)) {
1223                 DRM_DEBUG_KMS("eDP was not running\n");
1224                 msleep(intel_dp->panel_power_up_delay);
1225         }
1226
1227         return need_to_disable;
1228 }
1229
1230 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1231 {
1232         if (is_edp(intel_dp)) {
1233                 bool vdd = _edp_panel_vdd_on(intel_dp);
1234
1235                 WARN(!vdd, "eDP VDD already requested on\n");
1236         }
1237 }
1238
1239 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1240 {
1241         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1242         struct drm_i915_private *dev_priv = dev->dev_private;
1243         u32 pp;
1244         u32 pp_stat_reg, pp_ctrl_reg;
1245
1246         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1247
1248         if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1249                 struct intel_digital_port *intel_dig_port =
1250                                                 dp_to_dig_port(intel_dp);
1251                 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1252                 enum intel_display_power_domain power_domain;
1253
1254                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1255
1256                 pp = ironlake_get_pp_control(intel_dp);
1257                 pp &= ~EDP_FORCE_VDD;
1258
1259                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1260                 pp_stat_reg = _pp_stat_reg(intel_dp);
1261
1262                 I915_WRITE(pp_ctrl_reg, pp);
1263                 POSTING_READ(pp_ctrl_reg);
1264
1265                 /* Make sure sequencer is idle before allowing subsequent activity */
1266                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1267                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1268
1269                 if ((pp & POWER_TARGET_ON) == 0)
1270                         intel_dp->last_power_cycle = jiffies;
1271
1272                 power_domain = intel_display_port_power_domain(intel_encoder);
1273                 intel_display_power_put(dev_priv, power_domain);
1274         }
1275 }
1276
1277 static void edp_panel_vdd_work(struct work_struct *__work)
1278 {
1279         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1280                                                  struct intel_dp, panel_vdd_work);
1281         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1282
1283         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1284         edp_panel_vdd_off_sync(intel_dp);
1285         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1286 }
1287
1288 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1289 {
1290         unsigned long delay;
1291
1292         /*
1293          * Queue the timer to fire a long time from now (relative to the power
1294          * down delay) to keep the panel power up across a sequence of
1295          * operations.
1296          */
1297         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1298         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1299 }
1300
1301 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1302 {
1303         if (!is_edp(intel_dp))
1304                 return;
1305
1306         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1307
1308         intel_dp->want_panel_vdd = false;
1309
1310         if (sync)
1311                 edp_panel_vdd_off_sync(intel_dp);
1312         else
1313                 edp_panel_vdd_schedule_off(intel_dp);
1314 }
1315
1316 void intel_edp_panel_on(struct intel_dp *intel_dp)
1317 {
1318         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1319         struct drm_i915_private *dev_priv = dev->dev_private;
1320         u32 pp;
1321         u32 pp_ctrl_reg;
1322
1323         if (!is_edp(intel_dp))
1324                 return;
1325
1326         DRM_DEBUG_KMS("Turn eDP power on\n");
1327
1328         if (edp_have_panel_power(intel_dp)) {
1329                 DRM_DEBUG_KMS("eDP power already on\n");
1330                 return;
1331         }
1332
1333         wait_panel_power_cycle(intel_dp);
1334
1335         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1336         pp = ironlake_get_pp_control(intel_dp);
1337         if (IS_GEN5(dev)) {
1338                 /* ILK workaround: disable reset around power sequence */
1339                 pp &= ~PANEL_POWER_RESET;
1340                 I915_WRITE(pp_ctrl_reg, pp);
1341                 POSTING_READ(pp_ctrl_reg);
1342         }
1343
1344         pp |= POWER_TARGET_ON;
1345         if (!IS_GEN5(dev))
1346                 pp |= PANEL_POWER_RESET;
1347
1348         I915_WRITE(pp_ctrl_reg, pp);
1349         POSTING_READ(pp_ctrl_reg);
1350
1351         wait_panel_on(intel_dp);
1352         intel_dp->last_power_on = jiffies;
1353
1354         if (IS_GEN5(dev)) {
1355                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1356                 I915_WRITE(pp_ctrl_reg, pp);
1357                 POSTING_READ(pp_ctrl_reg);
1358         }
1359 }
1360
1361 void intel_edp_panel_off(struct intel_dp *intel_dp)
1362 {
1363         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1364         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1365         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1366         struct drm_i915_private *dev_priv = dev->dev_private;
1367         enum intel_display_power_domain power_domain;
1368         u32 pp;
1369         u32 pp_ctrl_reg;
1370
1371         if (!is_edp(intel_dp))
1372                 return;
1373
1374         DRM_DEBUG_KMS("Turn eDP power off\n");
1375
1376         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1377
1378         pp = ironlake_get_pp_control(intel_dp);
1379         /* We need to switch off panel power _and_ force vdd, for otherwise some
1380          * panels get very unhappy and cease to work. */
1381         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1382                 EDP_BLC_ENABLE);
1383
1384         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1385
1386         intel_dp->want_panel_vdd = false;
1387
1388         I915_WRITE(pp_ctrl_reg, pp);
1389         POSTING_READ(pp_ctrl_reg);
1390
1391         intel_dp->last_power_cycle = jiffies;
1392         wait_panel_off(intel_dp);
1393
1394         /* We got a reference when we enabled the VDD. */
1395         power_domain = intel_display_port_power_domain(intel_encoder);
1396         intel_display_power_put(dev_priv, power_domain);
1397 }
1398
1399 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1400 {
1401         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1402         struct drm_device *dev = intel_dig_port->base.base.dev;
1403         struct drm_i915_private *dev_priv = dev->dev_private;
1404         u32 pp;
1405         u32 pp_ctrl_reg;
1406
1407         if (!is_edp(intel_dp))
1408                 return;
1409
1410         DRM_DEBUG_KMS("\n");
1411
1412         intel_panel_enable_backlight(intel_dp->attached_connector);
1413
1414         /*
1415          * If we enable the backlight right away following a panel power
1416          * on, we may see slight flicker as the panel syncs with the eDP
1417          * link.  So delay a bit to make sure the image is solid before
1418          * allowing it to appear.
1419          */
1420         wait_backlight_on(intel_dp);
1421         pp = ironlake_get_pp_control(intel_dp);
1422         pp |= EDP_BLC_ENABLE;
1423
1424         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1425
1426         I915_WRITE(pp_ctrl_reg, pp);
1427         POSTING_READ(pp_ctrl_reg);
1428 }
1429
1430 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1431 {
1432         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1433         struct drm_i915_private *dev_priv = dev->dev_private;
1434         u32 pp;
1435         u32 pp_ctrl_reg;
1436
1437         if (!is_edp(intel_dp))
1438                 return;
1439
1440         DRM_DEBUG_KMS("\n");
1441         pp = ironlake_get_pp_control(intel_dp);
1442         pp &= ~EDP_BLC_ENABLE;
1443
1444         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1445
1446         I915_WRITE(pp_ctrl_reg, pp);
1447         POSTING_READ(pp_ctrl_reg);
1448         intel_dp->last_backlight_off = jiffies;
1449
1450         edp_wait_backlight_off(intel_dp);
1451
1452         intel_panel_disable_backlight(intel_dp->attached_connector);
1453 }
1454
1455 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1456 {
1457         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1458         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1459         struct drm_device *dev = crtc->dev;
1460         struct drm_i915_private *dev_priv = dev->dev_private;
1461         u32 dpa_ctl;
1462
1463         assert_pipe_disabled(dev_priv,
1464                              to_intel_crtc(crtc)->pipe);
1465
1466         DRM_DEBUG_KMS("\n");
1467         dpa_ctl = I915_READ(DP_A);
1468         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1469         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1470
1471         /* We don't adjust intel_dp->DP while tearing down the link, to
1472          * facilitate link retraining (e.g. after hotplug). Hence clear all
1473          * enable bits here to ensure that we don't enable too much. */
1474         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1475         intel_dp->DP |= DP_PLL_ENABLE;
1476         I915_WRITE(DP_A, intel_dp->DP);
1477         POSTING_READ(DP_A);
1478         udelay(200);
1479 }
1480
1481 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1482 {
1483         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1484         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1485         struct drm_device *dev = crtc->dev;
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487         u32 dpa_ctl;
1488
1489         assert_pipe_disabled(dev_priv,
1490                              to_intel_crtc(crtc)->pipe);
1491
1492         dpa_ctl = I915_READ(DP_A);
1493         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1494              "dp pll off, should be on\n");
1495         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1496
1497         /* We can't rely on the value tracked for the DP register in
1498          * intel_dp->DP because link_down must not change that (otherwise link
1499          * re-training will fail. */
1500         dpa_ctl &= ~DP_PLL_ENABLE;
1501         I915_WRITE(DP_A, dpa_ctl);
1502         POSTING_READ(DP_A);
1503         udelay(200);
1504 }
1505
1506 /* If the sink supports it, try to set the power state appropriately */
1507 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1508 {
1509         int ret, i;
1510
1511         /* Should have a valid DPCD by this point */
1512         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1513                 return;
1514
1515         if (mode != DRM_MODE_DPMS_ON) {
1516                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1517                                          DP_SET_POWER_D3);
1518                 if (ret != 1)
1519                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1520         } else {
1521                 /*
1522                  * When turning on, we need to retry for 1ms to give the sink
1523                  * time to wake up.
1524                  */
1525                 for (i = 0; i < 3; i++) {
1526                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1527                                                  DP_SET_POWER_D0);
1528                         if (ret == 1)
1529                                 break;
1530                         msleep(1);
1531                 }
1532         }
1533 }
1534
1535 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1536                                   enum pipe *pipe)
1537 {
1538         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1539         enum port port = dp_to_dig_port(intel_dp)->port;
1540         struct drm_device *dev = encoder->base.dev;
1541         struct drm_i915_private *dev_priv = dev->dev_private;
1542         enum intel_display_power_domain power_domain;
1543         u32 tmp;
1544
1545         power_domain = intel_display_port_power_domain(encoder);
1546         if (!intel_display_power_enabled(dev_priv, power_domain))
1547                 return false;
1548
1549         tmp = I915_READ(intel_dp->output_reg);
1550
1551         if (!(tmp & DP_PORT_EN))
1552                 return false;
1553
1554         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1555                 *pipe = PORT_TO_PIPE_CPT(tmp);
1556         } else if (IS_CHERRYVIEW(dev)) {
1557                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1558         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1559                 *pipe = PORT_TO_PIPE(tmp);
1560         } else {
1561                 u32 trans_sel;
1562                 u32 trans_dp;
1563                 int i;
1564
1565                 switch (intel_dp->output_reg) {
1566                 case PCH_DP_B:
1567                         trans_sel = TRANS_DP_PORT_SEL_B;
1568                         break;
1569                 case PCH_DP_C:
1570                         trans_sel = TRANS_DP_PORT_SEL_C;
1571                         break;
1572                 case PCH_DP_D:
1573                         trans_sel = TRANS_DP_PORT_SEL_D;
1574                         break;
1575                 default:
1576                         return true;
1577                 }
1578
1579                 for_each_pipe(i) {
1580                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1581                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1582                                 *pipe = i;
1583                                 return true;
1584                         }
1585                 }
1586
1587                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1588                               intel_dp->output_reg);
1589         }
1590
1591         return true;
1592 }
1593
1594 static void intel_dp_get_config(struct intel_encoder *encoder,
1595                                 struct intel_crtc_config *pipe_config)
1596 {
1597         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1598         u32 tmp, flags = 0;
1599         struct drm_device *dev = encoder->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         enum port port = dp_to_dig_port(intel_dp)->port;
1602         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1603         int dotclock;
1604
1605         tmp = I915_READ(intel_dp->output_reg);
1606         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1607                 pipe_config->has_audio = true;
1608
1609         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1610                 if (tmp & DP_SYNC_HS_HIGH)
1611                         flags |= DRM_MODE_FLAG_PHSYNC;
1612                 else
1613                         flags |= DRM_MODE_FLAG_NHSYNC;
1614
1615                 if (tmp & DP_SYNC_VS_HIGH)
1616                         flags |= DRM_MODE_FLAG_PVSYNC;
1617                 else
1618                         flags |= DRM_MODE_FLAG_NVSYNC;
1619         } else {
1620                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1621                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1622                         flags |= DRM_MODE_FLAG_PHSYNC;
1623                 else
1624                         flags |= DRM_MODE_FLAG_NHSYNC;
1625
1626                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1627                         flags |= DRM_MODE_FLAG_PVSYNC;
1628                 else
1629                         flags |= DRM_MODE_FLAG_NVSYNC;
1630         }
1631
1632         pipe_config->adjusted_mode.flags |= flags;
1633
1634         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1635             tmp & DP_COLOR_RANGE_16_235)
1636                 pipe_config->limited_color_range = true;
1637
1638         pipe_config->has_dp_encoder = true;
1639
1640         intel_dp_get_m_n(crtc, pipe_config);
1641
1642         if (port == PORT_A) {
1643                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1644                         pipe_config->port_clock = 162000;
1645                 else
1646                         pipe_config->port_clock = 270000;
1647         }
1648
1649         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1650                                             &pipe_config->dp_m_n);
1651
1652         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1653                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1654
1655         pipe_config->adjusted_mode.crtc_clock = dotclock;
1656
1657         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1658             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1659                 /*
1660                  * This is a big fat ugly hack.
1661                  *
1662                  * Some machines in UEFI boot mode provide us a VBT that has 18
1663                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1664                  * unknown we fail to light up. Yet the same BIOS boots up with
1665                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1666                  * max, not what it tells us to use.
1667                  *
1668                  * Note: This will still be broken if the eDP panel is not lit
1669                  * up by the BIOS, and thus we can't get the mode at module
1670                  * load.
1671                  */
1672                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1673                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1674                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1675         }
1676 }
1677
1678 static bool is_edp_psr(struct intel_dp *intel_dp)
1679 {
1680         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1681 }
1682
1683 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1684 {
1685         struct drm_i915_private *dev_priv = dev->dev_private;
1686
1687         if (!HAS_PSR(dev))
1688                 return false;
1689
1690         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1691 }
1692
1693 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1694                                     struct edp_vsc_psr *vsc_psr)
1695 {
1696         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1697         struct drm_device *dev = dig_port->base.base.dev;
1698         struct drm_i915_private *dev_priv = dev->dev_private;
1699         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1700         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1701         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1702         uint32_t *data = (uint32_t *) vsc_psr;
1703         unsigned int i;
1704
1705         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1706            the video DIP being updated before program video DIP data buffer
1707            registers for DIP being updated. */
1708         I915_WRITE(ctl_reg, 0);
1709         POSTING_READ(ctl_reg);
1710
1711         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1712                 if (i < sizeof(struct edp_vsc_psr))
1713                         I915_WRITE(data_reg + i, *data++);
1714                 else
1715                         I915_WRITE(data_reg + i, 0);
1716         }
1717
1718         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1719         POSTING_READ(ctl_reg);
1720 }
1721
1722 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1723 {
1724         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726         struct edp_vsc_psr psr_vsc;
1727
1728         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1729         memset(&psr_vsc, 0, sizeof(psr_vsc));
1730         psr_vsc.sdp_header.HB0 = 0;
1731         psr_vsc.sdp_header.HB1 = 0x7;
1732         psr_vsc.sdp_header.HB2 = 0x2;
1733         psr_vsc.sdp_header.HB3 = 0x8;
1734         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1735
1736         /* Avoid continuous PSR exit by masking memup and hpd */
1737         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1738                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1739 }
1740
1741 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1742 {
1743         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1744         struct drm_device *dev = dig_port->base.base.dev;
1745         struct drm_i915_private *dev_priv = dev->dev_private;
1746         uint32_t aux_clock_divider;
1747         int precharge = 0x3;
1748         int msg_size = 5;       /* Header(4) + Message(1) */
1749         bool only_standby = false;
1750
1751         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1752
1753         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1754                 only_standby = true;
1755
1756         /* Enable PSR in sink */
1757         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1758                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1759                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1760         else
1761                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1762                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1763
1764         /* Setup AUX registers */
1765         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1766         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1767         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1768                    DP_AUX_CH_CTL_TIME_OUT_400us |
1769                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1770                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1771                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1772 }
1773
1774 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1775 {
1776         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1777         struct drm_device *dev = dig_port->base.base.dev;
1778         struct drm_i915_private *dev_priv = dev->dev_private;
1779         uint32_t max_sleep_time = 0x1f;
1780         uint32_t idle_frames = 1;
1781         uint32_t val = 0x0;
1782         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1783         bool only_standby = false;
1784
1785         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1786                 only_standby = true;
1787
1788         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
1789                 val |= EDP_PSR_LINK_STANDBY;
1790                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1791                 val |= EDP_PSR_TP1_TIME_0us;
1792                 val |= EDP_PSR_SKIP_AUX_EXIT;
1793                 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
1794         } else
1795                 val |= EDP_PSR_LINK_DISABLE;
1796
1797         I915_WRITE(EDP_PSR_CTL(dev), val |
1798                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1799                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1800                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1801                    EDP_PSR_ENABLE);
1802 }
1803
1804 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1805 {
1806         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1807         struct drm_device *dev = dig_port->base.base.dev;
1808         struct drm_i915_private *dev_priv = dev->dev_private;
1809         struct drm_crtc *crtc = dig_port->base.base.crtc;
1810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1811
1812         lockdep_assert_held(&dev_priv->psr.lock);
1813         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1814         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1815
1816         dev_priv->psr.source_ok = false;
1817
1818         if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
1819                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1820                 return false;
1821         }
1822
1823         if (!i915.enable_psr) {
1824                 DRM_DEBUG_KMS("PSR disable by flag\n");
1825                 return false;
1826         }
1827
1828         /* Below limitations aren't valid for Broadwell */
1829         if (IS_BROADWELL(dev))
1830                 goto out;
1831
1832         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1833             S3D_ENABLE) {
1834                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1835                 return false;
1836         }
1837
1838         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1839                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1840                 return false;
1841         }
1842
1843  out:
1844         dev_priv->psr.source_ok = true;
1845         return true;
1846 }
1847
1848 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1849 {
1850         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1851         struct drm_device *dev = intel_dig_port->base.base.dev;
1852         struct drm_i915_private *dev_priv = dev->dev_private;
1853
1854         WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1855         WARN_ON(dev_priv->psr.active);
1856         lockdep_assert_held(&dev_priv->psr.lock);
1857
1858         /* Enable PSR on the panel */
1859         intel_edp_psr_enable_sink(intel_dp);
1860
1861         /* Enable PSR on the host */
1862         intel_edp_psr_enable_source(intel_dp);
1863
1864         dev_priv->psr.active = true;
1865 }
1866
1867 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1868 {
1869         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1870         struct drm_i915_private *dev_priv = dev->dev_private;
1871
1872         if (!HAS_PSR(dev)) {
1873                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1874                 return;
1875         }
1876
1877         if (!is_edp_psr(intel_dp)) {
1878                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1879                 return;
1880         }
1881
1882         mutex_lock(&dev_priv->psr.lock);
1883         if (dev_priv->psr.enabled) {
1884                 DRM_DEBUG_KMS("PSR already in use\n");
1885                 mutex_unlock(&dev_priv->psr.lock);
1886                 return;
1887         }
1888
1889         dev_priv->psr.busy_frontbuffer_bits = 0;
1890
1891         /* Setup PSR once */
1892         intel_edp_psr_setup(intel_dp);
1893
1894         if (intel_edp_psr_match_conditions(intel_dp))
1895                 dev_priv->psr.enabled = intel_dp;
1896         mutex_unlock(&dev_priv->psr.lock);
1897 }
1898
1899 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1900 {
1901         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1902         struct drm_i915_private *dev_priv = dev->dev_private;
1903
1904         mutex_lock(&dev_priv->psr.lock);
1905         if (!dev_priv->psr.enabled) {
1906                 mutex_unlock(&dev_priv->psr.lock);
1907                 return;
1908         }
1909
1910         if (dev_priv->psr.active) {
1911                 I915_WRITE(EDP_PSR_CTL(dev),
1912                            I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1913
1914                 /* Wait till PSR is idle */
1915                 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1916                                EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1917                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
1918
1919                 dev_priv->psr.active = false;
1920         } else {
1921                 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1922         }
1923
1924         dev_priv->psr.enabled = NULL;
1925         mutex_unlock(&dev_priv->psr.lock);
1926
1927         cancel_delayed_work_sync(&dev_priv->psr.work);
1928 }
1929
1930 static void intel_edp_psr_work(struct work_struct *work)
1931 {
1932         struct drm_i915_private *dev_priv =
1933                 container_of(work, typeof(*dev_priv), psr.work.work);
1934         struct intel_dp *intel_dp = dev_priv->psr.enabled;
1935
1936         mutex_lock(&dev_priv->psr.lock);
1937         intel_dp = dev_priv->psr.enabled;
1938
1939         if (!intel_dp)
1940                 goto unlock;
1941
1942         /*
1943          * The delayed work can race with an invalidate hence we need to
1944          * recheck. Since psr_flush first clears this and then reschedules we
1945          * won't ever miss a flush when bailing out here.
1946          */
1947         if (dev_priv->psr.busy_frontbuffer_bits)
1948                 goto unlock;
1949
1950         intel_edp_psr_do_enable(intel_dp);
1951 unlock:
1952         mutex_unlock(&dev_priv->psr.lock);
1953 }
1954
1955 static void intel_edp_psr_do_exit(struct drm_device *dev)
1956 {
1957         struct drm_i915_private *dev_priv = dev->dev_private;
1958
1959         if (dev_priv->psr.active) {
1960                 u32 val = I915_READ(EDP_PSR_CTL(dev));
1961
1962                 WARN_ON(!(val & EDP_PSR_ENABLE));
1963
1964                 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1965
1966                 dev_priv->psr.active = false;
1967         }
1968
1969 }
1970
1971 void intel_edp_psr_invalidate(struct drm_device *dev,
1972                               unsigned frontbuffer_bits)
1973 {
1974         struct drm_i915_private *dev_priv = dev->dev_private;
1975         struct drm_crtc *crtc;
1976         enum pipe pipe;
1977
1978         mutex_lock(&dev_priv->psr.lock);
1979         if (!dev_priv->psr.enabled) {
1980                 mutex_unlock(&dev_priv->psr.lock);
1981                 return;
1982         }
1983
1984         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1985         pipe = to_intel_crtc(crtc)->pipe;
1986
1987         intel_edp_psr_do_exit(dev);
1988
1989         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
1990
1991         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
1992         mutex_unlock(&dev_priv->psr.lock);
1993 }
1994
1995 void intel_edp_psr_flush(struct drm_device *dev,
1996                          unsigned frontbuffer_bits)
1997 {
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999         struct drm_crtc *crtc;
2000         enum pipe pipe;
2001
2002         mutex_lock(&dev_priv->psr.lock);
2003         if (!dev_priv->psr.enabled) {
2004                 mutex_unlock(&dev_priv->psr.lock);
2005                 return;
2006         }
2007
2008         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2009         pipe = to_intel_crtc(crtc)->pipe;
2010         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2011
2012         /*
2013          * On Haswell sprite plane updates don't result in a psr invalidating
2014          * signal in the hardware. Which means we need to manually fake this in
2015          * software for all flushes, not just when we've seen a preceding
2016          * invalidation through frontbuffer rendering.
2017          */
2018         if (IS_HASWELL(dev) &&
2019             (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2020                 intel_edp_psr_do_exit(dev);
2021
2022         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2023                 schedule_delayed_work(&dev_priv->psr.work,
2024                                       msecs_to_jiffies(100));
2025         mutex_unlock(&dev_priv->psr.lock);
2026 }
2027
2028 void intel_edp_psr_init(struct drm_device *dev)
2029 {
2030         struct drm_i915_private *dev_priv = dev->dev_private;
2031
2032         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2033         mutex_init(&dev_priv->psr.lock);
2034 }
2035
2036 static void intel_disable_dp(struct intel_encoder *encoder)
2037 {
2038         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2039         enum port port = dp_to_dig_port(intel_dp)->port;
2040         struct drm_device *dev = encoder->base.dev;
2041
2042         /* Make sure the panel is off before trying to change the mode. But also
2043          * ensure that we have vdd while we switch off the panel. */
2044         intel_edp_panel_vdd_on(intel_dp);
2045         intel_edp_backlight_off(intel_dp);
2046         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2047         intel_edp_panel_off(intel_dp);
2048
2049         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2050         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
2051                 intel_dp_link_down(intel_dp);
2052 }
2053
2054 static void g4x_post_disable_dp(struct intel_encoder *encoder)
2055 {
2056         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2057         enum port port = dp_to_dig_port(intel_dp)->port;
2058
2059         if (port != PORT_A)
2060                 return;
2061
2062         intel_dp_link_down(intel_dp);
2063         ironlake_edp_pll_off(intel_dp);
2064 }
2065
2066 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2067 {
2068         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2069
2070         intel_dp_link_down(intel_dp);
2071 }
2072
2073 static void chv_post_disable_dp(struct intel_encoder *encoder)
2074 {
2075         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2076         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2077         struct drm_device *dev = encoder->base.dev;
2078         struct drm_i915_private *dev_priv = dev->dev_private;
2079         struct intel_crtc *intel_crtc =
2080                 to_intel_crtc(encoder->base.crtc);
2081         enum dpio_channel ch = vlv_dport_to_channel(dport);
2082         enum pipe pipe = intel_crtc->pipe;
2083         u32 val;
2084
2085         intel_dp_link_down(intel_dp);
2086
2087         mutex_lock(&dev_priv->dpio_lock);
2088
2089         /* Propagate soft reset to data lane reset */
2090         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2091         val |= CHV_PCS_REQ_SOFTRESET_EN;
2092         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2093
2094         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2095         val |= CHV_PCS_REQ_SOFTRESET_EN;
2096         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2097
2098         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2099         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2100         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2101
2102         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2103         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2104         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2105
2106         mutex_unlock(&dev_priv->dpio_lock);
2107 }
2108
2109 static void intel_enable_dp(struct intel_encoder *encoder)
2110 {
2111         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2112         struct drm_device *dev = encoder->base.dev;
2113         struct drm_i915_private *dev_priv = dev->dev_private;
2114         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2115
2116         if (WARN_ON(dp_reg & DP_PORT_EN))
2117                 return;
2118
2119         intel_edp_panel_vdd_on(intel_dp);
2120         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2121         intel_dp_start_link_train(intel_dp);
2122         intel_edp_panel_on(intel_dp);
2123         edp_panel_vdd_off(intel_dp, true);
2124         intel_dp_complete_link_train(intel_dp);
2125         intel_dp_stop_link_train(intel_dp);
2126 }
2127
2128 static void g4x_enable_dp(struct intel_encoder *encoder)
2129 {
2130         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2131
2132         intel_enable_dp(encoder);
2133         intel_edp_backlight_on(intel_dp);
2134 }
2135
2136 static void vlv_enable_dp(struct intel_encoder *encoder)
2137 {
2138         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2139
2140         intel_edp_backlight_on(intel_dp);
2141 }
2142
2143 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2144 {
2145         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2146         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2147
2148         intel_dp_prepare(encoder);
2149
2150         /* Only ilk+ has port A */
2151         if (dport->port == PORT_A) {
2152                 ironlake_set_pll_cpu_edp(intel_dp);
2153                 ironlake_edp_pll_on(intel_dp);
2154         }
2155 }
2156
2157 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2158 {
2159         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2160         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2161         struct drm_device *dev = encoder->base.dev;
2162         struct drm_i915_private *dev_priv = dev->dev_private;
2163         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2164         enum dpio_channel port = vlv_dport_to_channel(dport);
2165         int pipe = intel_crtc->pipe;
2166         struct edp_power_seq power_seq;
2167         u32 val;
2168
2169         mutex_lock(&dev_priv->dpio_lock);
2170
2171         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2172         val = 0;
2173         if (pipe)
2174                 val |= (1<<21);
2175         else
2176                 val &= ~(1<<21);
2177         val |= 0x001000c4;
2178         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2179         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2180         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2181
2182         mutex_unlock(&dev_priv->dpio_lock);
2183
2184         if (is_edp(intel_dp)) {
2185                 /* init power sequencer on this pipe and port */
2186                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2187                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2188                                                               &power_seq);
2189         }
2190
2191         intel_enable_dp(encoder);
2192
2193         vlv_wait_port_ready(dev_priv, dport);
2194 }
2195
2196 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2197 {
2198         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2199         struct drm_device *dev = encoder->base.dev;
2200         struct drm_i915_private *dev_priv = dev->dev_private;
2201         struct intel_crtc *intel_crtc =
2202                 to_intel_crtc(encoder->base.crtc);
2203         enum dpio_channel port = vlv_dport_to_channel(dport);
2204         int pipe = intel_crtc->pipe;
2205
2206         intel_dp_prepare(encoder);
2207
2208         /* Program Tx lane resets to default */
2209         mutex_lock(&dev_priv->dpio_lock);
2210         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2211                          DPIO_PCS_TX_LANE2_RESET |
2212                          DPIO_PCS_TX_LANE1_RESET);
2213         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2214                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2215                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2216                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2217                                  DPIO_PCS_CLK_SOFT_RESET);
2218
2219         /* Fix up inter-pair skew failure */
2220         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2221         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2222         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2223         mutex_unlock(&dev_priv->dpio_lock);
2224 }
2225
2226 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2227 {
2228         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2229         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2230         struct drm_device *dev = encoder->base.dev;
2231         struct drm_i915_private *dev_priv = dev->dev_private;
2232         struct edp_power_seq power_seq;
2233         struct intel_crtc *intel_crtc =
2234                 to_intel_crtc(encoder->base.crtc);
2235         enum dpio_channel ch = vlv_dport_to_channel(dport);
2236         int pipe = intel_crtc->pipe;
2237         int data, i;
2238         u32 val;
2239
2240         mutex_lock(&dev_priv->dpio_lock);
2241
2242         /* Deassert soft data lane reset*/
2243         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2244         val |= CHV_PCS_REQ_SOFTRESET_EN;
2245         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2246
2247         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2248         val |= CHV_PCS_REQ_SOFTRESET_EN;
2249         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2250
2251         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2252         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2253         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2254
2255         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2256         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2257         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2258
2259         /* Program Tx lane latency optimal setting*/
2260         for (i = 0; i < 4; i++) {
2261                 /* Set the latency optimal bit */
2262                 data = (i == 1) ? 0x0 : 0x6;
2263                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2264                                 data << DPIO_FRC_LATENCY_SHFIT);
2265
2266                 /* Set the upar bit */
2267                 data = (i == 1) ? 0x0 : 0x1;
2268                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2269                                 data << DPIO_UPAR_SHIFT);
2270         }
2271
2272         /* Data lane stagger programming */
2273         /* FIXME: Fix up value only after power analysis */
2274
2275         mutex_unlock(&dev_priv->dpio_lock);
2276
2277         if (is_edp(intel_dp)) {
2278                 /* init power sequencer on this pipe and port */
2279                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2280                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2281                                                               &power_seq);
2282         }
2283
2284         intel_enable_dp(encoder);
2285
2286         vlv_wait_port_ready(dev_priv, dport);
2287 }
2288
2289 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2290 {
2291         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2292         struct drm_device *dev = encoder->base.dev;
2293         struct drm_i915_private *dev_priv = dev->dev_private;
2294         struct intel_crtc *intel_crtc =
2295                 to_intel_crtc(encoder->base.crtc);
2296         enum dpio_channel ch = vlv_dport_to_channel(dport);
2297         enum pipe pipe = intel_crtc->pipe;
2298         u32 val;
2299
2300         mutex_lock(&dev_priv->dpio_lock);
2301
2302         /* program left/right clock distribution */
2303         if (pipe != PIPE_B) {
2304                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2305                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2306                 if (ch == DPIO_CH0)
2307                         val |= CHV_BUFLEFTENA1_FORCE;
2308                 if (ch == DPIO_CH1)
2309                         val |= CHV_BUFRIGHTENA1_FORCE;
2310                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2311         } else {
2312                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2313                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2314                 if (ch == DPIO_CH0)
2315                         val |= CHV_BUFLEFTENA2_FORCE;
2316                 if (ch == DPIO_CH1)
2317                         val |= CHV_BUFRIGHTENA2_FORCE;
2318                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2319         }
2320
2321         /* program clock channel usage */
2322         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2323         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2324         if (pipe != PIPE_B)
2325                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2326         else
2327                 val |= CHV_PCS_USEDCLKCHANNEL;
2328         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2329
2330         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2331         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2332         if (pipe != PIPE_B)
2333                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2334         else
2335                 val |= CHV_PCS_USEDCLKCHANNEL;
2336         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2337
2338         /*
2339          * This a a bit weird since generally CL
2340          * matches the pipe, but here we need to
2341          * pick the CL based on the port.
2342          */
2343         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2344         if (pipe != PIPE_B)
2345                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2346         else
2347                 val |= CHV_CMN_USEDCLKCHANNEL;
2348         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2349
2350         mutex_unlock(&dev_priv->dpio_lock);
2351 }
2352
2353 /*
2354  * Native read with retry for link status and receiver capability reads for
2355  * cases where the sink may still be asleep.
2356  *
2357  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2358  * supposed to retry 3 times per the spec.
2359  */
2360 static ssize_t
2361 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2362                         void *buffer, size_t size)
2363 {
2364         ssize_t ret;
2365         int i;
2366
2367         for (i = 0; i < 3; i++) {
2368                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2369                 if (ret == size)
2370                         return ret;
2371                 msleep(1);
2372         }
2373
2374         return ret;
2375 }
2376
2377 /*
2378  * Fetch AUX CH registers 0x202 - 0x207 which contain
2379  * link status information
2380  */
2381 static bool
2382 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2383 {
2384         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2385                                        DP_LANE0_1_STATUS,
2386                                        link_status,
2387                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2388 }
2389
2390 /* These are source-specific values. */
2391 static uint8_t
2392 intel_dp_voltage_max(struct intel_dp *intel_dp)
2393 {
2394         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2395         enum port port = dp_to_dig_port(intel_dp)->port;
2396
2397         if (IS_VALLEYVIEW(dev))
2398                 return DP_TRAIN_VOLTAGE_SWING_1200;
2399         else if (IS_GEN7(dev) && port == PORT_A)
2400                 return DP_TRAIN_VOLTAGE_SWING_800;
2401         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2402                 return DP_TRAIN_VOLTAGE_SWING_1200;
2403         else
2404                 return DP_TRAIN_VOLTAGE_SWING_800;
2405 }
2406
2407 static uint8_t
2408 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2409 {
2410         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2411         enum port port = dp_to_dig_port(intel_dp)->port;
2412
2413         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2414                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2415                 case DP_TRAIN_VOLTAGE_SWING_400:
2416                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2417                 case DP_TRAIN_VOLTAGE_SWING_600:
2418                         return DP_TRAIN_PRE_EMPHASIS_6;
2419                 case DP_TRAIN_VOLTAGE_SWING_800:
2420                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2421                 case DP_TRAIN_VOLTAGE_SWING_1200:
2422                 default:
2423                         return DP_TRAIN_PRE_EMPHASIS_0;
2424                 }
2425         } else if (IS_VALLEYVIEW(dev)) {
2426                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2427                 case DP_TRAIN_VOLTAGE_SWING_400:
2428                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2429                 case DP_TRAIN_VOLTAGE_SWING_600:
2430                         return DP_TRAIN_PRE_EMPHASIS_6;
2431                 case DP_TRAIN_VOLTAGE_SWING_800:
2432                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2433                 case DP_TRAIN_VOLTAGE_SWING_1200:
2434                 default:
2435                         return DP_TRAIN_PRE_EMPHASIS_0;
2436                 }
2437         } else if (IS_GEN7(dev) && port == PORT_A) {
2438                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2439                 case DP_TRAIN_VOLTAGE_SWING_400:
2440                         return DP_TRAIN_PRE_EMPHASIS_6;
2441                 case DP_TRAIN_VOLTAGE_SWING_600:
2442                 case DP_TRAIN_VOLTAGE_SWING_800:
2443                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2444                 default:
2445                         return DP_TRAIN_PRE_EMPHASIS_0;
2446                 }
2447         } else {
2448                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2449                 case DP_TRAIN_VOLTAGE_SWING_400:
2450                         return DP_TRAIN_PRE_EMPHASIS_6;
2451                 case DP_TRAIN_VOLTAGE_SWING_600:
2452                         return DP_TRAIN_PRE_EMPHASIS_6;
2453                 case DP_TRAIN_VOLTAGE_SWING_800:
2454                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2455                 case DP_TRAIN_VOLTAGE_SWING_1200:
2456                 default:
2457                         return DP_TRAIN_PRE_EMPHASIS_0;
2458                 }
2459         }
2460 }
2461
2462 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2463 {
2464         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2465         struct drm_i915_private *dev_priv = dev->dev_private;
2466         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2467         struct intel_crtc *intel_crtc =
2468                 to_intel_crtc(dport->base.base.crtc);
2469         unsigned long demph_reg_value, preemph_reg_value,
2470                 uniqtranscale_reg_value;
2471         uint8_t train_set = intel_dp->train_set[0];
2472         enum dpio_channel port = vlv_dport_to_channel(dport);
2473         int pipe = intel_crtc->pipe;
2474
2475         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2476         case DP_TRAIN_PRE_EMPHASIS_0:
2477                 preemph_reg_value = 0x0004000;
2478                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2479                 case DP_TRAIN_VOLTAGE_SWING_400:
2480                         demph_reg_value = 0x2B405555;
2481                         uniqtranscale_reg_value = 0x552AB83A;
2482                         break;
2483                 case DP_TRAIN_VOLTAGE_SWING_600:
2484                         demph_reg_value = 0x2B404040;
2485                         uniqtranscale_reg_value = 0x5548B83A;
2486                         break;
2487                 case DP_TRAIN_VOLTAGE_SWING_800:
2488                         demph_reg_value = 0x2B245555;
2489                         uniqtranscale_reg_value = 0x5560B83A;
2490                         break;
2491                 case DP_TRAIN_VOLTAGE_SWING_1200:
2492                         demph_reg_value = 0x2B405555;
2493                         uniqtranscale_reg_value = 0x5598DA3A;
2494                         break;
2495                 default:
2496                         return 0;
2497                 }
2498                 break;
2499         case DP_TRAIN_PRE_EMPHASIS_3_5:
2500                 preemph_reg_value = 0x0002000;
2501                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2502                 case DP_TRAIN_VOLTAGE_SWING_400:
2503                         demph_reg_value = 0x2B404040;
2504                         uniqtranscale_reg_value = 0x5552B83A;
2505                         break;
2506                 case DP_TRAIN_VOLTAGE_SWING_600:
2507                         demph_reg_value = 0x2B404848;
2508                         uniqtranscale_reg_value = 0x5580B83A;
2509                         break;
2510                 case DP_TRAIN_VOLTAGE_SWING_800:
2511                         demph_reg_value = 0x2B404040;
2512                         uniqtranscale_reg_value = 0x55ADDA3A;
2513                         break;
2514                 default:
2515                         return 0;
2516                 }
2517                 break;
2518         case DP_TRAIN_PRE_EMPHASIS_6:
2519                 preemph_reg_value = 0x0000000;
2520                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2521                 case DP_TRAIN_VOLTAGE_SWING_400:
2522                         demph_reg_value = 0x2B305555;
2523                         uniqtranscale_reg_value = 0x5570B83A;
2524                         break;
2525                 case DP_TRAIN_VOLTAGE_SWING_600:
2526                         demph_reg_value = 0x2B2B4040;
2527                         uniqtranscale_reg_value = 0x55ADDA3A;
2528                         break;
2529                 default:
2530                         return 0;
2531                 }
2532                 break;
2533         case DP_TRAIN_PRE_EMPHASIS_9_5:
2534                 preemph_reg_value = 0x0006000;
2535                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2536                 case DP_TRAIN_VOLTAGE_SWING_400:
2537                         demph_reg_value = 0x1B405555;
2538                         uniqtranscale_reg_value = 0x55ADDA3A;
2539                         break;
2540                 default:
2541                         return 0;
2542                 }
2543                 break;
2544         default:
2545                 return 0;
2546         }
2547
2548         mutex_lock(&dev_priv->dpio_lock);
2549         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2550         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2551         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2552                          uniqtranscale_reg_value);
2553         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2554         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2555         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2556         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2557         mutex_unlock(&dev_priv->dpio_lock);
2558
2559         return 0;
2560 }
2561
2562 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2563 {
2564         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2565         struct drm_i915_private *dev_priv = dev->dev_private;
2566         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2567         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2568         u32 deemph_reg_value, margin_reg_value, val;
2569         uint8_t train_set = intel_dp->train_set[0];
2570         enum dpio_channel ch = vlv_dport_to_channel(dport);
2571         enum pipe pipe = intel_crtc->pipe;
2572         int i;
2573
2574         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2575         case DP_TRAIN_PRE_EMPHASIS_0:
2576                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2577                 case DP_TRAIN_VOLTAGE_SWING_400:
2578                         deemph_reg_value = 128;
2579                         margin_reg_value = 52;
2580                         break;
2581                 case DP_TRAIN_VOLTAGE_SWING_600:
2582                         deemph_reg_value = 128;
2583                         margin_reg_value = 77;
2584                         break;
2585                 case DP_TRAIN_VOLTAGE_SWING_800:
2586                         deemph_reg_value = 128;
2587                         margin_reg_value = 102;
2588                         break;
2589                 case DP_TRAIN_VOLTAGE_SWING_1200:
2590                         deemph_reg_value = 128;
2591                         margin_reg_value = 154;
2592                         /* FIXME extra to set for 1200 */
2593                         break;
2594                 default:
2595                         return 0;
2596                 }
2597                 break;
2598         case DP_TRAIN_PRE_EMPHASIS_3_5:
2599                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2600                 case DP_TRAIN_VOLTAGE_SWING_400:
2601                         deemph_reg_value = 85;
2602                         margin_reg_value = 78;
2603                         break;
2604                 case DP_TRAIN_VOLTAGE_SWING_600:
2605                         deemph_reg_value = 85;
2606                         margin_reg_value = 116;
2607                         break;
2608                 case DP_TRAIN_VOLTAGE_SWING_800:
2609                         deemph_reg_value = 85;
2610                         margin_reg_value = 154;
2611                         break;
2612                 default:
2613                         return 0;
2614                 }
2615                 break;
2616         case DP_TRAIN_PRE_EMPHASIS_6:
2617                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2618                 case DP_TRAIN_VOLTAGE_SWING_400:
2619                         deemph_reg_value = 64;
2620                         margin_reg_value = 104;
2621                         break;
2622                 case DP_TRAIN_VOLTAGE_SWING_600:
2623                         deemph_reg_value = 64;
2624                         margin_reg_value = 154;
2625                         break;
2626                 default:
2627                         return 0;
2628                 }
2629                 break;
2630         case DP_TRAIN_PRE_EMPHASIS_9_5:
2631                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2632                 case DP_TRAIN_VOLTAGE_SWING_400:
2633                         deemph_reg_value = 43;
2634                         margin_reg_value = 154;
2635                         break;
2636                 default:
2637                         return 0;
2638                 }
2639                 break;
2640         default:
2641                 return 0;
2642         }
2643
2644         mutex_lock(&dev_priv->dpio_lock);
2645
2646         /* Clear calc init */
2647         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2648         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2649         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2650
2651         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2652         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2653         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2654
2655         /* Program swing deemph */
2656         for (i = 0; i < 4; i++) {
2657                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2658                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2659                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2660                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2661         }
2662
2663         /* Program swing margin */
2664         for (i = 0; i < 4; i++) {
2665                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2666                 val &= ~DPIO_SWING_MARGIN_MASK;
2667                 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2668                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2669         }
2670
2671         /* Disable unique transition scale */
2672         for (i = 0; i < 4; i++) {
2673                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2674                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2675                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2676         }
2677
2678         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2679                         == DP_TRAIN_PRE_EMPHASIS_0) &&
2680                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2681                         == DP_TRAIN_VOLTAGE_SWING_1200)) {
2682
2683                 /*
2684                  * The document said it needs to set bit 27 for ch0 and bit 26
2685                  * for ch1. Might be a typo in the doc.
2686                  * For now, for this unique transition scale selection, set bit
2687                  * 27 for ch0 and ch1.
2688                  */
2689                 for (i = 0; i < 4; i++) {
2690                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2691                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2692                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2693                 }
2694
2695                 for (i = 0; i < 4; i++) {
2696                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2697                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2698                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2699                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2700                 }
2701         }
2702
2703         /* Start swing calculation */
2704         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2705         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2706         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2707
2708         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2709         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2710         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2711
2712         /* LRC Bypass */
2713         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2714         val |= DPIO_LRC_BYPASS;
2715         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2716
2717         mutex_unlock(&dev_priv->dpio_lock);
2718
2719         return 0;
2720 }
2721
2722 static void
2723 intel_get_adjust_train(struct intel_dp *intel_dp,
2724                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2725 {
2726         uint8_t v = 0;
2727         uint8_t p = 0;
2728         int lane;
2729         uint8_t voltage_max;
2730         uint8_t preemph_max;
2731
2732         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2733                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2734                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2735
2736                 if (this_v > v)
2737                         v = this_v;
2738                 if (this_p > p)
2739                         p = this_p;
2740         }
2741
2742         voltage_max = intel_dp_voltage_max(intel_dp);
2743         if (v >= voltage_max)
2744                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2745
2746         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2747         if (p >= preemph_max)
2748                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2749
2750         for (lane = 0; lane < 4; lane++)
2751                 intel_dp->train_set[lane] = v | p;
2752 }
2753
2754 static uint32_t
2755 intel_gen4_signal_levels(uint8_t train_set)
2756 {
2757         uint32_t        signal_levels = 0;
2758
2759         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2760         case DP_TRAIN_VOLTAGE_SWING_400:
2761         default:
2762                 signal_levels |= DP_VOLTAGE_0_4;
2763                 break;
2764         case DP_TRAIN_VOLTAGE_SWING_600:
2765                 signal_levels |= DP_VOLTAGE_0_6;
2766                 break;
2767         case DP_TRAIN_VOLTAGE_SWING_800:
2768                 signal_levels |= DP_VOLTAGE_0_8;
2769                 break;
2770         case DP_TRAIN_VOLTAGE_SWING_1200:
2771                 signal_levels |= DP_VOLTAGE_1_2;
2772                 break;
2773         }
2774         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2775         case DP_TRAIN_PRE_EMPHASIS_0:
2776         default:
2777                 signal_levels |= DP_PRE_EMPHASIS_0;
2778                 break;
2779         case DP_TRAIN_PRE_EMPHASIS_3_5:
2780                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2781                 break;
2782         case DP_TRAIN_PRE_EMPHASIS_6:
2783                 signal_levels |= DP_PRE_EMPHASIS_6;
2784                 break;
2785         case DP_TRAIN_PRE_EMPHASIS_9_5:
2786                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2787                 break;
2788         }
2789         return signal_levels;
2790 }
2791
2792 /* Gen6's DP voltage swing and pre-emphasis control */
2793 static uint32_t
2794 intel_gen6_edp_signal_levels(uint8_t train_set)
2795 {
2796         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2797                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2798         switch (signal_levels) {
2799         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2800         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2801                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2802         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2803                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2804         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2805         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2806                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2807         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2808         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2809                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2810         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2811         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2812                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2813         default:
2814                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2815                               "0x%x\n", signal_levels);
2816                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2817         }
2818 }
2819
2820 /* Gen7's DP voltage swing and pre-emphasis control */
2821 static uint32_t
2822 intel_gen7_edp_signal_levels(uint8_t train_set)
2823 {
2824         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2825                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2826         switch (signal_levels) {
2827         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2828                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2829         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2830                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2831         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2832                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2833
2834         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2835                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2836         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2837                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2838
2839         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2840                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2841         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2842                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2843
2844         default:
2845                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2846                               "0x%x\n", signal_levels);
2847                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2848         }
2849 }
2850
2851 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2852 static uint32_t
2853 intel_hsw_signal_levels(uint8_t train_set)
2854 {
2855         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2856                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2857         switch (signal_levels) {
2858         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2859                 return DDI_BUF_EMP_400MV_0DB_HSW;
2860         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2861                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2862         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2863                 return DDI_BUF_EMP_400MV_6DB_HSW;
2864         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2865                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2866
2867         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2868                 return DDI_BUF_EMP_600MV_0DB_HSW;
2869         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2870                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2871         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2872                 return DDI_BUF_EMP_600MV_6DB_HSW;
2873
2874         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2875                 return DDI_BUF_EMP_800MV_0DB_HSW;
2876         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2877                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2878         default:
2879                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2880                               "0x%x\n", signal_levels);
2881                 return DDI_BUF_EMP_400MV_0DB_HSW;
2882         }
2883 }
2884
2885 /* Properly updates "DP" with the correct signal levels. */
2886 static void
2887 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2888 {
2889         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2890         enum port port = intel_dig_port->port;
2891         struct drm_device *dev = intel_dig_port->base.base.dev;
2892         uint32_t signal_levels, mask;
2893         uint8_t train_set = intel_dp->train_set[0];
2894
2895         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2896                 signal_levels = intel_hsw_signal_levels(train_set);
2897                 mask = DDI_BUF_EMP_MASK;
2898         } else if (IS_CHERRYVIEW(dev)) {
2899                 signal_levels = intel_chv_signal_levels(intel_dp);
2900                 mask = 0;
2901         } else if (IS_VALLEYVIEW(dev)) {
2902                 signal_levels = intel_vlv_signal_levels(intel_dp);
2903                 mask = 0;
2904         } else if (IS_GEN7(dev) && port == PORT_A) {
2905                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2906                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2907         } else if (IS_GEN6(dev) && port == PORT_A) {
2908                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2909                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2910         } else {
2911                 signal_levels = intel_gen4_signal_levels(train_set);
2912                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2913         }
2914
2915         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2916
2917         *DP = (*DP & ~mask) | signal_levels;
2918 }
2919
2920 static bool
2921 intel_dp_set_link_train(struct intel_dp *intel_dp,
2922                         uint32_t *DP,
2923                         uint8_t dp_train_pat)
2924 {
2925         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2926         struct drm_device *dev = intel_dig_port->base.base.dev;
2927         struct drm_i915_private *dev_priv = dev->dev_private;
2928         enum port port = intel_dig_port->port;
2929         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2930         int ret, len;
2931
2932         if (HAS_DDI(dev)) {
2933                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2934
2935                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2936                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2937                 else
2938                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2939
2940                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2941                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2942                 case DP_TRAINING_PATTERN_DISABLE:
2943                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2944
2945                         break;
2946                 case DP_TRAINING_PATTERN_1:
2947                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2948                         break;
2949                 case DP_TRAINING_PATTERN_2:
2950                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2951                         break;
2952                 case DP_TRAINING_PATTERN_3:
2953                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2954                         break;
2955                 }
2956                 I915_WRITE(DP_TP_CTL(port), temp);
2957
2958         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2959                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2960
2961                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2962                 case DP_TRAINING_PATTERN_DISABLE:
2963                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2964                         break;
2965                 case DP_TRAINING_PATTERN_1:
2966                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2967                         break;
2968                 case DP_TRAINING_PATTERN_2:
2969                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2970                         break;
2971                 case DP_TRAINING_PATTERN_3:
2972                         DRM_ERROR("DP training pattern 3 not supported\n");
2973                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2974                         break;
2975                 }
2976
2977         } else {
2978                 *DP &= ~DP_LINK_TRAIN_MASK;
2979
2980                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2981                 case DP_TRAINING_PATTERN_DISABLE:
2982                         *DP |= DP_LINK_TRAIN_OFF;
2983                         break;
2984                 case DP_TRAINING_PATTERN_1:
2985                         *DP |= DP_LINK_TRAIN_PAT_1;
2986                         break;
2987                 case DP_TRAINING_PATTERN_2:
2988                         *DP |= DP_LINK_TRAIN_PAT_2;
2989                         break;
2990                 case DP_TRAINING_PATTERN_3:
2991                         DRM_ERROR("DP training pattern 3 not supported\n");
2992                         *DP |= DP_LINK_TRAIN_PAT_2;
2993                         break;
2994                 }
2995         }
2996
2997         I915_WRITE(intel_dp->output_reg, *DP);
2998         POSTING_READ(intel_dp->output_reg);
2999
3000         buf[0] = dp_train_pat;
3001         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3002             DP_TRAINING_PATTERN_DISABLE) {
3003                 /* don't write DP_TRAINING_LANEx_SET on disable */
3004                 len = 1;
3005         } else {
3006                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3007                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3008                 len = intel_dp->lane_count + 1;
3009         }
3010
3011         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3012                                 buf, len);
3013
3014         return ret == len;
3015 }
3016
3017 static bool
3018 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3019                         uint8_t dp_train_pat)
3020 {
3021         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3022         intel_dp_set_signal_levels(intel_dp, DP);
3023         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3024 }
3025
3026 static bool
3027 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3028                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3029 {
3030         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3031         struct drm_device *dev = intel_dig_port->base.base.dev;
3032         struct drm_i915_private *dev_priv = dev->dev_private;
3033         int ret;
3034
3035         intel_get_adjust_train(intel_dp, link_status);
3036         intel_dp_set_signal_levels(intel_dp, DP);
3037
3038         I915_WRITE(intel_dp->output_reg, *DP);
3039         POSTING_READ(intel_dp->output_reg);
3040
3041         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3042                                 intel_dp->train_set, intel_dp->lane_count);
3043
3044         return ret == intel_dp->lane_count;
3045 }
3046
3047 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3048 {
3049         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3050         struct drm_device *dev = intel_dig_port->base.base.dev;
3051         struct drm_i915_private *dev_priv = dev->dev_private;
3052         enum port port = intel_dig_port->port;
3053         uint32_t val;
3054
3055         if (!HAS_DDI(dev))
3056                 return;
3057
3058         val = I915_READ(DP_TP_CTL(port));
3059         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3060         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3061         I915_WRITE(DP_TP_CTL(port), val);
3062
3063         /*
3064          * On PORT_A we can have only eDP in SST mode. There the only reason
3065          * we need to set idle transmission mode is to work around a HW issue
3066          * where we enable the pipe while not in idle link-training mode.
3067          * In this case there is requirement to wait for a minimum number of
3068          * idle patterns to be sent.
3069          */
3070         if (port == PORT_A)
3071                 return;
3072
3073         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3074                      1))
3075                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3076 }
3077
3078 /* Enable corresponding port and start training pattern 1 */
3079 void
3080 intel_dp_start_link_train(struct intel_dp *intel_dp)
3081 {
3082         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3083         struct drm_device *dev = encoder->dev;
3084         int i;
3085         uint8_t voltage;
3086         int voltage_tries, loop_tries;
3087         uint32_t DP = intel_dp->DP;
3088         uint8_t link_config[2];
3089
3090         if (HAS_DDI(dev))
3091                 intel_ddi_prepare_link_retrain(encoder);
3092
3093         /* Write the link configuration data */
3094         link_config[0] = intel_dp->link_bw;
3095         link_config[1] = intel_dp->lane_count;
3096         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3097                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3098         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3099
3100         link_config[0] = 0;
3101         link_config[1] = DP_SET_ANSI_8B10B;
3102         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3103
3104         DP |= DP_PORT_EN;
3105
3106         /* clock recovery */
3107         if (!intel_dp_reset_link_train(intel_dp, &DP,
3108                                        DP_TRAINING_PATTERN_1 |
3109                                        DP_LINK_SCRAMBLING_DISABLE)) {
3110                 DRM_ERROR("failed to enable link training\n");
3111                 return;
3112         }
3113
3114         voltage = 0xff;
3115         voltage_tries = 0;
3116         loop_tries = 0;
3117         for (;;) {
3118                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3119
3120                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3121                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3122                         DRM_ERROR("failed to get link status\n");
3123                         break;
3124                 }
3125
3126                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3127                         DRM_DEBUG_KMS("clock recovery OK\n");
3128                         break;
3129                 }
3130
3131                 /* Check to see if we've tried the max voltage */
3132                 for (i = 0; i < intel_dp->lane_count; i++)
3133                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3134                                 break;
3135                 if (i == intel_dp->lane_count) {
3136                         ++loop_tries;
3137                         if (loop_tries == 5) {
3138                                 DRM_ERROR("too many full retries, give up\n");
3139                                 break;
3140                         }
3141                         intel_dp_reset_link_train(intel_dp, &DP,
3142                                                   DP_TRAINING_PATTERN_1 |
3143                                                   DP_LINK_SCRAMBLING_DISABLE);
3144                         voltage_tries = 0;
3145                         continue;
3146                 }
3147
3148                 /* Check to see if we've tried the same voltage 5 times */
3149                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3150                         ++voltage_tries;
3151                         if (voltage_tries == 5) {
3152                                 DRM_ERROR("too many voltage retries, give up\n");
3153                                 break;
3154                         }
3155                 } else
3156                         voltage_tries = 0;
3157                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3158
3159                 /* Update training set as requested by target */
3160                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3161                         DRM_ERROR("failed to update link training\n");
3162                         break;
3163                 }
3164         }
3165
3166         intel_dp->DP = DP;
3167 }
3168
3169 void
3170 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3171 {
3172         bool channel_eq = false;
3173         int tries, cr_tries;
3174         uint32_t DP = intel_dp->DP;
3175         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3176
3177         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3178         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3179                 training_pattern = DP_TRAINING_PATTERN_3;
3180
3181         /* channel equalization */
3182         if (!intel_dp_set_link_train(intel_dp, &DP,
3183                                      training_pattern |
3184                                      DP_LINK_SCRAMBLING_DISABLE)) {
3185                 DRM_ERROR("failed to start channel equalization\n");
3186                 return;
3187         }
3188
3189         tries = 0;
3190         cr_tries = 0;
3191         channel_eq = false;
3192         for (;;) {
3193                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3194
3195                 if (cr_tries > 5) {
3196                         DRM_ERROR("failed to train DP, aborting\n");
3197                         break;
3198                 }
3199
3200                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3201                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3202                         DRM_ERROR("failed to get link status\n");
3203                         break;
3204                 }
3205
3206                 /* Make sure clock is still ok */
3207                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3208                         intel_dp_start_link_train(intel_dp);
3209                         intel_dp_set_link_train(intel_dp, &DP,
3210                                                 training_pattern |
3211                                                 DP_LINK_SCRAMBLING_DISABLE);
3212                         cr_tries++;
3213                         continue;
3214                 }
3215
3216                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3217                         channel_eq = true;
3218                         break;
3219                 }
3220
3221                 /* Try 5 times, then try clock recovery if that fails */
3222                 if (tries > 5) {
3223                         intel_dp_link_down(intel_dp);
3224                         intel_dp_start_link_train(intel_dp);
3225                         intel_dp_set_link_train(intel_dp, &DP,
3226                                                 training_pattern |
3227                                                 DP_LINK_SCRAMBLING_DISABLE);
3228                         tries = 0;
3229                         cr_tries++;
3230                         continue;
3231                 }
3232
3233                 /* Update training set as requested by target */
3234                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3235                         DRM_ERROR("failed to update link training\n");
3236                         break;
3237                 }
3238                 ++tries;
3239         }
3240
3241         intel_dp_set_idle_link_train(intel_dp);
3242
3243         intel_dp->DP = DP;
3244
3245         if (channel_eq)
3246                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3247
3248 }
3249
3250 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3251 {
3252         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3253                                 DP_TRAINING_PATTERN_DISABLE);
3254 }
3255
3256 static void
3257 intel_dp_link_down(struct intel_dp *intel_dp)
3258 {
3259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3260         enum port port = intel_dig_port->port;
3261         struct drm_device *dev = intel_dig_port->base.base.dev;
3262         struct drm_i915_private *dev_priv = dev->dev_private;
3263         struct intel_crtc *intel_crtc =
3264                 to_intel_crtc(intel_dig_port->base.base.crtc);
3265         uint32_t DP = intel_dp->DP;
3266
3267         if (WARN_ON(HAS_DDI(dev)))
3268                 return;
3269
3270         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3271                 return;
3272
3273         DRM_DEBUG_KMS("\n");
3274
3275         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3276                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3277                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3278         } else {
3279                 DP &= ~DP_LINK_TRAIN_MASK;
3280                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3281         }
3282         POSTING_READ(intel_dp->output_reg);
3283
3284         if (HAS_PCH_IBX(dev) &&
3285             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3286                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3287
3288                 /* Hardware workaround: leaving our transcoder select
3289                  * set to transcoder B while it's off will prevent the
3290                  * corresponding HDMI output on transcoder A.
3291                  *
3292                  * Combine this with another hardware workaround:
3293                  * transcoder select bit can only be cleared while the
3294                  * port is enabled.
3295                  */
3296                 DP &= ~DP_PIPEB_SELECT;
3297                 I915_WRITE(intel_dp->output_reg, DP);
3298
3299                 /* Changes to enable or select take place the vblank
3300                  * after being written.
3301                  */
3302                 if (WARN_ON(crtc == NULL)) {
3303                         /* We should never try to disable a port without a crtc
3304                          * attached. For paranoia keep the code around for a
3305                          * bit. */
3306                         POSTING_READ(intel_dp->output_reg);
3307                         msleep(50);
3308                 } else
3309                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3310         }
3311
3312         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3313         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3314         POSTING_READ(intel_dp->output_reg);
3315         msleep(intel_dp->panel_power_down_delay);
3316 }
3317
3318 static bool
3319 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3320 {
3321         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3322         struct drm_device *dev = dig_port->base.base.dev;
3323         struct drm_i915_private *dev_priv = dev->dev_private;
3324
3325         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3326
3327         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3328                                     sizeof(intel_dp->dpcd)) < 0)
3329                 return false; /* aux transfer failed */
3330
3331         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3332                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3333         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3334
3335         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3336                 return false; /* DPCD not present */
3337
3338         /* Check if the panel supports PSR */
3339         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3340         if (is_edp(intel_dp)) {
3341                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3342                                         intel_dp->psr_dpcd,
3343                                         sizeof(intel_dp->psr_dpcd));
3344                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3345                         dev_priv->psr.sink_support = true;
3346                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3347                 }
3348         }
3349
3350         /* Training Pattern 3 support */
3351         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3352             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3353                 intel_dp->use_tps3 = true;
3354                 DRM_DEBUG_KMS("Displayport TPS3 supported");
3355         } else
3356                 intel_dp->use_tps3 = false;
3357
3358         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3359               DP_DWN_STRM_PORT_PRESENT))
3360                 return true; /* native DP sink */
3361
3362         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3363                 return true; /* no per-port downstream info */
3364
3365         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3366                                     intel_dp->downstream_ports,
3367                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3368                 return false; /* downstream port status fetch failed */
3369
3370         return true;
3371 }
3372
3373 static void
3374 intel_dp_probe_oui(struct intel_dp *intel_dp)
3375 {
3376         u8 buf[3];
3377
3378         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3379                 return;
3380
3381         intel_edp_panel_vdd_on(intel_dp);
3382
3383         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3384                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3385                               buf[0], buf[1], buf[2]);
3386
3387         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3388                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3389                               buf[0], buf[1], buf[2]);
3390
3391         edp_panel_vdd_off(intel_dp, false);
3392 }
3393
3394 static bool
3395 intel_dp_probe_mst(struct intel_dp *intel_dp)
3396 {
3397         u8 buf[1];
3398
3399         if (!intel_dp->can_mst)
3400                 return false;
3401
3402         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3403                 return false;
3404
3405         _edp_panel_vdd_on(intel_dp);
3406         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3407                 if (buf[0] & DP_MST_CAP) {
3408                         DRM_DEBUG_KMS("Sink is MST capable\n");
3409                         intel_dp->is_mst = true;
3410                 } else {
3411                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3412                         intel_dp->is_mst = false;
3413                 }
3414         }
3415         edp_panel_vdd_off(intel_dp, false);
3416
3417         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3418         return intel_dp->is_mst;
3419 }
3420
3421 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3422 {
3423         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3424         struct drm_device *dev = intel_dig_port->base.base.dev;
3425         struct intel_crtc *intel_crtc =
3426                 to_intel_crtc(intel_dig_port->base.base.crtc);
3427         u8 buf[1];
3428
3429         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3430                 return -EAGAIN;
3431
3432         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3433                 return -ENOTTY;
3434
3435         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3436                                DP_TEST_SINK_START) < 0)
3437                 return -EAGAIN;
3438
3439         /* Wait 2 vblanks to be sure we will have the correct CRC value */
3440         intel_wait_for_vblank(dev, intel_crtc->pipe);
3441         intel_wait_for_vblank(dev, intel_crtc->pipe);
3442
3443         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3444                 return -EAGAIN;
3445
3446         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3447         return 0;
3448 }
3449
3450 static bool
3451 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3452 {
3453         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3454                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3455                                        sink_irq_vector, 1) == 1;
3456 }
3457
3458 static bool
3459 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3460 {
3461         int ret;
3462
3463         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3464                                              DP_SINK_COUNT_ESI,
3465                                              sink_irq_vector, 14);
3466         if (ret != 14)
3467                 return false;
3468
3469         return true;
3470 }
3471
3472 static void
3473 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3474 {
3475         /* NAK by default */
3476         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3477 }
3478
3479 static int
3480 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3481 {
3482         bool bret;
3483
3484         if (intel_dp->is_mst) {
3485                 u8 esi[16] = { 0 };
3486                 int ret = 0;
3487                 int retry;
3488                 bool handled;
3489                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3490 go_again:
3491                 if (bret == true) {
3492
3493                         /* check link status - esi[10] = 0x200c */
3494                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3495                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3496                                 intel_dp_start_link_train(intel_dp);
3497                                 intel_dp_complete_link_train(intel_dp);
3498                                 intel_dp_stop_link_train(intel_dp);
3499                         }
3500
3501                         DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3502                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3503
3504                         if (handled) {
3505                                 for (retry = 0; retry < 3; retry++) {
3506                                         int wret;
3507                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3508                                                                  DP_SINK_COUNT_ESI+1,
3509                                                                  &esi[1], 3);
3510                                         if (wret == 3) {
3511                                                 break;
3512                                         }
3513                                 }
3514
3515                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3516                                 if (bret == true) {
3517                                         DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3518                                         goto go_again;
3519                                 }
3520                         } else
3521                                 ret = 0;
3522
3523                         return ret;
3524                 } else {
3525                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3526                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3527                         intel_dp->is_mst = false;
3528                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3529                         /* send a hotplug event */
3530                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3531                 }
3532         }
3533         return -EINVAL;
3534 }
3535
3536 /*
3537  * According to DP spec
3538  * 5.1.2:
3539  *  1. Read DPCD
3540  *  2. Configure link according to Receiver Capabilities
3541  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3542  *  4. Check link status on receipt of hot-plug interrupt
3543  */
3544 void
3545 intel_dp_check_link_status(struct intel_dp *intel_dp)
3546 {
3547         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3548         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3549         u8 sink_irq_vector;
3550         u8 link_status[DP_LINK_STATUS_SIZE];
3551
3552         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3553
3554         if (!intel_encoder->connectors_active)
3555                 return;
3556
3557         if (WARN_ON(!intel_encoder->base.crtc))
3558                 return;
3559
3560         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3561                 return;
3562
3563         /* Try to read receiver status if the link appears to be up */
3564         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3565                 return;
3566         }
3567
3568         /* Now read the DPCD to see if it's actually running */
3569         if (!intel_dp_get_dpcd(intel_dp)) {
3570                 return;
3571         }
3572
3573         /* Try to read the source of the interrupt */
3574         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3575             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3576                 /* Clear interrupt source */
3577                 drm_dp_dpcd_writeb(&intel_dp->aux,
3578                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3579                                    sink_irq_vector);
3580
3581                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3582                         intel_dp_handle_test_request(intel_dp);
3583                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3584                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3585         }
3586
3587         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3588                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3589                               intel_encoder->base.name);
3590                 intel_dp_start_link_train(intel_dp);
3591                 intel_dp_complete_link_train(intel_dp);
3592                 intel_dp_stop_link_train(intel_dp);
3593         }
3594 }
3595
3596 /* XXX this is probably wrong for multiple downstream ports */
3597 static enum drm_connector_status
3598 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3599 {
3600         uint8_t *dpcd = intel_dp->dpcd;
3601         uint8_t type;
3602
3603         if (!intel_dp_get_dpcd(intel_dp))
3604                 return connector_status_disconnected;
3605
3606         /* if there's no downstream port, we're done */
3607         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3608                 return connector_status_connected;
3609
3610         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3611         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3612             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3613                 uint8_t reg;
3614
3615                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3616                                             &reg, 1) < 0)
3617                         return connector_status_unknown;
3618
3619                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3620                                               : connector_status_disconnected;
3621         }
3622
3623         /* If no HPD, poke DDC gently */
3624         if (drm_probe_ddc(&intel_dp->aux.ddc))
3625                 return connector_status_connected;
3626
3627         /* Well we tried, say unknown for unreliable port types */
3628         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3629                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3630                 if (type == DP_DS_PORT_TYPE_VGA ||
3631                     type == DP_DS_PORT_TYPE_NON_EDID)
3632                         return connector_status_unknown;
3633         } else {
3634                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3635                         DP_DWN_STRM_PORT_TYPE_MASK;
3636                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3637                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3638                         return connector_status_unknown;
3639         }
3640
3641         /* Anything else is out of spec, warn and ignore */
3642         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3643         return connector_status_disconnected;
3644 }
3645
3646 static enum drm_connector_status
3647 ironlake_dp_detect(struct intel_dp *intel_dp)
3648 {
3649         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3650         struct drm_i915_private *dev_priv = dev->dev_private;
3651         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3652         enum drm_connector_status status;
3653
3654         /* Can't disconnect eDP, but you can close the lid... */
3655         if (is_edp(intel_dp)) {
3656                 status = intel_panel_detect(dev);
3657                 if (status == connector_status_unknown)
3658                         status = connector_status_connected;
3659                 return status;
3660         }
3661
3662         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3663                 return connector_status_disconnected;
3664
3665         return intel_dp_detect_dpcd(intel_dp);
3666 }
3667
3668 static int g4x_digital_port_connected(struct drm_device *dev,
3669                                        struct intel_digital_port *intel_dig_port)
3670 {
3671         struct drm_i915_private *dev_priv = dev->dev_private;
3672         uint32_t bit;
3673
3674         if (IS_VALLEYVIEW(dev)) {
3675                 switch (intel_dig_port->port) {
3676                 case PORT_B:
3677                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3678                         break;
3679                 case PORT_C:
3680                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3681                         break;
3682                 case PORT_D:
3683                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3684                         break;
3685                 default:
3686                         return -EINVAL;
3687                 }
3688         } else {
3689                 switch (intel_dig_port->port) {
3690                 case PORT_B:
3691                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3692                         break;
3693                 case PORT_C:
3694                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3695                         break;
3696                 case PORT_D:
3697                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3698                         break;
3699                 default:
3700                         return -EINVAL;
3701                 }
3702         }
3703
3704         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3705                 return 0;
3706         return 1;
3707 }
3708
3709 static enum drm_connector_status
3710 g4x_dp_detect(struct intel_dp *intel_dp)
3711 {
3712         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3713         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3714         int ret;
3715
3716         /* Can't disconnect eDP, but you can close the lid... */
3717         if (is_edp(intel_dp)) {
3718                 enum drm_connector_status status;
3719
3720                 status = intel_panel_detect(dev);
3721                 if (status == connector_status_unknown)
3722                         status = connector_status_connected;
3723                 return status;
3724         }
3725
3726         ret = g4x_digital_port_connected(dev, intel_dig_port);
3727         if (ret == -EINVAL)
3728                 return connector_status_unknown;
3729         else if (ret == 0)
3730                 return connector_status_disconnected;
3731
3732         return intel_dp_detect_dpcd(intel_dp);
3733 }
3734
3735 static struct edid *
3736 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3737 {
3738         struct intel_connector *intel_connector = to_intel_connector(connector);
3739
3740         /* use cached edid if we have one */
3741         if (intel_connector->edid) {
3742                 /* invalid edid */
3743                 if (IS_ERR(intel_connector->edid))
3744                         return NULL;
3745
3746                 return drm_edid_duplicate(intel_connector->edid);
3747         }
3748
3749         return drm_get_edid(connector, adapter);
3750 }
3751
3752 static int
3753 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3754 {
3755         struct intel_connector *intel_connector = to_intel_connector(connector);
3756
3757         /* use cached edid if we have one */
3758         if (intel_connector->edid) {
3759                 /* invalid edid */
3760                 if (IS_ERR(intel_connector->edid))
3761                         return 0;
3762
3763                 return intel_connector_update_modes(connector,
3764                                                     intel_connector->edid);
3765         }
3766
3767         return intel_ddc_get_modes(connector, adapter);
3768 }
3769
3770 static enum drm_connector_status
3771 intel_dp_detect(struct drm_connector *connector, bool force)
3772 {
3773         struct intel_dp *intel_dp = intel_attached_dp(connector);
3774         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3775         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3776         struct drm_device *dev = connector->dev;
3777         struct drm_i915_private *dev_priv = dev->dev_private;
3778         enum drm_connector_status status;
3779         enum intel_display_power_domain power_domain;
3780         struct edid *edid = NULL;
3781         bool ret;
3782
3783         power_domain = intel_display_port_power_domain(intel_encoder);
3784         intel_display_power_get(dev_priv, power_domain);
3785
3786         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3787                       connector->base.id, connector->name);
3788
3789         if (intel_dp->is_mst) {
3790                 /* MST devices are disconnected from a monitor POV */
3791                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3792                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3793                 status = connector_status_disconnected;
3794                 goto out;
3795         }
3796
3797         intel_dp->has_audio = false;
3798
3799         if (HAS_PCH_SPLIT(dev))
3800                 status = ironlake_dp_detect(intel_dp);
3801         else
3802                 status = g4x_dp_detect(intel_dp);
3803
3804         if (status != connector_status_connected)
3805                 goto out;
3806
3807         intel_dp_probe_oui(intel_dp);
3808
3809         ret = intel_dp_probe_mst(intel_dp);
3810         if (ret) {
3811                 /* if we are in MST mode then this connector
3812                    won't appear connected or have anything with EDID on it */
3813                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3814                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3815                 status = connector_status_disconnected;
3816                 goto out;
3817         }
3818
3819         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3820                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3821         } else {
3822                 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3823                 if (edid) {
3824                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3825                         kfree(edid);
3826                 }
3827         }
3828
3829         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3830                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3831         status = connector_status_connected;
3832
3833 out:
3834         intel_display_power_put(dev_priv, power_domain);
3835         return status;
3836 }
3837
3838 static int intel_dp_get_modes(struct drm_connector *connector)
3839 {
3840         struct intel_dp *intel_dp = intel_attached_dp(connector);
3841         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3842         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3843         struct intel_connector *intel_connector = to_intel_connector(connector);
3844         struct drm_device *dev = connector->dev;
3845         struct drm_i915_private *dev_priv = dev->dev_private;
3846         enum intel_display_power_domain power_domain;
3847         int ret;
3848
3849         /* We should parse the EDID data and find out if it has an audio sink
3850          */
3851
3852         power_domain = intel_display_port_power_domain(intel_encoder);
3853         intel_display_power_get(dev_priv, power_domain);
3854
3855         ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3856         intel_display_power_put(dev_priv, power_domain);
3857         if (ret)
3858                 return ret;
3859
3860         /* if eDP has no EDID, fall back to fixed mode */
3861         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3862                 struct drm_display_mode *mode;
3863                 mode = drm_mode_duplicate(dev,
3864                                           intel_connector->panel.fixed_mode);
3865                 if (mode) {
3866                         drm_mode_probed_add(connector, mode);
3867                         return 1;
3868                 }
3869         }
3870         return 0;
3871 }
3872
3873 static bool
3874 intel_dp_detect_audio(struct drm_connector *connector)
3875 {
3876         struct intel_dp *intel_dp = intel_attached_dp(connector);
3877         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3878         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3879         struct drm_device *dev = connector->dev;
3880         struct drm_i915_private *dev_priv = dev->dev_private;
3881         enum intel_display_power_domain power_domain;
3882         struct edid *edid;
3883         bool has_audio = false;
3884
3885         power_domain = intel_display_port_power_domain(intel_encoder);
3886         intel_display_power_get(dev_priv, power_domain);
3887
3888         edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3889         if (edid) {
3890                 has_audio = drm_detect_monitor_audio(edid);
3891                 kfree(edid);
3892         }
3893
3894         intel_display_power_put(dev_priv, power_domain);
3895
3896         return has_audio;
3897 }
3898
3899 static int
3900 intel_dp_set_property(struct drm_connector *connector,
3901                       struct drm_property *property,
3902                       uint64_t val)
3903 {
3904         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3905         struct intel_connector *intel_connector = to_intel_connector(connector);
3906         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3907         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3908         int ret;
3909
3910         ret = drm_object_property_set_value(&connector->base, property, val);
3911         if (ret)
3912                 return ret;
3913
3914         if (property == dev_priv->force_audio_property) {
3915                 int i = val;
3916                 bool has_audio;
3917
3918                 if (i == intel_dp->force_audio)
3919                         return 0;
3920
3921                 intel_dp->force_audio = i;
3922
3923                 if (i == HDMI_AUDIO_AUTO)
3924                         has_audio = intel_dp_detect_audio(connector);
3925                 else
3926                         has_audio = (i == HDMI_AUDIO_ON);
3927
3928                 if (has_audio == intel_dp->has_audio)
3929                         return 0;
3930
3931                 intel_dp->has_audio = has_audio;
3932                 goto done;
3933         }
3934
3935         if (property == dev_priv->broadcast_rgb_property) {
3936                 bool old_auto = intel_dp->color_range_auto;
3937                 uint32_t old_range = intel_dp->color_range;
3938
3939                 switch (val) {
3940                 case INTEL_BROADCAST_RGB_AUTO:
3941                         intel_dp->color_range_auto = true;
3942                         break;
3943                 case INTEL_BROADCAST_RGB_FULL:
3944                         intel_dp->color_range_auto = false;
3945                         intel_dp->color_range = 0;
3946                         break;
3947                 case INTEL_BROADCAST_RGB_LIMITED:
3948                         intel_dp->color_range_auto = false;
3949                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3950                         break;
3951                 default:
3952                         return -EINVAL;
3953                 }
3954
3955                 if (old_auto == intel_dp->color_range_auto &&
3956                     old_range == intel_dp->color_range)
3957                         return 0;
3958
3959                 goto done;
3960         }
3961
3962         if (is_edp(intel_dp) &&
3963             property == connector->dev->mode_config.scaling_mode_property) {
3964                 if (val == DRM_MODE_SCALE_NONE) {
3965                         DRM_DEBUG_KMS("no scaling not supported\n");
3966                         return -EINVAL;
3967                 }
3968
3969                 if (intel_connector->panel.fitting_mode == val) {
3970                         /* the eDP scaling property is not changed */
3971                         return 0;
3972                 }
3973                 intel_connector->panel.fitting_mode = val;
3974
3975                 goto done;
3976         }
3977
3978         return -EINVAL;
3979
3980 done:
3981         if (intel_encoder->base.crtc)
3982                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3983
3984         return 0;
3985 }
3986
3987 static void
3988 intel_dp_connector_destroy(struct drm_connector *connector)
3989 {
3990         struct intel_connector *intel_connector = to_intel_connector(connector);
3991
3992         if (!IS_ERR_OR_NULL(intel_connector->edid))
3993                 kfree(intel_connector->edid);
3994
3995         /* Can't call is_edp() since the encoder may have been destroyed
3996          * already. */
3997         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3998                 intel_panel_fini(&intel_connector->panel);
3999
4000         drm_connector_cleanup(connector);
4001         kfree(connector);
4002 }
4003
4004 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4005 {
4006         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4007         struct intel_dp *intel_dp = &intel_dig_port->dp;
4008         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4009
4010         drm_dp_aux_unregister(&intel_dp->aux);
4011         intel_dp_mst_encoder_cleanup(intel_dig_port);
4012         drm_encoder_cleanup(encoder);
4013         if (is_edp(intel_dp)) {
4014                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4015                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4016                 edp_panel_vdd_off_sync(intel_dp);
4017                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4018                 if (intel_dp->edp_notifier.notifier_call) {
4019                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4020                         intel_dp->edp_notifier.notifier_call = NULL;
4021                 }
4022         }
4023         kfree(intel_dig_port);
4024 }
4025
4026 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4027 {
4028         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4029
4030         if (!is_edp(intel_dp))
4031                 return;
4032
4033         edp_panel_vdd_off_sync(intel_dp);
4034 }
4035
4036 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4037 {
4038         intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4039 }
4040
4041 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4042         .dpms = intel_connector_dpms,
4043         .detect = intel_dp_detect,
4044         .fill_modes = drm_helper_probe_single_connector_modes,
4045         .set_property = intel_dp_set_property,
4046         .destroy = intel_dp_connector_destroy,
4047 };
4048
4049 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4050         .get_modes = intel_dp_get_modes,
4051         .mode_valid = intel_dp_mode_valid,
4052         .best_encoder = intel_best_encoder,
4053 };
4054
4055 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4056         .reset = intel_dp_encoder_reset,
4057         .destroy = intel_dp_encoder_destroy,
4058 };
4059
4060 void
4061 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4062 {
4063         return;
4064 }
4065
4066 bool
4067 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4068 {
4069         struct intel_dp *intel_dp = &intel_dig_port->dp;
4070         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4071         struct drm_device *dev = intel_dig_port->base.base.dev;
4072         struct drm_i915_private *dev_priv = dev->dev_private;
4073         enum intel_display_power_domain power_domain;
4074         bool ret = true;
4075
4076         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4077                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4078
4079         DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port,
4080                       long_hpd ? "long" : "short");
4081
4082         power_domain = intel_display_port_power_domain(intel_encoder);
4083         intel_display_power_get(dev_priv, power_domain);
4084
4085         if (long_hpd) {
4086
4087                 if (HAS_PCH_SPLIT(dev)) {
4088                         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4089                                 goto mst_fail;
4090                 } else {
4091                         if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4092                                 goto mst_fail;
4093                 }
4094
4095                 if (!intel_dp_get_dpcd(intel_dp)) {
4096                         goto mst_fail;
4097                 }
4098
4099                 intel_dp_probe_oui(intel_dp);
4100
4101                 if (!intel_dp_probe_mst(intel_dp))
4102                         goto mst_fail;
4103
4104         } else {
4105                 if (intel_dp->is_mst) {
4106                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4107                                 goto mst_fail;
4108                 }
4109
4110                 if (!intel_dp->is_mst) {
4111                         /*
4112                          * we'll check the link status via the normal hot plug path later -
4113                          * but for short hpds we should check it now
4114                          */
4115                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4116                         intel_dp_check_link_status(intel_dp);
4117                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4118                 }
4119         }
4120         ret = false;
4121         goto put_power;
4122 mst_fail:
4123         /* if we were in MST mode, and device is not there get out of MST mode */
4124         if (intel_dp->is_mst) {
4125                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4126                 intel_dp->is_mst = false;
4127                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4128         }
4129 put_power:
4130         intel_display_power_put(dev_priv, power_domain);
4131
4132         return ret;
4133 }
4134
4135 /* Return which DP Port should be selected for Transcoder DP control */
4136 int
4137 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4138 {
4139         struct drm_device *dev = crtc->dev;
4140         struct intel_encoder *intel_encoder;
4141         struct intel_dp *intel_dp;
4142
4143         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4144                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4145
4146                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4147                     intel_encoder->type == INTEL_OUTPUT_EDP)
4148                         return intel_dp->output_reg;
4149         }
4150
4151         return -1;
4152 }
4153
4154 /* check the VBT to see whether the eDP is on DP-D port */
4155 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4156 {
4157         struct drm_i915_private *dev_priv = dev->dev_private;
4158         union child_device_config *p_child;
4159         int i;
4160         static const short port_mapping[] = {
4161                 [PORT_B] = PORT_IDPB,
4162                 [PORT_C] = PORT_IDPC,
4163                 [PORT_D] = PORT_IDPD,
4164         };
4165
4166         if (port == PORT_A)
4167                 return true;
4168
4169         if (!dev_priv->vbt.child_dev_num)
4170                 return false;
4171
4172         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4173                 p_child = dev_priv->vbt.child_dev + i;
4174
4175                 if (p_child->common.dvo_port == port_mapping[port] &&
4176                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4177                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4178                         return true;
4179         }
4180         return false;
4181 }
4182
4183 void
4184 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4185 {
4186         struct intel_connector *intel_connector = to_intel_connector(connector);
4187
4188         intel_attach_force_audio_property(connector);
4189         intel_attach_broadcast_rgb_property(connector);
4190         intel_dp->color_range_auto = true;
4191
4192         if (is_edp(intel_dp)) {
4193                 drm_mode_create_scaling_mode_property(connector->dev);
4194                 drm_object_attach_property(
4195                         &connector->base,
4196                         connector->dev->mode_config.scaling_mode_property,
4197                         DRM_MODE_SCALE_ASPECT);
4198                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4199         }
4200 }
4201
4202 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4203 {
4204         intel_dp->last_power_cycle = jiffies;
4205         intel_dp->last_power_on = jiffies;
4206         intel_dp->last_backlight_off = jiffies;
4207 }
4208
4209 static void
4210 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4211                                     struct intel_dp *intel_dp,
4212                                     struct edp_power_seq *out)
4213 {
4214         struct drm_i915_private *dev_priv = dev->dev_private;
4215         struct edp_power_seq cur, vbt, spec, final;
4216         u32 pp_on, pp_off, pp_div, pp;
4217         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4218
4219         if (HAS_PCH_SPLIT(dev)) {
4220                 pp_ctrl_reg = PCH_PP_CONTROL;
4221                 pp_on_reg = PCH_PP_ON_DELAYS;
4222                 pp_off_reg = PCH_PP_OFF_DELAYS;
4223                 pp_div_reg = PCH_PP_DIVISOR;
4224         } else {
4225                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4226
4227                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4228                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4229                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4230                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4231         }
4232
4233         /* Workaround: Need to write PP_CONTROL with the unlock key as
4234          * the very first thing. */
4235         pp = ironlake_get_pp_control(intel_dp);
4236         I915_WRITE(pp_ctrl_reg, pp);
4237
4238         pp_on = I915_READ(pp_on_reg);
4239         pp_off = I915_READ(pp_off_reg);
4240         pp_div = I915_READ(pp_div_reg);
4241
4242         /* Pull timing values out of registers */
4243         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4244                 PANEL_POWER_UP_DELAY_SHIFT;
4245
4246         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4247                 PANEL_LIGHT_ON_DELAY_SHIFT;
4248
4249         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4250                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4251
4252         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4253                 PANEL_POWER_DOWN_DELAY_SHIFT;
4254
4255         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4256                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4257
4258         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4259                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4260
4261         vbt = dev_priv->vbt.edp_pps;
4262
4263         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4264          * our hw here, which are all in 100usec. */
4265         spec.t1_t3 = 210 * 10;
4266         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4267         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4268         spec.t10 = 500 * 10;
4269         /* This one is special and actually in units of 100ms, but zero
4270          * based in the hw (so we need to add 100 ms). But the sw vbt
4271          * table multiplies it with 1000 to make it in units of 100usec,
4272          * too. */
4273         spec.t11_t12 = (510 + 100) * 10;
4274
4275         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4276                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4277
4278         /* Use the max of the register settings and vbt. If both are
4279          * unset, fall back to the spec limits. */
4280 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
4281                                        spec.field : \
4282                                        max(cur.field, vbt.field))
4283         assign_final(t1_t3);
4284         assign_final(t8);
4285         assign_final(t9);
4286         assign_final(t10);
4287         assign_final(t11_t12);
4288 #undef assign_final
4289
4290 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
4291         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4292         intel_dp->backlight_on_delay = get_delay(t8);
4293         intel_dp->backlight_off_delay = get_delay(t9);
4294         intel_dp->panel_power_down_delay = get_delay(t10);
4295         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4296 #undef get_delay
4297
4298         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4299                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4300                       intel_dp->panel_power_cycle_delay);
4301
4302         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4303                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4304
4305         if (out)
4306                 *out = final;
4307 }
4308
4309 static void
4310 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4311                                               struct intel_dp *intel_dp,
4312                                               struct edp_power_seq *seq)
4313 {
4314         struct drm_i915_private *dev_priv = dev->dev_private;
4315         u32 pp_on, pp_off, pp_div, port_sel = 0;
4316         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4317         int pp_on_reg, pp_off_reg, pp_div_reg;
4318
4319         if (HAS_PCH_SPLIT(dev)) {
4320                 pp_on_reg = PCH_PP_ON_DELAYS;
4321                 pp_off_reg = PCH_PP_OFF_DELAYS;
4322                 pp_div_reg = PCH_PP_DIVISOR;
4323         } else {
4324                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4325
4326                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4327                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4328                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4329         }
4330
4331         /*
4332          * And finally store the new values in the power sequencer. The
4333          * backlight delays are set to 1 because we do manual waits on them. For
4334          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4335          * we'll end up waiting for the backlight off delay twice: once when we
4336          * do the manual sleep, and once when we disable the panel and wait for
4337          * the PP_STATUS bit to become zero.
4338          */
4339         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4340                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4341         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4342                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4343         /* Compute the divisor for the pp clock, simply match the Bspec
4344          * formula. */
4345         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4346         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4347                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4348
4349         /* Haswell doesn't have any port selection bits for the panel
4350          * power sequencer any more. */
4351         if (IS_VALLEYVIEW(dev)) {
4352                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4353                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
4354                 else
4355                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
4356         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4357                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
4358                         port_sel = PANEL_PORT_SELECT_DPA;
4359                 else
4360                         port_sel = PANEL_PORT_SELECT_DPD;
4361         }
4362
4363         pp_on |= port_sel;
4364
4365         I915_WRITE(pp_on_reg, pp_on);
4366         I915_WRITE(pp_off_reg, pp_off);
4367         I915_WRITE(pp_div_reg, pp_div);
4368
4369         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4370                       I915_READ(pp_on_reg),
4371                       I915_READ(pp_off_reg),
4372                       I915_READ(pp_div_reg));
4373 }
4374
4375 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4376 {
4377         struct drm_i915_private *dev_priv = dev->dev_private;
4378         struct intel_encoder *encoder;
4379         struct intel_dp *intel_dp = NULL;
4380         struct intel_crtc_config *config = NULL;
4381         struct intel_crtc *intel_crtc = NULL;
4382         struct intel_connector *intel_connector = dev_priv->drrs.connector;
4383         u32 reg, val;
4384         enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4385
4386         if (refresh_rate <= 0) {
4387                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4388                 return;
4389         }
4390
4391         if (intel_connector == NULL) {
4392                 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4393                 return;
4394         }
4395
4396         /*
4397          * FIXME: This needs proper synchronization with psr state. But really
4398          * hard to tell without seeing the user of this function of this code.
4399          * Check locking and ordering once that lands.
4400          */
4401         if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4402                 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4403                 return;
4404         }
4405
4406         encoder = intel_attached_encoder(&intel_connector->base);
4407         intel_dp = enc_to_intel_dp(&encoder->base);
4408         intel_crtc = encoder->new_crtc;
4409
4410         if (!intel_crtc) {
4411                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4412                 return;
4413         }
4414
4415         config = &intel_crtc->config;
4416
4417         if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4418                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4419                 return;
4420         }
4421
4422         if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4423                 index = DRRS_LOW_RR;
4424
4425         if (index == intel_dp->drrs_state.refresh_rate_type) {
4426                 DRM_DEBUG_KMS(
4427                         "DRRS requested for previously set RR...ignoring\n");
4428                 return;
4429         }
4430
4431         if (!intel_crtc->active) {
4432                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4433                 return;
4434         }
4435
4436         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4437                 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4438                 val = I915_READ(reg);
4439                 if (index > DRRS_HIGH_RR) {
4440                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
4441                         intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4442                 } else {
4443                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4444                 }
4445                 I915_WRITE(reg, val);
4446         }
4447
4448         /*
4449          * mutex taken to ensure that there is no race between differnt
4450          * drrs calls trying to update refresh rate. This scenario may occur
4451          * in future when idleness detection based DRRS in kernel and
4452          * possible calls from user space to set differnt RR are made.
4453          */
4454
4455         mutex_lock(&intel_dp->drrs_state.mutex);
4456
4457         intel_dp->drrs_state.refresh_rate_type = index;
4458
4459         mutex_unlock(&intel_dp->drrs_state.mutex);
4460
4461         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4462 }
4463
4464 static struct drm_display_mode *
4465 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4466                         struct intel_connector *intel_connector,
4467                         struct drm_display_mode *fixed_mode)
4468 {
4469         struct drm_connector *connector = &intel_connector->base;
4470         struct intel_dp *intel_dp = &intel_dig_port->dp;
4471         struct drm_device *dev = intel_dig_port->base.base.dev;
4472         struct drm_i915_private *dev_priv = dev->dev_private;
4473         struct drm_display_mode *downclock_mode = NULL;
4474
4475         if (INTEL_INFO(dev)->gen <= 6) {
4476                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4477                 return NULL;
4478         }
4479
4480         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4481                 DRM_INFO("VBT doesn't support DRRS\n");
4482                 return NULL;
4483         }
4484
4485         downclock_mode = intel_find_panel_downclock
4486                                         (dev, fixed_mode, connector);
4487
4488         if (!downclock_mode) {
4489                 DRM_INFO("DRRS not supported\n");
4490                 return NULL;
4491         }
4492
4493         dev_priv->drrs.connector = intel_connector;
4494
4495         mutex_init(&intel_dp->drrs_state.mutex);
4496
4497         intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4498
4499         intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4500         DRM_INFO("seamless DRRS supported for eDP panel.\n");
4501         return downclock_mode;
4502 }
4503
4504 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4505 {
4506         struct drm_device *dev = intel_encoder->base.dev;
4507         struct drm_i915_private *dev_priv = dev->dev_private;
4508         struct intel_dp *intel_dp;
4509         enum intel_display_power_domain power_domain;
4510
4511         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4512                 return;
4513
4514         intel_dp = enc_to_intel_dp(&intel_encoder->base);
4515         if (!edp_have_panel_vdd(intel_dp))
4516                 return;
4517         /*
4518          * The VDD bit needs a power domain reference, so if the bit is
4519          * already enabled when we boot or resume, grab this reference and
4520          * schedule a vdd off, so we don't hold on to the reference
4521          * indefinitely.
4522          */
4523         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4524         power_domain = intel_display_port_power_domain(intel_encoder);
4525         intel_display_power_get(dev_priv, power_domain);
4526
4527         edp_panel_vdd_schedule_off(intel_dp);
4528 }
4529
4530 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4531                                      struct intel_connector *intel_connector,
4532                                      struct edp_power_seq *power_seq)
4533 {
4534         struct drm_connector *connector = &intel_connector->base;
4535         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4536         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4537         struct drm_device *dev = intel_encoder->base.dev;
4538         struct drm_i915_private *dev_priv = dev->dev_private;
4539         struct drm_display_mode *fixed_mode = NULL;
4540         struct drm_display_mode *downclock_mode = NULL;
4541         bool has_dpcd;
4542         struct drm_display_mode *scan;
4543         struct edid *edid;
4544
4545         intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4546
4547         if (!is_edp(intel_dp))
4548                 return true;
4549
4550         intel_edp_panel_vdd_sanitize(intel_encoder);
4551
4552         /* Cache DPCD and EDID for edp. */
4553         intel_edp_panel_vdd_on(intel_dp);
4554         has_dpcd = intel_dp_get_dpcd(intel_dp);
4555         edp_panel_vdd_off(intel_dp, false);
4556
4557         if (has_dpcd) {
4558                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4559                         dev_priv->no_aux_handshake =
4560                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4561                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4562         } else {
4563                 /* if this fails, presume the device is a ghost */
4564                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4565                 return false;
4566         }
4567
4568         /* We now know it's not a ghost, init power sequence regs. */
4569         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4570
4571         mutex_lock(&dev->mode_config.mutex);
4572         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4573         if (edid) {
4574                 if (drm_add_edid_modes(connector, edid)) {
4575                         drm_mode_connector_update_edid_property(connector,
4576                                                                 edid);
4577                         drm_edid_to_eld(connector, edid);
4578                 } else {
4579                         kfree(edid);
4580                         edid = ERR_PTR(-EINVAL);
4581                 }
4582         } else {
4583                 edid = ERR_PTR(-ENOENT);
4584         }
4585         intel_connector->edid = edid;
4586
4587         /* prefer fixed mode from EDID if available */
4588         list_for_each_entry(scan, &connector->probed_modes, head) {
4589                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4590                         fixed_mode = drm_mode_duplicate(dev, scan);
4591                         downclock_mode = intel_dp_drrs_init(
4592                                                 intel_dig_port,
4593                                                 intel_connector, fixed_mode);
4594                         break;
4595                 }
4596         }
4597
4598         /* fallback to VBT if available for eDP */
4599         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4600                 fixed_mode = drm_mode_duplicate(dev,
4601                                         dev_priv->vbt.lfp_lvds_vbt_mode);
4602                 if (fixed_mode)
4603                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4604         }
4605         mutex_unlock(&dev->mode_config.mutex);
4606
4607         if (IS_VALLEYVIEW(dev)) {
4608                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4609                 register_reboot_notifier(&intel_dp->edp_notifier);
4610         }
4611
4612         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4613         intel_panel_setup_backlight(connector);
4614
4615         return true;
4616 }
4617
4618 bool
4619 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4620                         struct intel_connector *intel_connector)
4621 {
4622         struct drm_connector *connector = &intel_connector->base;
4623         struct intel_dp *intel_dp = &intel_dig_port->dp;
4624         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4625         struct drm_device *dev = intel_encoder->base.dev;
4626         struct drm_i915_private *dev_priv = dev->dev_private;
4627         enum port port = intel_dig_port->port;
4628         struct edp_power_seq power_seq = { 0 };
4629         int type;
4630
4631         /* intel_dp vfuncs */
4632         if (IS_VALLEYVIEW(dev))
4633                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4634         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4635                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4636         else if (HAS_PCH_SPLIT(dev))
4637                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4638         else
4639                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4640
4641         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4642
4643         /* Preserve the current hw state. */
4644         intel_dp->DP = I915_READ(intel_dp->output_reg);
4645         intel_dp->attached_connector = intel_connector;
4646
4647         if (intel_dp_is_edp(dev, port))
4648                 type = DRM_MODE_CONNECTOR_eDP;
4649         else
4650                 type = DRM_MODE_CONNECTOR_DisplayPort;
4651
4652         /*
4653          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4654          * for DP the encoder type can be set by the caller to
4655          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4656          */
4657         if (type == DRM_MODE_CONNECTOR_eDP)
4658                 intel_encoder->type = INTEL_OUTPUT_EDP;
4659
4660         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4661                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4662                         port_name(port));
4663
4664         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4665         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4666
4667         connector->interlace_allowed = true;
4668         connector->doublescan_allowed = 0;
4669
4670         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4671                           edp_panel_vdd_work);
4672
4673         intel_connector_attach_encoder(intel_connector, intel_encoder);
4674         drm_connector_register(connector);
4675
4676         if (HAS_DDI(dev))
4677                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4678         else
4679                 intel_connector->get_hw_state = intel_connector_get_hw_state;
4680         intel_connector->unregister = intel_dp_connector_unregister;
4681
4682         /* Set up the hotplug pin. */
4683         switch (port) {
4684         case PORT_A:
4685                 intel_encoder->hpd_pin = HPD_PORT_A;
4686                 break;
4687         case PORT_B:
4688                 intel_encoder->hpd_pin = HPD_PORT_B;
4689                 break;
4690         case PORT_C:
4691                 intel_encoder->hpd_pin = HPD_PORT_C;
4692                 break;
4693         case PORT_D:
4694                 intel_encoder->hpd_pin = HPD_PORT_D;
4695                 break;
4696         default:
4697                 BUG();
4698         }
4699
4700         if (is_edp(intel_dp)) {
4701                 intel_dp_init_panel_power_timestamps(intel_dp);
4702                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4703         }
4704
4705         intel_dp_aux_init(intel_dp, intel_connector);
4706
4707         /* init MST on ports that can support it */
4708         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4709                 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4710                         intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4711                 }
4712         }
4713
4714         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4715                 drm_dp_aux_unregister(&intel_dp->aux);
4716                 if (is_edp(intel_dp)) {
4717                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4718                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4719                         edp_panel_vdd_off_sync(intel_dp);
4720                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4721                 }
4722                 drm_connector_unregister(connector);
4723                 drm_connector_cleanup(connector);
4724                 return false;
4725         }
4726
4727         intel_dp_add_properties(intel_dp, connector);
4728
4729         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4730          * 0xd.  Failure to do so will result in spurious interrupts being
4731          * generated on the port when a cable is not attached.
4732          */
4733         if (IS_G4X(dev) && !IS_GM45(dev)) {
4734                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4735                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4736         }
4737
4738         return true;
4739 }
4740
4741 void
4742 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4743 {
4744         struct drm_i915_private *dev_priv = dev->dev_private;
4745         struct intel_digital_port *intel_dig_port;
4746         struct intel_encoder *intel_encoder;
4747         struct drm_encoder *encoder;
4748         struct intel_connector *intel_connector;
4749
4750         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4751         if (!intel_dig_port)
4752                 return;
4753
4754         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4755         if (!intel_connector) {
4756                 kfree(intel_dig_port);
4757                 return;
4758         }
4759
4760         intel_encoder = &intel_dig_port->base;
4761         encoder = &intel_encoder->base;
4762
4763         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4764                          DRM_MODE_ENCODER_TMDS);
4765
4766         intel_encoder->compute_config = intel_dp_compute_config;
4767         intel_encoder->disable = intel_disable_dp;
4768         intel_encoder->get_hw_state = intel_dp_get_hw_state;
4769         intel_encoder->get_config = intel_dp_get_config;
4770         intel_encoder->suspend = intel_dp_encoder_suspend;
4771         if (IS_CHERRYVIEW(dev)) {
4772                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4773                 intel_encoder->pre_enable = chv_pre_enable_dp;
4774                 intel_encoder->enable = vlv_enable_dp;
4775                 intel_encoder->post_disable = chv_post_disable_dp;
4776         } else if (IS_VALLEYVIEW(dev)) {
4777                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4778                 intel_encoder->pre_enable = vlv_pre_enable_dp;
4779                 intel_encoder->enable = vlv_enable_dp;
4780                 intel_encoder->post_disable = vlv_post_disable_dp;
4781         } else {
4782                 intel_encoder->pre_enable = g4x_pre_enable_dp;
4783                 intel_encoder->enable = g4x_enable_dp;
4784                 intel_encoder->post_disable = g4x_post_disable_dp;
4785         }
4786
4787         intel_dig_port->port = port;
4788         intel_dig_port->dp.output_reg = output_reg;
4789
4790         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4791         if (IS_CHERRYVIEW(dev)) {
4792                 if (port == PORT_D)
4793                         intel_encoder->crtc_mask = 1 << 2;
4794                 else
4795                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4796         } else {
4797                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4798         }
4799         intel_encoder->cloneable = 0;
4800         intel_encoder->hot_plug = intel_dp_hot_plug;
4801
4802         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4803         dev_priv->hpd_irq_port[port] = intel_dig_port;
4804
4805         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4806                 drm_encoder_cleanup(encoder);
4807                 kfree(intel_dig_port);
4808                 kfree(intel_connector);
4809         }
4810 }
4811
4812 void intel_dp_mst_suspend(struct drm_device *dev)
4813 {
4814         struct drm_i915_private *dev_priv = dev->dev_private;
4815         int i;
4816
4817         /* disable MST */
4818         for (i = 0; i < I915_MAX_PORTS; i++) {
4819                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4820                 if (!intel_dig_port)
4821                         continue;
4822
4823                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4824                         if (!intel_dig_port->dp.can_mst)
4825                                 continue;
4826                         if (intel_dig_port->dp.is_mst)
4827                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4828                 }
4829         }
4830 }
4831
4832 void intel_dp_mst_resume(struct drm_device *dev)
4833 {
4834         struct drm_i915_private *dev_priv = dev->dev_private;
4835         int i;
4836
4837         for (i = 0; i < I915_MAX_PORTS; i++) {
4838                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4839                 if (!intel_dig_port)
4840                         continue;
4841                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4842                         int ret;
4843
4844                         if (!intel_dig_port->dp.can_mst)
4845                                 continue;
4846
4847                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4848                         if (ret != 0) {
4849                                 intel_dp_check_mst_status(&intel_dig_port->dp);
4850                         }
4851                 }
4852         }
4853 }