drm/i915: Update DRIVER_DATE to 20190110
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Keith Packard <keithp@keithp.com>
25  *
26  */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
35 #include <drm/drm_atomic_helper.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_crtc_helper.h>
38 #include <drm/drm_dp_helper.h>
39 #include <drm/drm_edid.h>
40 #include <drm/drm_hdcp.h>
41 #include "intel_drv.h"
42 #include <drm/i915_drm.h>
43 #include "i915_drv.h"
44
45 #define DP_DPRX_ESI_LEN 14
46
47 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
48 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER      61440
49 #define DP_DSC_MIN_SUPPORTED_BPC                8
50 #define DP_DSC_MAX_SUPPORTED_BPC                10
51
52 /* DP DSC throughput values used for slice count calculations KPixels/s */
53 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
54 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
55 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
56
57 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
58 #define DP_DSC_FEC_OVERHEAD_FACTOR              976
59
60 /* Compliance test status bits  */
61 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
62 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
63 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
64 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
65
66 struct dp_link_dpll {
67         int clock;
68         struct dpll dpll;
69 };
70
71 static const struct dp_link_dpll g4x_dpll[] = {
72         { 162000,
73                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
74         { 270000,
75                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
76 };
77
78 static const struct dp_link_dpll pch_dpll[] = {
79         { 162000,
80                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
81         { 270000,
82                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
83 };
84
85 static const struct dp_link_dpll vlv_dpll[] = {
86         { 162000,
87                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
88         { 270000,
89                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
90 };
91
92 /*
93  * CHV supports eDP 1.4 that have  more link rates.
94  * Below only provides the fixed rate but exclude variable rate.
95  */
96 static const struct dp_link_dpll chv_dpll[] = {
97         /*
98          * CHV requires to program fractional division for m2.
99          * m2 is stored in fixed point format using formula below
100          * (m2_int << 22) | m2_fraction
101          */
102         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
103                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
104         { 270000,       /* m2_int = 27, m2_fraction = 0 */
105                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
106 };
107
108 /* Constants for DP DSC configurations */
109 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
110
111 /* With Single pipe configuration, HW is capable of supporting maximum
112  * of 4 slices per line.
113  */
114 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
115
116 /**
117  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
118  * @intel_dp: DP struct
119  *
120  * If a CPU or PCH DP output is attached to an eDP panel, this function
121  * will return true, and false otherwise.
122  */
123 bool intel_dp_is_edp(struct intel_dp *intel_dp)
124 {
125         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
126
127         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
128 }
129
130 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
131 {
132         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
133 }
134
135 static void intel_dp_link_down(struct intel_encoder *encoder,
136                                const struct intel_crtc_state *old_crtc_state);
137 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
138 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
139 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
140                                            const struct intel_crtc_state *crtc_state);
141 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
142                                       enum pipe pipe);
143 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
144
145 /* update sink rates from dpcd */
146 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
147 {
148         static const int dp_rates[] = {
149                 162000, 270000, 540000, 810000
150         };
151         int i, max_rate;
152
153         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
154
155         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
156                 if (dp_rates[i] > max_rate)
157                         break;
158                 intel_dp->sink_rates[i] = dp_rates[i];
159         }
160
161         intel_dp->num_sink_rates = i;
162 }
163
164 /* Get length of rates array potentially limited by max_rate. */
165 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
166 {
167         int i;
168
169         /* Limit results by potentially reduced max rate */
170         for (i = 0; i < len; i++) {
171                 if (rates[len - i - 1] <= max_rate)
172                         return len - i;
173         }
174
175         return 0;
176 }
177
178 /* Get length of common rates array potentially limited by max_rate. */
179 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
180                                           int max_rate)
181 {
182         return intel_dp_rate_limit_len(intel_dp->common_rates,
183                                        intel_dp->num_common_rates, max_rate);
184 }
185
186 /* Theoretical max between source and sink */
187 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
188 {
189         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
190 }
191
192 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
193 {
194         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
195         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
196         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
197         u32 lane_info;
198
199         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
200                 return 4;
201
202         lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
203                      DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
204                     DP_LANE_ASSIGNMENT_SHIFT(tc_port);
205
206         switch (lane_info) {
207         default:
208                 MISSING_CASE(lane_info);
209         case 1:
210         case 2:
211         case 4:
212         case 8:
213                 return 1;
214         case 3:
215         case 12:
216                 return 2;
217         case 15:
218                 return 4;
219         }
220 }
221
222 /* Theoretical max between source and sink */
223 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
224 {
225         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
226         int source_max = intel_dig_port->max_lanes;
227         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
228         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
229
230         return min3(source_max, sink_max, fia_max);
231 }
232
233 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
234 {
235         return intel_dp->max_link_lane_count;
236 }
237
238 int
239 intel_dp_link_required(int pixel_clock, int bpp)
240 {
241         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
242         return DIV_ROUND_UP(pixel_clock * bpp, 8);
243 }
244
245 int
246 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
247 {
248         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
249          * link rate that is generally expressed in Gbps. Since, 8 bits of data
250          * is transmitted every LS_Clk per lane, there is no need to account for
251          * the channel encoding that is done in the PHY layer here.
252          */
253
254         return max_link_clock * max_lanes;
255 }
256
257 static int
258 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
259 {
260         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
261         struct intel_encoder *encoder = &intel_dig_port->base;
262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
263         int max_dotclk = dev_priv->max_dotclk_freq;
264         int ds_max_dotclk;
265
266         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
267
268         if (type != DP_DS_PORT_TYPE_VGA)
269                 return max_dotclk;
270
271         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
272                                                     intel_dp->downstream_ports);
273
274         if (ds_max_dotclk != 0)
275                 max_dotclk = min(max_dotclk, ds_max_dotclk);
276
277         return max_dotclk;
278 }
279
280 static int cnl_max_source_rate(struct intel_dp *intel_dp)
281 {
282         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
283         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
284         enum port port = dig_port->base.port;
285
286         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
287
288         /* Low voltage SKUs are limited to max of 5.4G */
289         if (voltage == VOLTAGE_INFO_0_85V)
290                 return 540000;
291
292         /* For this SKU 8.1G is supported in all ports */
293         if (IS_CNL_WITH_PORT_F(dev_priv))
294                 return 810000;
295
296         /* For other SKUs, max rate on ports A and D is 5.4G */
297         if (port == PORT_A || port == PORT_D)
298                 return 540000;
299
300         return 810000;
301 }
302
303 static int icl_max_source_rate(struct intel_dp *intel_dp)
304 {
305         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
306         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
307         enum port port = dig_port->base.port;
308
309         if (intel_port_is_combophy(dev_priv, port) &&
310             !intel_dp_is_edp(intel_dp))
311                 return 540000;
312
313         return 810000;
314 }
315
316 static void
317 intel_dp_set_source_rates(struct intel_dp *intel_dp)
318 {
319         /* The values must be in increasing order */
320         static const int cnl_rates[] = {
321                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
322         };
323         static const int bxt_rates[] = {
324                 162000, 216000, 243000, 270000, 324000, 432000, 540000
325         };
326         static const int skl_rates[] = {
327                 162000, 216000, 270000, 324000, 432000, 540000
328         };
329         static const int hsw_rates[] = {
330                 162000, 270000, 540000
331         };
332         static const int g4x_rates[] = {
333                 162000, 270000
334         };
335         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
336         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
337         const struct ddi_vbt_port_info *info =
338                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
339         const int *source_rates;
340         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
341
342         /* This should only be done once */
343         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
344
345         if (INTEL_GEN(dev_priv) >= 10) {
346                 source_rates = cnl_rates;
347                 size = ARRAY_SIZE(cnl_rates);
348                 if (IS_GEN(dev_priv, 10))
349                         max_rate = cnl_max_source_rate(intel_dp);
350                 else
351                         max_rate = icl_max_source_rate(intel_dp);
352         } else if (IS_GEN9_LP(dev_priv)) {
353                 source_rates = bxt_rates;
354                 size = ARRAY_SIZE(bxt_rates);
355         } else if (IS_GEN9_BC(dev_priv)) {
356                 source_rates = skl_rates;
357                 size = ARRAY_SIZE(skl_rates);
358         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
359                    IS_BROADWELL(dev_priv)) {
360                 source_rates = hsw_rates;
361                 size = ARRAY_SIZE(hsw_rates);
362         } else {
363                 source_rates = g4x_rates;
364                 size = ARRAY_SIZE(g4x_rates);
365         }
366
367         if (max_rate && vbt_max_rate)
368                 max_rate = min(max_rate, vbt_max_rate);
369         else if (vbt_max_rate)
370                 max_rate = vbt_max_rate;
371
372         if (max_rate)
373                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
374
375         intel_dp->source_rates = source_rates;
376         intel_dp->num_source_rates = size;
377 }
378
379 static int intersect_rates(const int *source_rates, int source_len,
380                            const int *sink_rates, int sink_len,
381                            int *common_rates)
382 {
383         int i = 0, j = 0, k = 0;
384
385         while (i < source_len && j < sink_len) {
386                 if (source_rates[i] == sink_rates[j]) {
387                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
388                                 return k;
389                         common_rates[k] = source_rates[i];
390                         ++k;
391                         ++i;
392                         ++j;
393                 } else if (source_rates[i] < sink_rates[j]) {
394                         ++i;
395                 } else {
396                         ++j;
397                 }
398         }
399         return k;
400 }
401
402 /* return index of rate in rates array, or -1 if not found */
403 static int intel_dp_rate_index(const int *rates, int len, int rate)
404 {
405         int i;
406
407         for (i = 0; i < len; i++)
408                 if (rate == rates[i])
409                         return i;
410
411         return -1;
412 }
413
414 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
415 {
416         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
417
418         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
419                                                      intel_dp->num_source_rates,
420                                                      intel_dp->sink_rates,
421                                                      intel_dp->num_sink_rates,
422                                                      intel_dp->common_rates);
423
424         /* Paranoia, there should always be something in common. */
425         if (WARN_ON(intel_dp->num_common_rates == 0)) {
426                 intel_dp->common_rates[0] = 162000;
427                 intel_dp->num_common_rates = 1;
428         }
429 }
430
431 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
432                                        uint8_t lane_count)
433 {
434         /*
435          * FIXME: we need to synchronize the current link parameters with
436          * hardware readout. Currently fast link training doesn't work on
437          * boot-up.
438          */
439         if (link_rate == 0 ||
440             link_rate > intel_dp->max_link_rate)
441                 return false;
442
443         if (lane_count == 0 ||
444             lane_count > intel_dp_max_lane_count(intel_dp))
445                 return false;
446
447         return true;
448 }
449
450 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
451                                                      int link_rate,
452                                                      uint8_t lane_count)
453 {
454         const struct drm_display_mode *fixed_mode =
455                 intel_dp->attached_connector->panel.fixed_mode;
456         int mode_rate, max_rate;
457
458         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
459         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
460         if (mode_rate > max_rate)
461                 return false;
462
463         return true;
464 }
465
466 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
467                                             int link_rate, uint8_t lane_count)
468 {
469         int index;
470
471         index = intel_dp_rate_index(intel_dp->common_rates,
472                                     intel_dp->num_common_rates,
473                                     link_rate);
474         if (index > 0) {
475                 if (intel_dp_is_edp(intel_dp) &&
476                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
477                                                               intel_dp->common_rates[index - 1],
478                                                               lane_count)) {
479                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
480                         return 0;
481                 }
482                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
483                 intel_dp->max_link_lane_count = lane_count;
484         } else if (lane_count > 1) {
485                 if (intel_dp_is_edp(intel_dp) &&
486                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
487                                                               intel_dp_max_common_rate(intel_dp),
488                                                               lane_count >> 1)) {
489                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
490                         return 0;
491                 }
492                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
493                 intel_dp->max_link_lane_count = lane_count >> 1;
494         } else {
495                 DRM_ERROR("Link Training Unsuccessful\n");
496                 return -1;
497         }
498
499         return 0;
500 }
501
502 static enum drm_mode_status
503 intel_dp_mode_valid(struct drm_connector *connector,
504                     struct drm_display_mode *mode)
505 {
506         struct intel_dp *intel_dp = intel_attached_dp(connector);
507         struct intel_connector *intel_connector = to_intel_connector(connector);
508         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
509         struct drm_i915_private *dev_priv = to_i915(connector->dev);
510         int target_clock = mode->clock;
511         int max_rate, mode_rate, max_lanes, max_link_clock;
512         int max_dotclk;
513         u16 dsc_max_output_bpp = 0;
514         u8 dsc_slice_count = 0;
515
516         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
517                 return MODE_NO_DBLESCAN;
518
519         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
520
521         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
522                 if (mode->hdisplay > fixed_mode->hdisplay)
523                         return MODE_PANEL;
524
525                 if (mode->vdisplay > fixed_mode->vdisplay)
526                         return MODE_PANEL;
527
528                 target_clock = fixed_mode->clock;
529         }
530
531         max_link_clock = intel_dp_max_link_rate(intel_dp);
532         max_lanes = intel_dp_max_lane_count(intel_dp);
533
534         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
535         mode_rate = intel_dp_link_required(target_clock, 18);
536
537         /*
538          * Output bpp is stored in 6.4 format so right shift by 4 to get the
539          * integer value since we support only integer values of bpp.
540          */
541         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
542             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
543                 if (intel_dp_is_edp(intel_dp)) {
544                         dsc_max_output_bpp =
545                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
546                         dsc_slice_count =
547                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
548                                                                 true);
549                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
550                         dsc_max_output_bpp =
551                                 intel_dp_dsc_get_output_bpp(max_link_clock,
552                                                             max_lanes,
553                                                             target_clock,
554                                                             mode->hdisplay) >> 4;
555                         dsc_slice_count =
556                                 intel_dp_dsc_get_slice_count(intel_dp,
557                                                              target_clock,
558                                                              mode->hdisplay);
559                 }
560         }
561
562         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
563             target_clock > max_dotclk)
564                 return MODE_CLOCK_HIGH;
565
566         if (mode->clock < 10000)
567                 return MODE_CLOCK_LOW;
568
569         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
570                 return MODE_H_ILLEGAL;
571
572         return MODE_OK;
573 }
574
575 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
576 {
577         int     i;
578         uint32_t v = 0;
579
580         if (src_bytes > 4)
581                 src_bytes = 4;
582         for (i = 0; i < src_bytes; i++)
583                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
584         return v;
585 }
586
587 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
588 {
589         int i;
590         if (dst_bytes > 4)
591                 dst_bytes = 4;
592         for (i = 0; i < dst_bytes; i++)
593                 dst[i] = src >> ((3-i) * 8);
594 }
595
596 static void
597 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
598 static void
599 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
600                                               bool force_disable_vdd);
601 static void
602 intel_dp_pps_init(struct intel_dp *intel_dp);
603
604 static void pps_lock(struct intel_dp *intel_dp)
605 {
606         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
607
608         /*
609          * See intel_power_sequencer_reset() why we need
610          * a power domain reference here.
611          */
612         intel_display_power_get(dev_priv,
613                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
614
615         mutex_lock(&dev_priv->pps_mutex);
616 }
617
618 static void pps_unlock(struct intel_dp *intel_dp)
619 {
620         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
621
622         mutex_unlock(&dev_priv->pps_mutex);
623
624         intel_display_power_put(dev_priv,
625                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
626 }
627
628 static void
629 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
630 {
631         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
632         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
633         enum pipe pipe = intel_dp->pps_pipe;
634         bool pll_enabled, release_cl_override = false;
635         enum dpio_phy phy = DPIO_PHY(pipe);
636         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
637         uint32_t DP;
638
639         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
640                  "skipping pipe %c power sequencer kick due to port %c being active\n",
641                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
642                 return;
643
644         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
645                       pipe_name(pipe), port_name(intel_dig_port->base.port));
646
647         /* Preserve the BIOS-computed detected bit. This is
648          * supposed to be read-only.
649          */
650         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
651         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
652         DP |= DP_PORT_WIDTH(1);
653         DP |= DP_LINK_TRAIN_PAT_1;
654
655         if (IS_CHERRYVIEW(dev_priv))
656                 DP |= DP_PIPE_SEL_CHV(pipe);
657         else
658                 DP |= DP_PIPE_SEL(pipe);
659
660         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
661
662         /*
663          * The DPLL for the pipe must be enabled for this to work.
664          * So enable temporarily it if it's not already enabled.
665          */
666         if (!pll_enabled) {
667                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
668                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
669
670                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
671                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
672                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
673                                   pipe_name(pipe));
674                         return;
675                 }
676         }
677
678         /*
679          * Similar magic as in intel_dp_enable_port().
680          * We _must_ do this port enable + disable trick
681          * to make this power sequencer lock onto the port.
682          * Otherwise even VDD force bit won't work.
683          */
684         I915_WRITE(intel_dp->output_reg, DP);
685         POSTING_READ(intel_dp->output_reg);
686
687         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
688         POSTING_READ(intel_dp->output_reg);
689
690         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
691         POSTING_READ(intel_dp->output_reg);
692
693         if (!pll_enabled) {
694                 vlv_force_pll_off(dev_priv, pipe);
695
696                 if (release_cl_override)
697                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
698         }
699 }
700
701 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
702 {
703         struct intel_encoder *encoder;
704         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
705
706         /*
707          * We don't have power sequencer currently.
708          * Pick one that's not used by other ports.
709          */
710         for_each_intel_dp(&dev_priv->drm, encoder) {
711                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
712
713                 if (encoder->type == INTEL_OUTPUT_EDP) {
714                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
715                                 intel_dp->active_pipe != intel_dp->pps_pipe);
716
717                         if (intel_dp->pps_pipe != INVALID_PIPE)
718                                 pipes &= ~(1 << intel_dp->pps_pipe);
719                 } else {
720                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
721
722                         if (intel_dp->active_pipe != INVALID_PIPE)
723                                 pipes &= ~(1 << intel_dp->active_pipe);
724                 }
725         }
726
727         if (pipes == 0)
728                 return INVALID_PIPE;
729
730         return ffs(pipes) - 1;
731 }
732
733 static enum pipe
734 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
735 {
736         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
737         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
738         enum pipe pipe;
739
740         lockdep_assert_held(&dev_priv->pps_mutex);
741
742         /* We should never land here with regular DP ports */
743         WARN_ON(!intel_dp_is_edp(intel_dp));
744
745         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
746                 intel_dp->active_pipe != intel_dp->pps_pipe);
747
748         if (intel_dp->pps_pipe != INVALID_PIPE)
749                 return intel_dp->pps_pipe;
750
751         pipe = vlv_find_free_pps(dev_priv);
752
753         /*
754          * Didn't find one. This should not happen since there
755          * are two power sequencers and up to two eDP ports.
756          */
757         if (WARN_ON(pipe == INVALID_PIPE))
758                 pipe = PIPE_A;
759
760         vlv_steal_power_sequencer(dev_priv, pipe);
761         intel_dp->pps_pipe = pipe;
762
763         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
764                       pipe_name(intel_dp->pps_pipe),
765                       port_name(intel_dig_port->base.port));
766
767         /* init power sequencer on this pipe and port */
768         intel_dp_init_panel_power_sequencer(intel_dp);
769         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
770
771         /*
772          * Even vdd force doesn't work until we've made
773          * the power sequencer lock in on the port.
774          */
775         vlv_power_sequencer_kick(intel_dp);
776
777         return intel_dp->pps_pipe;
778 }
779
780 static int
781 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
782 {
783         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
784         int backlight_controller = dev_priv->vbt.backlight.controller;
785
786         lockdep_assert_held(&dev_priv->pps_mutex);
787
788         /* We should never land here with regular DP ports */
789         WARN_ON(!intel_dp_is_edp(intel_dp));
790
791         if (!intel_dp->pps_reset)
792                 return backlight_controller;
793
794         intel_dp->pps_reset = false;
795
796         /*
797          * Only the HW needs to be reprogrammed, the SW state is fixed and
798          * has been setup during connector init.
799          */
800         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
801
802         return backlight_controller;
803 }
804
805 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
806                                enum pipe pipe);
807
808 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
809                                enum pipe pipe)
810 {
811         return I915_READ(PP_STATUS(pipe)) & PP_ON;
812 }
813
814 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
815                                 enum pipe pipe)
816 {
817         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
818 }
819
820 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
821                          enum pipe pipe)
822 {
823         return true;
824 }
825
826 static enum pipe
827 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
828                      enum port port,
829                      vlv_pipe_check pipe_check)
830 {
831         enum pipe pipe;
832
833         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
834                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
835                         PANEL_PORT_SELECT_MASK;
836
837                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
838                         continue;
839
840                 if (!pipe_check(dev_priv, pipe))
841                         continue;
842
843                 return pipe;
844         }
845
846         return INVALID_PIPE;
847 }
848
849 static void
850 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
851 {
852         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
853         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
854         enum port port = intel_dig_port->base.port;
855
856         lockdep_assert_held(&dev_priv->pps_mutex);
857
858         /* try to find a pipe with this port selected */
859         /* first pick one where the panel is on */
860         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
861                                                   vlv_pipe_has_pp_on);
862         /* didn't find one? pick one where vdd is on */
863         if (intel_dp->pps_pipe == INVALID_PIPE)
864                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
865                                                           vlv_pipe_has_vdd_on);
866         /* didn't find one? pick one with just the correct port */
867         if (intel_dp->pps_pipe == INVALID_PIPE)
868                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
869                                                           vlv_pipe_any);
870
871         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
872         if (intel_dp->pps_pipe == INVALID_PIPE) {
873                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
874                               port_name(port));
875                 return;
876         }
877
878         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
879                       port_name(port), pipe_name(intel_dp->pps_pipe));
880
881         intel_dp_init_panel_power_sequencer(intel_dp);
882         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
883 }
884
885 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
886 {
887         struct intel_encoder *encoder;
888
889         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
890                     !IS_GEN9_LP(dev_priv)))
891                 return;
892
893         /*
894          * We can't grab pps_mutex here due to deadlock with power_domain
895          * mutex when power_domain functions are called while holding pps_mutex.
896          * That also means that in order to use pps_pipe the code needs to
897          * hold both a power domain reference and pps_mutex, and the power domain
898          * reference get/put must be done while _not_ holding pps_mutex.
899          * pps_{lock,unlock}() do these steps in the correct order, so one
900          * should use them always.
901          */
902
903         for_each_intel_dp(&dev_priv->drm, encoder) {
904                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
905
906                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
907
908                 if (encoder->type != INTEL_OUTPUT_EDP)
909                         continue;
910
911                 if (IS_GEN9_LP(dev_priv))
912                         intel_dp->pps_reset = true;
913                 else
914                         intel_dp->pps_pipe = INVALID_PIPE;
915         }
916 }
917
918 struct pps_registers {
919         i915_reg_t pp_ctrl;
920         i915_reg_t pp_stat;
921         i915_reg_t pp_on;
922         i915_reg_t pp_off;
923         i915_reg_t pp_div;
924 };
925
926 static void intel_pps_get_registers(struct intel_dp *intel_dp,
927                                     struct pps_registers *regs)
928 {
929         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
930         int pps_idx = 0;
931
932         memset(regs, 0, sizeof(*regs));
933
934         if (IS_GEN9_LP(dev_priv))
935                 pps_idx = bxt_power_sequencer_idx(intel_dp);
936         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
937                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
938
939         regs->pp_ctrl = PP_CONTROL(pps_idx);
940         regs->pp_stat = PP_STATUS(pps_idx);
941         regs->pp_on = PP_ON_DELAYS(pps_idx);
942         regs->pp_off = PP_OFF_DELAYS(pps_idx);
943         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
944             !HAS_PCH_ICP(dev_priv))
945                 regs->pp_div = PP_DIVISOR(pps_idx);
946 }
947
948 static i915_reg_t
949 _pp_ctrl_reg(struct intel_dp *intel_dp)
950 {
951         struct pps_registers regs;
952
953         intel_pps_get_registers(intel_dp, &regs);
954
955         return regs.pp_ctrl;
956 }
957
958 static i915_reg_t
959 _pp_stat_reg(struct intel_dp *intel_dp)
960 {
961         struct pps_registers regs;
962
963         intel_pps_get_registers(intel_dp, &regs);
964
965         return regs.pp_stat;
966 }
967
968 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
969    This function only applicable when panel PM state is not to be tracked */
970 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
971                               void *unused)
972 {
973         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
974                                                  edp_notifier);
975         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
976
977         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
978                 return 0;
979
980         pps_lock(intel_dp);
981
982         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
983                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
984                 i915_reg_t pp_ctrl_reg, pp_div_reg;
985                 u32 pp_div;
986
987                 pp_ctrl_reg = PP_CONTROL(pipe);
988                 pp_div_reg  = PP_DIVISOR(pipe);
989                 pp_div = I915_READ(pp_div_reg);
990                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
991
992                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
993                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
994                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
995                 msleep(intel_dp->panel_power_cycle_delay);
996         }
997
998         pps_unlock(intel_dp);
999
1000         return 0;
1001 }
1002
1003 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1004 {
1005         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1006
1007         lockdep_assert_held(&dev_priv->pps_mutex);
1008
1009         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1010             intel_dp->pps_pipe == INVALID_PIPE)
1011                 return false;
1012
1013         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1014 }
1015
1016 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1017 {
1018         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1019
1020         lockdep_assert_held(&dev_priv->pps_mutex);
1021
1022         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1023             intel_dp->pps_pipe == INVALID_PIPE)
1024                 return false;
1025
1026         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1027 }
1028
1029 static void
1030 intel_dp_check_edp(struct intel_dp *intel_dp)
1031 {
1032         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1033
1034         if (!intel_dp_is_edp(intel_dp))
1035                 return;
1036
1037         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1038                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1039                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1040                               I915_READ(_pp_stat_reg(intel_dp)),
1041                               I915_READ(_pp_ctrl_reg(intel_dp)));
1042         }
1043 }
1044
1045 static uint32_t
1046 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1047 {
1048         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1049         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1050         uint32_t status;
1051         bool done;
1052
1053 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1054         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1055                                   msecs_to_jiffies_timeout(10));
1056         if (!done)
1057                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1058 #undef C
1059
1060         return status;
1061 }
1062
1063 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1064 {
1065         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1066
1067         if (index)
1068                 return 0;
1069
1070         /*
1071          * The clock divider is based off the hrawclk, and would like to run at
1072          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1073          */
1074         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1075 }
1076
1077 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1078 {
1079         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1080         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1081
1082         if (index)
1083                 return 0;
1084
1085         /*
1086          * The clock divider is based off the cdclk or PCH rawclk, and would
1087          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1088          * divide by 2000 and use that
1089          */
1090         if (dig_port->aux_ch == AUX_CH_A)
1091                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1092         else
1093                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1094 }
1095
1096 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1097 {
1098         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1099         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1100
1101         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1102                 /* Workaround for non-ULT HSW */
1103                 switch (index) {
1104                 case 0: return 63;
1105                 case 1: return 72;
1106                 default: return 0;
1107                 }
1108         }
1109
1110         return ilk_get_aux_clock_divider(intel_dp, index);
1111 }
1112
1113 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1114 {
1115         /*
1116          * SKL doesn't need us to program the AUX clock divider (Hardware will
1117          * derive the clock from CDCLK automatically). We still implement the
1118          * get_aux_clock_divider vfunc to plug-in into the existing code.
1119          */
1120         return index ? 0 : 1;
1121 }
1122
1123 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1124                                      int send_bytes,
1125                                      uint32_t aux_clock_divider)
1126 {
1127         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1128         struct drm_i915_private *dev_priv =
1129                         to_i915(intel_dig_port->base.base.dev);
1130         uint32_t precharge, timeout;
1131
1132         if (IS_GEN(dev_priv, 6))
1133                 precharge = 3;
1134         else
1135                 precharge = 5;
1136
1137         if (IS_BROADWELL(dev_priv))
1138                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1139         else
1140                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1141
1142         return DP_AUX_CH_CTL_SEND_BUSY |
1143                DP_AUX_CH_CTL_DONE |
1144                DP_AUX_CH_CTL_INTERRUPT |
1145                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1146                timeout |
1147                DP_AUX_CH_CTL_RECEIVE_ERROR |
1148                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1149                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1150                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1151 }
1152
1153 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1154                                       int send_bytes,
1155                                       uint32_t unused)
1156 {
1157         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1158         uint32_t ret;
1159
1160         ret = DP_AUX_CH_CTL_SEND_BUSY |
1161               DP_AUX_CH_CTL_DONE |
1162               DP_AUX_CH_CTL_INTERRUPT |
1163               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1164               DP_AUX_CH_CTL_TIME_OUT_MAX |
1165               DP_AUX_CH_CTL_RECEIVE_ERROR |
1166               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1167               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1168               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1169
1170         if (intel_dig_port->tc_type == TC_PORT_TBT)
1171                 ret |= DP_AUX_CH_CTL_TBT_IO;
1172
1173         return ret;
1174 }
1175
1176 static int
1177 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1178                   const uint8_t *send, int send_bytes,
1179                   uint8_t *recv, int recv_size,
1180                   u32 aux_send_ctl_flags)
1181 {
1182         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1183         struct drm_i915_private *dev_priv =
1184                         to_i915(intel_dig_port->base.base.dev);
1185         i915_reg_t ch_ctl, ch_data[5];
1186         uint32_t aux_clock_divider;
1187         int i, ret, recv_bytes;
1188         uint32_t status;
1189         int try, clock = 0;
1190         bool vdd;
1191
1192         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1193         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1194                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1195
1196         pps_lock(intel_dp);
1197
1198         /*
1199          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1200          * In such cases we want to leave VDD enabled and it's up to upper layers
1201          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1202          * ourselves.
1203          */
1204         vdd = edp_panel_vdd_on(intel_dp);
1205
1206         /* dp aux is extremely sensitive to irq latency, hence request the
1207          * lowest possible wakeup latency and so prevent the cpu from going into
1208          * deep sleep states.
1209          */
1210         pm_qos_update_request(&dev_priv->pm_qos, 0);
1211
1212         intel_dp_check_edp(intel_dp);
1213
1214         /* Try to wait for any previous AUX channel activity */
1215         for (try = 0; try < 3; try++) {
1216                 status = I915_READ_NOTRACE(ch_ctl);
1217                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1218                         break;
1219                 msleep(1);
1220         }
1221
1222         if (try == 3) {
1223                 static u32 last_status = -1;
1224                 const u32 status = I915_READ(ch_ctl);
1225
1226                 if (status != last_status) {
1227                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1228                              status);
1229                         last_status = status;
1230                 }
1231
1232                 ret = -EBUSY;
1233                 goto out;
1234         }
1235
1236         /* Only 5 data registers! */
1237         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1238                 ret = -E2BIG;
1239                 goto out;
1240         }
1241
1242         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1243                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1244                                                           send_bytes,
1245                                                           aux_clock_divider);
1246
1247                 send_ctl |= aux_send_ctl_flags;
1248
1249                 /* Must try at least 3 times according to DP spec */
1250                 for (try = 0; try < 5; try++) {
1251                         /* Load the send data into the aux channel data registers */
1252                         for (i = 0; i < send_bytes; i += 4)
1253                                 I915_WRITE(ch_data[i >> 2],
1254                                            intel_dp_pack_aux(send + i,
1255                                                              send_bytes - i));
1256
1257                         /* Send the command and wait for it to complete */
1258                         I915_WRITE(ch_ctl, send_ctl);
1259
1260                         status = intel_dp_aux_wait_done(intel_dp);
1261
1262                         /* Clear done status and any errors */
1263                         I915_WRITE(ch_ctl,
1264                                    status |
1265                                    DP_AUX_CH_CTL_DONE |
1266                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1267                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1268
1269                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1270                          *   400us delay required for errors and timeouts
1271                          *   Timeout errors from the HW already meet this
1272                          *   requirement so skip to next iteration
1273                          */
1274                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1275                                 continue;
1276
1277                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1278                                 usleep_range(400, 500);
1279                                 continue;
1280                         }
1281                         if (status & DP_AUX_CH_CTL_DONE)
1282                                 goto done;
1283                 }
1284         }
1285
1286         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1287                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1288                 ret = -EBUSY;
1289                 goto out;
1290         }
1291
1292 done:
1293         /* Check for timeout or receive error.
1294          * Timeouts occur when the sink is not connected
1295          */
1296         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1297                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1298                 ret = -EIO;
1299                 goto out;
1300         }
1301
1302         /* Timeouts occur when the device isn't connected, so they're
1303          * "normal" -- don't fill the kernel log with these */
1304         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1305                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1306                 ret = -ETIMEDOUT;
1307                 goto out;
1308         }
1309
1310         /* Unload any bytes sent back from the other side */
1311         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1312                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1313
1314         /*
1315          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1316          * We have no idea of what happened so we return -EBUSY so
1317          * drm layer takes care for the necessary retries.
1318          */
1319         if (recv_bytes == 0 || recv_bytes > 20) {
1320                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1321                               recv_bytes);
1322                 ret = -EBUSY;
1323                 goto out;
1324         }
1325
1326         if (recv_bytes > recv_size)
1327                 recv_bytes = recv_size;
1328
1329         for (i = 0; i < recv_bytes; i += 4)
1330                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1331                                     recv + i, recv_bytes - i);
1332
1333         ret = recv_bytes;
1334 out:
1335         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1336
1337         if (vdd)
1338                 edp_panel_vdd_off(intel_dp, false);
1339
1340         pps_unlock(intel_dp);
1341
1342         return ret;
1343 }
1344
1345 #define BARE_ADDRESS_SIZE       3
1346 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1347
1348 static void
1349 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1350                     const struct drm_dp_aux_msg *msg)
1351 {
1352         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1353         txbuf[1] = (msg->address >> 8) & 0xff;
1354         txbuf[2] = msg->address & 0xff;
1355         txbuf[3] = msg->size - 1;
1356 }
1357
1358 static ssize_t
1359 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1360 {
1361         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1362         uint8_t txbuf[20], rxbuf[20];
1363         size_t txsize, rxsize;
1364         int ret;
1365
1366         intel_dp_aux_header(txbuf, msg);
1367
1368         switch (msg->request & ~DP_AUX_I2C_MOT) {
1369         case DP_AUX_NATIVE_WRITE:
1370         case DP_AUX_I2C_WRITE:
1371         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1372                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1373                 rxsize = 2; /* 0 or 1 data bytes */
1374
1375                 if (WARN_ON(txsize > 20))
1376                         return -E2BIG;
1377
1378                 WARN_ON(!msg->buffer != !msg->size);
1379
1380                 if (msg->buffer)
1381                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1382
1383                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1384                                         rxbuf, rxsize, 0);
1385                 if (ret > 0) {
1386                         msg->reply = rxbuf[0] >> 4;
1387
1388                         if (ret > 1) {
1389                                 /* Number of bytes written in a short write. */
1390                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1391                         } else {
1392                                 /* Return payload size. */
1393                                 ret = msg->size;
1394                         }
1395                 }
1396                 break;
1397
1398         case DP_AUX_NATIVE_READ:
1399         case DP_AUX_I2C_READ:
1400                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1401                 rxsize = msg->size + 1;
1402
1403                 if (WARN_ON(rxsize > 20))
1404                         return -E2BIG;
1405
1406                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1407                                         rxbuf, rxsize, 0);
1408                 if (ret > 0) {
1409                         msg->reply = rxbuf[0] >> 4;
1410                         /*
1411                          * Assume happy day, and copy the data. The caller is
1412                          * expected to check msg->reply before touching it.
1413                          *
1414                          * Return payload size.
1415                          */
1416                         ret--;
1417                         memcpy(msg->buffer, rxbuf + 1, ret);
1418                 }
1419                 break;
1420
1421         default:
1422                 ret = -EINVAL;
1423                 break;
1424         }
1425
1426         return ret;
1427 }
1428
1429
1430 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1431 {
1432         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1433         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1434         enum aux_ch aux_ch = dig_port->aux_ch;
1435
1436         switch (aux_ch) {
1437         case AUX_CH_B:
1438         case AUX_CH_C:
1439         case AUX_CH_D:
1440                 return DP_AUX_CH_CTL(aux_ch);
1441         default:
1442                 MISSING_CASE(aux_ch);
1443                 return DP_AUX_CH_CTL(AUX_CH_B);
1444         }
1445 }
1446
1447 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1448 {
1449         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1450         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1451         enum aux_ch aux_ch = dig_port->aux_ch;
1452
1453         switch (aux_ch) {
1454         case AUX_CH_B:
1455         case AUX_CH_C:
1456         case AUX_CH_D:
1457                 return DP_AUX_CH_DATA(aux_ch, index);
1458         default:
1459                 MISSING_CASE(aux_ch);
1460                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1461         }
1462 }
1463
1464 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1465 {
1466         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1467         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1468         enum aux_ch aux_ch = dig_port->aux_ch;
1469
1470         switch (aux_ch) {
1471         case AUX_CH_A:
1472                 return DP_AUX_CH_CTL(aux_ch);
1473         case AUX_CH_B:
1474         case AUX_CH_C:
1475         case AUX_CH_D:
1476                 return PCH_DP_AUX_CH_CTL(aux_ch);
1477         default:
1478                 MISSING_CASE(aux_ch);
1479                 return DP_AUX_CH_CTL(AUX_CH_A);
1480         }
1481 }
1482
1483 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1484 {
1485         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1486         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1487         enum aux_ch aux_ch = dig_port->aux_ch;
1488
1489         switch (aux_ch) {
1490         case AUX_CH_A:
1491                 return DP_AUX_CH_DATA(aux_ch, index);
1492         case AUX_CH_B:
1493         case AUX_CH_C:
1494         case AUX_CH_D:
1495                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1496         default:
1497                 MISSING_CASE(aux_ch);
1498                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1499         }
1500 }
1501
1502 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1503 {
1504         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1505         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1506         enum aux_ch aux_ch = dig_port->aux_ch;
1507
1508         switch (aux_ch) {
1509         case AUX_CH_A:
1510         case AUX_CH_B:
1511         case AUX_CH_C:
1512         case AUX_CH_D:
1513         case AUX_CH_E:
1514         case AUX_CH_F:
1515                 return DP_AUX_CH_CTL(aux_ch);
1516         default:
1517                 MISSING_CASE(aux_ch);
1518                 return DP_AUX_CH_CTL(AUX_CH_A);
1519         }
1520 }
1521
1522 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1523 {
1524         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1525         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1526         enum aux_ch aux_ch = dig_port->aux_ch;
1527
1528         switch (aux_ch) {
1529         case AUX_CH_A:
1530         case AUX_CH_B:
1531         case AUX_CH_C:
1532         case AUX_CH_D:
1533         case AUX_CH_E:
1534         case AUX_CH_F:
1535                 return DP_AUX_CH_DATA(aux_ch, index);
1536         default:
1537                 MISSING_CASE(aux_ch);
1538                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1539         }
1540 }
1541
1542 static void
1543 intel_dp_aux_fini(struct intel_dp *intel_dp)
1544 {
1545         kfree(intel_dp->aux.name);
1546 }
1547
1548 static void
1549 intel_dp_aux_init(struct intel_dp *intel_dp)
1550 {
1551         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1552         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1553         struct intel_encoder *encoder = &dig_port->base;
1554
1555         if (INTEL_GEN(dev_priv) >= 9) {
1556                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1557                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1558         } else if (HAS_PCH_SPLIT(dev_priv)) {
1559                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1560                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1561         } else {
1562                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1563                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1564         }
1565
1566         if (INTEL_GEN(dev_priv) >= 9)
1567                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1568         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1569                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1570         else if (HAS_PCH_SPLIT(dev_priv))
1571                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1572         else
1573                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1574
1575         if (INTEL_GEN(dev_priv) >= 9)
1576                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1577         else
1578                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1579
1580         drm_dp_aux_init(&intel_dp->aux);
1581
1582         /* Failure to allocate our preferred name is not critical */
1583         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1584                                        port_name(encoder->port));
1585         intel_dp->aux.transfer = intel_dp_aux_transfer;
1586 }
1587
1588 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1589 {
1590         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1591
1592         return max_rate >= 540000;
1593 }
1594
1595 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1596 {
1597         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1598
1599         return max_rate >= 810000;
1600 }
1601
1602 static void
1603 intel_dp_set_clock(struct intel_encoder *encoder,
1604                    struct intel_crtc_state *pipe_config)
1605 {
1606         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1607         const struct dp_link_dpll *divisor = NULL;
1608         int i, count = 0;
1609
1610         if (IS_G4X(dev_priv)) {
1611                 divisor = g4x_dpll;
1612                 count = ARRAY_SIZE(g4x_dpll);
1613         } else if (HAS_PCH_SPLIT(dev_priv)) {
1614                 divisor = pch_dpll;
1615                 count = ARRAY_SIZE(pch_dpll);
1616         } else if (IS_CHERRYVIEW(dev_priv)) {
1617                 divisor = chv_dpll;
1618                 count = ARRAY_SIZE(chv_dpll);
1619         } else if (IS_VALLEYVIEW(dev_priv)) {
1620                 divisor = vlv_dpll;
1621                 count = ARRAY_SIZE(vlv_dpll);
1622         }
1623
1624         if (divisor && count) {
1625                 for (i = 0; i < count; i++) {
1626                         if (pipe_config->port_clock == divisor[i].clock) {
1627                                 pipe_config->dpll = divisor[i].dpll;
1628                                 pipe_config->clock_set = true;
1629                                 break;
1630                         }
1631                 }
1632         }
1633 }
1634
1635 static void snprintf_int_array(char *str, size_t len,
1636                                const int *array, int nelem)
1637 {
1638         int i;
1639
1640         str[0] = '\0';
1641
1642         for (i = 0; i < nelem; i++) {
1643                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1644                 if (r >= len)
1645                         return;
1646                 str += r;
1647                 len -= r;
1648         }
1649 }
1650
1651 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1652 {
1653         char str[128]; /* FIXME: too big for stack? */
1654
1655         if ((drm_debug & DRM_UT_KMS) == 0)
1656                 return;
1657
1658         snprintf_int_array(str, sizeof(str),
1659                            intel_dp->source_rates, intel_dp->num_source_rates);
1660         DRM_DEBUG_KMS("source rates: %s\n", str);
1661
1662         snprintf_int_array(str, sizeof(str),
1663                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1664         DRM_DEBUG_KMS("sink rates: %s\n", str);
1665
1666         snprintf_int_array(str, sizeof(str),
1667                            intel_dp->common_rates, intel_dp->num_common_rates);
1668         DRM_DEBUG_KMS("common rates: %s\n", str);
1669 }
1670
1671 int
1672 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1673 {
1674         int len;
1675
1676         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1677         if (WARN_ON(len <= 0))
1678                 return 162000;
1679
1680         return intel_dp->common_rates[len - 1];
1681 }
1682
1683 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1684 {
1685         int i = intel_dp_rate_index(intel_dp->sink_rates,
1686                                     intel_dp->num_sink_rates, rate);
1687
1688         if (WARN_ON(i < 0))
1689                 i = 0;
1690
1691         return i;
1692 }
1693
1694 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1695                            uint8_t *link_bw, uint8_t *rate_select)
1696 {
1697         /* eDP 1.4 rate select method. */
1698         if (intel_dp->use_rate_select) {
1699                 *link_bw = 0;
1700                 *rate_select =
1701                         intel_dp_rate_select(intel_dp, port_clock);
1702         } else {
1703                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1704                 *rate_select = 0;
1705         }
1706 }
1707
1708 struct link_config_limits {
1709         int min_clock, max_clock;
1710         int min_lane_count, max_lane_count;
1711         int min_bpp, max_bpp;
1712 };
1713
1714 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1715                                          const struct intel_crtc_state *pipe_config)
1716 {
1717         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1718
1719         return INTEL_GEN(dev_priv) >= 11 &&
1720                 pipe_config->cpu_transcoder != TRANSCODER_A;
1721 }
1722
1723 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1724                                   const struct intel_crtc_state *pipe_config)
1725 {
1726         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1727                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1728 }
1729
1730 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1731                                          const struct intel_crtc_state *pipe_config)
1732 {
1733         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1734
1735         return INTEL_GEN(dev_priv) >= 10 &&
1736                 pipe_config->cpu_transcoder != TRANSCODER_A;
1737 }
1738
1739 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1740                                   const struct intel_crtc_state *pipe_config)
1741 {
1742         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1743                 return false;
1744
1745         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1746                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1747 }
1748
1749 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1750                                 struct intel_crtc_state *pipe_config)
1751 {
1752         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1753         struct intel_connector *intel_connector = intel_dp->attached_connector;
1754         int bpp, bpc;
1755
1756         bpp = pipe_config->pipe_bpp;
1757         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1758
1759         if (bpc > 0)
1760                 bpp = min(bpp, 3*bpc);
1761
1762         if (intel_dp_is_edp(intel_dp)) {
1763                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1764                 if (intel_connector->base.display_info.bpc == 0 &&
1765                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1766                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1767                                       dev_priv->vbt.edp.bpp);
1768                         bpp = dev_priv->vbt.edp.bpp;
1769                 }
1770         }
1771
1772         return bpp;
1773 }
1774
1775 /* Adjust link config limits based on compliance test requests. */
1776 static void
1777 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1778                                   struct intel_crtc_state *pipe_config,
1779                                   struct link_config_limits *limits)
1780 {
1781         /* For DP Compliance we override the computed bpp for the pipe */
1782         if (intel_dp->compliance.test_data.bpc != 0) {
1783                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1784
1785                 limits->min_bpp = limits->max_bpp = bpp;
1786                 pipe_config->dither_force_disable = bpp == 6 * 3;
1787
1788                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1789         }
1790
1791         /* Use values requested by Compliance Test Request */
1792         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1793                 int index;
1794
1795                 /* Validate the compliance test data since max values
1796                  * might have changed due to link train fallback.
1797                  */
1798                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1799                                                intel_dp->compliance.test_lane_count)) {
1800                         index = intel_dp_rate_index(intel_dp->common_rates,
1801                                                     intel_dp->num_common_rates,
1802                                                     intel_dp->compliance.test_link_rate);
1803                         if (index >= 0)
1804                                 limits->min_clock = limits->max_clock = index;
1805                         limits->min_lane_count = limits->max_lane_count =
1806                                 intel_dp->compliance.test_lane_count;
1807                 }
1808         }
1809 }
1810
1811 /* Optimize link config in order: max bpp, min clock, min lanes */
1812 static bool
1813 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1814                                   struct intel_crtc_state *pipe_config,
1815                                   const struct link_config_limits *limits)
1816 {
1817         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1818         int bpp, clock, lane_count;
1819         int mode_rate, link_clock, link_avail;
1820
1821         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1822                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1823                                                    bpp);
1824
1825                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1826                         for (lane_count = limits->min_lane_count;
1827                              lane_count <= limits->max_lane_count;
1828                              lane_count <<= 1) {
1829                                 link_clock = intel_dp->common_rates[clock];
1830                                 link_avail = intel_dp_max_data_rate(link_clock,
1831                                                                     lane_count);
1832
1833                                 if (mode_rate <= link_avail) {
1834                                         pipe_config->lane_count = lane_count;
1835                                         pipe_config->pipe_bpp = bpp;
1836                                         pipe_config->port_clock = link_clock;
1837
1838                                         return true;
1839                                 }
1840                         }
1841                 }
1842         }
1843
1844         return false;
1845 }
1846
1847 /* Optimize link config in order: max bpp, min lanes, min clock */
1848 static bool
1849 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1850                                   struct intel_crtc_state *pipe_config,
1851                                   const struct link_config_limits *limits)
1852 {
1853         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1854         int bpp, clock, lane_count;
1855         int mode_rate, link_clock, link_avail;
1856
1857         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1858                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1859                                                    bpp);
1860
1861                 for (lane_count = limits->min_lane_count;
1862                      lane_count <= limits->max_lane_count;
1863                      lane_count <<= 1) {
1864                         for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1865                                 link_clock = intel_dp->common_rates[clock];
1866                                 link_avail = intel_dp_max_data_rate(link_clock,
1867                                                                     lane_count);
1868
1869                                 if (mode_rate <= link_avail) {
1870                                         pipe_config->lane_count = lane_count;
1871                                         pipe_config->pipe_bpp = bpp;
1872                                         pipe_config->port_clock = link_clock;
1873
1874                                         return true;
1875                                 }
1876                         }
1877                 }
1878         }
1879
1880         return false;
1881 }
1882
1883 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1884 {
1885         int i, num_bpc;
1886         u8 dsc_bpc[3] = {0};
1887
1888         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1889                                                        dsc_bpc);
1890         for (i = 0; i < num_bpc; i++) {
1891                 if (dsc_max_bpc >= dsc_bpc[i])
1892                         return dsc_bpc[i] * 3;
1893         }
1894
1895         return 0;
1896 }
1897
1898 static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1899                                         struct intel_crtc_state *pipe_config,
1900                                         struct drm_connector_state *conn_state,
1901                                         struct link_config_limits *limits)
1902 {
1903         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1904         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1905         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1906         u8 dsc_max_bpc;
1907         int pipe_bpp;
1908
1909         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1910                 return false;
1911
1912         dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
1913                             conn_state->max_requested_bpc);
1914
1915         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1916         if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
1917                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1918                 return false;
1919         }
1920
1921         /*
1922          * For now enable DSC for max bpp, max link rate, max lane count.
1923          * Optimize this later for the minimum possible link rate/lane count
1924          * with DSC enabled for the requested mode.
1925          */
1926         pipe_config->pipe_bpp = pipe_bpp;
1927         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1928         pipe_config->lane_count = limits->max_lane_count;
1929
1930         if (intel_dp_is_edp(intel_dp)) {
1931                 pipe_config->dsc_params.compressed_bpp =
1932                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1933                               pipe_config->pipe_bpp);
1934                 pipe_config->dsc_params.slice_count =
1935                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1936                                                         true);
1937         } else {
1938                 u16 dsc_max_output_bpp;
1939                 u8 dsc_dp_slice_count;
1940
1941                 dsc_max_output_bpp =
1942                         intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
1943                                                     pipe_config->lane_count,
1944                                                     adjusted_mode->crtc_clock,
1945                                                     adjusted_mode->crtc_hdisplay);
1946                 dsc_dp_slice_count =
1947                         intel_dp_dsc_get_slice_count(intel_dp,
1948                                                      adjusted_mode->crtc_clock,
1949                                                      adjusted_mode->crtc_hdisplay);
1950                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1951                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1952                         return false;
1953                 }
1954                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
1955                                                                dsc_max_output_bpp >> 4,
1956                                                                pipe_config->pipe_bpp);
1957                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
1958         }
1959         /*
1960          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1961          * is greater than the maximum Cdclock and if slice count is even
1962          * then we need to use 2 VDSC instances.
1963          */
1964         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
1965                 if (pipe_config->dsc_params.slice_count > 1) {
1966                         pipe_config->dsc_params.dsc_split = true;
1967                 } else {
1968                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1969                         return false;
1970                 }
1971         }
1972         if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
1973                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1974                               "Compressed BPP = %d\n",
1975                               pipe_config->pipe_bpp,
1976                               pipe_config->dsc_params.compressed_bpp);
1977                 return false;
1978         }
1979         pipe_config->dsc_params.compression_enable = true;
1980         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
1981                       "Compressed Bpp = %d Slice Count = %d\n",
1982                       pipe_config->pipe_bpp,
1983                       pipe_config->dsc_params.compressed_bpp,
1984                       pipe_config->dsc_params.slice_count);
1985
1986         return true;
1987 }
1988
1989 static bool
1990 intel_dp_compute_link_config(struct intel_encoder *encoder,
1991                              struct intel_crtc_state *pipe_config,
1992                              struct drm_connector_state *conn_state)
1993 {
1994         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1995         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1996         struct link_config_limits limits;
1997         int common_len;
1998         bool ret;
1999
2000         common_len = intel_dp_common_len_rate_limit(intel_dp,
2001                                                     intel_dp->max_link_rate);
2002
2003         /* No common link rates between source and sink */
2004         WARN_ON(common_len <= 0);
2005
2006         limits.min_clock = 0;
2007         limits.max_clock = common_len - 1;
2008
2009         limits.min_lane_count = 1;
2010         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2011
2012         limits.min_bpp = 6 * 3;
2013         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2014
2015         if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
2016                 /*
2017                  * Use the maximum clock and number of lanes the eDP panel
2018                  * advertizes being capable of. The eDP 1.3 and earlier panels
2019                  * are generally designed to support only a single clock and
2020                  * lane configuration, and typically these values correspond to
2021                  * the native resolution of the panel. With eDP 1.4 rate select
2022                  * and DSC, this is decreasingly the case, and we need to be
2023                  * able to select less than maximum link config.
2024                  */
2025                 limits.min_lane_count = limits.max_lane_count;
2026                 limits.min_clock = limits.max_clock;
2027         }
2028
2029         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2030
2031         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2032                       "max rate %d max bpp %d pixel clock %iKHz\n",
2033                       limits.max_lane_count,
2034                       intel_dp->common_rates[limits.max_clock],
2035                       limits.max_bpp, adjusted_mode->crtc_clock);
2036
2037         if (intel_dp_is_edp(intel_dp))
2038                 /*
2039                  * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
2040                  * section A.1: "It is recommended that the minimum number of
2041                  * lanes be used, using the minimum link rate allowed for that
2042                  * lane configuration."
2043                  *
2044                  * Note that we use the max clock and lane count for eDP 1.3 and
2045                  * earlier, and fast vs. wide is irrelevant.
2046                  */
2047                 ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
2048                                                         &limits);
2049         else
2050                 /* Optimize for slow and wide. */
2051                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2052                                                         &limits);
2053
2054         /* enable compression if the mode doesn't fit available BW */
2055         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2056         if (!ret || intel_dp->force_dsc_en) {
2057                 if (!intel_dp_dsc_compute_config(intel_dp, pipe_config,
2058                                                  conn_state, &limits))
2059                         return false;
2060         }
2061
2062         if (pipe_config->dsc_params.compression_enable) {
2063                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2064                               pipe_config->lane_count, pipe_config->port_clock,
2065                               pipe_config->pipe_bpp,
2066                               pipe_config->dsc_params.compressed_bpp);
2067
2068                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2069                               intel_dp_link_required(adjusted_mode->crtc_clock,
2070                                                      pipe_config->dsc_params.compressed_bpp),
2071                               intel_dp_max_data_rate(pipe_config->port_clock,
2072                                                      pipe_config->lane_count));
2073         } else {
2074                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2075                               pipe_config->lane_count, pipe_config->port_clock,
2076                               pipe_config->pipe_bpp);
2077
2078                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2079                               intel_dp_link_required(adjusted_mode->crtc_clock,
2080                                                      pipe_config->pipe_bpp),
2081                               intel_dp_max_data_rate(pipe_config->port_clock,
2082                                                      pipe_config->lane_count));
2083         }
2084         return true;
2085 }
2086
2087 bool
2088 intel_dp_compute_config(struct intel_encoder *encoder,
2089                         struct intel_crtc_state *pipe_config,
2090                         struct drm_connector_state *conn_state)
2091 {
2092         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2093         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2094         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2095         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2096         enum port port = encoder->port;
2097         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2098         struct intel_connector *intel_connector = intel_dp->attached_connector;
2099         struct intel_digital_connector_state *intel_conn_state =
2100                 to_intel_digital_connector_state(conn_state);
2101         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2102                                            DP_DPCD_QUIRK_CONSTANT_N);
2103
2104         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2105                 pipe_config->has_pch_encoder = true;
2106
2107         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2108         if (lspcon->active)
2109                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2110
2111         pipe_config->has_drrs = false;
2112         if (IS_G4X(dev_priv) || port == PORT_A)
2113                 pipe_config->has_audio = false;
2114         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2115                 pipe_config->has_audio = intel_dp->has_audio;
2116         else
2117                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2118
2119         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2120                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2121                                        adjusted_mode);
2122
2123                 if (INTEL_GEN(dev_priv) >= 9) {
2124                         int ret;
2125
2126                         ret = skl_update_scaler_crtc(pipe_config);
2127                         if (ret)
2128                                 return ret;
2129                 }
2130
2131                 if (HAS_GMCH_DISPLAY(dev_priv))
2132                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2133                                                  conn_state->scaling_mode);
2134                 else
2135                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2136                                                 conn_state->scaling_mode);
2137         }
2138
2139         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2140                 return false;
2141
2142         if (HAS_GMCH_DISPLAY(dev_priv) &&
2143             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2144                 return false;
2145
2146         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2147                 return false;
2148
2149         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2150                                   intel_dp_supports_fec(intel_dp, pipe_config);
2151
2152         if (!intel_dp_compute_link_config(encoder, pipe_config, conn_state))
2153                 return false;
2154
2155         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2156                 /*
2157                  * See:
2158                  * CEA-861-E - 5.1 Default Encoding Parameters
2159                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2160                  */
2161                 pipe_config->limited_color_range =
2162                         pipe_config->pipe_bpp != 18 &&
2163                         drm_default_rgb_quant_range(adjusted_mode) ==
2164                         HDMI_QUANTIZATION_RANGE_LIMITED;
2165         } else {
2166                 pipe_config->limited_color_range =
2167                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2168         }
2169
2170         if (!pipe_config->dsc_params.compression_enable)
2171                 intel_link_compute_m_n(pipe_config->pipe_bpp,
2172                                        pipe_config->lane_count,
2173                                        adjusted_mode->crtc_clock,
2174                                        pipe_config->port_clock,
2175                                        &pipe_config->dp_m_n,
2176                                        constant_n);
2177         else
2178                 intel_link_compute_m_n(pipe_config->dsc_params.compressed_bpp,
2179                                        pipe_config->lane_count,
2180                                        adjusted_mode->crtc_clock,
2181                                        pipe_config->port_clock,
2182                                        &pipe_config->dp_m_n,
2183                                        constant_n);
2184
2185         if (intel_connector->panel.downclock_mode != NULL &&
2186                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2187                         pipe_config->has_drrs = true;
2188                         intel_link_compute_m_n(pipe_config->pipe_bpp,
2189                                                pipe_config->lane_count,
2190                                                intel_connector->panel.downclock_mode->clock,
2191                                                pipe_config->port_clock,
2192                                                &pipe_config->dp_m2_n2,
2193                                                constant_n);
2194         }
2195
2196         if (!HAS_DDI(dev_priv))
2197                 intel_dp_set_clock(encoder, pipe_config);
2198
2199         intel_psr_compute_config(intel_dp, pipe_config);
2200
2201         return true;
2202 }
2203
2204 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2205                               int link_rate, uint8_t lane_count,
2206                               bool link_mst)
2207 {
2208         intel_dp->link_trained = false;
2209         intel_dp->link_rate = link_rate;
2210         intel_dp->lane_count = lane_count;
2211         intel_dp->link_mst = link_mst;
2212 }
2213
2214 static void intel_dp_prepare(struct intel_encoder *encoder,
2215                              const struct intel_crtc_state *pipe_config)
2216 {
2217         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2218         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2219         enum port port = encoder->port;
2220         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2221         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2222
2223         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2224                                  pipe_config->lane_count,
2225                                  intel_crtc_has_type(pipe_config,
2226                                                      INTEL_OUTPUT_DP_MST));
2227
2228         /*
2229          * There are four kinds of DP registers:
2230          *
2231          *      IBX PCH
2232          *      SNB CPU
2233          *      IVB CPU
2234          *      CPT PCH
2235          *
2236          * IBX PCH and CPU are the same for almost everything,
2237          * except that the CPU DP PLL is configured in this
2238          * register
2239          *
2240          * CPT PCH is quite different, having many bits moved
2241          * to the TRANS_DP_CTL register instead. That
2242          * configuration happens (oddly) in ironlake_pch_enable
2243          */
2244
2245         /* Preserve the BIOS-computed detected bit. This is
2246          * supposed to be read-only.
2247          */
2248         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2249
2250         /* Handle DP bits in common between all three register formats */
2251         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2252         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2253
2254         /* Split out the IBX/CPU vs CPT settings */
2255
2256         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2257                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2258                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2259                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2260                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2261                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2262
2263                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2264                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2265
2266                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2267         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2268                 u32 trans_dp;
2269
2270                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2271
2272                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2273                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2274                         trans_dp |= TRANS_DP_ENH_FRAMING;
2275                 else
2276                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2277                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2278         } else {
2279                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2280                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2281
2282                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2283                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2284                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2285                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2286                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2287
2288                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2289                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2290
2291                 if (IS_CHERRYVIEW(dev_priv))
2292                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2293                 else
2294                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2295         }
2296 }
2297
2298 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2299 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2300
2301 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2302 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2303
2304 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2305 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2306
2307 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2308
2309 static void wait_panel_status(struct intel_dp *intel_dp,
2310                                        u32 mask,
2311                                        u32 value)
2312 {
2313         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2314         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2315
2316         lockdep_assert_held(&dev_priv->pps_mutex);
2317
2318         intel_pps_verify_state(intel_dp);
2319
2320         pp_stat_reg = _pp_stat_reg(intel_dp);
2321         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2322
2323         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2324                         mask, value,
2325                         I915_READ(pp_stat_reg),
2326                         I915_READ(pp_ctrl_reg));
2327
2328         if (intel_wait_for_register(dev_priv,
2329                                     pp_stat_reg, mask, value,
2330                                     5000))
2331                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2332                                 I915_READ(pp_stat_reg),
2333                                 I915_READ(pp_ctrl_reg));
2334
2335         DRM_DEBUG_KMS("Wait complete\n");
2336 }
2337
2338 static void wait_panel_on(struct intel_dp *intel_dp)
2339 {
2340         DRM_DEBUG_KMS("Wait for panel power on\n");
2341         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2342 }
2343
2344 static void wait_panel_off(struct intel_dp *intel_dp)
2345 {
2346         DRM_DEBUG_KMS("Wait for panel power off time\n");
2347         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2348 }
2349
2350 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2351 {
2352         ktime_t panel_power_on_time;
2353         s64 panel_power_off_duration;
2354
2355         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2356
2357         /* take the difference of currrent time and panel power off time
2358          * and then make panel wait for t11_t12 if needed. */
2359         panel_power_on_time = ktime_get_boottime();
2360         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2361
2362         /* When we disable the VDD override bit last we have to do the manual
2363          * wait. */
2364         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2365                 wait_remaining_ms_from_jiffies(jiffies,
2366                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2367
2368         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2369 }
2370
2371 static void wait_backlight_on(struct intel_dp *intel_dp)
2372 {
2373         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2374                                        intel_dp->backlight_on_delay);
2375 }
2376
2377 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2378 {
2379         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2380                                        intel_dp->backlight_off_delay);
2381 }
2382
2383 /* Read the current pp_control value, unlocking the register if it
2384  * is locked
2385  */
2386
2387 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2388 {
2389         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2390         u32 control;
2391
2392         lockdep_assert_held(&dev_priv->pps_mutex);
2393
2394         control = I915_READ(_pp_ctrl_reg(intel_dp));
2395         if (WARN_ON(!HAS_DDI(dev_priv) &&
2396                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2397                 control &= ~PANEL_UNLOCK_MASK;
2398                 control |= PANEL_UNLOCK_REGS;
2399         }
2400         return control;
2401 }
2402
2403 /*
2404  * Must be paired with edp_panel_vdd_off().
2405  * Must hold pps_mutex around the whole on/off sequence.
2406  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2407  */
2408 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2409 {
2410         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2411         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2412         u32 pp;
2413         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2414         bool need_to_disable = !intel_dp->want_panel_vdd;
2415
2416         lockdep_assert_held(&dev_priv->pps_mutex);
2417
2418         if (!intel_dp_is_edp(intel_dp))
2419                 return false;
2420
2421         cancel_delayed_work(&intel_dp->panel_vdd_work);
2422         intel_dp->want_panel_vdd = true;
2423
2424         if (edp_have_panel_vdd(intel_dp))
2425                 return need_to_disable;
2426
2427         intel_display_power_get(dev_priv,
2428                                 intel_aux_power_domain(intel_dig_port));
2429
2430         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2431                       port_name(intel_dig_port->base.port));
2432
2433         if (!edp_have_panel_power(intel_dp))
2434                 wait_panel_power_cycle(intel_dp);
2435
2436         pp = ironlake_get_pp_control(intel_dp);
2437         pp |= EDP_FORCE_VDD;
2438
2439         pp_stat_reg = _pp_stat_reg(intel_dp);
2440         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2441
2442         I915_WRITE(pp_ctrl_reg, pp);
2443         POSTING_READ(pp_ctrl_reg);
2444         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2445                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2446         /*
2447          * If the panel wasn't on, delay before accessing aux channel
2448          */
2449         if (!edp_have_panel_power(intel_dp)) {
2450                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2451                               port_name(intel_dig_port->base.port));
2452                 msleep(intel_dp->panel_power_up_delay);
2453         }
2454
2455         return need_to_disable;
2456 }
2457
2458 /*
2459  * Must be paired with intel_edp_panel_vdd_off() or
2460  * intel_edp_panel_off().
2461  * Nested calls to these functions are not allowed since
2462  * we drop the lock. Caller must use some higher level
2463  * locking to prevent nested calls from other threads.
2464  */
2465 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2466 {
2467         bool vdd;
2468
2469         if (!intel_dp_is_edp(intel_dp))
2470                 return;
2471
2472         pps_lock(intel_dp);
2473         vdd = edp_panel_vdd_on(intel_dp);
2474         pps_unlock(intel_dp);
2475
2476         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2477              port_name(dp_to_dig_port(intel_dp)->base.port));
2478 }
2479
2480 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2481 {
2482         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2483         struct intel_digital_port *intel_dig_port =
2484                 dp_to_dig_port(intel_dp);
2485         u32 pp;
2486         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2487
2488         lockdep_assert_held(&dev_priv->pps_mutex);
2489
2490         WARN_ON(intel_dp->want_panel_vdd);
2491
2492         if (!edp_have_panel_vdd(intel_dp))
2493                 return;
2494
2495         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2496                       port_name(intel_dig_port->base.port));
2497
2498         pp = ironlake_get_pp_control(intel_dp);
2499         pp &= ~EDP_FORCE_VDD;
2500
2501         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2502         pp_stat_reg = _pp_stat_reg(intel_dp);
2503
2504         I915_WRITE(pp_ctrl_reg, pp);
2505         POSTING_READ(pp_ctrl_reg);
2506
2507         /* Make sure sequencer is idle before allowing subsequent activity */
2508         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2509         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2510
2511         if ((pp & PANEL_POWER_ON) == 0)
2512                 intel_dp->panel_power_off_time = ktime_get_boottime();
2513
2514         intel_display_power_put(dev_priv,
2515                                 intel_aux_power_domain(intel_dig_port));
2516 }
2517
2518 static void edp_panel_vdd_work(struct work_struct *__work)
2519 {
2520         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2521                                                  struct intel_dp, panel_vdd_work);
2522
2523         pps_lock(intel_dp);
2524         if (!intel_dp->want_panel_vdd)
2525                 edp_panel_vdd_off_sync(intel_dp);
2526         pps_unlock(intel_dp);
2527 }
2528
2529 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2530 {
2531         unsigned long delay;
2532
2533         /*
2534          * Queue the timer to fire a long time from now (relative to the power
2535          * down delay) to keep the panel power up across a sequence of
2536          * operations.
2537          */
2538         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2539         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2540 }
2541
2542 /*
2543  * Must be paired with edp_panel_vdd_on().
2544  * Must hold pps_mutex around the whole on/off sequence.
2545  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2546  */
2547 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2548 {
2549         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2550
2551         lockdep_assert_held(&dev_priv->pps_mutex);
2552
2553         if (!intel_dp_is_edp(intel_dp))
2554                 return;
2555
2556         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2557              port_name(dp_to_dig_port(intel_dp)->base.port));
2558
2559         intel_dp->want_panel_vdd = false;
2560
2561         if (sync)
2562                 edp_panel_vdd_off_sync(intel_dp);
2563         else
2564                 edp_panel_vdd_schedule_off(intel_dp);
2565 }
2566
2567 static void edp_panel_on(struct intel_dp *intel_dp)
2568 {
2569         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2570         u32 pp;
2571         i915_reg_t pp_ctrl_reg;
2572
2573         lockdep_assert_held(&dev_priv->pps_mutex);
2574
2575         if (!intel_dp_is_edp(intel_dp))
2576                 return;
2577
2578         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2579                       port_name(dp_to_dig_port(intel_dp)->base.port));
2580
2581         if (WARN(edp_have_panel_power(intel_dp),
2582                  "eDP port %c panel power already on\n",
2583                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2584                 return;
2585
2586         wait_panel_power_cycle(intel_dp);
2587
2588         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2589         pp = ironlake_get_pp_control(intel_dp);
2590         if (IS_GEN(dev_priv, 5)) {
2591                 /* ILK workaround: disable reset around power sequence */
2592                 pp &= ~PANEL_POWER_RESET;
2593                 I915_WRITE(pp_ctrl_reg, pp);
2594                 POSTING_READ(pp_ctrl_reg);
2595         }
2596
2597         pp |= PANEL_POWER_ON;
2598         if (!IS_GEN(dev_priv, 5))
2599                 pp |= PANEL_POWER_RESET;
2600
2601         I915_WRITE(pp_ctrl_reg, pp);
2602         POSTING_READ(pp_ctrl_reg);
2603
2604         wait_panel_on(intel_dp);
2605         intel_dp->last_power_on = jiffies;
2606
2607         if (IS_GEN(dev_priv, 5)) {
2608                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2609                 I915_WRITE(pp_ctrl_reg, pp);
2610                 POSTING_READ(pp_ctrl_reg);
2611         }
2612 }
2613
2614 void intel_edp_panel_on(struct intel_dp *intel_dp)
2615 {
2616         if (!intel_dp_is_edp(intel_dp))
2617                 return;
2618
2619         pps_lock(intel_dp);
2620         edp_panel_on(intel_dp);
2621         pps_unlock(intel_dp);
2622 }
2623
2624
2625 static void edp_panel_off(struct intel_dp *intel_dp)
2626 {
2627         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2628         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2629         u32 pp;
2630         i915_reg_t pp_ctrl_reg;
2631
2632         lockdep_assert_held(&dev_priv->pps_mutex);
2633
2634         if (!intel_dp_is_edp(intel_dp))
2635                 return;
2636
2637         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2638                       port_name(dig_port->base.port));
2639
2640         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2641              port_name(dig_port->base.port));
2642
2643         pp = ironlake_get_pp_control(intel_dp);
2644         /* We need to switch off panel power _and_ force vdd, for otherwise some
2645          * panels get very unhappy and cease to work. */
2646         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2647                 EDP_BLC_ENABLE);
2648
2649         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2650
2651         intel_dp->want_panel_vdd = false;
2652
2653         I915_WRITE(pp_ctrl_reg, pp);
2654         POSTING_READ(pp_ctrl_reg);
2655
2656         wait_panel_off(intel_dp);
2657         intel_dp->panel_power_off_time = ktime_get_boottime();
2658
2659         /* We got a reference when we enabled the VDD. */
2660         intel_display_power_put(dev_priv, intel_aux_power_domain(dig_port));
2661 }
2662
2663 void intel_edp_panel_off(struct intel_dp *intel_dp)
2664 {
2665         if (!intel_dp_is_edp(intel_dp))
2666                 return;
2667
2668         pps_lock(intel_dp);
2669         edp_panel_off(intel_dp);
2670         pps_unlock(intel_dp);
2671 }
2672
2673 /* Enable backlight in the panel power control. */
2674 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2675 {
2676         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2677         u32 pp;
2678         i915_reg_t pp_ctrl_reg;
2679
2680         /*
2681          * If we enable the backlight right away following a panel power
2682          * on, we may see slight flicker as the panel syncs with the eDP
2683          * link.  So delay a bit to make sure the image is solid before
2684          * allowing it to appear.
2685          */
2686         wait_backlight_on(intel_dp);
2687
2688         pps_lock(intel_dp);
2689
2690         pp = ironlake_get_pp_control(intel_dp);
2691         pp |= EDP_BLC_ENABLE;
2692
2693         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2694
2695         I915_WRITE(pp_ctrl_reg, pp);
2696         POSTING_READ(pp_ctrl_reg);
2697
2698         pps_unlock(intel_dp);
2699 }
2700
2701 /* Enable backlight PWM and backlight PP control. */
2702 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2703                             const struct drm_connector_state *conn_state)
2704 {
2705         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2706
2707         if (!intel_dp_is_edp(intel_dp))
2708                 return;
2709
2710         DRM_DEBUG_KMS("\n");
2711
2712         intel_panel_enable_backlight(crtc_state, conn_state);
2713         _intel_edp_backlight_on(intel_dp);
2714 }
2715
2716 /* Disable backlight in the panel power control. */
2717 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2718 {
2719         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2720         u32 pp;
2721         i915_reg_t pp_ctrl_reg;
2722
2723         if (!intel_dp_is_edp(intel_dp))
2724                 return;
2725
2726         pps_lock(intel_dp);
2727
2728         pp = ironlake_get_pp_control(intel_dp);
2729         pp &= ~EDP_BLC_ENABLE;
2730
2731         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2732
2733         I915_WRITE(pp_ctrl_reg, pp);
2734         POSTING_READ(pp_ctrl_reg);
2735
2736         pps_unlock(intel_dp);
2737
2738         intel_dp->last_backlight_off = jiffies;
2739         edp_wait_backlight_off(intel_dp);
2740 }
2741
2742 /* Disable backlight PP control and backlight PWM. */
2743 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2744 {
2745         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2746
2747         if (!intel_dp_is_edp(intel_dp))
2748                 return;
2749
2750         DRM_DEBUG_KMS("\n");
2751
2752         _intel_edp_backlight_off(intel_dp);
2753         intel_panel_disable_backlight(old_conn_state);
2754 }
2755
2756 /*
2757  * Hook for controlling the panel power control backlight through the bl_power
2758  * sysfs attribute. Take care to handle multiple calls.
2759  */
2760 static void intel_edp_backlight_power(struct intel_connector *connector,
2761                                       bool enable)
2762 {
2763         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2764         bool is_enabled;
2765
2766         pps_lock(intel_dp);
2767         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2768         pps_unlock(intel_dp);
2769
2770         if (is_enabled == enable)
2771                 return;
2772
2773         DRM_DEBUG_KMS("panel power control backlight %s\n",
2774                       enable ? "enable" : "disable");
2775
2776         if (enable)
2777                 _intel_edp_backlight_on(intel_dp);
2778         else
2779                 _intel_edp_backlight_off(intel_dp);
2780 }
2781
2782 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2783 {
2784         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2785         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2786         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2787
2788         I915_STATE_WARN(cur_state != state,
2789                         "DP port %c state assertion failure (expected %s, current %s)\n",
2790                         port_name(dig_port->base.port),
2791                         onoff(state), onoff(cur_state));
2792 }
2793 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2794
2795 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2796 {
2797         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2798
2799         I915_STATE_WARN(cur_state != state,
2800                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2801                         onoff(state), onoff(cur_state));
2802 }
2803 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2804 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2805
2806 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2807                                 const struct intel_crtc_state *pipe_config)
2808 {
2809         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2810         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2811
2812         assert_pipe_disabled(dev_priv, crtc->pipe);
2813         assert_dp_port_disabled(intel_dp);
2814         assert_edp_pll_disabled(dev_priv);
2815
2816         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2817                       pipe_config->port_clock);
2818
2819         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2820
2821         if (pipe_config->port_clock == 162000)
2822                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2823         else
2824                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2825
2826         I915_WRITE(DP_A, intel_dp->DP);
2827         POSTING_READ(DP_A);
2828         udelay(500);
2829
2830         /*
2831          * [DevILK] Work around required when enabling DP PLL
2832          * while a pipe is enabled going to FDI:
2833          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2834          * 2. Program DP PLL enable
2835          */
2836         if (IS_GEN(dev_priv, 5))
2837                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2838
2839         intel_dp->DP |= DP_PLL_ENABLE;
2840
2841         I915_WRITE(DP_A, intel_dp->DP);
2842         POSTING_READ(DP_A);
2843         udelay(200);
2844 }
2845
2846 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2847                                  const struct intel_crtc_state *old_crtc_state)
2848 {
2849         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2850         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2851
2852         assert_pipe_disabled(dev_priv, crtc->pipe);
2853         assert_dp_port_disabled(intel_dp);
2854         assert_edp_pll_enabled(dev_priv);
2855
2856         DRM_DEBUG_KMS("disabling eDP PLL\n");
2857
2858         intel_dp->DP &= ~DP_PLL_ENABLE;
2859
2860         I915_WRITE(DP_A, intel_dp->DP);
2861         POSTING_READ(DP_A);
2862         udelay(200);
2863 }
2864
2865 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2866 {
2867         /*
2868          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2869          * be capable of signalling downstream hpd with a long pulse.
2870          * Whether or not that means D3 is safe to use is not clear,
2871          * but let's assume so until proven otherwise.
2872          *
2873          * FIXME should really check all downstream ports...
2874          */
2875         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2876                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2877                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2878 }
2879
2880 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2881                                            const struct intel_crtc_state *crtc_state,
2882                                            bool enable)
2883 {
2884         int ret;
2885
2886         if (!crtc_state->dsc_params.compression_enable)
2887                 return;
2888
2889         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2890                                  enable ? DP_DECOMPRESSION_EN : 0);
2891         if (ret < 0)
2892                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2893                               enable ? "enable" : "disable");
2894 }
2895
2896 /* If the sink supports it, try to set the power state appropriately */
2897 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2898 {
2899         int ret, i;
2900
2901         /* Should have a valid DPCD by this point */
2902         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2903                 return;
2904
2905         if (mode != DRM_MODE_DPMS_ON) {
2906                 if (downstream_hpd_needs_d0(intel_dp))
2907                         return;
2908
2909                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2910                                          DP_SET_POWER_D3);
2911         } else {
2912                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2913
2914                 /*
2915                  * When turning on, we need to retry for 1ms to give the sink
2916                  * time to wake up.
2917                  */
2918                 for (i = 0; i < 3; i++) {
2919                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2920                                                  DP_SET_POWER_D0);
2921                         if (ret == 1)
2922                                 break;
2923                         msleep(1);
2924                 }
2925
2926                 if (ret == 1 && lspcon->active)
2927                         lspcon_wait_pcon_mode(lspcon);
2928         }
2929
2930         if (ret != 1)
2931                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2932                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2933 }
2934
2935 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2936                                  enum port port, enum pipe *pipe)
2937 {
2938         enum pipe p;
2939
2940         for_each_pipe(dev_priv, p) {
2941                 u32 val = I915_READ(TRANS_DP_CTL(p));
2942
2943                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2944                         *pipe = p;
2945                         return true;
2946                 }
2947         }
2948
2949         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2950
2951         /* must initialize pipe to something for the asserts */
2952         *pipe = PIPE_A;
2953
2954         return false;
2955 }
2956
2957 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2958                            i915_reg_t dp_reg, enum port port,
2959                            enum pipe *pipe)
2960 {
2961         bool ret;
2962         u32 val;
2963
2964         val = I915_READ(dp_reg);
2965
2966         ret = val & DP_PORT_EN;
2967
2968         /* asserts want to know the pipe even if the port is disabled */
2969         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2970                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2971         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2972                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2973         else if (IS_CHERRYVIEW(dev_priv))
2974                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2975         else
2976                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2977
2978         return ret;
2979 }
2980
2981 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2982                                   enum pipe *pipe)
2983 {
2984         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2985         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2986         bool ret;
2987
2988         if (!intel_display_power_get_if_enabled(dev_priv,
2989                                                 encoder->power_domain))
2990                 return false;
2991
2992         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2993                                     encoder->port, pipe);
2994
2995         intel_display_power_put(dev_priv, encoder->power_domain);
2996
2997         return ret;
2998 }
2999
3000 static void intel_dp_get_config(struct intel_encoder *encoder,
3001                                 struct intel_crtc_state *pipe_config)
3002 {
3003         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3004         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3005         u32 tmp, flags = 0;
3006         enum port port = encoder->port;
3007         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3008
3009         if (encoder->type == INTEL_OUTPUT_EDP)
3010                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3011         else
3012                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3013
3014         tmp = I915_READ(intel_dp->output_reg);
3015
3016         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3017
3018         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3019                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3020
3021                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3022                         flags |= DRM_MODE_FLAG_PHSYNC;
3023                 else
3024                         flags |= DRM_MODE_FLAG_NHSYNC;
3025
3026                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3027                         flags |= DRM_MODE_FLAG_PVSYNC;
3028                 else
3029                         flags |= DRM_MODE_FLAG_NVSYNC;
3030         } else {
3031                 if (tmp & DP_SYNC_HS_HIGH)
3032                         flags |= DRM_MODE_FLAG_PHSYNC;
3033                 else
3034                         flags |= DRM_MODE_FLAG_NHSYNC;
3035
3036                 if (tmp & DP_SYNC_VS_HIGH)
3037                         flags |= DRM_MODE_FLAG_PVSYNC;
3038                 else
3039                         flags |= DRM_MODE_FLAG_NVSYNC;
3040         }
3041
3042         pipe_config->base.adjusted_mode.flags |= flags;
3043
3044         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3045                 pipe_config->limited_color_range = true;
3046
3047         pipe_config->lane_count =
3048                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3049
3050         intel_dp_get_m_n(crtc, pipe_config);
3051
3052         if (port == PORT_A) {
3053                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3054                         pipe_config->port_clock = 162000;
3055                 else
3056                         pipe_config->port_clock = 270000;
3057         }
3058
3059         pipe_config->base.adjusted_mode.crtc_clock =
3060                 intel_dotclock_calculate(pipe_config->port_clock,
3061                                          &pipe_config->dp_m_n);
3062
3063         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3064             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3065                 /*
3066                  * This is a big fat ugly hack.
3067                  *
3068                  * Some machines in UEFI boot mode provide us a VBT that has 18
3069                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3070                  * unknown we fail to light up. Yet the same BIOS boots up with
3071                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3072                  * max, not what it tells us to use.
3073                  *
3074                  * Note: This will still be broken if the eDP panel is not lit
3075                  * up by the BIOS, and thus we can't get the mode at module
3076                  * load.
3077                  */
3078                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3079                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3080                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3081         }
3082 }
3083
3084 static void intel_disable_dp(struct intel_encoder *encoder,
3085                              const struct intel_crtc_state *old_crtc_state,
3086                              const struct drm_connector_state *old_conn_state)
3087 {
3088         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3089
3090         intel_dp->link_trained = false;
3091
3092         if (old_crtc_state->has_audio)
3093                 intel_audio_codec_disable(encoder,
3094                                           old_crtc_state, old_conn_state);
3095
3096         /* Make sure the panel is off before trying to change the mode. But also
3097          * ensure that we have vdd while we switch off the panel. */
3098         intel_edp_panel_vdd_on(intel_dp);
3099         intel_edp_backlight_off(old_conn_state);
3100         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3101         intel_edp_panel_off(intel_dp);
3102 }
3103
3104 static void g4x_disable_dp(struct intel_encoder *encoder,
3105                            const struct intel_crtc_state *old_crtc_state,
3106                            const struct drm_connector_state *old_conn_state)
3107 {
3108         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3109 }
3110
3111 static void vlv_disable_dp(struct intel_encoder *encoder,
3112                            const struct intel_crtc_state *old_crtc_state,
3113                            const struct drm_connector_state *old_conn_state)
3114 {
3115         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3116 }
3117
3118 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3119                                 const struct intel_crtc_state *old_crtc_state,
3120                                 const struct drm_connector_state *old_conn_state)
3121 {
3122         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3123         enum port port = encoder->port;
3124