Merge tag 'drm-misc-next-2019-01-16' of git://anongit.freedesktop.org/drm/drm-misc...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Keith Packard <keithp@keithp.com>
25  *
26  */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
35 #include <drm/drmP.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_hdcp.h>
42 #include "intel_drv.h"
43 #include <drm/i915_drm.h>
44 #include "i915_drv.h"
45
46 #define DP_DPRX_ESI_LEN 14
47
48 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
49 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER      61440
50 #define DP_DSC_MIN_SUPPORTED_BPC                8
51 #define DP_DSC_MAX_SUPPORTED_BPC                10
52
53 /* DP DSC throughput values used for slice count calculations KPixels/s */
54 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
55 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
56 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
57
58 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
59 #define DP_DSC_FEC_OVERHEAD_FACTOR              976
60
61 /* Compliance test status bits  */
62 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
63 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
64 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
65 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
66
67 struct dp_link_dpll {
68         int clock;
69         struct dpll dpll;
70 };
71
72 static const struct dp_link_dpll g4x_dpll[] = {
73         { 162000,
74                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
75         { 270000,
76                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
77 };
78
79 static const struct dp_link_dpll pch_dpll[] = {
80         { 162000,
81                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
82         { 270000,
83                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
84 };
85
86 static const struct dp_link_dpll vlv_dpll[] = {
87         { 162000,
88                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
89         { 270000,
90                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
91 };
92
93 /*
94  * CHV supports eDP 1.4 that have  more link rates.
95  * Below only provides the fixed rate but exclude variable rate.
96  */
97 static const struct dp_link_dpll chv_dpll[] = {
98         /*
99          * CHV requires to program fractional division for m2.
100          * m2 is stored in fixed point format using formula below
101          * (m2_int << 22) | m2_fraction
102          */
103         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
104                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
105         { 270000,       /* m2_int = 27, m2_fraction = 0 */
106                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
107 };
108
109 /* Constants for DP DSC configurations */
110 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
111
112 /* With Single pipe configuration, HW is capable of supporting maximum
113  * of 4 slices per line.
114  */
115 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
116
117 /**
118  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
119  * @intel_dp: DP struct
120  *
121  * If a CPU or PCH DP output is attached to an eDP panel, this function
122  * will return true, and false otherwise.
123  */
124 bool intel_dp_is_edp(struct intel_dp *intel_dp)
125 {
126         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
127
128         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
129 }
130
131 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
132 {
133         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
134 }
135
136 static void intel_dp_link_down(struct intel_encoder *encoder,
137                                const struct intel_crtc_state *old_crtc_state);
138 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
139 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
140 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
141                                            const struct intel_crtc_state *crtc_state);
142 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
143                                       enum pipe pipe);
144 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
145
146 /* update sink rates from dpcd */
147 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
148 {
149         static const int dp_rates[] = {
150                 162000, 270000, 540000, 810000
151         };
152         int i, max_rate;
153
154         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
155
156         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
157                 if (dp_rates[i] > max_rate)
158                         break;
159                 intel_dp->sink_rates[i] = dp_rates[i];
160         }
161
162         intel_dp->num_sink_rates = i;
163 }
164
165 /* Get length of rates array potentially limited by max_rate. */
166 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
167 {
168         int i;
169
170         /* Limit results by potentially reduced max rate */
171         for (i = 0; i < len; i++) {
172                 if (rates[len - i - 1] <= max_rate)
173                         return len - i;
174         }
175
176         return 0;
177 }
178
179 /* Get length of common rates array potentially limited by max_rate. */
180 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
181                                           int max_rate)
182 {
183         return intel_dp_rate_limit_len(intel_dp->common_rates,
184                                        intel_dp->num_common_rates, max_rate);
185 }
186
187 /* Theoretical max between source and sink */
188 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
189 {
190         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
191 }
192
193 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
194 {
195         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
196         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
197         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
198         u32 lane_info;
199
200         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
201                 return 4;
202
203         lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
204                      DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
205                     DP_LANE_ASSIGNMENT_SHIFT(tc_port);
206
207         switch (lane_info) {
208         default:
209                 MISSING_CASE(lane_info);
210         case 1:
211         case 2:
212         case 4:
213         case 8:
214                 return 1;
215         case 3:
216         case 12:
217                 return 2;
218         case 15:
219                 return 4;
220         }
221 }
222
223 /* Theoretical max between source and sink */
224 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
225 {
226         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
227         int source_max = intel_dig_port->max_lanes;
228         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
229         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
230
231         return min3(source_max, sink_max, fia_max);
232 }
233
234 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
235 {
236         return intel_dp->max_link_lane_count;
237 }
238
239 int
240 intel_dp_link_required(int pixel_clock, int bpp)
241 {
242         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
243         return DIV_ROUND_UP(pixel_clock * bpp, 8);
244 }
245
246 int
247 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
248 {
249         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
250          * link rate that is generally expressed in Gbps. Since, 8 bits of data
251          * is transmitted every LS_Clk per lane, there is no need to account for
252          * the channel encoding that is done in the PHY layer here.
253          */
254
255         return max_link_clock * max_lanes;
256 }
257
258 static int
259 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
260 {
261         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
262         struct intel_encoder *encoder = &intel_dig_port->base;
263         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
264         int max_dotclk = dev_priv->max_dotclk_freq;
265         int ds_max_dotclk;
266
267         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
268
269         if (type != DP_DS_PORT_TYPE_VGA)
270                 return max_dotclk;
271
272         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
273                                                     intel_dp->downstream_ports);
274
275         if (ds_max_dotclk != 0)
276                 max_dotclk = min(max_dotclk, ds_max_dotclk);
277
278         return max_dotclk;
279 }
280
281 static int cnl_max_source_rate(struct intel_dp *intel_dp)
282 {
283         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
284         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
285         enum port port = dig_port->base.port;
286
287         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
288
289         /* Low voltage SKUs are limited to max of 5.4G */
290         if (voltage == VOLTAGE_INFO_0_85V)
291                 return 540000;
292
293         /* For this SKU 8.1G is supported in all ports */
294         if (IS_CNL_WITH_PORT_F(dev_priv))
295                 return 810000;
296
297         /* For other SKUs, max rate on ports A and D is 5.4G */
298         if (port == PORT_A || port == PORT_D)
299                 return 540000;
300
301         return 810000;
302 }
303
304 static int icl_max_source_rate(struct intel_dp *intel_dp)
305 {
306         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
307         enum port port = dig_port->base.port;
308
309         if (port == PORT_B)
310                 return 540000;
311
312         return 810000;
313 }
314
315 static void
316 intel_dp_set_source_rates(struct intel_dp *intel_dp)
317 {
318         /* The values must be in increasing order */
319         static const int cnl_rates[] = {
320                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
321         };
322         static const int bxt_rates[] = {
323                 162000, 216000, 243000, 270000, 324000, 432000, 540000
324         };
325         static const int skl_rates[] = {
326                 162000, 216000, 270000, 324000, 432000, 540000
327         };
328         static const int hsw_rates[] = {
329                 162000, 270000, 540000
330         };
331         static const int g4x_rates[] = {
332                 162000, 270000
333         };
334         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
335         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
336         const struct ddi_vbt_port_info *info =
337                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
338         const int *source_rates;
339         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
340
341         /* This should only be done once */
342         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
343
344         if (INTEL_GEN(dev_priv) >= 10) {
345                 source_rates = cnl_rates;
346                 size = ARRAY_SIZE(cnl_rates);
347                 if (IS_GEN10(dev_priv))
348                         max_rate = cnl_max_source_rate(intel_dp);
349                 else
350                         max_rate = icl_max_source_rate(intel_dp);
351         } else if (IS_GEN9_LP(dev_priv)) {
352                 source_rates = bxt_rates;
353                 size = ARRAY_SIZE(bxt_rates);
354         } else if (IS_GEN9_BC(dev_priv)) {
355                 source_rates = skl_rates;
356                 size = ARRAY_SIZE(skl_rates);
357         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
358                    IS_BROADWELL(dev_priv)) {
359                 source_rates = hsw_rates;
360                 size = ARRAY_SIZE(hsw_rates);
361         } else {
362                 source_rates = g4x_rates;
363                 size = ARRAY_SIZE(g4x_rates);
364         }
365
366         if (max_rate && vbt_max_rate)
367                 max_rate = min(max_rate, vbt_max_rate);
368         else if (vbt_max_rate)
369                 max_rate = vbt_max_rate;
370
371         if (max_rate)
372                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
373
374         intel_dp->source_rates = source_rates;
375         intel_dp->num_source_rates = size;
376 }
377
378 static int intersect_rates(const int *source_rates, int source_len,
379                            const int *sink_rates, int sink_len,
380                            int *common_rates)
381 {
382         int i = 0, j = 0, k = 0;
383
384         while (i < source_len && j < sink_len) {
385                 if (source_rates[i] == sink_rates[j]) {
386                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
387                                 return k;
388                         common_rates[k] = source_rates[i];
389                         ++k;
390                         ++i;
391                         ++j;
392                 } else if (source_rates[i] < sink_rates[j]) {
393                         ++i;
394                 } else {
395                         ++j;
396                 }
397         }
398         return k;
399 }
400
401 /* return index of rate in rates array, or -1 if not found */
402 static int intel_dp_rate_index(const int *rates, int len, int rate)
403 {
404         int i;
405
406         for (i = 0; i < len; i++)
407                 if (rate == rates[i])
408                         return i;
409
410         return -1;
411 }
412
413 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
414 {
415         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
416
417         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
418                                                      intel_dp->num_source_rates,
419                                                      intel_dp->sink_rates,
420                                                      intel_dp->num_sink_rates,
421                                                      intel_dp->common_rates);
422
423         /* Paranoia, there should always be something in common. */
424         if (WARN_ON(intel_dp->num_common_rates == 0)) {
425                 intel_dp->common_rates[0] = 162000;
426                 intel_dp->num_common_rates = 1;
427         }
428 }
429
430 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
431                                        uint8_t lane_count)
432 {
433         /*
434          * FIXME: we need to synchronize the current link parameters with
435          * hardware readout. Currently fast link training doesn't work on
436          * boot-up.
437          */
438         if (link_rate == 0 ||
439             link_rate > intel_dp->max_link_rate)
440                 return false;
441
442         if (lane_count == 0 ||
443             lane_count > intel_dp_max_lane_count(intel_dp))
444                 return false;
445
446         return true;
447 }
448
449 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
450                                                      int link_rate,
451                                                      uint8_t lane_count)
452 {
453         const struct drm_display_mode *fixed_mode =
454                 intel_dp->attached_connector->panel.fixed_mode;
455         int mode_rate, max_rate;
456
457         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
458         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
459         if (mode_rate > max_rate)
460                 return false;
461
462         return true;
463 }
464
465 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
466                                             int link_rate, uint8_t lane_count)
467 {
468         int index;
469
470         index = intel_dp_rate_index(intel_dp->common_rates,
471                                     intel_dp->num_common_rates,
472                                     link_rate);
473         if (index > 0) {
474                 if (intel_dp_is_edp(intel_dp) &&
475                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
476                                                               intel_dp->common_rates[index - 1],
477                                                               lane_count)) {
478                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
479                         return 0;
480                 }
481                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
482                 intel_dp->max_link_lane_count = lane_count;
483         } else if (lane_count > 1) {
484                 if (intel_dp_is_edp(intel_dp) &&
485                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
486                                                               intel_dp_max_common_rate(intel_dp),
487                                                               lane_count >> 1)) {
488                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
489                         return 0;
490                 }
491                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
492                 intel_dp->max_link_lane_count = lane_count >> 1;
493         } else {
494                 DRM_ERROR("Link Training Unsuccessful\n");
495                 return -1;
496         }
497
498         return 0;
499 }
500
501 static enum drm_mode_status
502 intel_dp_mode_valid(struct drm_connector *connector,
503                     struct drm_display_mode *mode)
504 {
505         struct intel_dp *intel_dp = intel_attached_dp(connector);
506         struct intel_connector *intel_connector = to_intel_connector(connector);
507         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
508         struct drm_i915_private *dev_priv = to_i915(connector->dev);
509         int target_clock = mode->clock;
510         int max_rate, mode_rate, max_lanes, max_link_clock;
511         int max_dotclk;
512         u16 dsc_max_output_bpp = 0;
513         u8 dsc_slice_count = 0;
514
515         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
516                 return MODE_NO_DBLESCAN;
517
518         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
519
520         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
521                 if (mode->hdisplay > fixed_mode->hdisplay)
522                         return MODE_PANEL;
523
524                 if (mode->vdisplay > fixed_mode->vdisplay)
525                         return MODE_PANEL;
526
527                 target_clock = fixed_mode->clock;
528         }
529
530         max_link_clock = intel_dp_max_link_rate(intel_dp);
531         max_lanes = intel_dp_max_lane_count(intel_dp);
532
533         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
534         mode_rate = intel_dp_link_required(target_clock, 18);
535
536         /*
537          * Output bpp is stored in 6.4 format so right shift by 4 to get the
538          * integer value since we support only integer values of bpp.
539          */
540         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
541             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
542                 if (intel_dp_is_edp(intel_dp)) {
543                         dsc_max_output_bpp =
544                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
545                         dsc_slice_count =
546                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
547                                                                 true);
548                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
549                         dsc_max_output_bpp =
550                                 intel_dp_dsc_get_output_bpp(max_link_clock,
551                                                             max_lanes,
552                                                             target_clock,
553                                                             mode->hdisplay) >> 4;
554                         dsc_slice_count =
555                                 intel_dp_dsc_get_slice_count(intel_dp,
556                                                              target_clock,
557                                                              mode->hdisplay);
558                 }
559         }
560
561         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
562             target_clock > max_dotclk)
563                 return MODE_CLOCK_HIGH;
564
565         if (mode->clock < 10000)
566                 return MODE_CLOCK_LOW;
567
568         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
569                 return MODE_H_ILLEGAL;
570
571         return MODE_OK;
572 }
573
574 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
575 {
576         int     i;
577         uint32_t v = 0;
578
579         if (src_bytes > 4)
580                 src_bytes = 4;
581         for (i = 0; i < src_bytes; i++)
582                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
583         return v;
584 }
585
586 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
587 {
588         int i;
589         if (dst_bytes > 4)
590                 dst_bytes = 4;
591         for (i = 0; i < dst_bytes; i++)
592                 dst[i] = src >> ((3-i) * 8);
593 }
594
595 static void
596 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
597 static void
598 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
599                                               bool force_disable_vdd);
600 static void
601 intel_dp_pps_init(struct intel_dp *intel_dp);
602
603 static void pps_lock(struct intel_dp *intel_dp)
604 {
605         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
606
607         /*
608          * See intel_power_sequencer_reset() why we need
609          * a power domain reference here.
610          */
611         intel_display_power_get(dev_priv,
612                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
613
614         mutex_lock(&dev_priv->pps_mutex);
615 }
616
617 static void pps_unlock(struct intel_dp *intel_dp)
618 {
619         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
620
621         mutex_unlock(&dev_priv->pps_mutex);
622
623         intel_display_power_put(dev_priv,
624                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
625 }
626
627 static void
628 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
629 {
630         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
631         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
632         enum pipe pipe = intel_dp->pps_pipe;
633         bool pll_enabled, release_cl_override = false;
634         enum dpio_phy phy = DPIO_PHY(pipe);
635         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
636         uint32_t DP;
637
638         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
639                  "skipping pipe %c power sequencer kick due to port %c being active\n",
640                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
641                 return;
642
643         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
644                       pipe_name(pipe), port_name(intel_dig_port->base.port));
645
646         /* Preserve the BIOS-computed detected bit. This is
647          * supposed to be read-only.
648          */
649         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
650         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
651         DP |= DP_PORT_WIDTH(1);
652         DP |= DP_LINK_TRAIN_PAT_1;
653
654         if (IS_CHERRYVIEW(dev_priv))
655                 DP |= DP_PIPE_SEL_CHV(pipe);
656         else
657                 DP |= DP_PIPE_SEL(pipe);
658
659         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
660
661         /*
662          * The DPLL for the pipe must be enabled for this to work.
663          * So enable temporarily it if it's not already enabled.
664          */
665         if (!pll_enabled) {
666                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
667                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
668
669                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
670                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
671                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
672                                   pipe_name(pipe));
673                         return;
674                 }
675         }
676
677         /*
678          * Similar magic as in intel_dp_enable_port().
679          * We _must_ do this port enable + disable trick
680          * to make this power sequencer lock onto the port.
681          * Otherwise even VDD force bit won't work.
682          */
683         I915_WRITE(intel_dp->output_reg, DP);
684         POSTING_READ(intel_dp->output_reg);
685
686         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
687         POSTING_READ(intel_dp->output_reg);
688
689         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
690         POSTING_READ(intel_dp->output_reg);
691
692         if (!pll_enabled) {
693                 vlv_force_pll_off(dev_priv, pipe);
694
695                 if (release_cl_override)
696                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
697         }
698 }
699
700 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
701 {
702         struct intel_encoder *encoder;
703         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
704
705         /*
706          * We don't have power sequencer currently.
707          * Pick one that's not used by other ports.
708          */
709         for_each_intel_dp(&dev_priv->drm, encoder) {
710                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
711
712                 if (encoder->type == INTEL_OUTPUT_EDP) {
713                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
714                                 intel_dp->active_pipe != intel_dp->pps_pipe);
715
716                         if (intel_dp->pps_pipe != INVALID_PIPE)
717                                 pipes &= ~(1 << intel_dp->pps_pipe);
718                 } else {
719                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
720
721                         if (intel_dp->active_pipe != INVALID_PIPE)
722                                 pipes &= ~(1 << intel_dp->active_pipe);
723                 }
724         }
725
726         if (pipes == 0)
727                 return INVALID_PIPE;
728
729         return ffs(pipes) - 1;
730 }
731
732 static enum pipe
733 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
734 {
735         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
736         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
737         enum pipe pipe;
738
739         lockdep_assert_held(&dev_priv->pps_mutex);
740
741         /* We should never land here with regular DP ports */
742         WARN_ON(!intel_dp_is_edp(intel_dp));
743
744         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
745                 intel_dp->active_pipe != intel_dp->pps_pipe);
746
747         if (intel_dp->pps_pipe != INVALID_PIPE)
748                 return intel_dp->pps_pipe;
749
750         pipe = vlv_find_free_pps(dev_priv);
751
752         /*
753          * Didn't find one. This should not happen since there
754          * are two power sequencers and up to two eDP ports.
755          */
756         if (WARN_ON(pipe == INVALID_PIPE))
757                 pipe = PIPE_A;
758
759         vlv_steal_power_sequencer(dev_priv, pipe);
760         intel_dp->pps_pipe = pipe;
761
762         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
763                       pipe_name(intel_dp->pps_pipe),
764                       port_name(intel_dig_port->base.port));
765
766         /* init power sequencer on this pipe and port */
767         intel_dp_init_panel_power_sequencer(intel_dp);
768         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
769
770         /*
771          * Even vdd force doesn't work until we've made
772          * the power sequencer lock in on the port.
773          */
774         vlv_power_sequencer_kick(intel_dp);
775
776         return intel_dp->pps_pipe;
777 }
778
779 static int
780 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
781 {
782         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
783         int backlight_controller = dev_priv->vbt.backlight.controller;
784
785         lockdep_assert_held(&dev_priv->pps_mutex);
786
787         /* We should never land here with regular DP ports */
788         WARN_ON(!intel_dp_is_edp(intel_dp));
789
790         if (!intel_dp->pps_reset)
791                 return backlight_controller;
792
793         intel_dp->pps_reset = false;
794
795         /*
796          * Only the HW needs to be reprogrammed, the SW state is fixed and
797          * has been setup during connector init.
798          */
799         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
800
801         return backlight_controller;
802 }
803
804 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
805                                enum pipe pipe);
806
807 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
808                                enum pipe pipe)
809 {
810         return I915_READ(PP_STATUS(pipe)) & PP_ON;
811 }
812
813 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
814                                 enum pipe pipe)
815 {
816         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
817 }
818
819 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
820                          enum pipe pipe)
821 {
822         return true;
823 }
824
825 static enum pipe
826 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
827                      enum port port,
828                      vlv_pipe_check pipe_check)
829 {
830         enum pipe pipe;
831
832         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
833                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
834                         PANEL_PORT_SELECT_MASK;
835
836                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
837                         continue;
838
839                 if (!pipe_check(dev_priv, pipe))
840                         continue;
841
842                 return pipe;
843         }
844
845         return INVALID_PIPE;
846 }
847
848 static void
849 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
850 {
851         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
852         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
853         enum port port = intel_dig_port->base.port;
854
855         lockdep_assert_held(&dev_priv->pps_mutex);
856
857         /* try to find a pipe with this port selected */
858         /* first pick one where the panel is on */
859         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
860                                                   vlv_pipe_has_pp_on);
861         /* didn't find one? pick one where vdd is on */
862         if (intel_dp->pps_pipe == INVALID_PIPE)
863                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
864                                                           vlv_pipe_has_vdd_on);
865         /* didn't find one? pick one with just the correct port */
866         if (intel_dp->pps_pipe == INVALID_PIPE)
867                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
868                                                           vlv_pipe_any);
869
870         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
871         if (intel_dp->pps_pipe == INVALID_PIPE) {
872                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
873                               port_name(port));
874                 return;
875         }
876
877         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
878                       port_name(port), pipe_name(intel_dp->pps_pipe));
879
880         intel_dp_init_panel_power_sequencer(intel_dp);
881         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
882 }
883
884 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
885 {
886         struct intel_encoder *encoder;
887
888         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
889                     !IS_GEN9_LP(dev_priv)))
890                 return;
891
892         /*
893          * We can't grab pps_mutex here due to deadlock with power_domain
894          * mutex when power_domain functions are called while holding pps_mutex.
895          * That also means that in order to use pps_pipe the code needs to
896          * hold both a power domain reference and pps_mutex, and the power domain
897          * reference get/put must be done while _not_ holding pps_mutex.
898          * pps_{lock,unlock}() do these steps in the correct order, so one
899          * should use them always.
900          */
901
902         for_each_intel_dp(&dev_priv->drm, encoder) {
903                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
904
905                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
906
907                 if (encoder->type != INTEL_OUTPUT_EDP)
908                         continue;
909
910                 if (IS_GEN9_LP(dev_priv))
911                         intel_dp->pps_reset = true;
912                 else
913                         intel_dp->pps_pipe = INVALID_PIPE;
914         }
915 }
916
917 struct pps_registers {
918         i915_reg_t pp_ctrl;
919         i915_reg_t pp_stat;
920         i915_reg_t pp_on;
921         i915_reg_t pp_off;
922         i915_reg_t pp_div;
923 };
924
925 static void intel_pps_get_registers(struct intel_dp *intel_dp,
926                                     struct pps_registers *regs)
927 {
928         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
929         int pps_idx = 0;
930
931         memset(regs, 0, sizeof(*regs));
932
933         if (IS_GEN9_LP(dev_priv))
934                 pps_idx = bxt_power_sequencer_idx(intel_dp);
935         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
936                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
937
938         regs->pp_ctrl = PP_CONTROL(pps_idx);
939         regs->pp_stat = PP_STATUS(pps_idx);
940         regs->pp_on = PP_ON_DELAYS(pps_idx);
941         regs->pp_off = PP_OFF_DELAYS(pps_idx);
942         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
943             !HAS_PCH_ICP(dev_priv))
944                 regs->pp_div = PP_DIVISOR(pps_idx);
945 }
946
947 static i915_reg_t
948 _pp_ctrl_reg(struct intel_dp *intel_dp)
949 {
950         struct pps_registers regs;
951
952         intel_pps_get_registers(intel_dp, &regs);
953
954         return regs.pp_ctrl;
955 }
956
957 static i915_reg_t
958 _pp_stat_reg(struct intel_dp *intel_dp)
959 {
960         struct pps_registers regs;
961
962         intel_pps_get_registers(intel_dp, &regs);
963
964         return regs.pp_stat;
965 }
966
967 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
968    This function only applicable when panel PM state is not to be tracked */
969 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
970                               void *unused)
971 {
972         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
973                                                  edp_notifier);
974         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
975
976         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
977                 return 0;
978
979         pps_lock(intel_dp);
980
981         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
982                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
983                 i915_reg_t pp_ctrl_reg, pp_div_reg;
984                 u32 pp_div;
985
986                 pp_ctrl_reg = PP_CONTROL(pipe);
987                 pp_div_reg  = PP_DIVISOR(pipe);
988                 pp_div = I915_READ(pp_div_reg);
989                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
990
991                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
992                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
993                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
994                 msleep(intel_dp->panel_power_cycle_delay);
995         }
996
997         pps_unlock(intel_dp);
998
999         return 0;
1000 }
1001
1002 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1003 {
1004         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1005
1006         lockdep_assert_held(&dev_priv->pps_mutex);
1007
1008         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1009             intel_dp->pps_pipe == INVALID_PIPE)
1010                 return false;
1011
1012         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1013 }
1014
1015 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1016 {
1017         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1018
1019         lockdep_assert_held(&dev_priv->pps_mutex);
1020
1021         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1022             intel_dp->pps_pipe == INVALID_PIPE)
1023                 return false;
1024
1025         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1026 }
1027
1028 static void
1029 intel_dp_check_edp(struct intel_dp *intel_dp)
1030 {
1031         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1032
1033         if (!intel_dp_is_edp(intel_dp))
1034                 return;
1035
1036         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1037                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1038                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1039                               I915_READ(_pp_stat_reg(intel_dp)),
1040                               I915_READ(_pp_ctrl_reg(intel_dp)));
1041         }
1042 }
1043
1044 static uint32_t
1045 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1046 {
1047         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1048         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1049         uint32_t status;
1050         bool done;
1051
1052 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1053         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1054                                   msecs_to_jiffies_timeout(10));
1055         if (!done)
1056                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1057 #undef C
1058
1059         return status;
1060 }
1061
1062 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1063 {
1064         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1065
1066         if (index)
1067                 return 0;
1068
1069         /*
1070          * The clock divider is based off the hrawclk, and would like to run at
1071          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1072          */
1073         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1074 }
1075
1076 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1077 {
1078         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1079         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1080
1081         if (index)
1082                 return 0;
1083
1084         /*
1085          * The clock divider is based off the cdclk or PCH rawclk, and would
1086          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1087          * divide by 2000 and use that
1088          */
1089         if (dig_port->aux_ch == AUX_CH_A)
1090                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1091         else
1092                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1093 }
1094
1095 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1096 {
1097         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1098         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1099
1100         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1101                 /* Workaround for non-ULT HSW */
1102                 switch (index) {
1103                 case 0: return 63;
1104                 case 1: return 72;
1105                 default: return 0;
1106                 }
1107         }
1108
1109         return ilk_get_aux_clock_divider(intel_dp, index);
1110 }
1111
1112 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1113 {
1114         /*
1115          * SKL doesn't need us to program the AUX clock divider (Hardware will
1116          * derive the clock from CDCLK automatically). We still implement the
1117          * get_aux_clock_divider vfunc to plug-in into the existing code.
1118          */
1119         return index ? 0 : 1;
1120 }
1121
1122 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1123                                      int send_bytes,
1124                                      uint32_t aux_clock_divider)
1125 {
1126         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1127         struct drm_i915_private *dev_priv =
1128                         to_i915(intel_dig_port->base.base.dev);
1129         uint32_t precharge, timeout;
1130
1131         if (IS_GEN6(dev_priv))
1132                 precharge = 3;
1133         else
1134                 precharge = 5;
1135
1136         if (IS_BROADWELL(dev_priv))
1137                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1138         else
1139                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1140
1141         return DP_AUX_CH_CTL_SEND_BUSY |
1142                DP_AUX_CH_CTL_DONE |
1143                DP_AUX_CH_CTL_INTERRUPT |
1144                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1145                timeout |
1146                DP_AUX_CH_CTL_RECEIVE_ERROR |
1147                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1148                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1149                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1150 }
1151
1152 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1153                                       int send_bytes,
1154                                       uint32_t unused)
1155 {
1156         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1157         uint32_t ret;
1158
1159         ret = DP_AUX_CH_CTL_SEND_BUSY |
1160               DP_AUX_CH_CTL_DONE |
1161               DP_AUX_CH_CTL_INTERRUPT |
1162               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1163               DP_AUX_CH_CTL_TIME_OUT_MAX |
1164               DP_AUX_CH_CTL_RECEIVE_ERROR |
1165               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1166               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1167               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1168
1169         if (intel_dig_port->tc_type == TC_PORT_TBT)
1170                 ret |= DP_AUX_CH_CTL_TBT_IO;
1171
1172         return ret;
1173 }
1174
1175 static int
1176 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1177                   const uint8_t *send, int send_bytes,
1178                   uint8_t *recv, int recv_size,
1179                   u32 aux_send_ctl_flags)
1180 {
1181         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1182         struct drm_i915_private *dev_priv =
1183                         to_i915(intel_dig_port->base.base.dev);
1184         i915_reg_t ch_ctl, ch_data[5];
1185         uint32_t aux_clock_divider;
1186         int i, ret, recv_bytes;
1187         uint32_t status;
1188         int try, clock = 0;
1189         bool vdd;
1190
1191         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1192         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1193                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1194
1195         pps_lock(intel_dp);
1196
1197         /*
1198          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1199          * In such cases we want to leave VDD enabled and it's up to upper layers
1200          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1201          * ourselves.
1202          */
1203         vdd = edp_panel_vdd_on(intel_dp);
1204
1205         /* dp aux is extremely sensitive to irq latency, hence request the
1206          * lowest possible wakeup latency and so prevent the cpu from going into
1207          * deep sleep states.
1208          */
1209         pm_qos_update_request(&dev_priv->pm_qos, 0);
1210
1211         intel_dp_check_edp(intel_dp);
1212
1213         /* Try to wait for any previous AUX channel activity */
1214         for (try = 0; try < 3; try++) {
1215                 status = I915_READ_NOTRACE(ch_ctl);
1216                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1217                         break;
1218                 msleep(1);
1219         }
1220
1221         if (try == 3) {
1222                 static u32 last_status = -1;
1223                 const u32 status = I915_READ(ch_ctl);
1224
1225                 if (status != last_status) {
1226                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1227                              status);
1228                         last_status = status;
1229                 }
1230
1231                 ret = -EBUSY;
1232                 goto out;
1233         }
1234
1235         /* Only 5 data registers! */
1236         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1237                 ret = -E2BIG;
1238                 goto out;
1239         }
1240
1241         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1242                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1243                                                           send_bytes,
1244                                                           aux_clock_divider);
1245
1246                 send_ctl |= aux_send_ctl_flags;
1247
1248                 /* Must try at least 3 times according to DP spec */
1249                 for (try = 0; try < 5; try++) {
1250                         /* Load the send data into the aux channel data registers */
1251                         for (i = 0; i < send_bytes; i += 4)
1252                                 I915_WRITE(ch_data[i >> 2],
1253                                            intel_dp_pack_aux(send + i,
1254                                                              send_bytes - i));
1255
1256                         /* Send the command and wait for it to complete */
1257                         I915_WRITE(ch_ctl, send_ctl);
1258
1259                         status = intel_dp_aux_wait_done(intel_dp);
1260
1261                         /* Clear done status and any errors */
1262                         I915_WRITE(ch_ctl,
1263                                    status |
1264                                    DP_AUX_CH_CTL_DONE |
1265                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1266                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1267
1268                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1269                          *   400us delay required for errors and timeouts
1270                          *   Timeout errors from the HW already meet this
1271                          *   requirement so skip to next iteration
1272                          */
1273                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1274                                 continue;
1275
1276                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1277                                 usleep_range(400, 500);
1278                                 continue;
1279                         }
1280                         if (status & DP_AUX_CH_CTL_DONE)
1281                                 goto done;
1282                 }
1283         }
1284
1285         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1286                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1287                 ret = -EBUSY;
1288                 goto out;
1289         }
1290
1291 done:
1292         /* Check for timeout or receive error.
1293          * Timeouts occur when the sink is not connected
1294          */
1295         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1296                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1297                 ret = -EIO;
1298                 goto out;
1299         }
1300
1301         /* Timeouts occur when the device isn't connected, so they're
1302          * "normal" -- don't fill the kernel log with these */
1303         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1304                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1305                 ret = -ETIMEDOUT;
1306                 goto out;
1307         }
1308
1309         /* Unload any bytes sent back from the other side */
1310         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1311                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1312
1313         /*
1314          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1315          * We have no idea of what happened so we return -EBUSY so
1316          * drm layer takes care for the necessary retries.
1317          */
1318         if (recv_bytes == 0 || recv_bytes > 20) {
1319                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1320                               recv_bytes);
1321                 ret = -EBUSY;
1322                 goto out;
1323         }
1324
1325         if (recv_bytes > recv_size)
1326                 recv_bytes = recv_size;
1327
1328         for (i = 0; i < recv_bytes; i += 4)
1329                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1330                                     recv + i, recv_bytes - i);
1331
1332         ret = recv_bytes;
1333 out:
1334         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1335
1336         if (vdd)
1337                 edp_panel_vdd_off(intel_dp, false);
1338
1339         pps_unlock(intel_dp);
1340
1341         return ret;
1342 }
1343
1344 #define BARE_ADDRESS_SIZE       3
1345 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1346
1347 static void
1348 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1349                     const struct drm_dp_aux_msg *msg)
1350 {
1351         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1352         txbuf[1] = (msg->address >> 8) & 0xff;
1353         txbuf[2] = msg->address & 0xff;
1354         txbuf[3] = msg->size - 1;
1355 }
1356
1357 static ssize_t
1358 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1359 {
1360         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1361         uint8_t txbuf[20], rxbuf[20];
1362         size_t txsize, rxsize;
1363         int ret;
1364
1365         intel_dp_aux_header(txbuf, msg);
1366
1367         switch (msg->request & ~DP_AUX_I2C_MOT) {
1368         case DP_AUX_NATIVE_WRITE:
1369         case DP_AUX_I2C_WRITE:
1370         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1371                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1372                 rxsize = 2; /* 0 or 1 data bytes */
1373
1374                 if (WARN_ON(txsize > 20))
1375                         return -E2BIG;
1376
1377                 WARN_ON(!msg->buffer != !msg->size);
1378
1379                 if (msg->buffer)
1380                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1381
1382                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1383                                         rxbuf, rxsize, 0);
1384                 if (ret > 0) {
1385                         msg->reply = rxbuf[0] >> 4;
1386
1387                         if (ret > 1) {
1388                                 /* Number of bytes written in a short write. */
1389                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1390                         } else {
1391                                 /* Return payload size. */
1392                                 ret = msg->size;
1393                         }
1394                 }
1395                 break;
1396
1397         case DP_AUX_NATIVE_READ:
1398         case DP_AUX_I2C_READ:
1399                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1400                 rxsize = msg->size + 1;
1401
1402                 if (WARN_ON(rxsize > 20))
1403                         return -E2BIG;
1404
1405                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1406                                         rxbuf, rxsize, 0);
1407                 if (ret > 0) {
1408                         msg->reply = rxbuf[0] >> 4;
1409                         /*
1410                          * Assume happy day, and copy the data. The caller is
1411                          * expected to check msg->reply before touching it.
1412                          *
1413                          * Return payload size.
1414                          */
1415                         ret--;
1416                         memcpy(msg->buffer, rxbuf + 1, ret);
1417                 }
1418                 break;
1419
1420         default:
1421                 ret = -EINVAL;
1422                 break;
1423         }
1424
1425         return ret;
1426 }
1427
1428
1429 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1430 {
1431         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1432         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1433         enum aux_ch aux_ch = dig_port->aux_ch;
1434
1435         switch (aux_ch) {
1436         case AUX_CH_B:
1437         case AUX_CH_C:
1438         case AUX_CH_D:
1439                 return DP_AUX_CH_CTL(aux_ch);
1440         default:
1441                 MISSING_CASE(aux_ch);
1442                 return DP_AUX_CH_CTL(AUX_CH_B);
1443         }
1444 }
1445
1446 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1447 {
1448         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1449         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1450         enum aux_ch aux_ch = dig_port->aux_ch;
1451
1452         switch (aux_ch) {
1453         case AUX_CH_B:
1454         case AUX_CH_C:
1455         case AUX_CH_D:
1456                 return DP_AUX_CH_DATA(aux_ch, index);
1457         default:
1458                 MISSING_CASE(aux_ch);
1459                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1460         }
1461 }
1462
1463 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1464 {
1465         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1466         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1467         enum aux_ch aux_ch = dig_port->aux_ch;
1468
1469         switch (aux_ch) {
1470         case AUX_CH_A:
1471                 return DP_AUX_CH_CTL(aux_ch);
1472         case AUX_CH_B:
1473         case AUX_CH_C:
1474         case AUX_CH_D:
1475                 return PCH_DP_AUX_CH_CTL(aux_ch);
1476         default:
1477                 MISSING_CASE(aux_ch);
1478                 return DP_AUX_CH_CTL(AUX_CH_A);
1479         }
1480 }
1481
1482 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1483 {
1484         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1485         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1486         enum aux_ch aux_ch = dig_port->aux_ch;
1487
1488         switch (aux_ch) {
1489         case AUX_CH_A:
1490                 return DP_AUX_CH_DATA(aux_ch, index);
1491         case AUX_CH_B:
1492         case AUX_CH_C:
1493         case AUX_CH_D:
1494                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1495         default:
1496                 MISSING_CASE(aux_ch);
1497                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1498         }
1499 }
1500
1501 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1502 {
1503         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1504         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1505         enum aux_ch aux_ch = dig_port->aux_ch;
1506
1507         switch (aux_ch) {
1508         case AUX_CH_A:
1509         case AUX_CH_B:
1510         case AUX_CH_C:
1511         case AUX_CH_D:
1512         case AUX_CH_E:
1513         case AUX_CH_F:
1514                 return DP_AUX_CH_CTL(aux_ch);
1515         default:
1516                 MISSING_CASE(aux_ch);
1517                 return DP_AUX_CH_CTL(AUX_CH_A);
1518         }
1519 }
1520
1521 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1522 {
1523         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1524         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1525         enum aux_ch aux_ch = dig_port->aux_ch;
1526
1527         switch (aux_ch) {
1528         case AUX_CH_A:
1529         case AUX_CH_B:
1530         case AUX_CH_C:
1531         case AUX_CH_D:
1532         case AUX_CH_E:
1533         case AUX_CH_F:
1534                 return DP_AUX_CH_DATA(aux_ch, index);
1535         default:
1536                 MISSING_CASE(aux_ch);
1537                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1538         }
1539 }
1540
1541 static void
1542 intel_dp_aux_fini(struct intel_dp *intel_dp)
1543 {
1544         kfree(intel_dp->aux.name);
1545 }
1546
1547 static void
1548 intel_dp_aux_init(struct intel_dp *intel_dp)
1549 {
1550         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1551         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1552         struct intel_encoder *encoder = &dig_port->base;
1553
1554         if (INTEL_GEN(dev_priv) >= 9) {
1555                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1556                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1557         } else if (HAS_PCH_SPLIT(dev_priv)) {
1558                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1559                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1560         } else {
1561                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1562                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1563         }
1564
1565         if (INTEL_GEN(dev_priv) >= 9)
1566                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1567         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1568                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1569         else if (HAS_PCH_SPLIT(dev_priv))
1570                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1571         else
1572                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1573
1574         if (INTEL_GEN(dev_priv) >= 9)
1575                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1576         else
1577                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1578
1579         drm_dp_aux_init(&intel_dp->aux);
1580
1581         /* Failure to allocate our preferred name is not critical */
1582         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1583                                        port_name(encoder->port));
1584         intel_dp->aux.transfer = intel_dp_aux_transfer;
1585 }
1586
1587 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1588 {
1589         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1590
1591         return max_rate >= 540000;
1592 }
1593
1594 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1595 {
1596         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1597
1598         return max_rate >= 810000;
1599 }
1600
1601 static void
1602 intel_dp_set_clock(struct intel_encoder *encoder,
1603                    struct intel_crtc_state *pipe_config)
1604 {
1605         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1606         const struct dp_link_dpll *divisor = NULL;
1607         int i, count = 0;
1608
1609         if (IS_G4X(dev_priv)) {
1610                 divisor = g4x_dpll;
1611                 count = ARRAY_SIZE(g4x_dpll);
1612         } else if (HAS_PCH_SPLIT(dev_priv)) {
1613                 divisor = pch_dpll;
1614                 count = ARRAY_SIZE(pch_dpll);
1615         } else if (IS_CHERRYVIEW(dev_priv)) {
1616                 divisor = chv_dpll;
1617                 count = ARRAY_SIZE(chv_dpll);
1618         } else if (IS_VALLEYVIEW(dev_priv)) {
1619                 divisor = vlv_dpll;
1620                 count = ARRAY_SIZE(vlv_dpll);
1621         }
1622
1623         if (divisor && count) {
1624                 for (i = 0; i < count; i++) {
1625                         if (pipe_config->port_clock == divisor[i].clock) {
1626                                 pipe_config->dpll = divisor[i].dpll;
1627                                 pipe_config->clock_set = true;
1628                                 break;
1629                         }
1630                 }
1631         }
1632 }
1633
1634 static void snprintf_int_array(char *str, size_t len,
1635                                const int *array, int nelem)
1636 {
1637         int i;
1638
1639         str[0] = '\0';
1640
1641         for (i = 0; i < nelem; i++) {
1642                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1643                 if (r >= len)
1644                         return;
1645                 str += r;
1646                 len -= r;
1647         }
1648 }
1649
1650 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1651 {
1652         char str[128]; /* FIXME: too big for stack? */
1653
1654         if ((drm_debug & DRM_UT_KMS) == 0)
1655                 return;
1656
1657         snprintf_int_array(str, sizeof(str),
1658                            intel_dp->source_rates, intel_dp->num_source_rates);
1659         DRM_DEBUG_KMS("source rates: %s\n", str);
1660
1661         snprintf_int_array(str, sizeof(str),
1662                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1663         DRM_DEBUG_KMS("sink rates: %s\n", str);
1664
1665         snprintf_int_array(str, sizeof(str),
1666                            intel_dp->common_rates, intel_dp->num_common_rates);
1667         DRM_DEBUG_KMS("common rates: %s\n", str);
1668 }
1669
1670 int
1671 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1672 {
1673         int len;
1674
1675         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1676         if (WARN_ON(len <= 0))
1677                 return 162000;
1678
1679         return intel_dp->common_rates[len - 1];
1680 }
1681
1682 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1683 {
1684         int i = intel_dp_rate_index(intel_dp->sink_rates,
1685                                     intel_dp->num_sink_rates, rate);
1686
1687         if (WARN_ON(i < 0))
1688                 i = 0;
1689
1690         return i;
1691 }
1692
1693 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1694                            uint8_t *link_bw, uint8_t *rate_select)
1695 {
1696         /* eDP 1.4 rate select method. */
1697         if (intel_dp->use_rate_select) {
1698                 *link_bw = 0;
1699                 *rate_select =
1700                         intel_dp_rate_select(intel_dp, port_clock);
1701         } else {
1702                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1703                 *rate_select = 0;
1704         }
1705 }
1706
1707 struct link_config_limits {
1708         int min_clock, max_clock;
1709         int min_lane_count, max_lane_count;
1710         int min_bpp, max_bpp;
1711 };
1712
1713 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1714                                          const struct intel_crtc_state *pipe_config)
1715 {
1716         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1717
1718         return INTEL_GEN(dev_priv) >= 11 &&
1719                 pipe_config->cpu_transcoder != TRANSCODER_A;
1720 }
1721
1722 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1723                                   const struct intel_crtc_state *pipe_config)
1724 {
1725         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1726                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1727 }
1728
1729 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1730                                          const struct intel_crtc_state *pipe_config)
1731 {
1732         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1733
1734         return INTEL_GEN(dev_priv) >= 10 &&
1735                 pipe_config->cpu_transcoder != TRANSCODER_A;
1736 }
1737
1738 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1739                                   const struct intel_crtc_state *pipe_config)
1740 {
1741         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1742                 return false;
1743
1744         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1745                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1746 }
1747
1748 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1749                                 struct intel_crtc_state *pipe_config)
1750 {
1751         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1752         struct intel_connector *intel_connector = intel_dp->attached_connector;
1753         int bpp, bpc;
1754
1755         bpp = pipe_config->pipe_bpp;
1756         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1757
1758         if (bpc > 0)
1759                 bpp = min(bpp, 3*bpc);
1760
1761         if (intel_dp_is_edp(intel_dp)) {
1762                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1763                 if (intel_connector->base.display_info.bpc == 0 &&
1764                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1765                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1766                                       dev_priv->vbt.edp.bpp);
1767                         bpp = dev_priv->vbt.edp.bpp;
1768                 }
1769         }
1770
1771         return bpp;
1772 }
1773
1774 /* Adjust link config limits based on compliance test requests. */
1775 static void
1776 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1777                                   struct intel_crtc_state *pipe_config,
1778                                   struct link_config_limits *limits)
1779 {
1780         /* For DP Compliance we override the computed bpp for the pipe */
1781         if (intel_dp->compliance.test_data.bpc != 0) {
1782                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1783
1784                 limits->min_bpp = limits->max_bpp = bpp;
1785                 pipe_config->dither_force_disable = bpp == 6 * 3;
1786
1787                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1788         }
1789
1790         /* Use values requested by Compliance Test Request */
1791         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1792                 int index;
1793
1794                 /* Validate the compliance test data since max values
1795                  * might have changed due to link train fallback.
1796                  */
1797                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1798                                                intel_dp->compliance.test_lane_count)) {
1799                         index = intel_dp_rate_index(intel_dp->common_rates,
1800                                                     intel_dp->num_common_rates,
1801                                                     intel_dp->compliance.test_link_rate);
1802                         if (index >= 0)
1803                                 limits->min_clock = limits->max_clock = index;
1804                         limits->min_lane_count = limits->max_lane_count =
1805                                 intel_dp->compliance.test_lane_count;
1806                 }
1807         }
1808 }
1809
1810 /* Optimize link config in order: max bpp, min clock, min lanes */
1811 static int
1812 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1813                                   struct intel_crtc_state *pipe_config,
1814                                   const struct link_config_limits *limits)
1815 {
1816         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1817         int bpp, clock, lane_count;
1818         int mode_rate, link_clock, link_avail;
1819
1820         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1821                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1822                                                    bpp);
1823
1824                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1825                         for (lane_count = limits->min_lane_count;
1826                              lane_count <= limits->max_lane_count;
1827                              lane_count <<= 1) {
1828                                 link_clock = intel_dp->common_rates[clock];
1829                                 link_avail = intel_dp_max_data_rate(link_clock,
1830                                                                     lane_count);
1831
1832                                 if (mode_rate <= link_avail) {
1833                                         pipe_config->lane_count = lane_count;
1834                                         pipe_config->pipe_bpp = bpp;
1835                                         pipe_config->port_clock = link_clock;
1836
1837                                         return 0;
1838                                 }
1839                         }
1840                 }
1841         }
1842
1843         return -EINVAL;
1844 }
1845
1846 /* Optimize link config in order: max bpp, min lanes, min clock */
1847 static int
1848 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1849                                   struct intel_crtc_state *pipe_config,
1850                                   const struct link_config_limits *limits)
1851 {
1852         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1853         int bpp, clock, lane_count;
1854         int mode_rate, link_clock, link_avail;
1855
1856         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1857                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1858                                                    bpp);
1859
1860                 for (lane_count = limits->min_lane_count;
1861                      lane_count <= limits->max_lane_count;
1862                      lane_count <<= 1) {
1863                         for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1864                                 link_clock = intel_dp->common_rates[clock];
1865                                 link_avail = intel_dp_max_data_rate(link_clock,
1866                                                                     lane_count);
1867
1868                                 if (mode_rate <= link_avail) {
1869                                         pipe_config->lane_count = lane_count;
1870                                         pipe_config->pipe_bpp = bpp;
1871                                         pipe_config->port_clock = link_clock;
1872
1873                                         return 0;
1874                                 }
1875                         }
1876                 }
1877         }
1878
1879         return -EINVAL;
1880 }
1881
1882 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1883 {
1884         int i, num_bpc;
1885         u8 dsc_bpc[3] = {0};
1886
1887         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1888                                                        dsc_bpc);
1889         for (i = 0; i < num_bpc; i++) {
1890                 if (dsc_max_bpc >= dsc_bpc[i])
1891                         return dsc_bpc[i] * 3;
1892         }
1893
1894         return 0;
1895 }
1896
1897 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1898                                        struct intel_crtc_state *pipe_config,
1899                                        struct drm_connector_state *conn_state,
1900                                        struct link_config_limits *limits)
1901 {
1902         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1903         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1904         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1905         u8 dsc_max_bpc;
1906         int pipe_bpp;
1907         int ret;
1908
1909         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1910                 return -EINVAL;
1911
1912         dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
1913                             conn_state->max_requested_bpc);
1914
1915         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1916         if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
1917                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1918                 return -EINVAL;
1919         }
1920
1921         /*
1922          * For now enable DSC for max bpp, max link rate, max lane count.
1923          * Optimize this later for the minimum possible link rate/lane count
1924          * with DSC enabled for the requested mode.
1925          */
1926         pipe_config->pipe_bpp = pipe_bpp;
1927         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1928         pipe_config->lane_count = limits->max_lane_count;
1929
1930         if (intel_dp_is_edp(intel_dp)) {
1931                 pipe_config->dsc_params.compressed_bpp =
1932                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1933                               pipe_config->pipe_bpp);
1934                 pipe_config->dsc_params.slice_count =
1935                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1936                                                         true);
1937         } else {
1938                 u16 dsc_max_output_bpp;
1939                 u8 dsc_dp_slice_count;
1940
1941                 dsc_max_output_bpp =
1942                         intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
1943                                                     pipe_config->lane_count,
1944                                                     adjusted_mode->crtc_clock,
1945                                                     adjusted_mode->crtc_hdisplay);
1946                 dsc_dp_slice_count =
1947                         intel_dp_dsc_get_slice_count(intel_dp,
1948                                                      adjusted_mode->crtc_clock,
1949                                                      adjusted_mode->crtc_hdisplay);
1950                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1951                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1952                         return -EINVAL;
1953                 }
1954                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
1955                                                                dsc_max_output_bpp >> 4,
1956                                                                pipe_config->pipe_bpp);
1957                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
1958         }
1959         /*
1960          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1961          * is greater than the maximum Cdclock and if slice count is even
1962          * then we need to use 2 VDSC instances.
1963          */
1964         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
1965                 if (pipe_config->dsc_params.slice_count > 1) {
1966                         pipe_config->dsc_params.dsc_split = true;
1967                 } else {
1968                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1969                         return -EINVAL;
1970                 }
1971         }
1972
1973         ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
1974         if (ret < 0) {
1975                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1976                               "Compressed BPP = %d\n",
1977                               pipe_config->pipe_bpp,
1978                               pipe_config->dsc_params.compressed_bpp);
1979                 return ret;
1980         }
1981
1982         pipe_config->dsc_params.compression_enable = true;
1983         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
1984                       "Compressed Bpp = %d Slice Count = %d\n",
1985                       pipe_config->pipe_bpp,
1986                       pipe_config->dsc_params.compressed_bpp,
1987                       pipe_config->dsc_params.slice_count);
1988
1989         return 0;
1990 }
1991
1992 static int
1993 intel_dp_compute_link_config(struct intel_encoder *encoder,
1994                              struct intel_crtc_state *pipe_config,
1995                              struct drm_connector_state *conn_state)
1996 {
1997         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1998         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1999         struct link_config_limits limits;
2000         int common_len;
2001         int ret;
2002
2003         common_len = intel_dp_common_len_rate_limit(intel_dp,
2004                                                     intel_dp->max_link_rate);
2005
2006         /* No common link rates between source and sink */
2007         WARN_ON(common_len <= 0);
2008
2009         limits.min_clock = 0;
2010         limits.max_clock = common_len - 1;
2011
2012         limits.min_lane_count = 1;
2013         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2014
2015         limits.min_bpp = 6 * 3;
2016         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2017
2018         if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
2019                 /*
2020                  * Use the maximum clock and number of lanes the eDP panel
2021                  * advertizes being capable of. The eDP 1.3 and earlier panels
2022                  * are generally designed to support only a single clock and
2023                  * lane configuration, and typically these values correspond to
2024                  * the native resolution of the panel. With eDP 1.4 rate select
2025                  * and DSC, this is decreasingly the case, and we need to be
2026                  * able to select less than maximum link config.
2027                  */
2028                 limits.min_lane_count = limits.max_lane_count;
2029                 limits.min_clock = limits.max_clock;
2030         }
2031
2032         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2033
2034         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2035                       "max rate %d max bpp %d pixel clock %iKHz\n",
2036                       limits.max_lane_count,
2037                       intel_dp->common_rates[limits.max_clock],
2038                       limits.max_bpp, adjusted_mode->crtc_clock);
2039
2040         if (intel_dp_is_edp(intel_dp))
2041                 /*
2042                  * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
2043                  * section A.1: "It is recommended that the minimum number of
2044                  * lanes be used, using the minimum link rate allowed for that
2045                  * lane configuration."
2046                  *
2047                  * Note that we use the max clock and lane count for eDP 1.3 and
2048                  * earlier, and fast vs. wide is irrelevant.
2049                  */
2050                 ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
2051                                                         &limits);
2052         else
2053                 /* Optimize for slow and wide. */
2054                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2055                                                         &limits);
2056
2057         /* enable compression if the mode doesn't fit available BW */
2058         if (ret) {
2059                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2060                                                   conn_state, &limits);
2061                 if (ret < 0)
2062                         return ret;
2063         }
2064
2065         if (pipe_config->dsc_params.compression_enable) {
2066                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2067                               pipe_config->lane_count, pipe_config->port_clock,
2068                               pipe_config->pipe_bpp,
2069                               pipe_config->dsc_params.compressed_bpp);
2070
2071                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2072                               intel_dp_link_required(adjusted_mode->crtc_clock,
2073                                                      pipe_config->dsc_params.compressed_bpp),
2074                               intel_dp_max_data_rate(pipe_config->port_clock,
2075                                                      pipe_config->lane_count));
2076         } else {
2077                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2078                               pipe_config->lane_count, pipe_config->port_clock,
2079                               pipe_config->pipe_bpp);
2080
2081                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2082                               intel_dp_link_required(adjusted_mode->crtc_clock,
2083                                                      pipe_config->pipe_bpp),
2084                               intel_dp_max_data_rate(pipe_config->port_clock,
2085                                                      pipe_config->lane_count));
2086         }
2087         return 0;
2088 }
2089
2090 int
2091 intel_dp_compute_config(struct intel_encoder *encoder,
2092                         struct intel_crtc_state *pipe_config,
2093                         struct drm_connector_state *conn_state)
2094 {
2095         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2096         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2097         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2098         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2099         enum port port = encoder->port;
2100         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2101         struct intel_connector *intel_connector = intel_dp->attached_connector;
2102         struct intel_digital_connector_state *intel_conn_state =
2103                 to_intel_digital_connector_state(conn_state);
2104         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2105                                            DP_DPCD_QUIRK_CONSTANT_N);
2106         int ret;
2107
2108         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2109                 pipe_config->has_pch_encoder = true;
2110
2111         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2112         if (lspcon->active)
2113                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2114
2115         pipe_config->has_drrs = false;
2116         if (IS_G4X(dev_priv) || port == PORT_A)
2117                 pipe_config->has_audio = false;
2118         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2119                 pipe_config->has_audio = intel_dp->has_audio;
2120         else
2121                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2122
2123         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2124                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2125                                        adjusted_mode);
2126
2127                 if (INTEL_GEN(dev_priv) >= 9) {
2128                         ret = skl_update_scaler_crtc(pipe_config);
2129                         if (ret)
2130                                 return ret;
2131                 }
2132
2133                 if (HAS_GMCH_DISPLAY(dev_priv))
2134                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2135                                                  conn_state->scaling_mode);
2136                 else
2137                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2138                                                 conn_state->scaling_mode);
2139         }
2140
2141         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2142                 return -EINVAL;
2143
2144         if (HAS_GMCH_DISPLAY(dev_priv) &&
2145             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2146                 return -EINVAL;
2147
2148         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2149                 return -EINVAL;
2150
2151         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2152                                   intel_dp_supports_fec(intel_dp, pipe_config);
2153
2154         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2155         if (ret < 0)
2156                 return ret;
2157
2158         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2159                 /*
2160                  * See:
2161                  * CEA-861-E - 5.1 Default Encoding Parameters
2162                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2163                  */
2164                 pipe_config->limited_color_range =
2165                         pipe_config->pipe_bpp != 18 &&
2166                         drm_default_rgb_quant_range(adjusted_mode) ==
2167                         HDMI_QUANTIZATION_RANGE_LIMITED;
2168         } else {
2169                 pipe_config->limited_color_range =
2170                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2171         }
2172
2173         if (!pipe_config->dsc_params.compression_enable)
2174                 intel_link_compute_m_n(pipe_config->pipe_bpp,
2175                                        pipe_config->lane_count,
2176                                        adjusted_mode->crtc_clock,
2177                                        pipe_config->port_clock,
2178                                        &pipe_config->dp_m_n,
2179                                        constant_n);
2180         else
2181                 intel_link_compute_m_n(pipe_config->dsc_params.compressed_bpp,
2182                                        pipe_config->lane_count,
2183                                        adjusted_mode->crtc_clock,
2184                                        pipe_config->port_clock,
2185                                        &pipe_config->dp_m_n,
2186                                        constant_n);
2187
2188         if (intel_connector->panel.downclock_mode != NULL &&
2189                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2190                         pipe_config->has_drrs = true;
2191                         intel_link_compute_m_n(pipe_config->pipe_bpp,
2192                                                pipe_config->lane_count,
2193                                                intel_connector->panel.downclock_mode->clock,
2194                                                pipe_config->port_clock,
2195                                                &pipe_config->dp_m2_n2,
2196                                                constant_n);
2197         }
2198
2199         if (!HAS_DDI(dev_priv))
2200                 intel_dp_set_clock(encoder, pipe_config);
2201
2202         intel_psr_compute_config(intel_dp, pipe_config);
2203
2204         return 0;
2205 }
2206
2207 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2208                               int link_rate, uint8_t lane_count,
2209                               bool link_mst)
2210 {
2211         intel_dp->link_trained = false;
2212         intel_dp->link_rate = link_rate;
2213         intel_dp->lane_count = lane_count;
2214         intel_dp->link_mst = link_mst;
2215 }
2216
2217 static void intel_dp_prepare(struct intel_encoder *encoder,
2218                              const struct intel_crtc_state *pipe_config)
2219 {
2220         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2221         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2222         enum port port = encoder->port;
2223         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2224         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2225
2226         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2227                                  pipe_config->lane_count,
2228                                  intel_crtc_has_type(pipe_config,
2229                                                      INTEL_OUTPUT_DP_MST));
2230
2231         /*
2232          * There are four kinds of DP registers:
2233          *
2234          *      IBX PCH
2235          *      SNB CPU
2236          *      IVB CPU
2237          *      CPT PCH
2238          *
2239          * IBX PCH and CPU are the same for almost everything,
2240          * except that the CPU DP PLL is configured in this
2241          * register
2242          *
2243          * CPT PCH is quite different, having many bits moved
2244          * to the TRANS_DP_CTL register instead. That
2245          * configuration happens (oddly) in ironlake_pch_enable
2246          */
2247
2248         /* Preserve the BIOS-computed detected bit. This is
2249          * supposed to be read-only.
2250          */
2251         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2252
2253         /* Handle DP bits in common between all three register formats */
2254         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2255         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2256
2257         /* Split out the IBX/CPU vs CPT settings */
2258
2259         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2260                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2261                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2262                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2263                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2264                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2265
2266                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2267                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2268
2269                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2270         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2271                 u32 trans_dp;
2272
2273                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2274
2275                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2276                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2277                         trans_dp |= TRANS_DP_ENH_FRAMING;
2278                 else
2279                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2280                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2281         } else {
2282                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2283                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2284
2285                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2286                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2287                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2288                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2289                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2290
2291                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2292                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2293
2294                 if (IS_CHERRYVIEW(dev_priv))
2295                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2296                 else
2297                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2298         }
2299 }
2300
2301 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2302 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2303
2304 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2305 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2306
2307 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2308 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2309
2310 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2311
2312 static void wait_panel_status(struct intel_dp *intel_dp,
2313                                        u32 mask,
2314                                        u32 value)
2315 {
2316         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2317         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2318
2319         lockdep_assert_held(&dev_priv->pps_mutex);
2320
2321         intel_pps_verify_state(intel_dp);
2322
2323         pp_stat_reg = _pp_stat_reg(intel_dp);
2324         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2325
2326         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2327                         mask, value,
2328                         I915_READ(pp_stat_reg),
2329                         I915_READ(pp_ctrl_reg));
2330
2331         if (intel_wait_for_register(dev_priv,
2332                                     pp_stat_reg, mask, value,
2333                                     5000))
2334                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2335                                 I915_READ(pp_stat_reg),
2336                                 I915_READ(pp_ctrl_reg));
2337
2338         DRM_DEBUG_KMS("Wait complete\n");
2339 }
2340
2341 static void wait_panel_on(struct intel_dp *intel_dp)
2342 {
2343         DRM_DEBUG_KMS("Wait for panel power on\n");
2344         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2345 }
2346
2347 static void wait_panel_off(struct intel_dp *intel_dp)
2348 {
2349         DRM_DEBUG_KMS("Wait for panel power off time\n");
2350         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2351 }
2352
2353 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2354 {
2355         ktime_t panel_power_on_time;
2356         s64 panel_power_off_duration;
2357
2358         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2359
2360         /* take the difference of currrent time and panel power off time
2361          * and then make panel wait for t11_t12 if needed. */
2362         panel_power_on_time = ktime_get_boottime();
2363         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2364
2365         /* When we disable the VDD override bit last we have to do the manual
2366          * wait. */
2367         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2368                 wait_remaining_ms_from_jiffies(jiffies,
2369                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2370
2371         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2372 }
2373
2374 static void wait_backlight_on(struct intel_dp *intel_dp)
2375 {
2376         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2377                                        intel_dp->backlight_on_delay);
2378 }
2379
2380 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2381 {
2382         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2383                                        intel_dp->backlight_off_delay);
2384 }
2385
2386 /* Read the current pp_control value, unlocking the register if it
2387  * is locked
2388  */
2389
2390 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2391 {
2392         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2393         u32 control;
2394
2395         lockdep_assert_held(&dev_priv->pps_mutex);
2396
2397         control = I915_READ(_pp_ctrl_reg(intel_dp));
2398         if (WARN_ON(!HAS_DDI(dev_priv) &&
2399                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2400                 control &= ~PANEL_UNLOCK_MASK;
2401                 control |= PANEL_UNLOCK_REGS;
2402         }
2403         return control;
2404 }
2405
2406 /*
2407  * Must be paired with edp_panel_vdd_off().
2408  * Must hold pps_mutex around the whole on/off sequence.
2409  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2410  */
2411 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2412 {
2413         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2414         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2415         u32 pp;
2416         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2417         bool need_to_disable = !intel_dp->want_panel_vdd;
2418
2419         lockdep_assert_held(&dev_priv->pps_mutex);
2420
2421         if (!intel_dp_is_edp(intel_dp))
2422                 return false;
2423
2424         cancel_delayed_work(&intel_dp->panel_vdd_work);
2425         intel_dp->want_panel_vdd = true;
2426
2427         if (edp_have_panel_vdd(intel_dp))
2428                 return need_to_disable;
2429
2430         intel_display_power_get(dev_priv,
2431                                 intel_aux_power_domain(intel_dig_port));
2432
2433         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2434                       port_name(intel_dig_port->base.port));
2435
2436         if (!edp_have_panel_power(intel_dp))
2437                 wait_panel_power_cycle(intel_dp);
2438
2439         pp = ironlake_get_pp_control(intel_dp);
2440         pp |= EDP_FORCE_VDD;
2441
2442         pp_stat_reg = _pp_stat_reg(intel_dp);
2443         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2444
2445         I915_WRITE(pp_ctrl_reg, pp);
2446         POSTING_READ(pp_ctrl_reg);
2447         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2448                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2449         /*
2450          * If the panel wasn't on, delay before accessing aux channel
2451          */
2452         if (!edp_have_panel_power(intel_dp)) {
2453                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2454                               port_name(intel_dig_port->base.port));
2455                 msleep(intel_dp->panel_power_up_delay);
2456         }
2457
2458         return need_to_disable;
2459 }
2460
2461 /*
2462  * Must be paired with intel_edp_panel_vdd_off() or
2463  * intel_edp_panel_off().
2464  * Nested calls to these functions are not allowed since
2465  * we drop the lock. Caller must use some higher level
2466  * locking to prevent nested calls from other threads.
2467  */
2468 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2469 {
2470         bool vdd;
2471
2472         if (!intel_dp_is_edp(intel_dp))
2473                 return;
2474
2475         pps_lock(intel_dp);
2476         vdd = edp_panel_vdd_on(intel_dp);
2477         pps_unlock(intel_dp);
2478
2479         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2480              port_name(dp_to_dig_port(intel_dp)->base.port));
2481 }
2482
2483 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2484 {
2485         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2486         struct intel_digital_port *intel_dig_port =
2487                 dp_to_dig_port(intel_dp);
2488         u32 pp;
2489         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2490
2491         lockdep_assert_held(&dev_priv->pps_mutex);
2492
2493         WARN_ON(intel_dp->want_panel_vdd);
2494
2495         if (!edp_have_panel_vdd(intel_dp))
2496                 return;
2497
2498         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2499                       port_name(intel_dig_port->base.port));
2500
2501         pp = ironlake_get_pp_control(intel_dp);
2502         pp &= ~EDP_FORCE_VDD;
2503
2504         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2505         pp_stat_reg = _pp_stat_reg(intel_dp);
2506
2507         I915_WRITE(pp_ctrl_reg, pp);
2508         POSTING_READ(pp_ctrl_reg);
2509
2510         /* Make sure sequencer is idle before allowing subsequent activity */
2511         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2512         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2513
2514         if ((pp & PANEL_POWER_ON) == 0)
2515                 intel_dp->panel_power_off_time = ktime_get_boottime();
2516
2517         intel_display_power_put(dev_priv,
2518                                 intel_aux_power_domain(intel_dig_port));
2519 }
2520
2521 static void edp_panel_vdd_work(struct work_struct *__work)
2522 {
2523         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2524                                                  struct intel_dp, panel_vdd_work);
2525
2526         pps_lock(intel_dp);
2527         if (!intel_dp->want_panel_vdd)
2528                 edp_panel_vdd_off_sync(intel_dp);
2529         pps_unlock(intel_dp);
2530 }
2531
2532 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2533 {
2534         unsigned long delay;
2535
2536         /*
2537          * Queue the timer to fire a long time from now (relative to the power
2538          * down delay) to keep the panel power up across a sequence of
2539          * operations.
2540          */
2541         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2542         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2543 }
2544
2545 /*
2546  * Must be paired with edp_panel_vdd_on().
2547  * Must hold pps_mutex around the whole on/off sequence.
2548  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2549  */
2550 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2551 {
2552         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2553
2554         lockdep_assert_held(&dev_priv->pps_mutex);
2555
2556         if (!intel_dp_is_edp(intel_dp))
2557                 return;
2558
2559         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2560              port_name(dp_to_dig_port(intel_dp)->base.port));
2561
2562         intel_dp->want_panel_vdd = false;
2563
2564         if (sync)
2565                 edp_panel_vdd_off_sync(intel_dp);
2566         else
2567                 edp_panel_vdd_schedule_off(intel_dp);
2568 }
2569
2570 static void edp_panel_on(struct intel_dp *intel_dp)
2571 {
2572         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2573         u32 pp;
2574         i915_reg_t pp_ctrl_reg;
2575
2576         lockdep_assert_held(&dev_priv->pps_mutex);
2577
2578         if (!intel_dp_is_edp(intel_dp))
2579                 return;
2580
2581         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2582                       port_name(dp_to_dig_port(intel_dp)->base.port));
2583
2584         if (WARN(edp_have_panel_power(intel_dp),
2585                  "eDP port %c panel power already on\n",
2586                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2587                 return;
2588
2589         wait_panel_power_cycle(intel_dp);
2590
2591         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2592         pp = ironlake_get_pp_control(intel_dp);
2593         if (IS_GEN5(dev_priv)) {
2594                 /* ILK workaround: disable reset around power sequence */
2595                 pp &= ~PANEL_POWER_RESET;
2596                 I915_WRITE(pp_ctrl_reg, pp);
2597                 POSTING_READ(pp_ctrl_reg);
2598         }
2599
2600         pp |= PANEL_POWER_ON;
2601         if (!IS_GEN5(dev_priv))
2602                 pp |= PANEL_POWER_RESET;
2603
2604         I915_WRITE(pp_ctrl_reg, pp);
2605         POSTING_READ(pp_ctrl_reg);
2606
2607         wait_panel_on(intel_dp);
2608         intel_dp->last_power_on = jiffies;
2609
2610         if (IS_GEN5(dev_priv)) {
2611                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2612                 I915_WRITE(pp_ctrl_reg, pp);
2613                 POSTING_READ(pp_ctrl_reg);
2614         }
2615 }
2616
2617 void intel_edp_panel_on(struct intel_dp *intel_dp)
2618 {
2619         if (!intel_dp_is_edp(intel_dp))
2620                 return;
2621
2622         pps_lock(intel_dp);
2623         edp_panel_on(intel_dp);
2624         pps_unlock(intel_dp);
2625 }
2626
2627
2628 static void edp_panel_off(struct intel_dp *intel_dp)
2629 {
2630         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2631         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2632         u32 pp;
2633         i915_reg_t pp_ctrl_reg;
2634
2635         lockdep_assert_held(&dev_priv->pps_mutex);
2636
2637         if (!intel_dp_is_edp(intel_dp))
2638                 return;
2639
2640         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2641                       port_name(dig_port->base.port));
2642
2643         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2644              port_name(dig_port->base.port));
2645
2646         pp = ironlake_get_pp_control(intel_dp);
2647         /* We need to switch off panel power _and_ force vdd, for otherwise some
2648          * panels get very unhappy and cease to work. */
2649         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2650                 EDP_BLC_ENABLE);
2651
2652         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2653
2654         intel_dp->want_panel_vdd = false;
2655
2656         I915_WRITE(pp_ctrl_reg, pp);
2657         POSTING_READ(pp_ctrl_reg);
2658
2659         wait_panel_off(intel_dp);
2660         intel_dp->panel_power_off_time = ktime_get_boottime();
2661
2662         /* We got a reference when we enabled the VDD. */
2663         intel_display_power_put(dev_priv, intel_aux_power_domain(dig_port));
2664 }
2665
2666 void intel_edp_panel_off(struct intel_dp *intel_dp)
2667 {
2668         if (!intel_dp_is_edp(intel_dp))
2669                 return;
2670
2671         pps_lock(intel_dp);
2672         edp_panel_off(intel_dp);
2673         pps_unlock(intel_dp);
2674 }
2675
2676 /* Enable backlight in the panel power control. */
2677 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2678 {
2679         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2680         u32 pp;
2681         i915_reg_t pp_ctrl_reg;
2682
2683         /*
2684          * If we enable the backlight right away following a panel power
2685          * on, we may see slight flicker as the panel syncs with the eDP
2686          * link.  So delay a bit to make sure the image is solid before
2687          * allowing it to appear.
2688          */
2689         wait_backlight_on(intel_dp);
2690
2691         pps_lock(intel_dp);
2692
2693         pp = ironlake_get_pp_control(intel_dp);
2694         pp |= EDP_BLC_ENABLE;
2695
2696         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2697
2698         I915_WRITE(pp_ctrl_reg, pp);
2699         POSTING_READ(pp_ctrl_reg);
2700
2701         pps_unlock(intel_dp);
2702 }
2703
2704 /* Enable backlight PWM and backlight PP control. */
2705 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2706                             const struct drm_connector_state *conn_state)
2707 {
2708         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2709
2710         if (!intel_dp_is_edp(intel_dp))
2711                 return;
2712
2713         DRM_DEBUG_KMS("\n");
2714
2715         intel_panel_enable_backlight(crtc_state, conn_state);
2716         _intel_edp_backlight_on(intel_dp);
2717 }
2718
2719 /* Disable backlight in the panel power control. */
2720 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2721 {
2722         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2723         u32 pp;
2724         i915_reg_t pp_ctrl_reg;
2725
2726         if (!intel_dp_is_edp(intel_dp))
2727                 return;
2728
2729         pps_lock(intel_dp);
2730
2731         pp = ironlake_get_pp_control(intel_dp);
2732         pp &= ~EDP_BLC_ENABLE;
2733
2734         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2735
2736         I915_WRITE(pp_ctrl_reg, pp);
2737         POSTING_READ(pp_ctrl_reg);
2738
2739         pps_unlock(intel_dp);
2740
2741         intel_dp->last_backlight_off = jiffies;
2742         edp_wait_backlight_off(intel_dp);
2743 }
2744
2745 /* Disable backlight PP control and backlight PWM. */
2746 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2747 {
2748         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2749
2750         if (!intel_dp_is_edp(intel_dp))
2751                 return;
2752
2753         DRM_DEBUG_KMS("\n");
2754
2755         _intel_edp_backlight_off(intel_dp);
2756         intel_panel_disable_backlight(old_conn_state);
2757 }
2758
2759 /*
2760  * Hook for controlling the panel power control backlight through the bl_power
2761  * sysfs attribute. Take care to handle multiple calls.
2762  */
2763 static void intel_edp_backlight_power(struct intel_connector *connector,
2764                                       bool enable)
2765 {
2766         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2767         bool is_enabled;
2768
2769         pps_lock(intel_dp);
2770         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2771         pps_unlock(intel_dp);
2772
2773         if (is_enabled == enable)
2774                 return;
2775
2776         DRM_DEBUG_KMS("panel power control backlight %s\n",
2777                       enable ? "enable" : "disable");
2778
2779         if (enable)
2780                 _intel_edp_backlight_on(intel_dp);
2781         else
2782                 _intel_edp_backlight_off(intel_dp);
2783 }
2784
2785 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2786 {
2787         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2788         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2789         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2790
2791         I915_STATE_WARN(cur_state != state,
2792                         "DP port %c state assertion failure (expected %s, current %s)\n",
2793                         port_name(dig_port->base.port),
2794                         onoff(state), onoff(cur_state));
2795 }
2796 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2797
2798 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2799 {
2800         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2801
2802         I915_STATE_WARN(cur_state != state,
2803                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2804                         onoff(state), onoff(cur_state));
2805 }
2806 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2807 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2808
2809 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2810                                 const struct intel_crtc_state *pipe_config)
2811 {
2812         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2813         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2814
2815         assert_pipe_disabled(dev_priv, crtc->pipe);
2816         assert_dp_port_disabled(intel_dp);
2817         assert_edp_pll_disabled(dev_priv);
2818
2819         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2820                       pipe_config->port_clock);
2821
2822         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2823
2824         if (pipe_config->port_clock == 162000)
2825                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2826         else
2827                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2828
2829         I915_WRITE(DP_A, intel_dp->DP);
2830         POSTING_READ(DP_A);
2831         udelay(500);
2832
2833         /*
2834          * [DevILK] Work around required when enabling DP PLL
2835          * while a pipe is enabled going to FDI:
2836          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2837          * 2. Program DP PLL enable
2838          */
2839         if (IS_GEN5(dev_priv))
2840                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2841
2842         intel_dp->DP |= DP_PLL_ENABLE;
2843
2844         I915_WRITE(DP_A, intel_dp->DP);
2845         POSTING_READ(DP_A);
2846         udelay(200);
2847 }
2848
2849 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2850                                  const struct intel_crtc_state *old_crtc_state)
2851 {
2852         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2853         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2854
2855         assert_pipe_disabled(dev_priv, crtc->pipe);
2856         assert_dp_port_disabled(intel_dp);
2857         assert_edp_pll_enabled(dev_priv);
2858
2859         DRM_DEBUG_KMS("disabling eDP PLL\n");
2860
2861         intel_dp->DP &= ~DP_PLL_ENABLE;
2862
2863         I915_WRITE(DP_A, intel_dp->DP);
2864         POSTING_READ(DP_A);
2865         udelay(200);
2866 }
2867
2868 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2869 {
2870         /*
2871          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2872          * be capable of signalling downstream hpd with a long pulse.
2873          * Whether or not that means D3 is safe to use is not clear,
2874          * but let's assume so until proven otherwise.
2875          *
2876          * FIXME should really check all downstream ports...
2877          */
2878         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2879                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2880                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2881 }
2882
2883 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2884                                            const struct intel_crtc_state *crtc_state,
2885                                            bool enable)
2886 {
2887         int ret;
2888
2889         if (!crtc_state->dsc_params.compression_enable)
2890                 return;
2891
2892         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2893                                  enable ? DP_DECOMPRESSION_EN : 0);
2894         if (ret < 0)
2895                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2896                               enable ? "enable" : "disable");
2897 }
2898
2899 /* If the sink supports it, try to set the power state appropriately */
2900 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2901 {
2902         int ret, i;
2903
2904         /* Should have a valid DPCD by this point */
2905         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2906                 return;
2907
2908         if (mode != DRM_MODE_DPMS_ON) {
2909                 if (downstream_hpd_needs_d0(intel_dp))
2910                         return;
2911
2912                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2913                                          DP_SET_POWER_D3);
2914         } else {
2915                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2916
2917                 /*
2918                  * When turning on, we need to retry for 1ms to give the sink
2919                  * time to wake up.
2920                  */
2921                 for (i = 0; i < 3; i++) {
2922                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2923                                                  DP_SET_POWER_D0);
2924                         if (ret == 1)
2925                                 break;
2926                         msleep(1);
2927                 }
2928
2929                 if (ret == 1 && lspcon->active)
2930                         lspcon_wait_pcon_mode(lspcon);
2931         }
2932
2933         if (ret != 1)
2934                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2935                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2936 }
2937
2938 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2939                                  enum port port, enum pipe *pipe)
2940 {
2941         enum pipe p;
2942
2943         for_each_pipe(dev_priv, p) {
2944                 u32 val = I915_READ(TRANS_DP_CTL(p));
2945
2946                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2947                         *pipe = p;
2948                         return true;
2949                 }
2950         }
2951
2952         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2953
2954         /* must initialize pipe to something for the asserts */
2955         *pipe = PIPE_A;
2956
2957         return false;
2958 }
2959
2960 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2961                            i915_reg_t dp_reg, enum port port,
2962                            enum pipe *pipe)
2963 {
2964         bool ret;
2965         u32 val;
2966
2967         val = I915_READ(dp_reg);
2968
2969         ret = val & DP_PORT_EN;
2970
2971         /* asserts want to know the pipe even if the port is disabled */
2972         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2973                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2974         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2975                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2976         else if (IS_CHERRYVIEW(dev_priv))
2977                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2978         else
2979                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2980
2981         return ret;
2982 }
2983
2984 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2985                                   enum pipe *pipe)
2986 {
2987         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2988         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2989         bool ret;
2990
2991         if (!intel_display_power_get_if_enabled(dev_priv,
2992                                                 encoder->power_domain))
2993                 return false;
2994
2995         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2996                                     encoder->port, pipe);
2997
2998         intel_display_power_put(dev_priv, encoder->power_domain);
2999
3000         return ret;
3001 }
3002
3003 static void intel_dp_get_config(struct intel_encoder *encoder,
3004                                 struct intel_crtc_state *pipe_config)
3005 {
3006         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3007         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3008         u32 tmp, flags = 0;
3009         enum port port = encoder->port;
3010         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3011
3012         if (encoder->type == INTEL_OUTPUT_EDP)
3013                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3014         else
3015                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3016
3017         tmp = I915_READ(intel_dp->output_reg);
3018
3019         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3020
3021         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3022                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3023
3024                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3025                         flags |= DRM_MODE_FLAG_PHSYNC;
3026                 else
3027                         flags |= DRM_MODE_FLAG_NHSYNC;
3028
3029                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3030                         flags |= DRM_MODE_FLAG_PVSYNC;
3031                 else
3032                         flags |= DRM_MODE_FLAG_NVSYNC;
3033         } else {
3034                 if (tmp & DP_SYNC_HS_HIGH)
3035                         flags |= DRM_MODE_FLAG_PHSYNC;
3036                 else
3037                         flags |= DRM_MODE_FLAG_NHSYNC;
3038
3039                 if (tmp & DP_SYNC_VS_HIGH)
3040                         flags |= DRM_MODE_FLAG_PVSYNC;
3041                 else
3042                         flags |= DRM_MODE_FLAG_NVSYNC;
3043         }
3044
3045         pipe_config->base.adjusted_mode.flags |= flags;
3046
3047         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3048                 pipe_config->limited_color_range = true;
3049
3050         pipe_config->lane_count =
3051                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3052
3053         intel_dp_get_m_n(crtc, pipe_config);
3054
3055         if (port == PORT_A) {
3056                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3057                         pipe_config->port_clock = 162000;
3058                 else
3059                         pipe_config->port_clock = 270000;
3060         }
3061
3062         pipe_config->base.adjusted_mode.crtc_clock =
3063                 intel_dotclock_calculate(pipe_config->port_clock,
3064                                          &pipe_config->dp_m_n);
3065
3066         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3067             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3068                 /*
3069                  * This is a big fat ugly hack.
3070                  *
3071                  * Some machines in UEFI boot mode provide us a VBT that has 18
3072                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3073                  * unknown we fail to light up. Yet the same BIOS boots up with
3074                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3075                  * max, not what it tells us to use.
3076                  *
3077                  * Note: This will still be broken if the eDP panel is not lit
3078                  * up by the BIOS, and thus we can't get the mode at module
3079                  * load.
3080                  */
3081                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3082                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3083                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3084         }
3085 }
3086
3087 static void intel_disable_dp(struct intel_encoder *encoder,
3088                              const struct intel_crtc_state *old_crtc_state,
3089                              const struct drm_connector_state *old_conn_state)
3090 {
3091         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3092
3093         intel_dp->link_trained = false;
3094
3095         if (old_crtc_state->has_audio)
3096                 intel_audio_codec_disable(encoder,
3097                                           old_crtc_state, old_conn_state);
3098
3099         /* Make sure the panel is off before trying to change the mode. But also
3100          * ensure that we have vdd while we switch off the panel. */
3101         intel_edp_panel_vdd_on(intel_dp);
3102         intel_edp_backlight_off(old_conn_state);
3103         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3104         intel_edp_panel_off(intel_dp);
3105 }
3106
3107 static void g4x_disable_dp(struct intel_encoder *encoder,
3108                            const struct intel_crtc_state *old_crtc_state,
3109                            const struct drm_connector_state *old_conn_state)
3110 {
3111         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3112 }
3113
3114 static void vlv_disable_dp(struct intel_encoder *encoder,
3115                            const struct intel_crtc_state *old_crtc_state,
3116                            const struct drm_connector_state *old_conn_state)
3117 {
3118         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3119 }
3120
3121 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3122                                 const struct intel_crtc_state *old_crtc_state,
3123                                 const struct drm_connector_state *old_conn_state)
3124 {
3125         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);