drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include "intel_drv.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  45 #define DP_DPRX_ESI_LEN 14
  46
  47 /* Compliance test status bits  */
  48 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  49 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  50 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52
  53 struct dp_link_dpll {
  54         int clock;
  55         struct dpll dpll;
  56 };
  57
  58 static const struct dp_link_dpll gen4_dpll[] = {
  59         { 162000,
  60                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  61         { 270000,
  62                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  63 };
  64
  65 static const struct dp_link_dpll pch_dpll[] = {
  66         { 162000,
  67                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  68         { 270000,
  69                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  70 };
  71
  72 static const struct dp_link_dpll vlv_dpll[] = {
  73         { 162000,
  74                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  75         { 270000,
  76                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  77 };
  78
  79 /*
  80  * CHV supports eDP 1.4 that have  more link rates.
  81  * Below only provides the fixed rate but exclude variable rate.
  82  */
  83 static const struct dp_link_dpll chv_dpll[] = {
  84         /*
  85          * CHV requires to program fractional division for m2.
  86          * m2 is stored in fixed point format using formula below
  87          * (m2_int << 22) | m2_fraction
  88          */
  89         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  90                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  91         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  92                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  93         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  94                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  95 };
  96
  97 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  98                                   324000, 432000, 540000 };
  99 static const int skl_rates[] = { 162000, 216000, 270000,
 100                                   324000, 432000, 540000 };
 101 static const int cnl_rates[] = { 162000, 216000, 270000,
 102                                  324000, 432000, 540000,
 103                                  648000, 810000 };
 104 static const int default_rates[] = { 162000, 270000, 540000 };
 105
 106 /**
 107  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 108  * @intel_dp: DP struct
 109  *
 110  * If a CPU or PCH DP output is attached to an eDP panel, this function
 111  * will return true, and false otherwise.
 112  */
 113 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 114 {
 115         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 116
 117         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 118 }
 119
 120 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 121 {
 122         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 123
 124         return intel_dig_port->base.base.dev;
 125 }
 126
 127 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 128 {
 129         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 130 }
 131
 132 static void intel_dp_link_down(struct intel_encoder *encoder,
 133                                const struct intel_crtc_state *old_crtc_state);
 134 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 135 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 136 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 137                                            const struct intel_crtc_state *crtc_state);
 138 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 139                                       enum pipe pipe);
 140 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 141
 142 /* update sink rates from dpcd */
 143 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 144 {
 145         int i, max_rate;
 146
 147         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 148
 149         for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
 150                 if (default_rates[i] > max_rate)
 151                         break;
 152                 intel_dp->sink_rates[i] = default_rates[i];
 153         }
 154
 155         intel_dp->num_sink_rates = i;
 156 }
 157
 158 /* Theoretical max between source and sink */
 159 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 160 {
 161         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 162 }
 163
 164 /* Theoretical max between source and sink */
 165 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 166 {
 167         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 168         int source_max = intel_dig_port->max_lanes;
 169         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 170
 171         return min(source_max, sink_max);
 172 }
 173
 174 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 175 {
 176         return intel_dp->max_link_lane_count;
 177 }
 178
 179 int
 180 intel_dp_link_required(int pixel_clock, int bpp)
 181 {
 182         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 183         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 184 }
 185
 186 int
 187 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 188 {
 189         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 190          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 191          * is transmitted every LS_Clk per lane, there is no need to account for
 192          * the channel encoding that is done in the PHY layer here.
 193          */
 194
 195         return max_link_clock * max_lanes;
 196 }
 197
 198 static int
 199 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 200 {
 201         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 202         struct intel_encoder *encoder = &intel_dig_port->base;
 203         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 204         int max_dotclk = dev_priv->max_dotclk_freq;
 205         int ds_max_dotclk;
 206
 207         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 208
 209         if (type != DP_DS_PORT_TYPE_VGA)
 210                 return max_dotclk;
 211
 212         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 213                                                     intel_dp->downstream_ports);
 214
 215         if (ds_max_dotclk != 0)
 216                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 217
 218         return max_dotclk;
 219 }
 220
 221 static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size)
 222 {
 223         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 224         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 225         enum port port = dig_port->base.port;
 226
 227         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 228
 229         /* Low voltage SKUs are limited to max of 5.4G */
 230         if (voltage == VOLTAGE_INFO_0_85V)
 231                 return size - 2;
 232
 233         /* For this SKU 8.1G is supported in all ports */
 234         if (IS_CNL_WITH_PORT_F(dev_priv))
 235                 return size;
 236
 237         /* For other SKUs, max rate on ports A and B is 5.4G */
 238         if (port == PORT_A || port == PORT_D)
 239                 return size - 2;
 240
 241         return size;
 242 }
 243
 244 static void
 245 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 246 {
 247         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 248         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 249         const int *source_rates;
 250         int size;
 251
 252         /* This should only be done once */
 253         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 254
 255         if (IS_GEN9_LP(dev_priv)) {
 256                 source_rates = bxt_rates;
 257                 size = ARRAY_SIZE(bxt_rates);
 258         } else if (IS_CANNONLAKE(dev_priv)) {
 259                 source_rates = cnl_rates;
 260                 size = cnl_adjusted_max_rate(intel_dp, ARRAY_SIZE(cnl_rates));
 261         } else if (IS_GEN9_BC(dev_priv)) {
 262                 source_rates = skl_rates;
 263                 size = ARRAY_SIZE(skl_rates);
 264         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 265                    IS_BROADWELL(dev_priv)) {
 266                 source_rates = default_rates;
 267                 size = ARRAY_SIZE(default_rates);
 268         } else {
 269                 source_rates = default_rates;
 270                 size = ARRAY_SIZE(default_rates) - 1;
 271         }
 272
 273         intel_dp->source_rates = source_rates;
 274         intel_dp->num_source_rates = size;
 275 }
 276
 277 static int intersect_rates(const int *source_rates, int source_len,
 278                            const int *sink_rates, int sink_len,
 279                            int *common_rates)
 280 {
 281         int i = 0, j = 0, k = 0;
 282
 283         while (i < source_len && j < sink_len) {
 284                 if (source_rates[i] == sink_rates[j]) {
 285                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 286                                 return k;
 287                         common_rates[k] = source_rates[i];
 288                         ++k;
 289                         ++i;
 290                         ++j;
 291                 } else if (source_rates[i] < sink_rates[j]) {
 292                         ++i;
 293                 } else {
 294                         ++j;
 295                 }
 296         }
 297         return k;
 298 }
 299
 300 /* return index of rate in rates array, or -1 if not found */
 301 static int intel_dp_rate_index(const int *rates, int len, int rate)
 302 {
 303         int i;
 304
 305         for (i = 0; i < len; i++)
 306                 if (rate == rates[i])
 307                         return i;
 308
 309         return -1;
 310 }
 311
 312 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 313 {
 314         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 315
 316         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 317                                                      intel_dp->num_source_rates,
 318                                                      intel_dp->sink_rates,
 319                                                      intel_dp->num_sink_rates,
 320                                                      intel_dp->common_rates);
 321
 322         /* Paranoia, there should always be something in common. */
 323         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 324                 intel_dp->common_rates[0] = default_rates[0];
 325                 intel_dp->num_common_rates = 1;
 326         }
 327 }
 328
 329 /* get length of common rates potentially limited by max_rate */
 330 static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
 331                                           int max_rate)
 332 {
 333         const int *common_rates = intel_dp->common_rates;
 334         int i, common_len = intel_dp->num_common_rates;
 335
 336         /* Limit results by potentially reduced max rate */
 337         for (i = 0; i < common_len; i++) {
 338                 if (common_rates[common_len - i - 1] <= max_rate)
 339                         return common_len - i;
 340         }
 341
 342         return 0;
 343 }
 344
 345 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 346                                        uint8_t lane_count)
 347 {
 348         /*
 349          * FIXME: we need to synchronize the current link parameters with
 350          * hardware readout. Currently fast link training doesn't work on
 351          * boot-up.
 352          */
 353         if (link_rate == 0 ||
 354             link_rate > intel_dp->max_link_rate)
 355                 return false;
 356
 357         if (lane_count == 0 ||
 358             lane_count > intel_dp_max_lane_count(intel_dp))
 359                 return false;
 360
 361         return true;
 362 }
 363
 364 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 365                                             int link_rate, uint8_t lane_count)
 366 {
 367         int index;
 368
 369         index = intel_dp_rate_index(intel_dp->common_rates,
 370                                     intel_dp->num_common_rates,
 371                                     link_rate);
 372         if (index > 0) {
 373                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 374                 intel_dp->max_link_lane_count = lane_count;
 375         } else if (lane_count > 1) {
 376                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 377                 intel_dp->max_link_lane_count = lane_count >> 1;
 378         } else {
 379                 DRM_ERROR("Link Training Unsuccessful\n");
 380                 return -1;
 381         }
 382
 383         return 0;
 384 }
 385
 386 static enum drm_mode_status
 387 intel_dp_mode_valid(struct drm_connector *connector,
 388                     struct drm_display_mode *mode)
 389 {
 390         struct intel_dp *intel_dp = intel_attached_dp(connector);
 391         struct intel_connector *intel_connector = to_intel_connector(connector);
 392         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 393         int target_clock = mode->clock;
 394         int max_rate, mode_rate, max_lanes, max_link_clock;
 395         int max_dotclk;
 396
 397         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 398
 399         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 400                 if (mode->hdisplay > fixed_mode->hdisplay)
 401                         return MODE_PANEL;
 402
 403                 if (mode->vdisplay > fixed_mode->vdisplay)
 404                         return MODE_PANEL;
 405
 406                 target_clock = fixed_mode->clock;
 407         }
 408
 409         max_link_clock = intel_dp_max_link_rate(intel_dp);
 410         max_lanes = intel_dp_max_lane_count(intel_dp);
 411
 412         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 413         mode_rate = intel_dp_link_required(target_clock, 18);
 414
 415         if (mode_rate > max_rate || target_clock > max_dotclk)
 416                 return MODE_CLOCK_HIGH;
 417
 418         if (mode->clock < 10000)
 419                 return MODE_CLOCK_LOW;
 420
 421         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 422                 return MODE_H_ILLEGAL;
 423
 424         return MODE_OK;
 425 }
 426
 427 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 428 {
 429         int     i;
 430         uint32_t v = 0;
 431
 432         if (src_bytes > 4)
 433                 src_bytes = 4;
 434         for (i = 0; i < src_bytes; i++)
 435                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 436         return v;
 437 }
 438
 439 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 440 {
 441         int i;
 442         if (dst_bytes > 4)
 443                 dst_bytes = 4;
 444         for (i = 0; i < dst_bytes; i++)
 445                 dst[i] = src >> ((3-i) * 8);
 446 }
 447
 448 static void
 449 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 450 static void
 451 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 452                                               bool force_disable_vdd);
 453 static void
 454 intel_dp_pps_init(struct intel_dp *intel_dp);
 455
 456 static void pps_lock(struct intel_dp *intel_dp)
 457 {
 458         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 459
 460         /*
 461          * See intel_power_sequencer_reset() why we need
 462          * a power domain reference here.
 463          */
 464         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 465
 466         mutex_lock(&dev_priv->pps_mutex);
 467 }
 468
 469 static void pps_unlock(struct intel_dp *intel_dp)
 470 {
 471         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 472
 473         mutex_unlock(&dev_priv->pps_mutex);
 474
 475         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 476 }
 477
 478 static void
 479 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 480 {
 481         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 482         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 483         enum pipe pipe = intel_dp->pps_pipe;
 484         bool pll_enabled, release_cl_override = false;
 485         enum dpio_phy phy = DPIO_PHY(pipe);
 486         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 487         uint32_t DP;
 488
 489         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 490                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 491                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 492                 return;
 493
 494         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 495                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 496
 497         /* Preserve the BIOS-computed detected bit. This is
 498          * supposed to be read-only.
 499          */
 500         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 501         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 502         DP |= DP_PORT_WIDTH(1);
 503         DP |= DP_LINK_TRAIN_PAT_1;
 504
 505         if (IS_CHERRYVIEW(dev_priv))
 506                 DP |= DP_PIPE_SELECT_CHV(pipe);
 507         else if (pipe == PIPE_B)
 508                 DP |= DP_PIPEB_SELECT;
 509
 510         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 511
 512         /*
 513          * The DPLL for the pipe must be enabled for this to work.
 514          * So enable temporarily it if it's not already enabled.
 515          */
 516         if (!pll_enabled) {
 517                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 518                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 519
 520                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 521                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 522                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 523                                   pipe_name(pipe));
 524                         return;
 525                 }
 526         }
 527
 528         /*
 529          * Similar magic as in intel_dp_enable_port().
 530          * We _must_ do this port enable + disable trick
 531          * to make this power seqeuencer lock onto the port.
 532          * Otherwise even VDD force bit won't work.
 533          */
 534         I915_WRITE(intel_dp->output_reg, DP);
 535         POSTING_READ(intel_dp->output_reg);
 536
 537         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 538         POSTING_READ(intel_dp->output_reg);
 539
 540         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 541         POSTING_READ(intel_dp->output_reg);
 542
 543         if (!pll_enabled) {
 544                 vlv_force_pll_off(dev_priv, pipe);
 545
 546                 if (release_cl_override)
 547                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 548         }
 549 }
 550
 551 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 552 {
 553         struct intel_encoder *encoder;
 554         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 555
 556         /*
 557          * We don't have power sequencer currently.
 558          * Pick one that's not used by other ports.
 559          */
 560         for_each_intel_encoder(&dev_priv->drm, encoder) {
 561                 struct intel_dp *intel_dp;
 562
 563                 if (encoder->type != INTEL_OUTPUT_DP &&
 564                     encoder->type != INTEL_OUTPUT_EDP)
 565                         continue;
 566
 567                 intel_dp = enc_to_intel_dp(&encoder->base);
 568
 569                 if (encoder->type == INTEL_OUTPUT_EDP) {
 570                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 571                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 572
 573                         if (intel_dp->pps_pipe != INVALID_PIPE)
 574                                 pipes &= ~(1 << intel_dp->pps_pipe);
 575                 } else {
 576                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 577
 578                         if (intel_dp->active_pipe != INVALID_PIPE)
 579                                 pipes &= ~(1 << intel_dp->active_pipe);
 580                 }
 581         }
 582
 583         if (pipes == 0)
 584                 return INVALID_PIPE;
 585
 586         return ffs(pipes) - 1;
 587 }
 588
 589 static enum pipe
 590 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 591 {
 592         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 593         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 594         enum pipe pipe;
 595
 596         lockdep_assert_held(&dev_priv->pps_mutex);
 597
 598         /* We should never land here with regular DP ports */
 599         WARN_ON(!intel_dp_is_edp(intel_dp));
 600
 601         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 602                 intel_dp->active_pipe != intel_dp->pps_pipe);
 603
 604         if (intel_dp->pps_pipe != INVALID_PIPE)
 605                 return intel_dp->pps_pipe;
 606
 607         pipe = vlv_find_free_pps(dev_priv);
 608
 609         /*
 610          * Didn't find one. This should not happen since there
 611          * are two power sequencers and up to two eDP ports.
 612          */
 613         if (WARN_ON(pipe == INVALID_PIPE))
 614                 pipe = PIPE_A;
 615
 616         vlv_steal_power_sequencer(dev_priv, pipe);
 617         intel_dp->pps_pipe = pipe;
 618
 619         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 620                       pipe_name(intel_dp->pps_pipe),
 621                       port_name(intel_dig_port->base.port));
 622
 623         /* init power sequencer on this pipe and port */
 624         intel_dp_init_panel_power_sequencer(intel_dp);
 625         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 626
 627         /*
 628          * Even vdd force doesn't work until we've made
 629          * the power sequencer lock in on the port.
 630          */
 631         vlv_power_sequencer_kick(intel_dp);
 632
 633         return intel_dp->pps_pipe;
 634 }
 635
 636 static int
 637 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 638 {
 639         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 640
 641         lockdep_assert_held(&dev_priv->pps_mutex);
 642
 643         /* We should never land here with regular DP ports */
 644         WARN_ON(!intel_dp_is_edp(intel_dp));
 645
 646         /*
 647          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 648          * mapping needs to be retrieved from VBT, for now just hard-code to
 649          * use instance #0 always.
 650          */
 651         if (!intel_dp->pps_reset)
 652                 return 0;
 653
 654         intel_dp->pps_reset = false;
 655
 656         /*
 657          * Only the HW needs to be reprogrammed, the SW state is fixed and
 658          * has been setup during connector init.
 659          */
 660         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 661
 662         return 0;
 663 }
 664
 665 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 666                                enum pipe pipe);
 667
 668 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 669                                enum pipe pipe)
 670 {
 671         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 672 }
 673
 674 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 675                                 enum pipe pipe)
 676 {
 677         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 678 }
 679
 680 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 681                          enum pipe pipe)
 682 {
 683         return true;
 684 }
 685
 686 static enum pipe
 687 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 688                      enum port port,
 689                      vlv_pipe_check pipe_check)
 690 {
 691         enum pipe pipe;
 692
 693         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 694                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 695                         PANEL_PORT_SELECT_MASK;
 696
 697                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 698                         continue;
 699
 700                 if (!pipe_check(dev_priv, pipe))
 701                         continue;
 702
 703                 return pipe;
 704         }
 705
 706         return INVALID_PIPE;
 707 }
 708
 709 static void
 710 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 711 {
 712         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 713         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 714         enum port port = intel_dig_port->base.port;
 715
 716         lockdep_assert_held(&dev_priv->pps_mutex);
 717
 718         /* try to find a pipe with this port selected */
 719         /* first pick one where the panel is on */
 720         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 721                                                   vlv_pipe_has_pp_on);
 722         /* didn't find one? pick one where vdd is on */
 723         if (intel_dp->pps_pipe == INVALID_PIPE)
 724                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 725                                                           vlv_pipe_has_vdd_on);
 726         /* didn't find one? pick one with just the correct port */
 727         if (intel_dp->pps_pipe == INVALID_PIPE)
 728                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 729                                                           vlv_pipe_any);
 730
 731         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 732         if (intel_dp->pps_pipe == INVALID_PIPE) {
 733                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 734                               port_name(port));
 735                 return;
 736         }
 737
 738         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 739                       port_name(port), pipe_name(intel_dp->pps_pipe));
 740
 741         intel_dp_init_panel_power_sequencer(intel_dp);
 742         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 743 }
 744
 745 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 746 {
 747         struct intel_encoder *encoder;
 748
 749         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 750                     !IS_GEN9_LP(dev_priv)))
 751                 return;
 752
 753         /*
 754          * We can't grab pps_mutex here due to deadlock with power_domain
 755          * mutex when power_domain functions are called while holding pps_mutex.
 756          * That also means that in order to use pps_pipe the code needs to
 757          * hold both a power domain reference and pps_mutex, and the power domain
 758          * reference get/put must be done while _not_ holding pps_mutex.
 759          * pps_{lock,unlock}() do these steps in the correct order, so one
 760          * should use them always.
 761          */
 762
 763         for_each_intel_encoder(&dev_priv->drm, encoder) {
 764                 struct intel_dp *intel_dp;
 765
 766                 if (encoder->type != INTEL_OUTPUT_DP &&
 767                     encoder->type != INTEL_OUTPUT_EDP &&
 768                     encoder->type != INTEL_OUTPUT_DDI)
 769                         continue;
 770
 771                 intel_dp = enc_to_intel_dp(&encoder->base);
 772
 773                 /* Skip pure DVI/HDMI DDI encoders */
 774                 if (!i915_mmio_reg_valid(intel_dp->output_reg))
 775                         continue;
 776
 777                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 778
 779                 if (encoder->type != INTEL_OUTPUT_EDP)
 780                         continue;
 781
 782                 if (IS_GEN9_LP(dev_priv))
 783                         intel_dp->pps_reset = true;
 784                 else
 785                         intel_dp->pps_pipe = INVALID_PIPE;
 786         }
 787 }
 788
 789 struct pps_registers {
 790         i915_reg_t pp_ctrl;
 791         i915_reg_t pp_stat;
 792         i915_reg_t pp_on;
 793         i915_reg_t pp_off;
 794         i915_reg_t pp_div;
 795 };
 796
 797 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 798                                     struct pps_registers *regs)
 799 {
 800         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 801         int pps_idx = 0;
 802
 803         memset(regs, 0, sizeof(*regs));
 804
 805         if (IS_GEN9_LP(dev_priv))
 806                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 807         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 808                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 809
 810         regs->pp_ctrl = PP_CONTROL(pps_idx);
 811         regs->pp_stat = PP_STATUS(pps_idx);
 812         regs->pp_on = PP_ON_DELAYS(pps_idx);
 813         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 814         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
 815             !HAS_PCH_ICP(dev_priv))
 816                 regs->pp_div = PP_DIVISOR(pps_idx);
 817 }
 818
 819 static i915_reg_t
 820 _pp_ctrl_reg(struct intel_dp *intel_dp)
 821 {
 822         struct pps_registers regs;
 823
 824         intel_pps_get_registers(intel_dp, &regs);
 825
 826         return regs.pp_ctrl;
 827 }
 828
 829 static i915_reg_t
 830 _pp_stat_reg(struct intel_dp *intel_dp)
 831 {
 832         struct pps_registers regs;
 833
 834         intel_pps_get_registers(intel_dp, &regs);
 835
 836         return regs.pp_stat;
 837 }
 838
 839 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 840    This function only applicable when panel PM state is not to be tracked */
 841 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 842                               void *unused)
 843 {
 844         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 845                                                  edp_notifier);
 846         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 847
 848         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 849                 return 0;
 850
 851         pps_lock(intel_dp);
 852
 853         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 854                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 855                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 856                 u32 pp_div;
 857
 858                 pp_ctrl_reg = PP_CONTROL(pipe);
 859                 pp_div_reg  = PP_DIVISOR(pipe);
 860                 pp_div = I915_READ(pp_div_reg);
 861                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 862
 863                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 864                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 865                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 866                 msleep(intel_dp->panel_power_cycle_delay);
 867         }
 868
 869         pps_unlock(intel_dp);
 870
 871         return 0;
 872 }
 873
 874 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 875 {
 876         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 877
 878         lockdep_assert_held(&dev_priv->pps_mutex);
 879
 880         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 881             intel_dp->pps_pipe == INVALID_PIPE)
 882                 return false;
 883
 884         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 885 }
 886
 887 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 888 {
 889         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 890
 891         lockdep_assert_held(&dev_priv->pps_mutex);
 892
 893         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 894             intel_dp->pps_pipe == INVALID_PIPE)
 895                 return false;
 896
 897         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 898 }
 899
 900 static void
 901 intel_dp_check_edp(struct intel_dp *intel_dp)
 902 {
 903         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 904
 905         if (!intel_dp_is_edp(intel_dp))
 906                 return;
 907
 908         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 909                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 910                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 911                               I915_READ(_pp_stat_reg(intel_dp)),
 912                               I915_READ(_pp_ctrl_reg(intel_dp)));
 913         }
 914 }
 915
 916 static uint32_t
 917 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 918 {
 919         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 920         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 921         uint32_t status;
 922         bool done;
 923
 924 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 925         if (has_aux_irq)
 926                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 927                                           msecs_to_jiffies_timeout(10));
 928         else
 929                 done = wait_for(C, 10) == 0;
 930         if (!done)
 931                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 932                           has_aux_irq);
 933 #undef C
 934
 935         return status;
 936 }
 937
 938 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 939 {
 940         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 941         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 942
 943         if (index)
 944                 return 0;
 945
 946         /*
 947          * The clock divider is based off the hrawclk, and would like to run at
 948          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 949          */
 950         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 951 }
 952
 953 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 954 {
 955         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 956         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 957
 958         if (index)
 959                 return 0;
 960
 961         /*
 962          * The clock divider is based off the cdclk or PCH rawclk, and would
 963          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 964          * divide by 2000 and use that
 965          */
 966         if (intel_dig_port->base.port == PORT_A)
 967                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 968         else
 969                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 970 }
 971
 972 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 973 {
 974         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 975         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 976
 977         if (intel_dig_port->base.port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 978                 /* Workaround for non-ULT HSW */
 979                 switch (index) {
 980                 case 0: return 63;
 981                 case 1: return 72;
 982                 default: return 0;
 983                 }
 984         }
 985
 986         return ilk_get_aux_clock_divider(intel_dp, index);
 987 }
 988
 989 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 990 {
 991         /*
 992          * SKL doesn't need us to program the AUX clock divider (Hardware will
 993          * derive the clock from CDCLK automatically). We still implement the
 994          * get_aux_clock_divider vfunc to plug-in into the existing code.
 995          */
 996         return index ? 0 : 1;
 997 }
 998
 999 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1000                                      bool has_aux_irq,
1001                                      int send_bytes,
1002                                      uint32_t aux_clock_divider)
1003 {
1004         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1005         struct drm_i915_private *dev_priv =
1006                         to_i915(intel_dig_port->base.base.dev);
1007         uint32_t precharge, timeout;
1008
1009         if (IS_GEN6(dev_priv))
1010                 precharge = 3;
1011         else
1012                 precharge = 5;
1013
1014         if (IS_BROADWELL(dev_priv))
1015                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1016         else
1017                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1018
1019         return DP_AUX_CH_CTL_SEND_BUSY |
1020                DP_AUX_CH_CTL_DONE |
1021                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1022                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1023                timeout |
1024                DP_AUX_CH_CTL_RECEIVE_ERROR |
1025                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1026                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1027                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1028 }
1029
1030 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1031                                       bool has_aux_irq,
1032                                       int send_bytes,
1033                                       uint32_t unused)
1034 {
1035         return DP_AUX_CH_CTL_SEND_BUSY |
1036                DP_AUX_CH_CTL_DONE |
1037                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1038                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1039                DP_AUX_CH_CTL_TIME_OUT_MAX |
1040                DP_AUX_CH_CTL_RECEIVE_ERROR |
1041                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1042                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1043                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1044 }
1045
1046 static int
1047 intel_dp_aux_ch(struct intel_dp *intel_dp,
1048                 const uint8_t *send, int send_bytes,
1049                 uint8_t *recv, int recv_size)
1050 {
1051         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1052         struct drm_i915_private *dev_priv =
1053                         to_i915(intel_dig_port->base.base.dev);
1054         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1055         uint32_t aux_clock_divider;
1056         int i, ret, recv_bytes;
1057         uint32_t status;
1058         int try, clock = 0;
1059         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1060         bool vdd;
1061
1062         pps_lock(intel_dp);
1063
1064         /*
1065          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1066          * In such cases we want to leave VDD enabled and it's up to upper layers
1067          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1068          * ourselves.
1069          */
1070         vdd = edp_panel_vdd_on(intel_dp);
1071
1072         /* dp aux is extremely sensitive to irq latency, hence request the
1073          * lowest possible wakeup latency and so prevent the cpu from going into
1074          * deep sleep states.
1075          */
1076         pm_qos_update_request(&dev_priv->pm_qos, 0);
1077
1078         intel_dp_check_edp(intel_dp);
1079
1080         /* Try to wait for any previous AUX channel activity */
1081         for (try = 0; try < 3; try++) {
1082                 status = I915_READ_NOTRACE(ch_ctl);
1083                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1084                         break;
1085                 msleep(1);
1086         }
1087
1088         if (try == 3) {
1089                 static u32 last_status = -1;
1090                 const u32 status = I915_READ(ch_ctl);
1091
1092                 if (status != last_status) {
1093                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1094                              status);
1095                         last_status = status;
1096                 }
1097
1098                 ret = -EBUSY;
1099                 goto out;
1100         }
1101
1102         /* Only 5 data registers! */
1103         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1104                 ret = -E2BIG;
1105                 goto out;
1106         }
1107
1108         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1109                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1110                                                           has_aux_irq,
1111                                                           send_bytes,
1112                                                           aux_clock_divider);
1113
1114                 /* Must try at least 3 times according to DP spec */
1115                 for (try = 0; try < 5; try++) {
1116                         /* Load the send data into the aux channel data registers */
1117                         for (i = 0; i < send_bytes; i += 4)
1118                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1119                                            intel_dp_pack_aux(send + i,
1120                                                              send_bytes - i));
1121
1122                         /* Send the command and wait for it to complete */
1123                         I915_WRITE(ch_ctl, send_ctl);
1124
1125                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1126
1127                         /* Clear done status and any errors */
1128                         I915_WRITE(ch_ctl,
1129                                    status |
1130                                    DP_AUX_CH_CTL_DONE |
1131                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1132                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1133
1134                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1135                                 continue;
1136
1137                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1138                          *   400us delay required for errors and timeouts
1139                          *   Timeout errors from the HW already meet this
1140                          *   requirement so skip to next iteration
1141                          */
1142                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1143                                 usleep_range(400, 500);
1144                                 continue;
1145                         }
1146                         if (status & DP_AUX_CH_CTL_DONE)
1147                                 goto done;
1148                 }
1149         }
1150
1151         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1152                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1153                 ret = -EBUSY;
1154                 goto out;
1155         }
1156
1157 done:
1158         /* Check for timeout or receive error.
1159          * Timeouts occur when the sink is not connected
1160          */
1161         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1162                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1163                 ret = -EIO;
1164                 goto out;
1165         }
1166
1167         /* Timeouts occur when the device isn't connected, so they're
1168          * "normal" -- don't fill the kernel log with these */
1169         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1170                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1171                 ret = -ETIMEDOUT;
1172                 goto out;
1173         }
1174
1175         /* Unload any bytes sent back from the other side */
1176         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1177                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1178
1179         /*
1180          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1181          * We have no idea of what happened so we return -EBUSY so
1182          * drm layer takes care for the necessary retries.
1183          */
1184         if (recv_bytes == 0 || recv_bytes > 20) {
1185                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1186                               recv_bytes);
1187                 /*
1188                  * FIXME: This patch was created on top of a series that
1189                  * organize the retries at drm level. There EBUSY should
1190                  * also take care for 1ms wait before retrying.
1191                  * That aux retries re-org is still needed and after that is
1192                  * merged we remove this sleep from here.
1193                  */
1194                 usleep_range(1000, 1500);
1195                 ret = -EBUSY;
1196                 goto out;
1197         }
1198
1199         if (recv_bytes > recv_size)
1200                 recv_bytes = recv_size;
1201
1202         for (i = 0; i < recv_bytes; i += 4)
1203                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1204                                     recv + i, recv_bytes - i);
1205
1206         ret = recv_bytes;
1207 out:
1208         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1209
1210         if (vdd)
1211                 edp_panel_vdd_off(intel_dp, false);
1212
1213         pps_unlock(intel_dp);
1214
1215         return ret;
1216 }
1217
1218 #define BARE_ADDRESS_SIZE       3
1219 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1220 static ssize_t
1221 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1222 {
1223         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1224         uint8_t txbuf[20], rxbuf[20];
1225         size_t txsize, rxsize;
1226         int ret;
1227
1228         txbuf[0] = (msg->request << 4) |
1229                 ((msg->address >> 16) & 0xf);
1230         txbuf[1] = (msg->address >> 8) & 0xff;
1231         txbuf[2] = msg->address & 0xff;
1232         txbuf[3] = msg->size - 1;
1233
1234         switch (msg->request & ~DP_AUX_I2C_MOT) {
1235         case DP_AUX_NATIVE_WRITE:
1236         case DP_AUX_I2C_WRITE:
1237         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1238                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1239                 rxsize = 2; /* 0 or 1 data bytes */
1240
1241                 if (WARN_ON(txsize > 20))
1242                         return -E2BIG;
1243
1244                 WARN_ON(!msg->buffer != !msg->size);
1245
1246                 if (msg->buffer)
1247                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1248
1249                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1250                 if (ret > 0) {
1251                         msg->reply = rxbuf[0] >> 4;
1252
1253                         if (ret > 1) {
1254                                 /* Number of bytes written in a short write. */
1255                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1256                         } else {
1257                                 /* Return payload size. */
1258                                 ret = msg->size;
1259                         }
1260                 }
1261                 break;
1262
1263         case DP_AUX_NATIVE_READ:
1264         case DP_AUX_I2C_READ:
1265                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1266                 rxsize = msg->size + 1;
1267
1268                 if (WARN_ON(rxsize > 20))
1269                         return -E2BIG;
1270
1271                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1272                 if (ret > 0) {
1273                         msg->reply = rxbuf[0] >> 4;
1274                         /*
1275                          * Assume happy day, and copy the data. The caller is
1276                          * expected to check msg->reply before touching it.
1277                          *
1278                          * Return payload size.
1279                          */
1280                         ret--;
1281                         memcpy(msg->buffer, rxbuf + 1, ret);
1282                 }
1283                 break;
1284
1285         default:
1286                 ret = -EINVAL;
1287                 break;
1288         }
1289
1290         return ret;
1291 }
1292
1293 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1294                                 enum port port)
1295 {
1296         const struct ddi_vbt_port_info *info =
1297                 &dev_priv->vbt.ddi_port_info[port];
1298         enum port aux_port;
1299
1300         if (!info->alternate_aux_channel) {
1301                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1302                               port_name(port), port_name(port));
1303                 return port;
1304         }
1305
1306         switch (info->alternate_aux_channel) {
1307         case DP_AUX_A:
1308                 aux_port = PORT_A;
1309                 break;
1310         case DP_AUX_B:
1311                 aux_port = PORT_B;
1312                 break;
1313         case DP_AUX_C:
1314                 aux_port = PORT_C;
1315                 break;
1316         case DP_AUX_D:
1317                 aux_port = PORT_D;
1318                 break;
1319         case DP_AUX_F:
1320                 aux_port = PORT_F;
1321                 break;
1322         default:
1323                 MISSING_CASE(info->alternate_aux_channel);
1324                 aux_port = PORT_A;
1325                 break;
1326         }
1327
1328         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1329                       port_name(aux_port), port_name(port));
1330
1331         return aux_port;
1332 }
1333
1334 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1335                                   enum port port)
1336 {
1337         switch (port) {
1338         case PORT_B:
1339         case PORT_C:
1340         case PORT_D:
1341                 return DP_AUX_CH_CTL(port);
1342         default:
1343                 MISSING_CASE(port);
1344                 return DP_AUX_CH_CTL(PORT_B);
1345         }
1346 }
1347
1348 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1349                                    enum port port, int index)
1350 {
1351         switch (port) {
1352         case PORT_B:
1353         case PORT_C:
1354         case PORT_D:
1355                 return DP_AUX_CH_DATA(port, index);
1356         default:
1357                 MISSING_CASE(port);
1358                 return DP_AUX_CH_DATA(PORT_B, index);
1359         }
1360 }
1361
1362 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1363                                   enum port port)
1364 {
1365         switch (port) {
1366         case PORT_A:
1367                 return DP_AUX_CH_CTL(port);
1368         case PORT_B:
1369         case PORT_C:
1370         case PORT_D:
1371                 return PCH_DP_AUX_CH_CTL(port);
1372         default:
1373                 MISSING_CASE(port);
1374                 return DP_AUX_CH_CTL(PORT_A);
1375         }
1376 }
1377
1378 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1379                                    enum port port, int index)
1380 {
1381         switch (port) {
1382         case PORT_A:
1383                 return DP_AUX_CH_DATA(port, index);
1384         case PORT_B:
1385         case PORT_C:
1386         case PORT_D:
1387                 return PCH_DP_AUX_CH_DATA(port, index);
1388         default:
1389                 MISSING_CASE(port);
1390                 return DP_AUX_CH_DATA(PORT_A, index);
1391         }
1392 }
1393
1394 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1395                                   enum port port)
1396 {
1397         switch (port) {
1398         case PORT_A:
1399         case PORT_B:
1400         case PORT_C:
1401         case PORT_D:
1402         case PORT_F:
1403                 return DP_AUX_CH_CTL(port);
1404         default:
1405                 MISSING_CASE(port);
1406                 return DP_AUX_CH_CTL(PORT_A);
1407         }
1408 }
1409
1410 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1411                                    enum port port, int index)
1412 {
1413         switch (port) {
1414         case PORT_A:
1415         case PORT_B:
1416         case PORT_C:
1417         case PORT_D:
1418         case PORT_F:
1419                 return DP_AUX_CH_DATA(port, index);
1420         default:
1421                 MISSING_CASE(port);
1422                 return DP_AUX_CH_DATA(PORT_A, index);
1423         }
1424 }
1425
1426 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1427                                     enum port port)
1428 {
1429         if (INTEL_INFO(dev_priv)->gen >= 9)
1430                 return skl_aux_ctl_reg(dev_priv, port);
1431         else if (HAS_PCH_SPLIT(dev_priv))
1432                 return ilk_aux_ctl_reg(dev_priv, port);
1433         else
1434                 return g4x_aux_ctl_reg(dev_priv, port);
1435 }
1436
1437 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1438                                      enum port port, int index)
1439 {
1440         if (INTEL_INFO(dev_priv)->gen >= 9)
1441                 return skl_aux_data_reg(dev_priv, port, index);
1442         else if (HAS_PCH_SPLIT(dev_priv))
1443                 return ilk_aux_data_reg(dev_priv, port, index);
1444         else
1445                 return g4x_aux_data_reg(dev_priv, port, index);
1446 }
1447
1448 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1449 {
1450         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1451         enum port port = intel_aux_port(dev_priv,
1452                                         dp_to_dig_port(intel_dp)->base.port);
1453         int i;
1454
1455         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1456         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1457                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1458 }
1459
1460 static void
1461 intel_dp_aux_fini(struct intel_dp *intel_dp)
1462 {
1463         kfree(intel_dp->aux.name);
1464 }
1465
1466 static void
1467 intel_dp_aux_init(struct intel_dp *intel_dp)
1468 {
1469         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1470         enum port port = intel_dig_port->base.port;
1471
1472         intel_aux_reg_init(intel_dp);
1473         drm_dp_aux_init(&intel_dp->aux);
1474
1475         /* Failure to allocate our preferred name is not critical */
1476         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1477         intel_dp->aux.transfer = intel_dp_aux_transfer;
1478 }
1479
1480 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1481 {
1482         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1483
1484         return max_rate >= 540000;
1485 }
1486
1487 static void
1488 intel_dp_set_clock(struct intel_encoder *encoder,
1489                    struct intel_crtc_state *pipe_config)
1490 {
1491         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1492         const struct dp_link_dpll *divisor = NULL;
1493         int i, count = 0;
1494
1495         if (IS_G4X(dev_priv)) {
1496                 divisor = gen4_dpll;
1497                 count = ARRAY_SIZE(gen4_dpll);
1498         } else if (HAS_PCH_SPLIT(dev_priv)) {
1499                 divisor = pch_dpll;
1500                 count = ARRAY_SIZE(pch_dpll);
1501         } else if (IS_CHERRYVIEW(dev_priv)) {
1502                 divisor = chv_dpll;
1503                 count = ARRAY_SIZE(chv_dpll);
1504         } else if (IS_VALLEYVIEW(dev_priv)) {
1505                 divisor = vlv_dpll;
1506                 count = ARRAY_SIZE(vlv_dpll);
1507         }
1508
1509         if (divisor && count) {
1510                 for (i = 0; i < count; i++) {
1511                         if (pipe_config->port_clock == divisor[i].clock) {
1512                                 pipe_config->dpll = divisor[i].dpll;
1513                                 pipe_config->clock_set = true;
1514                                 break;
1515                         }
1516                 }
1517         }
1518 }
1519
1520 static void snprintf_int_array(char *str, size_t len,
1521                                const int *array, int nelem)
1522 {
1523         int i;
1524
1525         str[0] = '\0';
1526
1527         for (i = 0; i < nelem; i++) {
1528                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1529                 if (r >= len)
1530                         return;
1531                 str += r;
1532                 len -= r;
1533         }
1534 }
1535
1536 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1537 {
1538         char str[128]; /* FIXME: too big for stack? */
1539
1540         if ((drm_debug & DRM_UT_KMS) == 0)
1541                 return;
1542
1543         snprintf_int_array(str, sizeof(str),
1544                            intel_dp->source_rates, intel_dp->num_source_rates);
1545         DRM_DEBUG_KMS("source rates: %s\n", str);
1546
1547         snprintf_int_array(str, sizeof(str),
1548                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1549         DRM_DEBUG_KMS("sink rates: %s\n", str);
1550
1551         snprintf_int_array(str, sizeof(str),
1552                            intel_dp->common_rates, intel_dp->num_common_rates);
1553         DRM_DEBUG_KMS("common rates: %s\n", str);
1554 }
1555
1556 int
1557 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1558 {
1559         int len;
1560
1561         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1562         if (WARN_ON(len <= 0))
1563                 return 162000;
1564
1565         return intel_dp->common_rates[len - 1];
1566 }
1567
1568 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1569 {
1570         int i = intel_dp_rate_index(intel_dp->sink_rates,
1571                                     intel_dp->num_sink_rates, rate);
1572
1573         if (WARN_ON(i < 0))
1574                 i = 0;
1575
1576         return i;
1577 }
1578
1579 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1580                            uint8_t *link_bw, uint8_t *rate_select)
1581 {
1582         /* eDP 1.4 rate select method. */
1583         if (intel_dp->use_rate_select) {
1584                 *link_bw = 0;
1585                 *rate_select =
1586                         intel_dp_rate_select(intel_dp, port_clock);
1587         } else {
1588                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1589                 *rate_select = 0;
1590         }
1591 }
1592
1593 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1594                                 struct intel_crtc_state *pipe_config)
1595 {
1596         int bpp, bpc;
1597
1598         bpp = pipe_config->pipe_bpp;
1599         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1600
1601         if (bpc > 0)
1602                 bpp = min(bpp, 3*bpc);
1603
1604         /* For DP Compliance we override the computed bpp for the pipe */
1605         if (intel_dp->compliance.test_data.bpc != 0) {
1606                 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1607                 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1608                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1609                               pipe_config->pipe_bpp);
1610         }
1611         return bpp;
1612 }
1613
1614 static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
1615                                        struct drm_display_mode *m2)
1616 {
1617         bool bres = false;
1618
1619         if (m1 && m2)
1620                 bres = (m1->hdisplay == m2->hdisplay &&
1621                         m1->hsync_start == m2->hsync_start &&
1622                         m1->hsync_end == m2->hsync_end &&
1623                         m1->htotal == m2->htotal &&
1624                         m1->vdisplay == m2->vdisplay &&
1625                         m1->vsync_start == m2->vsync_start &&
1626                         m1->vsync_end == m2->vsync_end &&
1627                         m1->vtotal == m2->vtotal);
1628         return bres;
1629 }
1630
1631 bool
1632 intel_dp_compute_config(struct intel_encoder *encoder,
1633                         struct intel_crtc_state *pipe_config,
1634                         struct drm_connector_state *conn_state)
1635 {
1636         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1637         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1638         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1639         enum port port = encoder->port;
1640         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1641         struct intel_connector *intel_connector = intel_dp->attached_connector;
1642         struct intel_digital_connector_state *intel_conn_state =
1643                 to_intel_digital_connector_state(conn_state);
1644         int lane_count, clock;
1645         int min_lane_count = 1;
1646         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1647         /* Conveniently, the link BW constants become indices with a shift...*/
1648         int min_clock = 0;
1649         int max_clock;
1650         int bpp, mode_rate;
1651         int link_avail, link_clock;
1652         int common_len;
1653         uint8_t link_bw, rate_select;
1654         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1655                                            DP_DPCD_QUIRK_LIMITED_M_N);
1656
1657         common_len = intel_dp_common_len_rate_limit(intel_dp,
1658                                                     intel_dp->max_link_rate);
1659
1660         /* No common link rates between source and sink */
1661         WARN_ON(common_len <= 0);
1662
1663         max_clock = common_len - 1;
1664
1665         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1666                 pipe_config->has_pch_encoder = true;
1667
1668         pipe_config->has_drrs = false;
1669         if (IS_G4X(dev_priv) || port == PORT_A)
1670                 pipe_config->has_audio = false;
1671         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1672                 pipe_config->has_audio = intel_dp->has_audio;
1673         else
1674                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1675
1676         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1677                 struct drm_display_mode *panel_mode =
1678                         intel_connector->panel.alt_fixed_mode;
1679                 struct drm_display_mode *req_mode = &pipe_config->base.mode;
1680
1681                 if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
1682                         panel_mode = intel_connector->panel.fixed_mode;
1683
1684                 drm_mode_debug_printmodeline(panel_mode);
1685
1686                 intel_fixed_panel_mode(panel_mode, adjusted_mode);
1687
1688                 if (INTEL_GEN(dev_priv) >= 9) {
1689                         int ret;
1690                         ret = skl_update_scaler_crtc(pipe_config);
1691                         if (ret)
1692                                 return ret;
1693                 }
1694
1695                 if (HAS_GMCH_DISPLAY(dev_priv))
1696                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1697                                                  conn_state->scaling_mode);
1698                 else
1699                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1700                                                 conn_state->scaling_mode);
1701         }
1702
1703         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1704             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1705                 return false;
1706
1707         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1708                 return false;
1709
1710         /* Use values requested by Compliance Test Request */
1711         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1712                 int index;
1713
1714                 /* Validate the compliance test data since max values
1715                  * might have changed due to link train fallback.
1716                  */
1717                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1718                                                intel_dp->compliance.test_lane_count)) {
1719                         index = intel_dp_rate_index(intel_dp->common_rates,
1720                                                     intel_dp->num_common_rates,
1721                                                     intel_dp->compliance.test_link_rate);
1722                         if (index >= 0)
1723                                 min_clock = max_clock = index;
1724                         min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1725                 }
1726         }
1727         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1728                       "max bw %d pixel clock %iKHz\n",
1729                       max_lane_count, intel_dp->common_rates[max_clock],
1730                       adjusted_mode->crtc_clock);
1731
1732         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1733          * bpc in between. */
1734         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1735         if (intel_dp_is_edp(intel_dp)) {
1736
1737                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1738                 if (intel_connector->base.display_info.bpc == 0 &&
1739                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1740                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1741                                       dev_priv->vbt.edp.bpp);
1742                         bpp = dev_priv->vbt.edp.bpp;
1743                 }
1744
1745                 /*
1746                  * Use the maximum clock and number of lanes the eDP panel
1747                  * advertizes being capable of. The panels are generally
1748                  * designed to support only a single clock and lane
1749                  * configuration, and typically these values correspond to the
1750                  * native resolution of the panel.
1751                  */
1752                 min_lane_count = max_lane_count;
1753                 min_clock = max_clock;
1754         }
1755
1756         for (; bpp >= 6*3; bpp -= 2*3) {
1757                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1758                                                    bpp);
1759
1760                 for (clock = min_clock; clock <= max_clock; clock++) {
1761                         for (lane_count = min_lane_count;
1762                                 lane_count <= max_lane_count;
1763                                 lane_count <<= 1) {
1764
1765                                 link_clock = intel_dp->common_rates[clock];
1766                                 link_avail = intel_dp_max_data_rate(link_clock,
1767                                                                     lane_count);
1768
1769                                 if (mode_rate <= link_avail) {
1770                                         goto found;
1771                                 }
1772                         }
1773                 }
1774         }
1775
1776         return false;
1777
1778 found:
1779         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1780                 /*
1781                  * See:
1782                  * CEA-861-E - 5.1 Default Encoding Parameters
1783                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1784                  */
1785                 pipe_config->limited_color_range =
1786                         bpp != 18 &&
1787                         drm_default_rgb_quant_range(adjusted_mode) ==
1788                         HDMI_QUANTIZATION_RANGE_LIMITED;
1789         } else {
1790                 pipe_config->limited_color_range =
1791                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1792         }
1793
1794         pipe_config->lane_count = lane_count;
1795
1796         pipe_config->pipe_bpp = bpp;
1797         pipe_config->port_clock = intel_dp->common_rates[clock];
1798
1799         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1800                               &link_bw, &rate_select);
1801
1802         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1803                       link_bw, rate_select, pipe_config->lane_count,
1804                       pipe_config->port_clock, bpp);
1805         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1806                       mode_rate, link_avail);
1807
1808         intel_link_compute_m_n(bpp, lane_count,
1809                                adjusted_mode->crtc_clock,
1810                                pipe_config->port_clock,
1811                                &pipe_config->dp_m_n,
1812                                reduce_m_n);
1813
1814         if (intel_connector->panel.downclock_mode != NULL &&
1815                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1816                         pipe_config->has_drrs = true;
1817                         intel_link_compute_m_n(bpp, lane_count,
1818                                 intel_connector->panel.downclock_mode->clock,
1819                                 pipe_config->port_clock,
1820                                 &pipe_config->dp_m2_n2,
1821                                 reduce_m_n);
1822         }
1823
1824         /*
1825          * DPLL0 VCO may need to be adjusted to get the correct
1826          * clock for eDP. This will affect cdclk as well.
1827          */
1828         if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1829                 int vco;
1830
1831                 switch (pipe_config->port_clock / 2) {
1832                 case 108000:
1833                 case 216000:
1834                         vco = 8640000;
1835                         break;
1836                 default:
1837                         vco = 8100000;
1838                         break;
1839                 }
1840
1841                 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1842         }
1843
1844         if (!HAS_DDI(dev_priv))
1845                 intel_dp_set_clock(encoder, pipe_config);
1846
1847         intel_psr_compute_config(intel_dp, pipe_config);
1848
1849         return true;
1850 }
1851
1852 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1853                               int link_rate, uint8_t lane_count,
1854                               bool link_mst)
1855 {
1856         intel_dp->link_rate = link_rate;
1857         intel_dp->lane_count = lane_count;
1858         intel_dp->link_mst = link_mst;
1859 }
1860
1861 static void intel_dp_prepare(struct intel_encoder *encoder,
1862                              const struct intel_crtc_state *pipe_config)
1863 {
1864         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1865         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1866         enum port port = encoder->port;
1867         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1868         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1869
1870         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1871                                  pipe_config->lane_count,
1872                                  intel_crtc_has_type(pipe_config,
1873                                                      INTEL_OUTPUT_DP_MST));
1874
1875         /*
1876          * There are four kinds of DP registers:
1877          *
1878          *      IBX PCH
1879          *      SNB CPU
1880          *      IVB CPU
1881          *      CPT PCH
1882          *
1883          * IBX PCH and CPU are the same for almost everything,
1884          * except that the CPU DP PLL is configured in this
1885          * register
1886          *
1887          * CPT PCH is quite different, having many bits moved
1888          * to the TRANS_DP_CTL register instead. That
1889          * configuration happens (oddly) in ironlake_pch_enable
1890          */
1891
1892         /* Preserve the BIOS-computed detected bit. This is
1893          * supposed to be read-only.
1894          */
1895         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1896
1897         /* Handle DP bits in common between all three register formats */
1898         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1899         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1900
1901         /* Split out the IBX/CPU vs CPT settings */
1902
1903         if (IS_GEN7(dev_priv) && port == PORT_A) {
1904                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1905                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1906                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1907                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1908                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1909
1910                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1911                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1912
1913                 intel_dp->DP |= crtc->pipe << 29;
1914         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1915                 u32 trans_dp;
1916
1917                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1918
1919                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1920                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1921                         trans_dp |= TRANS_DP_ENH_FRAMING;
1922                 else
1923                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1924                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1925         } else {
1926                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1927                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1928
1929                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1930                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1931                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1932                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1933                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1934
1935                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1936                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1937
1938                 if (IS_CHERRYVIEW(dev_priv))
1939                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1940                 else if (crtc->pipe == PIPE_B)
1941                         intel_dp->DP |= DP_PIPEB_SELECT;
1942         }
1943 }
1944
1945 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1946 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1947
1948 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1949 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1950
1951 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1952 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1953
1954 static void intel_pps_verify_state(struct intel_dp *intel_dp);
1955
1956 static void wait_panel_status(struct intel_dp *intel_dp,
1957                                        u32 mask,
1958                                        u32 value)
1959 {
1960         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1961         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1962
1963         lockdep_assert_held(&dev_priv->pps_mutex);
1964
1965         intel_pps_verify_state(intel_dp);
1966
1967         pp_stat_reg = _pp_stat_reg(intel_dp);
1968         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1969
1970         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1971                         mask, value,
1972                         I915_READ(pp_stat_reg),
1973                         I915_READ(pp_ctrl_reg));
1974
1975         if (intel_wait_for_register(dev_priv,
1976                                     pp_stat_reg, mask, value,
1977                                     5000))
1978                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1979                                 I915_READ(pp_stat_reg),
1980                                 I915_READ(pp_ctrl_reg));
1981
1982         DRM_DEBUG_KMS("Wait complete\n");
1983 }
1984
1985 static void wait_panel_on(struct intel_dp *intel_dp)
1986 {
1987         DRM_DEBUG_KMS("Wait for panel power on\n");
1988         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1989 }
1990
1991 static void wait_panel_off(struct intel_dp *intel_dp)
1992 {
1993         DRM_DEBUG_KMS("Wait for panel power off time\n");
1994         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1995 }
1996
1997 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1998 {
1999         ktime_t panel_power_on_time;
2000         s64 panel_power_off_duration;
2001
2002         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2003
2004         /* take the difference of currrent time and panel power off time
2005          * and then make panel wait for t11_t12 if needed. */
2006         panel_power_on_time = ktime_get_boottime();
2007         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2008
2009         /* When we disable the VDD override bit last we have to do the manual
2010          * wait. */
2011         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2012                 wait_remaining_ms_from_jiffies(jiffies,
2013                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2014
2015         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2016 }
2017
2018 static void wait_backlight_on(struct intel_dp *intel_dp)
2019 {
2020         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2021                                        intel_dp->backlight_on_delay);
2022 }
2023
2024 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2025 {
2026         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2027                                        intel_dp->backlight_off_delay);
2028 }
2029
2030 /* Read the current pp_control value, unlocking the register if it
2031  * is locked
2032  */
2033
2034 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2035 {
2036         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2037         u32 control;
2038
2039         lockdep_assert_held(&dev_priv->pps_mutex);
2040
2041         control = I915_READ(_pp_ctrl_reg(intel_dp));
2042         if (WARN_ON(!HAS_DDI(dev_priv) &&
2043                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2044                 control &= ~PANEL_UNLOCK_MASK;
2045                 control |= PANEL_UNLOCK_REGS;
2046         }
2047         return control;
2048 }
2049
2050 /*
2051  * Must be paired with edp_panel_vdd_off().
2052  * Must hold pps_mutex around the whole on/off sequence.
2053  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2054  */
2055 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2056 {
2057         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2058         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2059         u32 pp;
2060         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2061         bool need_to_disable = !intel_dp->want_panel_vdd;
2062
2063         lockdep_assert_held(&dev_priv->pps_mutex);
2064
2065         if (!intel_dp_is_edp(intel_dp))
2066                 return false;
2067
2068         cancel_delayed_work(&intel_dp->panel_vdd_work);
2069         intel_dp->want_panel_vdd = true;
2070
2071         if (edp_have_panel_vdd(intel_dp))
2072                 return need_to_disable;
2073
2074         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2075
2076         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2077                       port_name(intel_dig_port->base.port));
2078
2079         if (!edp_have_panel_power(intel_dp))
2080                 wait_panel_power_cycle(intel_dp);
2081
2082         pp = ironlake_get_pp_control(intel_dp);
2083         pp |= EDP_FORCE_VDD;
2084
2085         pp_stat_reg = _pp_stat_reg(intel_dp);
2086         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2087
2088         I915_WRITE(pp_ctrl_reg, pp);
2089         POSTING_READ(pp_ctrl_reg);
2090         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2091                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2092         /*
2093          * If the panel wasn't on, delay before accessing aux channel
2094          */
2095         if (!edp_have_panel_power(intel_dp)) {
2096                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2097                               port_name(intel_dig_port->base.port));
2098                 msleep(intel_dp->panel_power_up_delay);
2099         }
2100
2101         return need_to_disable;
2102 }
2103
2104 /*
2105  * Must be paired with intel_edp_panel_vdd_off() or
2106  * intel_edp_panel_off().
2107  * Nested calls to these functions are not allowed since
2108  * we drop the lock. Caller must use some higher level
2109  * locking to prevent nested calls from other threads.
2110  */
2111 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2112 {
2113         bool vdd;
2114
2115         if (!intel_dp_is_edp(intel_dp))
2116                 return;
2117
2118         pps_lock(intel_dp);
2119         vdd = edp_panel_vdd_on(intel_dp);
2120         pps_unlock(intel_dp);
2121
2122         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2123              port_name(dp_to_dig_port(intel_dp)->base.port));
2124 }
2125
2126 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2127 {
2128         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2129         struct intel_digital_port *intel_dig_port =
2130                 dp_to_dig_port(intel_dp);
2131         u32 pp;
2132         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2133
2134         lockdep_assert_held(&dev_priv->pps_mutex);
2135
2136         WARN_ON(intel_dp->want_panel_vdd);
2137
2138         if (!edp_have_panel_vdd(intel_dp))
2139                 return;
2140
2141         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2142                       port_name(intel_dig_port->base.port));
2143
2144         pp = ironlake_get_pp_control(intel_dp);
2145         pp &= ~EDP_FORCE_VDD;
2146
2147         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2148         pp_stat_reg = _pp_stat_reg(intel_dp);
2149
2150         I915_WRITE(pp_ctrl_reg, pp);
2151         POSTING_READ(pp_ctrl_reg);
2152
2153         /* Make sure sequencer is idle before allowing subsequent activity */
2154         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2155         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2156
2157         if ((pp & PANEL_POWER_ON) == 0)
2158                 intel_dp->panel_power_off_time = ktime_get_boottime();
2159
2160         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2161 }
2162
2163 static void edp_panel_vdd_work(struct work_struct *__work)
2164 {
2165         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2166                                                  struct intel_dp, panel_vdd_work);
2167
2168         pps_lock(intel_dp);
2169         if (!intel_dp->want_panel_vdd)
2170                 edp_panel_vdd_off_sync(intel_dp);
2171         pps_unlock(intel_dp);
2172 }
2173
2174 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2175 {
2176         unsigned long delay;
2177
2178         /*
2179          * Queue the timer to fire a long time from now (relative to the power
2180          * down delay) to keep the panel power up across a sequence of
2181          * operations.
2182          */
2183         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2184         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2185 }
2186
2187 /*
2188  * Must be paired with edp_panel_vdd_on().
2189  * Must hold pps_mutex around the whole on/off sequence.
2190  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2191  */
2192 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2193 {
2194         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2195
2196         lockdep_assert_held(&dev_priv->pps_mutex);
2197
2198         if (!intel_dp_is_edp(intel_dp))
2199                 return;
2200
2201         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2202              port_name(dp_to_dig_port(intel_dp)->base.port));
2203
2204         intel_dp->want_panel_vdd = false;
2205
2206         if (sync)
2207                 edp_panel_vdd_off_sync(intel_dp);
2208         else
2209                 edp_panel_vdd_schedule_off(intel_dp);
2210 }
2211
2212 static void edp_panel_on(struct intel_dp *intel_dp)
2213 {
2214         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2215         u32 pp;
2216         i915_reg_t pp_ctrl_reg;
2217
2218         lockdep_assert_held(&dev_priv->pps_mutex);
2219
2220         if (!intel_dp_is_edp(intel_dp))
2221                 return;
2222
2223         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2224                       port_name(dp_to_dig_port(intel_dp)->base.port));
2225
2226         if (WARN(edp_have_panel_power(intel_dp),
2227                  "eDP port %c panel power already on\n",
2228                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2229                 return;
2230
2231         wait_panel_power_cycle(intel_dp);
2232
2233         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2234         pp = ironlake_get_pp_control(intel_dp);
2235         if (IS_GEN5(dev_priv)) {
2236                 /* ILK workaround: disable reset around power sequence */
2237                 pp &= ~PANEL_POWER_RESET;
2238                 I915_WRITE(pp_ctrl_reg, pp);
2239                 POSTING_READ(pp_ctrl_reg);
2240         }
2241
2242         pp |= PANEL_POWER_ON;
2243         if (!IS_GEN5(dev_priv))
2244                 pp |= PANEL_POWER_RESET;
2245
2246         I915_WRITE(pp_ctrl_reg, pp);
2247         POSTING_READ(pp_ctrl_reg);
2248
2249         wait_panel_on(intel_dp);
2250         intel_dp->last_power_on = jiffies;
2251
2252         if (IS_GEN5(dev_priv)) {
2253                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2254                 I915_WRITE(pp_ctrl_reg, pp);
2255                 POSTING_READ(pp_ctrl_reg);
2256         }
2257 }
2258
2259 void intel_edp_panel_on(struct intel_dp *intel_dp)
2260 {
2261         if (!intel_dp_is_edp(intel_dp))
2262                 return;
2263
2264         pps_lock(intel_dp);
2265         edp_panel_on(intel_dp);
2266         pps_unlock(intel_dp);
2267 }
2268
2269
2270 static void edp_panel_off(struct intel_dp *intel_dp)
2271 {
2272         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2273         u32 pp;
2274         i915_reg_t pp_ctrl_reg;
2275
2276         lockdep_assert_held(&dev_priv->pps_mutex);
2277
2278         if (!intel_dp_is_edp(intel_dp))
2279                 return;
2280
2281         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2282                       port_name(dp_to_dig_port(intel_dp)->base.port));
2283
2284         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2285              port_name(dp_to_dig_port(intel_dp)->base.port));
2286
2287         pp = ironlake_get_pp_control(intel_dp);
2288         /* We need to switch off panel power _and_ force vdd, for otherwise some
2289          * panels get very unhappy and cease to work. */
2290         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2291                 EDP_BLC_ENABLE);
2292
2293         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2294
2295         intel_dp->want_panel_vdd = false;
2296
2297         I915_WRITE(pp_ctrl_reg, pp);
2298         POSTING_READ(pp_ctrl_reg);
2299
2300         wait_panel_off(intel_dp);
2301         intel_dp->panel_power_off_time = ktime_get_boottime();
2302
2303         /* We got a reference when we enabled the VDD. */
2304         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2305 }
2306
2307 void intel_edp_panel_off(struct intel_dp *intel_dp)
2308 {
2309         if (!intel_dp_is_edp(intel_dp))
2310                 return;
2311
2312         pps_lock(intel_dp);
2313         edp_panel_off(intel_dp);
2314         pps_unlock(intel_dp);
2315 }
2316
2317 /* Enable backlight in the panel power control. */
2318 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2319 {
2320         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2321         u32 pp;
2322         i915_reg_t pp_ctrl_reg;
2323
2324         /*
2325          * If we enable the backlight right away following a panel power
2326          * on, we may see slight flicker as the panel syncs with the eDP
2327          * link.  So delay a bit to make sure the image is solid before
2328          * allowing it to appear.
2329          */
2330         wait_backlight_on(intel_dp);
2331
2332         pps_lock(intel_dp);
2333
2334         pp = ironlake_get_pp_control(intel_dp);
2335         pp |= EDP_BLC_ENABLE;
2336
2337         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2338
2339         I915_WRITE(pp_ctrl_reg, pp);
2340         POSTING_READ(pp_ctrl_reg);
2341
2342         pps_unlock(intel_dp);
2343 }
2344
2345 /* Enable backlight PWM and backlight PP control. */
2346 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2347                             const struct drm_connector_state *conn_state)
2348 {
2349         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2350
2351         if (!intel_dp_is_edp(intel_dp))
2352                 return;
2353
2354         DRM_DEBUG_KMS("\n");
2355
2356         intel_panel_enable_backlight(crtc_state, conn_state);
2357         _intel_edp_backlight_on(intel_dp);
2358 }
2359
2360 /* Disable backlight in the panel power control. */
2361 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2362 {
2363         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2364         u32 pp;
2365         i915_reg_t pp_ctrl_reg;
2366
2367         if (!intel_dp_is_edp(intel_dp))
2368                 return;
2369
2370         pps_lock(intel_dp);
2371
2372         pp = ironlake_get_pp_control(intel_dp);
2373         pp &= ~EDP_BLC_ENABLE;
2374
2375         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2376
2377         I915_WRITE(pp_ctrl_reg, pp);
2378         POSTING_READ(pp_ctrl_reg);
2379
2380         pps_unlock(intel_dp);
2381
2382         intel_dp->last_backlight_off = jiffies;
2383         edp_wait_backlight_off(intel_dp);
2384 }
2385
2386 /* Disable backlight PP control and backlight PWM. */
2387 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2388 {
2389         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2390
2391         if (!intel_dp_is_edp(intel_dp))
2392                 return;
2393
2394         DRM_DEBUG_KMS("\n");
2395
2396         _intel_edp_backlight_off(intel_dp);
2397         intel_panel_disable_backlight(old_conn_state);
2398 }
2399
2400 /*
2401  * Hook for controlling the panel power control backlight through the bl_power
2402  * sysfs attribute. Take care to handle multiple calls.
2403  */
2404 static void intel_edp_backlight_power(struct intel_connector *connector,
2405                                       bool enable)
2406 {
2407         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2408         bool is_enabled;
2409
2410         pps_lock(intel_dp);
2411         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2412         pps_unlock(intel_dp);
2413
2414         if (is_enabled == enable)
2415                 return;
2416
2417         DRM_DEBUG_KMS("panel power control backlight %s\n",
2418                       enable ? "enable" : "disable");
2419
2420         if (enable)
2421                 _intel_edp_backlight_on(intel_dp);
2422         else
2423                 _intel_edp_backlight_off(intel_dp);
2424 }
2425
2426 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2427 {
2428         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2429         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2430         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2431
2432         I915_STATE_WARN(cur_state != state,
2433                         "DP port %c state assertion failure (expected %s, current %s)\n",
2434                         port_name(dig_port->base.port),
2435                         onoff(state), onoff(cur_state));
2436 }
2437 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2438
2439 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2440 {
2441         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2442
2443         I915_STATE_WARN(cur_state != state,
2444                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2445                         onoff(state), onoff(cur_state));
2446 }
2447 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2448 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2449
2450 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2451                                 const struct intel_crtc_state *pipe_config)
2452 {
2453         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2454         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2455
2456         assert_pipe_disabled(dev_priv, crtc->pipe);
2457         assert_dp_port_disabled(intel_dp);
2458         assert_edp_pll_disabled(dev_priv);
2459
2460         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2461                       pipe_config->port_clock);
2462
2463         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2464
2465         if (pipe_config->port_clock == 162000)
2466                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2467         else
2468                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2469
2470         I915_WRITE(DP_A, intel_dp->DP);
2471         POSTING_READ(DP_A);
2472         udelay(500);
2473
2474         /*
2475          * [DevILK] Work around required when enabling DP PLL
2476          * while a pipe is enabled going to FDI:
2477          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2478          * 2. Program DP PLL enable
2479          */
2480         if (IS_GEN5(dev_priv))
2481                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2482
2483         intel_dp->DP |= DP_PLL_ENABLE;
2484
2485         I915_WRITE(DP_A, intel_dp->DP);
2486         POSTING_READ(DP_A);
2487         udelay(200);
2488 }
2489
2490 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2491                                  const struct intel_crtc_state *old_crtc_state)
2492 {
2493         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2494         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2495
2496         assert_pipe_disabled(dev_priv, crtc->pipe);
2497         assert_dp_port_disabled(intel_dp);
2498         assert_edp_pll_enabled(dev_priv);
2499
2500         DRM_DEBUG_KMS("disabling eDP PLL\n");
2501
2502         intel_dp->DP &= ~DP_PLL_ENABLE;
2503
2504         I915_WRITE(DP_A, intel_dp->DP);
2505         POSTING_READ(DP_A);
2506         udelay(200);
2507 }
2508
2509 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2510 {
2511         /*
2512          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2513          * be capable of signalling downstream hpd with a long pulse.
2514          * Whether or not that means D3 is safe to use is not clear,
2515          * but let's assume so until proven otherwise.
2516          *
2517          * FIXME should really check all downstream ports...
2518          */
2519         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2520                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2521                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2522 }
2523
2524 /* If the sink supports it, try to set the power state appropriately */
2525 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2526 {
2527         int ret, i;
2528
2529         /* Should have a valid DPCD by this point */
2530         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2531                 return;
2532
2533         if (mode != DRM_MODE_DPMS_ON) {
2534                 if (downstream_hpd_needs_d0(intel_dp))
2535                         return;
2536
2537                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2538                                          DP_SET_POWER_D3);
2539         } else {
2540                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2541
2542                 /*
2543                  * When turning on, we need to retry for 1ms to give the sink
2544                  * time to wake up.
2545                  */
2546                 for (i = 0; i < 3; i++) {
2547                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2548                                                  DP_SET_POWER_D0);
2549                         if (ret == 1)
2550                                 break;
2551                         msleep(1);
2552                 }
2553
2554                 if (ret == 1 && lspcon->active)
2555                         lspcon_wait_pcon_mode(lspcon);
2556         }
2557
2558         if (ret != 1)
2559                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2560                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2561 }
2562
2563 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2564                                   enum pipe *pipe)
2565 {
2566         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2567         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2568         enum port port = encoder->port;
2569         u32 tmp;
2570         bool ret;
2571
2572         if (!intel_display_power_get_if_enabled(dev_priv,
2573                                                 encoder->power_domain))
2574                 return false;
2575
2576         ret = false;
2577
2578         tmp = I915_READ(intel_dp->output_reg);
2579
2580         if (!(tmp & DP_PORT_EN))
2581                 goto out;
2582
2583         if (IS_GEN7(dev_priv) && port == PORT_A) {
2584                 *pipe = PORT_TO_PIPE_CPT(tmp);
2585         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2586                 enum pipe p;
2587
2588                 for_each_pipe(dev_priv, p) {
2589                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2590                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2591                                 *pipe = p;
2592                                 ret = true;
2593
2594                                 goto out;
2595                         }
2596                 }
2597
2598                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2599                               i915_mmio_reg_offset(intel_dp->output_reg));
2600         } else if (IS_CHERRYVIEW(dev_priv)) {
2601                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2602         } else {
2603                 *pipe = PORT_TO_PIPE(tmp);
2604         }
2605
2606         ret = true;
2607
2608 out:
2609         intel_display_power_put(dev_priv, encoder->power_domain);
2610
2611         return ret;
2612 }
2613
2614 static void intel_dp_get_config(struct intel_encoder *encoder,
2615                                 struct intel_crtc_state *pipe_config)
2616 {
2617         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2618         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2619         u32 tmp, flags = 0;
2620         enum port port = encoder->port;
2621         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2622
2623         if (encoder->type == INTEL_OUTPUT_EDP)
2624                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2625         else
2626                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2627
2628         tmp = I915_READ(intel_dp->output_reg);
2629
2630         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2631
2632         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2633                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2634
2635                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2636                         flags |= DRM_MODE_FLAG_PHSYNC;
2637                 else
2638                         flags |= DRM_MODE_FLAG_NHSYNC;
2639
2640                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2641                         flags |= DRM_MODE_FLAG_PVSYNC;
2642                 else
2643                         flags |= DRM_MODE_FLAG_NVSYNC;
2644         } else {
2645                 if (tmp & DP_SYNC_HS_HIGH)
2646                         flags |= DRM_MODE_FLAG_PHSYNC;
2647                 else
2648                         flags |= DRM_MODE_FLAG_NHSYNC;
2649
2650                 if (tmp & DP_SYNC_VS_HIGH)
2651                         flags |= DRM_MODE_FLAG_PVSYNC;
2652                 else
2653                         flags |= DRM_MODE_FLAG_NVSYNC;
2654         }
2655
2656         pipe_config->base.adjusted_mode.flags |= flags;
2657
2658         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2659                 pipe_config->limited_color_range = true;
2660
2661         pipe_config->lane_count =
2662                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2663
2664         intel_dp_get_m_n(crtc, pipe_config);
2665
2666         if (port == PORT_A) {
2667                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2668                         pipe_config->port_clock = 162000;
2669                 else
2670                         pipe_config->port_clock = 270000;
2671         }
2672
2673         pipe_config->base.adjusted_mode.crtc_clock =
2674                 intel_dotclock_calculate(pipe_config->port_clock,
2675                                          &pipe_config->dp_m_n);
2676
2677         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2678             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2679                 /*
2680                  * This is a big fat ugly hack.
2681                  *
2682                  * Some machines in UEFI boot mode provide us a VBT that has 18
2683                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2684                  * unknown we fail to light up. Yet the same BIOS boots up with
2685                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2686                  * max, not what it tells us to use.
2687                  *
2688                  * Note: This will still be broken if the eDP panel is not lit
2689                  * up by the BIOS, and thus we can't get the mode at module
2690                  * load.
2691                  */
2692                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2693                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2694                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2695         }
2696 }
2697
2698 static void intel_disable_dp(struct intel_encoder *encoder,
2699                              const struct intel_crtc_state *old_crtc_state,
2700                              const struct drm_connector_state *old_conn_state)
2701 {
2702         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2703
2704         if (old_crtc_state->has_audio)
2705                 intel_audio_codec_disable(encoder,
2706                                           old_crtc_state, old_conn_state);
2707
2708         /* Make sure the panel is off before trying to change the mode. But also
2709          * ensure that we have vdd while we switch off the panel. */
2710         intel_edp_panel_vdd_on(intel_dp);
2711         intel_edp_backlight_off(old_conn_state);
2712         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2713         intel_edp_panel_off(intel_dp);
2714 }
2715
2716 static void g4x_disable_dp(struct intel_encoder *encoder,
2717                            const struct intel_crtc_state *old_crtc_state,
2718                            const struct drm_connector_state *old_conn_state)
2719 {
2720         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2721
2722         /* disable the port before the pipe on g4x */
2723         intel_dp_link_down(encoder, old_crtc_state);
2724 }
2725
2726 static void ilk_disable_dp(struct intel_encoder *encoder,
2727                            const struct intel_crtc_state *old_crtc_state,
2728                            const struct drm_connector_state *old_conn_state)
2729 {
2730         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2731 }
2732
2733 static void vlv_disable_dp(struct intel_encoder *encoder,
2734                            const struct intel_crtc_state *old_crtc_state,
2735                            const struct drm_connector_state *old_conn_state)
2736 {
2737         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2738
2739         intel_psr_disable(intel_dp, old_crtc_state);
2740
2741         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2742 }
2743
2744 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2745                                 const struct intel_crtc_state *old_crtc_state,
2746                                 const struct drm_connector_state *old_conn_state)
2747 {
2748         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2749         enum port port = encoder->port;
2750
2751         intel_dp_link_down(encoder, old_crtc_state);
2752
2753         /* Only ilk+ has port A */
2754         if (port == PORT_A)
2755                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
2756 }
2757
2758 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2759                                 const struct intel_crtc_state *old_crtc_state,
2760                                 const struct drm_connector_state *old_conn_state)
2761 {
2762         intel_dp_link_down(encoder, old_crtc_state);
2763 }
2764
2765 static void chv_post_disable_dp(struct intel_encoder *encoder,
2766                                 const struct intel_crtc_state *old_crtc_state,
2767                                 const struct drm_connector_state *old_conn_state)
2768 {
2769         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2770
2771         intel_dp_link_down(encoder, old_crtc_state);
2772
2773         mutex_lock(&dev_priv->sb_lock);
2774
2775         /* Assert data lane reset */
2776         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2777
2778         mutex_unlock(&dev_priv->sb_lock);
2779 }
2780
2781 static void
2782 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2783                          uint32_t *DP,
2784                          uint8_t dp_train_pat)
2785 {
2786         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2787         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2788         enum port port = intel_dig_port->base.port;
2789
2790         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2791                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2792                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2793
2794         if (HAS_DDI(dev_priv)) {
2795                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2796
2797                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2798                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2799                 else
2800                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2801
2802                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2803                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2804                 case DP_TRAINING_PATTERN_DISABLE:
2805                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2806
2807                         break;
2808                 case DP_TRAINING_PATTERN_1:
2809                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2810                         break;
2811                 case DP_TRAINING_PATTERN_2:
2812                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2813                         break;
2814                 case DP_TRAINING_PATTERN_3:
2815                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2816                         break;
2817                 }
2818                 I915_WRITE(DP_TP_CTL(port), temp);
2819
2820         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2821                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2822                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2823
2824                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2825                 case DP_TRAINING_PATTERN_DISABLE:
2826                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2827                         break;
2828                 case DP_TRAINING_PATTERN_1:
2829                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2830                         break;
2831                 case DP_TRAINING_PATTERN_2:
2832                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2833                         break;
2834                 case DP_TRAINING_PATTERN_3:
2835                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2836                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2837                         break;
2838                 }
2839
2840         } else {
2841                 if (IS_CHERRYVIEW(dev_priv))
2842                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2843                 else
2844                         *DP &= ~DP_LINK_TRAIN_MASK;
2845
2846                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2847                 case DP_TRAINING_PATTERN_DISABLE:
2848                         *DP |= DP_LINK_TRAIN_OFF;
2849                         break;
2850                 case DP_TRAINING_PATTERN_1:
2851                         *DP |= DP_LINK_TRAIN_PAT_1;
2852                         break;
2853                 case DP_TRAINING_PATTERN_2:
2854                         *DP |= DP_LINK_TRAIN_PAT_2;
2855                         break;
2856                 case DP_TRAINING_PATTERN_3:
2857                         if (IS_CHERRYVIEW(dev_priv)) {
2858                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2859                         } else {
2860                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2861                                 *DP |= DP_LINK_TRAIN_PAT_2;
2862                         }
2863                         break;
2864                 }
2865         }
2866 }
2867
2868 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2869                                  const struct intel_crtc_state *old_crtc_state)
2870 {
2871         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2872
2873         /* enable with pattern 1 (as per spec) */
2874
2875         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2876
2877         /*
2878          * Magic for VLV/CHV. We _must_ first set up the register
2879          * without actually enabling the port, and then do another
2880          * write to enable the port. Otherwise link training will
2881          * fail when the power sequencer is freshly used for this port.
2882          */
2883         intel_dp->DP |= DP_PORT_EN;
2884         if (old_crtc_state->has_audio)
2885                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2886
2887         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2888         POSTING_READ(intel_dp->output_reg);
2889 }
2890
2891 static void intel_enable_dp(struct intel_encoder *encoder,
2892                             const struct intel_crtc_state *pipe_config,
2893                             const struct drm_connector_state *conn_state)
2894 {
2895         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2896         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2897         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2898         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2899         enum pipe pipe = crtc->pipe;
2900
2901         if (WARN_ON(dp_reg & DP_PORT_EN))
2902                 return;
2903
2904         pps_lock(intel_dp);
2905
2906         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2907                 vlv_init_panel_power_sequencer(encoder, pipe_config);
2908
2909         intel_dp_enable_port(intel_dp, pipe_config);
2910
2911         edp_panel_vdd_on(intel_dp);
2912         edp_panel_on(intel_dp);
2913         edp_panel_vdd_off(intel_dp, true);
2914
2915         pps_unlock(intel_dp);
2916
2917         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2918                 unsigned int lane_mask = 0x0;
2919
2920                 if (IS_CHERRYVIEW(dev_priv))
2921                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2922
2923                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2924                                     lane_mask);
2925         }
2926
2927         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2928         intel_dp_start_link_train(intel_dp);
2929         intel_dp_stop_link_train(intel_dp);
2930
2931         if (pipe_config->has_audio) {
2932                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2933                                  pipe_name(pipe));
2934                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2935         }
2936 }
2937
2938 static void g4x_enable_dp(struct intel_encoder *encoder,
2939                           const struct intel_crtc_state *pipe_config,
2940                           const struct drm_connector_state *conn_state)
2941 {
2942         intel_enable_dp(encoder, pipe_config, conn_state);
2943         intel_edp_backlight_on(pipe_config, conn_state);
2944 }
2945
2946 static void vlv_enable_dp(struct intel_encoder *encoder,
2947                           const struct intel_crtc_state *pipe_config,
2948                           const struct drm_connector_state *conn_state)
2949 {
2950         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2951
2952         intel_edp_backlight_on(pipe_config, conn_state);
2953         intel_psr_enable(intel_dp, pipe_config);
2954 }
2955
2956 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2957                               const struct intel_crtc_state *pipe_config,
2958                               const struct drm_connector_state *conn_state)
2959 {
2960         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2961         enum port port = encoder->port;
2962
2963         intel_dp_prepare(encoder, pipe_config);
2964
2965         /* Only ilk+ has port A */
2966         if (port == PORT_A)
2967                 ironlake_edp_pll_on(intel_dp, pipe_config);
2968 }
2969
2970 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2971 {
2972         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2973         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2974         enum pipe pipe = intel_dp->pps_pipe;
2975         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2976
2977         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2978
2979         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2980                 return;
2981
2982         edp_panel_vdd_off_sync(intel_dp);
2983
2984         /*
2985          * VLV seems to get confused when multiple power seqeuencers
2986          * have the same port selected (even if only one has power/vdd
2987          * enabled). The failure manifests as vlv_wait_port_ready() failing
2988          * CHV on the other hand doesn't seem to mind having the same port
2989          * selected in multiple power seqeuencers, but let's clear the
2990          * port select always when logically disconnecting a power sequencer
2991          * from a port.
2992          */
2993         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2994                       pipe_name(pipe), port_name(intel_dig_port->base.port));
2995         I915_WRITE(pp_on_reg, 0);
2996         POSTING_READ(pp_on_reg);
2997
2998         intel_dp->pps_pipe = INVALID_PIPE;
2999 }
3000
3001 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3002                                       enum pipe pipe)
3003 {
3004         struct intel_encoder *encoder;
3005
3006         lockdep_assert_held(&dev_priv->pps_mutex);
3007
3008         for_each_intel_encoder(&dev_priv->drm, encoder) {
3009                 struct intel_dp *intel_dp;
3010                 enum port port;
3011
3012                 if (encoder->type != INTEL_OUTPUT_DP &&
3013                     encoder->type != INTEL_OUTPUT_EDP)
3014                         continue;
3015
3016                 intel_dp = enc_to_intel_dp(&encoder->base);
3017                 port = dp_to_dig_port(intel_dp)->base.port;
3018
3019                 WARN(intel_dp->active_pipe == pipe,
3020                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3021                      pipe_name(pipe), port_name(port));
3022
3023                 if (intel_dp->pps_pipe != pipe)
3024                         continue;
3025
3026                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3027                               pipe_name(pipe), port_name(port));
3028
3029                 /* make sure vdd is off before we steal it */
3030                 vlv_detach_power_sequencer(intel_dp);
3031         }
3032 }
3033
3034 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3035                                            const struct intel_crtc_state *crtc_state)
3036 {
3037         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3038         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3039         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3040
3041         lockdep_assert_held(&dev_priv->pps_mutex);
3042
3043         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3044
3045         if (intel_dp->pps_pipe != INVALID_PIPE &&
3046             intel_dp->pps_pipe != crtc->pipe) {
3047                 /*
3048                  * If another power sequencer was being used on this
3049                  * port previously make sure to turn off vdd there while
3050                  * we still have control of it.
3051                  */
3052                 vlv_detach_power_sequencer(intel_dp);
3053         }
3054
3055         /*
3056          * We may be stealing the power
3057          * sequencer from another port.
3058          */
3059         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3060
3061         intel_dp->active_pipe = crtc->pipe;
3062
3063         if (!intel_dp_is_edp(intel_dp))
3064                 return;
3065
3066         /* now it's all ours */
3067         intel_dp->pps_pipe = crtc->pipe;
3068
3069         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3070                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3071
3072         /* init power sequencer on this pipe and port */
3073         intel_dp_init_panel_power_sequencer(intel_dp);
3074         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3075 }
3076
3077 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3078                               const struct intel_crtc_state *pipe_config,
3079                               const struct drm_connector_state *conn_state)
3080 {
3081         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3082
3083         intel_enable_dp(encoder, pipe_config, conn_state);
3084 }
3085
3086 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3087                                   const struct intel_crtc_state *pipe_config,
3088                                   const struct drm_connector_state *conn_state)
3089 {
3090         intel_dp_prepare(encoder, pipe_config);
3091
3092         vlv_phy_pre_pll_enable(encoder, pipe_config);
3093 }
3094
3095 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3096                               const struct intel_crtc_state *pipe_config,
3097                               const struct drm_connector_state *conn_state)
3098 {
3099         chv_phy_pre_encoder_enable(encoder, pipe_config);
3100
3101         intel_enable_dp(encoder, pipe_config, conn_state);
3102
3103         /* Second common lane will stay alive on its own now */
3104         chv_phy_release_cl2_override(encoder);
3105 }
3106
3107 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3108                                   const struct intel_crtc_state *pipe_config,
3109                                   const struct drm_connector_state *conn_state)
3110 {
3111         intel_dp_prepare(encoder, pipe_config);
3112
3113         chv_phy_pre_pll_enable(encoder, pipe_config);
3114 }
3115
3116 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3117                                     const struct intel_crtc_state *old_crtc_state,
3118                                     const struct drm_connector_state *old_conn_state)
3119 {
3120         chv_phy_post_pll_disable(encoder, old_crtc_state);
3121 }
3122
3123 /*
3124  * Fetch AUX CH registers 0x202 - 0x207 which contain
3125  * link status information
3126  */
3127 bool
3128 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3129 {
3130         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3131                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3132 }
3133
3134 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3135 {
3136         uint8_t psr_caps = 0;
3137
3138         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
3139                 return false;
3140         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3141 }
3142
3143 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3144 {
3145         uint8_t dprx = 0;
3146
3147         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3148                               &dprx) != 1)
3149                 return false;
3150         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3151 }
3152
3153 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3154 {
3155         uint8_t alpm_caps = 0;
3156
3157         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
3158                               &alpm_caps) != 1)
3159                 return false;
3160         return alpm_caps & DP_ALPM_CAP;
3161 }
3162
3163 /* These are source-specific values. */
3164 uint8_t
3165 intel_dp_voltage_max(struct intel_dp *intel_dp)
3166 {
3167         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3168         enum port port = dp_to_dig_port(intel_dp)->base.port;
3169
3170         if (INTEL_GEN(dev_priv) >= 9) {
3171                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3172                 return intel_ddi_dp_voltage_max(encoder);
3173         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3174                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3175         else if (IS_GEN7(dev_priv) && port == PORT_A)
3176                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3177         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3178                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3179         else
3180                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3181 }
3182
3183 uint8_t
3184 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3185 {
3186         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3187         enum port port = dp_to_dig_port(intel_dp)->base.port;
3188
3189         if (INTEL_GEN(dev_priv) >= 9) {
3190                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3191                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3192                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3193                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3194                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3195                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3196                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3197                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3198                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3199                 default:
3200                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3201                 }
3202         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3203                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3204                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3205                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3206                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3207                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3208                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3209                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3210                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3211                 default:
3212                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3213                 }
3214         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3215                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3216                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3217                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3218                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3219                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3220                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3221                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3222                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3223                 default:
3224                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3225                 }
3226         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3227                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3228                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3229                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3230                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3231                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3232                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3233                 default:
3234                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3235                 }
3236         } else {
3237                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3238                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3239                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3240                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3241                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3242                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3243                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3244                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3245                 default:
3246                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3247                 }
3248         }
3249 }
3250
3251 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3252 {
3253         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3254         unsigned long demph_reg_value, preemph_reg_value,
3255                 uniqtranscale_reg_value;
3256         uint8_t train_set = intel_dp->train_set[0];
3257
3258         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3259         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3260                 preemph_reg_value = 0x0004000;
3261                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3262                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3263                         demph_reg_value = 0x2B405555;
3264                         uniqtranscale_reg_value = 0x552AB83A;
3265                         break;
3266                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3267                         demph_reg_value = 0x2B404040;
3268                         uniqtranscale_reg_value = 0x5548B83A;
3269                         break;
3270                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3271                         demph_reg_value = 0x2B245555;
3272                         uniqtranscale_reg_value = 0x5560B83A;
3273                         break;
3274                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3275                         demph_reg_value = 0x2B405555;
3276                         uniqtranscale_reg_value = 0x5598DA3A;
3277                         break;
3278                 default:
3279                         return 0;
3280                 }
3281                 break;
3282         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3283                 preemph_reg_value = 0x0002000;
3284                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3285                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3286                         demph_reg_value = 0x2B404040;
3287                         uniqtranscale_reg_value = 0x5552B83A;
3288                         break;
3289                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3290                         demph_reg_value = 0x2B404848;
3291                         uniqtranscale_reg_value = 0x5580B83A;
3292                         break;
3293                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3294                         demph_reg_value = 0x2B404040;
3295                         uniqtranscale_reg_value = 0x55ADDA3A;
3296                         break;
3297                 default:
3298                         return 0;
3299                 }
3300                 break;
3301         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3302                 preemph_reg_value = 0x0000000;
3303                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3304                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3305                         demph_reg_value = 0x2B305555;
3306                         uniqtranscale_reg_value = 0x5570B83A;
3307                         break;
3308                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3309                         demph_reg_value = 0x2B2B4040;
3310                         uniqtranscale_reg_value = 0x55ADDA3A;
3311                         break;
3312                 default:
3313                         return 0;
3314                 }
3315                 break;
3316         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3317                 preemph_reg_value = 0x0006000;
3318                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3319                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3320                         demph_reg_value = 0x1B405555;
3321                         uniqtranscale_reg_value = 0x55ADDA3A;
3322                         break;
3323                 default:
3324                         return 0;
3325                 }
3326                 break;
3327         default:
3328                 return 0;
3329         }
3330
3331         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3332                                  uniqtranscale_reg_value, 0);
3333
3334         return 0;
3335 }
3336
3337 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3338 {
3339         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3340         u32 deemph_reg_value, margin_reg_value;
3341         bool uniq_trans_scale = false;
3342         uint8_t train_set = intel_dp->train_set[0];
3343
3344         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3345         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3346                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3347                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3348                         deemph_reg_value = 128;
3349                         margin_reg_value = 52;
3350                         break;
3351                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3352                         deemph_reg_value = 128;
3353                         margin_reg_value = 77;
3354                         break;
3355                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3356                         deemph_reg_value = 128;
3357                         margin_reg_value = 102;
3358                         break;
3359                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3360                         deemph_reg_value = 128;
3361                         margin_reg_value = 154;
3362                         uniq_trans_scale = true;
3363                         break;
3364                 default:
3365                         return 0;
3366                 }
3367                 break;
3368         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3369                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3370                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3371                         deemph_reg_value = 85;
3372                         margin_reg_value = 78;
3373                         break;
3374                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3375                         deemph_reg_value = 85;
3376                         margin_reg_value = 116;
3377                         break;
3378                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3379                         deemph_reg_value = 85;
3380                         margin_reg_value = 154;
3381                         break;
3382                 default:
3383                         return 0;
3384                 }
3385                 break;
3386         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3387                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3388                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3389                         deemph_reg_value = 64;
3390                         margin_reg_value = 104;
3391                         break;
3392                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3393                         deemph_reg_value = 64;
3394                         margin_reg_value = 154;
3395                         break;
3396                 default:
3397                         return 0;
3398                 }
3399                 break;
3400         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3401                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3402                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3403                         deemph_reg_value = 43;
3404                         margin_reg_value = 154;
3405                         break;
3406                 default:
3407                         return 0;
3408                 }
3409                 break;
3410         default:
3411                 return 0;
3412         }
3413
3414         chv_set_phy_signal_level(encoder, deemph_reg_value,
3415                                  margin_reg_value, uniq_trans_scale);
3416
3417         return 0;
3418 }
3419
3420 static uint32_t
3421 gen4_signal_levels(uint8_t train_set)
3422 {
3423         uint32_t        signal_levels = 0;
3424
3425         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3426         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3427         default:
3428                 signal_levels |= DP_VOLTAGE_0_4;
3429                 break;
3430         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3431                 signal_levels |= DP_VOLTAGE_0_6;
3432                 break;
3433         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3434                 signal_levels |= DP_VOLTAGE_0_8;
3435                 break;
3436         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3437                 signal_levels |= DP_VOLTAGE_1_2;
3438                 break;
3439         }
3440         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3441         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3442         default:
3443                 signal_levels |= DP_PRE_EMPHASIS_0;
3444                 break;
3445         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3446                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3447                 break;
3448         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3449                 signal_levels |= DP_PRE_EMPHASIS_6;
3450                 break;
3451         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3452                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3453                 break;
3454         }
3455         return signal_levels;
3456 }
3457
3458 /* Gen6's DP voltage swing and pre-emphasis control */
3459 static uint32_t
3460 gen6_edp_signal_levels(uint8_t train_set)
3461 {
3462         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3463                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3464         switch (signal_levels) {
3465         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3466         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3467                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3468         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3469                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3470         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3471         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3472                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3473         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3474         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3475                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3476         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3477         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3478                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3479         default:
3480                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3481                               "0x%x\n", signal_levels);
3482                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3483         }
3484 }
3485
3486 /* Gen7's DP voltage swing and pre-emphasis control */
3487 static uint32_t
3488 gen7_edp_signal_levels(uint8_t train_set)
3489 {
3490         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3491                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3492         switch (signal_levels) {
3493         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3494                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3495         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3496                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3497         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3498                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3499
3500         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3501                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3502         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3503                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3504
3505         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3506                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3507         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3508                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3509
3510         default:
3511                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3512                               "0x%x\n", signal_levels);
3513                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3514         }
3515 }
3516
3517 void
3518 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3519 {
3520         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3521         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3522         enum port port = intel_dig_port->base.port;
3523         uint32_t signal_levels, mask = 0;
3524         uint8_t train_set = intel_dp->train_set[0];
3525
3526         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3527                 signal_levels = bxt_signal_levels(intel_dp);
3528         } else if (HAS_DDI(dev_priv)) {
3529                 signal_levels = ddi_signal_levels(intel_dp);
3530                 mask = DDI_BUF_EMP_MASK;
3531         } else if (IS_CHERRYVIEW(dev_priv)) {
3532                 signal_levels = chv_signal_levels(intel_dp);
3533         } else if (IS_VALLEYVIEW(dev_priv)) {
3534                 signal_levels = vlv_signal_levels(intel_dp);
3535         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3536                 signal_levels = gen7_edp_signal_levels(train_set);
3537                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3538         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3539                 signal_levels = gen6_edp_signal_levels(train_set);
3540                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3541         } else {
3542                 signal_levels = gen4_signal_levels(train_set);
3543                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3544         }
3545
3546         if (mask)
3547                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3548
3549         DRM_DEBUG_KMS("Using vswing level %d\n",
3550                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3551         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3552                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3553                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3554
3555         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3556
3557         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3558         POSTING_READ(intel_dp->output_reg);
3559 }
3560
3561 void
3562 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3563                                        uint8_t dp_train_pat)
3564 {
3565         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3566         struct drm_i915_private *dev_priv =
3567                 to_i915(intel_dig_port->base.base.dev);
3568
3569         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3570
3571         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3572         POSTING_READ(intel_dp->output_reg);
3573 }
3574
3575 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3576 {
3577         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3578         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3579         enum port port = intel_dig_port->base.port;
3580         uint32_t val;
3581
3582         if (!HAS_DDI(dev_priv))
3583                 return;
3584
3585         val = I915_READ(DP_TP_CTL(port));
3586         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3587         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3588         I915_WRITE(DP_TP_CTL(port), val);
3589
3590         /*
3591          * On PORT_A we can have only eDP in SST mode. There the only reason
3592          * we need to set idle transmission mode is to work around a HW issue
3593          * where we enable the pipe while not in idle link-training mode.
3594          * In this case there is requirement to wait for a minimum number of
3595          * idle patterns to be sent.
3596          */
3597         if (port == PORT_A)
3598                 return;
3599
3600         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3601                                     DP_TP_STATUS_IDLE_DONE,
3602                                     DP_TP_STATUS_IDLE_DONE,
3603                                     1))
3604                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3605 }
3606
3607 static void
3608 intel_dp_link_down(struct intel_encoder *encoder,
3609                    const struct intel_crtc_state *old_crtc_state)
3610 {
3611         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3612         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3613         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3614         enum port port = encoder->port;
3615         uint32_t DP = intel_dp->DP;
3616
3617         if (WARN_ON(HAS_DDI(dev_priv)))
3618                 return;
3619
3620         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3621                 return;
3622
3623         DRM_DEBUG_KMS("\n");
3624
3625         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3626             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3627                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3628                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3629         } else {
3630                 if (IS_CHERRYVIEW(dev_priv))
3631                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3632                 else
3633                         DP &= ~DP_LINK_TRAIN_MASK;
3634                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3635         }
3636         I915_WRITE(intel_dp->output_reg, DP);
3637         POSTING_READ(intel_dp->output_reg);
3638
3639         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3640         I915_WRITE(intel_dp->output_reg, DP);
3641         POSTING_READ(intel_dp->output_reg);
3642
3643         /*
3644          * HW workaround for IBX, we need to move the port
3645          * to transcoder A after disabling it to allow the
3646          * matching HDMI port to be enabled on transcoder A.
3647          */
3648         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3649                 /*
3650                  * We get CPU/PCH FIFO underruns on the other pipe when
3651                  * doing the workaround. Sweep them under the rug.
3652                  */
3653                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3654                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3655
3656                 /* always enable with pattern 1 (as per spec) */
3657                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3658                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3659                 I915_WRITE(intel_dp->output_reg, DP);
3660                 POSTING_READ(intel_dp->output_reg);
3661
3662                 DP &= ~DP_PORT_EN;
3663                 I915_WRITE(intel_dp->output_reg, DP);
3664                 POSTING_READ(intel_dp->output_reg);
3665
3666                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3667                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3668                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3669         }
3670
3671         msleep(intel_dp->panel_power_down_delay);
3672
3673         intel_dp->DP = DP;
3674
3675         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3676                 pps_lock(intel_dp);
3677                 intel_dp->active_pipe = INVALID_PIPE;
3678                 pps_unlock(intel_dp);
3679         }
3680 }
3681
3682 bool
3683 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3684 {
3685         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3686                              sizeof(intel_dp->dpcd)) < 0)
3687                 return false; /* aux transfer failed */
3688
3689         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3690
3691         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3692 }
3693
3694 static bool
3695 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3696 {
3697         struct drm_i915_private *dev_priv =
3698                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3699
3700         /* this function is meant to be called only once */
3701         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3702
3703         if (!intel_dp_read_dpcd(intel_dp))
3704                 return false;
3705
3706         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3707                          drm_dp_is_branch(intel_dp->dpcd));
3708
3709         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3710                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3711                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3712
3713         /* Check if the panel supports PSR */
3714         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3715                          intel_dp->psr_dpcd,
3716                          sizeof(intel_dp->psr_dpcd));
3717         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3718                 dev_priv->psr.sink_support = true;
3719                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3720         }
3721
3722         if (INTEL_GEN(dev_priv) >= 9 &&
3723             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3724                 uint8_t frame_sync_cap;
3725
3726                 dev_priv->psr.sink_support = true;
3727                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3728                                       DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3729                                       &frame_sync_cap) != 1)
3730                         frame_sync_cap = 0;
3731                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3732                 /* PSR2 needs frame sync as well */
3733                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3734                 DRM_DEBUG_KMS("PSR2 %s on sink",
3735                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3736
3737                 if (dev_priv->psr.psr2_support) {
3738                         dev_priv->psr.y_cord_support =
3739                                 intel_dp_get_y_cord_status(intel_dp);
3740                         dev_priv->psr.colorimetry_support =
3741                                 intel_dp_get_colorimetry_status(intel_dp);
3742                         dev_priv->psr.alpm =
3743                                 intel_dp_get_alpm_status(intel_dp);
3744                 }
3745
3746         }
3747
3748         /*
3749          * Read the eDP display control registers.
3750          *
3751          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3752          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3753          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3754          * method). The display control registers should read zero if they're
3755          * not supported anyway.
3756          */
3757         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3758                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3759                              sizeof(intel_dp->edp_dpcd))
3760                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3761                               intel_dp->edp_dpcd);
3762
3763         /* Read the eDP 1.4+ supported link rates. */
3764         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3765                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3766                 int i;
3767
3768                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3769                                 sink_rates, sizeof(sink_rates));
3770
3771                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3772                         int val = le16_to_cpu(sink_rates[i]);
3773
3774                         if (val == 0)
3775                                 break;
3776
3777                         /* Value read multiplied by 200kHz gives the per-lane
3778                          * link rate in kHz. The source rates are, however,
3779                          * stored in terms of LS_Clk kHz. The full conversion
3780                          * back to symbols is
3781                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3782                          */
3783                         intel_dp->sink_rates[i] = (val * 200) / 10;
3784                 }
3785                 intel_dp->num_sink_rates = i;
3786         }
3787
3788         /*
3789          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3790          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3791          */
3792         if (intel_dp->num_sink_rates)
3793                 intel_dp->use_rate_select = true;
3794         else
3795                 intel_dp_set_sink_rates(intel_dp);
3796
3797         intel_dp_set_common_rates(intel_dp);
3798
3799         return true;
3800 }
3801
3802
3803 static bool
3804 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3805 {
3806         u8 sink_count;
3807
3808         if (!intel_dp_read_dpcd(intel_dp))
3809                 return false;
3810
3811         /* Don't clobber cached eDP rates. */
3812         if (!intel_dp_is_edp(intel_dp)) {
3813                 intel_dp_set_sink_rates(intel_dp);
3814                 intel_dp_set_common_rates(intel_dp);
3815         }
3816
3817         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3818                 return false;
3819
3820         /*
3821          * Sink count can change between short pulse hpd hence
3822          * a member variable in intel_dp will track any changes
3823          * between short pulse interrupts.
3824          */
3825         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3826
3827         /*
3828          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3829          * a dongle is present but no display. Unless we require to know
3830          * if a dongle is present or not, we don't need to update
3831          * downstream port information. So, an early return here saves
3832          * time from performing other operations which are not required.
3833          */
3834         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3835                 return false;
3836
3837         if (!drm_dp_is_branch(intel_dp->dpcd))
3838                 return true; /* native DP sink */
3839
3840         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3841                 return true; /* no per-port downstream info */
3842
3843         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3844                              intel_dp->downstream_ports,
3845                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3846                 return false; /* downstream port status fetch failed */
3847
3848         return true;
3849 }
3850
3851 static bool
3852 intel_dp_can_mst(struct intel_dp *intel_dp)
3853 {
3854         u8 mstm_cap;
3855
3856         if (!i915_modparams.enable_dp_mst)
3857                 return false;
3858
3859         if (!intel_dp->can_mst)
3860                 return false;
3861
3862         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3863                 return false;
3864
3865         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3866                 return false;
3867
3868         return mstm_cap & DP_MST_CAP;
3869 }
3870
3871 static void
3872 intel_dp_configure_mst(struct intel_dp *intel_dp)
3873 {
3874         if (!i915_modparams.enable_dp_mst)
3875                 return;
3876
3877         if (!intel_dp->can_mst)
3878                 return;
3879
3880         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3881
3882         if (intel_dp->is_mst)
3883                 DRM_DEBUG_KMS("Sink is MST capable\n");
3884         else
3885                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3886
3887         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3888                                         intel_dp->is_mst);
3889 }
3890
3891 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp,
3892                                   struct intel_crtc_state *crtc_state, bool disable_wa)
3893 {
3894         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3895         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3896         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3897         u8 buf;
3898         int ret = 0;
3899         int count = 0;
3900         int attempts = 10;
3901
3902         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3903                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3904                 ret = -EIO;
3905                 goto out;
3906         }
3907
3908         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3909                                buf & ~DP_TEST_SINK_START) < 0) {
3910                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3911                 ret = -EIO;
3912                 goto out;
3913         }
3914
3915         do {
3916                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3917
3918                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3919                                       DP_TEST_SINK_MISC, &buf) < 0) {
3920                         ret = -EIO;
3921                         goto out;
3922                 }
3923                 count = buf & DP_TEST_COUNT_MASK;
3924         } while (--attempts && count);
3925
3926         if (attempts == 0) {
3927                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3928                 ret = -ETIMEDOUT;
3929         }
3930
3931  out:
3932         if (disable_wa)
3933                 hsw_enable_ips(crtc_state);
3934         return ret;
3935 }
3936
3937 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp,
3938                                    struct intel_crtc_state *crtc_state)
3939 {
3940         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3941         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3943         u8 buf;
3944         int ret;
3945
3946         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3947                 return -EIO;
3948
3949         if (!(buf & DP_TEST_CRC_SUPPORTED))
3950                 return -ENOTTY;
3951
3952         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3953                 return -EIO;
3954
3955         if (buf & DP_TEST_SINK_START) {
3956                 ret = intel_dp_sink_crc_stop(intel_dp, crtc_state, false);
3957                 if (ret)
3958                         return ret;
3959         }
3960
3961         hsw_disable_ips(crtc_state);
3962
3963         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3964                                buf | DP_TEST_SINK_START) < 0) {
3965                 hsw_enable_ips(crtc_state);
3966                 return -EIO;
3967         }
3968
3969         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3970         return 0;
3971 }
3972
3973 int intel_dp_sink_crc(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, u8 *crc)
3974 {
3975         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3976         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3978         u8 buf;
3979         int count, ret;
3980         int attempts = 6;
3981
3982         ret = intel_dp_sink_crc_start(intel_dp, crtc_state);
3983         if (ret)
3984                 return ret;
3985
3986         do {
3987                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3988
3989                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3990                                       DP_TEST_SINK_MISC, &buf) < 0) {
3991                         ret = -EIO;
3992                         goto stop;
3993                 }
3994                 count = buf & DP_TEST_COUNT_MASK;
3995
3996         } while (--attempts && count == 0);
3997
3998         if (attempts == 0) {
3999                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4000                 ret = -ETIMEDOUT;
4001                 goto stop;
4002         }
4003
4004         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4005                 ret = -EIO;
4006                 goto stop;
4007         }
4008
4009 stop:
4010         intel_dp_sink_crc_stop(intel_dp, crtc_state, true);
4011         return ret;
4012 }
4013
4014 static bool
4015 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4016 {
4017         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
4018                                  sink_irq_vector) == 1;
4019 }
4020
4021 static bool
4022 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4023 {
4024         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4025                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4026                 DP_DPRX_ESI_LEN;
4027 }
4028
4029 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4030 {
4031         int status = 0;
4032         int test_link_rate;
4033         uint8_t test_lane_count, test_link_bw;
4034         /* (DP CTS 1.2)
4035          * 4.3.1.11
4036          */
4037         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4038         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4039                                    &test_lane_count);
4040
4041         if (status <= 0) {
4042                 DRM_DEBUG_KMS("Lane count read failed\n");
4043                 return DP_TEST_NAK;
4044         }
4045         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4046
4047         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4048                                    &test_link_bw);
4049         if (status <= 0) {
4050                 DRM_DEBUG_KMS("Link Rate read failed\n");
4051                 return DP_TEST_NAK;
4052         }
4053         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4054
4055         /* Validate the requested link rate and lane count */
4056         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4057                                         test_lane_count))
4058                 return DP_TEST_NAK;
4059
4060         intel_dp->compliance.test_lane_count = test_lane_count;
4061         intel_dp->compliance.test_link_rate = test_link_rate;
4062
4063         return DP_TEST_ACK;
4064 }
4065
4066 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4067 {
4068         uint8_t test_pattern;
4069         uint8_t test_misc;
4070         __be16 h_width, v_height;
4071         int status = 0;
4072
4073         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4074         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4075                                    &test_pattern);
4076         if (status <= 0) {
4077                 DRM_DEBUG_KMS("Test pattern read failed\n");
4078                 return DP_TEST_NAK;
4079         }
4080         if (test_pattern != DP_COLOR_RAMP)
4081                 return DP_TEST_NAK;
4082
4083         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4084                                   &h_width, 2);
4085         if (status <= 0) {
4086                 DRM_DEBUG_KMS("H Width read failed\n");
4087                 return DP_TEST_NAK;
4088         }
4089
4090         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4091                                   &v_height, 2);
4092         if (status <= 0) {
4093                 DRM_DEBUG_KMS("V Height read failed\n");
4094                 return DP_TEST_NAK;
4095         }
4096
4097         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4098                                    &test_misc);
4099         if (status <= 0) {
4100                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4101                 return DP_TEST_NAK;
4102         }
4103         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4104                 return DP_TEST_NAK;
4105         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4106                 return DP_TEST_NAK;
4107         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4108         case DP_TEST_BIT_DEPTH_6:
4109                 intel_dp->compliance.test_data.bpc = 6;
4110                 break;
4111         case DP_TEST_BIT_DEPTH_8:
4112                 intel_dp->compliance.test_data.bpc = 8;
4113                 break;
4114         default:
4115                 return DP_TEST_NAK;
4116         }
4117
4118         intel_dp->compliance.test_data.video_pattern = test_pattern;
4119         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4120         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4121         /* Set test active flag here so userspace doesn't interrupt things */
4122         intel_dp->compliance.test_active = 1;
4123
4124         return DP_TEST_ACK;
4125 }
4126
4127 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4128 {
4129         uint8_t test_result = DP_TEST_ACK;
4130         struct intel_connector *intel_connector = intel_dp->attached_connector;
4131         struct drm_connector *connector = &intel_connector->base;
4132
4133         if (intel_connector->detect_edid == NULL ||
4134             connector->edid_corrupt ||
4135             intel_dp->aux.i2c_defer_count > 6) {
4136                 /* Check EDID read for NACKs, DEFERs and corruption
4137                  * (DP CTS 1.2 Core r1.1)
4138                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4139                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4140                  *    4.2.2.6 : EDID corruption detected
4141                  * Use failsafe mode for all cases
4142                  */
4143                 if (intel_dp->aux.i2c_nack_count > 0 ||
4144                         intel_dp->aux.i2c_defer_count > 0)
4145                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4146                                       intel_dp->aux.i2c_nack_count,
4147                                       intel_dp->aux.i2c_defer_count);
4148                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4149         } else {
4150                 struct edid *block = intel_connector->detect_edid;
4151
4152                 /* We have to write the checksum
4153                  * of the last block read
4154                  */
4155                 block += intel_connector->detect_edid->extensions;
4156
4157                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4158                                        block->checksum) <= 0)
4159                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4160
4161                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4162                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4163         }
4164
4165         /* Set test active flag here so userspace doesn't interrupt things */
4166         intel_dp->compliance.test_active = 1;
4167
4168         return test_result;
4169 }
4170
4171 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4172 {
4173         uint8_t test_result = DP_TEST_NAK;
4174         return test_result;
4175 }
4176
4177 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4178 {
4179         uint8_t response = DP_TEST_NAK;
4180         uint8_t request = 0;
4181         int status;
4182
4183         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4184         if (status <= 0) {
4185                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4186                 goto update_status;
4187         }
4188
4189         switch (request) {
4190         case DP_TEST_LINK_TRAINING:
4191                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4192                 response = intel_dp_autotest_link_training(intel_dp);
4193                 break;
4194         case DP_TEST_LINK_VIDEO_PATTERN:
4195                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4196                 response = intel_dp_autotest_video_pattern(intel_dp);
4197                 break;
4198         case DP_TEST_LINK_EDID_READ:
4199                 DRM_DEBUG_KMS("EDID test requested\n");
4200                 response = intel_dp_autotest_edid(intel_dp);
4201                 break;
4202         case DP_TEST_LINK_PHY_TEST_PATTERN:
4203                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4204                 response = intel_dp_autotest_phy_pattern(intel_dp);
4205                 break;
4206         default:
4207                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4208                 break;
4209         }
4210
4211         if (response & DP_TEST_ACK)
4212                 intel_dp->compliance.test_type = request;
4213
4214 update_status:
4215         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4216         if (status <= 0)
4217                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4218 }
4219
4220 static int
4221 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4222 {
4223         bool bret;
4224
4225         if (intel_dp->is_mst) {
4226                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4227                 int ret = 0;
4228                 int retry;
4229                 bool handled;
4230                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4231 go_again:
4232                 if (bret == true) {
4233
4234                         /* check link status - esi[10] = 0x200c */
4235                         if (intel_dp->active_mst_links &&
4236                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4237                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4238                                 intel_dp_start_link_train(intel_dp);
4239                                 intel_dp_stop_link_train(intel_dp);
4240                         }
4241
4242                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4243                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4244
4245                         if (handled) {
4246                                 for (retry = 0; retry < 3; retry++) {
4247                                         int wret;
4248                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4249                                                                  DP_SINK_COUNT_ESI+1,
4250                                                                  &esi[1], 3);
4251                                         if (wret == 3) {
4252                                                 break;
4253                                         }
4254                                 }
4255
4256                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4257                                 if (bret == true) {
4258                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4259                                         goto go_again;
4260                                 }
4261                         } else
4262                                 ret = 0;
4263
4264                         return ret;
4265                 } else {
4266                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4267                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4268                         intel_dp->is_mst = false;
4269                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4270                         /* send a hotplug event */
4271                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4272                 }
4273         }
4274         return -EINVAL;
4275 }
4276
4277 static void
4278 intel_dp_retrain_link(struct intel_dp *intel_dp)
4279 {
4280         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4281         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4282         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4283
4284         /* Suppress underruns caused by re-training */
4285         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4286         if (crtc->config->has_pch_encoder)
4287                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4288                                                       intel_crtc_pch_transcoder(crtc), false);
4289
4290         intel_dp_start_link_train(intel_dp);
4291         intel_dp_stop_link_train(intel_dp);
4292
4293         /* Keep underrun reporting disabled until things are stable */
4294         intel_wait_for_vblank(dev_priv, crtc->pipe);
4295
4296         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4297         if (crtc->config->has_pch_encoder)
4298                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4299                                                       intel_crtc_pch_transcoder(crtc), true);
4300 }
4301
4302 static void
4303 intel_dp_check_link_status(struct intel_dp *intel_dp)
4304 {
4305         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4306         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4307         struct drm_connector_state *conn_state =
4308                 intel_dp->attached_connector->base.state;
4309         u8 link_status[DP_LINK_STATUS_SIZE];
4310
4311         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4312
4313         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4314                 DRM_ERROR("Failed to get link status\n");
4315                 return;
4316         }
4317
4318         if (!conn_state->crtc)
4319                 return;
4320
4321         WARN_ON(!drm_modeset_is_locked(&conn_state->crtc->mutex));
4322
4323         if (!conn_state->crtc->state->active)
4324                 return;
4325
4326         if (conn_state->commit &&
4327             !try_wait_for_completion(&conn_state->commit->hw_done))
4328                 return;
4329
4330         /*
4331          * Validate the cached values of intel_dp->link_rate and
4332          * intel_dp->lane_count before attempting to retrain.
4333          */
4334         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4335                                         intel_dp->lane_count))
4336                 return;
4337
4338         /* Retrain if Channel EQ or CR not ok */
4339         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4340                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4341                               intel_encoder->base.name);
4342
4343                 intel_dp_retrain_link(intel_dp);
4344         }
4345 }
4346
4347 /*
4348  * According to DP spec
4349  * 5.1.2:
4350  *  1. Read DPCD
4351  *  2. Configure link according to Receiver Capabilities
4352  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4353  *  4. Check link status on receipt of hot-plug interrupt
4354  *
4355  * intel_dp_short_pulse -  handles short pulse interrupts
4356  * when full detection is not required.
4357  * Returns %true if short pulse is handled and full detection
4358  * is NOT required and %false otherwise.
4359  */
4360 static bool
4361 intel_dp_short_pulse(struct intel_dp *intel_dp)
4362 {
4363         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4364         u8 sink_irq_vector = 0;
4365         u8 old_sink_count = intel_dp->sink_count;
4366         bool ret;
4367
4368         /*
4369          * Clearing compliance test variables to allow capturing
4370          * of values for next automated test request.
4371          */
4372         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4373
4374         /*
4375          * Now read the DPCD to see if it's actually running
4376          * If the current value of sink count doesn't match with
4377          * the value that was stored earlier or dpcd read failed
4378          * we need to do full detection
4379          */
4380         ret = intel_dp_get_dpcd(intel_dp);
4381
4382         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4383                 /* No need to proceed if we are going to do full detect */
4384                 return false;
4385         }
4386
4387         /* Try to read the source of the interrupt */
4388         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4389             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4390             sink_irq_vector != 0) {
4391                 /* Clear interrupt source */
4392                 drm_dp_dpcd_writeb(&intel_dp->aux,
4393                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4394                                    sink_irq_vector);
4395
4396                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4397                         intel_dp_handle_test_request(intel_dp);
4398                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4399                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4400         }
4401
4402         intel_dp_check_link_status(intel_dp);
4403
4404         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4405                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4406                 /* Send a Hotplug Uevent to userspace to start modeset */
4407                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4408         }
4409
4410         return true;
4411 }
4412
4413 /* XXX this is probably wrong for multiple downstream ports */
4414 static enum drm_connector_status
4415 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4416 {
4417         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4418         uint8_t *dpcd = intel_dp->dpcd;
4419         uint8_t type;
4420
4421         if (lspcon->active)
4422                 lspcon_resume(lspcon);
4423
4424         if (!intel_dp_get_dpcd(intel_dp))
4425                 return connector_status_disconnected;
4426
4427         if (intel_dp_is_edp(intel_dp))
4428                 return connector_status_connected;
4429
4430         /* if there's no downstream port, we're done */
4431         if (!drm_dp_is_branch(dpcd))
4432                 return connector_status_connected;
4433
4434         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4435         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4436             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4437
4438                 return intel_dp->sink_count ?
4439                 connector_status_connected : connector_status_disconnected;
4440         }
4441
4442         if (intel_dp_can_mst(intel_dp))
4443                 return connector_status_connected;
4444
4445         /* If no HPD, poke DDC gently */
4446         if (drm_probe_ddc(&intel_dp->aux.ddc))
4447                 return connector_status_connected;
4448
4449         /* Well we tried, say unknown for unreliable port types */
4450         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4451                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4452                 if (type == DP_DS_PORT_TYPE_VGA ||
4453                     type == DP_DS_PORT_TYPE_NON_EDID)
4454                         return connector_status_unknown;
4455         } else {
4456                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4457                         DP_DWN_STRM_PORT_TYPE_MASK;
4458                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4459                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4460                         return connector_status_unknown;
4461         }
4462
4463         /* Anything else is out of spec, warn and ignore */
4464         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4465         return connector_status_disconnected;
4466 }
4467
4468 static enum drm_connector_status
4469 edp_detect(struct intel_dp *intel_dp)
4470 {
4471         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4472         enum drm_connector_status status;
4473
4474         status = intel_panel_detect(dev_priv);
4475         if (status == connector_status_unknown)
4476                 status = connector_status_connected;
4477
4478         return status;
4479 }
4480
4481 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4482 {
4483         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4484         u32 bit;
4485
4486         switch (encoder->hpd_pin) {
4487         case HPD_PORT_B:
4488                 bit = SDE_PORTB_HOTPLUG;
4489                 break;
4490         case HPD_PORT_C:
4491                 bit = SDE_PORTC_HOTPLUG;
4492                 break;
4493         case HPD_PORT_D:
4494                 bit = SDE_PORTD_HOTPLUG;
4495                 break;
4496         default:
4497                 MISSING_CASE(encoder->hpd_pin);
4498                 return false;
4499         }
4500
4501         return I915_READ(SDEISR) & bit;
4502 }
4503
4504 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4505 {
4506         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4507         u32 bit;
4508
4509         switch (encoder->hpd_pin) {
4510         case HPD_PORT_B:
4511                 bit = SDE_PORTB_HOTPLUG_CPT;
4512                 break;
4513         case HPD_PORT_C:
4514                 bit = SDE_PORTC_HOTPLUG_CPT;
4515                 break;
4516         case HPD_PORT_D:
4517                 bit = SDE_PORTD_HOTPLUG_CPT;
4518                 break;
4519         default:
4520                 MISSING_CASE(encoder->hpd_pin);
4521                 return false;
4522         }
4523
4524         return I915_READ(SDEISR) & bit;
4525 }
4526
4527 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4528 {
4529         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4530         u32 bit;
4531
4532         switch (encoder->hpd_pin) {
4533         case HPD_PORT_A:
4534                 bit = SDE_PORTA_HOTPLUG_SPT;
4535                 break;
4536         case HPD_PORT_E:
4537                 bit = SDE_PORTE_HOTPLUG_SPT;
4538                 break;
4539         default:
4540                 return cpt_digital_port_connected(encoder);
4541         }
4542
4543         return I915_READ(SDEISR) & bit;
4544 }
4545
4546 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4547 {
4548         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4549         u32 bit;
4550
4551         switch (encoder->hpd_pin) {
4552         case HPD_PORT_B:
4553                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4554                 break;
4555         case HPD_PORT_C:
4556                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4557                 break;
4558         case HPD_PORT_D:
4559                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4560                 break;
4561         default:
4562                 MISSING_CASE(encoder->hpd_pin);
4563                 return false;
4564         }
4565
4566         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4567 }
4568
4569 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4570 {
4571         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4572         u32 bit;
4573
4574         switch (encoder->hpd_pin) {
4575         case HPD_PORT_B:
4576                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4577                 break;
4578         case HPD_PORT_C:
4579                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4580                 break;
4581         case HPD_PORT_D:
4582                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4583                 break;
4584         default:
4585                 MISSING_CASE(encoder->hpd_pin);
4586                 return false;
4587         }
4588
4589         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4590 }
4591
4592 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4593 {
4594         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4595
4596         if (encoder->hpd_pin == HPD_PORT_A)
4597                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4598         else
4599                 return ibx_digital_port_connected(encoder);
4600 }
4601
4602 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4603 {
4604         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4605
4606         if (encoder->hpd_pin == HPD_PORT_A)
4607                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4608         else
4609                 return cpt_digital_port_connected(encoder);
4610 }
4611
4612 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4613 {
4614         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4615
4616         if (encoder->hpd_pin == HPD_PORT_A)
4617                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4618         else
4619                 return cpt_digital_port_connected(encoder);
4620 }
4621
4622 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4623 {
4624         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4625
4626         if (encoder->hpd_pin == HPD_PORT_A)
4627                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4628         else
4629                 return cpt_digital_port_connected(encoder);
4630 }
4631
4632 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
4633 {
4634         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4635         u32 bit;
4636
4637         switch (encoder->hpd_pin) {
4638         case HPD_PORT_A:
4639                 bit = BXT_DE_PORT_HP_DDIA;
4640                 break;
4641         case HPD_PORT_B:
4642                 bit = BXT_DE_PORT_HP_DDIB;
4643                 break;
4644         case HPD_PORT_C:
4645                 bit = BXT_DE_PORT_HP_DDIC;
4646                 break;
4647         default:
4648                 MISSING_CASE(encoder->hpd_pin);
4649                 return false;
4650         }
4651
4652         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4653 }
4654
4655 /*
4656  * intel_digital_port_connected - is the specified port connected?
4657  * @encoder: intel_encoder
4658  *
4659  * Return %true if port is connected, %false otherwise.
4660  */
4661 bool intel_digital_port_connected(struct intel_encoder *encoder)
4662 {
4663         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4664
4665         if (HAS_GMCH_DISPLAY(dev_priv)) {
4666                 if (IS_GM45(dev_priv))
4667                         return gm45_digital_port_connected(encoder);
4668                 else
4669                         return g4x_digital_port_connected(encoder);
4670         }
4671
4672         if (IS_GEN5(dev_priv))
4673                 return ilk_digital_port_connected(encoder);
4674         else if (IS_GEN6(dev_priv))
4675                 return snb_digital_port_connected(encoder);
4676         else if (IS_GEN7(dev_priv))
4677                 return ivb_digital_port_connected(encoder);
4678         else if (IS_GEN8(dev_priv))
4679                 return bdw_digital_port_connected(encoder);
4680         else if (IS_GEN9_LP(dev_priv))
4681                 return bxt_digital_port_connected(encoder);
4682         else
4683                 return spt_digital_port_connected(encoder);
4684 }
4685
4686 static struct edid *
4687 intel_dp_get_edid(struct intel_dp *intel_dp)
4688 {
4689         struct intel_connector *intel_connector = intel_dp->attached_connector;
4690
4691         /* use cached edid if we have one */
4692         if (intel_connector->edid) {
4693                 /* invalid edid */
4694                 if (IS_ERR(intel_connector->edid))
4695                         return NULL;
4696
4697                 return drm_edid_duplicate(intel_connector->edid);
4698         } else
4699                 return drm_get_edid(&intel_connector->base,
4700                                     &intel_dp->aux.ddc);
4701 }
4702
4703 static void
4704 intel_dp_set_edid(struct intel_dp *intel_dp)
4705 {
4706         struct intel_connector *intel_connector = intel_dp->attached_connector;
4707         struct edid *edid;
4708
4709         intel_dp_unset_edid(intel_dp);
4710         edid = intel_dp_get_edid(intel_dp);
4711         intel_connector->detect_edid = edid;
4712
4713         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4714 }
4715
4716 static void
4717 intel_dp_unset_edid(struct intel_dp *intel_dp)
4718 {
4719         struct intel_connector *intel_connector = intel_dp->attached_connector;
4720
4721         kfree(intel_connector->detect_edid);
4722         intel_connector->detect_edid = NULL;
4723
4724         intel_dp->has_audio = false;
4725 }
4726
4727 static int
4728 intel_dp_long_pulse(struct intel_connector *connector)
4729 {
4730         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
4731         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
4732         enum drm_connector_status status;
4733         u8 sink_irq_vector = 0;
4734
4735         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4736
4737         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4738
4739         /* Can't disconnect eDP, but you can close the lid... */
4740         if (intel_dp_is_edp(intel_dp))
4741                 status = edp_detect(intel_dp);
4742         else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
4743                 status = intel_dp_detect_dpcd(intel_dp);
4744         else
4745                 status = connector_status_disconnected;
4746
4747         if (status == connector_status_disconnected) {
4748                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4749
4750                 if (intel_dp->is_mst) {
4751                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4752                                       intel_dp->is_mst,
4753                                       intel_dp->mst_mgr.mst_state);
4754                         intel_dp->is_mst = false;
4755                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4756                                                         intel_dp->is_mst);
4757                 }
4758
4759                 goto out;
4760         }
4761
4762         if (intel_dp->reset_link_params) {
4763                 /* Initial max link lane count */
4764                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4765
4766                 /* Initial max link rate */
4767                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4768
4769                 intel_dp->reset_link_params = false;
4770         }
4771
4772         intel_dp_print_rates(intel_dp);
4773
4774         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4775                          drm_dp_is_branch(intel_dp->dpcd));
4776
4777         intel_dp_configure_mst(intel_dp);
4778
4779         if (intel_dp->is_mst) {
4780                 /*
4781                  * If we are in MST mode then this connector
4782                  * won't appear connected or have anything
4783                  * with EDID on it
4784                  */
4785                 status = connector_status_disconnected;
4786                 goto out;
4787         } else {
4788                 /*
4789                  * If display is now connected check links status,
4790                  * there has been known issues of link loss triggerring
4791                  * long pulse.
4792                  *
4793                  * Some sinks (eg. ASUS PB287Q) seem to perform some
4794                  * weird HPD ping pong during modesets. So we can apparently
4795                  * end up with HPD going low during a modeset, and then
4796                  * going back up soon after. And once that happens we must
4797                  * retrain the link to get a picture. That's in case no
4798                  * userspace component reacted to intermittent HPD dip.
4799                  */
4800                 intel_dp_check_link_status(intel_dp);
4801         }
4802
4803         /*
4804          * Clearing NACK and defer counts to get their exact values
4805          * while reading EDID which are required by Compliance tests
4806          * 4.2.2.4 and 4.2.2.5
4807          */
4808         intel_dp->aux.i2c_nack_count = 0;
4809         intel_dp->aux.i2c_defer_count = 0;
4810
4811         intel_dp_set_edid(intel_dp);
4812         if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
4813                 status = connector_status_connected;
4814         intel_dp->detect_done = true;
4815
4816         /* Try to read the source of the interrupt */
4817         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4818             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4819             sink_irq_vector != 0) {
4820                 /* Clear interrupt source */
4821                 drm_dp_dpcd_writeb(&intel_dp->aux,
4822                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4823                                    sink_irq_vector);
4824
4825                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4826                         intel_dp_handle_test_request(intel_dp);
4827                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4828                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4829         }
4830
4831 out:
4832         if (status != connector_status_connected && !intel_dp->is_mst)
4833                 intel_dp_unset_edid(intel_dp);
4834
4835         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4836         return status;
4837 }
4838
4839 static int
4840 intel_dp_detect(struct drm_connector *connector,
4841                 struct drm_modeset_acquire_ctx *ctx,
4842                 bool force)
4843 {
4844         struct intel_dp *intel_dp = intel_attached_dp(connector);
4845         int status = connector->status;
4846
4847         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4848                       connector->base.id, connector->name);
4849
4850         /* If full detect is not performed yet, do a full detect */
4851         if (!intel_dp->detect_done) {
4852                 struct drm_crtc *crtc;
4853                 int ret;
4854
4855                 crtc = connector->state->crtc;
4856                 if (crtc) {
4857                         ret = drm_modeset_lock(&crtc->mutex, ctx);
4858                         if (ret)
4859                                 return ret;
4860                 }
4861
4862                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4863         }
4864
4865         intel_dp->detect_done = false;
4866
4867         return status;
4868 }
4869
4870 static void
4871 intel_dp_force(struct drm_connector *connector)
4872 {
4873         struct intel_dp *intel_dp = intel_attached_dp(connector);
4874         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4875         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4876
4877         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4878                       connector->base.id, connector->name);
4879         intel_dp_unset_edid(intel_dp);
4880
4881         if (connector->status != connector_status_connected)
4882                 return;
4883
4884         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4885
4886         intel_dp_set_edid(intel_dp);
4887
4888         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4889 }
4890
4891 static int intel_dp_get_modes(struct drm_connector *connector)
4892 {
4893         struct intel_connector *intel_connector = to_intel_connector(connector);
4894         struct edid *edid;
4895
4896         edid = intel_connector->detect_edid;
4897         if (edid) {
4898                 int ret = intel_connector_update_modes(connector, edid);
4899                 if (ret)
4900                         return ret;
4901         }
4902
4903         /* if eDP has no EDID, fall back to fixed mode */
4904         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4905             intel_connector->panel.fixed_mode) {
4906                 struct drm_display_mode *mode;
4907
4908                 mode = drm_mode_duplicate(connector->dev,
4909                                           intel_connector->panel.fixed_mode);
4910                 if (mode) {
4911                         drm_mode_probed_add(connector, mode);
4912                         return 1;
4913                 }
4914         }
4915
4916         return 0;
4917 }
4918
4919 static int
4920 intel_dp_connector_register(struct drm_connector *connector)
4921 {
4922         struct intel_dp *intel_dp = intel_attached_dp(connector);
4923         int ret;
4924
4925         ret = intel_connector_register(connector);
4926         if (ret)
4927                 return ret;
4928
4929         i915_debugfs_connector_add(connector);
4930
4931         DRM_DEBUG_KMS("registering %s bus for %s\n",
4932                       intel_dp->aux.name, connector->kdev->kobj.name);
4933
4934         intel_dp->aux.dev = connector->kdev;
4935         return drm_dp_aux_register(&intel_dp->aux);
4936 }
4937
4938 static void
4939 intel_dp_connector_unregister(struct drm_connector *connector)
4940 {
4941         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4942         intel_connector_unregister(connector);
4943 }
4944
4945 static void
4946 intel_dp_connector_destroy(struct drm_connector *connector)
4947 {
4948         struct intel_connector *intel_connector = to_intel_connector(connector);
4949
4950         kfree(intel_connector->detect_edid);
4951
4952         if (!IS_ERR_OR_NULL(intel_connector->edid))
4953                 kfree(intel_connector->edid);
4954
4955         /*
4956          * Can't call intel_dp_is_edp() since the encoder may have been
4957          * destroyed already.
4958          */
4959         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4960                 intel_panel_fini(&intel_connector->panel);
4961
4962         drm_connector_cleanup(connector);
4963         kfree(connector);
4964 }
4965
4966 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4967 {
4968         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4969         struct intel_dp *intel_dp = &intel_dig_port->dp;
4970
4971         intel_dp_mst_encoder_cleanup(intel_dig_port);
4972         if (intel_dp_is_edp(intel_dp)) {
4973                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4974                 /*
4975                  * vdd might still be enabled do to the delayed vdd off.
4976                  * Make sure vdd is actually turned off here.
4977                  */
4978                 pps_lock(intel_dp);
4979                 edp_panel_vdd_off_sync(intel_dp);
4980                 pps_unlock(intel_dp);
4981
4982                 if (intel_dp->edp_notifier.notifier_call) {
4983                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4984                         intel_dp->edp_notifier.notifier_call = NULL;
4985                 }
4986         }
4987
4988         intel_dp_aux_fini(intel_dp);
4989
4990         drm_encoder_cleanup(encoder);
4991         kfree(intel_dig_port);
4992 }
4993
4994 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4995 {
4996         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4997
4998         if (!intel_dp_is_edp(intel_dp))
4999                 return;
5000
5001         /*
5002          * vdd might still be enabled do to the delayed vdd off.
5003          * Make sure vdd is actually turned off here.
5004          */
5005         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5006         pps_lock(intel_dp);
5007         edp_panel_vdd_off_sync(intel_dp);
5008         pps_unlock(intel_dp);
5009 }
5010
5011 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5012 {
5013         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5014
5015         lockdep_assert_held(&dev_priv->pps_mutex);
5016
5017         if (!edp_have_panel_vdd(intel_dp))
5018                 return;
5019
5020         /*
5021          * The VDD bit needs a power domain reference, so if the bit is
5022          * already enabled when we boot or resume, grab this reference and
5023          * schedule a vdd off, so we don't hold on to the reference
5024          * indefinitely.
5025          */
5026         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5027         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5028
5029         edp_panel_vdd_schedule_off(intel_dp);
5030 }
5031
5032 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5033 {
5034         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5035
5036         if ((intel_dp->DP & DP_PORT_EN) == 0)
5037                 return INVALID_PIPE;
5038
5039         if (IS_CHERRYVIEW(dev_priv))
5040                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5041         else
5042                 return PORT_TO_PIPE(intel_dp->DP);
5043 }
5044
5045 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5046 {
5047         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5048         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5049         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5050
5051         if (!HAS_DDI(dev_priv))
5052                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5053
5054         if (lspcon->active)
5055                 lspcon_resume(lspcon);
5056
5057         intel_dp->reset_link_params = true;
5058
5059         pps_lock(intel_dp);
5060
5061         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5062                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5063
5064         if (intel_dp_is_edp(intel_dp)) {
5065                 /* Reinit the power sequencer, in case BIOS did something with it. */
5066                 intel_dp_pps_init(intel_dp);
5067                 intel_edp_panel_vdd_sanitize(intel_dp);
5068         }
5069
5070         pps_unlock(intel_dp);
5071 }
5072
5073 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5074         .force = intel_dp_force,
5075         .fill_modes = drm_helper_probe_single_connector_modes,
5076         .atomic_get_property = intel_digital_connector_atomic_get_property,
5077         .atomic_set_property = intel_digital_connector_atomic_set_property,
5078         .late_register = intel_dp_connector_register,
5079         .early_unregister = intel_dp_connector_unregister,
5080         .destroy = intel_dp_connector_destroy,
5081         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5082         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5083 };
5084
5085 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5086         .detect_ctx = intel_dp_detect,
5087         .get_modes = intel_dp_get_modes,
5088         .mode_valid = intel_dp_mode_valid,
5089         .atomic_check = intel_digital_connector_atomic_check,
5090 };
5091
5092 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5093         .reset = intel_dp_encoder_reset,
5094         .destroy = intel_dp_encoder_destroy,
5095 };
5096
5097 enum irqreturn
5098 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5099 {
5100         struct intel_dp *intel_dp = &intel_dig_port->dp;
5101         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5102         enum irqreturn ret = IRQ_NONE;
5103
5104         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5105                 /*
5106                  * vdd off can generate a long pulse on eDP which
5107                  * would require vdd on to handle it, and thus we
5108                  * would end up in an endless cycle of
5109                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5110                  */
5111                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5112                               port_name(intel_dig_port->base.port));
5113                 return IRQ_HANDLED;
5114         }
5115
5116         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5117                       port_name(intel_dig_port->base.port),
5118                       long_hpd ? "long" : "short");
5119
5120         if (long_hpd) {
5121                 intel_dp->reset_link_params = true;
5122                 intel_dp->detect_done = false;
5123                 return IRQ_NONE;
5124         }
5125
5126         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5127
5128         if (intel_dp->is_mst) {
5129                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5130                         /*
5131                          * If we were in MST mode, and device is not
5132                          * there, get out of MST mode
5133                          */
5134                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5135                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5136                         intel_dp->is_mst = false;
5137                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5138                                                         intel_dp->is_mst);
5139                         intel_dp->detect_done = false;
5140                         goto put_power;
5141                 }
5142         }
5143
5144         if (!intel_dp->is_mst) {
5145                 struct drm_modeset_acquire_ctx ctx;
5146                 struct drm_connector *connector = &intel_dp->attached_connector->base;
5147                 struct drm_crtc *crtc;
5148                 int iret;
5149                 bool handled = false;
5150
5151                 drm_modeset_acquire_init(&ctx, 0);
5152 retry:
5153                 iret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
5154                 if (iret)
5155                         goto err;
5156
5157                 crtc = connector->state->crtc;
5158                 if (crtc) {
5159                         iret = drm_modeset_lock(&crtc->mutex, &ctx);
5160                         if (iret)
5161                                 goto err;
5162                 }
5163
5164                 handled = intel_dp_short_pulse(intel_dp);
5165
5166 err:
5167                 if (iret == -EDEADLK) {
5168                         drm_modeset_backoff(&ctx);
5169                         goto retry;
5170                 }
5171
5172                 drm_modeset_drop_locks(&ctx);
5173                 drm_modeset_acquire_fini(&ctx);
5174                 WARN(iret, "Acquiring modeset locks failed with %i\n", iret);
5175
5176                 if (!handled) {
5177                         intel_dp->detect_done = false;
5178                         goto put_power;
5179                 }
5180         }
5181
5182         ret = IRQ_HANDLED;
5183
5184 put_power:
5185         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5186
5187         return ret;
5188 }
5189
5190 /* check the VBT to see whether the eDP is on another port */
5191 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5192 {
5193         /*
5194          * eDP not supported on g4x. so bail out early just
5195          * for a bit extra safety in case the VBT is bonkers.
5196          */
5197         if (INTEL_GEN(dev_priv) < 5)
5198                 return false;
5199
5200         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5201                 return true;
5202
5203         return intel_bios_is_port_edp(dev_priv, port);
5204 }
5205
5206 static void
5207 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5208 {
5209         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5210         enum port port = dp_to_dig_port(intel_dp)->base.port;
5211
5212         if (!IS_G4X(dev_priv) && port != PORT_A)
5213                 intel_attach_force_audio_property(connector);
5214
5215         intel_attach_broadcast_rgb_property(connector);
5216
5217         if (intel_dp_is_edp(intel_dp)) {
5218                 u32 allowed_scalers;
5219
5220                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5221                 if (!HAS_GMCH_DISPLAY(dev_priv))
5222                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5223
5224                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5225
5226                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5227
5228         }
5229 }
5230
5231 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5232 {
5233         intel_dp->panel_power_off_time = ktime_get_boottime();
5234         intel_dp->last_power_on = jiffies;
5235         intel_dp->last_backlight_off = jiffies;
5236 }
5237
5238 static void
5239 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5240 {
5241         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5242         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5243         struct pps_registers regs;
5244
5245         intel_pps_get_registers(intel_dp, &regs);
5246
5247         /* Workaround: Need to write PP_CONTROL with the unlock key as
5248          * the very first thing. */
5249         pp_ctl = ironlake_get_pp_control(intel_dp);
5250
5251         pp_on = I915_READ(regs.pp_on);
5252         pp_off = I915_READ(regs.pp_off);
5253         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5254             !HAS_PCH_ICP(dev_priv)) {
5255                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5256                 pp_div = I915_READ(regs.pp_div);
5257         }
5258
5259         /* Pull timing values out of registers */
5260         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5261                      PANEL_POWER_UP_DELAY_SHIFT;
5262
5263         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5264                   PANEL_LIGHT_ON_DELAY_SHIFT;
5265
5266         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5267                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5268
5269         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5270                    PANEL_POWER_DOWN_DELAY_SHIFT;
5271
5272         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5273             HAS_PCH_ICP(dev_priv)) {
5274                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5275                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5276         } else {
5277                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5278                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5279         }
5280 }
5281
5282 static void
5283 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5284 {
5285         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5286                       state_name,
5287                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5288 }
5289
5290 static void
5291 intel_pps_verify_state(struct intel_dp *intel_dp)
5292 {
5293         struct edp_power_seq hw;
5294         struct edp_power_seq *sw = &intel_dp->pps_delays;
5295
5296         intel_pps_readout_hw_state(intel_dp, &hw);
5297
5298         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5299             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5300                 DRM_ERROR("PPS state mismatch\n");
5301                 intel_pps_dump_state("sw", sw);
5302                 intel_pps_dump_state("hw", &hw);
5303         }
5304 }
5305
5306 static void
5307 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5308 {
5309         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5310         struct edp_power_seq cur, vbt, spec,
5311                 *final = &intel_dp->pps_delays;
5312
5313         lockdep_assert_held(&dev_priv->pps_mutex);
5314
5315         /* already initialized? */
5316         if (final->t11_t12 != 0)
5317                 return;
5318
5319         intel_pps_readout_hw_state(intel_dp, &cur);
5320
5321         intel_pps_dump_state("cur", &cur);
5322
5323         vbt = dev_priv->vbt.edp.pps;
5324         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5325          * of 500ms appears to be too short. Ocassionally the panel
5326          * just fails to power back on. Increasing the delay to 800ms
5327          * seems sufficient to avoid this problem.
5328          */
5329         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5330                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5331                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5332                               vbt.t11_t12);
5333         }
5334         /* T11_T12 delay is special and actually in units of 100ms, but zero
5335          * based in the hw (so we need to add 100 ms). But the sw vbt
5336          * table multiplies it with 1000 to make it in units of 100usec,
5337          * too. */
5338         vbt.t11_t12 += 100 * 10;
5339
5340         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5341          * our hw here, which are all in 100usec. */
5342         spec.t1_t3 = 210 * 10;
5343         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5344         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5345         spec.t10 = 500 * 10;
5346         /* This one is special and actually in units of 100ms, but zero
5347          * based in the hw (so we need to add 100 ms). But the sw vbt
5348          * table multiplies it with 1000 to make it in units of 100usec,
5349          * too. */
5350         spec.t11_t12 = (510 + 100) * 10;
5351
5352         intel_pps_dump_state("vbt", &vbt);
5353
5354         /* Use the max of the register settings and vbt. If both are
5355          * unset, fall back to the spec limits. */
5356 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5357                                        spec.field : \
5358                                        max(cur.field, vbt.field))
5359         assign_final(t1_t3);
5360         assign_final(t8);
5361         assign_final(t9);
5362         assign_final(t10);
5363         assign_final(t11_t12);
5364 #undef assign_final
5365
5366 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5367         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5368         intel_dp->backlight_on_delay = get_delay(t8);
5369         intel_dp->backlight_off_delay = get_delay(t9);
5370         intel_dp->panel_power_down_delay = get_delay(t10);
5371         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5372 #undef get_delay
5373
5374         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5375                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5376                       intel_dp->panel_power_cycle_delay);
5377
5378         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5379                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5380
5381         /*
5382          * We override the HW backlight delays to 1 because we do manual waits
5383          * on them. For T8, even BSpec recommends doing it. For T9, if we
5384          * don't do this, we'll end up waiting for the backlight off delay
5385          * twice: once when we do the manual sleep, and once when we disable
5386          * the panel and wait for the PP_STATUS bit to become zero.
5387          */
5388         final->t8 = 1;
5389         final->t9 = 1;
5390
5391         /*
5392          * HW has only a 100msec granularity for t11_t12 so round it up
5393          * accordingly.
5394          */
5395         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5396 }
5397
5398 static void
5399 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5400                                               bool force_disable_vdd)
5401 {
5402         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5403         u32 pp_on, pp_off, pp_div, port_sel = 0;
5404         int div = dev_priv->rawclk_freq / 1000;
5405         struct pps_registers regs;
5406         enum port port = dp_to_dig_port(intel_dp)->base.port;
5407         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5408
5409         lockdep_assert_held(&dev_priv->pps_mutex);
5410
5411         intel_pps_get_registers(intel_dp, &regs);
5412
5413         /*
5414          * On some VLV machines the BIOS can leave the VDD
5415          * enabled even on power seqeuencers which aren't
5416          * hooked up to any port. This would mess up the
5417          * power domain tracking the first time we pick
5418          * one of these power sequencers for use since
5419          * edp_panel_vdd_on() would notice that the VDD was
5420          * already on and therefore wouldn't grab the power
5421          * domain reference. Disable VDD first to avoid this.
5422          * This also avoids spuriously turning the VDD on as
5423          * soon as the new power seqeuencer gets initialized.
5424          */
5425         if (force_disable_vdd) {
5426                 u32 pp = ironlake_get_pp_control(intel_dp);
5427
5428                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5429
5430                 if (pp & EDP_FORCE_VDD)
5431                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5432
5433                 pp &= ~EDP_FORCE_VDD;
5434
5435                 I915_WRITE(regs.pp_ctrl, pp);
5436         }
5437
5438         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5439                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5440         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5441                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5442         /* Compute the divisor for the pp clock, simply match the Bspec
5443          * formula. */
5444         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5445             HAS_PCH_ICP(dev_priv)) {
5446                 pp_div = I915_READ(regs.pp_ctrl);
5447                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5448                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5449                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5450         } else {
5451                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5452                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5453                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5454         }
5455
5456         /* Haswell doesn't have any port selection bits for the panel
5457          * power sequencer any more. */
5458         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5459                 port_sel = PANEL_PORT_SELECT_VLV(port);
5460         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5461                 if (port == PORT_A)
5462                         port_sel = PANEL_PORT_SELECT_DPA;
5463                 else
5464                         port_sel = PANEL_PORT_SELECT_DPD;
5465         }
5466
5467         pp_on |= port_sel;
5468
5469         I915_WRITE(regs.pp_on, pp_on);
5470         I915_WRITE(regs.pp_off, pp_off);
5471         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5472             HAS_PCH_ICP(dev_priv))
5473                 I915_WRITE(regs.pp_ctrl, pp_div);
5474         else
5475                 I915_WRITE(regs.pp_div, pp_div);
5476
5477         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5478                       I915_READ(regs.pp_on),
5479                       I915_READ(regs.pp_off),
5480                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
5481                        HAS_PCH_ICP(dev_priv)) ?
5482                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5483                       I915_READ(regs.pp_div));
5484 }
5485
5486 static void intel_dp_pps_init(struct intel_dp *intel_dp)
5487 {
5488         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5489
5490         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5491                 vlv_initial_power_sequencer_setup(intel_dp);
5492         } else {
5493                 intel_dp_init_panel_power_sequencer(intel_dp);
5494                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
5495         }
5496 }
5497
5498 /**
5499  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5500  * @dev_priv: i915 device
5501  * @crtc_state: a pointer to the active intel_crtc_state
5502  * @refresh_rate: RR to be programmed
5503  *
5504  * This function gets called when refresh rate (RR) has to be changed from
5505  * one frequency to another. Switches can be between high and low RR
5506  * supported by the panel or to any other RR based on media playback (in
5507  * this case, RR value needs to be passed from user space).
5508  *
5509  * The caller of this function needs to take a lock on dev_priv->drrs.
5510  */
5511 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5512                                     const struct intel_crtc_state *crtc_state,
5513                                     int refresh_rate)
5514 {
5515         struct intel_encoder *encoder;
5516         struct intel_digital_port *dig_port = NULL;
5517         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5519         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5520
5521         if (refresh_rate <= 0) {
5522                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5523                 return;
5524         }
5525
5526         if (intel_dp == NULL) {
5527                 DRM_DEBUG_KMS("DRRS not supported.\n");
5528                 return;
5529         }
5530
5531         dig_port = dp_to_dig_port(intel_dp);
5532         encoder = &dig_port->base;
5533
5534         if (!intel_crtc) {
5535                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5536                 return;
5537         }
5538
5539         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5540                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5541                 return;
5542         }
5543
5544         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5545                         refresh_rate)
5546                 index = DRRS_LOW_RR;
5547
5548         if (index == dev_priv->drrs.refresh_rate_type) {
5549                 DRM_DEBUG_KMS(
5550                         "DRRS requested for previously set RR...ignoring\n");
5551                 return;
5552         }
5553
5554         if (!crtc_state->base.active) {
5555                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5556                 return;
5557         }
5558
5559         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5560                 switch (index) {
5561                 case DRRS_HIGH_RR:
5562                         intel_dp_set_m_n(intel_crtc, M1_N1);
5563                         break;
5564                 case DRRS_LOW_RR:
5565                         intel_dp_set_m_n(intel_crtc, M2_N2);
5566                         break;
5567                 case DRRS_MAX_RR:
5568                 default:
5569                         DRM_ERROR("Unsupported refreshrate type\n");
5570                 }
5571         } else if (INTEL_GEN(dev_priv) > 6) {
5572                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5573                 u32 val;
5574
5575                 val = I915_READ(reg);
5576                 if (index > DRRS_HIGH_RR) {
5577                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5578                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5579                         else
5580                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5581                 } else {
5582                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5583                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5584                         else
5585                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5586                 }
5587                 I915_WRITE(reg, val);
5588         }
5589
5590         dev_priv->drrs.refresh_rate_type = index;
5591
5592         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5593 }
5594
5595 /**
5596  * intel_edp_drrs_enable - init drrs struct if supported
5597  * @intel_dp: DP struct
5598  * @crtc_state: A pointer to the active crtc state.
5599  *
5600  * Initializes frontbuffer_bits and drrs.dp
5601  */
5602 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5603                            const struct intel_crtc_state *crtc_state)
5604 {
5605         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5606
5607         if (!crtc_state->has_drrs) {
5608                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5609                 return;
5610         }
5611
5612         if (dev_priv->psr.enabled) {
5613                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5614                 return;
5615         }
5616
5617         mutex_lock(&dev_priv->drrs.mutex);
5618         if (WARN_ON(dev_priv->drrs.dp)) {
5619                 DRM_ERROR("DRRS already enabled\n");
5620                 goto unlock;
5621         }
5622
5623         dev_priv->drrs.busy_frontbuffer_bits = 0;
5624
5625         dev_priv->drrs.dp = intel_dp;
5626
5627 unlock:
5628         mutex_unlock(&dev_priv->drrs.mutex);
5629 }
5630
5631 /**
5632  * intel_edp_drrs_disable - Disable DRRS
5633  * @intel_dp: DP struct
5634  * @old_crtc_state: Pointer to old crtc_state.
5635  *
5636  */
5637 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5638                             const struct intel_crtc_state *old_crtc_state)
5639 {
5640         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5641
5642         if (!old_crtc_state->has_drrs)
5643                 return;
5644
5645         mutex_lock(&dev_priv->drrs.mutex);
5646         if (!dev_priv->drrs.dp) {
5647                 mutex_unlock(&dev_priv->drrs.mutex);
5648                 return;
5649         }
5650
5651         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5652                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5653                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5654
5655         dev_priv->drrs.dp = NULL;
5656         mutex_unlock(&dev_priv->drrs.mutex);
5657
5658         cancel_delayed_work_sync(&dev_priv->drrs.work);
5659 }
5660
5661 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5662 {
5663         struct drm_i915_private *dev_priv =
5664                 container_of(work, typeof(*dev_priv), drrs.work.work);
5665         struct intel_dp *intel_dp;
5666
5667         mutex_lock(&dev_priv->drrs.mutex);
5668
5669         intel_dp = dev_priv->drrs.dp;
5670
5671         if (!intel_dp)
5672                 goto unlock;
5673
5674         /*
5675          * The delayed work can race with an invalidate hence we need to
5676          * recheck.
5677          */
5678
5679         if (dev_priv->drrs.busy_frontbuffer_bits)
5680                 goto unlock;
5681
5682         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5683                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5684
5685                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5686                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5687         }
5688
5689 unlock:
5690         mutex_unlock(&dev_priv->drrs.mutex);
5691 }
5692
5693 /**
5694  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5695  * @dev_priv: i915 device
5696  * @frontbuffer_bits: frontbuffer plane tracking bits
5697  *
5698  * This function gets called everytime rendering on the given planes start.
5699  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5700  *
5701  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5702  */
5703 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5704                                unsigned int frontbuffer_bits)
5705 {
5706         struct drm_crtc *crtc;
5707         enum pipe pipe;
5708
5709         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5710                 return;
5711
5712         cancel_delayed_work(&dev_priv->drrs.work);
5713
5714         mutex_lock(&dev_priv->drrs.mutex);
5715         if (!dev_priv->drrs.dp) {
5716                 mutex_unlock(&dev_priv->drrs.mutex);
5717                 return;
5718         }
5719
5720         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5721         pipe = to_intel_crtc(crtc)->pipe;
5722
5723         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5724         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5725
5726         /* invalidate means busy screen hence upclock */
5727         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5728                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5729                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5730
5731         mutex_unlock(&dev_priv->drrs.mutex);
5732 }
5733
5734 /**
5735  * intel_edp_drrs_flush - Restart Idleness DRRS
5736  * @dev_priv: i915 device
5737  * @frontbuffer_bits: frontbuffer plane tracking bits
5738  *
5739  * This function gets called every time rendering on the given planes has
5740  * completed or flip on a crtc is completed. So DRRS should be upclocked
5741  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5742  * if no other planes are dirty.
5743  *
5744  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5745  */
5746 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5747                           unsigned int frontbuffer_bits)
5748 {
5749         struct drm_crtc *crtc;
5750         enum pipe pipe;
5751
5752         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5753                 return;
5754
5755         cancel_delayed_work(&dev_priv->drrs.work);
5756
5757         mutex_lock(&dev_priv->drrs.mutex);
5758         if (!dev_priv->drrs.dp) {
5759                 mutex_unlock(&dev_priv->drrs.mutex);
5760                 return;
5761         }
5762
5763         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5764         pipe = to_intel_crtc(crtc)->pipe;
5765
5766         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5767         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5768
5769         /* flush means busy screen hence upclock */
5770         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5771                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5772                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5773
5774         /*
5775          * flush also means no more activity hence schedule downclock, if all
5776          * other fbs are quiescent too
5777          */
5778         if (!dev_priv->drrs.busy_frontbuffer_bits)
5779                 schedule_delayed_work(&dev_priv->drrs.work,
5780                                 msecs_to_jiffies(1000));
5781         mutex_unlock(&dev_priv->drrs.mutex);
5782 }
5783
5784 /**
5785  * DOC: Display Refresh Rate Switching (DRRS)
5786  *
5787  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5788  * which enables swtching between low and high refresh rates,
5789  * dynamically, based on the usage scenario. This feature is applicable
5790  * for internal panels.
5791  *
5792  * Indication that the panel supports DRRS is given by the panel EDID, which
5793  * would list multiple refresh rates for one resolution.
5794  *
5795  * DRRS is of 2 types - static and seamless.
5796  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5797  * (may appear as a blink on screen) and is used in dock-undock scenario.
5798  * Seamless DRRS involves changing RR without any visual effect to the user
5799  * and can be used during normal system usage. This is done by programming
5800  * certain registers.
5801  *
5802  * Support for static/seamless DRRS may be indicated in the VBT based on
5803  * inputs from the panel spec.
5804  *
5805  * DRRS saves power by switching to low RR based on usage scenarios.
5806  *
5807  * The implementation is based on frontbuffer tracking implementation.  When
5808  * there is a disturbance on the screen triggered by user activity or a periodic
5809  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5810  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5811  * made.
5812  *
5813  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5814  * and intel_edp_drrs_flush() are called.
5815  *
5816  * DRRS can be further extended to support other internal panels and also
5817  * the scenario of video playback wherein RR is set based on the rate
5818  * requested by userspace.
5819  */
5820
5821 /**
5822  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5823  * @connector: eDP connector
5824  * @fixed_mode: preferred mode of panel
5825  *
5826  * This function is  called only once at driver load to initialize basic
5827  * DRRS stuff.
5828  *
5829  * Returns:
5830  * Downclock mode if panel supports it, else return NULL.
5831  * DRRS support is determined by the presence of downclock mode (apart
5832  * from VBT setting).
5833  */
5834 static struct drm_display_mode *
5835 intel_dp_drrs_init(struct intel_connector *connector,
5836                    struct drm_display_mode *fixed_mode)
5837 {
5838         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5839         struct drm_display_mode *downclock_mode = NULL;
5840
5841         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5842         mutex_init(&dev_priv->drrs.mutex);
5843
5844         if (INTEL_GEN(dev_priv) <= 6) {
5845                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5846                 return NULL;
5847         }
5848
5849         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5850                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5851                 return NULL;
5852         }
5853
5854         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
5855                                                     &connector->base);
5856
5857         if (!downclock_mode) {
5858                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5859                 return NULL;
5860         }
5861
5862         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5863
5864         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5865         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5866         return downclock_mode;
5867 }
5868
5869 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5870                                      struct intel_connector *intel_connector)
5871 {
5872         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5873         struct drm_i915_private *dev_priv = to_i915(dev);
5874         struct drm_connector *connector = &intel_connector->base;
5875         struct drm_display_mode *fixed_mode = NULL;
5876         struct drm_display_mode *alt_fixed_mode = NULL;
5877         struct drm_display_mode *downclock_mode = NULL;
5878         bool has_dpcd;
5879         struct drm_display_mode *scan;
5880         struct edid *edid;
5881         enum pipe pipe = INVALID_PIPE;
5882
5883         if (!intel_dp_is_edp(intel_dp))
5884                 return true;
5885
5886         /*
5887          * On IBX/CPT we may get here with LVDS already registered. Since the
5888          * driver uses the only internal power sequencer available for both
5889          * eDP and LVDS bail out early in this case to prevent interfering
5890          * with an already powered-on LVDS power sequencer.
5891          */
5892         if (intel_get_lvds_encoder(&dev_priv->drm)) {
5893                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5894                 DRM_INFO("LVDS was detected, not registering eDP\n");
5895
5896                 return false;
5897         }
5898
5899         pps_lock(intel_dp);
5900
5901         intel_dp_init_panel_power_timestamps(intel_dp);
5902         intel_dp_pps_init(intel_dp);
5903         intel_edp_panel_vdd_sanitize(intel_dp);
5904
5905         pps_unlock(intel_dp);
5906
5907         /* Cache DPCD and EDID for edp. */
5908         has_dpcd = intel_edp_init_dpcd(intel_dp);
5909
5910         if (!has_dpcd) {
5911                 /* if this fails, presume the device is a ghost */
5912                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5913                 goto out_vdd_off;
5914         }
5915
5916         mutex_lock(&dev->mode_config.mutex);
5917         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5918         if (edid) {
5919                 if (drm_add_edid_modes(connector, edid)) {
5920                         drm_mode_connector_update_edid_property(connector,
5921                                                                 edid);
5922                 } else {
5923                         kfree(edid);
5924                         edid = ERR_PTR(-EINVAL);
5925                 }
5926         } else {
5927                 edid = ERR_PTR(-ENOENT);
5928         }
5929         intel_connector->edid = edid;
5930
5931         /* prefer fixed mode from EDID if available, save an alt mode also */
5932         list_for_each_entry(scan, &connector->probed_modes, head) {
5933                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5934                         fixed_mode = drm_mode_duplicate(dev, scan);
5935                         downclock_mode = intel_dp_drrs_init(
5936                                                 intel_connector, fixed_mode);
5937                 } else if (!alt_fixed_mode) {
5938                         alt_fixed_mode = drm_mode_duplicate(dev, scan);
5939                 }
5940         }
5941
5942         /* fallback to VBT if available for eDP */
5943         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5944                 fixed_mode = drm_mode_duplicate(dev,
5945                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5946                 if (fixed_mode) {
5947                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5948                         connector->display_info.width_mm = fixed_mode->width_mm;
5949                         connector->display_info.height_mm = fixed_mode->height_mm;
5950                 }
5951         }
5952         mutex_unlock(&dev->mode_config.mutex);
5953
5954         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5955                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5956                 register_reboot_notifier(&intel_dp->edp_notifier);
5957
5958                 /*
5959                  * Figure out the current pipe for the initial backlight setup.
5960                  * If the current pipe isn't valid, try the PPS pipe, and if that
5961                  * fails just assume pipe A.
5962                  */
5963                 pipe = vlv_active_pipe(intel_dp);
5964
5965                 if (pipe != PIPE_A && pipe != PIPE_B)
5966                         pipe = intel_dp->pps_pipe;
5967
5968                 if (pipe != PIPE_A && pipe != PIPE_B)
5969                         pipe = PIPE_A;
5970
5971                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5972                               pipe_name(pipe));
5973         }
5974
5975         intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode,
5976                          downclock_mode);
5977         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5978         intel_panel_setup_backlight(connector, pipe);
5979
5980         return true;
5981
5982 out_vdd_off:
5983         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5984         /*
5985          * vdd might still be enabled do to the delayed vdd off.
5986          * Make sure vdd is actually turned off here.
5987          */
5988         pps_lock(intel_dp);
5989         edp_panel_vdd_off_sync(intel_dp);
5990         pps_unlock(intel_dp);
5991
5992         return false;
5993 }
5994
5995 /* Set up the hotplug pin and aux power domain. */
5996 static void
5997 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5998 {
5999         struct intel_encoder *encoder = &intel_dig_port->base;
6000         struct intel_dp *intel_dp = &intel_dig_port->dp;
6001         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6002         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
6003
6004         encoder->hpd_pin = intel_hpd_pin_default(dev_priv, encoder->port);
6005
6006         switch (encoder->port) {
6007         case PORT_A:
6008                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
6009                 break;
6010         case PORT_B:
6011                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
6012                 break;
6013         case PORT_C:
6014                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
6015                 break;
6016         case PORT_D:
6017                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
6018                 break;
6019         case PORT_E:
6020                 /* FIXME: Check VBT for actual wiring of PORT E */
6021                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
6022                 break;
6023         case PORT_F:
6024                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_F;
6025                 break;
6026         default:
6027                 MISSING_CASE(encoder->port);
6028         }
6029 }
6030
6031 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6032 {
6033         struct intel_connector *intel_connector;
6034         struct drm_connector *connector;
6035
6036         intel_connector = container_of(work, typeof(*intel_connector),
6037                                        modeset_retry_work);
6038         connector = &intel_connector->base;
6039         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6040                       connector->name);
6041
6042         /* Grab the locks before changing connector property*/
6043         mutex_lock(&connector->dev->mode_config.mutex);
6044         /* Set connector link status to BAD and send a Uevent to notify
6045          * userspace to do a modeset.
6046          */
6047         drm_mode_connector_set_link_status_property(connector,
6048                                                     DRM_MODE_LINK_STATUS_BAD);
6049         mutex_unlock(&connector->dev->mode_config.mutex);
6050         /* Send Hotplug uevent so userspace can reprobe */
6051         drm_kms_helper_hotplug_event(connector->dev);
6052 }
6053
6054 bool
6055 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6056                         struct intel_connector *intel_connector)
6057 {
6058         struct drm_connector *connector = &intel_connector->base;
6059         struct intel_dp *intel_dp = &intel_dig_port->dp;
6060         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6061         struct drm_device *dev = intel_encoder->base.dev;
6062         struct drm_i915_private *dev_priv = to_i915(dev);
6063         enum port port = intel_encoder->port;
6064         int type;
6065
6066         /* Initialize the work for modeset in case of link train failure */
6067         INIT_WORK(&intel_connector->modeset_retry_work,
6068                   intel_dp_modeset_retry_work_fn);
6069
6070         if (WARN(intel_dig_port->max_lanes < 1,
6071                  "Not enough lanes (%d) for DP on port %c\n",
6072                  intel_dig_port->max_lanes, port_name(port)))
6073                 return false;
6074
6075         intel_dp_set_source_rates(intel_dp);
6076
6077         intel_dp->reset_link_params = true;
6078         intel_dp->pps_pipe = INVALID_PIPE;
6079         intel_dp->active_pipe = INVALID_PIPE;
6080
6081         /* intel_dp vfuncs */
6082         if (INTEL_GEN(dev_priv) >= 9)
6083                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
6084         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6085                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6086         else if (HAS_PCH_SPLIT(dev_priv))
6087                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
6088         else
6089                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
6090
6091         if (INTEL_GEN(dev_priv) >= 9)
6092                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
6093         else
6094                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
6095
6096         if (HAS_DDI(dev_priv))
6097                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6098
6099         /* Preserve the current hw state. */
6100         intel_dp->DP = I915_READ(intel_dp->output_reg);
6101         intel_dp->attached_connector = intel_connector;
6102
6103         if (intel_dp_is_port_edp(dev_priv, port))
6104                 type = DRM_MODE_CONNECTOR_eDP;
6105         else
6106                 type = DRM_MODE_CONNECTOR_DisplayPort;
6107
6108         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6109                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6110
6111         /*
6112          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6113          * for DP the encoder type can be set by the caller to
6114          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6115          */
6116         if (type == DRM_MODE_CONNECTOR_eDP)
6117                 intel_encoder->type = INTEL_OUTPUT_EDP;
6118
6119         /* eDP only on port B and/or C on vlv/chv */
6120         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6121                     intel_dp_is_edp(intel_dp) &&
6122                     port != PORT_B && port != PORT_C))
6123                 return false;
6124
6125         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6126                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6127                         port_name(port));
6128
6129         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6130         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6131
6132         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
6133                 connector->interlace_allowed = true;
6134         connector->doublescan_allowed = 0;
6135
6136         intel_dp_init_connector_port_info(intel_dig_port);
6137
6138         intel_dp_aux_init(intel_dp);
6139
6140         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6141                           edp_panel_vdd_work);
6142
6143         intel_connector_attach_encoder(intel_connector, intel_encoder);
6144
6145         if (HAS_DDI(dev_priv))
6146                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6147         else
6148                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6149
6150         /* init MST on ports that can support it */
6151         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6152             (port == PORT_B || port == PORT_C ||
6153              port == PORT_D || port == PORT_F))
6154                 intel_dp_mst_encoder_init(intel_dig_port,
6155                                           intel_connector->base.base.id);
6156
6157         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6158                 intel_dp_aux_fini(intel_dp);
6159                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6160                 goto fail;
6161         }
6162
6163         intel_dp_add_properties(intel_dp, connector);
6164
6165         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6166          * 0xd.  Failure to do so will result in spurious interrupts being
6167          * generated on the port when a cable is not attached.
6168          */
6169         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6170                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6171                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6172         }
6173
6174         return true;
6175
6176 fail:
6177         drm_connector_cleanup(connector);
6178
6179         return false;
6180 }
6181
6182 bool intel_dp_init(struct drm_i915_private *dev_priv,
6183                    i915_reg_t output_reg,
6184                    enum port port)
6185 {
6186         struct intel_digital_port *intel_dig_port;
6187         struct intel_encoder *intel_encoder;
6188         struct drm_encoder *encoder;
6189         struct intel_connector *intel_connector;
6190
6191         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6192         if (!intel_dig_port)
6193                 return false;
6194
6195         intel_connector = intel_connector_alloc();
6196         if (!intel_connector)
6197                 goto err_connector_alloc;
6198
6199         intel_encoder = &intel_dig_port->base;
6200         encoder = &intel_encoder->base;
6201
6202         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6203                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6204                              "DP %c", port_name(port)))
6205                 goto err_encoder_init;
6206
6207         intel_encoder->compute_config = intel_dp_compute_config;
6208         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6209         intel_encoder->get_config = intel_dp_get_config;
6210         intel_encoder->suspend = intel_dp_encoder_suspend;
6211         if (IS_CHERRYVIEW(dev_priv)) {
6212                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6213                 intel_encoder->pre_enable = chv_pre_enable_dp;
6214                 intel_encoder->enable = vlv_enable_dp;
6215                 intel_encoder->disable = vlv_disable_dp;
6216                 intel_encoder->post_disable = chv_post_disable_dp;
6217                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6218         } else if (IS_VALLEYVIEW(dev_priv)) {
6219                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6220                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6221                 intel_encoder->enable = vlv_enable_dp;
6222                 intel_encoder->disable = vlv_disable_dp;
6223                 intel_encoder->post_disable = vlv_post_disable_dp;
6224         } else if (INTEL_GEN(dev_priv) >= 5) {
6225                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6226                 intel_encoder->enable = g4x_enable_dp;
6227                 intel_encoder->disable = ilk_disable_dp;
6228                 intel_encoder->post_disable = ilk_post_disable_dp;
6229         } else {
6230                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6231                 intel_encoder->enable = g4x_enable_dp;
6232                 intel_encoder->disable = g4x_disable_dp;
6233         }
6234
6235         intel_dig_port->dp.output_reg = output_reg;
6236         intel_dig_port->max_lanes = 4;
6237
6238         intel_encoder->type = INTEL_OUTPUT_DP;
6239         intel_encoder->power_domain = intel_port_to_power_domain(port);
6240         if (IS_CHERRYVIEW(dev_priv)) {
6241                 if (port == PORT_D)
6242                         intel_encoder->crtc_mask = 1 << 2;
6243                 else
6244                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6245         } else {
6246                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6247         }
6248         intel_encoder->cloneable = 0;
6249         intel_encoder->port = port;
6250
6251         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6252         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6253
6254         if (port != PORT_A)
6255                 intel_infoframe_init(intel_dig_port);
6256
6257         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6258                 goto err_init_connector;
6259
6260         return true;
6261
6262 err_init_connector:
6263         drm_encoder_cleanup(encoder);
6264 err_encoder_init:
6265         kfree(intel_connector);
6266 err_connector_alloc:
6267         kfree(intel_dig_port);
6268         return false;
6269 }
6270
6271 void intel_dp_mst_suspend(struct drm_device *dev)
6272 {
6273         struct drm_i915_private *dev_priv = to_i915(dev);
6274         int i;
6275
6276         /* disable MST */
6277         for (i = 0; i < I915_MAX_PORTS; i++) {
6278                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6279
6280                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6281                         continue;
6282
6283                 if (intel_dig_port->dp.is_mst)
6284                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6285         }
6286 }
6287
6288 void intel_dp_mst_resume(struct drm_device *dev)
6289 {
6290         struct drm_i915_private *dev_priv = to_i915(dev);
6291         int i;
6292
6293         for (i = 0; i < I915_MAX_PORTS; i++) {
6294                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6295                 int ret;
6296
6297                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6298                         continue;
6299
6300                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6301                 if (ret)
6302                         intel_dp_check_mst_status(&intel_dig_port->dp);
6303         }
6304 }