Merge drm/drm-next into drm-intel-next-queued
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Keith Packard <keithp@keithp.com>
25  *
26  */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
35 #include <drm/drm_atomic_helper.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_dp_helper.h>
38 #include <drm/drm_edid.h>
39 #include <drm/drm_hdcp.h>
40 #include <drm/drm_probe_helper.h>
41 #include "intel_drv.h"
42 #include <drm/i915_drm.h>
43 #include "i915_drv.h"
44
45 #define DP_DPRX_ESI_LEN 14
46
47 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
48 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER      61440
49 #define DP_DSC_MIN_SUPPORTED_BPC                8
50 #define DP_DSC_MAX_SUPPORTED_BPC                10
51
52 /* DP DSC throughput values used for slice count calculations KPixels/s */
53 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
54 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
55 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
56
57 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
58 #define DP_DSC_FEC_OVERHEAD_FACTOR              976
59
60 /* Compliance test status bits  */
61 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
62 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
63 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
64 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
65
66 struct dp_link_dpll {
67         int clock;
68         struct dpll dpll;
69 };
70
71 static const struct dp_link_dpll g4x_dpll[] = {
72         { 162000,
73                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
74         { 270000,
75                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
76 };
77
78 static const struct dp_link_dpll pch_dpll[] = {
79         { 162000,
80                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
81         { 270000,
82                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
83 };
84
85 static const struct dp_link_dpll vlv_dpll[] = {
86         { 162000,
87                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
88         { 270000,
89                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
90 };
91
92 /*
93  * CHV supports eDP 1.4 that have  more link rates.
94  * Below only provides the fixed rate but exclude variable rate.
95  */
96 static const struct dp_link_dpll chv_dpll[] = {
97         /*
98          * CHV requires to program fractional division for m2.
99          * m2 is stored in fixed point format using formula below
100          * (m2_int << 22) | m2_fraction
101          */
102         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
103                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
104         { 270000,       /* m2_int = 27, m2_fraction = 0 */
105                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
106 };
107
108 /* Constants for DP DSC configurations */
109 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
110
111 /* With Single pipe configuration, HW is capable of supporting maximum
112  * of 4 slices per line.
113  */
114 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
115
116 /**
117  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
118  * @intel_dp: DP struct
119  *
120  * If a CPU or PCH DP output is attached to an eDP panel, this function
121  * will return true, and false otherwise.
122  */
123 bool intel_dp_is_edp(struct intel_dp *intel_dp)
124 {
125         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
126
127         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
128 }
129
130 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
131 {
132         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
133 }
134
135 static void intel_dp_link_down(struct intel_encoder *encoder,
136                                const struct intel_crtc_state *old_crtc_state);
137 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
138 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
139 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
140                                            const struct intel_crtc_state *crtc_state);
141 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
142                                       enum pipe pipe);
143 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
144
145 /* update sink rates from dpcd */
146 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
147 {
148         static const int dp_rates[] = {
149                 162000, 270000, 540000, 810000
150         };
151         int i, max_rate;
152
153         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
154
155         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
156                 if (dp_rates[i] > max_rate)
157                         break;
158                 intel_dp->sink_rates[i] = dp_rates[i];
159         }
160
161         intel_dp->num_sink_rates = i;
162 }
163
164 /* Get length of rates array potentially limited by max_rate. */
165 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
166 {
167         int i;
168
169         /* Limit results by potentially reduced max rate */
170         for (i = 0; i < len; i++) {
171                 if (rates[len - i - 1] <= max_rate)
172                         return len - i;
173         }
174
175         return 0;
176 }
177
178 /* Get length of common rates array potentially limited by max_rate. */
179 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
180                                           int max_rate)
181 {
182         return intel_dp_rate_limit_len(intel_dp->common_rates,
183                                        intel_dp->num_common_rates, max_rate);
184 }
185
186 /* Theoretical max between source and sink */
187 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
188 {
189         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
190 }
191
192 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
193 {
194         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
195         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
196         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
197         u32 lane_info;
198
199         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
200                 return 4;
201
202         lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
203                      DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
204                     DP_LANE_ASSIGNMENT_SHIFT(tc_port);
205
206         switch (lane_info) {
207         default:
208                 MISSING_CASE(lane_info);
209         case 1:
210         case 2:
211         case 4:
212         case 8:
213                 return 1;
214         case 3:
215         case 12:
216                 return 2;
217         case 15:
218                 return 4;
219         }
220 }
221
222 /* Theoretical max between source and sink */
223 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
224 {
225         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
226         int source_max = intel_dig_port->max_lanes;
227         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
228         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
229
230         return min3(source_max, sink_max, fia_max);
231 }
232
233 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
234 {
235         return intel_dp->max_link_lane_count;
236 }
237
238 int
239 intel_dp_link_required(int pixel_clock, int bpp)
240 {
241         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
242         return DIV_ROUND_UP(pixel_clock * bpp, 8);
243 }
244
245 int
246 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
247 {
248         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
249          * link rate that is generally expressed in Gbps. Since, 8 bits of data
250          * is transmitted every LS_Clk per lane, there is no need to account for
251          * the channel encoding that is done in the PHY layer here.
252          */
253
254         return max_link_clock * max_lanes;
255 }
256
257 static int
258 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
259 {
260         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
261         struct intel_encoder *encoder = &intel_dig_port->base;
262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
263         int max_dotclk = dev_priv->max_dotclk_freq;
264         int ds_max_dotclk;
265
266         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
267
268         if (type != DP_DS_PORT_TYPE_VGA)
269                 return max_dotclk;
270
271         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
272                                                     intel_dp->downstream_ports);
273
274         if (ds_max_dotclk != 0)
275                 max_dotclk = min(max_dotclk, ds_max_dotclk);
276
277         return max_dotclk;
278 }
279
280 static int cnl_max_source_rate(struct intel_dp *intel_dp)
281 {
282         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
283         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
284         enum port port = dig_port->base.port;
285
286         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
287
288         /* Low voltage SKUs are limited to max of 5.4G */
289         if (voltage == VOLTAGE_INFO_0_85V)
290                 return 540000;
291
292         /* For this SKU 8.1G is supported in all ports */
293         if (IS_CNL_WITH_PORT_F(dev_priv))
294                 return 810000;
295
296         /* For other SKUs, max rate on ports A and D is 5.4G */
297         if (port == PORT_A || port == PORT_D)
298                 return 540000;
299
300         return 810000;
301 }
302
303 static int icl_max_source_rate(struct intel_dp *intel_dp)
304 {
305         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
306         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
307         enum port port = dig_port->base.port;
308
309         if (intel_port_is_combophy(dev_priv, port) &&
310             !intel_dp_is_edp(intel_dp))
311                 return 540000;
312
313         return 810000;
314 }
315
316 static void
317 intel_dp_set_source_rates(struct intel_dp *intel_dp)
318 {
319         /* The values must be in increasing order */
320         static const int cnl_rates[] = {
321                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
322         };
323         static const int bxt_rates[] = {
324                 162000, 216000, 243000, 270000, 324000, 432000, 540000
325         };
326         static const int skl_rates[] = {
327                 162000, 216000, 270000, 324000, 432000, 540000
328         };
329         static const int hsw_rates[] = {
330                 162000, 270000, 540000
331         };
332         static const int g4x_rates[] = {
333                 162000, 270000
334         };
335         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
336         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
337         const struct ddi_vbt_port_info *info =
338                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
339         const int *source_rates;
340         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
341
342         /* This should only be done once */
343         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
344
345         if (INTEL_GEN(dev_priv) >= 10) {
346                 source_rates = cnl_rates;
347                 size = ARRAY_SIZE(cnl_rates);
348                 if (IS_GEN(dev_priv, 10))
349                         max_rate = cnl_max_source_rate(intel_dp);
350                 else
351                         max_rate = icl_max_source_rate(intel_dp);
352         } else if (IS_GEN9_LP(dev_priv)) {
353                 source_rates = bxt_rates;
354                 size = ARRAY_SIZE(bxt_rates);
355         } else if (IS_GEN9_BC(dev_priv)) {
356                 source_rates = skl_rates;
357                 size = ARRAY_SIZE(skl_rates);
358         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
359                    IS_BROADWELL(dev_priv)) {
360                 source_rates = hsw_rates;
361                 size = ARRAY_SIZE(hsw_rates);
362         } else {
363                 source_rates = g4x_rates;
364                 size = ARRAY_SIZE(g4x_rates);
365         }
366
367         if (max_rate && vbt_max_rate)
368                 max_rate = min(max_rate, vbt_max_rate);
369         else if (vbt_max_rate)
370                 max_rate = vbt_max_rate;
371
372         if (max_rate)
373                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
374
375         intel_dp->source_rates = source_rates;
376         intel_dp->num_source_rates = size;
377 }
378
379 static int intersect_rates(const int *source_rates, int source_len,
380                            const int *sink_rates, int sink_len,
381                            int *common_rates)
382 {
383         int i = 0, j = 0, k = 0;
384
385         while (i < source_len && j < sink_len) {
386                 if (source_rates[i] == sink_rates[j]) {
387                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
388                                 return k;
389                         common_rates[k] = source_rates[i];
390                         ++k;
391                         ++i;
392                         ++j;
393                 } else if (source_rates[i] < sink_rates[j]) {
394                         ++i;
395                 } else {
396                         ++j;
397                 }
398         }
399         return k;
400 }
401
402 /* return index of rate in rates array, or -1 if not found */
403 static int intel_dp_rate_index(const int *rates, int len, int rate)
404 {
405         int i;
406
407         for (i = 0; i < len; i++)
408                 if (rate == rates[i])
409                         return i;
410
411         return -1;
412 }
413
414 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
415 {
416         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
417
418         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
419                                                      intel_dp->num_source_rates,
420                                                      intel_dp->sink_rates,
421                                                      intel_dp->num_sink_rates,
422                                                      intel_dp->common_rates);
423
424         /* Paranoia, there should always be something in common. */
425         if (WARN_ON(intel_dp->num_common_rates == 0)) {
426                 intel_dp->common_rates[0] = 162000;
427                 intel_dp->num_common_rates = 1;
428         }
429 }
430
431 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
432                                        u8 lane_count)
433 {
434         /*
435          * FIXME: we need to synchronize the current link parameters with
436          * hardware readout. Currently fast link training doesn't work on
437          * boot-up.
438          */
439         if (link_rate == 0 ||
440             link_rate > intel_dp->max_link_rate)
441                 return false;
442
443         if (lane_count == 0 ||
444             lane_count > intel_dp_max_lane_count(intel_dp))
445                 return false;
446
447         return true;
448 }
449
450 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
451                                                      int link_rate,
452                                                      u8 lane_count)
453 {
454         const struct drm_display_mode *fixed_mode =
455                 intel_dp->attached_connector->panel.fixed_mode;
456         int mode_rate, max_rate;
457
458         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
459         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
460         if (mode_rate > max_rate)
461                 return false;
462
463         return true;
464 }
465
466 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
467                                             int link_rate, u8 lane_count)
468 {
469         int index;
470
471         index = intel_dp_rate_index(intel_dp->common_rates,
472                                     intel_dp->num_common_rates,
473                                     link_rate);
474         if (index > 0) {
475                 if (intel_dp_is_edp(intel_dp) &&
476                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
477                                                               intel_dp->common_rates[index - 1],
478                                                               lane_count)) {
479                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
480                         return 0;
481                 }
482                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
483                 intel_dp->max_link_lane_count = lane_count;
484         } else if (lane_count > 1) {
485                 if (intel_dp_is_edp(intel_dp) &&
486                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
487                                                               intel_dp_max_common_rate(intel_dp),
488                                                               lane_count >> 1)) {
489                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
490                         return 0;
491                 }
492                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
493                 intel_dp->max_link_lane_count = lane_count >> 1;
494         } else {
495                 DRM_ERROR("Link Training Unsuccessful\n");
496                 return -1;
497         }
498
499         return 0;
500 }
501
502 static enum drm_mode_status
503 intel_dp_mode_valid(struct drm_connector *connector,
504                     struct drm_display_mode *mode)
505 {
506         struct intel_dp *intel_dp = intel_attached_dp(connector);
507         struct intel_connector *intel_connector = to_intel_connector(connector);
508         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
509         struct drm_i915_private *dev_priv = to_i915(connector->dev);
510         int target_clock = mode->clock;
511         int max_rate, mode_rate, max_lanes, max_link_clock;
512         int max_dotclk;
513         u16 dsc_max_output_bpp = 0;
514         u8 dsc_slice_count = 0;
515
516         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
517                 return MODE_NO_DBLESCAN;
518
519         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
520
521         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
522                 if (mode->hdisplay > fixed_mode->hdisplay)
523                         return MODE_PANEL;
524
525                 if (mode->vdisplay > fixed_mode->vdisplay)
526                         return MODE_PANEL;
527
528                 target_clock = fixed_mode->clock;
529         }
530
531         max_link_clock = intel_dp_max_link_rate(intel_dp);
532         max_lanes = intel_dp_max_lane_count(intel_dp);
533
534         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
535         mode_rate = intel_dp_link_required(target_clock, 18);
536
537         /*
538          * Output bpp is stored in 6.4 format so right shift by 4 to get the
539          * integer value since we support only integer values of bpp.
540          */
541         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
542             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
543                 if (intel_dp_is_edp(intel_dp)) {
544                         dsc_max_output_bpp =
545                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
546                         dsc_slice_count =
547                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
548                                                                 true);
549                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
550                         dsc_max_output_bpp =
551                                 intel_dp_dsc_get_output_bpp(max_link_clock,
552                                                             max_lanes,
553                                                             target_clock,
554                                                             mode->hdisplay) >> 4;
555                         dsc_slice_count =
556                                 intel_dp_dsc_get_slice_count(intel_dp,
557                                                              target_clock,
558                                                              mode->hdisplay);
559                 }
560         }
561
562         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
563             target_clock > max_dotclk)
564                 return MODE_CLOCK_HIGH;
565
566         if (mode->clock < 10000)
567                 return MODE_CLOCK_LOW;
568
569         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
570                 return MODE_H_ILLEGAL;
571
572         return MODE_OK;
573 }
574
575 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
576 {
577         int i;
578         u32 v = 0;
579
580         if (src_bytes > 4)
581                 src_bytes = 4;
582         for (i = 0; i < src_bytes; i++)
583                 v |= ((u32)src[i]) << ((3 - i) * 8);
584         return v;
585 }
586
587 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
588 {
589         int i;
590         if (dst_bytes > 4)
591                 dst_bytes = 4;
592         for (i = 0; i < dst_bytes; i++)
593                 dst[i] = src >> ((3-i) * 8);
594 }
595
596 static void
597 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
598 static void
599 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
600                                               bool force_disable_vdd);
601 static void
602 intel_dp_pps_init(struct intel_dp *intel_dp);
603
604 static intel_wakeref_t
605 pps_lock(struct intel_dp *intel_dp)
606 {
607         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
608         intel_wakeref_t wakeref;
609
610         /*
611          * See intel_power_sequencer_reset() why we need
612          * a power domain reference here.
613          */
614         wakeref = intel_display_power_get(dev_priv,
615                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
616
617         mutex_lock(&dev_priv->pps_mutex);
618
619         return wakeref;
620 }
621
622 static intel_wakeref_t
623 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
624 {
625         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
626
627         mutex_unlock(&dev_priv->pps_mutex);
628         intel_display_power_put(dev_priv,
629                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
630                                 wakeref);
631         return 0;
632 }
633
634 #define with_pps_lock(dp, wf) \
635         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
636
637 static void
638 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
639 {
640         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
641         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
642         enum pipe pipe = intel_dp->pps_pipe;
643         bool pll_enabled, release_cl_override = false;
644         enum dpio_phy phy = DPIO_PHY(pipe);
645         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
646         u32 DP;
647
648         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
649                  "skipping pipe %c power sequencer kick due to port %c being active\n",
650                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
651                 return;
652
653         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
654                       pipe_name(pipe), port_name(intel_dig_port->base.port));
655
656         /* Preserve the BIOS-computed detected bit. This is
657          * supposed to be read-only.
658          */
659         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
660         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
661         DP |= DP_PORT_WIDTH(1);
662         DP |= DP_LINK_TRAIN_PAT_1;
663
664         if (IS_CHERRYVIEW(dev_priv))
665                 DP |= DP_PIPE_SEL_CHV(pipe);
666         else
667                 DP |= DP_PIPE_SEL(pipe);
668
669         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
670
671         /*
672          * The DPLL for the pipe must be enabled for this to work.
673          * So enable temporarily it if it's not already enabled.
674          */
675         if (!pll_enabled) {
676                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
677                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
678
679                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
680                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
681                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
682                                   pipe_name(pipe));
683                         return;
684                 }
685         }
686
687         /*
688          * Similar magic as in intel_dp_enable_port().
689          * We _must_ do this port enable + disable trick
690          * to make this power sequencer lock onto the port.
691          * Otherwise even VDD force bit won't work.
692          */
693         I915_WRITE(intel_dp->output_reg, DP);
694         POSTING_READ(intel_dp->output_reg);
695
696         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
697         POSTING_READ(intel_dp->output_reg);
698
699         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
700         POSTING_READ(intel_dp->output_reg);
701
702         if (!pll_enabled) {
703                 vlv_force_pll_off(dev_priv, pipe);
704
705                 if (release_cl_override)
706                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
707         }
708 }
709
710 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
711 {
712         struct intel_encoder *encoder;
713         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
714
715         /*
716          * We don't have power sequencer currently.
717          * Pick one that's not used by other ports.
718          */
719         for_each_intel_dp(&dev_priv->drm, encoder) {
720                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
721
722                 if (encoder->type == INTEL_OUTPUT_EDP) {
723                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
724                                 intel_dp->active_pipe != intel_dp->pps_pipe);
725
726                         if (intel_dp->pps_pipe != INVALID_PIPE)
727                                 pipes &= ~(1 << intel_dp->pps_pipe);
728                 } else {
729                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
730
731                         if (intel_dp->active_pipe != INVALID_PIPE)
732                                 pipes &= ~(1 << intel_dp->active_pipe);
733                 }
734         }
735
736         if (pipes == 0)
737                 return INVALID_PIPE;
738
739         return ffs(pipes) - 1;
740 }
741
742 static enum pipe
743 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
744 {
745         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
746         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
747         enum pipe pipe;
748
749         lockdep_assert_held(&dev_priv->pps_mutex);
750
751         /* We should never land here with regular DP ports */
752         WARN_ON(!intel_dp_is_edp(intel_dp));
753
754         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
755                 intel_dp->active_pipe != intel_dp->pps_pipe);
756
757         if (intel_dp->pps_pipe != INVALID_PIPE)
758                 return intel_dp->pps_pipe;
759
760         pipe = vlv_find_free_pps(dev_priv);
761
762         /*
763          * Didn't find one. This should not happen since there
764          * are two power sequencers and up to two eDP ports.
765          */
766         if (WARN_ON(pipe == INVALID_PIPE))
767                 pipe = PIPE_A;
768
769         vlv_steal_power_sequencer(dev_priv, pipe);
770         intel_dp->pps_pipe = pipe;
771
772         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
773                       pipe_name(intel_dp->pps_pipe),
774                       port_name(intel_dig_port->base.port));
775
776         /* init power sequencer on this pipe and port */
777         intel_dp_init_panel_power_sequencer(intel_dp);
778         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
779
780         /*
781          * Even vdd force doesn't work until we've made
782          * the power sequencer lock in on the port.
783          */
784         vlv_power_sequencer_kick(intel_dp);
785
786         return intel_dp->pps_pipe;
787 }
788
789 static int
790 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
791 {
792         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
793         int backlight_controller = dev_priv->vbt.backlight.controller;
794
795         lockdep_assert_held(&dev_priv->pps_mutex);
796
797         /* We should never land here with regular DP ports */
798         WARN_ON(!intel_dp_is_edp(intel_dp));
799
800         if (!intel_dp->pps_reset)
801                 return backlight_controller;
802
803         intel_dp->pps_reset = false;
804
805         /*
806          * Only the HW needs to be reprogrammed, the SW state is fixed and
807          * has been setup during connector init.
808          */
809         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
810
811         return backlight_controller;
812 }
813
814 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
815                                enum pipe pipe);
816
817 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
818                                enum pipe pipe)
819 {
820         return I915_READ(PP_STATUS(pipe)) & PP_ON;
821 }
822
823 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
824                                 enum pipe pipe)
825 {
826         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
827 }
828
829 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
830                          enum pipe pipe)
831 {
832         return true;
833 }
834
835 static enum pipe
836 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
837                      enum port port,
838                      vlv_pipe_check pipe_check)
839 {
840         enum pipe pipe;
841
842         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
843                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
844                         PANEL_PORT_SELECT_MASK;
845
846                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
847                         continue;
848
849                 if (!pipe_check(dev_priv, pipe))
850                         continue;
851
852                 return pipe;
853         }
854
855         return INVALID_PIPE;
856 }
857
858 static void
859 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
860 {
861         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
862         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
863         enum port port = intel_dig_port->base.port;
864
865         lockdep_assert_held(&dev_priv->pps_mutex);
866
867         /* try to find a pipe with this port selected */
868         /* first pick one where the panel is on */
869         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
870                                                   vlv_pipe_has_pp_on);
871         /* didn't find one? pick one where vdd is on */
872         if (intel_dp->pps_pipe == INVALID_PIPE)
873                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
874                                                           vlv_pipe_has_vdd_on);
875         /* didn't find one? pick one with just the correct port */
876         if (intel_dp->pps_pipe == INVALID_PIPE)
877                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
878                                                           vlv_pipe_any);
879
880         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
881         if (intel_dp->pps_pipe == INVALID_PIPE) {
882                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
883                               port_name(port));
884                 return;
885         }
886
887         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
888                       port_name(port), pipe_name(intel_dp->pps_pipe));
889
890         intel_dp_init_panel_power_sequencer(intel_dp);
891         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
892 }
893
894 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
895 {
896         struct intel_encoder *encoder;
897
898         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
899                     !IS_GEN9_LP(dev_priv)))
900                 return;
901
902         /*
903          * We can't grab pps_mutex here due to deadlock with power_domain
904          * mutex when power_domain functions are called while holding pps_mutex.
905          * That also means that in order to use pps_pipe the code needs to
906          * hold both a power domain reference and pps_mutex, and the power domain
907          * reference get/put must be done while _not_ holding pps_mutex.
908          * pps_{lock,unlock}() do these steps in the correct order, so one
909          * should use them always.
910          */
911
912         for_each_intel_dp(&dev_priv->drm, encoder) {
913                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
914
915                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
916
917                 if (encoder->type != INTEL_OUTPUT_EDP)
918                         continue;
919
920                 if (IS_GEN9_LP(dev_priv))
921                         intel_dp->pps_reset = true;
922                 else
923                         intel_dp->pps_pipe = INVALID_PIPE;
924         }
925 }
926
927 struct pps_registers {
928         i915_reg_t pp_ctrl;
929         i915_reg_t pp_stat;
930         i915_reg_t pp_on;
931         i915_reg_t pp_off;
932         i915_reg_t pp_div;
933 };
934
935 static void intel_pps_get_registers(struct intel_dp *intel_dp,
936                                     struct pps_registers *regs)
937 {
938         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
939         int pps_idx = 0;
940
941         memset(regs, 0, sizeof(*regs));
942
943         if (IS_GEN9_LP(dev_priv))
944                 pps_idx = bxt_power_sequencer_idx(intel_dp);
945         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
946                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
947
948         regs->pp_ctrl = PP_CONTROL(pps_idx);
949         regs->pp_stat = PP_STATUS(pps_idx);
950         regs->pp_on = PP_ON_DELAYS(pps_idx);
951         regs->pp_off = PP_OFF_DELAYS(pps_idx);
952
953         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
954         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
955                 regs->pp_div = INVALID_MMIO_REG;
956         else
957                 regs->pp_div = PP_DIVISOR(pps_idx);
958 }
959
960 static i915_reg_t
961 _pp_ctrl_reg(struct intel_dp *intel_dp)
962 {
963         struct pps_registers regs;
964
965         intel_pps_get_registers(intel_dp, &regs);
966
967         return regs.pp_ctrl;
968 }
969
970 static i915_reg_t
971 _pp_stat_reg(struct intel_dp *intel_dp)
972 {
973         struct pps_registers regs;
974
975         intel_pps_get_registers(intel_dp, &regs);
976
977         return regs.pp_stat;
978 }
979
980 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
981    This function only applicable when panel PM state is not to be tracked */
982 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
983                               void *unused)
984 {
985         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
986                                                  edp_notifier);
987         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
988         intel_wakeref_t wakeref;
989
990         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
991                 return 0;
992
993         with_pps_lock(intel_dp, wakeref) {
994                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
995                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
996                         i915_reg_t pp_ctrl_reg, pp_div_reg;
997                         u32 pp_div;
998
999                         pp_ctrl_reg = PP_CONTROL(pipe);
1000                         pp_div_reg  = PP_DIVISOR(pipe);
1001                         pp_div = I915_READ(pp_div_reg);
1002                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1003
1004                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1005                         I915_WRITE(pp_div_reg, pp_div | 0x1F);
1006                         I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
1007                         msleep(intel_dp->panel_power_cycle_delay);
1008                 }
1009         }
1010
1011         return 0;
1012 }
1013
1014 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1015 {
1016         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1017
1018         lockdep_assert_held(&dev_priv->pps_mutex);
1019
1020         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1021             intel_dp->pps_pipe == INVALID_PIPE)
1022                 return false;
1023
1024         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1025 }
1026
1027 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1028 {
1029         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1030
1031         lockdep_assert_held(&dev_priv->pps_mutex);
1032
1033         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1034             intel_dp->pps_pipe == INVALID_PIPE)
1035                 return false;
1036
1037         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1038 }
1039
1040 static void
1041 intel_dp_check_edp(struct intel_dp *intel_dp)
1042 {
1043         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1044
1045         if (!intel_dp_is_edp(intel_dp))
1046                 return;
1047
1048         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1049                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1050                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1051                               I915_READ(_pp_stat_reg(intel_dp)),
1052                               I915_READ(_pp_ctrl_reg(intel_dp)));
1053         }
1054 }
1055
1056 static u32
1057 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1058 {
1059         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1060         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1061         u32 status;
1062         bool done;
1063
1064 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1065         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1066                                   msecs_to_jiffies_timeout(10));
1067
1068         /* just trace the final value */
1069         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1070
1071         if (!done)
1072                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1073 #undef C
1074
1075         return status;
1076 }
1077
1078 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1079 {
1080         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1081
1082         if (index)
1083                 return 0;
1084
1085         /*
1086          * The clock divider is based off the hrawclk, and would like to run at
1087          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1088          */
1089         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1090 }
1091
1092 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1093 {
1094         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1095         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1096
1097         if (index)
1098                 return 0;
1099
1100         /*
1101          * The clock divider is based off the cdclk or PCH rawclk, and would
1102          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1103          * divide by 2000 and use that
1104          */
1105         if (dig_port->aux_ch == AUX_CH_A)
1106                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1107         else
1108                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1109 }
1110
1111 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1112 {
1113         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1114         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1115
1116         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1117                 /* Workaround for non-ULT HSW */
1118                 switch (index) {
1119                 case 0: return 63;
1120                 case 1: return 72;
1121                 default: return 0;
1122                 }
1123         }
1124
1125         return ilk_get_aux_clock_divider(intel_dp, index);
1126 }
1127
1128 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1129 {
1130         /*
1131          * SKL doesn't need us to program the AUX clock divider (Hardware will
1132          * derive the clock from CDCLK automatically). We still implement the
1133          * get_aux_clock_divider vfunc to plug-in into the existing code.
1134          */
1135         return index ? 0 : 1;
1136 }
1137
1138 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1139                                 int send_bytes,
1140                                 u32 aux_clock_divider)
1141 {
1142         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1143         struct drm_i915_private *dev_priv =
1144                         to_i915(intel_dig_port->base.base.dev);
1145         u32 precharge, timeout;
1146
1147         if (IS_GEN(dev_priv, 6))
1148                 precharge = 3;
1149         else
1150                 precharge = 5;
1151
1152         if (IS_BROADWELL(dev_priv))
1153                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1154         else
1155                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1156
1157         return DP_AUX_CH_CTL_SEND_BUSY |
1158                DP_AUX_CH_CTL_DONE |
1159                DP_AUX_CH_CTL_INTERRUPT |
1160                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1161                timeout |
1162                DP_AUX_CH_CTL_RECEIVE_ERROR |
1163                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1164                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1165                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1166 }
1167
1168 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1169                                 int send_bytes,
1170                                 u32 unused)
1171 {
1172         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1173         u32 ret;
1174
1175         ret = DP_AUX_CH_CTL_SEND_BUSY |
1176               DP_AUX_CH_CTL_DONE |
1177               DP_AUX_CH_CTL_INTERRUPT |
1178               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1179               DP_AUX_CH_CTL_TIME_OUT_MAX |
1180               DP_AUX_CH_CTL_RECEIVE_ERROR |
1181               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1182               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1183               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1184
1185         if (intel_dig_port->tc_type == TC_PORT_TBT)
1186                 ret |= DP_AUX_CH_CTL_TBT_IO;
1187
1188         return ret;
1189 }
1190
1191 static int
1192 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1193                   const u8 *send, int send_bytes,
1194                   u8 *recv, int recv_size,
1195                   u32 aux_send_ctl_flags)
1196 {
1197         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1198         struct drm_i915_private *dev_priv =
1199                         to_i915(intel_dig_port->base.base.dev);
1200         i915_reg_t ch_ctl, ch_data[5];
1201         u32 aux_clock_divider;
1202         intel_wakeref_t wakeref;
1203         int i, ret, recv_bytes;
1204         int try, clock = 0;
1205         u32 status;
1206         bool vdd;
1207
1208         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1209         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1210                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1211
1212         wakeref = pps_lock(intel_dp);
1213
1214         /*
1215          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1216          * In such cases we want to leave VDD enabled and it's up to upper layers
1217          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1218          * ourselves.
1219          */
1220         vdd = edp_panel_vdd_on(intel_dp);
1221
1222         /* dp aux is extremely sensitive to irq latency, hence request the
1223          * lowest possible wakeup latency and so prevent the cpu from going into
1224          * deep sleep states.
1225          */
1226         pm_qos_update_request(&dev_priv->pm_qos, 0);
1227
1228         intel_dp_check_edp(intel_dp);
1229
1230         /* Try to wait for any previous AUX channel activity */
1231         for (try = 0; try < 3; try++) {
1232                 status = I915_READ_NOTRACE(ch_ctl);
1233                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1234                         break;
1235                 msleep(1);
1236         }
1237         /* just trace the final value */
1238         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1239
1240         if (try == 3) {
1241                 static u32 last_status = -1;
1242                 const u32 status = I915_READ(ch_ctl);
1243
1244                 if (status != last_status) {
1245                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1246                              status);
1247                         last_status = status;
1248                 }
1249
1250                 ret = -EBUSY;
1251                 goto out;
1252         }
1253
1254         /* Only 5 data registers! */
1255         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1256                 ret = -E2BIG;
1257                 goto out;
1258         }
1259
1260         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1261                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1262                                                           send_bytes,
1263                                                           aux_clock_divider);
1264
1265                 send_ctl |= aux_send_ctl_flags;
1266
1267                 /* Must try at least 3 times according to DP spec */
1268                 for (try = 0; try < 5; try++) {
1269                         /* Load the send data into the aux channel data registers */
1270                         for (i = 0; i < send_bytes; i += 4)
1271                                 I915_WRITE(ch_data[i >> 2],
1272                                            intel_dp_pack_aux(send + i,
1273                                                              send_bytes - i));
1274
1275                         /* Send the command and wait for it to complete */
1276                         I915_WRITE(ch_ctl, send_ctl);
1277
1278                         status = intel_dp_aux_wait_done(intel_dp);
1279
1280                         /* Clear done status and any errors */
1281                         I915_WRITE(ch_ctl,
1282                                    status |
1283                                    DP_AUX_CH_CTL_DONE |
1284                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1285                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1286
1287                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1288                          *   400us delay required for errors and timeouts
1289                          *   Timeout errors from the HW already meet this
1290                          *   requirement so skip to next iteration
1291                          */
1292                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1293                                 continue;
1294
1295                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1296                                 usleep_range(400, 500);
1297                                 continue;
1298                         }
1299                         if (status & DP_AUX_CH_CTL_DONE)
1300                                 goto done;
1301                 }
1302         }
1303
1304         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1305                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1306                 ret = -EBUSY;
1307                 goto out;
1308         }
1309
1310 done:
1311         /* Check for timeout or receive error.
1312          * Timeouts occur when the sink is not connected
1313          */
1314         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1315                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1316                 ret = -EIO;
1317                 goto out;
1318         }
1319
1320         /* Timeouts occur when the device isn't connected, so they're
1321          * "normal" -- don't fill the kernel log with these */
1322         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1323                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1324                 ret = -ETIMEDOUT;
1325                 goto out;
1326         }
1327
1328         /* Unload any bytes sent back from the other side */
1329         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1330                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1331
1332         /*
1333          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1334          * We have no idea of what happened so we return -EBUSY so
1335          * drm layer takes care for the necessary retries.
1336          */
1337         if (recv_bytes == 0 || recv_bytes > 20) {
1338                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1339                               recv_bytes);
1340                 ret = -EBUSY;
1341                 goto out;
1342         }
1343
1344         if (recv_bytes > recv_size)
1345                 recv_bytes = recv_size;
1346
1347         for (i = 0; i < recv_bytes; i += 4)
1348                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1349                                     recv + i, recv_bytes - i);
1350
1351         ret = recv_bytes;
1352 out:
1353         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1354
1355         if (vdd)
1356                 edp_panel_vdd_off(intel_dp, false);
1357
1358         pps_unlock(intel_dp, wakeref);
1359
1360         return ret;
1361 }
1362
1363 #define BARE_ADDRESS_SIZE       3
1364 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1365
1366 static void
1367 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1368                     const struct drm_dp_aux_msg *msg)
1369 {
1370         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1371         txbuf[1] = (msg->address >> 8) & 0xff;
1372         txbuf[2] = msg->address & 0xff;
1373         txbuf[3] = msg->size - 1;
1374 }
1375
1376 static ssize_t
1377 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1378 {
1379         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1380         u8 txbuf[20], rxbuf[20];
1381         size_t txsize, rxsize;
1382         int ret;
1383
1384         intel_dp_aux_header(txbuf, msg);
1385
1386         switch (msg->request & ~DP_AUX_I2C_MOT) {
1387         case DP_AUX_NATIVE_WRITE:
1388         case DP_AUX_I2C_WRITE:
1389         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1390                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1391                 rxsize = 2; /* 0 or 1 data bytes */
1392
1393                 if (WARN_ON(txsize > 20))
1394                         return -E2BIG;
1395
1396                 WARN_ON(!msg->buffer != !msg->size);
1397
1398                 if (msg->buffer)
1399                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1400
1401                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1402                                         rxbuf, rxsize, 0);
1403                 if (ret > 0) {
1404                         msg->reply = rxbuf[0] >> 4;
1405
1406                         if (ret > 1) {
1407                                 /* Number of bytes written in a short write. */
1408                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1409                         } else {
1410                                 /* Return payload size. */
1411                                 ret = msg->size;
1412                         }
1413                 }
1414                 break;
1415
1416         case DP_AUX_NATIVE_READ:
1417         case DP_AUX_I2C_READ:
1418                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1419                 rxsize = msg->size + 1;
1420
1421                 if (WARN_ON(rxsize > 20))
1422                         return -E2BIG;
1423
1424                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1425                                         rxbuf, rxsize, 0);
1426                 if (ret > 0) {
1427                         msg->reply = rxbuf[0] >> 4;
1428                         /*
1429                          * Assume happy day, and copy the data. The caller is
1430                          * expected to check msg->reply before touching it.
1431                          *
1432                          * Return payload size.
1433                          */
1434                         ret--;
1435                         memcpy(msg->buffer, rxbuf + 1, ret);
1436                 }
1437                 break;
1438
1439         default:
1440                 ret = -EINVAL;
1441                 break;
1442         }
1443
1444         return ret;
1445 }
1446
1447
1448 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1449 {
1450         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1451         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1452         enum aux_ch aux_ch = dig_port->aux_ch;
1453
1454         switch (aux_ch) {
1455         case AUX_CH_B:
1456         case AUX_CH_C:
1457         case AUX_CH_D:
1458                 return DP_AUX_CH_CTL(aux_ch);
1459         default:
1460                 MISSING_CASE(aux_ch);
1461                 return DP_AUX_CH_CTL(AUX_CH_B);
1462         }
1463 }
1464
1465 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1466 {
1467         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1468         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1469         enum aux_ch aux_ch = dig_port->aux_ch;
1470
1471         switch (aux_ch) {
1472         case AUX_CH_B:
1473         case AUX_CH_C:
1474         case AUX_CH_D:
1475                 return DP_AUX_CH_DATA(aux_ch, index);
1476         default:
1477                 MISSING_CASE(aux_ch);
1478                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1479         }
1480 }
1481
1482 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1483 {
1484         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1485         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1486         enum aux_ch aux_ch = dig_port->aux_ch;
1487
1488         switch (aux_ch) {
1489         case AUX_CH_A:
1490                 return DP_AUX_CH_CTL(aux_ch);
1491         case AUX_CH_B:
1492         case AUX_CH_C:
1493         case AUX_CH_D:
1494                 return PCH_DP_AUX_CH_CTL(aux_ch);
1495         default:
1496                 MISSING_CASE(aux_ch);
1497                 return DP_AUX_CH_CTL(AUX_CH_A);
1498         }
1499 }
1500
1501 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1502 {
1503         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1504         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1505         enum aux_ch aux_ch = dig_port->aux_ch;
1506
1507         switch (aux_ch) {
1508         case AUX_CH_A:
1509                 return DP_AUX_CH_DATA(aux_ch, index);
1510         case AUX_CH_B:
1511         case AUX_CH_C:
1512         case AUX_CH_D:
1513                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1514         default:
1515                 MISSING_CASE(aux_ch);
1516                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1517         }
1518 }
1519
1520 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1521 {
1522         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1523         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1524         enum aux_ch aux_ch = dig_port->aux_ch;
1525
1526         switch (aux_ch) {
1527         case AUX_CH_A:
1528         case AUX_CH_B:
1529         case AUX_CH_C:
1530         case AUX_CH_D:
1531         case AUX_CH_E:
1532         case AUX_CH_F:
1533                 return DP_AUX_CH_CTL(aux_ch);
1534         default:
1535                 MISSING_CASE(aux_ch);
1536                 return DP_AUX_CH_CTL(AUX_CH_A);
1537         }
1538 }
1539
1540 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1541 {
1542         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1543         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1544         enum aux_ch aux_ch = dig_port->aux_ch;
1545
1546         switch (aux_ch) {
1547         case AUX_CH_A:
1548         case AUX_CH_B:
1549         case AUX_CH_C:
1550         case AUX_CH_D:
1551         case AUX_CH_E:
1552         case AUX_CH_F:
1553                 return DP_AUX_CH_DATA(aux_ch, index);
1554         default:
1555                 MISSING_CASE(aux_ch);
1556                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1557         }
1558 }
1559
1560 static void
1561 intel_dp_aux_fini(struct intel_dp *intel_dp)
1562 {
1563         kfree(intel_dp->aux.name);
1564 }
1565
1566 static void
1567 intel_dp_aux_init(struct intel_dp *intel_dp)
1568 {
1569         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1570         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1571         struct intel_encoder *encoder = &dig_port->base;
1572
1573         if (INTEL_GEN(dev_priv) >= 9) {
1574                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1575                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1576         } else if (HAS_PCH_SPLIT(dev_priv)) {
1577                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1578                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1579         } else {
1580                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1581                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1582         }
1583
1584         if (INTEL_GEN(dev_priv) >= 9)
1585                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1586         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1587                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1588         else if (HAS_PCH_SPLIT(dev_priv))
1589                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1590         else
1591                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1592
1593         if (INTEL_GEN(dev_priv) >= 9)
1594                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1595         else
1596                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1597
1598         drm_dp_aux_init(&intel_dp->aux);
1599
1600         /* Failure to allocate our preferred name is not critical */
1601         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1602                                        port_name(encoder->port));
1603         intel_dp->aux.transfer = intel_dp_aux_transfer;
1604 }
1605
1606 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1607 {
1608         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1609
1610         return max_rate >= 540000;
1611 }
1612
1613 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1614 {
1615         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1616
1617         return max_rate >= 810000;
1618 }
1619
1620 static void
1621 intel_dp_set_clock(struct intel_encoder *encoder,
1622                    struct intel_crtc_state *pipe_config)
1623 {
1624         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1625         const struct dp_link_dpll *divisor = NULL;
1626         int i, count = 0;
1627
1628         if (IS_G4X(dev_priv)) {
1629                 divisor = g4x_dpll;
1630                 count = ARRAY_SIZE(g4x_dpll);
1631         } else if (HAS_PCH_SPLIT(dev_priv)) {
1632                 divisor = pch_dpll;
1633                 count = ARRAY_SIZE(pch_dpll);
1634         } else if (IS_CHERRYVIEW(dev_priv)) {
1635                 divisor = chv_dpll;
1636                 count = ARRAY_SIZE(chv_dpll);
1637         } else if (IS_VALLEYVIEW(dev_priv)) {
1638                 divisor = vlv_dpll;
1639                 count = ARRAY_SIZE(vlv_dpll);
1640         }
1641
1642         if (divisor && count) {
1643                 for (i = 0; i < count; i++) {
1644                         if (pipe_config->port_clock == divisor[i].clock) {
1645                                 pipe_config->dpll = divisor[i].dpll;
1646                                 pipe_config->clock_set = true;
1647                                 break;
1648                         }
1649                 }
1650         }
1651 }
1652
1653 static void snprintf_int_array(char *str, size_t len,
1654                                const int *array, int nelem)
1655 {
1656         int i;
1657
1658         str[0] = '\0';
1659
1660         for (i = 0; i < nelem; i++) {
1661                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1662                 if (r >= len)
1663                         return;
1664                 str += r;
1665                 len -= r;
1666         }
1667 }
1668
1669 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1670 {
1671         char str[128]; /* FIXME: too big for stack? */
1672
1673         if ((drm_debug & DRM_UT_KMS) == 0)
1674                 return;
1675
1676         snprintf_int_array(str, sizeof(str),
1677                            intel_dp->source_rates, intel_dp->num_source_rates);
1678         DRM_DEBUG_KMS("source rates: %s\n", str);
1679
1680         snprintf_int_array(str, sizeof(str),
1681                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1682         DRM_DEBUG_KMS("sink rates: %s\n", str);
1683
1684         snprintf_int_array(str, sizeof(str),
1685                            intel_dp->common_rates, intel_dp->num_common_rates);
1686         DRM_DEBUG_KMS("common rates: %s\n", str);
1687 }
1688
1689 int
1690 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1691 {
1692         int len;
1693
1694         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1695         if (WARN_ON(len <= 0))
1696                 return 162000;
1697
1698         return intel_dp->common_rates[len - 1];
1699 }
1700
1701 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1702 {
1703         int i = intel_dp_rate_index(intel_dp->sink_rates,
1704                                     intel_dp->num_sink_rates, rate);
1705
1706         if (WARN_ON(i < 0))
1707                 i = 0;
1708
1709         return i;
1710 }
1711
1712 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1713                            u8 *link_bw, u8 *rate_select)
1714 {
1715         /* eDP 1.4 rate select method. */
1716         if (intel_dp->use_rate_select) {
1717                 *link_bw = 0;
1718                 *rate_select =
1719                         intel_dp_rate_select(intel_dp, port_clock);
1720         } else {
1721                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1722                 *rate_select = 0;
1723         }
1724 }
1725
1726 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1727                                          const struct intel_crtc_state *pipe_config)
1728 {
1729         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1730
1731         return INTEL_GEN(dev_priv) >= 11 &&
1732                 pipe_config->cpu_transcoder != TRANSCODER_A;
1733 }
1734
1735 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1736                                   const struct intel_crtc_state *pipe_config)
1737 {
1738         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1739                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1740 }
1741
1742 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1743                                          const struct intel_crtc_state *pipe_config)
1744 {
1745         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1746
1747         return INTEL_GEN(dev_priv) >= 10 &&
1748                 pipe_config->cpu_transcoder != TRANSCODER_A;
1749 }
1750
1751 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1752                                   const struct intel_crtc_state *pipe_config)
1753 {
1754         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1755                 return false;
1756
1757         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1758                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1759 }
1760
1761 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1762                                 struct intel_crtc_state *pipe_config)
1763 {
1764         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1765         struct intel_connector *intel_connector = intel_dp->attached_connector;
1766         int bpp, bpc;
1767
1768         bpp = pipe_config->pipe_bpp;
1769         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1770
1771         if (bpc > 0)
1772                 bpp = min(bpp, 3*bpc);
1773
1774         if (intel_dp_is_edp(intel_dp)) {
1775                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1776                 if (intel_connector->base.display_info.bpc == 0 &&
1777                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1778                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1779                                       dev_priv->vbt.edp.bpp);
1780                         bpp = dev_priv->vbt.edp.bpp;
1781                 }
1782         }
1783
1784         return bpp;
1785 }
1786
1787 /* Adjust link config limits based on compliance test requests. */
1788 void
1789 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1790                                   struct intel_crtc_state *pipe_config,
1791                                   struct link_config_limits *limits)
1792 {
1793         /* For DP Compliance we override the computed bpp for the pipe */
1794         if (intel_dp->compliance.test_data.bpc != 0) {
1795                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1796
1797                 limits->min_bpp = limits->max_bpp = bpp;
1798                 pipe_config->dither_force_disable = bpp == 6 * 3;
1799
1800                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1801         }
1802
1803         /* Use values requested by Compliance Test Request */
1804         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1805                 int index;
1806
1807                 /* Validate the compliance test data since max values
1808                  * might have changed due to link train fallback.
1809                  */
1810                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1811                                                intel_dp->compliance.test_lane_count)) {
1812                         index = intel_dp_rate_index(intel_dp->common_rates,
1813                                                     intel_dp->num_common_rates,
1814                                                     intel_dp->compliance.test_link_rate);
1815                         if (index >= 0)
1816                                 limits->min_clock = limits->max_clock = index;
1817                         limits->min_lane_count = limits->max_lane_count =
1818                                 intel_dp->compliance.test_lane_count;
1819                 }
1820         }
1821 }
1822
1823 /* Optimize link config in order: max bpp, min clock, min lanes */
1824 static int
1825 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1826                                   struct intel_crtc_state *pipe_config,
1827                                   const struct link_config_limits *limits)
1828 {
1829         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1830         int bpp, clock, lane_count;
1831         int mode_rate, link_clock, link_avail;
1832
1833         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1834                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1835                                                    bpp);
1836
1837                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1838                         for (lane_count = limits->min_lane_count;
1839                              lane_count <= limits->max_lane_count;
1840                              lane_count <<= 1) {
1841                                 link_clock = intel_dp->common_rates[clock];
1842                                 link_avail = intel_dp_max_data_rate(link_clock,
1843                                                                     lane_count);
1844
1845                                 if (mode_rate <= link_avail) {
1846                                         pipe_config->lane_count = lane_count;
1847                                         pipe_config->pipe_bpp = bpp;
1848                                         pipe_config->port_clock = link_clock;
1849
1850                                         return 0;
1851                                 }
1852                         }
1853                 }
1854         }
1855
1856         return -EINVAL;
1857 }
1858
1859 /* Optimize link config in order: max bpp, min lanes, min clock */
1860 static int
1861 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1862                                   struct intel_crtc_state *pipe_config,
1863                                   const struct link_config_limits *limits)
1864 {
1865         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1866         int bpp, clock, lane_count;
1867         int mode_rate, link_clock, link_avail;
1868
1869         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1870                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1871                                                    bpp);
1872
1873                 for (lane_count = limits->min_lane_count;
1874                      lane_count <= limits->max_lane_count;
1875                      lane_count <<= 1) {
1876                         for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1877                                 link_clock = intel_dp->common_rates[clock];
1878                                 link_avail = intel_dp_max_data_rate(link_clock,
1879                                                                     lane_count);
1880
1881                                 if (mode_rate <= link_avail) {
1882                                         pipe_config->lane_count = lane_count;
1883                                         pipe_config->pipe_bpp = bpp;
1884                                         pipe_config->port_clock = link_clock;
1885
1886                                         return 0;
1887                                 }
1888                         }
1889                 }
1890         }
1891
1892         return -EINVAL;
1893 }
1894
1895 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1896 {
1897         int i, num_bpc;
1898         u8 dsc_bpc[3] = {0};
1899
1900         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1901                                                        dsc_bpc);
1902         for (i = 0; i < num_bpc; i++) {
1903                 if (dsc_max_bpc >= dsc_bpc[i])
1904                         return dsc_bpc[i] * 3;
1905         }
1906
1907         return 0;
1908 }
1909
1910 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1911                                        struct intel_crtc_state *pipe_config,
1912                                        struct drm_connector_state *conn_state,
1913                                        struct link_config_limits *limits)
1914 {
1915         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1916         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1917         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1918         u8 dsc_max_bpc;
1919         int pipe_bpp;
1920         int ret;
1921
1922         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1923                 return -EINVAL;
1924
1925         dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
1926                             conn_state->max_requested_bpc);
1927
1928         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1929         if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
1930                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1931                 return -EINVAL;
1932         }
1933
1934         /*
1935          * For now enable DSC for max bpp, max link rate, max lane count.
1936          * Optimize this later for the minimum possible link rate/lane count
1937          * with DSC enabled for the requested mode.
1938          */
1939         pipe_config->pipe_bpp = pipe_bpp;
1940         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1941         pipe_config->lane_count = limits->max_lane_count;
1942
1943         if (intel_dp_is_edp(intel_dp)) {
1944                 pipe_config->dsc_params.compressed_bpp =
1945                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1946                               pipe_config->pipe_bpp);
1947                 pipe_config->dsc_params.slice_count =
1948                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1949                                                         true);
1950         } else {
1951                 u16 dsc_max_output_bpp;
1952                 u8 dsc_dp_slice_count;
1953
1954                 dsc_max_output_bpp =
1955                         intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
1956                                                     pipe_config->lane_count,
1957                                                     adjusted_mode->crtc_clock,
1958                                                     adjusted_mode->crtc_hdisplay);
1959                 dsc_dp_slice_count =
1960                         intel_dp_dsc_get_slice_count(intel_dp,
1961                                                      adjusted_mode->crtc_clock,
1962                                                      adjusted_mode->crtc_hdisplay);
1963                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1964                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1965                         return -EINVAL;
1966                 }
1967                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
1968                                                                dsc_max_output_bpp >> 4,
1969                                                                pipe_config->pipe_bpp);
1970                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
1971         }
1972         /*
1973          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1974          * is greater than the maximum Cdclock and if slice count is even
1975          * then we need to use 2 VDSC instances.
1976          */
1977         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
1978                 if (pipe_config->dsc_params.slice_count > 1) {
1979                         pipe_config->dsc_params.dsc_split = true;
1980                 } else {
1981                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1982                         return -EINVAL;
1983                 }
1984         }
1985
1986         ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
1987         if (ret < 0) {
1988                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1989                               "Compressed BPP = %d\n",
1990                               pipe_config->pipe_bpp,
1991                               pipe_config->dsc_params.compressed_bpp);
1992                 return ret;
1993         }
1994
1995         pipe_config->dsc_params.compression_enable = true;
1996         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
1997                       "Compressed Bpp = %d Slice Count = %d\n",
1998                       pipe_config->pipe_bpp,
1999                       pipe_config->dsc_params.compressed_bpp,
2000                       pipe_config->dsc_params.slice_count);
2001
2002         return 0;
2003 }
2004
2005 static int
2006 intel_dp_compute_link_config(struct intel_encoder *encoder,
2007                              struct intel_crtc_state *pipe_config,
2008                              struct drm_connector_state *conn_state)
2009 {
2010         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2011         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2012         struct link_config_limits limits;
2013         int common_len;
2014         int ret;
2015
2016         common_len = intel_dp_common_len_rate_limit(intel_dp,
2017                                                     intel_dp->max_link_rate);
2018
2019         /* No common link rates between source and sink */
2020         WARN_ON(common_len <= 0);
2021
2022         limits.min_clock = 0;
2023         limits.max_clock = common_len - 1;
2024
2025         limits.min_lane_count = 1;
2026         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2027
2028         limits.min_bpp = 6 * 3;
2029         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2030
2031         if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
2032                 /*
2033                  * Use the maximum clock and number of lanes the eDP panel
2034                  * advertizes being capable of. The eDP 1.3 and earlier panels
2035                  * are generally designed to support only a single clock and
2036                  * lane configuration, and typically these values correspond to
2037                  * the native resolution of the panel. With eDP 1.4 rate select
2038                  * and DSC, this is decreasingly the case, and we need to be
2039                  * able to select less than maximum link config.
2040                  */
2041                 limits.min_lane_count = limits.max_lane_count;
2042                 limits.min_clock = limits.max_clock;
2043         }
2044
2045         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2046
2047         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2048                       "max rate %d max bpp %d pixel clock %iKHz\n",
2049                       limits.max_lane_count,
2050                       intel_dp->common_rates[limits.max_clock],
2051                       limits.max_bpp, adjusted_mode->crtc_clock);
2052
2053         if (intel_dp_is_edp(intel_dp))
2054                 /*
2055                  * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
2056                  * section A.1: "It is recommended that the minimum number of
2057                  * lanes be used, using the minimum link rate allowed for that
2058                  * lane configuration."
2059                  *
2060                  * Note that we use the max clock and lane count for eDP 1.3 and
2061                  * earlier, and fast vs. wide is irrelevant.
2062                  */
2063                 ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
2064                                                         &limits);
2065         else
2066                 /* Optimize for slow and wide. */
2067                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2068                                                         &limits);
2069
2070         /* enable compression if the mode doesn't fit available BW */
2071         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2072         if (ret || intel_dp->force_dsc_en) {
2073                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2074                                                   conn_state, &limits);
2075                 if (ret < 0)
2076                         return ret;
2077         }
2078
2079         if (pipe_config->dsc_params.compression_enable) {
2080                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2081                               pipe_config->lane_count, pipe_config->port_clock,
2082                               pipe_config->pipe_bpp,
2083                               pipe_config->dsc_params.compressed_bpp);
2084
2085                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2086                               intel_dp_link_required(adjusted_mode->crtc_clock,
2087                                                      pipe_config->dsc_params.compressed_bpp),
2088                               intel_dp_max_data_rate(pipe_config->port_clock,
2089                                                      pipe_config->lane_count));
2090         } else {
2091                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2092                               pipe_config->lane_count, pipe_config->port_clock,
2093                               pipe_config->pipe_bpp);
2094
2095                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2096                               intel_dp_link_required(adjusted_mode->crtc_clock,
2097                                                      pipe_config->pipe_bpp),
2098                               intel_dp_max_data_rate(pipe_config->port_clock,
2099                                                      pipe_config->lane_count));
2100         }
2101         return 0;
2102 }
2103
2104 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2105                                   const struct drm_connector_state *conn_state)
2106 {
2107         const struct intel_digital_connector_state *intel_conn_state =
2108                 to_intel_digital_connector_state(conn_state);
2109         const struct drm_display_mode *adjusted_mode =
2110                 &crtc_state->base.adjusted_mode;
2111
2112         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2113                 /*
2114                  * See:
2115                  * CEA-861-E - 5.1 Default Encoding Parameters
2116                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2117                  */
2118                 return crtc_state->pipe_bpp != 18 &&
2119                         drm_default_rgb_quant_range(adjusted_mode) ==
2120                         HDMI_QUANTIZATION_RANGE_LIMITED;
2121         } else {
2122                 return intel_conn_state->broadcast_rgb ==
2123                         INTEL_BROADCAST_RGB_LIMITED;
2124         }
2125 }
2126
2127 int
2128 intel_dp_compute_config(struct intel_encoder *encoder,
2129                         struct intel_crtc_state *pipe_config,
2130                         struct drm_connector_state *conn_state)
2131 {
2132         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2133         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2134         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2135         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2136         enum port port = encoder->port;
2137         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2138         struct intel_connector *intel_connector = intel_dp->attached_connector;
2139         struct intel_digital_connector_state *intel_conn_state =
2140                 to_intel_digital_connector_state(conn_state);
2141         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2142                                            DP_DPCD_QUIRK_CONSTANT_N);
2143         int ret;
2144
2145         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2146                 pipe_config->has_pch_encoder = true;
2147
2148         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2149         if (lspcon->active)
2150                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2151
2152         pipe_config->has_drrs = false;
2153         if (IS_G4X(dev_priv) || port == PORT_A)
2154                 pipe_config->has_audio = false;
2155         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2156                 pipe_config->has_audio = intel_dp->has_audio;
2157         else
2158                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2159
2160         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2161                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2162                                        adjusted_mode);
2163
2164                 if (INTEL_GEN(dev_priv) >= 9) {
2165                         ret = skl_update_scaler_crtc(pipe_config);
2166                         if (ret)
2167                                 return ret;
2168                 }
2169
2170                 if (HAS_GMCH(dev_priv))
2171                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2172                                                  conn_state->scaling_mode);
2173                 else
2174                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2175                                                 conn_state->scaling_mode);
2176         }
2177
2178         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2179                 return -EINVAL;
2180
2181         if (HAS_GMCH(dev_priv) &&
2182             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2183                 return -EINVAL;
2184
2185         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2186                 return -EINVAL;
2187
2188         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2189                                   intel_dp_supports_fec(intel_dp, pipe_config);
2190
2191         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2192         if (ret < 0)
2193                 return ret;
2194
2195         pipe_config->limited_color_range =
2196                 intel_dp_limited_color_range(pipe_config, conn_state);
2197
2198         if (!pipe_config->dsc_params.compression_enable)
2199                 intel_link_compute_m_n(pipe_config->pipe_bpp,
2200                                        pipe_config->lane_count,
2201                                        adjusted_mode->crtc_clock,
2202                                        pipe_config->port_clock,
2203                                        &pipe_config->dp_m_n,
2204                                        constant_n);
2205         else
2206                 intel_link_compute_m_n(pipe_config->dsc_params.compressed_bpp,
2207                                        pipe_config->lane_count,
2208                                        adjusted_mode->crtc_clock,
2209                                        pipe_config->port_clock,
2210                                        &pipe_config->dp_m_n,
2211                                        constant_n);
2212
2213         if (intel_connector->panel.downclock_mode != NULL &&
2214                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2215                         pipe_config->has_drrs = true;
2216                         intel_link_compute_m_n(pipe_config->pipe_bpp,
2217                                                pipe_config->lane_count,
2218                                                intel_connector->panel.downclock_mode->clock,
2219                                                pipe_config->port_clock,
2220                                                &pipe_config->dp_m2_n2,
2221                                                constant_n);
2222         }
2223
2224         if (!HAS_DDI(dev_priv))
2225                 intel_dp_set_clock(encoder, pipe_config);
2226
2227         intel_psr_compute_config(intel_dp, pipe_config);
2228
2229         return 0;
2230 }
2231
2232 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2233                               int link_rate, u8 lane_count,
2234                               bool link_mst)
2235 {
2236         intel_dp->link_trained = false;
2237         intel_dp->link_rate = link_rate;
2238         intel_dp->lane_count = lane_count;
2239         intel_dp->link_mst = link_mst;
2240 }
2241
2242 static void intel_dp_prepare(struct intel_encoder *encoder,
2243                              const struct intel_crtc_state *pipe_config)
2244 {
2245         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2246         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2247         enum port port = encoder->port;
2248         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2249         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2250
2251         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2252                                  pipe_config->lane_count,
2253                                  intel_crtc_has_type(pipe_config,
2254                                                      INTEL_OUTPUT_DP_MST));
2255
2256         /*
2257          * There are four kinds of DP registers:
2258          *
2259          *      IBX PCH
2260          *      SNB CPU
2261          *      IVB CPU
2262          *      CPT PCH
2263          *
2264          * IBX PCH and CPU are the same for almost everything,
2265          * except that the CPU DP PLL is configured in this
2266          * register
2267          *
2268          * CPT PCH is quite different, having many bits moved
2269          * to the TRANS_DP_CTL register instead. That
2270          * configuration happens (oddly) in ironlake_pch_enable
2271          */
2272
2273         /* Preserve the BIOS-computed detected bit. This is
2274          * supposed to be read-only.
2275          */
2276         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2277
2278         /* Handle DP bits in common between all three register formats */
2279         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2280         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2281
2282         /* Split out the IBX/CPU vs CPT settings */
2283
2284         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2285                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2286                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2287                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2288                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2289                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2290
2291                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2292                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2293
2294                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2295         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2296                 u32 trans_dp;
2297
2298                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2299
2300                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2301                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2302                         trans_dp |= TRANS_DP_ENH_FRAMING;
2303                 else
2304                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2305                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2306         } else {
2307                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2308                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2309
2310                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2311                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2312                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2313                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2314                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2315
2316                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2317                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2318
2319                 if (IS_CHERRYVIEW(dev_priv))
2320                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2321                 else
2322                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2323         }
2324 }
2325
2326 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2327 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2328
2329 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2330 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2331
2332 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2333 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2334
2335 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2336
2337 static void wait_panel_status(struct intel_dp *intel_dp,
2338                                        u32 mask,
2339                                        u32 value)
2340 {
2341         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2342         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2343
2344         lockdep_assert_held(&dev_priv->pps_mutex);
2345
2346         intel_pps_verify_state(intel_dp);
2347
2348         pp_stat_reg = _pp_stat_reg(intel_dp);
2349         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2350
2351         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2352                         mask, value,
2353                         I915_READ(pp_stat_reg),
2354                         I915_READ(pp_ctrl_reg));
2355
2356         if (intel_wait_for_register(&dev_priv->uncore,
2357                                     pp_stat_reg, mask, value,
2358                                     5000))
2359                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2360                                 I915_READ(pp_stat_reg),
2361                                 I915_READ(pp_ctrl_reg));
2362
2363         DRM_DEBUG_KMS("Wait complete\n");
2364 }
2365
2366 static void wait_panel_on(struct intel_dp *intel_dp)
2367 {
2368         DRM_DEBUG_KMS("Wait for panel power on\n");
2369         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2370 }
2371
2372 static void wait_panel_off(struct intel_dp *intel_dp)
2373 {
2374         DRM_DEBUG_KMS("Wait for panel power off time\n");
2375         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2376 }
2377
2378 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2379 {
2380         ktime_t panel_power_on_time;
2381         s64 panel_power_off_duration;
2382
2383         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2384
2385         /* take the difference of currrent time and panel power off time
2386          * and then make panel wait for t11_t12 if needed. */
2387         panel_power_on_time = ktime_get_boottime();
2388         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2389
2390         /* When we disable the VDD override bit last we have to do the manual
2391          * wait. */
2392         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2393                 wait_remaining_ms_from_jiffies(jiffies,
2394                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2395
2396         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2397 }
2398
2399 static void wait_backlight_on(struct intel_dp *intel_dp)
2400 {
2401         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2402                                        intel_dp->backlight_on_delay);
2403 }
2404
2405 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2406 {
2407         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2408                                        intel_dp->backlight_off_delay);
2409 }
2410
2411 /* Read the current pp_control value, unlocking the register if it
2412  * is locked
2413  */
2414
2415 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2416 {
2417         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2418         u32 control;
2419
2420         lockdep_assert_held(&dev_priv->pps_mutex);
2421
2422         control = I915_READ(_pp_ctrl_reg(intel_dp));
2423         if (WARN_ON(!HAS_DDI(dev_priv) &&
2424                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2425                 control &= ~PANEL_UNLOCK_MASK;
2426                 control |= PANEL_UNLOCK_REGS;
2427         }
2428         return control;
2429 }
2430
2431 /*
2432  * Must be paired with edp_panel_vdd_off().
2433  * Must hold pps_mutex around the whole on/off sequence.
2434  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2435  */
2436 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2437 {
2438         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2439         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2440         u32 pp;
2441         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2442         bool need_to_disable = !intel_dp->want_panel_vdd;
2443
2444         lockdep_assert_held(&dev_priv->pps_mutex);
2445
2446         if (!intel_dp_is_edp(intel_dp))
2447                 return false;
2448
2449         cancel_delayed_work(&intel_dp->panel_vdd_work);
2450         intel_dp->want_panel_vdd = true;
2451
2452         if (edp_have_panel_vdd(intel_dp))
2453                 return need_to_disable;
2454
2455         intel_display_power_get(dev_priv,
2456                                 intel_aux_power_domain(intel_dig_port));
2457
2458         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2459                       port_name(intel_dig_port->base.port));
2460
2461         if (!edp_have_panel_power(intel_dp))
2462                 wait_panel_power_cycle(intel_dp);
2463
2464         pp = ironlake_get_pp_control(intel_dp);
2465         pp |= EDP_FORCE_VDD;
2466
2467         pp_stat_reg = _pp_stat_reg(intel_dp);
2468         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2469
2470         I915_WRITE(pp_ctrl_reg, pp);
2471         POSTING_READ(pp_ctrl_reg);
2472         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2473                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2474         /*
2475          * If the panel wasn't on, delay before accessing aux channel
2476          */
2477         if (!edp_have_panel_power(intel_dp)) {
2478                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2479                               port_name(intel_dig_port->base.port));
2480                 msleep(intel_dp->panel_power_up_delay);
2481         }
2482
2483         return need_to_disable;
2484 }
2485
2486 /*
2487  * Must be paired with intel_edp_panel_vdd_off() or
2488  * intel_edp_panel_off().
2489  * Nested calls to these functions are not allowed since
2490  * we drop the lock. Caller must use some higher level
2491  * locking to prevent nested calls from other threads.
2492  */
2493 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2494 {
2495         intel_wakeref_t wakeref;
2496         bool vdd;
2497
2498         if (!intel_dp_is_edp(intel_dp))
2499                 return;
2500
2501         vdd = false;
2502         with_pps_lock(intel_dp, wakeref)
2503                 vdd = edp_panel_vdd_on(intel_dp);
2504         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2505              port_name(dp_to_dig_port(intel_dp)->base.port));
2506 }
2507
2508 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2509 {
2510         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2511         struct intel_digital_port *intel_dig_port =
2512                 dp_to_dig_port(intel_dp);
2513         u32 pp;
2514         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2515
2516         lockdep_assert_held(&dev_priv->pps_mutex);
2517
2518         WARN_ON(intel_dp->want_panel_vdd);
2519
2520         if (!edp_have_panel_vdd(intel_dp))
2521                 return;
2522
2523         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2524                       port_name(intel_dig_port->base.port));
2525
2526         pp = ironlake_get_pp_control(intel_dp);
2527         pp &= ~EDP_FORCE_VDD;
2528
2529         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2530         pp_stat_reg = _pp_stat_reg(intel_dp);
2531
2532         I915_WRITE(pp_ctrl_reg, pp);
2533         POSTING_READ(pp_ctrl_reg);
2534
2535         /* Make sure sequencer is idle before allowing subsequent activity */
2536         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2537         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2538
2539         if ((pp & PANEL_POWER_ON) == 0)
2540                 intel_dp->panel_power_off_time = ktime_get_boottime();
2541
2542         intel_display_power_put_unchecked(dev_priv,
2543                                           intel_aux_power_domain(intel_dig_port));
2544 }
2545
2546 static void edp_panel_vdd_work(struct work_struct *__work)
2547 {
2548         struct intel_dp *intel_dp =
2549                 container_of(to_delayed_work(__work),
2550                              struct intel_dp, panel_vdd_work);
2551         intel_wakeref_t wakeref;
2552
2553         with_pps_lock(intel_dp, wakeref) {
2554                 if (!intel_dp->want_panel_vdd)
2555                         edp_panel_vdd_off_sync(intel_dp);
2556         }
2557 }
2558
2559 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2560 {
2561         unsigned long delay;
2562
2563         /*
2564          * Queue the timer to fire a long time from now (relative to the power
2565          * down delay) to keep the panel power up across a sequence of
2566          * operations.
2567          */
2568         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2569         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2570 }
2571
2572 /*
2573  * Must be paired with edp_panel_vdd_on().
2574  * Must hold pps_mutex around the whole on/off sequence.
2575  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2576  */
2577 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2578 {
2579         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2580
2581         lockdep_assert_held(&dev_priv->pps_mutex);
2582
2583         if (!intel_dp_is_edp(intel_dp))
2584                 return;
2585
2586         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2587              port_name(dp_to_dig_port(intel_dp)->base.port));
2588
2589         intel_dp->want_panel_vdd = false;
2590
2591         if (sync)
2592                 edp_panel_vdd_off_sync(intel_dp);
2593         else
2594                 edp_panel_vdd_schedule_off(intel_dp);
2595 }
2596
2597 static void edp_panel_on(struct intel_dp *intel_dp)
2598 {
2599         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2600         u32 pp;
2601         i915_reg_t pp_ctrl_reg;
2602
2603         lockdep_assert_held(&dev_priv->pps_mutex);
2604
2605         if (!intel_dp_is_edp(intel_dp))
2606                 return;
2607
2608         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2609                       port_name(dp_to_dig_port(intel_dp)->base.port));
2610
2611         if (WARN(edp_have_panel_power(intel_dp),
2612                  "eDP port %c panel power already on\n",
2613                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2614                 return;
2615
2616         wait_panel_power_cycle(intel_dp);
2617
2618         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2619         pp = ironlake_get_pp_control(intel_dp);
2620         if (IS_GEN(dev_priv, 5)) {
2621                 /* ILK workaround: disable reset around power sequence */
2622                 pp &= ~PANEL_POWER_RESET;
2623                 I915_WRITE(pp_ctrl_reg, pp);
2624                 POSTING_READ(pp_ctrl_reg);
2625         }
2626
2627         pp |= PANEL_POWER_ON;
2628         if (!IS_GEN(dev_priv, 5))
2629                 pp |= PANEL_POWER_RESET;
2630
2631         I915_WRITE(pp_ctrl_reg, pp);
2632         POSTING_READ(pp_ctrl_reg);
2633
2634         wait_panel_on(intel_dp);
2635         intel_dp->last_power_on = jiffies;
2636
2637         if (IS_GEN(dev_priv, 5)) {
2638                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2639                 I915_WRITE(pp_ctrl_reg, pp);
2640                 POSTING_READ(pp_ctrl_reg);
2641         }
2642 }
2643
2644 void intel_edp_panel_on(struct intel_dp *intel_dp)
2645 {
2646         intel_wakeref_t wakeref;
2647
2648         if (!intel_dp_is_edp(intel_dp))
2649                 return;
2650
2651         with_pps_lock(intel_dp, wakeref)
2652                 edp_panel_on(intel_dp);
2653 }
2654
2655
2656 static void edp_panel_off(struct intel_dp *intel_dp)
2657 {
2658         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2659         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2660         u32 pp;
2661         i915_reg_t pp_ctrl_reg;
2662
2663         lockdep_assert_held(&dev_priv->pps_mutex);
2664
2665         if (!intel_dp_is_edp(intel_dp))
2666                 return;
2667
2668         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2669                       port_name(dig_port->base.port));
2670
2671         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2672              port_name(dig_port->base.port));
2673
2674         pp = ironlake_get_pp_control(intel_dp);
2675         /* We need to switch off panel power _and_ force vdd, for otherwise some
2676          * panels get very unhappy and cease to work. */
2677         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2678                 EDP_BLC_ENABLE);
2679
2680         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2681
2682         intel_dp->want_panel_vdd = false;
2683
2684         I915_WRITE(pp_ctrl_reg, pp);
2685         POSTING_READ(pp_ctrl_reg);
2686
2687         wait_panel_off(intel_dp);
2688         intel_dp->panel_power_off_time = ktime_get_boottime();
2689
2690         /* We got a reference when we enabled the VDD. */
2691         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2692 }
2693
2694 void intel_edp_panel_off(struct intel_dp *intel_dp)
2695 {
2696         intel_wakeref_t wakeref;
2697
2698         if (!intel_dp_is_edp(intel_dp))
2699                 return;
2700
2701         with_pps_lock(intel_dp, wakeref)
2702                 edp_panel_off(intel_dp);
2703 }
2704
2705 /* Enable backlight in the panel power control. */
2706 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2707 {
2708         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2709         intel_wakeref_t wakeref;
2710
2711         /*
2712          * If we enable the backlight right away following a panel power
2713          * on, we may see slight flicker as the panel syncs with the eDP
2714          * link.  So delay a bit to make sure the image is solid before
2715          * allowing it to appear.
2716          */
2717         wait_backlight_on(intel_dp);
2718
2719         with_pps_lock(intel_dp, wakeref) {
2720                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2721                 u32 pp;
2722
2723                 pp = ironlake_get_pp_control(intel_dp);
2724                 pp |= EDP_BLC_ENABLE;
2725
2726                 I915_WRITE(pp_ctrl_reg, pp);
2727                 POSTING_READ(pp_ctrl_reg);
2728         }
2729 }
2730
2731 /* Enable backlight PWM and backlight PP control. */
2732 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2733                             const struct drm_connector_state *conn_state)
2734 {
2735         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2736
2737         if (!intel_dp_is_edp(intel_dp))
2738                 return;
2739
2740         DRM_DEBUG_KMS("\n");
2741
2742         intel_panel_enable_backlight(crtc_state, conn_state);
2743         _intel_edp_backlight_on(intel_dp);
2744 }
2745
2746 /* Disable backlight in the panel power control. */
2747 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2748 {
2749         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2750         intel_wakeref_t wakeref;
2751
2752         if (!intel_dp_is_edp(intel_dp))
2753                 return;
2754
2755         with_pps_lock(intel_dp, wakeref) {
2756                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2757                 u32 pp;
2758
2759                 pp = ironlake_get_pp_control(intel_dp);
2760                 pp &= ~EDP_BLC_ENABLE;
2761
2762                 I915_WRITE(pp_ctrl_reg, pp);
2763                 POSTING_READ(pp_ctrl_reg);
2764         }
2765
2766         intel_dp->last_backlight_off = jiffies;
2767         edp_wait_backlight_off(intel_dp);
2768 }
2769
2770 /* Disable backlight PP control and backlight PWM. */
2771 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2772 {
2773         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2774
2775         if (!intel_dp_is_edp(intel_dp))
2776                 return;
2777
2778         DRM_DEBUG_KMS("\n");
2779
2780         _intel_edp_backlight_off(intel_dp);
2781         intel_panel_disable_backlight(old_conn_state);
2782 }
2783
2784 /*
2785  * Hook for controlling the panel power control backlight through the bl_power
2786  * sysfs attribute. Take care to handle multiple calls.
2787  */
2788 static void intel_edp_backlight_power(struct intel_connector *connector,
2789                                       bool enable)
2790 {
2791         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2792         intel_wakeref_t wakeref;
2793         bool is_enabled;
2794
2795         is_enabled = false;
2796         with_pps_lock(intel_dp, wakeref)
2797                 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2798         if (is_enabled == enable)
2799                 return;
2800
2801         DRM_DEBUG_KMS("panel power control backlight %s\n",
2802                       enable ? "enable" : "disable");
2803
2804         if (enable)
2805                 _intel_edp_backlight_on(intel_dp);
2806         else
2807                 _intel_edp_backlight_off(intel_dp);
2808 }
2809
2810 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2811 {
2812         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2813         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2814         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2815
2816         I915_STATE_WARN(cur_state != state,
2817                         "DP port %c state assertion failure (expected %s, current %s)\n",
2818                         port_name(dig_port->base.port),
2819                         onoff(state), onoff(cur_state));
2820 }
2821 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2822
2823 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2824 {
2825         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2826
2827         I915_STATE_WARN(cur_state != state,
2828                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2829                         onoff(state), onoff(cur_state));
2830 }
2831 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2832 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2833
2834 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2835                                 const struct intel_crtc_state *pipe_config)
2836 {
2837         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2838         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2839
2840         assert_pipe_disabled(dev_priv, crtc->pipe);
2841         assert_dp_port_disabled(intel_dp);
2842         assert_edp_pll_disabled(dev_priv);
2843
2844         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2845                       pipe_config->port_clock);
2846
2847         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2848
2849         if (pipe_config->port_clock == 162000)
2850                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2851         else
2852                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2853
2854         I915_WRITE(DP_A, intel_dp->DP);
2855         POSTING_READ(DP_A);
2856         udelay(500);
2857
2858         /*
2859          * [DevILK] Work around required when enabling DP PLL
2860          * while a pipe is enabled going to FDI:
2861          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2862          * 2. Program DP PLL enable
2863          */
2864         if (IS_GEN(dev_priv, 5))
2865                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2866
2867         intel_dp->DP |= DP_PLL_ENABLE;
2868
2869         I915_WRITE(DP_A, intel_dp->DP);
2870         POSTING_READ(DP_A);
2871         udelay(200);
2872 }
2873
2874 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2875                                  const struct intel_crtc_state *old_crtc_state)
2876 {
2877         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2878         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2879
2880         assert_pipe_disabled(dev_priv, crtc->pipe);
2881         assert_dp_port_disabled(intel_dp);
2882         assert_edp_pll_enabled(dev_priv);
2883
2884         DRM_DEBUG_KMS("disabling eDP PLL\n");
2885
2886         intel_dp->DP &= ~DP_PLL_ENABLE;
2887
2888         I915_WRITE(DP_A, intel_dp->DP);
2889         POSTING_READ(DP_A);
2890         udelay(200);
2891 }
2892
2893 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2894 {
2895         /*
2896          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2897          * be capable of signalling downstream hpd with a long pulse.
2898          * Whether or not that means D3 is safe to use is not clear,
2899          * but let's assume so until proven otherwise.
2900          *
2901          * FIXME should really check all downstream ports...
2902          */
2903         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2904                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2905                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2906 }
2907
2908 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2909                                            const struct intel_crtc_state *crtc_state,
2910                                            bool enable)
2911 {
2912         int ret;
2913
2914         if (!crtc_state->dsc_params.compression_enable)
2915                 return;
2916
2917         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2918                                  enable ? DP_DECOMPRESSION_EN : 0);
2919         if (ret < 0)
2920                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2921                               enable ? "enable" : "disable");
2922 }
2923
2924 /* If the sink supports it, try to set the power state appropriately */
2925 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2926 {
2927         int ret, i;
2928
2929         /* Should have a valid DPCD by this point */
2930         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2931                 return;
2932
2933         if (mode != DRM_MODE_DPMS_ON) {
2934                 if (downstream_hpd_needs_d0(intel_dp))
2935                         return;
2936
2937                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2938                                          DP_SET_POWER_D3);
2939         } else {
2940                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2941
2942                 /*
2943                  * When turning on, we need to retry for 1ms to give the sink
2944                  * time to wake up.
2945                  */
2946                 for (i = 0; i < 3; i++) {
2947                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2948                                                  DP_SET_POWER_D0);
2949                         if (ret == 1)
2950                                 break;
2951                         msleep(1);
2952                 }
2953
2954                 if (ret == 1 && lspcon->active)
2955                         lspcon_wait_pcon_mode(lspcon);
2956         }
2957
2958         if (ret != 1)
2959                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2960                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2961 }
2962
2963 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2964                                  enum port port, enum pipe *pipe)
2965 {
2966         enum pipe p;
2967
2968         for_each_pipe(dev_priv, p) {
2969                 u32 val = I915_READ(TRANS_DP_CTL(p));
2970
2971                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2972                         *pipe = p;
2973                         return true;
2974                 }
2975         }
2976
2977         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2978
2979         /* must initialize pipe to something for the asserts */
2980         *pipe = PIPE_A;
2981
2982         return false;
2983 }
2984
2985 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2986                            i915_reg_t dp_reg, enum port port,
2987                            enum pipe *pipe)
2988 {
2989         bool ret;
2990         u32 val;
2991
2992         val = I915_READ(dp_reg);
2993
2994         ret = val & DP_PORT_EN;
2995
2996         /* asserts want to know the pipe even if the port is disabled */
2997         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2998                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2999         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3000                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3001         else if (IS_CHERRYVIEW(dev_priv))
3002                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3003         else
3004                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3005
3006         return ret;
3007 }
3008
3009 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3010                                   enum pipe *pipe)
3011 {
3012         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3013         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3014         intel_wakeref_t wakeref;
3015         bool ret;
3016
3017         wakeref = intel_display_power_get_if_enabled(dev_priv,
3018                                                      encoder->power_domain);
3019         if (!wakeref)
3020                 return false;
3021
3022         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3023                                     encoder->port, pipe);
3024
3025         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3026
3027         return ret;
3028 }
3029
3030 static void intel_dp_get_config(struct intel_encoder *encoder,
3031                                 struct intel_crtc_state *pipe_config)
3032 {
3033         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3034         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3035         u32 tmp, flags = 0;
3036         enum port port = encoder->port;
3037         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3038
3039         if (encoder->type == INTEL_OUTPUT_EDP)
3040                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3041         else
3042                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3043
3044         tmp = I915_READ(intel_dp->output_reg);
3045
3046         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3047
3048         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3049                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3050
3051                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3052                         flags |= DRM_MODE_FLAG_PHSYNC;
3053                 else
3054                         flags |= DRM_MODE_FLAG_NHSYNC;
3055
3056                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3057                         flags |= DRM_MODE_FLAG_PVSYNC;
3058                 else
3059                         flags |= DRM_MODE_FLAG_NVSYNC;
3060         } else {
3061                 if (tmp & DP_SYNC_HS_HIGH)
3062                         flags |= DRM_MODE_FLAG_PHSYNC;
3063                 else
3064                         flags |= DRM_MODE_FLAG_NHSYNC;
3065
3066                 if (tmp & DP_SYNC_VS_HIGH)
3067                         flags |= DRM_MODE_FLAG_PVSYNC;
3068                 else
3069                         flags |= DRM_MODE_FLAG_NVSYNC;
3070         }
3071
3072         pipe_config->base.adjusted_mode.flags |= flags;
3073
3074         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3075                 pipe_config->limited_color_range = true;
3076
3077         pipe_config->lane_count =
3078                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3079
3080         intel_dp_get_m_n(crtc, pipe_config);
3081
3082         if (port == PORT_A) {
3083                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3084                         pipe_config->port_clock = 162000;
3085                 else
3086                         pipe_config->port_clock = 270000;
3087         }
3088
3089         pipe_config->base.adjusted_mode.crtc_clock =
3090                 intel_dotclock_calculate(pipe_config->port_clock,
3091                                          &pipe_config->dp_m_n);
3092
3093         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3094             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3095                 /*
3096                  * This is a big fat ugly hack.
3097                  *
3098                  * Some machines in UEFI boot mode provide us a VBT that has 18
3099                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3100                  * unknown we fail to light up. Yet the same BIOS boots up with
3101                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3102                  * max, not what it tells us to use.
3103                  *
3104                  * Note: This will still be broken if the eDP panel is not lit
3105                  * up by the BIOS, and thus we can't get the mode at module
3106                  * load.
3107                  */
3108                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3109                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3110                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3111         }
3112 }
3113
3114 static void intel_disable_dp(struct intel_encoder *encoder,
3115                              const struct intel_crtc_state *old_crtc_state,
3116                              const struct drm_connector_state *old_conn_state)
3117 {
3118         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3119
3120         intel_dp->link_trained = false;