2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll[] = {
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53 static const struct dp_link_dpll pch_dpll[] = {
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60 static const struct dp_link_dpll vlv_dpll[] = {
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
74 static bool is_edp(struct intel_dp *intel_dp)
76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
85 return intel_dig_port->base.base.dev;
88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
93 static void intel_dp_link_down(struct intel_dp *intel_dp);
94 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
95 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
98 intel_dp_max_link_bw(struct intel_dp *intel_dp)
100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
112 max_link_bw = DP_LINK_BW_2_7;
115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
117 max_link_bw = DP_LINK_BW_1_62;
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
129 * 270000 * 1 * 8 / 10 == 216000
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
141 intel_dp_link_required(int pixel_clock, int bpp)
143 return (pixel_clock * bpp + 9) / 10;
147 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
149 return (max_link_clock * max_lanes * 8) / 10;
152 static enum drm_mode_status
153 intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
156 struct intel_dp *intel_dp = intel_attached_dp(connector);
157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
166 if (mode->vdisplay > fixed_mode->vdisplay)
169 target_clock = fixed_mode->clock;
172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
178 if (mode_rate > max_rate)
179 return MODE_CLOCK_HIGH;
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
191 pack_aux(uint8_t *src, int src_bytes)
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
204 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
213 /* hrawclock is 1/4 the FSB frequency */
215 intel_hrawclk(struct drm_device *dev)
217 struct drm_i915_private *dev_priv = dev->dev_private;
220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
234 case CLKCFG_FSB_1067:
236 case CLKCFG_FSB_1333:
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
248 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
252 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
257 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
266 /* modeset should have pipe */
268 return to_intel_crtc(crtc)->pipe;
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
284 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
294 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
304 static bool edp_have_panel_power(struct intel_dp *intel_dp)
306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
307 struct drm_i915_private *dev_priv = dev->dev_private;
309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
312 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
315 struct drm_i915_private *dev_priv = dev->dev_private;
317 return !dev_priv->pm.suspended &&
318 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
322 intel_dp_check_edp(struct intel_dp *intel_dp)
324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
325 struct drm_i915_private *dev_priv = dev->dev_private;
327 if (!is_edp(intel_dp))
330 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
331 WARN(1, "eDP powered off while attempting aux channel communication.\n");
332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
333 I915_READ(_pp_stat_reg(intel_dp)),
334 I915_READ(_pp_ctrl_reg(intel_dp)));
339 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
342 struct drm_device *dev = intel_dig_port->base.base.dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
344 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
348 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
350 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
351 msecs_to_jiffies_timeout(10));
353 done = wait_for_atomic(C, 10) == 0;
355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
362 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365 struct drm_device *dev = intel_dig_port->base.base.dev;
368 * The clock divider is based off the hrawclk, and would like to run at
369 * 2MHz. So, take the hrawclk value and divide by 2 and use that
371 return index ? 0 : intel_hrawclk(dev) / 2;
374 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
377 struct drm_device *dev = intel_dig_port->base.base.dev;
382 if (intel_dig_port->port == PORT_A) {
383 if (IS_GEN6(dev) || IS_GEN7(dev))
384 return 200; /* SNB & IVB eDP input clock at 400Mhz */
386 return 225; /* eDP input clock at 450Mhz */
388 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
392 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
395 struct drm_device *dev = intel_dig_port->base.base.dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
398 if (intel_dig_port->port == PORT_A) {
401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
402 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
403 /* Workaround for non-ULT HSW */
410 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
414 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
416 return index ? 0 : 100;
419 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
422 uint32_t aux_clock_divider)
424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425 struct drm_device *dev = intel_dig_port->base.base.dev;
426 uint32_t precharge, timeout;
433 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
434 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
436 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
438 return DP_AUX_CH_CTL_SEND_BUSY |
440 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
441 DP_AUX_CH_CTL_TIME_OUT_ERROR |
443 DP_AUX_CH_CTL_RECEIVE_ERROR |
444 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
445 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
446 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
450 intel_dp_aux_ch(struct intel_dp *intel_dp,
451 uint8_t *send, int send_bytes,
452 uint8_t *recv, int recv_size)
454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
455 struct drm_device *dev = intel_dig_port->base.base.dev;
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
458 uint32_t ch_data = ch_ctl + 4;
459 uint32_t aux_clock_divider;
460 int i, ret, recv_bytes;
463 bool has_aux_irq = HAS_AUX_IRQ(dev);
466 vdd = _edp_panel_vdd_on(intel_dp);
468 /* dp aux is extremely sensitive to irq latency, hence request the
469 * lowest possible wakeup latency and so prevent the cpu from going into
472 pm_qos_update_request(&dev_priv->pm_qos, 0);
474 intel_dp_check_edp(intel_dp);
476 intel_aux_display_runtime_get(dev_priv);
478 /* Try to wait for any previous AUX channel activity */
479 for (try = 0; try < 3; try++) {
480 status = I915_READ_NOTRACE(ch_ctl);
481 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
487 WARN(1, "dp_aux_ch not started status 0x%08x\n",
493 /* Only 5 data registers! */
494 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
499 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
500 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
505 /* Must try at least 3 times according to DP spec */
506 for (try = 0; try < 5; try++) {
507 /* Load the send data into the aux channel data registers */
508 for (i = 0; i < send_bytes; i += 4)
509 I915_WRITE(ch_data + i,
510 pack_aux(send + i, send_bytes - i));
512 /* Send the command and wait for it to complete */
513 I915_WRITE(ch_ctl, send_ctl);
515 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
517 /* Clear done status and any errors */
521 DP_AUX_CH_CTL_TIME_OUT_ERROR |
522 DP_AUX_CH_CTL_RECEIVE_ERROR);
524 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
525 DP_AUX_CH_CTL_RECEIVE_ERROR))
527 if (status & DP_AUX_CH_CTL_DONE)
530 if (status & DP_AUX_CH_CTL_DONE)
534 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
535 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
540 /* Check for timeout or receive error.
541 * Timeouts occur when the sink is not connected
543 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
544 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
549 /* Timeouts occur when the device isn't connected, so they're
550 * "normal" -- don't fill the kernel log with these */
551 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
552 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
557 /* Unload any bytes sent back from the other side */
558 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
559 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
560 if (recv_bytes > recv_size)
561 recv_bytes = recv_size;
563 for (i = 0; i < recv_bytes; i += 4)
564 unpack_aux(I915_READ(ch_data + i),
565 recv + i, recv_bytes - i);
569 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
570 intel_aux_display_runtime_put(dev_priv);
573 edp_panel_vdd_off(intel_dp, false);
578 #define HEADER_SIZE 4
580 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
582 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
583 uint8_t txbuf[20], rxbuf[20];
584 size_t txsize, rxsize;
587 txbuf[0] = msg->request << 4;
588 txbuf[1] = msg->address >> 8;
589 txbuf[2] = msg->address & 0xff;
590 txbuf[3] = msg->size - 1;
592 switch (msg->request & ~DP_AUX_I2C_MOT) {
593 case DP_AUX_NATIVE_WRITE:
594 case DP_AUX_I2C_WRITE:
595 txsize = HEADER_SIZE + msg->size;
598 if (WARN_ON(txsize > 20))
601 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
603 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
605 msg->reply = rxbuf[0] >> 4;
607 /* Return payload size. */
612 case DP_AUX_NATIVE_READ:
613 case DP_AUX_I2C_READ:
614 txsize = HEADER_SIZE;
615 rxsize = msg->size + 1;
617 if (WARN_ON(rxsize > 20))
620 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
622 msg->reply = rxbuf[0] >> 4;
624 * Assume happy day, and copy the data. The caller is
625 * expected to check msg->reply before touching it.
627 * Return payload size.
630 memcpy(msg->buffer, rxbuf + 1, ret);
643 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
646 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
647 enum port port = intel_dig_port->port;
648 const char *name = NULL;
653 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
657 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
661 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
665 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
673 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
675 intel_dp->aux.name = name;
676 intel_dp->aux.dev = dev->dev;
677 intel_dp->aux.transfer = intel_dp_aux_transfer;
679 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
680 connector->base.kdev->kobj.name);
682 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
684 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
689 ret = sysfs_create_link(&connector->base.kdev->kobj,
690 &intel_dp->aux.ddc.dev.kobj,
691 intel_dp->aux.ddc.dev.kobj.name);
693 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
694 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
699 intel_dp_connector_unregister(struct intel_connector *intel_connector)
701 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
703 sysfs_remove_link(&intel_connector->base.kdev->kobj,
704 intel_dp->aux.ddc.dev.kobj.name);
705 intel_connector_unregister(intel_connector);
709 intel_dp_set_clock(struct intel_encoder *encoder,
710 struct intel_crtc_config *pipe_config, int link_bw)
712 struct drm_device *dev = encoder->base.dev;
713 const struct dp_link_dpll *divisor = NULL;
718 count = ARRAY_SIZE(gen4_dpll);
719 } else if (IS_HASWELL(dev)) {
720 /* Haswell has special-purpose DP DDI clocks. */
721 } else if (HAS_PCH_SPLIT(dev)) {
723 count = ARRAY_SIZE(pch_dpll);
724 } else if (IS_VALLEYVIEW(dev)) {
726 count = ARRAY_SIZE(vlv_dpll);
729 if (divisor && count) {
730 for (i = 0; i < count; i++) {
731 if (link_bw == divisor[i].link_bw) {
732 pipe_config->dpll = divisor[i].dpll;
733 pipe_config->clock_set = true;
741 intel_dp_compute_config(struct intel_encoder *encoder,
742 struct intel_crtc_config *pipe_config)
744 struct drm_device *dev = encoder->base.dev;
745 struct drm_i915_private *dev_priv = dev->dev_private;
746 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
747 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
748 enum port port = dp_to_dig_port(intel_dp)->port;
749 struct intel_crtc *intel_crtc = encoder->new_crtc;
750 struct intel_connector *intel_connector = intel_dp->attached_connector;
751 int lane_count, clock;
752 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
753 /* Conveniently, the link BW constants become indices with a shift...*/
754 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
756 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
757 int link_avail, link_clock;
759 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
760 pipe_config->has_pch_encoder = true;
762 pipe_config->has_dp_encoder = true;
764 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
765 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
767 if (!HAS_PCH_SPLIT(dev))
768 intel_gmch_panel_fitting(intel_crtc, pipe_config,
769 intel_connector->panel.fitting_mode);
771 intel_pch_panel_fitting(intel_crtc, pipe_config,
772 intel_connector->panel.fitting_mode);
775 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
778 DRM_DEBUG_KMS("DP link computation with max lane count %i "
779 "max bw %02x pixel clock %iKHz\n",
780 max_lane_count, bws[max_clock],
781 adjusted_mode->crtc_clock);
783 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
785 bpp = pipe_config->pipe_bpp;
786 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
787 dev_priv->vbt.edp_bpp < bpp) {
788 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
789 dev_priv->vbt.edp_bpp);
790 bpp = dev_priv->vbt.edp_bpp;
793 for (; bpp >= 6*3; bpp -= 2*3) {
794 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
797 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
798 for (clock = 0; clock <= max_clock; clock++) {
799 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
800 link_avail = intel_dp_max_data_rate(link_clock,
803 if (mode_rate <= link_avail) {
813 if (intel_dp->color_range_auto) {
816 * CEA-861-E - 5.1 Default Encoding Parameters
817 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
819 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
820 intel_dp->color_range = DP_COLOR_RANGE_16_235;
822 intel_dp->color_range = 0;
825 if (intel_dp->color_range)
826 pipe_config->limited_color_range = true;
828 intel_dp->link_bw = bws[clock];
829 intel_dp->lane_count = lane_count;
830 pipe_config->pipe_bpp = bpp;
831 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
833 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
834 intel_dp->link_bw, intel_dp->lane_count,
835 pipe_config->port_clock, bpp);
836 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
837 mode_rate, link_avail);
839 intel_link_compute_m_n(bpp, lane_count,
840 adjusted_mode->crtc_clock,
841 pipe_config->port_clock,
842 &pipe_config->dp_m_n);
844 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
849 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
851 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
852 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
853 struct drm_device *dev = crtc->base.dev;
854 struct drm_i915_private *dev_priv = dev->dev_private;
857 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
858 dpa_ctl = I915_READ(DP_A);
859 dpa_ctl &= ~DP_PLL_FREQ_MASK;
861 if (crtc->config.port_clock == 162000) {
862 /* For a long time we've carried around a ILK-DevA w/a for the
863 * 160MHz clock. If we're really unlucky, it's still required.
865 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
866 dpa_ctl |= DP_PLL_FREQ_160MHZ;
867 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
869 dpa_ctl |= DP_PLL_FREQ_270MHZ;
870 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
873 I915_WRITE(DP_A, dpa_ctl);
879 static void intel_dp_mode_set(struct intel_encoder *encoder)
881 struct drm_device *dev = encoder->base.dev;
882 struct drm_i915_private *dev_priv = dev->dev_private;
883 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
884 enum port port = dp_to_dig_port(intel_dp)->port;
885 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
886 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
889 * There are four kinds of DP registers:
896 * IBX PCH and CPU are the same for almost everything,
897 * except that the CPU DP PLL is configured in this
900 * CPT PCH is quite different, having many bits moved
901 * to the TRANS_DP_CTL register instead. That
902 * configuration happens (oddly) in ironlake_pch_enable
905 /* Preserve the BIOS-computed detected bit. This is
906 * supposed to be read-only.
908 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
910 /* Handle DP bits in common between all three register formats */
911 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
912 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
914 if (intel_dp->has_audio) {
915 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
916 pipe_name(crtc->pipe));
917 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
918 intel_write_eld(&encoder->base, adjusted_mode);
921 /* Split out the IBX/CPU vs CPT settings */
923 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
924 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
925 intel_dp->DP |= DP_SYNC_HS_HIGH;
926 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
927 intel_dp->DP |= DP_SYNC_VS_HIGH;
928 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
930 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
931 intel_dp->DP |= DP_ENHANCED_FRAMING;
933 intel_dp->DP |= crtc->pipe << 29;
934 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
935 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
936 intel_dp->DP |= intel_dp->color_range;
938 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
939 intel_dp->DP |= DP_SYNC_HS_HIGH;
940 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
941 intel_dp->DP |= DP_SYNC_VS_HIGH;
942 intel_dp->DP |= DP_LINK_TRAIN_OFF;
944 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
945 intel_dp->DP |= DP_ENHANCED_FRAMING;
948 intel_dp->DP |= DP_PIPEB_SELECT;
950 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
953 if (port == PORT_A && !IS_VALLEYVIEW(dev))
954 ironlake_set_pll_cpu_edp(intel_dp);
957 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
958 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
960 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
961 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
963 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
964 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
966 static void wait_panel_status(struct intel_dp *intel_dp,
970 struct drm_device *dev = intel_dp_to_dev(intel_dp);
971 struct drm_i915_private *dev_priv = dev->dev_private;
972 u32 pp_stat_reg, pp_ctrl_reg;
974 pp_stat_reg = _pp_stat_reg(intel_dp);
975 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
977 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
979 I915_READ(pp_stat_reg),
980 I915_READ(pp_ctrl_reg));
982 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
983 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
984 I915_READ(pp_stat_reg),
985 I915_READ(pp_ctrl_reg));
988 DRM_DEBUG_KMS("Wait complete\n");
991 static void wait_panel_on(struct intel_dp *intel_dp)
993 DRM_DEBUG_KMS("Wait for panel power on\n");
994 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
997 static void wait_panel_off(struct intel_dp *intel_dp)
999 DRM_DEBUG_KMS("Wait for panel power off time\n");
1000 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1003 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1005 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1007 /* When we disable the VDD override bit last we have to do the manual
1009 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1010 intel_dp->panel_power_cycle_delay);
1012 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1015 static void wait_backlight_on(struct intel_dp *intel_dp)
1017 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1018 intel_dp->backlight_on_delay);
1021 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1023 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1024 intel_dp->backlight_off_delay);
1027 /* Read the current pp_control value, unlocking the register if it
1031 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1033 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1034 struct drm_i915_private *dev_priv = dev->dev_private;
1037 control = I915_READ(_pp_ctrl_reg(intel_dp));
1038 control &= ~PANEL_UNLOCK_MASK;
1039 control |= PANEL_UNLOCK_REGS;
1043 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1045 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1046 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1047 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1048 struct drm_i915_private *dev_priv = dev->dev_private;
1049 enum intel_display_power_domain power_domain;
1051 u32 pp_stat_reg, pp_ctrl_reg;
1052 bool need_to_disable = !intel_dp->want_panel_vdd;
1054 if (!is_edp(intel_dp))
1057 intel_dp->want_panel_vdd = true;
1059 if (edp_have_panel_vdd(intel_dp))
1060 return need_to_disable;
1062 power_domain = intel_display_port_power_domain(intel_encoder);
1063 intel_display_power_get(dev_priv, power_domain);
1065 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1067 if (!edp_have_panel_power(intel_dp))
1068 wait_panel_power_cycle(intel_dp);
1070 pp = ironlake_get_pp_control(intel_dp);
1071 pp |= EDP_FORCE_VDD;
1073 pp_stat_reg = _pp_stat_reg(intel_dp);
1074 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1076 I915_WRITE(pp_ctrl_reg, pp);
1077 POSTING_READ(pp_ctrl_reg);
1078 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1079 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1081 * If the panel wasn't on, delay before accessing aux channel
1083 if (!edp_have_panel_power(intel_dp)) {
1084 DRM_DEBUG_KMS("eDP was not running\n");
1085 msleep(intel_dp->panel_power_up_delay);
1088 return need_to_disable;
1091 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1093 if (is_edp(intel_dp)) {
1094 bool vdd = _edp_panel_vdd_on(intel_dp);
1096 WARN(!vdd, "eDP VDD already requested on\n");
1100 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1102 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1103 struct drm_i915_private *dev_priv = dev->dev_private;
1105 u32 pp_stat_reg, pp_ctrl_reg;
1107 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1109 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1110 struct intel_digital_port *intel_dig_port =
1111 dp_to_dig_port(intel_dp);
1112 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1113 enum intel_display_power_domain power_domain;
1115 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1117 pp = ironlake_get_pp_control(intel_dp);
1118 pp &= ~EDP_FORCE_VDD;
1120 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1121 pp_stat_reg = _pp_stat_reg(intel_dp);
1123 I915_WRITE(pp_ctrl_reg, pp);
1124 POSTING_READ(pp_ctrl_reg);
1126 /* Make sure sequencer is idle before allowing subsequent activity */
1127 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1128 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1130 if ((pp & POWER_TARGET_ON) == 0)
1131 intel_dp->last_power_cycle = jiffies;
1133 power_domain = intel_display_port_power_domain(intel_encoder);
1134 intel_display_power_put(dev_priv, power_domain);
1138 static void edp_panel_vdd_work(struct work_struct *__work)
1140 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1141 struct intel_dp, panel_vdd_work);
1142 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1144 mutex_lock(&dev->mode_config.mutex);
1145 edp_panel_vdd_off_sync(intel_dp);
1146 mutex_unlock(&dev->mode_config.mutex);
1149 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1151 if (!is_edp(intel_dp))
1154 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1156 intel_dp->want_panel_vdd = false;
1159 edp_panel_vdd_off_sync(intel_dp);
1162 * Queue the timer to fire a long
1163 * time from now (relative to the power down delay)
1164 * to keep the panel power up across a sequence of operations
1166 schedule_delayed_work(&intel_dp->panel_vdd_work,
1167 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1171 void intel_edp_panel_on(struct intel_dp *intel_dp)
1173 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1174 struct drm_i915_private *dev_priv = dev->dev_private;
1178 if (!is_edp(intel_dp))
1181 DRM_DEBUG_KMS("Turn eDP power on\n");
1183 if (edp_have_panel_power(intel_dp)) {
1184 DRM_DEBUG_KMS("eDP power already on\n");
1188 wait_panel_power_cycle(intel_dp);
1190 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1191 pp = ironlake_get_pp_control(intel_dp);
1193 /* ILK workaround: disable reset around power sequence */
1194 pp &= ~PANEL_POWER_RESET;
1195 I915_WRITE(pp_ctrl_reg, pp);
1196 POSTING_READ(pp_ctrl_reg);
1199 pp |= POWER_TARGET_ON;
1201 pp |= PANEL_POWER_RESET;
1203 I915_WRITE(pp_ctrl_reg, pp);
1204 POSTING_READ(pp_ctrl_reg);
1206 wait_panel_on(intel_dp);
1207 intel_dp->last_power_on = jiffies;
1210 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1211 I915_WRITE(pp_ctrl_reg, pp);
1212 POSTING_READ(pp_ctrl_reg);
1216 void intel_edp_panel_off(struct intel_dp *intel_dp)
1218 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1219 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1220 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1221 struct drm_i915_private *dev_priv = dev->dev_private;
1222 enum intel_display_power_domain power_domain;
1226 if (!is_edp(intel_dp))
1229 DRM_DEBUG_KMS("Turn eDP power off\n");
1231 edp_wait_backlight_off(intel_dp);
1233 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1235 pp = ironlake_get_pp_control(intel_dp);
1236 /* We need to switch off panel power _and_ force vdd, for otherwise some
1237 * panels get very unhappy and cease to work. */
1238 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1241 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1243 intel_dp->want_panel_vdd = false;
1245 I915_WRITE(pp_ctrl_reg, pp);
1246 POSTING_READ(pp_ctrl_reg);
1248 intel_dp->last_power_cycle = jiffies;
1249 wait_panel_off(intel_dp);
1251 /* We got a reference when we enabled the VDD. */
1252 power_domain = intel_display_port_power_domain(intel_encoder);
1253 intel_display_power_put(dev_priv, power_domain);
1256 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1259 struct drm_device *dev = intel_dig_port->base.base.dev;
1260 struct drm_i915_private *dev_priv = dev->dev_private;
1264 if (!is_edp(intel_dp))
1267 DRM_DEBUG_KMS("\n");
1269 * If we enable the backlight right away following a panel power
1270 * on, we may see slight flicker as the panel syncs with the eDP
1271 * link. So delay a bit to make sure the image is solid before
1272 * allowing it to appear.
1274 wait_backlight_on(intel_dp);
1275 pp = ironlake_get_pp_control(intel_dp);
1276 pp |= EDP_BLC_ENABLE;
1278 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1280 I915_WRITE(pp_ctrl_reg, pp);
1281 POSTING_READ(pp_ctrl_reg);
1283 intel_panel_enable_backlight(intel_dp->attached_connector);
1286 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1288 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1289 struct drm_i915_private *dev_priv = dev->dev_private;
1293 if (!is_edp(intel_dp))
1296 intel_panel_disable_backlight(intel_dp->attached_connector);
1298 DRM_DEBUG_KMS("\n");
1299 pp = ironlake_get_pp_control(intel_dp);
1300 pp &= ~EDP_BLC_ENABLE;
1302 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1304 I915_WRITE(pp_ctrl_reg, pp);
1305 POSTING_READ(pp_ctrl_reg);
1306 intel_dp->last_backlight_off = jiffies;
1309 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1311 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1312 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1313 struct drm_device *dev = crtc->dev;
1314 struct drm_i915_private *dev_priv = dev->dev_private;
1317 assert_pipe_disabled(dev_priv,
1318 to_intel_crtc(crtc)->pipe);
1320 DRM_DEBUG_KMS("\n");
1321 dpa_ctl = I915_READ(DP_A);
1322 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1323 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1325 /* We don't adjust intel_dp->DP while tearing down the link, to
1326 * facilitate link retraining (e.g. after hotplug). Hence clear all
1327 * enable bits here to ensure that we don't enable too much. */
1328 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1329 intel_dp->DP |= DP_PLL_ENABLE;
1330 I915_WRITE(DP_A, intel_dp->DP);
1335 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1337 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1338 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1339 struct drm_device *dev = crtc->dev;
1340 struct drm_i915_private *dev_priv = dev->dev_private;
1343 assert_pipe_disabled(dev_priv,
1344 to_intel_crtc(crtc)->pipe);
1346 dpa_ctl = I915_READ(DP_A);
1347 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1348 "dp pll off, should be on\n");
1349 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1351 /* We can't rely on the value tracked for the DP register in
1352 * intel_dp->DP because link_down must not change that (otherwise link
1353 * re-training will fail. */
1354 dpa_ctl &= ~DP_PLL_ENABLE;
1355 I915_WRITE(DP_A, dpa_ctl);
1360 /* If the sink supports it, try to set the power state appropriately */
1361 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1365 /* Should have a valid DPCD by this point */
1366 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1369 if (mode != DRM_MODE_DPMS_ON) {
1370 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1373 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1376 * When turning on, we need to retry for 1ms to give the sink
1379 for (i = 0; i < 3; i++) {
1380 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1389 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1392 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1393 enum port port = dp_to_dig_port(intel_dp)->port;
1394 struct drm_device *dev = encoder->base.dev;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 enum intel_display_power_domain power_domain;
1399 power_domain = intel_display_port_power_domain(encoder);
1400 if (!intel_display_power_enabled(dev_priv, power_domain))
1403 tmp = I915_READ(intel_dp->output_reg);
1405 if (!(tmp & DP_PORT_EN))
1408 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1409 *pipe = PORT_TO_PIPE_CPT(tmp);
1410 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1411 *pipe = PORT_TO_PIPE(tmp);
1417 switch (intel_dp->output_reg) {
1419 trans_sel = TRANS_DP_PORT_SEL_B;
1422 trans_sel = TRANS_DP_PORT_SEL_C;
1425 trans_sel = TRANS_DP_PORT_SEL_D;
1432 trans_dp = I915_READ(TRANS_DP_CTL(i));
1433 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1439 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1440 intel_dp->output_reg);
1446 static void intel_dp_get_config(struct intel_encoder *encoder,
1447 struct intel_crtc_config *pipe_config)
1449 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1451 struct drm_device *dev = encoder->base.dev;
1452 struct drm_i915_private *dev_priv = dev->dev_private;
1453 enum port port = dp_to_dig_port(intel_dp)->port;
1454 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1457 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1458 tmp = I915_READ(intel_dp->output_reg);
1459 if (tmp & DP_SYNC_HS_HIGH)
1460 flags |= DRM_MODE_FLAG_PHSYNC;
1462 flags |= DRM_MODE_FLAG_NHSYNC;
1464 if (tmp & DP_SYNC_VS_HIGH)
1465 flags |= DRM_MODE_FLAG_PVSYNC;
1467 flags |= DRM_MODE_FLAG_NVSYNC;
1469 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1470 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1471 flags |= DRM_MODE_FLAG_PHSYNC;
1473 flags |= DRM_MODE_FLAG_NHSYNC;
1475 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1476 flags |= DRM_MODE_FLAG_PVSYNC;
1478 flags |= DRM_MODE_FLAG_NVSYNC;
1481 pipe_config->adjusted_mode.flags |= flags;
1483 pipe_config->has_dp_encoder = true;
1485 intel_dp_get_m_n(crtc, pipe_config);
1487 if (port == PORT_A) {
1488 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1489 pipe_config->port_clock = 162000;
1491 pipe_config->port_clock = 270000;
1494 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1495 &pipe_config->dp_m_n);
1497 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1498 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1500 pipe_config->adjusted_mode.crtc_clock = dotclock;
1502 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1503 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1505 * This is a big fat ugly hack.
1507 * Some machines in UEFI boot mode provide us a VBT that has 18
1508 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1509 * unknown we fail to light up. Yet the same BIOS boots up with
1510 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1511 * max, not what it tells us to use.
1513 * Note: This will still be broken if the eDP panel is not lit
1514 * up by the BIOS, and thus we can't get the mode at module
1517 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1518 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1519 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1523 static bool is_edp_psr(struct drm_device *dev)
1525 struct drm_i915_private *dev_priv = dev->dev_private;
1527 return dev_priv->psr.sink_support;
1530 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1537 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1540 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1541 struct edp_vsc_psr *vsc_psr)
1543 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1544 struct drm_device *dev = dig_port->base.base.dev;
1545 struct drm_i915_private *dev_priv = dev->dev_private;
1546 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1547 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1548 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1549 uint32_t *data = (uint32_t *) vsc_psr;
1552 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1553 the video DIP being updated before program video DIP data buffer
1554 registers for DIP being updated. */
1555 I915_WRITE(ctl_reg, 0);
1556 POSTING_READ(ctl_reg);
1558 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1559 if (i < sizeof(struct edp_vsc_psr))
1560 I915_WRITE(data_reg + i, *data++);
1562 I915_WRITE(data_reg + i, 0);
1565 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1566 POSTING_READ(ctl_reg);
1569 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1571 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573 struct edp_vsc_psr psr_vsc;
1575 if (intel_dp->psr_setup_done)
1578 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1579 memset(&psr_vsc, 0, sizeof(psr_vsc));
1580 psr_vsc.sdp_header.HB0 = 0;
1581 psr_vsc.sdp_header.HB1 = 0x7;
1582 psr_vsc.sdp_header.HB2 = 0x2;
1583 psr_vsc.sdp_header.HB3 = 0x8;
1584 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1586 /* Avoid continuous PSR exit by masking memup and hpd */
1587 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1588 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1590 intel_dp->psr_setup_done = true;
1593 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1595 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597 uint32_t aux_clock_divider;
1598 int precharge = 0x3;
1599 int msg_size = 5; /* Header(4) + Message(1) */
1601 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1603 /* Enable PSR in sink */
1604 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1605 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1606 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1608 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1609 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1611 /* Setup AUX registers */
1612 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1613 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1614 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1615 DP_AUX_CH_CTL_TIME_OUT_400us |
1616 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1617 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1618 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1621 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1623 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625 uint32_t max_sleep_time = 0x1f;
1626 uint32_t idle_frames = 1;
1628 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1630 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1631 val |= EDP_PSR_LINK_STANDBY;
1632 val |= EDP_PSR_TP2_TP3_TIME_0us;
1633 val |= EDP_PSR_TP1_TIME_0us;
1634 val |= EDP_PSR_SKIP_AUX_EXIT;
1636 val |= EDP_PSR_LINK_DISABLE;
1638 I915_WRITE(EDP_PSR_CTL(dev), val |
1639 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1640 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1641 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1645 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1647 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1648 struct drm_device *dev = dig_port->base.base.dev;
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650 struct drm_crtc *crtc = dig_port->base.base.crtc;
1651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1652 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1653 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1655 dev_priv->psr.source_ok = false;
1657 if (!HAS_PSR(dev)) {
1658 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1662 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1663 (dig_port->port != PORT_A)) {
1664 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1668 if (!i915.enable_psr) {
1669 DRM_DEBUG_KMS("PSR disable by flag\n");
1673 crtc = dig_port->base.base.crtc;
1675 DRM_DEBUG_KMS("crtc not active for PSR\n");
1679 intel_crtc = to_intel_crtc(crtc);
1680 if (!intel_crtc_active(crtc)) {
1681 DRM_DEBUG_KMS("crtc not active for PSR\n");
1685 obj = to_intel_framebuffer(crtc->fb)->obj;
1686 if (obj->tiling_mode != I915_TILING_X ||
1687 obj->fence_reg == I915_FENCE_REG_NONE) {
1688 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1692 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1693 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1697 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1699 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1703 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1704 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1708 dev_priv->psr.source_ok = true;
1712 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1714 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1716 if (!intel_edp_psr_match_conditions(intel_dp) ||
1717 intel_edp_is_psr_enabled(dev))
1720 /* Setup PSR once */
1721 intel_edp_psr_setup(intel_dp);
1723 /* Enable PSR on the panel */
1724 intel_edp_psr_enable_sink(intel_dp);
1726 /* Enable PSR on the host */
1727 intel_edp_psr_enable_source(intel_dp);
1730 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1732 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1734 if (intel_edp_psr_match_conditions(intel_dp) &&
1735 !intel_edp_is_psr_enabled(dev))
1736 intel_edp_psr_do_enable(intel_dp);
1739 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1741 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1744 if (!intel_edp_is_psr_enabled(dev))
1747 I915_WRITE(EDP_PSR_CTL(dev),
1748 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1750 /* Wait till PSR is idle */
1751 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1752 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1753 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1756 void intel_edp_psr_update(struct drm_device *dev)
1758 struct intel_encoder *encoder;
1759 struct intel_dp *intel_dp = NULL;
1761 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1762 if (encoder->type == INTEL_OUTPUT_EDP) {
1763 intel_dp = enc_to_intel_dp(&encoder->base);
1765 if (!is_edp_psr(dev))
1768 if (!intel_edp_psr_match_conditions(intel_dp))
1769 intel_edp_psr_disable(intel_dp);
1771 if (!intel_edp_is_psr_enabled(dev))
1772 intel_edp_psr_do_enable(intel_dp);
1776 static void intel_disable_dp(struct intel_encoder *encoder)
1778 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1779 enum port port = dp_to_dig_port(intel_dp)->port;
1780 struct drm_device *dev = encoder->base.dev;
1782 /* Make sure the panel is off before trying to change the mode. But also
1783 * ensure that we have vdd while we switch off the panel. */
1784 intel_edp_panel_vdd_on(intel_dp);
1785 intel_edp_backlight_off(intel_dp);
1786 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1787 intel_edp_panel_off(intel_dp);
1789 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1790 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1791 intel_dp_link_down(intel_dp);
1794 static void intel_post_disable_dp(struct intel_encoder *encoder)
1796 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1797 enum port port = dp_to_dig_port(intel_dp)->port;
1798 struct drm_device *dev = encoder->base.dev;
1800 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1801 intel_dp_link_down(intel_dp);
1802 if (!IS_VALLEYVIEW(dev))
1803 ironlake_edp_pll_off(intel_dp);
1807 static void intel_enable_dp(struct intel_encoder *encoder)
1809 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1810 struct drm_device *dev = encoder->base.dev;
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1814 if (WARN_ON(dp_reg & DP_PORT_EN))
1817 intel_edp_panel_vdd_on(intel_dp);
1818 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1819 intel_dp_start_link_train(intel_dp);
1820 intel_edp_panel_on(intel_dp);
1821 edp_panel_vdd_off(intel_dp, true);
1822 intel_dp_complete_link_train(intel_dp);
1823 intel_dp_stop_link_train(intel_dp);
1826 static void g4x_enable_dp(struct intel_encoder *encoder)
1828 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1830 intel_enable_dp(encoder);
1831 intel_edp_backlight_on(intel_dp);
1834 static void vlv_enable_dp(struct intel_encoder *encoder)
1836 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1838 intel_edp_backlight_on(intel_dp);
1841 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1843 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1844 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1846 if (dport->port == PORT_A)
1847 ironlake_edp_pll_on(intel_dp);
1850 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1852 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1853 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1854 struct drm_device *dev = encoder->base.dev;
1855 struct drm_i915_private *dev_priv = dev->dev_private;
1856 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1857 enum dpio_channel port = vlv_dport_to_channel(dport);
1858 int pipe = intel_crtc->pipe;
1859 struct edp_power_seq power_seq;
1862 mutex_lock(&dev_priv->dpio_lock);
1864 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1871 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1872 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1873 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1875 mutex_unlock(&dev_priv->dpio_lock);
1877 if (is_edp(intel_dp)) {
1878 /* init power sequencer on this pipe and port */
1879 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1880 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1884 intel_enable_dp(encoder);
1886 vlv_wait_port_ready(dev_priv, dport);
1889 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1891 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1892 struct drm_device *dev = encoder->base.dev;
1893 struct drm_i915_private *dev_priv = dev->dev_private;
1894 struct intel_crtc *intel_crtc =
1895 to_intel_crtc(encoder->base.crtc);
1896 enum dpio_channel port = vlv_dport_to_channel(dport);
1897 int pipe = intel_crtc->pipe;
1899 /* Program Tx lane resets to default */
1900 mutex_lock(&dev_priv->dpio_lock);
1901 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1902 DPIO_PCS_TX_LANE2_RESET |
1903 DPIO_PCS_TX_LANE1_RESET);
1904 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1905 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1906 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1907 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1908 DPIO_PCS_CLK_SOFT_RESET);
1910 /* Fix up inter-pair skew failure */
1911 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1912 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1913 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1914 mutex_unlock(&dev_priv->dpio_lock);
1918 * Native read with retry for link status and receiver capability reads for
1919 * cases where the sink may still be asleep.
1921 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1922 * supposed to retry 3 times per the spec.
1925 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1926 void *buffer, size_t size)
1931 for (i = 0; i < 3; i++) {
1932 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1942 * Fetch AUX CH registers 0x202 - 0x207 which contain
1943 * link status information
1946 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1948 return intel_dp_dpcd_read_wake(&intel_dp->aux,
1951 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
1955 * These are source-specific values; current Intel hardware supports
1956 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1960 intel_dp_voltage_max(struct intel_dp *intel_dp)
1962 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1963 enum port port = dp_to_dig_port(intel_dp)->port;
1965 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1966 return DP_TRAIN_VOLTAGE_SWING_1200;
1967 else if (IS_GEN7(dev) && port == PORT_A)
1968 return DP_TRAIN_VOLTAGE_SWING_800;
1969 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1970 return DP_TRAIN_VOLTAGE_SWING_1200;
1972 return DP_TRAIN_VOLTAGE_SWING_800;
1976 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1978 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1979 enum port port = dp_to_dig_port(intel_dp)->port;
1981 if (IS_BROADWELL(dev)) {
1982 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1983 case DP_TRAIN_VOLTAGE_SWING_400:
1984 case DP_TRAIN_VOLTAGE_SWING_600:
1985 return DP_TRAIN_PRE_EMPHASIS_6;
1986 case DP_TRAIN_VOLTAGE_SWING_800:
1987 return DP_TRAIN_PRE_EMPHASIS_3_5;
1988 case DP_TRAIN_VOLTAGE_SWING_1200:
1990 return DP_TRAIN_PRE_EMPHASIS_0;
1992 } else if (IS_HASWELL(dev)) {
1993 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1994 case DP_TRAIN_VOLTAGE_SWING_400:
1995 return DP_TRAIN_PRE_EMPHASIS_9_5;
1996 case DP_TRAIN_VOLTAGE_SWING_600:
1997 return DP_TRAIN_PRE_EMPHASIS_6;
1998 case DP_TRAIN_VOLTAGE_SWING_800:
1999 return DP_TRAIN_PRE_EMPHASIS_3_5;
2000 case DP_TRAIN_VOLTAGE_SWING_1200:
2002 return DP_TRAIN_PRE_EMPHASIS_0;
2004 } else if (IS_VALLEYVIEW(dev)) {
2005 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2006 case DP_TRAIN_VOLTAGE_SWING_400:
2007 return DP_TRAIN_PRE_EMPHASIS_9_5;
2008 case DP_TRAIN_VOLTAGE_SWING_600:
2009 return DP_TRAIN_PRE_EMPHASIS_6;
2010 case DP_TRAIN_VOLTAGE_SWING_800:
2011 return DP_TRAIN_PRE_EMPHASIS_3_5;
2012 case DP_TRAIN_VOLTAGE_SWING_1200:
2014 return DP_TRAIN_PRE_EMPHASIS_0;
2016 } else if (IS_GEN7(dev) && port == PORT_A) {
2017 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2018 case DP_TRAIN_VOLTAGE_SWING_400:
2019 return DP_TRAIN_PRE_EMPHASIS_6;
2020 case DP_TRAIN_VOLTAGE_SWING_600:
2021 case DP_TRAIN_VOLTAGE_SWING_800:
2022 return DP_TRAIN_PRE_EMPHASIS_3_5;
2024 return DP_TRAIN_PRE_EMPHASIS_0;
2027 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2028 case DP_TRAIN_VOLTAGE_SWING_400:
2029 return DP_TRAIN_PRE_EMPHASIS_6;
2030 case DP_TRAIN_VOLTAGE_SWING_600:
2031 return DP_TRAIN_PRE_EMPHASIS_6;
2032 case DP_TRAIN_VOLTAGE_SWING_800:
2033 return DP_TRAIN_PRE_EMPHASIS_3_5;
2034 case DP_TRAIN_VOLTAGE_SWING_1200:
2036 return DP_TRAIN_PRE_EMPHASIS_0;
2041 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2043 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2046 struct intel_crtc *intel_crtc =
2047 to_intel_crtc(dport->base.base.crtc);
2048 unsigned long demph_reg_value, preemph_reg_value,
2049 uniqtranscale_reg_value;
2050 uint8_t train_set = intel_dp->train_set[0];
2051 enum dpio_channel port = vlv_dport_to_channel(dport);
2052 int pipe = intel_crtc->pipe;
2054 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2055 case DP_TRAIN_PRE_EMPHASIS_0:
2056 preemph_reg_value = 0x0004000;
2057 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2058 case DP_TRAIN_VOLTAGE_SWING_400:
2059 demph_reg_value = 0x2B405555;
2060 uniqtranscale_reg_value = 0x552AB83A;
2062 case DP_TRAIN_VOLTAGE_SWING_600:
2063 demph_reg_value = 0x2B404040;
2064 uniqtranscale_reg_value = 0x5548B83A;
2066 case DP_TRAIN_VOLTAGE_SWING_800:
2067 demph_reg_value = 0x2B245555;
2068 uniqtranscale_reg_value = 0x5560B83A;
2070 case DP_TRAIN_VOLTAGE_SWING_1200:
2071 demph_reg_value = 0x2B405555;
2072 uniqtranscale_reg_value = 0x5598DA3A;
2078 case DP_TRAIN_PRE_EMPHASIS_3_5:
2079 preemph_reg_value = 0x0002000;
2080 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2081 case DP_TRAIN_VOLTAGE_SWING_400:
2082 demph_reg_value = 0x2B404040;
2083 uniqtranscale_reg_value = 0x5552B83A;
2085 case DP_TRAIN_VOLTAGE_SWING_600:
2086 demph_reg_value = 0x2B404848;
2087 uniqtranscale_reg_value = 0x5580B83A;
2089 case DP_TRAIN_VOLTAGE_SWING_800:
2090 demph_reg_value = 0x2B404040;
2091 uniqtranscale_reg_value = 0x55ADDA3A;
2097 case DP_TRAIN_PRE_EMPHASIS_6:
2098 preemph_reg_value = 0x0000000;
2099 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2100 case DP_TRAIN_VOLTAGE_SWING_400:
2101 demph_reg_value = 0x2B305555;
2102 uniqtranscale_reg_value = 0x5570B83A;
2104 case DP_TRAIN_VOLTAGE_SWING_600:
2105 demph_reg_value = 0x2B2B4040;
2106 uniqtranscale_reg_value = 0x55ADDA3A;
2112 case DP_TRAIN_PRE_EMPHASIS_9_5:
2113 preemph_reg_value = 0x0006000;
2114 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2115 case DP_TRAIN_VOLTAGE_SWING_400:
2116 demph_reg_value = 0x1B405555;
2117 uniqtranscale_reg_value = 0x55ADDA3A;
2127 mutex_lock(&dev_priv->dpio_lock);
2128 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2129 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2130 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2131 uniqtranscale_reg_value);
2132 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2133 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2134 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2135 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2136 mutex_unlock(&dev_priv->dpio_lock);
2142 intel_get_adjust_train(struct intel_dp *intel_dp,
2143 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2148 uint8_t voltage_max;
2149 uint8_t preemph_max;
2151 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2152 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2153 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2161 voltage_max = intel_dp_voltage_max(intel_dp);
2162 if (v >= voltage_max)
2163 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2165 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2166 if (p >= preemph_max)
2167 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2169 for (lane = 0; lane < 4; lane++)
2170 intel_dp->train_set[lane] = v | p;
2174 intel_gen4_signal_levels(uint8_t train_set)
2176 uint32_t signal_levels = 0;
2178 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2179 case DP_TRAIN_VOLTAGE_SWING_400:
2181 signal_levels |= DP_VOLTAGE_0_4;
2183 case DP_TRAIN_VOLTAGE_SWING_600:
2184 signal_levels |= DP_VOLTAGE_0_6;
2186 case DP_TRAIN_VOLTAGE_SWING_800:
2187 signal_levels |= DP_VOLTAGE_0_8;
2189 case DP_TRAIN_VOLTAGE_SWING_1200:
2190 signal_levels |= DP_VOLTAGE_1_2;
2193 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2194 case DP_TRAIN_PRE_EMPHASIS_0:
2196 signal_levels |= DP_PRE_EMPHASIS_0;
2198 case DP_TRAIN_PRE_EMPHASIS_3_5:
2199 signal_levels |= DP_PRE_EMPHASIS_3_5;
2201 case DP_TRAIN_PRE_EMPHASIS_6:
2202 signal_levels |= DP_PRE_EMPHASIS_6;
2204 case DP_TRAIN_PRE_EMPHASIS_9_5:
2205 signal_levels |= DP_PRE_EMPHASIS_9_5;
2208 return signal_levels;
2211 /* Gen6's DP voltage swing and pre-emphasis control */
2213 intel_gen6_edp_signal_levels(uint8_t train_set)
2215 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2216 DP_TRAIN_PRE_EMPHASIS_MASK);
2217 switch (signal_levels) {
2218 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2219 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2220 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2221 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2222 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2223 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2224 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2225 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2226 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2227 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2228 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2229 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2230 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2231 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2233 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2234 "0x%x\n", signal_levels);
2235 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2239 /* Gen7's DP voltage swing and pre-emphasis control */
2241 intel_gen7_edp_signal_levels(uint8_t train_set)
2243 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2244 DP_TRAIN_PRE_EMPHASIS_MASK);
2245 switch (signal_levels) {
2246 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2247 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2248 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2249 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2250 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2251 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2253 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2254 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2255 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2256 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2258 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2259 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2260 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2261 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2264 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2265 "0x%x\n", signal_levels);
2266 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2270 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2272 intel_hsw_signal_levels(uint8_t train_set)
2274 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2275 DP_TRAIN_PRE_EMPHASIS_MASK);
2276 switch (signal_levels) {
2277 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2278 return DDI_BUF_EMP_400MV_0DB_HSW;
2279 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2280 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2281 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2282 return DDI_BUF_EMP_400MV_6DB_HSW;
2283 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2284 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2286 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2287 return DDI_BUF_EMP_600MV_0DB_HSW;
2288 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2289 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2290 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2291 return DDI_BUF_EMP_600MV_6DB_HSW;
2293 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2294 return DDI_BUF_EMP_800MV_0DB_HSW;
2295 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2296 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2298 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2299 "0x%x\n", signal_levels);
2300 return DDI_BUF_EMP_400MV_0DB_HSW;
2305 intel_bdw_signal_levels(uint8_t train_set)
2307 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2308 DP_TRAIN_PRE_EMPHASIS_MASK);
2309 switch (signal_levels) {
2310 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2311 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2312 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2313 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2314 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2315 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2317 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2318 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2319 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2320 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2321 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2322 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2324 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2325 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2326 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2327 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2329 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2330 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2333 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2334 "0x%x\n", signal_levels);
2335 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2339 /* Properly updates "DP" with the correct signal levels. */
2341 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2343 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2344 enum port port = intel_dig_port->port;
2345 struct drm_device *dev = intel_dig_port->base.base.dev;
2346 uint32_t signal_levels, mask;
2347 uint8_t train_set = intel_dp->train_set[0];
2349 if (IS_BROADWELL(dev)) {
2350 signal_levels = intel_bdw_signal_levels(train_set);
2351 mask = DDI_BUF_EMP_MASK;
2352 } else if (IS_HASWELL(dev)) {
2353 signal_levels = intel_hsw_signal_levels(train_set);
2354 mask = DDI_BUF_EMP_MASK;
2355 } else if (IS_VALLEYVIEW(dev)) {
2356 signal_levels = intel_vlv_signal_levels(intel_dp);
2358 } else if (IS_GEN7(dev) && port == PORT_A) {
2359 signal_levels = intel_gen7_edp_signal_levels(train_set);
2360 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2361 } else if (IS_GEN6(dev) && port == PORT_A) {
2362 signal_levels = intel_gen6_edp_signal_levels(train_set);
2363 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2365 signal_levels = intel_gen4_signal_levels(train_set);
2366 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2369 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2371 *DP = (*DP & ~mask) | signal_levels;
2375 intel_dp_set_link_train(struct intel_dp *intel_dp,
2377 uint8_t dp_train_pat)
2379 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2380 struct drm_device *dev = intel_dig_port->base.base.dev;
2381 struct drm_i915_private *dev_priv = dev->dev_private;
2382 enum port port = intel_dig_port->port;
2383 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2387 uint32_t temp = I915_READ(DP_TP_CTL(port));
2389 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2390 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2392 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2394 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2395 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2396 case DP_TRAINING_PATTERN_DISABLE:
2397 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2400 case DP_TRAINING_PATTERN_1:
2401 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2403 case DP_TRAINING_PATTERN_2:
2404 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2406 case DP_TRAINING_PATTERN_3:
2407 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2410 I915_WRITE(DP_TP_CTL(port), temp);
2412 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2413 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2415 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2416 case DP_TRAINING_PATTERN_DISABLE:
2417 *DP |= DP_LINK_TRAIN_OFF_CPT;
2419 case DP_TRAINING_PATTERN_1:
2420 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2422 case DP_TRAINING_PATTERN_2:
2423 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2425 case DP_TRAINING_PATTERN_3:
2426 DRM_ERROR("DP training pattern 3 not supported\n");
2427 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2432 *DP &= ~DP_LINK_TRAIN_MASK;
2434 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2435 case DP_TRAINING_PATTERN_DISABLE:
2436 *DP |= DP_LINK_TRAIN_OFF;
2438 case DP_TRAINING_PATTERN_1:
2439 *DP |= DP_LINK_TRAIN_PAT_1;
2441 case DP_TRAINING_PATTERN_2:
2442 *DP |= DP_LINK_TRAIN_PAT_2;
2444 case DP_TRAINING_PATTERN_3:
2445 DRM_ERROR("DP training pattern 3 not supported\n");
2446 *DP |= DP_LINK_TRAIN_PAT_2;
2451 I915_WRITE(intel_dp->output_reg, *DP);
2452 POSTING_READ(intel_dp->output_reg);
2454 buf[0] = dp_train_pat;
2455 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2456 DP_TRAINING_PATTERN_DISABLE) {
2457 /* don't write DP_TRAINING_LANEx_SET on disable */
2460 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2461 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2462 len = intel_dp->lane_count + 1;
2465 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2472 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2473 uint8_t dp_train_pat)
2475 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2476 intel_dp_set_signal_levels(intel_dp, DP);
2477 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2481 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2482 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2484 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2485 struct drm_device *dev = intel_dig_port->base.base.dev;
2486 struct drm_i915_private *dev_priv = dev->dev_private;
2489 intel_get_adjust_train(intel_dp, link_status);
2490 intel_dp_set_signal_levels(intel_dp, DP);
2492 I915_WRITE(intel_dp->output_reg, *DP);
2493 POSTING_READ(intel_dp->output_reg);
2495 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2496 intel_dp->train_set, intel_dp->lane_count);
2498 return ret == intel_dp->lane_count;
2501 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2503 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2504 struct drm_device *dev = intel_dig_port->base.base.dev;
2505 struct drm_i915_private *dev_priv = dev->dev_private;
2506 enum port port = intel_dig_port->port;
2512 val = I915_READ(DP_TP_CTL(port));
2513 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2514 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2515 I915_WRITE(DP_TP_CTL(port), val);
2518 * On PORT_A we can have only eDP in SST mode. There the only reason
2519 * we need to set idle transmission mode is to work around a HW issue
2520 * where we enable the pipe while not in idle link-training mode.
2521 * In this case there is requirement to wait for a minimum number of
2522 * idle patterns to be sent.
2527 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2529 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2532 /* Enable corresponding port and start training pattern 1 */
2534 intel_dp_start_link_train(struct intel_dp *intel_dp)
2536 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2537 struct drm_device *dev = encoder->dev;
2540 int voltage_tries, loop_tries;
2541 uint32_t DP = intel_dp->DP;
2542 uint8_t link_config[2];
2545 intel_ddi_prepare_link_retrain(encoder);
2547 /* Write the link configuration data */
2548 link_config[0] = intel_dp->link_bw;
2549 link_config[1] = intel_dp->lane_count;
2550 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2551 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2552 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2555 link_config[1] = DP_SET_ANSI_8B10B;
2556 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
2560 /* clock recovery */
2561 if (!intel_dp_reset_link_train(intel_dp, &DP,
2562 DP_TRAINING_PATTERN_1 |
2563 DP_LINK_SCRAMBLING_DISABLE)) {
2564 DRM_ERROR("failed to enable link training\n");
2572 uint8_t link_status[DP_LINK_STATUS_SIZE];
2574 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2575 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2576 DRM_ERROR("failed to get link status\n");
2580 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2581 DRM_DEBUG_KMS("clock recovery OK\n");
2585 /* Check to see if we've tried the max voltage */
2586 for (i = 0; i < intel_dp->lane_count; i++)
2587 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2589 if (i == intel_dp->lane_count) {
2591 if (loop_tries == 5) {
2592 DRM_ERROR("too many full retries, give up\n");
2595 intel_dp_reset_link_train(intel_dp, &DP,
2596 DP_TRAINING_PATTERN_1 |
2597 DP_LINK_SCRAMBLING_DISABLE);
2602 /* Check to see if we've tried the same voltage 5 times */
2603 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2605 if (voltage_tries == 5) {
2606 DRM_ERROR("too many voltage retries, give up\n");
2611 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2613 /* Update training set as requested by target */
2614 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2615 DRM_ERROR("failed to update link training\n");
2624 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2626 bool channel_eq = false;
2627 int tries, cr_tries;
2628 uint32_t DP = intel_dp->DP;
2629 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2631 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2632 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2633 training_pattern = DP_TRAINING_PATTERN_3;
2635 /* channel equalization */
2636 if (!intel_dp_set_link_train(intel_dp, &DP,
2638 DP_LINK_SCRAMBLING_DISABLE)) {
2639 DRM_ERROR("failed to start channel equalization\n");
2647 uint8_t link_status[DP_LINK_STATUS_SIZE];
2650 DRM_ERROR("failed to train DP, aborting\n");
2654 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2655 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2656 DRM_ERROR("failed to get link status\n");
2660 /* Make sure clock is still ok */
2661 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2662 intel_dp_start_link_train(intel_dp);
2663 intel_dp_set_link_train(intel_dp, &DP,
2665 DP_LINK_SCRAMBLING_DISABLE);
2670 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2675 /* Try 5 times, then try clock recovery if that fails */
2677 intel_dp_link_down(intel_dp);
2678 intel_dp_start_link_train(intel_dp);
2679 intel_dp_set_link_train(intel_dp, &DP,
2681 DP_LINK_SCRAMBLING_DISABLE);
2687 /* Update training set as requested by target */
2688 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2689 DRM_ERROR("failed to update link training\n");
2695 intel_dp_set_idle_link_train(intel_dp);
2700 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2704 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2706 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2707 DP_TRAINING_PATTERN_DISABLE);
2711 intel_dp_link_down(struct intel_dp *intel_dp)
2713 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2714 enum port port = intel_dig_port->port;
2715 struct drm_device *dev = intel_dig_port->base.base.dev;
2716 struct drm_i915_private *dev_priv = dev->dev_private;
2717 struct intel_crtc *intel_crtc =
2718 to_intel_crtc(intel_dig_port->base.base.crtc);
2719 uint32_t DP = intel_dp->DP;
2722 * DDI code has a strict mode set sequence and we should try to respect
2723 * it, otherwise we might hang the machine in many different ways. So we
2724 * really should be disabling the port only on a complete crtc_disable
2725 * sequence. This function is just called under two conditions on DDI
2727 * - Link train failed while doing crtc_enable, and on this case we
2728 * really should respect the mode set sequence and wait for a
2730 * - Someone turned the monitor off and intel_dp_check_link_status
2731 * called us. We don't need to disable the whole port on this case, so
2732 * when someone turns the monitor on again,
2733 * intel_ddi_prepare_link_retrain will take care of redoing the link
2739 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2742 DRM_DEBUG_KMS("\n");
2744 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2745 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2746 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2748 DP &= ~DP_LINK_TRAIN_MASK;
2749 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2751 POSTING_READ(intel_dp->output_reg);
2753 /* We don't really know why we're doing this */
2754 intel_wait_for_vblank(dev, intel_crtc->pipe);
2756 if (HAS_PCH_IBX(dev) &&
2757 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2758 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2760 /* Hardware workaround: leaving our transcoder select
2761 * set to transcoder B while it's off will prevent the
2762 * corresponding HDMI output on transcoder A.
2764 * Combine this with another hardware workaround:
2765 * transcoder select bit can only be cleared while the
2768 DP &= ~DP_PIPEB_SELECT;
2769 I915_WRITE(intel_dp->output_reg, DP);
2771 /* Changes to enable or select take place the vblank
2772 * after being written.
2774 if (WARN_ON(crtc == NULL)) {
2775 /* We should never try to disable a port without a crtc
2776 * attached. For paranoia keep the code around for a
2778 POSTING_READ(intel_dp->output_reg);
2781 intel_wait_for_vblank(dev, intel_crtc->pipe);
2784 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2785 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2786 POSTING_READ(intel_dp->output_reg);
2787 msleep(intel_dp->panel_power_down_delay);
2791 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2793 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2794 struct drm_device *dev = dig_port->base.base.dev;
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2797 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2799 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2800 sizeof(intel_dp->dpcd)) < 0)
2801 return false; /* aux transfer failed */
2803 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2804 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2805 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2807 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2808 return false; /* DPCD not present */
2810 /* Check if the panel supports PSR */
2811 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2812 if (is_edp(intel_dp)) {
2813 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2815 sizeof(intel_dp->psr_dpcd));
2816 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2817 dev_priv->psr.sink_support = true;
2818 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2822 /* Training Pattern 3 support */
2823 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2824 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2825 intel_dp->use_tps3 = true;
2826 DRM_DEBUG_KMS("Displayport TPS3 supported");
2828 intel_dp->use_tps3 = false;
2830 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2831 DP_DWN_STRM_PORT_PRESENT))
2832 return true; /* native DP sink */
2834 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2835 return true; /* no per-port downstream info */
2837 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2838 intel_dp->downstream_ports,
2839 DP_MAX_DOWNSTREAM_PORTS) < 0)
2840 return false; /* downstream port status fetch failed */
2846 intel_dp_probe_oui(struct intel_dp *intel_dp)
2850 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2853 intel_edp_panel_vdd_on(intel_dp);
2855 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
2856 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2857 buf[0], buf[1], buf[2]);
2859 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
2860 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2861 buf[0], buf[1], buf[2]);
2863 edp_panel_vdd_off(intel_dp, false);
2866 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2868 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2869 struct drm_device *dev = intel_dig_port->base.base.dev;
2870 struct intel_crtc *intel_crtc =
2871 to_intel_crtc(intel_dig_port->base.base.crtc);
2874 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
2877 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2880 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2881 DP_TEST_SINK_START) < 0)
2884 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2885 intel_wait_for_vblank(dev, intel_crtc->pipe);
2886 intel_wait_for_vblank(dev, intel_crtc->pipe);
2888 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
2891 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
2896 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2898 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2899 DP_DEVICE_SERVICE_IRQ_VECTOR,
2900 sink_irq_vector, 1) == 1;
2904 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2906 /* NAK by default */
2907 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
2911 * According to DP spec
2914 * 2. Configure link according to Receiver Capabilities
2915 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2916 * 4. Check link status on receipt of hot-plug interrupt
2920 intel_dp_check_link_status(struct intel_dp *intel_dp)
2922 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2924 u8 link_status[DP_LINK_STATUS_SIZE];
2926 if (!intel_encoder->connectors_active)
2929 if (WARN_ON(!intel_encoder->base.crtc))
2932 /* Try to read receiver status if the link appears to be up */
2933 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2937 /* Now read the DPCD to see if it's actually running */
2938 if (!intel_dp_get_dpcd(intel_dp)) {
2942 /* Try to read the source of the interrupt */
2943 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2944 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2945 /* Clear interrupt source */
2946 drm_dp_dpcd_writeb(&intel_dp->aux,
2947 DP_DEVICE_SERVICE_IRQ_VECTOR,
2950 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2951 intel_dp_handle_test_request(intel_dp);
2952 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2953 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2956 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2957 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2958 drm_get_encoder_name(&intel_encoder->base));
2959 intel_dp_start_link_train(intel_dp);
2960 intel_dp_complete_link_train(intel_dp);
2961 intel_dp_stop_link_train(intel_dp);
2965 /* XXX this is probably wrong for multiple downstream ports */
2966 static enum drm_connector_status
2967 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2969 uint8_t *dpcd = intel_dp->dpcd;
2972 if (!intel_dp_get_dpcd(intel_dp))
2973 return connector_status_disconnected;
2975 /* if there's no downstream port, we're done */
2976 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2977 return connector_status_connected;
2979 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2980 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2981 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2984 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
2986 return connector_status_unknown;
2988 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2989 : connector_status_disconnected;
2992 /* If no HPD, poke DDC gently */
2993 if (drm_probe_ddc(&intel_dp->aux.ddc))
2994 return connector_status_connected;
2996 /* Well we tried, say unknown for unreliable port types */
2997 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2998 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2999 if (type == DP_DS_PORT_TYPE_VGA ||
3000 type == DP_DS_PORT_TYPE_NON_EDID)
3001 return connector_status_unknown;
3003 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3004 DP_DWN_STRM_PORT_TYPE_MASK;
3005 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3006 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3007 return connector_status_unknown;
3010 /* Anything else is out of spec, warn and ignore */
3011 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3012 return connector_status_disconnected;
3015 static enum drm_connector_status
3016 ironlake_dp_detect(struct intel_dp *intel_dp)
3018 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3021 enum drm_connector_status status;
3023 /* Can't disconnect eDP, but you can close the lid... */
3024 if (is_edp(intel_dp)) {
3025 status = intel_panel_detect(dev);
3026 if (status == connector_status_unknown)
3027 status = connector_status_connected;
3031 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3032 return connector_status_disconnected;
3034 return intel_dp_detect_dpcd(intel_dp);
3037 static enum drm_connector_status
3038 g4x_dp_detect(struct intel_dp *intel_dp)
3040 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3045 /* Can't disconnect eDP, but you can close the lid... */
3046 if (is_edp(intel_dp)) {
3047 enum drm_connector_status status;
3049 status = intel_panel_detect(dev);
3050 if (status == connector_status_unknown)
3051 status = connector_status_connected;
3055 if (IS_VALLEYVIEW(dev)) {
3056 switch (intel_dig_port->port) {
3058 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3061 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3064 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3067 return connector_status_unknown;
3070 switch (intel_dig_port->port) {
3072 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3075 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3078 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3081 return connector_status_unknown;
3085 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3086 return connector_status_disconnected;
3088 return intel_dp_detect_dpcd(intel_dp);
3091 static struct edid *
3092 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3094 struct intel_connector *intel_connector = to_intel_connector(connector);
3096 /* use cached edid if we have one */
3097 if (intel_connector->edid) {
3099 if (IS_ERR(intel_connector->edid))
3102 return drm_edid_duplicate(intel_connector->edid);
3105 return drm_get_edid(connector, adapter);
3109 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3111 struct intel_connector *intel_connector = to_intel_connector(connector);
3113 /* use cached edid if we have one */
3114 if (intel_connector->edid) {
3116 if (IS_ERR(intel_connector->edid))
3119 return intel_connector_update_modes(connector,
3120 intel_connector->edid);
3123 return intel_ddc_get_modes(connector, adapter);
3126 static enum drm_connector_status
3127 intel_dp_detect(struct drm_connector *connector, bool force)
3129 struct intel_dp *intel_dp = intel_attached_dp(connector);
3130 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3131 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3132 struct drm_device *dev = connector->dev;
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134 enum drm_connector_status status;
3135 enum intel_display_power_domain power_domain;
3136 struct edid *edid = NULL;
3138 intel_runtime_pm_get(dev_priv);
3140 power_domain = intel_display_port_power_domain(intel_encoder);
3141 intel_display_power_get(dev_priv, power_domain);
3143 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3144 connector->base.id, drm_get_connector_name(connector));
3146 intel_dp->has_audio = false;
3148 if (HAS_PCH_SPLIT(dev))
3149 status = ironlake_dp_detect(intel_dp);
3151 status = g4x_dp_detect(intel_dp);
3153 if (status != connector_status_connected)
3156 intel_dp_probe_oui(intel_dp);
3158 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3159 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3161 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3163 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3168 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3169 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3170 status = connector_status_connected;
3173 intel_display_power_put(dev_priv, power_domain);
3175 intel_runtime_pm_put(dev_priv);
3180 static int intel_dp_get_modes(struct drm_connector *connector)
3182 struct intel_dp *intel_dp = intel_attached_dp(connector);
3183 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3184 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3185 struct intel_connector *intel_connector = to_intel_connector(connector);
3186 struct drm_device *dev = connector->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 enum intel_display_power_domain power_domain;
3191 /* We should parse the EDID data and find out if it has an audio sink
3194 power_domain = intel_display_port_power_domain(intel_encoder);
3195 intel_display_power_get(dev_priv, power_domain);
3197 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3198 intel_display_power_put(dev_priv, power_domain);
3202 /* if eDP has no EDID, fall back to fixed mode */
3203 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3204 struct drm_display_mode *mode;
3205 mode = drm_mode_duplicate(dev,
3206 intel_connector->panel.fixed_mode);
3208 drm_mode_probed_add(connector, mode);
3216 intel_dp_detect_audio(struct drm_connector *connector)
3218 struct intel_dp *intel_dp = intel_attached_dp(connector);
3219 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3220 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3221 struct drm_device *dev = connector->dev;
3222 struct drm_i915_private *dev_priv = dev->dev_private;
3223 enum intel_display_power_domain power_domain;
3225 bool has_audio = false;
3227 power_domain = intel_display_port_power_domain(intel_encoder);
3228 intel_display_power_get(dev_priv, power_domain);
3230 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3232 has_audio = drm_detect_monitor_audio(edid);
3236 intel_display_power_put(dev_priv, power_domain);
3242 intel_dp_set_property(struct drm_connector *connector,
3243 struct drm_property *property,
3246 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3247 struct intel_connector *intel_connector = to_intel_connector(connector);
3248 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3249 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3252 ret = drm_object_property_set_value(&connector->base, property, val);
3256 if (property == dev_priv->force_audio_property) {
3260 if (i == intel_dp->force_audio)
3263 intel_dp->force_audio = i;
3265 if (i == HDMI_AUDIO_AUTO)
3266 has_audio = intel_dp_detect_audio(connector);
3268 has_audio = (i == HDMI_AUDIO_ON);
3270 if (has_audio == intel_dp->has_audio)
3273 intel_dp->has_audio = has_audio;
3277 if (property == dev_priv->broadcast_rgb_property) {
3278 bool old_auto = intel_dp->color_range_auto;
3279 uint32_t old_range = intel_dp->color_range;
3282 case INTEL_BROADCAST_RGB_AUTO:
3283 intel_dp->color_range_auto = true;
3285 case INTEL_BROADCAST_RGB_FULL:
3286 intel_dp->color_range_auto = false;
3287 intel_dp->color_range = 0;
3289 case INTEL_BROADCAST_RGB_LIMITED:
3290 intel_dp->color_range_auto = false;
3291 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3297 if (old_auto == intel_dp->color_range_auto &&
3298 old_range == intel_dp->color_range)
3304 if (is_edp(intel_dp) &&
3305 property == connector->dev->mode_config.scaling_mode_property) {
3306 if (val == DRM_MODE_SCALE_NONE) {
3307 DRM_DEBUG_KMS("no scaling not supported\n");
3311 if (intel_connector->panel.fitting_mode == val) {
3312 /* the eDP scaling property is not changed */
3315 intel_connector->panel.fitting_mode = val;
3323 if (intel_encoder->base.crtc)
3324 intel_crtc_restore_mode(intel_encoder->base.crtc);
3330 intel_dp_connector_destroy(struct drm_connector *connector)
3332 struct intel_connector *intel_connector = to_intel_connector(connector);
3334 if (!IS_ERR_OR_NULL(intel_connector->edid))
3335 kfree(intel_connector->edid);
3337 /* Can't call is_edp() since the encoder may have been destroyed
3339 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3340 intel_panel_fini(&intel_connector->panel);
3342 drm_connector_cleanup(connector);
3346 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3348 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3349 struct intel_dp *intel_dp = &intel_dig_port->dp;
3350 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3352 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3353 drm_encoder_cleanup(encoder);
3354 if (is_edp(intel_dp)) {
3355 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3356 mutex_lock(&dev->mode_config.mutex);
3357 edp_panel_vdd_off_sync(intel_dp);
3358 mutex_unlock(&dev->mode_config.mutex);
3360 kfree(intel_dig_port);
3363 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3364 .dpms = intel_connector_dpms,
3365 .detect = intel_dp_detect,
3366 .fill_modes = drm_helper_probe_single_connector_modes,
3367 .set_property = intel_dp_set_property,
3368 .destroy = intel_dp_connector_destroy,
3371 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3372 .get_modes = intel_dp_get_modes,
3373 .mode_valid = intel_dp_mode_valid,
3374 .best_encoder = intel_best_encoder,
3377 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3378 .destroy = intel_dp_encoder_destroy,
3382 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3384 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3386 intel_dp_check_link_status(intel_dp);
3389 /* Return which DP Port should be selected for Transcoder DP control */
3391 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3393 struct drm_device *dev = crtc->dev;
3394 struct intel_encoder *intel_encoder;
3395 struct intel_dp *intel_dp;
3397 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3398 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3400 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3401 intel_encoder->type == INTEL_OUTPUT_EDP)
3402 return intel_dp->output_reg;
3408 /* check the VBT to see whether the eDP is on DP-D port */
3409 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3411 struct drm_i915_private *dev_priv = dev->dev_private;
3412 union child_device_config *p_child;
3414 static const short port_mapping[] = {
3415 [PORT_B] = PORT_IDPB,
3416 [PORT_C] = PORT_IDPC,
3417 [PORT_D] = PORT_IDPD,
3423 if (!dev_priv->vbt.child_dev_num)
3426 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3427 p_child = dev_priv->vbt.child_dev + i;
3429 if (p_child->common.dvo_port == port_mapping[port] &&
3430 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3431 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3438 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3440 struct intel_connector *intel_connector = to_intel_connector(connector);
3442 intel_attach_force_audio_property(connector);
3443 intel_attach_broadcast_rgb_property(connector);
3444 intel_dp->color_range_auto = true;
3446 if (is_edp(intel_dp)) {
3447 drm_mode_create_scaling_mode_property(connector->dev);
3448 drm_object_attach_property(
3450 connector->dev->mode_config.scaling_mode_property,
3451 DRM_MODE_SCALE_ASPECT);
3452 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3456 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3458 intel_dp->last_power_cycle = jiffies;
3459 intel_dp->last_power_on = jiffies;
3460 intel_dp->last_backlight_off = jiffies;
3464 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3465 struct intel_dp *intel_dp,
3466 struct edp_power_seq *out)
3468 struct drm_i915_private *dev_priv = dev->dev_private;
3469 struct edp_power_seq cur, vbt, spec, final;
3470 u32 pp_on, pp_off, pp_div, pp;
3471 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3473 if (HAS_PCH_SPLIT(dev)) {
3474 pp_ctrl_reg = PCH_PP_CONTROL;
3475 pp_on_reg = PCH_PP_ON_DELAYS;
3476 pp_off_reg = PCH_PP_OFF_DELAYS;
3477 pp_div_reg = PCH_PP_DIVISOR;
3479 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3481 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3482 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3483 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3484 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3487 /* Workaround: Need to write PP_CONTROL with the unlock key as
3488 * the very first thing. */
3489 pp = ironlake_get_pp_control(intel_dp);
3490 I915_WRITE(pp_ctrl_reg, pp);
3492 pp_on = I915_READ(pp_on_reg);
3493 pp_off = I915_READ(pp_off_reg);
3494 pp_div = I915_READ(pp_div_reg);
3496 /* Pull timing values out of registers */
3497 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3498 PANEL_POWER_UP_DELAY_SHIFT;
3500 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3501 PANEL_LIGHT_ON_DELAY_SHIFT;
3503 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3504 PANEL_LIGHT_OFF_DELAY_SHIFT;
3506 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3507 PANEL_POWER_DOWN_DELAY_SHIFT;
3509 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3510 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3512 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3513 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3515 vbt = dev_priv->vbt.edp_pps;
3517 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3518 * our hw here, which are all in 100usec. */
3519 spec.t1_t3 = 210 * 10;
3520 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3521 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3522 spec.t10 = 500 * 10;
3523 /* This one is special and actually in units of 100ms, but zero
3524 * based in the hw (so we need to add 100 ms). But the sw vbt
3525 * table multiplies it with 1000 to make it in units of 100usec,
3527 spec.t11_t12 = (510 + 100) * 10;
3529 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3530 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3532 /* Use the max of the register settings and vbt. If both are
3533 * unset, fall back to the spec limits. */
3534 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3536 max(cur.field, vbt.field))
3537 assign_final(t1_t3);
3541 assign_final(t11_t12);
3544 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3545 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3546 intel_dp->backlight_on_delay = get_delay(t8);
3547 intel_dp->backlight_off_delay = get_delay(t9);
3548 intel_dp->panel_power_down_delay = get_delay(t10);
3549 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3552 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3553 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3554 intel_dp->panel_power_cycle_delay);
3556 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3557 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3564 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3565 struct intel_dp *intel_dp,
3566 struct edp_power_seq *seq)
3568 struct drm_i915_private *dev_priv = dev->dev_private;
3569 u32 pp_on, pp_off, pp_div, port_sel = 0;
3570 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3571 int pp_on_reg, pp_off_reg, pp_div_reg;
3573 if (HAS_PCH_SPLIT(dev)) {
3574 pp_on_reg = PCH_PP_ON_DELAYS;
3575 pp_off_reg = PCH_PP_OFF_DELAYS;
3576 pp_div_reg = PCH_PP_DIVISOR;
3578 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3580 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3581 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3582 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3586 * And finally store the new values in the power sequencer. The
3587 * backlight delays are set to 1 because we do manual waits on them. For
3588 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3589 * we'll end up waiting for the backlight off delay twice: once when we
3590 * do the manual sleep, and once when we disable the panel and wait for
3591 * the PP_STATUS bit to become zero.
3593 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3594 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3595 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3596 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3597 /* Compute the divisor for the pp clock, simply match the Bspec
3599 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3600 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3601 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3603 /* Haswell doesn't have any port selection bits for the panel
3604 * power sequencer any more. */
3605 if (IS_VALLEYVIEW(dev)) {
3606 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3607 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3609 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3610 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3611 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3612 port_sel = PANEL_PORT_SELECT_DPA;
3614 port_sel = PANEL_PORT_SELECT_DPD;
3619 I915_WRITE(pp_on_reg, pp_on);
3620 I915_WRITE(pp_off_reg, pp_off);
3621 I915_WRITE(pp_div_reg, pp_div);
3623 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3624 I915_READ(pp_on_reg),
3625 I915_READ(pp_off_reg),
3626 I915_READ(pp_div_reg));
3629 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3630 struct intel_connector *intel_connector,
3631 struct edp_power_seq *power_seq)
3633 struct drm_connector *connector = &intel_connector->base;
3634 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3635 struct drm_device *dev = intel_dig_port->base.base.dev;
3636 struct drm_i915_private *dev_priv = dev->dev_private;
3637 struct drm_display_mode *fixed_mode = NULL;
3639 struct drm_display_mode *scan;
3642 if (!is_edp(intel_dp))
3645 /* Cache DPCD and EDID for edp. */
3646 intel_edp_panel_vdd_on(intel_dp);
3647 has_dpcd = intel_dp_get_dpcd(intel_dp);
3648 edp_panel_vdd_off(intel_dp, false);
3651 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3652 dev_priv->no_aux_handshake =
3653 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3654 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3656 /* if this fails, presume the device is a ghost */
3657 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3661 /* We now know it's not a ghost, init power sequence regs. */
3662 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3664 mutex_lock(&dev->mode_config.mutex);
3665 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
3667 if (drm_add_edid_modes(connector, edid)) {
3668 drm_mode_connector_update_edid_property(connector,
3670 drm_edid_to_eld(connector, edid);
3673 edid = ERR_PTR(-EINVAL);
3676 edid = ERR_PTR(-ENOENT);
3678 intel_connector->edid = edid;
3680 /* prefer fixed mode from EDID if available */
3681 list_for_each_entry(scan, &connector->probed_modes, head) {
3682 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3683 fixed_mode = drm_mode_duplicate(dev, scan);
3688 /* fallback to VBT if available for eDP */
3689 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3690 fixed_mode = drm_mode_duplicate(dev,
3691 dev_priv->vbt.lfp_lvds_vbt_mode);
3693 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3695 mutex_unlock(&dev->mode_config.mutex);
3697 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
3698 intel_panel_setup_backlight(connector);
3704 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3705 struct intel_connector *intel_connector)
3707 struct drm_connector *connector = &intel_connector->base;
3708 struct intel_dp *intel_dp = &intel_dig_port->dp;
3709 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3710 struct drm_device *dev = intel_encoder->base.dev;
3711 struct drm_i915_private *dev_priv = dev->dev_private;
3712 enum port port = intel_dig_port->port;
3713 struct edp_power_seq power_seq = { 0 };
3716 /* intel_dp vfuncs */
3717 if (IS_VALLEYVIEW(dev))
3718 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3719 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3720 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3721 else if (HAS_PCH_SPLIT(dev))
3722 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3724 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3726 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3728 /* Preserve the current hw state. */
3729 intel_dp->DP = I915_READ(intel_dp->output_reg);
3730 intel_dp->attached_connector = intel_connector;
3732 if (intel_dp_is_edp(dev, port))
3733 type = DRM_MODE_CONNECTOR_eDP;
3735 type = DRM_MODE_CONNECTOR_DisplayPort;
3738 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3739 * for DP the encoder type can be set by the caller to
3740 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3742 if (type == DRM_MODE_CONNECTOR_eDP)
3743 intel_encoder->type = INTEL_OUTPUT_EDP;
3745 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3746 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3749 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3750 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3752 connector->interlace_allowed = true;
3753 connector->doublescan_allowed = 0;
3755 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3756 edp_panel_vdd_work);
3758 intel_connector_attach_encoder(intel_connector, intel_encoder);
3759 drm_sysfs_connector_add(connector);
3762 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3764 intel_connector->get_hw_state = intel_connector_get_hw_state;
3765 intel_connector->unregister = intel_dp_connector_unregister;
3767 /* Set up the hotplug pin. */
3770 intel_encoder->hpd_pin = HPD_PORT_A;
3773 intel_encoder->hpd_pin = HPD_PORT_B;
3776 intel_encoder->hpd_pin = HPD_PORT_C;
3779 intel_encoder->hpd_pin = HPD_PORT_D;
3785 if (is_edp(intel_dp)) {
3786 intel_dp_init_panel_power_timestamps(intel_dp);
3787 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3790 intel_dp_aux_init(intel_dp, intel_connector);
3792 intel_dp->psr_setup_done = false;
3794 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3795 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3796 if (is_edp(intel_dp)) {
3797 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3798 mutex_lock(&dev->mode_config.mutex);
3799 edp_panel_vdd_off_sync(intel_dp);
3800 mutex_unlock(&dev->mode_config.mutex);
3802 drm_sysfs_connector_remove(connector);
3803 drm_connector_cleanup(connector);
3807 intel_dp_add_properties(intel_dp, connector);
3809 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3810 * 0xd. Failure to do so will result in spurious interrupts being
3811 * generated on the port when a cable is not attached.
3813 if (IS_G4X(dev) && !IS_GM45(dev)) {
3814 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3815 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3822 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3824 struct intel_digital_port *intel_dig_port;
3825 struct intel_encoder *intel_encoder;
3826 struct drm_encoder *encoder;
3827 struct intel_connector *intel_connector;
3829 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3830 if (!intel_dig_port)
3833 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3834 if (!intel_connector) {
3835 kfree(intel_dig_port);
3839 intel_encoder = &intel_dig_port->base;
3840 encoder = &intel_encoder->base;
3842 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3843 DRM_MODE_ENCODER_TMDS);
3845 intel_encoder->compute_config = intel_dp_compute_config;
3846 intel_encoder->mode_set = intel_dp_mode_set;
3847 intel_encoder->disable = intel_disable_dp;
3848 intel_encoder->post_disable = intel_post_disable_dp;
3849 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3850 intel_encoder->get_config = intel_dp_get_config;
3851 if (IS_VALLEYVIEW(dev)) {
3852 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3853 intel_encoder->pre_enable = vlv_pre_enable_dp;
3854 intel_encoder->enable = vlv_enable_dp;
3856 intel_encoder->pre_enable = g4x_pre_enable_dp;
3857 intel_encoder->enable = g4x_enable_dp;
3860 intel_dig_port->port = port;
3861 intel_dig_port->dp.output_reg = output_reg;
3863 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3864 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3865 intel_encoder->cloneable = 0;
3866 intel_encoder->hot_plug = intel_dp_hot_plug;
3868 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3869 drm_encoder_cleanup(encoder);
3870 kfree(intel_dig_port);
3871 kfree(intel_connector);