drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include "intel_drv.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  45
  46 /* Compliance test status bits  */
  47 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  48 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  50 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51
  52 struct dp_link_dpll {
  53         int clock;
  54         struct dpll dpll;
  55 };
  56
  57 static const struct dp_link_dpll gen4_dpll[] = {
  58         { 162000,
  59                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  60         { 270000,
  61                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  62 };
  63
  64 static const struct dp_link_dpll pch_dpll[] = {
  65         { 162000,
  66                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  67         { 270000,
  68                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  69 };
  70
  71 static const struct dp_link_dpll vlv_dpll[] = {
  72         { 162000,
  73                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  74         { 270000,
  75                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  76 };
  77
  78 /*
  79  * CHV supports eDP 1.4 that have  more link rates.
  80  * Below only provides the fixed rate but exclude variable rate.
  81  */
  82 static const struct dp_link_dpll chv_dpll[] = {
  83         /*
  84          * CHV requires to program fractional division for m2.
  85          * m2 is stored in fixed point format using formula below
  86          * (m2_int << 22) | m2_fraction
  87          */
  88         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  89                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  90         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  92         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  93                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  94 };
  95
  96 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int skl_rates[] = { 162000, 216000, 270000,
  99                                   324000, 432000, 540000 };
 100 static const int cnl_rates[] = { 162000, 216000, 270000,
 101                                  324000, 432000, 540000,
 102                                  648000, 810000 };
 103 static const int default_rates[] = { 162000, 270000, 540000 };
 104
 105 /**
 106  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 107  * @intel_dp: DP struct
 108  *
 109  * If a CPU or PCH DP output is attached to an eDP panel, this function
 110  * will return true, and false otherwise.
 111  */
 112 static bool is_edp(struct intel_dp *intel_dp)
 113 {
 114         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 115
 116         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 117 }
 118
 119 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 120 {
 121         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 122
 123         return intel_dig_port->base.base.dev;
 124 }
 125
 126 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 127 {
 128         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 129 }
 130
 131 static void intel_dp_link_down(struct intel_dp *intel_dp);
 132 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 133 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 134 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 135 static void vlv_steal_power_sequencer(struct drm_device *dev,
 136                                       enum pipe pipe);
 137 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 138
 139 static int intel_dp_num_rates(u8 link_bw_code)
 140 {
 141         switch (link_bw_code) {
 142         default:
 143                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 144                      link_bw_code);
 145         case DP_LINK_BW_1_62:
 146                 return 1;
 147         case DP_LINK_BW_2_7:
 148                 return 2;
 149         case DP_LINK_BW_5_4:
 150                 return 3;
 151         }
 152 }
 153
 154 /* update sink rates from dpcd */
 155 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 156 {
 157         int i, num_rates;
 158
 159         num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 160
 161         for (i = 0; i < num_rates; i++)
 162                 intel_dp->sink_rates[i] = default_rates[i];
 163
 164         intel_dp->num_sink_rates = num_rates;
 165 }
 166
 167 /* Theoretical max between source and sink */
 168 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 169 {
 170         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 171 }
 172
 173 /* Theoretical max between source and sink */
 174 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 175 {
 176         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 177         int source_max = intel_dig_port->max_lanes;
 178         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 179
 180         return min(source_max, sink_max);
 181 }
 182
 183 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 184 {
 185         return intel_dp->max_link_lane_count;
 186 }
 187
 188 int
 189 intel_dp_link_required(int pixel_clock, int bpp)
 190 {
 191         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 192         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 193 }
 194
 195 int
 196 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 197 {
 198         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 199          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 200          * is transmitted every LS_Clk per lane, there is no need to account for
 201          * the channel encoding that is done in the PHY layer here.
 202          */
 203
 204         return max_link_clock * max_lanes;
 205 }
 206
 207 static int
 208 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 209 {
 210         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 211         struct intel_encoder *encoder = &intel_dig_port->base;
 212         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 213         int max_dotclk = dev_priv->max_dotclk_freq;
 214         int ds_max_dotclk;
 215
 216         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 217
 218         if (type != DP_DS_PORT_TYPE_VGA)
 219                 return max_dotclk;
 220
 221         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 222                                                     intel_dp->downstream_ports);
 223
 224         if (ds_max_dotclk != 0)
 225                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 226
 227         return max_dotclk;
 228 }
 229
 230 static void
 231 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 232 {
 233         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 234         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 235         enum port port = dig_port->port;
 236         const int *source_rates;
 237         int size;
 238         u32 voltage;
 239
 240         /* This should only be done once */
 241         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 242
 243         if (IS_GEN9_LP(dev_priv)) {
 244                 source_rates = bxt_rates;
 245                 size = ARRAY_SIZE(bxt_rates);
 246         } else if (IS_CANNONLAKE(dev_priv)) {
 247                 source_rates = cnl_rates;
 248                 size = ARRAY_SIZE(cnl_rates);
 249                 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 250                 if (port == PORT_A || port == PORT_D ||
 251                     voltage == VOLTAGE_INFO_0_85V)
 252                         size -= 2;
 253         } else if (IS_GEN9_BC(dev_priv)) {
 254                 source_rates = skl_rates;
 255                 size = ARRAY_SIZE(skl_rates);
 256         } else {
 257                 source_rates = default_rates;
 258                 size = ARRAY_SIZE(default_rates);
 259         }
 260
 261         /* This depends on the fact that 5.4 is last value in the array */
 262         if (!intel_dp_source_supports_hbr2(intel_dp))
 263                 size--;
 264
 265         intel_dp->source_rates = source_rates;
 266         intel_dp->num_source_rates = size;
 267 }
 268
 269 static int intersect_rates(const int *source_rates, int source_len,
 270                            const int *sink_rates, int sink_len,
 271                            int *common_rates)
 272 {
 273         int i = 0, j = 0, k = 0;
 274
 275         while (i < source_len && j < sink_len) {
 276                 if (source_rates[i] == sink_rates[j]) {
 277                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 278                                 return k;
 279                         common_rates[k] = source_rates[i];
 280                         ++k;
 281                         ++i;
 282                         ++j;
 283                 } else if (source_rates[i] < sink_rates[j]) {
 284                         ++i;
 285                 } else {
 286                         ++j;
 287                 }
 288         }
 289         return k;
 290 }
 291
 292 /* return index of rate in rates array, or -1 if not found */
 293 static int intel_dp_rate_index(const int *rates, int len, int rate)
 294 {
 295         int i;
 296
 297         for (i = 0; i < len; i++)
 298                 if (rate == rates[i])
 299                         return i;
 300
 301         return -1;
 302 }
 303
 304 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 305 {
 306         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 307
 308         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 309                                                      intel_dp->num_source_rates,
 310                                                      intel_dp->sink_rates,
 311                                                      intel_dp->num_sink_rates,
 312                                                      intel_dp->common_rates);
 313
 314         /* Paranoia, there should always be something in common. */
 315         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 316                 intel_dp->common_rates[0] = default_rates[0];
 317                 intel_dp->num_common_rates = 1;
 318         }
 319 }
 320
 321 /* get length of common rates potentially limited by max_rate */
 322 static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
 323                                           int max_rate)
 324 {
 325         const int *common_rates = intel_dp->common_rates;
 326         int i, common_len = intel_dp->num_common_rates;
 327
 328         /* Limit results by potentially reduced max rate */
 329         for (i = 0; i < common_len; i++) {
 330                 if (common_rates[common_len - i - 1] <= max_rate)
 331                         return common_len - i;
 332         }
 333
 334         return 0;
 335 }
 336
 337 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 338                                        uint8_t lane_count)
 339 {
 340         /*
 341          * FIXME: we need to synchronize the current link parameters with
 342          * hardware readout. Currently fast link training doesn't work on
 343          * boot-up.
 344          */
 345         if (link_rate == 0 ||
 346             link_rate > intel_dp->max_link_rate)
 347                 return false;
 348
 349         if (lane_count == 0 ||
 350             lane_count > intel_dp_max_lane_count(intel_dp))
 351                 return false;
 352
 353         return true;
 354 }
 355
 356 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 357                                             int link_rate, uint8_t lane_count)
 358 {
 359         int index;
 360
 361         index = intel_dp_rate_index(intel_dp->common_rates,
 362                                     intel_dp->num_common_rates,
 363                                     link_rate);
 364         if (index > 0) {
 365                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 366                 intel_dp->max_link_lane_count = lane_count;
 367         } else if (lane_count > 1) {
 368                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 369                 intel_dp->max_link_lane_count = lane_count >> 1;
 370         } else {
 371                 DRM_ERROR("Link Training Unsuccessful\n");
 372                 return -1;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static enum drm_mode_status
 379 intel_dp_mode_valid(struct drm_connector *connector,
 380                     struct drm_display_mode *mode)
 381 {
 382         struct intel_dp *intel_dp = intel_attached_dp(connector);
 383         struct intel_connector *intel_connector = to_intel_connector(connector);
 384         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 385         int target_clock = mode->clock;
 386         int max_rate, mode_rate, max_lanes, max_link_clock;
 387         int max_dotclk;
 388
 389         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 390
 391         if (is_edp(intel_dp) && fixed_mode) {
 392                 if (mode->hdisplay > fixed_mode->hdisplay)
 393                         return MODE_PANEL;
 394
 395                 if (mode->vdisplay > fixed_mode->vdisplay)
 396                         return MODE_PANEL;
 397
 398                 target_clock = fixed_mode->clock;
 399         }
 400
 401         max_link_clock = intel_dp_max_link_rate(intel_dp);
 402         max_lanes = intel_dp_max_lane_count(intel_dp);
 403
 404         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 405         mode_rate = intel_dp_link_required(target_clock, 18);
 406
 407         if (mode_rate > max_rate || target_clock > max_dotclk)
 408                 return MODE_CLOCK_HIGH;
 409
 410         if (mode->clock < 10000)
 411                 return MODE_CLOCK_LOW;
 412
 413         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 414                 return MODE_H_ILLEGAL;
 415
 416         return MODE_OK;
 417 }
 418
 419 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 420 {
 421         int     i;
 422         uint32_t v = 0;
 423
 424         if (src_bytes > 4)
 425                 src_bytes = 4;
 426         for (i = 0; i < src_bytes; i++)
 427                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 428         return v;
 429 }
 430
 431 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 432 {
 433         int i;
 434         if (dst_bytes > 4)
 435                 dst_bytes = 4;
 436         for (i = 0; i < dst_bytes; i++)
 437                 dst[i] = src >> ((3-i) * 8);
 438 }
 439
 440 static void
 441 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 442                                     struct intel_dp *intel_dp);
 443 static void
 444 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 445                                               struct intel_dp *intel_dp,
 446                                               bool force_disable_vdd);
 447 static void
 448 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
 449
 450 static void pps_lock(struct intel_dp *intel_dp)
 451 {
 452         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 453         struct intel_encoder *encoder = &intel_dig_port->base;
 454         struct drm_device *dev = encoder->base.dev;
 455         struct drm_i915_private *dev_priv = to_i915(dev);
 456
 457         /*
 458          * See vlv_power_sequencer_reset() why we need
 459          * a power domain reference here.
 460          */
 461         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 462
 463         mutex_lock(&dev_priv->pps_mutex);
 464 }
 465
 466 static void pps_unlock(struct intel_dp *intel_dp)
 467 {
 468         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 469         struct intel_encoder *encoder = &intel_dig_port->base;
 470         struct drm_device *dev = encoder->base.dev;
 471         struct drm_i915_private *dev_priv = to_i915(dev);
 472
 473         mutex_unlock(&dev_priv->pps_mutex);
 474
 475         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 476 }
 477
 478 static void
 479 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 480 {
 481         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 482         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 483         enum pipe pipe = intel_dp->pps_pipe;
 484         bool pll_enabled, release_cl_override = false;
 485         enum dpio_phy phy = DPIO_PHY(pipe);
 486         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 487         uint32_t DP;
 488
 489         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 490                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 491                  pipe_name(pipe), port_name(intel_dig_port->port)))
 492                 return;
 493
 494         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 495                       pipe_name(pipe), port_name(intel_dig_port->port));
 496
 497         /* Preserve the BIOS-computed detected bit. This is
 498          * supposed to be read-only.
 499          */
 500         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 501         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 502         DP |= DP_PORT_WIDTH(1);
 503         DP |= DP_LINK_TRAIN_PAT_1;
 504
 505         if (IS_CHERRYVIEW(dev_priv))
 506                 DP |= DP_PIPE_SELECT_CHV(pipe);
 507         else if (pipe == PIPE_B)
 508                 DP |= DP_PIPEB_SELECT;
 509
 510         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 511
 512         /*
 513          * The DPLL for the pipe must be enabled for this to work.
 514          * So enable temporarily it if it's not already enabled.
 515          */
 516         if (!pll_enabled) {
 517                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 518                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 519
 520                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 521                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 522                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 523                                   pipe_name(pipe));
 524                         return;
 525                 }
 526         }
 527
 528         /*
 529          * Similar magic as in intel_dp_enable_port().
 530          * We _must_ do this port enable + disable trick
 531          * to make this power seqeuencer lock onto the port.
 532          * Otherwise even VDD force bit won't work.
 533          */
 534         I915_WRITE(intel_dp->output_reg, DP);
 535         POSTING_READ(intel_dp->output_reg);
 536
 537         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 538         POSTING_READ(intel_dp->output_reg);
 539
 540         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 541         POSTING_READ(intel_dp->output_reg);
 542
 543         if (!pll_enabled) {
 544                 vlv_force_pll_off(dev_priv, pipe);
 545
 546                 if (release_cl_override)
 547                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 548         }
 549 }
 550
 551 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 552 {
 553         struct intel_encoder *encoder;
 554         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 555
 556         /*
 557          * We don't have power sequencer currently.
 558          * Pick one that's not used by other ports.
 559          */
 560         for_each_intel_encoder(&dev_priv->drm, encoder) {
 561                 struct intel_dp *intel_dp;
 562
 563                 if (encoder->type != INTEL_OUTPUT_DP &&
 564                     encoder->type != INTEL_OUTPUT_EDP)
 565                         continue;
 566
 567                 intel_dp = enc_to_intel_dp(&encoder->base);
 568
 569                 if (encoder->type == INTEL_OUTPUT_EDP) {
 570                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 571                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 572
 573                         if (intel_dp->pps_pipe != INVALID_PIPE)
 574                                 pipes &= ~(1 << intel_dp->pps_pipe);
 575                 } else {
 576                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 577
 578                         if (intel_dp->active_pipe != INVALID_PIPE)
 579                                 pipes &= ~(1 << intel_dp->active_pipe);
 580                 }
 581         }
 582
 583         if (pipes == 0)
 584                 return INVALID_PIPE;
 585
 586         return ffs(pipes) - 1;
 587 }
 588
 589 static enum pipe
 590 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 591 {
 592         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 593         struct drm_device *dev = intel_dig_port->base.base.dev;
 594         struct drm_i915_private *dev_priv = to_i915(dev);
 595         enum pipe pipe;
 596
 597         lockdep_assert_held(&dev_priv->pps_mutex);
 598
 599         /* We should never land here with regular DP ports */
 600         WARN_ON(!is_edp(intel_dp));
 601
 602         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 603                 intel_dp->active_pipe != intel_dp->pps_pipe);
 604
 605         if (intel_dp->pps_pipe != INVALID_PIPE)
 606                 return intel_dp->pps_pipe;
 607
 608         pipe = vlv_find_free_pps(dev_priv);
 609
 610         /*
 611          * Didn't find one. This should not happen since there
 612          * are two power sequencers and up to two eDP ports.
 613          */
 614         if (WARN_ON(pipe == INVALID_PIPE))
 615                 pipe = PIPE_A;
 616
 617         vlv_steal_power_sequencer(dev, pipe);
 618         intel_dp->pps_pipe = pipe;
 619
 620         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 621                       pipe_name(intel_dp->pps_pipe),
 622                       port_name(intel_dig_port->port));
 623
 624         /* init power sequencer on this pipe and port */
 625         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 626         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
 627
 628         /*
 629          * Even vdd force doesn't work until we've made
 630          * the power sequencer lock in on the port.
 631          */
 632         vlv_power_sequencer_kick(intel_dp);
 633
 634         return intel_dp->pps_pipe;
 635 }
 636
 637 static int
 638 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 639 {
 640         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 641         struct drm_device *dev = intel_dig_port->base.base.dev;
 642         struct drm_i915_private *dev_priv = to_i915(dev);
 643
 644         lockdep_assert_held(&dev_priv->pps_mutex);
 645
 646         /* We should never land here with regular DP ports */
 647         WARN_ON(!is_edp(intel_dp));
 648
 649         /*
 650          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 651          * mapping needs to be retrieved from VBT, for now just hard-code to
 652          * use instance #0 always.
 653          */
 654         if (!intel_dp->pps_reset)
 655                 return 0;
 656
 657         intel_dp->pps_reset = false;
 658
 659         /*
 660          * Only the HW needs to be reprogrammed, the SW state is fixed and
 661          * has been setup during connector init.
 662          */
 663         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 664
 665         return 0;
 666 }
 667
 668 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 669                                enum pipe pipe);
 670
 671 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 672                                enum pipe pipe)
 673 {
 674         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 675 }
 676
 677 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 678                                 enum pipe pipe)
 679 {
 680         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 681 }
 682
 683 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 684                          enum pipe pipe)
 685 {
 686         return true;
 687 }
 688
 689 static enum pipe
 690 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 691                      enum port port,
 692                      vlv_pipe_check pipe_check)
 693 {
 694         enum pipe pipe;
 695
 696         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 697                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 698                         PANEL_PORT_SELECT_MASK;
 699
 700                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 701                         continue;
 702
 703                 if (!pipe_check(dev_priv, pipe))
 704                         continue;
 705
 706                 return pipe;
 707         }
 708
 709         return INVALID_PIPE;
 710 }
 711
 712 static void
 713 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 714 {
 715         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 716         struct drm_device *dev = intel_dig_port->base.base.dev;
 717         struct drm_i915_private *dev_priv = to_i915(dev);
 718         enum port port = intel_dig_port->port;
 719
 720         lockdep_assert_held(&dev_priv->pps_mutex);
 721
 722         /* try to find a pipe with this port selected */
 723         /* first pick one where the panel is on */
 724         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 725                                                   vlv_pipe_has_pp_on);
 726         /* didn't find one? pick one where vdd is on */
 727         if (intel_dp->pps_pipe == INVALID_PIPE)
 728                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 729                                                           vlv_pipe_has_vdd_on);
 730         /* didn't find one? pick one with just the correct port */
 731         if (intel_dp->pps_pipe == INVALID_PIPE)
 732                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 733                                                           vlv_pipe_any);
 734
 735         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 736         if (intel_dp->pps_pipe == INVALID_PIPE) {
 737                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 738                               port_name(port));
 739                 return;
 740         }
 741
 742         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 743                       port_name(port), pipe_name(intel_dp->pps_pipe));
 744
 745         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 746         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 747 }
 748
 749 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 750 {
 751         struct drm_device *dev = &dev_priv->drm;
 752         struct intel_encoder *encoder;
 753
 754         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 755                     !IS_GEN9_LP(dev_priv)))
 756                 return;
 757
 758         /*
 759          * We can't grab pps_mutex here due to deadlock with power_domain
 760          * mutex when power_domain functions are called while holding pps_mutex.
 761          * That also means that in order to use pps_pipe the code needs to
 762          * hold both a power domain reference and pps_mutex, and the power domain
 763          * reference get/put must be done while _not_ holding pps_mutex.
 764          * pps_{lock,unlock}() do these steps in the correct order, so one
 765          * should use them always.
 766          */
 767
 768         for_each_intel_encoder(dev, encoder) {
 769                 struct intel_dp *intel_dp;
 770
 771                 if (encoder->type != INTEL_OUTPUT_DP &&
 772                     encoder->type != INTEL_OUTPUT_EDP)
 773                         continue;
 774
 775                 intel_dp = enc_to_intel_dp(&encoder->base);
 776
 777                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 778
 779                 if (encoder->type != INTEL_OUTPUT_EDP)
 780                         continue;
 781
 782                 if (IS_GEN9_LP(dev_priv))
 783                         intel_dp->pps_reset = true;
 784                 else
 785                         intel_dp->pps_pipe = INVALID_PIPE;
 786         }
 787 }
 788
 789 struct pps_registers {
 790         i915_reg_t pp_ctrl;
 791         i915_reg_t pp_stat;
 792         i915_reg_t pp_on;
 793         i915_reg_t pp_off;
 794         i915_reg_t pp_div;
 795 };
 796
 797 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 798                                     struct intel_dp *intel_dp,
 799                                     struct pps_registers *regs)
 800 {
 801         int pps_idx = 0;
 802
 803         memset(regs, 0, sizeof(*regs));
 804
 805         if (IS_GEN9_LP(dev_priv))
 806                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 807         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 808                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 809
 810         regs->pp_ctrl = PP_CONTROL(pps_idx);
 811         regs->pp_stat = PP_STATUS(pps_idx);
 812         regs->pp_on = PP_ON_DELAYS(pps_idx);
 813         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 814         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
 815                 regs->pp_div = PP_DIVISOR(pps_idx);
 816 }
 817
 818 static i915_reg_t
 819 _pp_ctrl_reg(struct intel_dp *intel_dp)
 820 {
 821         struct pps_registers regs;
 822
 823         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 824                                 &regs);
 825
 826         return regs.pp_ctrl;
 827 }
 828
 829 static i915_reg_t
 830 _pp_stat_reg(struct intel_dp *intel_dp)
 831 {
 832         struct pps_registers regs;
 833
 834         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 835                                 &regs);
 836
 837         return regs.pp_stat;
 838 }
 839
 840 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 841    This function only applicable when panel PM state is not to be tracked */
 842 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 843                               void *unused)
 844 {
 845         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 846                                                  edp_notifier);
 847         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 848         struct drm_i915_private *dev_priv = to_i915(dev);
 849
 850         if (!is_edp(intel_dp) || code != SYS_RESTART)
 851                 return 0;
 852
 853         pps_lock(intel_dp);
 854
 855         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 856                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 857                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 858                 u32 pp_div;
 859
 860                 pp_ctrl_reg = PP_CONTROL(pipe);
 861                 pp_div_reg  = PP_DIVISOR(pipe);
 862                 pp_div = I915_READ(pp_div_reg);
 863                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 864
 865                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 866                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 867                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 868                 msleep(intel_dp->panel_power_cycle_delay);
 869         }
 870
 871         pps_unlock(intel_dp);
 872
 873         return 0;
 874 }
 875
 876 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 877 {
 878         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 879         struct drm_i915_private *dev_priv = to_i915(dev);
 880
 881         lockdep_assert_held(&dev_priv->pps_mutex);
 882
 883         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 884             intel_dp->pps_pipe == INVALID_PIPE)
 885                 return false;
 886
 887         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 888 }
 889
 890 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 891 {
 892         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 893         struct drm_i915_private *dev_priv = to_i915(dev);
 894
 895         lockdep_assert_held(&dev_priv->pps_mutex);
 896
 897         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 898             intel_dp->pps_pipe == INVALID_PIPE)
 899                 return false;
 900
 901         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 902 }
 903
 904 static void
 905 intel_dp_check_edp(struct intel_dp *intel_dp)
 906 {
 907         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 908         struct drm_i915_private *dev_priv = to_i915(dev);
 909
 910         if (!is_edp(intel_dp))
 911                 return;
 912
 913         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 914                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 915                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 916                               I915_READ(_pp_stat_reg(intel_dp)),
 917                               I915_READ(_pp_ctrl_reg(intel_dp)));
 918         }
 919 }
 920
 921 static uint32_t
 922 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 923 {
 924         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 925         struct drm_device *dev = intel_dig_port->base.base.dev;
 926         struct drm_i915_private *dev_priv = to_i915(dev);
 927         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 928         uint32_t status;
 929         bool done;
 930
 931 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 932         if (has_aux_irq)
 933                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 934                                           msecs_to_jiffies_timeout(10));
 935         else
 936                 done = wait_for(C, 10) == 0;
 937         if (!done)
 938                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 939                           has_aux_irq);
 940 #undef C
 941
 942         return status;
 943 }
 944
 945 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 946 {
 947         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 948         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 949
 950         if (index)
 951                 return 0;
 952
 953         /*
 954          * The clock divider is based off the hrawclk, and would like to run at
 955          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 956          */
 957         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 958 }
 959
 960 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 961 {
 962         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 963         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 964
 965         if (index)
 966                 return 0;
 967
 968         /*
 969          * The clock divider is based off the cdclk or PCH rawclk, and would
 970          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 971          * divide by 2000 and use that
 972          */
 973         if (intel_dig_port->port == PORT_A)
 974                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 975         else
 976                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 977 }
 978
 979 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 980 {
 981         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 982         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 983
 984         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 985                 /* Workaround for non-ULT HSW */
 986                 switch (index) {
 987                 case 0: return 63;
 988                 case 1: return 72;
 989                 default: return 0;
 990                 }
 991         }
 992
 993         return ilk_get_aux_clock_divider(intel_dp, index);
 994 }
 995
 996 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 997 {
 998         /*
 999          * SKL doesn't need us to program the AUX clock divider (Hardware will
1000          * derive the clock from CDCLK automatically). We still implement the
1001          * get_aux_clock_divider vfunc to plug-in into the existing code.
1002          */
1003         return index ? 0 : 1;
1004 }
1005
1006 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1007                                      bool has_aux_irq,
1008                                      int send_bytes,
1009                                      uint32_t aux_clock_divider)
1010 {
1011         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1012         struct drm_i915_private *dev_priv =
1013                         to_i915(intel_dig_port->base.base.dev);
1014         uint32_t precharge, timeout;
1015
1016         if (IS_GEN6(dev_priv))
1017                 precharge = 3;
1018         else
1019                 precharge = 5;
1020
1021         if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
1022                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1023         else
1024                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1025
1026         return DP_AUX_CH_CTL_SEND_BUSY |
1027                DP_AUX_CH_CTL_DONE |
1028                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1029                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1030                timeout |
1031                DP_AUX_CH_CTL_RECEIVE_ERROR |
1032                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1033                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1034                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1035 }
1036
1037 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1038                                       bool has_aux_irq,
1039                                       int send_bytes,
1040                                       uint32_t unused)
1041 {
1042         return DP_AUX_CH_CTL_SEND_BUSY |
1043                DP_AUX_CH_CTL_DONE |
1044                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1045                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1046                DP_AUX_CH_CTL_TIME_OUT_1600us |
1047                DP_AUX_CH_CTL_RECEIVE_ERROR |
1048                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1049                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1050                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1051 }
1052
1053 static int
1054 intel_dp_aux_ch(struct intel_dp *intel_dp,
1055                 const uint8_t *send, int send_bytes,
1056                 uint8_t *recv, int recv_size)
1057 {
1058         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1059         struct drm_i915_private *dev_priv =
1060                         to_i915(intel_dig_port->base.base.dev);
1061         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1062         uint32_t aux_clock_divider;
1063         int i, ret, recv_bytes;
1064         uint32_t status;
1065         int try, clock = 0;
1066         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1067         bool vdd;
1068
1069         pps_lock(intel_dp);
1070
1071         /*
1072          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1073          * In such cases we want to leave VDD enabled and it's up to upper layers
1074          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1075          * ourselves.
1076          */
1077         vdd = edp_panel_vdd_on(intel_dp);
1078
1079         /* dp aux is extremely sensitive to irq latency, hence request the
1080          * lowest possible wakeup latency and so prevent the cpu from going into
1081          * deep sleep states.
1082          */
1083         pm_qos_update_request(&dev_priv->pm_qos, 0);
1084
1085         intel_dp_check_edp(intel_dp);
1086
1087         /* Try to wait for any previous AUX channel activity */
1088         for (try = 0; try < 3; try++) {
1089                 status = I915_READ_NOTRACE(ch_ctl);
1090                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1091                         break;
1092                 msleep(1);
1093         }
1094
1095         if (try == 3) {
1096                 static u32 last_status = -1;
1097                 const u32 status = I915_READ(ch_ctl);
1098
1099                 if (status != last_status) {
1100                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1101                              status);
1102                         last_status = status;
1103                 }
1104
1105                 ret = -EBUSY;
1106                 goto out;
1107         }
1108
1109         /* Only 5 data registers! */
1110         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1111                 ret = -E2BIG;
1112                 goto out;
1113         }
1114
1115         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1116                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1117                                                           has_aux_irq,
1118                                                           send_bytes,
1119                                                           aux_clock_divider);
1120
1121                 /* Must try at least 3 times according to DP spec */
1122                 for (try = 0; try < 5; try++) {
1123                         /* Load the send data into the aux channel data registers */
1124                         for (i = 0; i < send_bytes; i += 4)
1125                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1126                                            intel_dp_pack_aux(send + i,
1127                                                              send_bytes - i));
1128
1129                         /* Send the command and wait for it to complete */
1130                         I915_WRITE(ch_ctl, send_ctl);
1131
1132                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1133
1134                         /* Clear done status and any errors */
1135                         I915_WRITE(ch_ctl,
1136                                    status |
1137                                    DP_AUX_CH_CTL_DONE |
1138                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1139                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1140
1141                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1142                                 continue;
1143
1144                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1145                          *   400us delay required for errors and timeouts
1146                          *   Timeout errors from the HW already meet this
1147                          *   requirement so skip to next iteration
1148                          */
1149                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1150                                 usleep_range(400, 500);
1151                                 continue;
1152                         }
1153                         if (status & DP_AUX_CH_CTL_DONE)
1154                                 goto done;
1155                 }
1156         }
1157
1158         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1159                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1160                 ret = -EBUSY;
1161                 goto out;
1162         }
1163
1164 done:
1165         /* Check for timeout or receive error.
1166          * Timeouts occur when the sink is not connected
1167          */
1168         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1169                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1170                 ret = -EIO;
1171                 goto out;
1172         }
1173
1174         /* Timeouts occur when the device isn't connected, so they're
1175          * "normal" -- don't fill the kernel log with these */
1176         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1177                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1178                 ret = -ETIMEDOUT;
1179                 goto out;
1180         }
1181
1182         /* Unload any bytes sent back from the other side */
1183         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1184                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1185
1186         /*
1187          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1188          * We have no idea of what happened so we return -EBUSY so
1189          * drm layer takes care for the necessary retries.
1190          */
1191         if (recv_bytes == 0 || recv_bytes > 20) {
1192                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1193                               recv_bytes);
1194                 /*
1195                  * FIXME: This patch was created on top of a series that
1196                  * organize the retries at drm level. There EBUSY should
1197                  * also take care for 1ms wait before retrying.
1198                  * That aux retries re-org is still needed and after that is
1199                  * merged we remove this sleep from here.
1200                  */
1201                 usleep_range(1000, 1500);
1202                 ret = -EBUSY;
1203                 goto out;
1204         }
1205
1206         if (recv_bytes > recv_size)
1207                 recv_bytes = recv_size;
1208
1209         for (i = 0; i < recv_bytes; i += 4)
1210                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1211                                     recv + i, recv_bytes - i);
1212
1213         ret = recv_bytes;
1214 out:
1215         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1216
1217         if (vdd)
1218                 edp_panel_vdd_off(intel_dp, false);
1219
1220         pps_unlock(intel_dp);
1221
1222         return ret;
1223 }
1224
1225 #define BARE_ADDRESS_SIZE       3
1226 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1227 static ssize_t
1228 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1229 {
1230         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1231         uint8_t txbuf[20], rxbuf[20];
1232         size_t txsize, rxsize;
1233         int ret;
1234
1235         txbuf[0] = (msg->request << 4) |
1236                 ((msg->address >> 16) & 0xf);
1237         txbuf[1] = (msg->address >> 8) & 0xff;
1238         txbuf[2] = msg->address & 0xff;
1239         txbuf[3] = msg->size - 1;
1240
1241         switch (msg->request & ~DP_AUX_I2C_MOT) {
1242         case DP_AUX_NATIVE_WRITE:
1243         case DP_AUX_I2C_WRITE:
1244         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1245                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1246                 rxsize = 2; /* 0 or 1 data bytes */
1247
1248                 if (WARN_ON(txsize > 20))
1249                         return -E2BIG;
1250
1251                 WARN_ON(!msg->buffer != !msg->size);
1252
1253                 if (msg->buffer)
1254                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1255
1256                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1257                 if (ret > 0) {
1258                         msg->reply = rxbuf[0] >> 4;
1259
1260                         if (ret > 1) {
1261                                 /* Number of bytes written in a short write. */
1262                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1263                         } else {
1264                                 /* Return payload size. */
1265                                 ret = msg->size;
1266                         }
1267                 }
1268                 break;
1269
1270         case DP_AUX_NATIVE_READ:
1271         case DP_AUX_I2C_READ:
1272                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1273                 rxsize = msg->size + 1;
1274
1275                 if (WARN_ON(rxsize > 20))
1276                         return -E2BIG;
1277
1278                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1279                 if (ret > 0) {
1280                         msg->reply = rxbuf[0] >> 4;
1281                         /*
1282                          * Assume happy day, and copy the data. The caller is
1283                          * expected to check msg->reply before touching it.
1284                          *
1285                          * Return payload size.
1286                          */
1287                         ret--;
1288                         memcpy(msg->buffer, rxbuf + 1, ret);
1289                 }
1290                 break;
1291
1292         default:
1293                 ret = -EINVAL;
1294                 break;
1295         }
1296
1297         return ret;
1298 }
1299
1300 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1301                                 enum port port)
1302 {
1303         const struct ddi_vbt_port_info *info =
1304                 &dev_priv->vbt.ddi_port_info[port];
1305         enum port aux_port;
1306
1307         if (!info->alternate_aux_channel) {
1308                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1309                               port_name(port), port_name(port));
1310                 return port;
1311         }
1312
1313         switch (info->alternate_aux_channel) {
1314         case DP_AUX_A:
1315                 aux_port = PORT_A;
1316                 break;
1317         case DP_AUX_B:
1318                 aux_port = PORT_B;
1319                 break;
1320         case DP_AUX_C:
1321                 aux_port = PORT_C;
1322                 break;
1323         case DP_AUX_D:
1324                 aux_port = PORT_D;
1325                 break;
1326         default:
1327                 MISSING_CASE(info->alternate_aux_channel);
1328                 aux_port = PORT_A;
1329                 break;
1330         }
1331
1332         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1333                       port_name(aux_port), port_name(port));
1334
1335         return aux_port;
1336 }
1337
1338 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1339                                   enum port port)
1340 {
1341         switch (port) {
1342         case PORT_B:
1343         case PORT_C:
1344         case PORT_D:
1345                 return DP_AUX_CH_CTL(port);
1346         default:
1347                 MISSING_CASE(port);
1348                 return DP_AUX_CH_CTL(PORT_B);
1349         }
1350 }
1351
1352 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1353                                    enum port port, int index)
1354 {
1355         switch (port) {
1356         case PORT_B:
1357         case PORT_C:
1358         case PORT_D:
1359                 return DP_AUX_CH_DATA(port, index);
1360         default:
1361                 MISSING_CASE(port);
1362                 return DP_AUX_CH_DATA(PORT_B, index);
1363         }
1364 }
1365
1366 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1367                                   enum port port)
1368 {
1369         switch (port) {
1370         case PORT_A:
1371                 return DP_AUX_CH_CTL(port);
1372         case PORT_B:
1373         case PORT_C:
1374         case PORT_D:
1375                 return PCH_DP_AUX_CH_CTL(port);
1376         default:
1377                 MISSING_CASE(port);
1378                 return DP_AUX_CH_CTL(PORT_A);
1379         }
1380 }
1381
1382 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1383                                    enum port port, int index)
1384 {
1385         switch (port) {
1386         case PORT_A:
1387                 return DP_AUX_CH_DATA(port, index);
1388         case PORT_B:
1389         case PORT_C:
1390         case PORT_D:
1391                 return PCH_DP_AUX_CH_DATA(port, index);
1392         default:
1393                 MISSING_CASE(port);
1394                 return DP_AUX_CH_DATA(PORT_A, index);
1395         }
1396 }
1397
1398 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1399                                   enum port port)
1400 {
1401         switch (port) {
1402         case PORT_A:
1403         case PORT_B:
1404         case PORT_C:
1405         case PORT_D:
1406                 return DP_AUX_CH_CTL(port);
1407         default:
1408                 MISSING_CASE(port);
1409                 return DP_AUX_CH_CTL(PORT_A);
1410         }
1411 }
1412
1413 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1414                                    enum port port, int index)
1415 {
1416         switch (port) {
1417         case PORT_A:
1418         case PORT_B:
1419         case PORT_C:
1420         case PORT_D:
1421                 return DP_AUX_CH_DATA(port, index);
1422         default:
1423                 MISSING_CASE(port);
1424                 return DP_AUX_CH_DATA(PORT_A, index);
1425         }
1426 }
1427
1428 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1429                                     enum port port)
1430 {
1431         if (INTEL_INFO(dev_priv)->gen >= 9)
1432                 return skl_aux_ctl_reg(dev_priv, port);
1433         else if (HAS_PCH_SPLIT(dev_priv))
1434                 return ilk_aux_ctl_reg(dev_priv, port);
1435         else
1436                 return g4x_aux_ctl_reg(dev_priv, port);
1437 }
1438
1439 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1440                                      enum port port, int index)
1441 {
1442         if (INTEL_INFO(dev_priv)->gen >= 9)
1443                 return skl_aux_data_reg(dev_priv, port, index);
1444         else if (HAS_PCH_SPLIT(dev_priv))
1445                 return ilk_aux_data_reg(dev_priv, port, index);
1446         else
1447                 return g4x_aux_data_reg(dev_priv, port, index);
1448 }
1449
1450 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1451 {
1452         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1453         enum port port = intel_aux_port(dev_priv,
1454                                         dp_to_dig_port(intel_dp)->port);
1455         int i;
1456
1457         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1458         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1459                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1460 }
1461
1462 static void
1463 intel_dp_aux_fini(struct intel_dp *intel_dp)
1464 {
1465         kfree(intel_dp->aux.name);
1466 }
1467
1468 static void
1469 intel_dp_aux_init(struct intel_dp *intel_dp)
1470 {
1471         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1472         enum port port = intel_dig_port->port;
1473
1474         intel_aux_reg_init(intel_dp);
1475         drm_dp_aux_init(&intel_dp->aux);
1476
1477         /* Failure to allocate our preferred name is not critical */
1478         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1479         intel_dp->aux.transfer = intel_dp_aux_transfer;
1480 }
1481
1482 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1483 {
1484         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1485         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1486
1487         if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1488             IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1489                 return true;
1490         else
1491                 return false;
1492 }
1493
1494 static void
1495 intel_dp_set_clock(struct intel_encoder *encoder,
1496                    struct intel_crtc_state *pipe_config)
1497 {
1498         struct drm_device *dev = encoder->base.dev;
1499         struct drm_i915_private *dev_priv = to_i915(dev);
1500         const struct dp_link_dpll *divisor = NULL;
1501         int i, count = 0;
1502
1503         if (IS_G4X(dev_priv)) {
1504                 divisor = gen4_dpll;
1505                 count = ARRAY_SIZE(gen4_dpll);
1506         } else if (HAS_PCH_SPLIT(dev_priv)) {
1507                 divisor = pch_dpll;
1508                 count = ARRAY_SIZE(pch_dpll);
1509         } else if (IS_CHERRYVIEW(dev_priv)) {
1510                 divisor = chv_dpll;
1511                 count = ARRAY_SIZE(chv_dpll);
1512         } else if (IS_VALLEYVIEW(dev_priv)) {
1513                 divisor = vlv_dpll;
1514                 count = ARRAY_SIZE(vlv_dpll);
1515         }
1516
1517         if (divisor && count) {
1518                 for (i = 0; i < count; i++) {
1519                         if (pipe_config->port_clock == divisor[i].clock) {
1520                                 pipe_config->dpll = divisor[i].dpll;
1521                                 pipe_config->clock_set = true;
1522                                 break;
1523                         }
1524                 }
1525         }
1526 }
1527
1528 static void snprintf_int_array(char *str, size_t len,
1529                                const int *array, int nelem)
1530 {
1531         int i;
1532
1533         str[0] = '\0';
1534
1535         for (i = 0; i < nelem; i++) {
1536                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1537                 if (r >= len)
1538                         return;
1539                 str += r;
1540                 len -= r;
1541         }
1542 }
1543
1544 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1545 {
1546         char str[128]; /* FIXME: too big for stack? */
1547
1548         if ((drm_debug & DRM_UT_KMS) == 0)
1549                 return;
1550
1551         snprintf_int_array(str, sizeof(str),
1552                            intel_dp->source_rates, intel_dp->num_source_rates);
1553         DRM_DEBUG_KMS("source rates: %s\n", str);
1554
1555         snprintf_int_array(str, sizeof(str),
1556                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1557         DRM_DEBUG_KMS("sink rates: %s\n", str);
1558
1559         snprintf_int_array(str, sizeof(str),
1560                            intel_dp->common_rates, intel_dp->num_common_rates);
1561         DRM_DEBUG_KMS("common rates: %s\n", str);
1562 }
1563
1564 int
1565 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1566 {
1567         int len;
1568
1569         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1570         if (WARN_ON(len <= 0))
1571                 return 162000;
1572
1573         return intel_dp->common_rates[len - 1];
1574 }
1575
1576 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1577 {
1578         int i = intel_dp_rate_index(intel_dp->sink_rates,
1579                                     intel_dp->num_sink_rates, rate);
1580
1581         if (WARN_ON(i < 0))
1582                 i = 0;
1583
1584         return i;
1585 }
1586
1587 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1588                            uint8_t *link_bw, uint8_t *rate_select)
1589 {
1590         /* eDP 1.4 rate select method. */
1591         if (intel_dp->use_rate_select) {
1592                 *link_bw = 0;
1593                 *rate_select =
1594                         intel_dp_rate_select(intel_dp, port_clock);
1595         } else {
1596                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1597                 *rate_select = 0;
1598         }
1599 }
1600
1601 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1602                                 struct intel_crtc_state *pipe_config)
1603 {
1604         int bpp, bpc;
1605
1606         bpp = pipe_config->pipe_bpp;
1607         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1608
1609         if (bpc > 0)
1610                 bpp = min(bpp, 3*bpc);
1611
1612         /* For DP Compliance we override the computed bpp for the pipe */
1613         if (intel_dp->compliance.test_data.bpc != 0) {
1614                 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1615                 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1616                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1617                               pipe_config->pipe_bpp);
1618         }
1619         return bpp;
1620 }
1621
1622 static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
1623                                        struct drm_display_mode *m2)
1624 {
1625         bool bres = false;
1626
1627         if (m1 && m2)
1628                 bres = (m1->hdisplay == m2->hdisplay &&
1629                         m1->hsync_start == m2->hsync_start &&
1630                         m1->hsync_end == m2->hsync_end &&
1631                         m1->htotal == m2->htotal &&
1632                         m1->vdisplay == m2->vdisplay &&
1633                         m1->vsync_start == m2->vsync_start &&
1634                         m1->vsync_end == m2->vsync_end &&
1635                         m1->vtotal == m2->vtotal);
1636         return bres;
1637 }
1638
1639 bool
1640 intel_dp_compute_config(struct intel_encoder *encoder,
1641                         struct intel_crtc_state *pipe_config,
1642                         struct drm_connector_state *conn_state)
1643 {
1644         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1645         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1646         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1647         enum port port = dp_to_dig_port(intel_dp)->port;
1648         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1649         struct intel_connector *intel_connector = intel_dp->attached_connector;
1650         struct intel_digital_connector_state *intel_conn_state =
1651                 to_intel_digital_connector_state(conn_state);
1652         int lane_count, clock;
1653         int min_lane_count = 1;
1654         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1655         /* Conveniently, the link BW constants become indices with a shift...*/
1656         int min_clock = 0;
1657         int max_clock;
1658         int bpp, mode_rate;
1659         int link_avail, link_clock;
1660         int common_len;
1661         uint8_t link_bw, rate_select;
1662         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1663                                            DP_DPCD_QUIRK_LIMITED_M_N);
1664
1665         common_len = intel_dp_common_len_rate_limit(intel_dp,
1666                                                     intel_dp->max_link_rate);
1667
1668         /* No common link rates between source and sink */
1669         WARN_ON(common_len <= 0);
1670
1671         max_clock = common_len - 1;
1672
1673         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1674                 pipe_config->has_pch_encoder = true;
1675
1676         pipe_config->has_drrs = false;
1677         if (port == PORT_A)
1678                 pipe_config->has_audio = false;
1679         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1680                 pipe_config->has_audio = intel_dp->has_audio;
1681         else
1682                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1683
1684         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1685                 struct drm_display_mode *panel_mode =
1686                         intel_connector->panel.alt_fixed_mode;
1687                 struct drm_display_mode *req_mode = &pipe_config->base.mode;
1688
1689                 if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
1690                         panel_mode = intel_connector->panel.fixed_mode;
1691
1692                 drm_mode_debug_printmodeline(panel_mode);
1693
1694                 intel_fixed_panel_mode(panel_mode, adjusted_mode);
1695
1696                 if (INTEL_GEN(dev_priv) >= 9) {
1697                         int ret;
1698                         ret = skl_update_scaler_crtc(pipe_config);
1699                         if (ret)
1700                                 return ret;
1701                 }
1702
1703                 if (HAS_GMCH_DISPLAY(dev_priv))
1704                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1705                                                  conn_state->scaling_mode);
1706                 else
1707                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1708                                                 conn_state->scaling_mode);
1709         }
1710
1711         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1712                 return false;
1713
1714         /* Use values requested by Compliance Test Request */
1715         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1716                 int index;
1717
1718                 /* Validate the compliance test data since max values
1719                  * might have changed due to link train fallback.
1720                  */
1721                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1722                                                intel_dp->compliance.test_lane_count)) {
1723                         index = intel_dp_rate_index(intel_dp->common_rates,
1724                                                     intel_dp->num_common_rates,
1725                                                     intel_dp->compliance.test_link_rate);
1726                         if (index >= 0)
1727                                 min_clock = max_clock = index;
1728                         min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1729                 }
1730         }
1731         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1732                       "max bw %d pixel clock %iKHz\n",
1733                       max_lane_count, intel_dp->common_rates[max_clock],
1734                       adjusted_mode->crtc_clock);
1735
1736         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1737          * bpc in between. */
1738         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1739         if (is_edp(intel_dp)) {
1740
1741                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1742                 if (intel_connector->base.display_info.bpc == 0 &&
1743                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1744                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1745                                       dev_priv->vbt.edp.bpp);
1746                         bpp = dev_priv->vbt.edp.bpp;
1747                 }
1748
1749                 /*
1750                  * Use the maximum clock and number of lanes the eDP panel
1751                  * advertizes being capable of. The panels are generally
1752                  * designed to support only a single clock and lane
1753                  * configuration, and typically these values correspond to the
1754                  * native resolution of the panel.
1755                  */
1756                 min_lane_count = max_lane_count;
1757                 min_clock = max_clock;
1758         }
1759
1760         for (; bpp >= 6*3; bpp -= 2*3) {
1761                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1762                                                    bpp);
1763
1764                 for (clock = min_clock; clock <= max_clock; clock++) {
1765                         for (lane_count = min_lane_count;
1766                                 lane_count <= max_lane_count;
1767                                 lane_count <<= 1) {
1768
1769                                 link_clock = intel_dp->common_rates[clock];
1770                                 link_avail = intel_dp_max_data_rate(link_clock,
1771                                                                     lane_count);
1772
1773                                 if (mode_rate <= link_avail) {
1774                                         goto found;
1775                                 }
1776                         }
1777                 }
1778         }
1779
1780         return false;
1781
1782 found:
1783         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1784                 /*
1785                  * See:
1786                  * CEA-861-E - 5.1 Default Encoding Parameters
1787                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1788                  */
1789                 pipe_config->limited_color_range =
1790                         bpp != 18 &&
1791                         drm_default_rgb_quant_range(adjusted_mode) ==
1792                         HDMI_QUANTIZATION_RANGE_LIMITED;
1793         } else {
1794                 pipe_config->limited_color_range =
1795                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1796         }
1797
1798         pipe_config->lane_count = lane_count;
1799
1800         pipe_config->pipe_bpp = bpp;
1801         pipe_config->port_clock = intel_dp->common_rates[clock];
1802
1803         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1804                               &link_bw, &rate_select);
1805
1806         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1807                       link_bw, rate_select, pipe_config->lane_count,
1808                       pipe_config->port_clock, bpp);
1809         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1810                       mode_rate, link_avail);
1811
1812         intel_link_compute_m_n(bpp, lane_count,
1813                                adjusted_mode->crtc_clock,
1814                                pipe_config->port_clock,
1815                                &pipe_config->dp_m_n,
1816                                reduce_m_n);
1817
1818         if (intel_connector->panel.downclock_mode != NULL &&
1819                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1820                         pipe_config->has_drrs = true;
1821                         intel_link_compute_m_n(bpp, lane_count,
1822                                 intel_connector->panel.downclock_mode->clock,
1823                                 pipe_config->port_clock,
1824                                 &pipe_config->dp_m2_n2,
1825                                 reduce_m_n);
1826         }
1827
1828         /*
1829          * DPLL0 VCO may need to be adjusted to get the correct
1830          * clock for eDP. This will affect cdclk as well.
1831          */
1832         if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1833                 int vco;
1834
1835                 switch (pipe_config->port_clock / 2) {
1836                 case 108000:
1837                 case 216000:
1838                         vco = 8640000;
1839                         break;
1840                 default:
1841                         vco = 8100000;
1842                         break;
1843                 }
1844
1845                 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1846         }
1847
1848         if (!HAS_DDI(dev_priv))
1849                 intel_dp_set_clock(encoder, pipe_config);
1850
1851         return true;
1852 }
1853
1854 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1855                               int link_rate, uint8_t lane_count,
1856                               bool link_mst)
1857 {
1858         intel_dp->link_rate = link_rate;
1859         intel_dp->lane_count = lane_count;
1860         intel_dp->link_mst = link_mst;
1861 }
1862
1863 static void intel_dp_prepare(struct intel_encoder *encoder,
1864                              struct intel_crtc_state *pipe_config)
1865 {
1866         struct drm_device *dev = encoder->base.dev;
1867         struct drm_i915_private *dev_priv = to_i915(dev);
1868         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1869         enum port port = dp_to_dig_port(intel_dp)->port;
1870         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1871         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1872
1873         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1874                                  pipe_config->lane_count,
1875                                  intel_crtc_has_type(pipe_config,
1876                                                      INTEL_OUTPUT_DP_MST));
1877
1878         /*
1879          * There are four kinds of DP registers:
1880          *
1881          *      IBX PCH
1882          *      SNB CPU
1883          *      IVB CPU
1884          *      CPT PCH
1885          *
1886          * IBX PCH and CPU are the same for almost everything,
1887          * except that the CPU DP PLL is configured in this
1888          * register
1889          *
1890          * CPT PCH is quite different, having many bits moved
1891          * to the TRANS_DP_CTL register instead. That
1892          * configuration happens (oddly) in ironlake_pch_enable
1893          */
1894
1895         /* Preserve the BIOS-computed detected bit. This is
1896          * supposed to be read-only.
1897          */
1898         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1899
1900         /* Handle DP bits in common between all three register formats */
1901         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1902         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1903
1904         /* Split out the IBX/CPU vs CPT settings */
1905
1906         if (IS_GEN7(dev_priv) && port == PORT_A) {
1907                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1908                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1909                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1910                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1911                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1912
1913                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1914                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1915
1916                 intel_dp->DP |= crtc->pipe << 29;
1917         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1918                 u32 trans_dp;
1919
1920                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1921
1922                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1923                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1924                         trans_dp |= TRANS_DP_ENH_FRAMING;
1925                 else
1926                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1927                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1928         } else {
1929                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1930                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1931
1932                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1933                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1934                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1935                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1936                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1937
1938                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1939                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1940
1941                 if (IS_CHERRYVIEW(dev_priv))
1942                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1943                 else if (crtc->pipe == PIPE_B)
1944                         intel_dp->DP |= DP_PIPEB_SELECT;
1945         }
1946 }
1947
1948 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1949 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1950
1951 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1952 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1953
1954 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1955 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1956
1957 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1958                                    struct intel_dp *intel_dp);
1959
1960 static void wait_panel_status(struct intel_dp *intel_dp,
1961                                        u32 mask,
1962                                        u32 value)
1963 {
1964         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1965         struct drm_i915_private *dev_priv = to_i915(dev);
1966         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1967
1968         lockdep_assert_held(&dev_priv->pps_mutex);
1969
1970         intel_pps_verify_state(dev_priv, intel_dp);
1971
1972         pp_stat_reg = _pp_stat_reg(intel_dp);
1973         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1974
1975         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1976                         mask, value,
1977                         I915_READ(pp_stat_reg),
1978                         I915_READ(pp_ctrl_reg));
1979
1980         if (intel_wait_for_register(dev_priv,
1981                                     pp_stat_reg, mask, value,
1982                                     5000))
1983                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1984                                 I915_READ(pp_stat_reg),
1985                                 I915_READ(pp_ctrl_reg));
1986
1987         DRM_DEBUG_KMS("Wait complete\n");
1988 }
1989
1990 static void wait_panel_on(struct intel_dp *intel_dp)
1991 {
1992         DRM_DEBUG_KMS("Wait for panel power on\n");
1993         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1994 }
1995
1996 static void wait_panel_off(struct intel_dp *intel_dp)
1997 {
1998         DRM_DEBUG_KMS("Wait for panel power off time\n");
1999         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2000 }
2001
2002 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2003 {
2004         ktime_t panel_power_on_time;
2005         s64 panel_power_off_duration;
2006
2007         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2008
2009         /* take the difference of currrent time and panel power off time
2010          * and then make panel wait for t11_t12 if needed. */
2011         panel_power_on_time = ktime_get_boottime();
2012         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2013
2014         /* When we disable the VDD override bit last we have to do the manual
2015          * wait. */
2016         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2017                 wait_remaining_ms_from_jiffies(jiffies,
2018                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2019
2020         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2021 }
2022
2023 static void wait_backlight_on(struct intel_dp *intel_dp)
2024 {
2025         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2026                                        intel_dp->backlight_on_delay);
2027 }
2028
2029 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2030 {
2031         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2032                                        intel_dp->backlight_off_delay);
2033 }
2034
2035 /* Read the current pp_control value, unlocking the register if it
2036  * is locked
2037  */
2038
2039 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2040 {
2041         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2042         struct drm_i915_private *dev_priv = to_i915(dev);
2043         u32 control;
2044
2045         lockdep_assert_held(&dev_priv->pps_mutex);
2046
2047         control = I915_READ(_pp_ctrl_reg(intel_dp));
2048         if (WARN_ON(!HAS_DDI(dev_priv) &&
2049                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2050                 control &= ~PANEL_UNLOCK_MASK;
2051                 control |= PANEL_UNLOCK_REGS;
2052         }
2053         return control;
2054 }
2055
2056 /*
2057  * Must be paired with edp_panel_vdd_off().
2058  * Must hold pps_mutex around the whole on/off sequence.
2059  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2060  */
2061 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2062 {
2063         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2064         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2065         struct drm_i915_private *dev_priv = to_i915(dev);
2066         u32 pp;
2067         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2068         bool need_to_disable = !intel_dp->want_panel_vdd;
2069
2070         lockdep_assert_held(&dev_priv->pps_mutex);
2071
2072         if (!is_edp(intel_dp))
2073                 return false;
2074
2075         cancel_delayed_work(&intel_dp->panel_vdd_work);
2076         intel_dp->want_panel_vdd = true;
2077
2078         if (edp_have_panel_vdd(intel_dp))
2079                 return need_to_disable;
2080
2081         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2082
2083         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2084                       port_name(intel_dig_port->port));
2085
2086         if (!edp_have_panel_power(intel_dp))
2087                 wait_panel_power_cycle(intel_dp);
2088
2089         pp = ironlake_get_pp_control(intel_dp);
2090         pp |= EDP_FORCE_VDD;
2091
2092         pp_stat_reg = _pp_stat_reg(intel_dp);
2093         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2094
2095         I915_WRITE(pp_ctrl_reg, pp);
2096         POSTING_READ(pp_ctrl_reg);
2097         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2098                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2099         /*
2100          * If the panel wasn't on, delay before accessing aux channel
2101          */
2102         if (!edp_have_panel_power(intel_dp)) {
2103                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2104                               port_name(intel_dig_port->port));
2105                 msleep(intel_dp->panel_power_up_delay);
2106         }
2107
2108         return need_to_disable;
2109 }
2110
2111 /*
2112  * Must be paired with intel_edp_panel_vdd_off() or
2113  * intel_edp_panel_off().
2114  * Nested calls to these functions are not allowed since
2115  * we drop the lock. Caller must use some higher level
2116  * locking to prevent nested calls from other threads.
2117  */
2118 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2119 {
2120         bool vdd;
2121
2122         if (!is_edp(intel_dp))
2123                 return;
2124
2125         pps_lock(intel_dp);
2126         vdd = edp_panel_vdd_on(intel_dp);
2127         pps_unlock(intel_dp);
2128
2129         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2130              port_name(dp_to_dig_port(intel_dp)->port));
2131 }
2132
2133 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2134 {
2135         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2136         struct drm_i915_private *dev_priv = to_i915(dev);
2137         struct intel_digital_port *intel_dig_port =
2138                 dp_to_dig_port(intel_dp);
2139         u32 pp;
2140         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2141
2142         lockdep_assert_held(&dev_priv->pps_mutex);
2143
2144         WARN_ON(intel_dp->want_panel_vdd);
2145
2146         if (!edp_have_panel_vdd(intel_dp))
2147                 return;
2148
2149         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2150                       port_name(intel_dig_port->port));
2151
2152         pp = ironlake_get_pp_control(intel_dp);
2153         pp &= ~EDP_FORCE_VDD;
2154
2155         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2156         pp_stat_reg = _pp_stat_reg(intel_dp);
2157
2158         I915_WRITE(pp_ctrl_reg, pp);
2159         POSTING_READ(pp_ctrl_reg);
2160
2161         /* Make sure sequencer is idle before allowing subsequent activity */
2162         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2163         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2164
2165         if ((pp & PANEL_POWER_ON) == 0)
2166                 intel_dp->panel_power_off_time = ktime_get_boottime();
2167
2168         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2169 }
2170
2171 static void edp_panel_vdd_work(struct work_struct *__work)
2172 {
2173         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2174                                                  struct intel_dp, panel_vdd_work);
2175
2176         pps_lock(intel_dp);
2177         if (!intel_dp->want_panel_vdd)
2178                 edp_panel_vdd_off_sync(intel_dp);
2179         pps_unlock(intel_dp);
2180 }
2181
2182 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2183 {
2184         unsigned long delay;
2185
2186         /*
2187          * Queue the timer to fire a long time from now (relative to the power
2188          * down delay) to keep the panel power up across a sequence of
2189          * operations.
2190          */
2191         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2192         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2193 }
2194
2195 /*
2196  * Must be paired with edp_panel_vdd_on().
2197  * Must hold pps_mutex around the whole on/off sequence.
2198  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2199  */
2200 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2201 {
2202         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2203
2204         lockdep_assert_held(&dev_priv->pps_mutex);
2205
2206         if (!is_edp(intel_dp))
2207                 return;
2208
2209         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2210              port_name(dp_to_dig_port(intel_dp)->port));
2211
2212         intel_dp->want_panel_vdd = false;
2213
2214         if (sync)
2215                 edp_panel_vdd_off_sync(intel_dp);
2216         else
2217                 edp_panel_vdd_schedule_off(intel_dp);
2218 }
2219
2220 static void edp_panel_on(struct intel_dp *intel_dp)
2221 {
2222         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2223         struct drm_i915_private *dev_priv = to_i915(dev);
2224         u32 pp;
2225         i915_reg_t pp_ctrl_reg;
2226
2227         lockdep_assert_held(&dev_priv->pps_mutex);
2228
2229         if (!is_edp(intel_dp))
2230                 return;
2231
2232         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2233                       port_name(dp_to_dig_port(intel_dp)->port));
2234
2235         if (WARN(edp_have_panel_power(intel_dp),
2236                  "eDP port %c panel power already on\n",
2237                  port_name(dp_to_dig_port(intel_dp)->port)))
2238                 return;
2239
2240         wait_panel_power_cycle(intel_dp);
2241
2242         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2243         pp = ironlake_get_pp_control(intel_dp);
2244         if (IS_GEN5(dev_priv)) {
2245                 /* ILK workaround: disable reset around power sequence */
2246                 pp &= ~PANEL_POWER_RESET;
2247                 I915_WRITE(pp_ctrl_reg, pp);
2248                 POSTING_READ(pp_ctrl_reg);
2249         }
2250
2251         pp |= PANEL_POWER_ON;
2252         if (!IS_GEN5(dev_priv))
2253                 pp |= PANEL_POWER_RESET;
2254
2255         I915_WRITE(pp_ctrl_reg, pp);
2256         POSTING_READ(pp_ctrl_reg);
2257
2258         wait_panel_on(intel_dp);
2259         intel_dp->last_power_on = jiffies;
2260
2261         if (IS_GEN5(dev_priv)) {
2262                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2263                 I915_WRITE(pp_ctrl_reg, pp);
2264                 POSTING_READ(pp_ctrl_reg);
2265         }
2266 }
2267
2268 void intel_edp_panel_on(struct intel_dp *intel_dp)
2269 {
2270         if (!is_edp(intel_dp))
2271                 return;
2272
2273         pps_lock(intel_dp);
2274         edp_panel_on(intel_dp);
2275         pps_unlock(intel_dp);
2276 }
2277
2278
2279 static void edp_panel_off(struct intel_dp *intel_dp)
2280 {
2281         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2282         struct drm_i915_private *dev_priv = to_i915(dev);
2283         u32 pp;
2284         i915_reg_t pp_ctrl_reg;
2285
2286         lockdep_assert_held(&dev_priv->pps_mutex);
2287
2288         if (!is_edp(intel_dp))
2289                 return;
2290
2291         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2292                       port_name(dp_to_dig_port(intel_dp)->port));
2293
2294         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2295              port_name(dp_to_dig_port(intel_dp)->port));
2296
2297         pp = ironlake_get_pp_control(intel_dp);
2298         /* We need to switch off panel power _and_ force vdd, for otherwise some
2299          * panels get very unhappy and cease to work. */
2300         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2301                 EDP_BLC_ENABLE);
2302
2303         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2304
2305         intel_dp->want_panel_vdd = false;
2306
2307         I915_WRITE(pp_ctrl_reg, pp);
2308         POSTING_READ(pp_ctrl_reg);
2309
2310         wait_panel_off(intel_dp);
2311         intel_dp->panel_power_off_time = ktime_get_boottime();
2312
2313         /* We got a reference when we enabled the VDD. */
2314         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2315 }
2316
2317 void intel_edp_panel_off(struct intel_dp *intel_dp)
2318 {
2319         if (!is_edp(intel_dp))
2320                 return;
2321
2322         pps_lock(intel_dp);
2323         edp_panel_off(intel_dp);
2324         pps_unlock(intel_dp);
2325 }
2326
2327 /* Enable backlight in the panel power control. */
2328 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2329 {
2330         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2331         struct drm_device *dev = intel_dig_port->base.base.dev;
2332         struct drm_i915_private *dev_priv = to_i915(dev);
2333         u32 pp;
2334         i915_reg_t pp_ctrl_reg;
2335
2336         /*
2337          * If we enable the backlight right away following a panel power
2338          * on, we may see slight flicker as the panel syncs with the eDP
2339          * link.  So delay a bit to make sure the image is solid before
2340          * allowing it to appear.
2341          */
2342         wait_backlight_on(intel_dp);
2343
2344         pps_lock(intel_dp);
2345
2346         pp = ironlake_get_pp_control(intel_dp);
2347         pp |= EDP_BLC_ENABLE;
2348
2349         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2350
2351         I915_WRITE(pp_ctrl_reg, pp);
2352         POSTING_READ(pp_ctrl_reg);
2353
2354         pps_unlock(intel_dp);
2355 }
2356
2357 /* Enable backlight PWM and backlight PP control. */
2358 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2359                             const struct drm_connector_state *conn_state)
2360 {
2361         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2362
2363         if (!is_edp(intel_dp))
2364                 return;
2365
2366         DRM_DEBUG_KMS("\n");
2367
2368         intel_panel_enable_backlight(crtc_state, conn_state);
2369         _intel_edp_backlight_on(intel_dp);
2370 }
2371
2372 /* Disable backlight in the panel power control. */
2373 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2374 {
2375         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2376         struct drm_i915_private *dev_priv = to_i915(dev);
2377         u32 pp;
2378         i915_reg_t pp_ctrl_reg;
2379
2380         if (!is_edp(intel_dp))
2381                 return;
2382
2383         pps_lock(intel_dp);
2384
2385         pp = ironlake_get_pp_control(intel_dp);
2386         pp &= ~EDP_BLC_ENABLE;
2387
2388         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2389
2390         I915_WRITE(pp_ctrl_reg, pp);
2391         POSTING_READ(pp_ctrl_reg);
2392
2393         pps_unlock(intel_dp);
2394
2395         intel_dp->last_backlight_off = jiffies;
2396         edp_wait_backlight_off(intel_dp);
2397 }
2398
2399 /* Disable backlight PP control and backlight PWM. */
2400 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2401 {
2402         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2403
2404         if (!is_edp(intel_dp))
2405                 return;
2406
2407         DRM_DEBUG_KMS("\n");
2408
2409         _intel_edp_backlight_off(intel_dp);
2410         intel_panel_disable_backlight(old_conn_state);
2411 }
2412
2413 /*
2414  * Hook for controlling the panel power control backlight through the bl_power
2415  * sysfs attribute. Take care to handle multiple calls.
2416  */
2417 static void intel_edp_backlight_power(struct intel_connector *connector,
2418                                       bool enable)
2419 {
2420         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2421         bool is_enabled;
2422
2423         pps_lock(intel_dp);
2424         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2425         pps_unlock(intel_dp);
2426
2427         if (is_enabled == enable)
2428                 return;
2429
2430         DRM_DEBUG_KMS("panel power control backlight %s\n",
2431                       enable ? "enable" : "disable");
2432
2433         if (enable)
2434                 _intel_edp_backlight_on(intel_dp);
2435         else
2436                 _intel_edp_backlight_off(intel_dp);
2437 }
2438
2439 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2440 {
2441         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2442         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2443         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2444
2445         I915_STATE_WARN(cur_state != state,
2446                         "DP port %c state assertion failure (expected %s, current %s)\n",
2447                         port_name(dig_port->port),
2448                         onoff(state), onoff(cur_state));
2449 }
2450 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2451
2452 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2453 {
2454         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2455
2456         I915_STATE_WARN(cur_state != state,
2457                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2458                         onoff(state), onoff(cur_state));
2459 }
2460 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2461 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2462
2463 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2464                                 struct intel_crtc_state *pipe_config)
2465 {
2466         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2467         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2468
2469         assert_pipe_disabled(dev_priv, crtc->pipe);
2470         assert_dp_port_disabled(intel_dp);
2471         assert_edp_pll_disabled(dev_priv);
2472
2473         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2474                       pipe_config->port_clock);
2475
2476         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2477
2478         if (pipe_config->port_clock == 162000)
2479                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2480         else
2481                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2482
2483         I915_WRITE(DP_A, intel_dp->DP);
2484         POSTING_READ(DP_A);
2485         udelay(500);
2486
2487         /*
2488          * [DevILK] Work around required when enabling DP PLL
2489          * while a pipe is enabled going to FDI:
2490          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2491          * 2. Program DP PLL enable
2492          */
2493         if (IS_GEN5(dev_priv))
2494                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2495
2496         intel_dp->DP |= DP_PLL_ENABLE;
2497
2498         I915_WRITE(DP_A, intel_dp->DP);
2499         POSTING_READ(DP_A);
2500         udelay(200);
2501 }
2502
2503 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2504 {
2505         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2506         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2507         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2508
2509         assert_pipe_disabled(dev_priv, crtc->pipe);
2510         assert_dp_port_disabled(intel_dp);
2511         assert_edp_pll_enabled(dev_priv);
2512
2513         DRM_DEBUG_KMS("disabling eDP PLL\n");
2514
2515         intel_dp->DP &= ~DP_PLL_ENABLE;
2516
2517         I915_WRITE(DP_A, intel_dp->DP);
2518         POSTING_READ(DP_A);
2519         udelay(200);
2520 }
2521
2522 /* If the sink supports it, try to set the power state appropriately */
2523 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2524 {
2525         int ret, i;
2526
2527         /* Should have a valid DPCD by this point */
2528         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2529                 return;
2530
2531         if (mode != DRM_MODE_DPMS_ON) {
2532                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2533                                          DP_SET_POWER_D3);
2534         } else {
2535                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2536
2537                 /*
2538                  * When turning on, we need to retry for 1ms to give the sink
2539                  * time to wake up.
2540                  */
2541                 for (i = 0; i < 3; i++) {
2542                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2543                                                  DP_SET_POWER_D0);
2544                         if (ret == 1)
2545                                 break;
2546                         msleep(1);
2547                 }
2548
2549                 if (ret == 1 && lspcon->active)
2550                         lspcon_wait_pcon_mode(lspcon);
2551         }
2552
2553         if (ret != 1)
2554                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2555                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2556 }
2557
2558 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2559                                   enum pipe *pipe)
2560 {
2561         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2562         enum port port = dp_to_dig_port(intel_dp)->port;
2563         struct drm_device *dev = encoder->base.dev;
2564         struct drm_i915_private *dev_priv = to_i915(dev);
2565         u32 tmp;
2566         bool ret;
2567
2568         if (!intel_display_power_get_if_enabled(dev_priv,
2569                                                 encoder->power_domain))
2570                 return false;
2571
2572         ret = false;
2573
2574         tmp = I915_READ(intel_dp->output_reg);
2575
2576         if (!(tmp & DP_PORT_EN))
2577                 goto out;
2578
2579         if (IS_GEN7(dev_priv) && port == PORT_A) {
2580                 *pipe = PORT_TO_PIPE_CPT(tmp);
2581         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2582                 enum pipe p;
2583
2584                 for_each_pipe(dev_priv, p) {
2585                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2586                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2587                                 *pipe = p;
2588                                 ret = true;
2589
2590                                 goto out;
2591                         }
2592                 }
2593
2594                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2595                               i915_mmio_reg_offset(intel_dp->output_reg));
2596         } else if (IS_CHERRYVIEW(dev_priv)) {
2597                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2598         } else {
2599                 *pipe = PORT_TO_PIPE(tmp);
2600         }
2601
2602         ret = true;
2603
2604 out:
2605         intel_display_power_put(dev_priv, encoder->power_domain);
2606
2607         return ret;
2608 }
2609
2610 static void intel_dp_get_config(struct intel_encoder *encoder,
2611                                 struct intel_crtc_state *pipe_config)
2612 {
2613         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2614         u32 tmp, flags = 0;
2615         struct drm_device *dev = encoder->base.dev;
2616         struct drm_i915_private *dev_priv = to_i915(dev);
2617         enum port port = dp_to_dig_port(intel_dp)->port;
2618         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2619
2620         tmp = I915_READ(intel_dp->output_reg);
2621
2622         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2623
2624         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2625                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2626
2627                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2628                         flags |= DRM_MODE_FLAG_PHSYNC;
2629                 else
2630                         flags |= DRM_MODE_FLAG_NHSYNC;
2631
2632                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2633                         flags |= DRM_MODE_FLAG_PVSYNC;
2634                 else
2635                         flags |= DRM_MODE_FLAG_NVSYNC;
2636         } else {
2637                 if (tmp & DP_SYNC_HS_HIGH)
2638                         flags |= DRM_MODE_FLAG_PHSYNC;
2639                 else
2640                         flags |= DRM_MODE_FLAG_NHSYNC;
2641
2642                 if (tmp & DP_SYNC_VS_HIGH)
2643                         flags |= DRM_MODE_FLAG_PVSYNC;
2644                 else
2645                         flags |= DRM_MODE_FLAG_NVSYNC;
2646         }
2647
2648         pipe_config->base.adjusted_mode.flags |= flags;
2649
2650         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2651                 pipe_config->limited_color_range = true;
2652
2653         pipe_config->lane_count =
2654                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2655
2656         intel_dp_get_m_n(crtc, pipe_config);
2657
2658         if (port == PORT_A) {
2659                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2660                         pipe_config->port_clock = 162000;
2661                 else
2662                         pipe_config->port_clock = 270000;
2663         }
2664
2665         pipe_config->base.adjusted_mode.crtc_clock =
2666                 intel_dotclock_calculate(pipe_config->port_clock,
2667                                          &pipe_config->dp_m_n);
2668
2669         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2670             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2671                 /*
2672                  * This is a big fat ugly hack.
2673                  *
2674                  * Some machines in UEFI boot mode provide us a VBT that has 18
2675                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2676                  * unknown we fail to light up. Yet the same BIOS boots up with
2677                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2678                  * max, not what it tells us to use.
2679                  *
2680                  * Note: This will still be broken if the eDP panel is not lit
2681                  * up by the BIOS, and thus we can't get the mode at module
2682                  * load.
2683                  */
2684                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2685                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2686                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2687         }
2688 }
2689
2690 static void intel_disable_dp(struct intel_encoder *encoder,
2691                              struct intel_crtc_state *old_crtc_state,
2692                              struct drm_connector_state *old_conn_state)
2693 {
2694         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2695         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2696
2697         if (old_crtc_state->has_audio)
2698                 intel_audio_codec_disable(encoder);
2699
2700         if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2701                 intel_psr_disable(intel_dp);
2702
2703         /* Make sure the panel is off before trying to change the mode. But also
2704          * ensure that we have vdd while we switch off the panel. */
2705         intel_edp_panel_vdd_on(intel_dp);
2706         intel_edp_backlight_off(old_conn_state);
2707         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2708         intel_edp_panel_off(intel_dp);
2709
2710         /* disable the port before the pipe on g4x */
2711         if (INTEL_GEN(dev_priv) < 5)
2712                 intel_dp_link_down(intel_dp);
2713 }
2714
2715 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2716                                 struct intel_crtc_state *old_crtc_state,
2717                                 struct drm_connector_state *old_conn_state)
2718 {
2719         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2720         enum port port = dp_to_dig_port(intel_dp)->port;
2721
2722         intel_dp_link_down(intel_dp);
2723
2724         /* Only ilk+ has port A */
2725         if (port == PORT_A)
2726                 ironlake_edp_pll_off(intel_dp);
2727 }
2728
2729 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2730                                 struct intel_crtc_state *old_crtc_state,
2731                                 struct drm_connector_state *old_conn_state)
2732 {
2733         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2734
2735         intel_dp_link_down(intel_dp);
2736 }
2737
2738 static void chv_post_disable_dp(struct intel_encoder *encoder,
2739                                 struct intel_crtc_state *old_crtc_state,
2740                                 struct drm_connector_state *old_conn_state)
2741 {
2742         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2743         struct drm_device *dev = encoder->base.dev;
2744         struct drm_i915_private *dev_priv = to_i915(dev);
2745
2746         intel_dp_link_down(intel_dp);
2747
2748         mutex_lock(&dev_priv->sb_lock);
2749
2750         /* Assert data lane reset */
2751         chv_data_lane_soft_reset(encoder, true);
2752
2753         mutex_unlock(&dev_priv->sb_lock);
2754 }
2755
2756 static void
2757 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2758                          uint32_t *DP,
2759                          uint8_t dp_train_pat)
2760 {
2761         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2762         struct drm_device *dev = intel_dig_port->base.base.dev;
2763         struct drm_i915_private *dev_priv = to_i915(dev);
2764         enum port port = intel_dig_port->port;
2765
2766         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2767                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2768                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2769
2770         if (HAS_DDI(dev_priv)) {
2771                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2772
2773                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2774                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2775                 else
2776                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2777
2778                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2779                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2780                 case DP_TRAINING_PATTERN_DISABLE:
2781                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2782
2783                         break;
2784                 case DP_TRAINING_PATTERN_1:
2785                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2786                         break;
2787                 case DP_TRAINING_PATTERN_2:
2788                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2789                         break;
2790                 case DP_TRAINING_PATTERN_3:
2791                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2792                         break;
2793                 }
2794                 I915_WRITE(DP_TP_CTL(port), temp);
2795
2796         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2797                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2798                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2799
2800                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2801                 case DP_TRAINING_PATTERN_DISABLE:
2802                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2803                         break;
2804                 case DP_TRAINING_PATTERN_1:
2805                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2806                         break;
2807                 case DP_TRAINING_PATTERN_2:
2808                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2809                         break;
2810                 case DP_TRAINING_PATTERN_3:
2811                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2812                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2813                         break;
2814                 }
2815
2816         } else {
2817                 if (IS_CHERRYVIEW(dev_priv))
2818                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2819                 else
2820                         *DP &= ~DP_LINK_TRAIN_MASK;
2821
2822                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2823                 case DP_TRAINING_PATTERN_DISABLE:
2824                         *DP |= DP_LINK_TRAIN_OFF;
2825                         break;
2826                 case DP_TRAINING_PATTERN_1:
2827                         *DP |= DP_LINK_TRAIN_PAT_1;
2828                         break;
2829                 case DP_TRAINING_PATTERN_2:
2830                         *DP |= DP_LINK_TRAIN_PAT_2;
2831                         break;
2832                 case DP_TRAINING_PATTERN_3:
2833                         if (IS_CHERRYVIEW(dev_priv)) {
2834                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2835                         } else {
2836                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2837                                 *DP |= DP_LINK_TRAIN_PAT_2;
2838                         }
2839                         break;
2840                 }
2841         }
2842 }
2843
2844 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2845                                  struct intel_crtc_state *old_crtc_state)
2846 {
2847         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2848         struct drm_i915_private *dev_priv = to_i915(dev);
2849
2850         /* enable with pattern 1 (as per spec) */
2851
2852         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2853
2854         /*
2855          * Magic for VLV/CHV. We _must_ first set up the register
2856          * without actually enabling the port, and then do another
2857          * write to enable the port. Otherwise link training will
2858          * fail when the power sequencer is freshly used for this port.
2859          */
2860         intel_dp->DP |= DP_PORT_EN;
2861         if (old_crtc_state->has_audio)
2862                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2863
2864         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2865         POSTING_READ(intel_dp->output_reg);
2866 }
2867
2868 static void intel_enable_dp(struct intel_encoder *encoder,
2869                             struct intel_crtc_state *pipe_config,
2870                             struct drm_connector_state *conn_state)
2871 {
2872         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2873         struct drm_device *dev = encoder->base.dev;
2874         struct drm_i915_private *dev_priv = to_i915(dev);
2875         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2876         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2877         enum pipe pipe = crtc->pipe;
2878
2879         if (WARN_ON(dp_reg & DP_PORT_EN))
2880                 return;
2881
2882         pps_lock(intel_dp);
2883
2884         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2885                 vlv_init_panel_power_sequencer(intel_dp);
2886
2887         intel_dp_enable_port(intel_dp, pipe_config);
2888
2889         edp_panel_vdd_on(intel_dp);
2890         edp_panel_on(intel_dp);
2891         edp_panel_vdd_off(intel_dp, true);
2892
2893         pps_unlock(intel_dp);
2894
2895         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2896                 unsigned int lane_mask = 0x0;
2897
2898                 if (IS_CHERRYVIEW(dev_priv))
2899                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2900
2901                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2902                                     lane_mask);
2903         }
2904
2905         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2906         intel_dp_start_link_train(intel_dp);
2907         intel_dp_stop_link_train(intel_dp);
2908
2909         if (pipe_config->has_audio) {
2910                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2911                                  pipe_name(pipe));
2912                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2913         }
2914 }
2915
2916 static void g4x_enable_dp(struct intel_encoder *encoder,
2917                           struct intel_crtc_state *pipe_config,
2918                           struct drm_connector_state *conn_state)
2919 {
2920         intel_enable_dp(encoder, pipe_config, conn_state);
2921         intel_edp_backlight_on(pipe_config, conn_state);
2922 }
2923
2924 static void vlv_enable_dp(struct intel_encoder *encoder,
2925                           struct intel_crtc_state *pipe_config,
2926                           struct drm_connector_state *conn_state)
2927 {
2928         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2929
2930         intel_edp_backlight_on(pipe_config, conn_state);
2931         intel_psr_enable(intel_dp);
2932 }
2933
2934 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2935                               struct intel_crtc_state *pipe_config,
2936                               struct drm_connector_state *conn_state)
2937 {
2938         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2939         enum port port = dp_to_dig_port(intel_dp)->port;
2940
2941         intel_dp_prepare(encoder, pipe_config);
2942
2943         /* Only ilk+ has port A */
2944         if (port == PORT_A)
2945                 ironlake_edp_pll_on(intel_dp, pipe_config);
2946 }
2947
2948 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2949 {
2950         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2951         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2952         enum pipe pipe = intel_dp->pps_pipe;
2953         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2954
2955         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2956
2957         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2958                 return;
2959
2960         edp_panel_vdd_off_sync(intel_dp);
2961
2962         /*
2963          * VLV seems to get confused when multiple power seqeuencers
2964          * have the same port selected (even if only one has power/vdd
2965          * enabled). The failure manifests as vlv_wait_port_ready() failing
2966          * CHV on the other hand doesn't seem to mind having the same port
2967          * selected in multiple power seqeuencers, but let's clear the
2968          * port select always when logically disconnecting a power sequencer
2969          * from a port.
2970          */
2971         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2972                       pipe_name(pipe), port_name(intel_dig_port->port));
2973         I915_WRITE(pp_on_reg, 0);
2974         POSTING_READ(pp_on_reg);
2975
2976         intel_dp->pps_pipe = INVALID_PIPE;
2977 }
2978
2979 static void vlv_steal_power_sequencer(struct drm_device *dev,
2980                                       enum pipe pipe)
2981 {
2982         struct drm_i915_private *dev_priv = to_i915(dev);
2983         struct intel_encoder *encoder;
2984
2985         lockdep_assert_held(&dev_priv->pps_mutex);
2986
2987         for_each_intel_encoder(dev, encoder) {
2988                 struct intel_dp *intel_dp;
2989                 enum port port;
2990
2991                 if (encoder->type != INTEL_OUTPUT_DP &&
2992                     encoder->type != INTEL_OUTPUT_EDP)
2993                         continue;
2994
2995                 intel_dp = enc_to_intel_dp(&encoder->base);
2996                 port = dp_to_dig_port(intel_dp)->port;
2997
2998                 WARN(intel_dp->active_pipe == pipe,
2999                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3000                      pipe_name(pipe), port_name(port));
3001
3002                 if (intel_dp->pps_pipe != pipe)
3003                         continue;
3004
3005                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3006                               pipe_name(pipe), port_name(port));
3007
3008                 /* make sure vdd is off before we steal it */
3009                 vlv_detach_power_sequencer(intel_dp);
3010         }
3011 }
3012
3013 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
3014 {
3015         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3016         struct intel_encoder *encoder = &intel_dig_port->base;
3017         struct drm_device *dev = encoder->base.dev;
3018         struct drm_i915_private *dev_priv = to_i915(dev);
3019         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
3020
3021         lockdep_assert_held(&dev_priv->pps_mutex);
3022
3023         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3024
3025         if (intel_dp->pps_pipe != INVALID_PIPE &&
3026             intel_dp->pps_pipe != crtc->pipe) {
3027                 /*
3028                  * If another power sequencer was being used on this
3029                  * port previously make sure to turn off vdd there while
3030                  * we still have control of it.
3031                  */
3032                 vlv_detach_power_sequencer(intel_dp);
3033         }
3034
3035         /*
3036          * We may be stealing the power
3037          * sequencer from another port.
3038          */
3039         vlv_steal_power_sequencer(dev, crtc->pipe);
3040
3041         intel_dp->active_pipe = crtc->pipe;
3042
3043         if (!is_edp(intel_dp))
3044                 return;
3045
3046         /* now it's all ours */
3047         intel_dp->pps_pipe = crtc->pipe;
3048
3049         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3050                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
3051
3052         /* init power sequencer on this pipe and port */
3053         intel_dp_init_panel_power_sequencer(dev, intel_dp);
3054         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
3055 }
3056
3057 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3058                               struct intel_crtc_state *pipe_config,
3059                               struct drm_connector_state *conn_state)
3060 {
3061         vlv_phy_pre_encoder_enable(encoder);
3062
3063         intel_enable_dp(encoder, pipe_config, conn_state);
3064 }
3065
3066 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3067                                   struct intel_crtc_state *pipe_config,
3068                                   struct drm_connector_state *conn_state)
3069 {
3070         intel_dp_prepare(encoder, pipe_config);
3071
3072         vlv_phy_pre_pll_enable(encoder);
3073 }
3074
3075 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3076                               struct intel_crtc_state *pipe_config,
3077                               struct drm_connector_state *conn_state)
3078 {
3079         chv_phy_pre_encoder_enable(encoder);
3080
3081         intel_enable_dp(encoder, pipe_config, conn_state);
3082
3083         /* Second common lane will stay alive on its own now */
3084         chv_phy_release_cl2_override(encoder);
3085 }
3086
3087 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3088                                   struct intel_crtc_state *pipe_config,
3089                                   struct drm_connector_state *conn_state)
3090 {
3091         intel_dp_prepare(encoder, pipe_config);
3092
3093         chv_phy_pre_pll_enable(encoder);
3094 }
3095
3096 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3097                                     struct intel_crtc_state *pipe_config,
3098                                     struct drm_connector_state *conn_state)
3099 {
3100         chv_phy_post_pll_disable(encoder);
3101 }
3102
3103 /*
3104  * Fetch AUX CH registers 0x202 - 0x207 which contain
3105  * link status information
3106  */
3107 bool
3108 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3109 {
3110         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3111                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3112 }
3113
3114 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3115 {
3116         uint8_t psr_caps = 0;
3117
3118         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
3119                 return false;
3120         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3121 }
3122
3123 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3124 {
3125         uint8_t dprx = 0;
3126
3127         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3128                               &dprx) != 1)
3129                 return false;
3130         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3131 }
3132
3133 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3134 {
3135         uint8_t alpm_caps = 0;
3136
3137         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
3138                               &alpm_caps) != 1)
3139                 return false;
3140         return alpm_caps & DP_ALPM_CAP;
3141 }
3142
3143 /* These are source-specific values. */
3144 uint8_t
3145 intel_dp_voltage_max(struct intel_dp *intel_dp)
3146 {
3147         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3148         enum port port = dp_to_dig_port(intel_dp)->port;
3149
3150         if (IS_GEN9_LP(dev_priv))
3151                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3152         else if (INTEL_GEN(dev_priv) >= 9) {
3153                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3154                 return intel_ddi_dp_voltage_max(encoder);
3155         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3156                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3157         else if (IS_GEN7(dev_priv) && port == PORT_A)
3158                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3159         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3160                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3161         else
3162                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3163 }
3164
3165 uint8_t
3166 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3167 {
3168         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3169         enum port port = dp_to_dig_port(intel_dp)->port;
3170
3171         if (INTEL_GEN(dev_priv) >= 9) {
3172                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3173                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3174                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3175                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3176                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3177                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3178                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3179                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3180                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3181                 default:
3182                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3183                 }
3184         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3185                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3186                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3187                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3188                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3189                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3190                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3191                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3192                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3193                 default:
3194                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3195                 }
3196         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3197                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3198                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3199                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3200                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3201                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3202                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3203                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3204                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3205                 default:
3206                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3207                 }
3208         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3209                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3210                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3211                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3212                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3213                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3214                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3215                 default:
3216                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3217                 }
3218         } else {
3219                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3220                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3221                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3222                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3223                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3224                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3225                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3226                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3227                 default:
3228                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3229                 }
3230         }
3231 }
3232
3233 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3234 {
3235         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3236         unsigned long demph_reg_value, preemph_reg_value,
3237                 uniqtranscale_reg_value;
3238         uint8_t train_set = intel_dp->train_set[0];
3239
3240         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3241         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3242                 preemph_reg_value = 0x0004000;
3243                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3244                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3245                         demph_reg_value = 0x2B405555;
3246                         uniqtranscale_reg_value = 0x552AB83A;
3247                         break;
3248                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3249                         demph_reg_value = 0x2B404040;
3250                         uniqtranscale_reg_value = 0x5548B83A;
3251                         break;
3252                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3253                         demph_reg_value = 0x2B245555;
3254                         uniqtranscale_reg_value = 0x5560B83A;
3255                         break;
3256                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3257                         demph_reg_value = 0x2B405555;
3258                         uniqtranscale_reg_value = 0x5598DA3A;
3259                         break;
3260                 default:
3261                         return 0;
3262                 }
3263                 break;
3264         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3265                 preemph_reg_value = 0x0002000;
3266                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3267                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3268                         demph_reg_value = 0x2B404040;
3269                         uniqtranscale_reg_value = 0x5552B83A;
3270                         break;
3271                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3272                         demph_reg_value = 0x2B404848;
3273                         uniqtranscale_reg_value = 0x5580B83A;
3274                         break;
3275                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3276                         demph_reg_value = 0x2B404040;
3277                         uniqtranscale_reg_value = 0x55ADDA3A;
3278                         break;
3279                 default:
3280                         return 0;
3281                 }
3282                 break;
3283         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3284                 preemph_reg_value = 0x0000000;
3285                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3286                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3287                         demph_reg_value = 0x2B305555;
3288                         uniqtranscale_reg_value = 0x5570B83A;
3289                         break;
3290                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3291                         demph_reg_value = 0x2B2B4040;
3292                         uniqtranscale_reg_value = 0x55ADDA3A;
3293                         break;
3294                 default:
3295                         return 0;
3296                 }
3297                 break;
3298         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3299                 preemph_reg_value = 0x0006000;
3300                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3301                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3302                         demph_reg_value = 0x1B405555;
3303                         uniqtranscale_reg_value = 0x55ADDA3A;
3304                         break;
3305                 default:
3306                         return 0;
3307                 }
3308                 break;
3309         default:
3310                 return 0;
3311         }
3312
3313         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3314                                  uniqtranscale_reg_value, 0);
3315
3316         return 0;
3317 }
3318
3319 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3320 {
3321         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3322         u32 deemph_reg_value, margin_reg_value;
3323         bool uniq_trans_scale = false;
3324         uint8_t train_set = intel_dp->train_set[0];
3325
3326         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3327         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3328                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3329                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3330                         deemph_reg_value = 128;
3331                         margin_reg_value = 52;
3332                         break;
3333                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3334                         deemph_reg_value = 128;
3335                         margin_reg_value = 77;
3336                         break;
3337                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3338                         deemph_reg_value = 128;
3339                         margin_reg_value = 102;
3340                         break;
3341                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3342                         deemph_reg_value = 128;
3343                         margin_reg_value = 154;
3344                         uniq_trans_scale = true;
3345                         break;
3346                 default:
3347                         return 0;
3348                 }
3349                 break;
3350         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3351                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3352                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3353                         deemph_reg_value = 85;
3354                         margin_reg_value = 78;
3355                         break;
3356                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3357                         deemph_reg_value = 85;
3358                         margin_reg_value = 116;
3359                         break;
3360                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3361                         deemph_reg_value = 85;
3362                         margin_reg_value = 154;
3363                         break;
3364                 default:
3365                         return 0;
3366                 }
3367                 break;
3368         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3369                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3370                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3371                         deemph_reg_value = 64;
3372                         margin_reg_value = 104;
3373                         break;
3374                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3375                         deemph_reg_value = 64;
3376                         margin_reg_value = 154;
3377                         break;
3378                 default:
3379                         return 0;
3380                 }
3381                 break;
3382         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3383                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3384                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3385                         deemph_reg_value = 43;
3386                         margin_reg_value = 154;
3387                         break;
3388                 default:
3389                         return 0;
3390                 }
3391                 break;
3392         default:
3393                 return 0;
3394         }
3395
3396         chv_set_phy_signal_level(encoder, deemph_reg_value,
3397                                  margin_reg_value, uniq_trans_scale);
3398
3399         return 0;
3400 }
3401
3402 static uint32_t
3403 gen4_signal_levels(uint8_t train_set)
3404 {
3405         uint32_t        signal_levels = 0;
3406
3407         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3408         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3409         default:
3410                 signal_levels |= DP_VOLTAGE_0_4;
3411                 break;
3412         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3413                 signal_levels |= DP_VOLTAGE_0_6;
3414                 break;
3415         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3416                 signal_levels |= DP_VOLTAGE_0_8;
3417                 break;
3418         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3419                 signal_levels |= DP_VOLTAGE_1_2;
3420                 break;
3421         }
3422         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3423         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3424         default:
3425                 signal_levels |= DP_PRE_EMPHASIS_0;
3426                 break;
3427         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3428                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3429                 break;
3430         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3431                 signal_levels |= DP_PRE_EMPHASIS_6;
3432                 break;
3433         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3434                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3435                 break;
3436         }
3437         return signal_levels;
3438 }
3439
3440 /* Gen6's DP voltage swing and pre-emphasis control */
3441 static uint32_t
3442 gen6_edp_signal_levels(uint8_t train_set)
3443 {
3444         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3445                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3446         switch (signal_levels) {
3447         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3448         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3449                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3450         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3451                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3452         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3453         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3454                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3455         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3456         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3457                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3458         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3459         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3460                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3461         default:
3462                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3463                               "0x%x\n", signal_levels);
3464                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3465         }
3466 }
3467
3468 /* Gen7's DP voltage swing and pre-emphasis control */
3469 static uint32_t
3470 gen7_edp_signal_levels(uint8_t train_set)
3471 {
3472         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3473                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3474         switch (signal_levels) {
3475         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3476                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3477         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3478                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3479         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3480                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3481
3482         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3483                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3484         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3485                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3486
3487         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3488                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3489         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3490                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3491
3492         default:
3493                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3494                               "0x%x\n", signal_levels);
3495                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3496         }
3497 }
3498
3499 void
3500 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3501 {
3502         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3503         enum port port = intel_dig_port->port;
3504         struct drm_device *dev = intel_dig_port->base.base.dev;
3505         struct drm_i915_private *dev_priv = to_i915(dev);
3506         uint32_t signal_levels, mask = 0;
3507         uint8_t train_set = intel_dp->train_set[0];
3508
3509         if (HAS_DDI(dev_priv)) {
3510                 signal_levels = ddi_signal_levels(intel_dp);
3511
3512                 if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
3513                         signal_levels = 0;
3514                 else
3515                         mask = DDI_BUF_EMP_MASK;
3516         } else if (IS_CHERRYVIEW(dev_priv)) {
3517                 signal_levels = chv_signal_levels(intel_dp);
3518         } else if (IS_VALLEYVIEW(dev_priv)) {
3519                 signal_levels = vlv_signal_levels(intel_dp);
3520         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3521                 signal_levels = gen7_edp_signal_levels(train_set);
3522                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3523         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3524                 signal_levels = gen6_edp_signal_levels(train_set);
3525                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3526         } else {
3527                 signal_levels = gen4_signal_levels(train_set);
3528                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3529         }
3530
3531         if (mask)
3532                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3533
3534         DRM_DEBUG_KMS("Using vswing level %d\n",
3535                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3536         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3537                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3538                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3539
3540         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3541
3542         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3543         POSTING_READ(intel_dp->output_reg);
3544 }
3545
3546 void
3547 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3548                                        uint8_t dp_train_pat)
3549 {
3550         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3551         struct drm_i915_private *dev_priv =
3552                 to_i915(intel_dig_port->base.base.dev);
3553
3554         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3555
3556         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3557         POSTING_READ(intel_dp->output_reg);
3558 }
3559
3560 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3561 {
3562         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3563         struct drm_device *dev = intel_dig_port->base.base.dev;
3564         struct drm_i915_private *dev_priv = to_i915(dev);
3565         enum port port = intel_dig_port->port;
3566         uint32_t val;
3567
3568         if (!HAS_DDI(dev_priv))
3569                 return;
3570
3571         val = I915_READ(DP_TP_CTL(port));
3572         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3573         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3574         I915_WRITE(DP_TP_CTL(port), val);
3575
3576         /*
3577          * On PORT_A we can have only eDP in SST mode. There the only reason
3578          * we need to set idle transmission mode is to work around a HW issue
3579          * where we enable the pipe while not in idle link-training mode.
3580          * In this case there is requirement to wait for a minimum number of
3581          * idle patterns to be sent.
3582          */
3583         if (port == PORT_A)
3584                 return;
3585
3586         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3587                                     DP_TP_STATUS_IDLE_DONE,
3588                                     DP_TP_STATUS_IDLE_DONE,
3589                                     1))
3590                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3591 }
3592
3593 static void
3594 intel_dp_link_down(struct intel_dp *intel_dp)
3595 {
3596         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3597         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3598         enum port port = intel_dig_port->port;
3599         struct drm_device *dev = intel_dig_port->base.base.dev;
3600         struct drm_i915_private *dev_priv = to_i915(dev);
3601         uint32_t DP = intel_dp->DP;
3602
3603         if (WARN_ON(HAS_DDI(dev_priv)))
3604                 return;
3605
3606         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3607                 return;
3608
3609         DRM_DEBUG_KMS("\n");
3610
3611         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3612             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3613                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3614                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3615         } else {
3616                 if (IS_CHERRYVIEW(dev_priv))
3617                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3618                 else
3619                         DP &= ~DP_LINK_TRAIN_MASK;
3620                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3621         }
3622         I915_WRITE(intel_dp->output_reg, DP);
3623         POSTING_READ(intel_dp->output_reg);
3624
3625         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3626         I915_WRITE(intel_dp->output_reg, DP);
3627         POSTING_READ(intel_dp->output_reg);
3628
3629         /*
3630          * HW workaround for IBX, we need to move the port
3631          * to transcoder A after disabling it to allow the
3632          * matching HDMI port to be enabled on transcoder A.
3633          */
3634         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3635                 /*
3636                  * We get CPU/PCH FIFO underruns on the other pipe when
3637                  * doing the workaround. Sweep them under the rug.
3638                  */
3639                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3640                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3641
3642                 /* always enable with pattern 1 (as per spec) */
3643                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3644                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3645                 I915_WRITE(intel_dp->output_reg, DP);
3646                 POSTING_READ(intel_dp->output_reg);
3647
3648                 DP &= ~DP_PORT_EN;
3649                 I915_WRITE(intel_dp->output_reg, DP);
3650                 POSTING_READ(intel_dp->output_reg);
3651
3652                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3653                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3654                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3655         }
3656
3657         msleep(intel_dp->panel_power_down_delay);
3658
3659         intel_dp->DP = DP;
3660
3661         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3662                 pps_lock(intel_dp);
3663                 intel_dp->active_pipe = INVALID_PIPE;
3664                 pps_unlock(intel_dp);
3665         }
3666 }
3667
3668 bool
3669 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3670 {
3671         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3672                              sizeof(intel_dp->dpcd)) < 0)
3673                 return false; /* aux transfer failed */
3674
3675         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3676
3677         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3678 }
3679
3680 static bool
3681 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3682 {
3683         struct drm_i915_private *dev_priv =
3684                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3685
3686         /* this function is meant to be called only once */
3687         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3688
3689         if (!intel_dp_read_dpcd(intel_dp))
3690                 return false;
3691
3692         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3693                          drm_dp_is_branch(intel_dp->dpcd));
3694
3695         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3696                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3697                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3698
3699         /* Check if the panel supports PSR */
3700         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3701                          intel_dp->psr_dpcd,
3702                          sizeof(intel_dp->psr_dpcd));
3703         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3704                 dev_priv->psr.sink_support = true;
3705                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3706         }
3707
3708         if (INTEL_GEN(dev_priv) >= 9 &&
3709             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3710                 uint8_t frame_sync_cap;
3711
3712                 dev_priv->psr.sink_support = true;
3713                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3714                                       DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3715                                       &frame_sync_cap) != 1)
3716                         frame_sync_cap = 0;
3717                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3718                 /* PSR2 needs frame sync as well */
3719                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3720                 DRM_DEBUG_KMS("PSR2 %s on sink",
3721                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3722
3723                 if (dev_priv->psr.psr2_support) {
3724                         dev_priv->psr.y_cord_support =
3725                                 intel_dp_get_y_cord_status(intel_dp);
3726                         dev_priv->psr.colorimetry_support =
3727                                 intel_dp_get_colorimetry_status(intel_dp);
3728                         dev_priv->psr.alpm =
3729                                 intel_dp_get_alpm_status(intel_dp);
3730                 }
3731
3732         }
3733
3734         /*
3735          * Read the eDP display control registers.
3736          *
3737          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3738          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3739          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3740          * method). The display control registers should read zero if they're
3741          * not supported anyway.
3742          */
3743         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3744                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3745                              sizeof(intel_dp->edp_dpcd))
3746                 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3747                               intel_dp->edp_dpcd);
3748
3749         /* Intermediate frequency support */
3750         if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3751                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3752                 int i;
3753
3754                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3755                                 sink_rates, sizeof(sink_rates));
3756
3757                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3758                         int val = le16_to_cpu(sink_rates[i]);
3759
3760                         if (val == 0)
3761                                 break;
3762
3763                         /* Value read multiplied by 200kHz gives the per-lane
3764                          * link rate in kHz. The source rates are, however,
3765                          * stored in terms of LS_Clk kHz. The full conversion
3766                          * back to symbols is
3767                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3768                          */
3769                         intel_dp->sink_rates[i] = (val * 200) / 10;
3770                 }
3771                 intel_dp->num_sink_rates = i;
3772         }
3773
3774         if (intel_dp->num_sink_rates)
3775                 intel_dp->use_rate_select = true;
3776         else
3777                 intel_dp_set_sink_rates(intel_dp);
3778
3779         intel_dp_set_common_rates(intel_dp);
3780
3781         return true;
3782 }
3783
3784
3785 static bool
3786 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3787 {
3788         u8 sink_count;
3789
3790         if (!intel_dp_read_dpcd(intel_dp))
3791                 return false;
3792
3793         /* Don't clobber cached eDP rates. */
3794         if (!is_edp(intel_dp)) {
3795                 intel_dp_set_sink_rates(intel_dp);
3796                 intel_dp_set_common_rates(intel_dp);
3797         }
3798
3799         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3800                 return false;
3801
3802         /*
3803          * Sink count can change between short pulse hpd hence
3804          * a member variable in intel_dp will track any changes
3805          * between short pulse interrupts.
3806          */
3807         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3808
3809         /*
3810          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3811          * a dongle is present but no display. Unless we require to know
3812          * if a dongle is present or not, we don't need to update
3813          * downstream port information. So, an early return here saves
3814          * time from performing other operations which are not required.
3815          */
3816         if (!is_edp(intel_dp) && !intel_dp->sink_count)
3817                 return false;
3818
3819         if (!drm_dp_is_branch(intel_dp->dpcd))
3820                 return true; /* native DP sink */
3821
3822         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3823                 return true; /* no per-port downstream info */
3824
3825         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3826                              intel_dp->downstream_ports,
3827                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3828                 return false; /* downstream port status fetch failed */
3829
3830         return true;
3831 }
3832
3833 static bool
3834 intel_dp_can_mst(struct intel_dp *intel_dp)
3835 {
3836         u8 mstm_cap;
3837
3838         if (!i915.enable_dp_mst)
3839                 return false;
3840
3841         if (!intel_dp->can_mst)
3842                 return false;
3843
3844         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3845                 return false;
3846
3847         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3848                 return false;
3849
3850         return mstm_cap & DP_MST_CAP;
3851 }
3852
3853 static void
3854 intel_dp_configure_mst(struct intel_dp *intel_dp)
3855 {
3856         if (!i915.enable_dp_mst)
3857                 return;
3858
3859         if (!intel_dp->can_mst)
3860                 return;
3861
3862         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3863
3864         if (intel_dp->is_mst)
3865                 DRM_DEBUG_KMS("Sink is MST capable\n");
3866         else
3867                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3868
3869         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3870                                         intel_dp->is_mst);
3871 }
3872
3873 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3874 {
3875         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3876         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3877         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3878         u8 buf;
3879         int ret = 0;
3880         int count = 0;
3881         int attempts = 10;
3882
3883         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3884                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3885                 ret = -EIO;
3886                 goto out;
3887         }
3888
3889         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3890                                buf & ~DP_TEST_SINK_START) < 0) {
3891                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3892                 ret = -EIO;
3893                 goto out;
3894         }
3895
3896         do {
3897                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3898
3899                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3900                                       DP_TEST_SINK_MISC, &buf) < 0) {
3901                         ret = -EIO;
3902                         goto out;
3903                 }
3904                 count = buf & DP_TEST_COUNT_MASK;
3905         } while (--attempts && count);
3906
3907         if (attempts == 0) {
3908                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3909                 ret = -ETIMEDOUT;
3910         }
3911
3912  out:
3913         hsw_enable_ips(intel_crtc);
3914         return ret;
3915 }
3916
3917 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3918 {
3919         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3920         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3921         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3922         u8 buf;
3923         int ret;
3924
3925         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3926                 return -EIO;
3927
3928         if (!(buf & DP_TEST_CRC_SUPPORTED))
3929                 return -ENOTTY;
3930
3931         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3932                 return -EIO;
3933
3934         if (buf & DP_TEST_SINK_START) {
3935                 ret = intel_dp_sink_crc_stop(intel_dp);
3936                 if (ret)
3937                         return ret;
3938         }
3939
3940         hsw_disable_ips(intel_crtc);
3941
3942         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3943                                buf | DP_TEST_SINK_START) < 0) {
3944                 hsw_enable_ips(intel_crtc);
3945                 return -EIO;
3946         }
3947
3948         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3949         return 0;
3950 }
3951
3952 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3953 {
3954         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3955         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3956         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3957         u8 buf;
3958         int count, ret;
3959         int attempts = 6;
3960
3961         ret = intel_dp_sink_crc_start(intel_dp);
3962         if (ret)
3963                 return ret;
3964
3965         do {
3966                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3967
3968                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3969                                       DP_TEST_SINK_MISC, &buf) < 0) {
3970                         ret = -EIO;
3971                         goto stop;
3972                 }
3973                 count = buf & DP_TEST_COUNT_MASK;
3974
3975         } while (--attempts && count == 0);
3976
3977         if (attempts == 0) {
3978                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3979                 ret = -ETIMEDOUT;
3980                 goto stop;
3981         }
3982
3983         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3984                 ret = -EIO;
3985                 goto stop;
3986         }
3987
3988 stop:
3989         intel_dp_sink_crc_stop(intel_dp);
3990         return ret;
3991 }
3992
3993 static bool
3994 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3995 {
3996         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
3997                                  sink_irq_vector) == 1;
3998 }
3999
4000 static bool
4001 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4002 {
4003         int ret;
4004
4005         ret = drm_dp_dpcd_read(&intel_dp->aux,
4006                                              DP_SINK_COUNT_ESI,
4007                                              sink_irq_vector, 14);
4008         if (ret != 14)
4009                 return false;
4010
4011         return true;
4012 }
4013
4014 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4015 {
4016         int status = 0;
4017         int test_link_rate;
4018         uint8_t test_lane_count, test_link_bw;
4019         /* (DP CTS 1.2)
4020          * 4.3.1.11
4021          */
4022         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4023         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4024                                    &test_lane_count);
4025
4026         if (status <= 0) {
4027                 DRM_DEBUG_KMS("Lane count read failed\n");
4028                 return DP_TEST_NAK;
4029         }
4030         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4031
4032         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4033                                    &test_link_bw);
4034         if (status <= 0) {
4035                 DRM_DEBUG_KMS("Link Rate read failed\n");
4036                 return DP_TEST_NAK;
4037         }
4038         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4039
4040         /* Validate the requested link rate and lane count */
4041         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4042                                         test_lane_count))
4043                 return DP_TEST_NAK;
4044
4045         intel_dp->compliance.test_lane_count = test_lane_count;
4046         intel_dp->compliance.test_link_rate = test_link_rate;
4047
4048         return DP_TEST_ACK;
4049 }
4050
4051 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4052 {
4053         uint8_t test_pattern;
4054         uint8_t test_misc;
4055         __be16 h_width, v_height;
4056         int status = 0;
4057
4058         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4059         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4060                                    &test_pattern);
4061         if (status <= 0) {
4062                 DRM_DEBUG_KMS("Test pattern read failed\n");
4063                 return DP_TEST_NAK;
4064         }
4065         if (test_pattern != DP_COLOR_RAMP)
4066                 return DP_TEST_NAK;
4067
4068         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4069                                   &h_width, 2);
4070         if (status <= 0) {
4071                 DRM_DEBUG_KMS("H Width read failed\n");
4072                 return DP_TEST_NAK;
4073         }
4074
4075         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4076                                   &v_height, 2);
4077         if (status <= 0) {
4078                 DRM_DEBUG_KMS("V Height read failed\n");
4079                 return DP_TEST_NAK;
4080         }
4081
4082         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4083                                    &test_misc);
4084         if (status <= 0) {
4085                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4086                 return DP_TEST_NAK;
4087         }
4088         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4089                 return DP_TEST_NAK;
4090         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4091                 return DP_TEST_NAK;
4092         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4093         case DP_TEST_BIT_DEPTH_6:
4094                 intel_dp->compliance.test_data.bpc = 6;
4095                 break;
4096         case DP_TEST_BIT_DEPTH_8:
4097                 intel_dp->compliance.test_data.bpc = 8;
4098                 break;
4099         default:
4100                 return DP_TEST_NAK;
4101         }
4102
4103         intel_dp->compliance.test_data.video_pattern = test_pattern;
4104         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4105         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4106         /* Set test active flag here so userspace doesn't interrupt things */
4107         intel_dp->compliance.test_active = 1;
4108
4109         return DP_TEST_ACK;
4110 }
4111
4112 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4113 {
4114         uint8_t test_result = DP_TEST_ACK;
4115         struct intel_connector *intel_connector = intel_dp->attached_connector;
4116         struct drm_connector *connector = &intel_connector->base;
4117
4118         if (intel_connector->detect_edid == NULL ||
4119             connector->edid_corrupt ||
4120             intel_dp->aux.i2c_defer_count > 6) {
4121                 /* Check EDID read for NACKs, DEFERs and corruption
4122                  * (DP CTS 1.2 Core r1.1)
4123                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4124                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4125                  *    4.2.2.6 : EDID corruption detected
4126                  * Use failsafe mode for all cases
4127                  */
4128                 if (intel_dp->aux.i2c_nack_count > 0 ||
4129                         intel_dp->aux.i2c_defer_count > 0)
4130                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4131                                       intel_dp->aux.i2c_nack_count,
4132                                       intel_dp->aux.i2c_defer_count);
4133                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4134         } else {
4135                 struct edid *block = intel_connector->detect_edid;
4136
4137                 /* We have to write the checksum
4138                  * of the last block read
4139                  */
4140                 block += intel_connector->detect_edid->extensions;
4141
4142                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4143                                        block->checksum) <= 0)
4144                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4145
4146                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4147                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4148         }
4149
4150         /* Set test active flag here so userspace doesn't interrupt things */
4151         intel_dp->compliance.test_active = 1;
4152
4153         return test_result;
4154 }
4155
4156 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4157 {
4158         uint8_t test_result = DP_TEST_NAK;
4159         return test_result;
4160 }
4161
4162 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4163 {
4164         uint8_t response = DP_TEST_NAK;
4165         uint8_t request = 0;
4166         int status;
4167
4168         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4169         if (status <= 0) {
4170                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4171                 goto update_status;
4172         }
4173
4174         switch (request) {
4175         case DP_TEST_LINK_TRAINING:
4176                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4177                 response = intel_dp_autotest_link_training(intel_dp);
4178                 break;
4179         case DP_TEST_LINK_VIDEO_PATTERN:
4180                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4181                 response = intel_dp_autotest_video_pattern(intel_dp);
4182                 break;
4183         case DP_TEST_LINK_EDID_READ:
4184                 DRM_DEBUG_KMS("EDID test requested\n");
4185                 response = intel_dp_autotest_edid(intel_dp);
4186                 break;
4187         case DP_TEST_LINK_PHY_TEST_PATTERN:
4188                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4189                 response = intel_dp_autotest_phy_pattern(intel_dp);
4190                 break;
4191         default:
4192                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4193                 break;
4194         }
4195
4196         if (response & DP_TEST_ACK)
4197                 intel_dp->compliance.test_type = request;
4198
4199 update_status:
4200         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4201         if (status <= 0)
4202                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4203 }
4204
4205 static int
4206 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4207 {
4208         bool bret;
4209
4210         if (intel_dp->is_mst) {
4211                 u8 esi[16] = { 0 };
4212                 int ret = 0;
4213                 int retry;
4214                 bool handled;
4215                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4216 go_again:
4217                 if (bret == true) {
4218
4219                         /* check link status - esi[10] = 0x200c */
4220                         if (intel_dp->active_mst_links &&
4221                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4222                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4223                                 intel_dp_start_link_train(intel_dp);
4224                                 intel_dp_stop_link_train(intel_dp);
4225                         }
4226
4227                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4228                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4229
4230                         if (handled) {
4231                                 for (retry = 0; retry < 3; retry++) {
4232                                         int wret;
4233                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4234                                                                  DP_SINK_COUNT_ESI+1,
4235                                                                  &esi[1], 3);
4236                                         if (wret == 3) {
4237                                                 break;
4238                                         }
4239                                 }
4240
4241                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4242                                 if (bret == true) {
4243                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4244                                         goto go_again;
4245                                 }
4246                         } else
4247                                 ret = 0;
4248
4249                         return ret;
4250                 } else {
4251                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4252                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4253                         intel_dp->is_mst = false;
4254                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4255                         /* send a hotplug event */
4256                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4257                 }
4258         }
4259         return -EINVAL;
4260 }
4261
4262 static void
4263 intel_dp_retrain_link(struct intel_dp *intel_dp)
4264 {
4265         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4266         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4267         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4268
4269         /* Suppress underruns caused by re-training */
4270         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4271         if (crtc->config->has_pch_encoder)
4272                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4273                                                       intel_crtc_pch_transcoder(crtc), false);
4274
4275         intel_dp_start_link_train(intel_dp);
4276         intel_dp_stop_link_train(intel_dp);
4277
4278         /* Keep underrun reporting disabled until things are stable */
4279         intel_wait_for_vblank(dev_priv, crtc->pipe);
4280
4281         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4282         if (crtc->config->has_pch_encoder)
4283                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4284                                                       intel_crtc_pch_transcoder(crtc), true);
4285 }
4286
4287 static void
4288 intel_dp_check_link_status(struct intel_dp *intel_dp)
4289 {
4290         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4291         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4292         u8 link_status[DP_LINK_STATUS_SIZE];
4293
4294         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4295
4296         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4297                 DRM_ERROR("Failed to get link status\n");
4298                 return;
4299         }
4300
4301         if (!intel_encoder->base.crtc)
4302                 return;
4303
4304         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4305                 return;
4306
4307         /*
4308          * Validate the cached values of intel_dp->link_rate and
4309          * intel_dp->lane_count before attempting to retrain.
4310          */
4311         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4312                                         intel_dp->lane_count))
4313                 return;
4314
4315         /* Retrain if Channel EQ or CR not ok */
4316         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4317                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4318                               intel_encoder->base.name);
4319
4320                 intel_dp_retrain_link(intel_dp);
4321         }
4322 }
4323
4324 /*
4325  * According to DP spec
4326  * 5.1.2:
4327  *  1. Read DPCD
4328  *  2. Configure link according to Receiver Capabilities
4329  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4330  *  4. Check link status on receipt of hot-plug interrupt
4331  *
4332  * intel_dp_short_pulse -  handles short pulse interrupts
4333  * when full detection is not required.
4334  * Returns %true if short pulse is handled and full detection
4335  * is NOT required and %false otherwise.
4336  */
4337 static bool
4338 intel_dp_short_pulse(struct intel_dp *intel_dp)
4339 {
4340         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4341         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4342         u8 sink_irq_vector = 0;
4343         u8 old_sink_count = intel_dp->sink_count;
4344         bool ret;
4345
4346         /*
4347          * Clearing compliance test variables to allow capturing
4348          * of values for next automated test request.
4349          */
4350         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4351
4352         /*
4353          * Now read the DPCD to see if it's actually running
4354          * If the current value of sink count doesn't match with
4355          * the value that was stored earlier or dpcd read failed
4356          * we need to do full detection
4357          */
4358         ret = intel_dp_get_dpcd(intel_dp);
4359
4360         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4361                 /* No need to proceed if we are going to do full detect */
4362                 return false;
4363         }
4364
4365         /* Try to read the source of the interrupt */
4366         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4367             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4368             sink_irq_vector != 0) {
4369                 /* Clear interrupt source */
4370                 drm_dp_dpcd_writeb(&intel_dp->aux,
4371                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4372                                    sink_irq_vector);
4373
4374                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4375                         intel_dp_handle_test_request(intel_dp);
4376                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4377                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4378         }
4379
4380         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4381         intel_dp_check_link_status(intel_dp);
4382         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4383         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4384                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4385                 /* Send a Hotplug Uevent to userspace to start modeset */
4386                 drm_kms_helper_hotplug_event(intel_encoder->base.dev);
4387         }
4388
4389         return true;
4390 }
4391
4392 /* XXX this is probably wrong for multiple downstream ports */
4393 static enum drm_connector_status
4394 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4395 {
4396         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4397         uint8_t *dpcd = intel_dp->dpcd;
4398         uint8_t type;
4399
4400         if (lspcon->active)
4401                 lspcon_resume(lspcon);
4402
4403         if (!intel_dp_get_dpcd(intel_dp))
4404                 return connector_status_disconnected;
4405
4406         if (is_edp(intel_dp))
4407                 return connector_status_connected;
4408
4409         /* if there's no downstream port, we're done */
4410         if (!drm_dp_is_branch(dpcd))
4411                 return connector_status_connected;
4412
4413         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4414         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4415             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4416
4417                 return intel_dp->sink_count ?
4418                 connector_status_connected : connector_status_disconnected;
4419         }
4420
4421         if (intel_dp_can_mst(intel_dp))
4422                 return connector_status_connected;
4423
4424         /* If no HPD, poke DDC gently */
4425         if (drm_probe_ddc(&intel_dp->aux.ddc))
4426                 return connector_status_connected;
4427
4428         /* Well we tried, say unknown for unreliable port types */
4429         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4430                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4431                 if (type == DP_DS_PORT_TYPE_VGA ||
4432                     type == DP_DS_PORT_TYPE_NON_EDID)
4433                         return connector_status_unknown;
4434         } else {
4435                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4436                         DP_DWN_STRM_PORT_TYPE_MASK;
4437                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4438                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4439                         return connector_status_unknown;
4440         }
4441
4442         /* Anything else is out of spec, warn and ignore */
4443         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4444         return connector_status_disconnected;
4445 }
4446
4447 static enum drm_connector_status
4448 edp_detect(struct intel_dp *intel_dp)
4449 {
4450         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4451         struct drm_i915_private *dev_priv = to_i915(dev);
4452         enum drm_connector_status status;
4453
4454         status = intel_panel_detect(dev_priv);
4455         if (status == connector_status_unknown)
4456                 status = connector_status_connected;
4457
4458         return status;
4459 }
4460
4461 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4462                                        struct intel_digital_port *port)
4463 {
4464         u32 bit;
4465
4466         switch (port->port) {
4467         case PORT_B:
4468                 bit = SDE_PORTB_HOTPLUG;
4469                 break;
4470         case PORT_C:
4471                 bit = SDE_PORTC_HOTPLUG;
4472                 break;
4473         case PORT_D:
4474                 bit = SDE_PORTD_HOTPLUG;
4475                 break;
4476         default:
4477                 MISSING_CASE(port->port);
4478                 return false;
4479         }
4480
4481         return I915_READ(SDEISR) & bit;
4482 }
4483
4484 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4485                                        struct intel_digital_port *port)
4486 {
4487         u32 bit;
4488
4489         switch (port->port) {
4490         case PORT_B:
4491                 bit = SDE_PORTB_HOTPLUG_CPT;
4492                 break;
4493         case PORT_C:
4494                 bit = SDE_PORTC_HOTPLUG_CPT;
4495                 break;
4496         case PORT_D:
4497                 bit = SDE_PORTD_HOTPLUG_CPT;
4498                 break;
4499         default:
4500                 MISSING_CASE(port->port);
4501                 return false;
4502         }
4503
4504         return I915_READ(SDEISR) & bit;
4505 }
4506
4507 static bool spt_digital_port_connected(struct drm_i915_private *dev_priv,
4508                                        struct intel_digital_port *port)
4509 {
4510         u32 bit;
4511
4512         switch (port->port) {
4513         case PORT_A:
4514                 bit = SDE_PORTA_HOTPLUG_SPT;
4515                 break;
4516         case PORT_E:
4517                 bit = SDE_PORTE_HOTPLUG_SPT;
4518                 break;
4519         default:
4520                 return cpt_digital_port_connected(dev_priv, port);
4521         }
4522
4523         return I915_READ(SDEISR) & bit;
4524 }
4525
4526 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4527                                        struct intel_digital_port *port)
4528 {
4529         u32 bit;
4530
4531         switch (port->port) {
4532         case PORT_B:
4533                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4534                 break;
4535         case PORT_C:
4536                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4537                 break;
4538         case PORT_D:
4539                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4540                 break;
4541         default:
4542                 MISSING_CASE(port->port);
4543                 return false;
4544         }
4545
4546         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4547 }
4548
4549 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4550                                         struct intel_digital_port *port)
4551 {
4552         u32 bit;
4553
4554         switch (port->port) {
4555         case PORT_B:
4556                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4557                 break;
4558         case PORT_C:
4559                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4560                 break;
4561         case PORT_D:
4562                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4563                 break;
4564         default:
4565                 MISSING_CASE(port->port);
4566                 return false;
4567         }
4568
4569         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4570 }
4571
4572 static bool ilk_digital_port_connected(struct drm_i915_private *dev_priv,
4573                                        struct intel_digital_port *port)
4574 {
4575         if (port->port == PORT_A)
4576                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4577         else
4578                 return ibx_digital_port_connected(dev_priv, port);
4579 }
4580
4581 static bool snb_digital_port_connected(struct drm_i915_private *dev_priv,
4582                                        struct intel_digital_port *port)
4583 {
4584         if (port->port == PORT_A)
4585                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4586         else
4587                 return cpt_digital_port_connected(dev_priv, port);
4588 }
4589
4590 static bool ivb_digital_port_connected(struct drm_i915_private *dev_priv,
4591                                        struct intel_digital_port *port)
4592 {
4593         if (port->port == PORT_A)
4594                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4595         else
4596                 return cpt_digital_port_connected(dev_priv, port);
4597 }
4598
4599 static bool bdw_digital_port_connected(struct drm_i915_private *dev_priv,
4600                                        struct intel_digital_port *port)
4601 {
4602         if (port->port == PORT_A)
4603                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4604         else
4605                 return cpt_digital_port_connected(dev_priv, port);
4606 }
4607
4608 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4609                                        struct intel_digital_port *intel_dig_port)
4610 {
4611         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4612         enum port port;
4613         u32 bit;
4614
4615         port = intel_hpd_pin_to_port(intel_encoder->hpd_pin);
4616         switch (port) {
4617         case PORT_A:
4618                 bit = BXT_DE_PORT_HP_DDIA;
4619                 break;
4620         case PORT_B:
4621                 bit = BXT_DE_PORT_HP_DDIB;
4622                 break;
4623         case PORT_C:
4624                 bit = BXT_DE_PORT_HP_DDIC;
4625                 break;
4626         default:
4627                 MISSING_CASE(port);
4628                 return false;
4629         }
4630
4631         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4632 }
4633
4634 /*
4635  * intel_digital_port_connected - is the specified port connected?
4636  * @dev_priv: i915 private structure
4637  * @port: the port to test
4638  *
4639  * Return %true if @port is connected, %false otherwise.
4640  */
4641 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4642                                   struct intel_digital_port *port)
4643 {
4644         if (HAS_GMCH_DISPLAY(dev_priv)) {
4645                 if (IS_GM45(dev_priv))
4646                         return gm45_digital_port_connected(dev_priv, port);
4647                 else
4648                         return g4x_digital_port_connected(dev_priv, port);
4649         }
4650
4651         if (IS_GEN5(dev_priv))
4652                 return ilk_digital_port_connected(dev_priv, port);
4653         else if (IS_GEN6(dev_priv))
4654                 return snb_digital_port_connected(dev_priv, port);
4655         else if (IS_GEN7(dev_priv))
4656                 return ivb_digital_port_connected(dev_priv, port);
4657         else if (IS_GEN8(dev_priv))
4658                 return bdw_digital_port_connected(dev_priv, port);
4659         else if (IS_GEN9_LP(dev_priv))
4660                 return bxt_digital_port_connected(dev_priv, port);
4661         else
4662                 return spt_digital_port_connected(dev_priv, port);
4663 }
4664
4665 static struct edid *
4666 intel_dp_get_edid(struct intel_dp *intel_dp)
4667 {
4668         struct intel_connector *intel_connector = intel_dp->attached_connector;
4669
4670         /* use cached edid if we have one */
4671         if (intel_connector->edid) {
4672                 /* invalid edid */
4673                 if (IS_ERR(intel_connector->edid))
4674                         return NULL;
4675
4676                 return drm_edid_duplicate(intel_connector->edid);
4677         } else
4678                 return drm_get_edid(&intel_connector->base,
4679                                     &intel_dp->aux.ddc);
4680 }
4681
4682 static void
4683 intel_dp_set_edid(struct intel_dp *intel_dp)
4684 {
4685         struct intel_connector *intel_connector = intel_dp->attached_connector;
4686         struct edid *edid;
4687
4688         intel_dp_unset_edid(intel_dp);
4689         edid = intel_dp_get_edid(intel_dp);
4690         intel_connector->detect_edid = edid;
4691
4692         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4693 }
4694
4695 static void
4696 intel_dp_unset_edid(struct intel_dp *intel_dp)
4697 {
4698         struct intel_connector *intel_connector = intel_dp->attached_connector;
4699
4700         kfree(intel_connector->detect_edid);
4701         intel_connector->detect_edid = NULL;
4702
4703         intel_dp->has_audio = false;
4704 }
4705
4706 static int
4707 intel_dp_long_pulse(struct intel_connector *intel_connector)
4708 {
4709         struct drm_connector *connector = &intel_connector->base;
4710         struct intel_dp *intel_dp = intel_attached_dp(connector);
4711         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4712         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4713         struct drm_device *dev = connector->dev;
4714         enum drm_connector_status status;
4715         u8 sink_irq_vector = 0;
4716
4717         WARN_ON(!drm_modeset_is_locked(&connector->dev->mode_config.connection_mutex));
4718
4719         intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
4720
4721         /* Can't disconnect eDP, but you can close the lid... */
4722         if (is_edp(intel_dp))
4723                 status = edp_detect(intel_dp);
4724         else if (intel_digital_port_connected(to_i915(dev),
4725                                               dp_to_dig_port(intel_dp)))
4726                 status = intel_dp_detect_dpcd(intel_dp);
4727         else
4728                 status = connector_status_disconnected;
4729
4730         if (status == connector_status_disconnected) {
4731                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4732
4733                 if (intel_dp->is_mst) {
4734                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4735                                       intel_dp->is_mst,
4736                                       intel_dp->mst_mgr.mst_state);
4737                         intel_dp->is_mst = false;
4738                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4739                                                         intel_dp->is_mst);
4740                 }
4741
4742                 goto out;
4743         }
4744
4745         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4746                 intel_encoder->type = INTEL_OUTPUT_DP;
4747
4748         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4749                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
4750                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4751
4752         if (intel_dp->reset_link_params) {
4753                 /* Initial max link lane count */
4754                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4755
4756                 /* Initial max link rate */
4757                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4758
4759                 intel_dp->reset_link_params = false;
4760         }
4761
4762         intel_dp_print_rates(intel_dp);
4763
4764         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4765                          drm_dp_is_branch(intel_dp->dpcd));
4766
4767         intel_dp_configure_mst(intel_dp);
4768
4769         if (intel_dp->is_mst) {
4770                 /*
4771                  * If we are in MST mode then this connector
4772                  * won't appear connected or have anything
4773                  * with EDID on it
4774                  */
4775                 status = connector_status_disconnected;
4776                 goto out;
4777         } else {
4778                 /*
4779                  * If display is now connected check links status,
4780                  * there has been known issues of link loss triggerring
4781                  * long pulse.
4782                  *
4783                  * Some sinks (eg. ASUS PB287Q) seem to perform some
4784                  * weird HPD ping pong during modesets. So we can apparently
4785                  * end up with HPD going low during a modeset, and then
4786                  * going back up soon after. And once that happens we must
4787                  * retrain the link to get a picture. That's in case no
4788                  * userspace component reacted to intermittent HPD dip.
4789                  */
4790                 intel_dp_check_link_status(intel_dp);
4791         }
4792
4793         /*
4794          * Clearing NACK and defer counts to get their exact values
4795          * while reading EDID which are required by Compliance tests
4796          * 4.2.2.4 and 4.2.2.5
4797          */
4798         intel_dp->aux.i2c_nack_count = 0;
4799         intel_dp->aux.i2c_defer_count = 0;
4800
4801         intel_dp_set_edid(intel_dp);
4802         if (is_edp(intel_dp) || intel_connector->detect_edid)
4803                 status = connector_status_connected;
4804         intel_dp->detect_done = true;
4805
4806         /* Try to read the source of the interrupt */
4807         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4808             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4809             sink_irq_vector != 0) {
4810                 /* Clear interrupt source */
4811                 drm_dp_dpcd_writeb(&intel_dp->aux,
4812                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4813                                    sink_irq_vector);
4814
4815                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4816                         intel_dp_handle_test_request(intel_dp);
4817                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4818                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4819         }
4820
4821 out:
4822         if (status != connector_status_connected && !intel_dp->is_mst)
4823                 intel_dp_unset_edid(intel_dp);
4824
4825         intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain);
4826         return status;
4827 }
4828
4829 static int
4830 intel_dp_detect(struct drm_connector *connector,
4831                 struct drm_modeset_acquire_ctx *ctx,
4832                 bool force)
4833 {
4834         struct intel_dp *intel_dp = intel_attached_dp(connector);
4835         int status = connector->status;
4836
4837         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4838                       connector->base.id, connector->name);
4839
4840         /* If full detect is not performed yet, do a full detect */
4841         if (!intel_dp->detect_done)
4842                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4843
4844         intel_dp->detect_done = false;
4845
4846         return status;
4847 }
4848
4849 static void
4850 intel_dp_force(struct drm_connector *connector)
4851 {
4852         struct intel_dp *intel_dp = intel_attached_dp(connector);
4853         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4854         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4855
4856         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4857                       connector->base.id, connector->name);
4858         intel_dp_unset_edid(intel_dp);
4859
4860         if (connector->status != connector_status_connected)
4861                 return;
4862
4863         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4864
4865         intel_dp_set_edid(intel_dp);
4866
4867         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4868
4869         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4870                 intel_encoder->type = INTEL_OUTPUT_DP;
4871 }
4872
4873 static int intel_dp_get_modes(struct drm_connector *connector)
4874 {
4875         struct intel_connector *intel_connector = to_intel_connector(connector);
4876         struct edid *edid;
4877
4878         edid = intel_connector->detect_edid;
4879         if (edid) {
4880                 int ret = intel_connector_update_modes(connector, edid);
4881                 if (ret)
4882                         return ret;
4883         }
4884
4885         /* if eDP has no EDID, fall back to fixed mode */
4886         if (is_edp(intel_attached_dp(connector)) &&
4887             intel_connector->panel.fixed_mode) {
4888                 struct drm_display_mode *mode;
4889
4890                 mode = drm_mode_duplicate(connector->dev,
4891                                           intel_connector->panel.fixed_mode);
4892                 if (mode) {
4893                         drm_mode_probed_add(connector, mode);
4894                         return 1;
4895                 }
4896         }
4897
4898         return 0;
4899 }
4900
4901 static int
4902 intel_dp_connector_register(struct drm_connector *connector)
4903 {
4904         struct intel_dp *intel_dp = intel_attached_dp(connector);
4905         int ret;
4906
4907         ret = intel_connector_register(connector);
4908         if (ret)
4909                 return ret;
4910
4911         i915_debugfs_connector_add(connector);
4912
4913         DRM_DEBUG_KMS("registering %s bus for %s\n",
4914                       intel_dp->aux.name, connector->kdev->kobj.name);
4915
4916         intel_dp->aux.dev = connector->kdev;
4917         return drm_dp_aux_register(&intel_dp->aux);
4918 }
4919
4920 static void
4921 intel_dp_connector_unregister(struct drm_connector *connector)
4922 {
4923         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4924         intel_connector_unregister(connector);
4925 }
4926
4927 static void
4928 intel_dp_connector_destroy(struct drm_connector *connector)
4929 {
4930         struct intel_connector *intel_connector = to_intel_connector(connector);
4931
4932         kfree(intel_connector->detect_edid);
4933
4934         if (!IS_ERR_OR_NULL(intel_connector->edid))
4935                 kfree(intel_connector->edid);
4936
4937         /* Can't call is_edp() since the encoder may have been destroyed
4938          * already. */
4939         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4940                 intel_panel_fini(&intel_connector->panel);
4941
4942         drm_connector_cleanup(connector);
4943         kfree(connector);
4944 }
4945
4946 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4947 {
4948         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4949         struct intel_dp *intel_dp = &intel_dig_port->dp;
4950
4951         intel_dp_mst_encoder_cleanup(intel_dig_port);
4952         if (is_edp(intel_dp)) {
4953                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4954                 /*
4955                  * vdd might still be enabled do to the delayed vdd off.
4956                  * Make sure vdd is actually turned off here.
4957                  */
4958                 pps_lock(intel_dp);
4959                 edp_panel_vdd_off_sync(intel_dp);
4960                 pps_unlock(intel_dp);
4961
4962                 if (intel_dp->edp_notifier.notifier_call) {
4963                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4964                         intel_dp->edp_notifier.notifier_call = NULL;
4965                 }
4966         }
4967
4968         intel_dp_aux_fini(intel_dp);
4969
4970         drm_encoder_cleanup(encoder);
4971         kfree(intel_dig_port);
4972 }
4973
4974 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4975 {
4976         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4977
4978         if (!is_edp(intel_dp))
4979                 return;
4980
4981         /*
4982          * vdd might still be enabled do to the delayed vdd off.
4983          * Make sure vdd is actually turned off here.
4984          */
4985         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4986         pps_lock(intel_dp);
4987         edp_panel_vdd_off_sync(intel_dp);
4988         pps_unlock(intel_dp);
4989 }
4990
4991 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4992 {
4993         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4994         struct drm_device *dev = intel_dig_port->base.base.dev;
4995         struct drm_i915_private *dev_priv = to_i915(dev);
4996
4997         lockdep_assert_held(&dev_priv->pps_mutex);
4998
4999         if (!edp_have_panel_vdd(intel_dp))
5000                 return;
5001
5002         /*
5003          * The VDD bit needs a power domain reference, so if the bit is
5004          * already enabled when we boot or resume, grab this reference and
5005          * schedule a vdd off, so we don't hold on to the reference
5006          * indefinitely.
5007          */
5008         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5009         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5010
5011         edp_panel_vdd_schedule_off(intel_dp);
5012 }
5013
5014 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5015 {
5016         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5017
5018         if ((intel_dp->DP & DP_PORT_EN) == 0)
5019                 return INVALID_PIPE;
5020
5021         if (IS_CHERRYVIEW(dev_priv))
5022                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5023         else
5024                 return PORT_TO_PIPE(intel_dp->DP);
5025 }
5026
5027 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5028 {
5029         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5030         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5031         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5032
5033         if (!HAS_DDI(dev_priv))
5034                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5035
5036         if (lspcon->active)
5037                 lspcon_resume(lspcon);
5038
5039         intel_dp->reset_link_params = true;
5040
5041         pps_lock(intel_dp);
5042
5043         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5044                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5045
5046         if (is_edp(intel_dp)) {
5047                 /* Reinit the power sequencer, in case BIOS did something with it. */
5048                 intel_dp_pps_init(encoder->dev, intel_dp);
5049                 intel_edp_panel_vdd_sanitize(intel_dp);
5050         }
5051
5052         pps_unlock(intel_dp);
5053 }
5054
5055 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5056         .force = intel_dp_force,
5057         .fill_modes = drm_helper_probe_single_connector_modes,
5058         .atomic_get_property = intel_digital_connector_atomic_get_property,
5059         .atomic_set_property = intel_digital_connector_atomic_set_property,
5060         .late_register = intel_dp_connector_register,
5061         .early_unregister = intel_dp_connector_unregister,
5062         .destroy = intel_dp_connector_destroy,
5063         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5064         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5065 };
5066
5067 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5068         .detect_ctx = intel_dp_detect,
5069         .get_modes = intel_dp_get_modes,
5070         .mode_valid = intel_dp_mode_valid,
5071         .atomic_check = intel_digital_connector_atomic_check,
5072 };
5073
5074 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5075         .reset = intel_dp_encoder_reset,
5076         .destroy = intel_dp_encoder_destroy,
5077 };
5078
5079 enum irqreturn
5080 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5081 {
5082         struct intel_dp *intel_dp = &intel_dig_port->dp;
5083         struct drm_device *dev = intel_dig_port->base.base.dev;
5084         struct drm_i915_private *dev_priv = to_i915(dev);
5085         enum irqreturn ret = IRQ_NONE;
5086
5087         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
5088             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
5089                 intel_dig_port->base.type = INTEL_OUTPUT_DP;
5090
5091         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5092                 /*
5093                  * vdd off can generate a long pulse on eDP which
5094                  * would require vdd on to handle it, and thus we
5095                  * would end up in an endless cycle of
5096                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5097                  */
5098                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5099                               port_name(intel_dig_port->port));
5100                 return IRQ_HANDLED;
5101         }
5102
5103         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5104                       port_name(intel_dig_port->port),
5105                       long_hpd ? "long" : "short");
5106
5107         if (long_hpd) {
5108                 intel_dp->reset_link_params = true;
5109                 intel_dp->detect_done = false;
5110                 return IRQ_NONE;
5111         }
5112
5113         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5114
5115         if (intel_dp->is_mst) {
5116                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5117                         /*
5118                          * If we were in MST mode, and device is not
5119                          * there, get out of MST mode
5120                          */
5121                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5122                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5123                         intel_dp->is_mst = false;
5124                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5125                                                         intel_dp->is_mst);
5126                         intel_dp->detect_done = false;
5127                         goto put_power;
5128                 }
5129         }
5130
5131         if (!intel_dp->is_mst) {
5132                 if (!intel_dp_short_pulse(intel_dp)) {
5133                         intel_dp->detect_done = false;
5134                         goto put_power;
5135                 }
5136         }
5137
5138         ret = IRQ_HANDLED;
5139
5140 put_power:
5141         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5142
5143         return ret;
5144 }
5145
5146 /* check the VBT to see whether the eDP is on another port */
5147 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
5148 {
5149         /*
5150          * eDP not supported on g4x. so bail out early just
5151          * for a bit extra safety in case the VBT is bonkers.
5152          */
5153         if (INTEL_GEN(dev_priv) < 5)
5154                 return false;
5155
5156         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5157                 return true;
5158
5159         return intel_bios_is_port_edp(dev_priv, port);
5160 }
5161
5162 static void
5163 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5164 {
5165         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5166
5167         intel_attach_force_audio_property(connector);
5168         intel_attach_broadcast_rgb_property(connector);
5169
5170         if (is_edp(intel_dp)) {
5171                 u32 allowed_scalers;
5172
5173                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5174                 if (!HAS_GMCH_DISPLAY(dev_priv))
5175                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5176
5177                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5178
5179                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5180
5181         }
5182 }
5183
5184 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5185 {
5186         intel_dp->panel_power_off_time = ktime_get_boottime();
5187         intel_dp->last_power_on = jiffies;
5188         intel_dp->last_backlight_off = jiffies;
5189 }
5190
5191 static void
5192 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5193                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
5194 {
5195         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5196         struct pps_registers regs;
5197
5198         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5199
5200         /* Workaround: Need to write PP_CONTROL with the unlock key as
5201          * the very first thing. */
5202         pp_ctl = ironlake_get_pp_control(intel_dp);
5203
5204         pp_on = I915_READ(regs.pp_on);
5205         pp_off = I915_READ(regs.pp_off);
5206         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
5207                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5208                 pp_div = I915_READ(regs.pp_div);
5209         }
5210
5211         /* Pull timing values out of registers */
5212         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5213                      PANEL_POWER_UP_DELAY_SHIFT;
5214
5215         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5216                   PANEL_LIGHT_ON_DELAY_SHIFT;
5217
5218         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5219                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5220
5221         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5222                    PANEL_POWER_DOWN_DELAY_SHIFT;
5223
5224         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5225                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5226                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5227         } else {
5228                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5229                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5230         }
5231 }
5232
5233 static void
5234 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5235 {
5236         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5237                       state_name,
5238                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5239 }
5240
5241 static void
5242 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5243                        struct intel_dp *intel_dp)
5244 {
5245         struct edp_power_seq hw;
5246         struct edp_power_seq *sw = &intel_dp->pps_delays;
5247
5248         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5249
5250         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5251             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5252                 DRM_ERROR("PPS state mismatch\n");
5253                 intel_pps_dump_state("sw", sw);
5254                 intel_pps_dump_state("hw", &hw);
5255         }
5256 }
5257
5258 static void
5259 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5260                                     struct intel_dp *intel_dp)
5261 {
5262         struct drm_i915_private *dev_priv = to_i915(dev);
5263         struct edp_power_seq cur, vbt, spec,
5264                 *final = &intel_dp->pps_delays;
5265
5266         lockdep_assert_held(&dev_priv->pps_mutex);
5267
5268         /* already initialized? */
5269         if (final->t11_t12 != 0)
5270                 return;
5271
5272         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5273
5274         intel_pps_dump_state("cur", &cur);
5275
5276         vbt = dev_priv->vbt.edp.pps;
5277         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5278          * of 500ms appears to be too short. Ocassionally the panel
5279          * just fails to power back on. Increasing the delay to 800ms
5280          * seems sufficient to avoid this problem.
5281          */
5282         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5283                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5284                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5285                               vbt.t11_t12);
5286         }
5287         /* T11_T12 delay is special and actually in units of 100ms, but zero
5288          * based in the hw (so we need to add 100 ms). But the sw vbt
5289          * table multiplies it with 1000 to make it in units of 100usec,
5290          * too. */
5291         vbt.t11_t12 += 100 * 10;
5292
5293         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5294          * our hw here, which are all in 100usec. */
5295         spec.t1_t3 = 210 * 10;
5296         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5297         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5298         spec.t10 = 500 * 10;
5299         /* This one is special and actually in units of 100ms, but zero
5300          * based in the hw (so we need to add 100 ms). But the sw vbt
5301          * table multiplies it with 1000 to make it in units of 100usec,
5302          * too. */
5303         spec.t11_t12 = (510 + 100) * 10;
5304
5305         intel_pps_dump_state("vbt", &vbt);
5306
5307         /* Use the max of the register settings and vbt. If both are
5308          * unset, fall back to the spec limits. */
5309 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5310                                        spec.field : \
5311                                        max(cur.field, vbt.field))
5312         assign_final(t1_t3);
5313         assign_final(t8);
5314         assign_final(t9);
5315         assign_final(t10);
5316         assign_final(t11_t12);
5317 #undef assign_final
5318
5319 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5320         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5321         intel_dp->backlight_on_delay = get_delay(t8);
5322         intel_dp->backlight_off_delay = get_delay(t9);
5323         intel_dp->panel_power_down_delay = get_delay(t10);
5324         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5325 #undef get_delay
5326
5327         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5328                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5329                       intel_dp->panel_power_cycle_delay);
5330
5331         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5332                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5333
5334         /*
5335          * We override the HW backlight delays to 1 because we do manual waits
5336          * on them. For T8, even BSpec recommends doing it. For T9, if we
5337          * don't do this, we'll end up waiting for the backlight off delay
5338          * twice: once when we do the manual sleep, and once when we disable
5339          * the panel and wait for the PP_STATUS bit to become zero.
5340          */
5341         final->t8 = 1;
5342         final->t9 = 1;
5343 }
5344
5345 static void
5346 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5347                                               struct intel_dp *intel_dp,
5348                                               bool force_disable_vdd)
5349 {
5350         struct drm_i915_private *dev_priv = to_i915(dev);
5351         u32 pp_on, pp_off, pp_div, port_sel = 0;
5352         int div = dev_priv->rawclk_freq / 1000;
5353         struct pps_registers regs;
5354         enum port port = dp_to_dig_port(intel_dp)->port;
5355         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5356
5357         lockdep_assert_held(&dev_priv->pps_mutex);
5358
5359         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5360
5361         /*
5362          * On some VLV machines the BIOS can leave the VDD
5363          * enabled even on power seqeuencers which aren't
5364          * hooked up to any port. This would mess up the
5365          * power domain tracking the first time we pick
5366          * one of these power sequencers for use since
5367          * edp_panel_vdd_on() would notice that the VDD was
5368          * already on and therefore wouldn't grab the power
5369          * domain reference. Disable VDD first to avoid this.
5370          * This also avoids spuriously turning the VDD on as
5371          * soon as the new power seqeuencer gets initialized.
5372          */
5373         if (force_disable_vdd) {
5374                 u32 pp = ironlake_get_pp_control(intel_dp);
5375
5376                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5377
5378                 if (pp & EDP_FORCE_VDD)
5379                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5380
5381                 pp &= ~EDP_FORCE_VDD;
5382
5383                 I915_WRITE(regs.pp_ctrl, pp);
5384         }
5385
5386         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5387                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5388         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5389                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5390         /* Compute the divisor for the pp clock, simply match the Bspec
5391          * formula. */
5392         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5393                 pp_div = I915_READ(regs.pp_ctrl);
5394                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5395                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5396                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5397         } else {
5398                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5399                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5400                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5401         }
5402
5403         /* Haswell doesn't have any port selection bits for the panel
5404          * power sequencer any more. */
5405         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5406                 port_sel = PANEL_PORT_SELECT_VLV(port);
5407         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5408                 if (port == PORT_A)
5409                         port_sel = PANEL_PORT_SELECT_DPA;
5410                 else
5411                         port_sel = PANEL_PORT_SELECT_DPD;
5412         }
5413
5414         pp_on |= port_sel;
5415
5416         I915_WRITE(regs.pp_on, pp_on);
5417         I915_WRITE(regs.pp_off, pp_off);
5418         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
5419                 I915_WRITE(regs.pp_ctrl, pp_div);
5420         else
5421                 I915_WRITE(regs.pp_div, pp_div);
5422
5423         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5424                       I915_READ(regs.pp_on),
5425                       I915_READ(regs.pp_off),
5426                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
5427                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5428                       I915_READ(regs.pp_div));
5429 }
5430
5431 static void intel_dp_pps_init(struct drm_device *dev,
5432                               struct intel_dp *intel_dp)
5433 {
5434         struct drm_i915_private *dev_priv = to_i915(dev);
5435
5436         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5437                 vlv_initial_power_sequencer_setup(intel_dp);
5438         } else {
5439                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5440                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5441         }
5442 }
5443
5444 /**
5445  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5446  * @dev_priv: i915 device
5447  * @crtc_state: a pointer to the active intel_crtc_state
5448  * @refresh_rate: RR to be programmed
5449  *
5450  * This function gets called when refresh rate (RR) has to be changed from
5451  * one frequency to another. Switches can be between high and low RR
5452  * supported by the panel or to any other RR based on media playback (in
5453  * this case, RR value needs to be passed from user space).
5454  *
5455  * The caller of this function needs to take a lock on dev_priv->drrs.
5456  */
5457 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5458                                     struct intel_crtc_state *crtc_state,
5459                                     int refresh_rate)
5460 {
5461         struct intel_encoder *encoder;
5462         struct intel_digital_port *dig_port = NULL;
5463         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5465         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5466
5467         if (refresh_rate <= 0) {
5468                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5469                 return;
5470         }
5471
5472         if (intel_dp == NULL) {
5473                 DRM_DEBUG_KMS("DRRS not supported.\n");
5474                 return;
5475         }
5476
5477         /*
5478          * FIXME: This needs proper synchronization with psr state for some
5479          * platforms that cannot have PSR and DRRS enabled at the same time.
5480          */
5481
5482         dig_port = dp_to_dig_port(intel_dp);
5483         encoder = &dig_port->base;
5484         intel_crtc = to_intel_crtc(encoder->base.crtc);
5485
5486         if (!intel_crtc) {
5487                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5488                 return;
5489         }
5490
5491         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5492                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5493                 return;
5494         }
5495
5496         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5497                         refresh_rate)
5498                 index = DRRS_LOW_RR;
5499
5500         if (index == dev_priv->drrs.refresh_rate_type) {
5501                 DRM_DEBUG_KMS(
5502                         "DRRS requested for previously set RR...ignoring\n");
5503                 return;
5504         }
5505
5506         if (!crtc_state->base.active) {
5507                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5508                 return;
5509         }
5510
5511         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5512                 switch (index) {
5513                 case DRRS_HIGH_RR:
5514                         intel_dp_set_m_n(intel_crtc, M1_N1);
5515                         break;
5516                 case DRRS_LOW_RR:
5517                         intel_dp_set_m_n(intel_crtc, M2_N2);
5518                         break;
5519                 case DRRS_MAX_RR:
5520                 default:
5521                         DRM_ERROR("Unsupported refreshrate type\n");
5522                 }
5523         } else if (INTEL_GEN(dev_priv) > 6) {
5524                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5525                 u32 val;
5526
5527                 val = I915_READ(reg);
5528                 if (index > DRRS_HIGH_RR) {
5529                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5530                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5531                         else
5532                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5533                 } else {
5534                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5535                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5536                         else
5537                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5538                 }
5539                 I915_WRITE(reg, val);
5540         }
5541
5542         dev_priv->drrs.refresh_rate_type = index;
5543
5544         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5545 }
5546
5547 /**
5548  * intel_edp_drrs_enable - init drrs struct if supported
5549  * @intel_dp: DP struct
5550  * @crtc_state: A pointer to the active crtc state.
5551  *
5552  * Initializes frontbuffer_bits and drrs.dp
5553  */
5554 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5555                            struct intel_crtc_state *crtc_state)
5556 {
5557         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5558         struct drm_i915_private *dev_priv = to_i915(dev);
5559
5560         if (!crtc_state->has_drrs) {
5561                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5562                 return;
5563         }
5564
5565         mutex_lock(&dev_priv->drrs.mutex);
5566         if (WARN_ON(dev_priv->drrs.dp)) {
5567                 DRM_ERROR("DRRS already enabled\n");
5568                 goto unlock;
5569         }
5570
5571         dev_priv->drrs.busy_frontbuffer_bits = 0;
5572
5573         dev_priv->drrs.dp = intel_dp;
5574
5575 unlock:
5576         mutex_unlock(&dev_priv->drrs.mutex);
5577 }
5578
5579 /**
5580  * intel_edp_drrs_disable - Disable DRRS
5581  * @intel_dp: DP struct
5582  * @old_crtc_state: Pointer to old crtc_state.
5583  *
5584  */
5585 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5586                             struct intel_crtc_state *old_crtc_state)
5587 {
5588         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5589         struct drm_i915_private *dev_priv = to_i915(dev);
5590
5591         if (!old_crtc_state->has_drrs)
5592                 return;
5593
5594         mutex_lock(&dev_priv->drrs.mutex);
5595         if (!dev_priv->drrs.dp) {
5596                 mutex_unlock(&dev_priv->drrs.mutex);
5597                 return;
5598         }
5599
5600         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5601                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5602                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5603
5604         dev_priv->drrs.dp = NULL;
5605         mutex_unlock(&dev_priv->drrs.mutex);
5606
5607         cancel_delayed_work_sync(&dev_priv->drrs.work);
5608 }
5609
5610 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5611 {
5612         struct drm_i915_private *dev_priv =
5613                 container_of(work, typeof(*dev_priv), drrs.work.work);
5614         struct intel_dp *intel_dp;
5615
5616         mutex_lock(&dev_priv->drrs.mutex);
5617
5618         intel_dp = dev_priv->drrs.dp;
5619
5620         if (!intel_dp)
5621                 goto unlock;
5622
5623         /*
5624          * The delayed work can race with an invalidate hence we need to
5625          * recheck.
5626          */
5627
5628         if (dev_priv->drrs.busy_frontbuffer_bits)
5629                 goto unlock;
5630
5631         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5632                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5633
5634                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5635                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5636         }
5637
5638 unlock:
5639         mutex_unlock(&dev_priv->drrs.mutex);
5640 }
5641
5642 /**
5643  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5644  * @dev_priv: i915 device
5645  * @frontbuffer_bits: frontbuffer plane tracking bits
5646  *
5647  * This function gets called everytime rendering on the given planes start.
5648  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5649  *
5650  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5651  */
5652 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5653                                unsigned int frontbuffer_bits)
5654 {
5655         struct drm_crtc *crtc;
5656         enum pipe pipe;
5657
5658         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5659                 return;
5660
5661         cancel_delayed_work(&dev_priv->drrs.work);
5662
5663         mutex_lock(&dev_priv->drrs.mutex);
5664         if (!dev_priv->drrs.dp) {
5665                 mutex_unlock(&dev_priv->drrs.mutex);
5666                 return;
5667         }
5668
5669         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5670         pipe = to_intel_crtc(crtc)->pipe;
5671
5672         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5673         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5674
5675         /* invalidate means busy screen hence upclock */
5676         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5677                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5678                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5679
5680         mutex_unlock(&dev_priv->drrs.mutex);
5681 }
5682
5683 /**
5684  * intel_edp_drrs_flush - Restart Idleness DRRS
5685  * @dev_priv: i915 device
5686  * @frontbuffer_bits: frontbuffer plane tracking bits
5687  *
5688  * This function gets called every time rendering on the given planes has
5689  * completed or flip on a crtc is completed. So DRRS should be upclocked
5690  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5691  * if no other planes are dirty.
5692  *
5693  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5694  */
5695 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5696                           unsigned int frontbuffer_bits)
5697 {
5698         struct drm_crtc *crtc;
5699         enum pipe pipe;
5700
5701         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5702                 return;
5703
5704         cancel_delayed_work(&dev_priv->drrs.work);
5705
5706         mutex_lock(&dev_priv->drrs.mutex);
5707         if (!dev_priv->drrs.dp) {
5708                 mutex_unlock(&dev_priv->drrs.mutex);
5709                 return;
5710         }
5711
5712         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5713         pipe = to_intel_crtc(crtc)->pipe;
5714
5715         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5716         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5717
5718         /* flush means busy screen hence upclock */
5719         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5720                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5721                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5722
5723         /*
5724          * flush also means no more activity hence schedule downclock, if all
5725          * other fbs are quiescent too
5726          */
5727         if (!dev_priv->drrs.busy_frontbuffer_bits)
5728                 schedule_delayed_work(&dev_priv->drrs.work,
5729                                 msecs_to_jiffies(1000));
5730         mutex_unlock(&dev_priv->drrs.mutex);
5731 }
5732
5733 /**
5734  * DOC: Display Refresh Rate Switching (DRRS)
5735  *
5736  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5737  * which enables swtching between low and high refresh rates,
5738  * dynamically, based on the usage scenario. This feature is applicable
5739  * for internal panels.
5740  *
5741  * Indication that the panel supports DRRS is given by the panel EDID, which
5742  * would list multiple refresh rates for one resolution.
5743  *
5744  * DRRS is of 2 types - static and seamless.
5745  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5746  * (may appear as a blink on screen) and is used in dock-undock scenario.
5747  * Seamless DRRS involves changing RR without any visual effect to the user
5748  * and can be used during normal system usage. This is done by programming
5749  * certain registers.
5750  *
5751  * Support for static/seamless DRRS may be indicated in the VBT based on
5752  * inputs from the panel spec.
5753  *
5754  * DRRS saves power by switching to low RR based on usage scenarios.
5755  *
5756  * The implementation is based on frontbuffer tracking implementation.  When
5757  * there is a disturbance on the screen triggered by user activity or a periodic
5758  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5759  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5760  * made.
5761  *
5762  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5763  * and intel_edp_drrs_flush() are called.
5764  *
5765  * DRRS can be further extended to support other internal panels and also
5766  * the scenario of video playback wherein RR is set based on the rate
5767  * requested by userspace.
5768  */
5769
5770 /**
5771  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5772  * @intel_connector: eDP connector
5773  * @fixed_mode: preferred mode of panel
5774  *
5775  * This function is  called only once at driver load to initialize basic
5776  * DRRS stuff.
5777  *
5778  * Returns:
5779  * Downclock mode if panel supports it, else return NULL.
5780  * DRRS support is determined by the presence of downclock mode (apart
5781  * from VBT setting).
5782  */
5783 static struct drm_display_mode *
5784 intel_dp_drrs_init(struct intel_connector *intel_connector,
5785                 struct drm_display_mode *fixed_mode)
5786 {
5787         struct drm_connector *connector = &intel_connector->base;
5788         struct drm_device *dev = connector->dev;
5789         struct drm_i915_private *dev_priv = to_i915(dev);
5790         struct drm_display_mode *downclock_mode = NULL;
5791
5792         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5793         mutex_init(&dev_priv->drrs.mutex);
5794
5795         if (INTEL_GEN(dev_priv) <= 6) {
5796                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5797                 return NULL;
5798         }
5799
5800         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5801                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5802                 return NULL;
5803         }
5804
5805         downclock_mode = intel_find_panel_downclock
5806                                         (dev_priv, fixed_mode, connector);
5807
5808         if (!downclock_mode) {
5809                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5810                 return NULL;
5811         }
5812
5813         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5814
5815         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5816         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5817         return downclock_mode;
5818 }
5819
5820 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5821                                      struct intel_connector *intel_connector)
5822 {
5823         struct drm_connector *connector = &intel_connector->base;
5824         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5825         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5826         struct drm_device *dev = intel_encoder->base.dev;
5827         struct drm_i915_private *dev_priv = to_i915(dev);
5828         struct drm_display_mode *fixed_mode = NULL;
5829         struct drm_display_mode *alt_fixed_mode = NULL;
5830         struct drm_display_mode *downclock_mode = NULL;
5831         bool has_dpcd;
5832         struct drm_display_mode *scan;
5833         struct edid *edid;
5834         enum pipe pipe = INVALID_PIPE;
5835
5836         if (!is_edp(intel_dp))
5837                 return true;
5838
5839         /*
5840          * On IBX/CPT we may get here with LVDS already registered. Since the
5841          * driver uses the only internal power sequencer available for both
5842          * eDP and LVDS bail out early in this case to prevent interfering
5843          * with an already powered-on LVDS power sequencer.
5844          */
5845         if (intel_get_lvds_encoder(dev)) {
5846                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5847                 DRM_INFO("LVDS was detected, not registering eDP\n");
5848
5849                 return false;
5850         }
5851
5852         pps_lock(intel_dp);
5853
5854         intel_dp_init_panel_power_timestamps(intel_dp);
5855         intel_dp_pps_init(dev, intel_dp);
5856         intel_edp_panel_vdd_sanitize(intel_dp);
5857
5858         pps_unlock(intel_dp);
5859
5860         /* Cache DPCD and EDID for edp. */
5861         has_dpcd = intel_edp_init_dpcd(intel_dp);
5862
5863         if (!has_dpcd) {
5864                 /* if this fails, presume the device is a ghost */
5865                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5866                 goto out_vdd_off;
5867         }
5868
5869         mutex_lock(&dev->mode_config.mutex);
5870         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5871         if (edid) {
5872                 if (drm_add_edid_modes(connector, edid)) {
5873                         drm_mode_connector_update_edid_property(connector,
5874                                                                 edid);
5875                         drm_edid_to_eld(connector, edid);
5876                 } else {
5877                         kfree(edid);
5878                         edid = ERR_PTR(-EINVAL);
5879                 }
5880         } else {
5881                 edid = ERR_PTR(-ENOENT);
5882         }
5883         intel_connector->edid = edid;
5884
5885         /* prefer fixed mode from EDID if available, save an alt mode also */
5886         list_for_each_entry(scan, &connector->probed_modes, head) {
5887                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5888                         fixed_mode = drm_mode_duplicate(dev, scan);
5889                         downclock_mode = intel_dp_drrs_init(
5890                                                 intel_connector, fixed_mode);
5891                 } else if (!alt_fixed_mode) {
5892                         alt_fixed_mode = drm_mode_duplicate(dev, scan);
5893                 }
5894         }
5895
5896         /* fallback to VBT if available for eDP */
5897         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5898                 fixed_mode = drm_mode_duplicate(dev,
5899                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5900                 if (fixed_mode) {
5901                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5902                         connector->display_info.width_mm = fixed_mode->width_mm;
5903                         connector->display_info.height_mm = fixed_mode->height_mm;
5904                 }
5905         }
5906         mutex_unlock(&dev->mode_config.mutex);
5907
5908         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5909                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5910                 register_reboot_notifier(&intel_dp->edp_notifier);
5911
5912                 /*
5913                  * Figure out the current pipe for the initial backlight setup.
5914                  * If the current pipe isn't valid, try the PPS pipe, and if that
5915                  * fails just assume pipe A.
5916                  */
5917                 pipe = vlv_active_pipe(intel_dp);
5918
5919                 if (pipe != PIPE_A && pipe != PIPE_B)
5920                         pipe = intel_dp->pps_pipe;
5921
5922                 if (pipe != PIPE_A && pipe != PIPE_B)
5923                         pipe = PIPE_A;
5924
5925                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5926                               pipe_name(pipe));
5927         }
5928
5929         intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode,
5930                          downclock_mode);
5931         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5932         intel_panel_setup_backlight(connector, pipe);
5933
5934         return true;
5935
5936 out_vdd_off:
5937         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5938         /*
5939          * vdd might still be enabled do to the delayed vdd off.
5940          * Make sure vdd is actually turned off here.
5941          */
5942         pps_lock(intel_dp);
5943         edp_panel_vdd_off_sync(intel_dp);
5944         pps_unlock(intel_dp);
5945
5946         return false;
5947 }
5948
5949 /* Set up the hotplug pin and aux power domain. */
5950 static void
5951 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5952 {
5953         struct intel_encoder *encoder = &intel_dig_port->base;
5954         struct intel_dp *intel_dp = &intel_dig_port->dp;
5955
5956         encoder->hpd_pin = intel_hpd_pin(intel_dig_port->port);
5957
5958         switch (intel_dig_port->port) {
5959         case PORT_A:
5960                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5961                 break;
5962         case PORT_B:
5963                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5964                 break;
5965         case PORT_C:
5966                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5967                 break;
5968         case PORT_D:
5969                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5970                 break;
5971         case PORT_E:
5972                 /* FIXME: Check VBT for actual wiring of PORT E */
5973                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5974                 break;
5975         default:
5976                 MISSING_CASE(intel_dig_port->port);
5977         }
5978 }
5979
5980 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5981 {
5982         struct intel_connector *intel_connector;
5983         struct drm_connector *connector;
5984
5985         intel_connector = container_of(work, typeof(*intel_connector),
5986                                        modeset_retry_work);
5987         connector = &intel_connector->base;
5988         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5989                       connector->name);
5990
5991         /* Grab the locks before changing connector property*/
5992         mutex_lock(&connector->dev->mode_config.mutex);
5993         /* Set connector link status to BAD and send a Uevent to notify
5994          * userspace to do a modeset.
5995          */
5996         drm_mode_connector_set_link_status_property(connector,
5997                                                     DRM_MODE_LINK_STATUS_BAD);
5998         mutex_unlock(&connector->dev->mode_config.mutex);
5999         /* Send Hotplug uevent so userspace can reprobe */
6000         drm_kms_helper_hotplug_event(connector->dev);
6001 }
6002
6003 bool
6004 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6005                         struct intel_connector *intel_connector)
6006 {
6007         struct drm_connector *connector = &intel_connector->base;
6008         struct intel_dp *intel_dp = &intel_dig_port->dp;
6009         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6010         struct drm_device *dev = intel_encoder->base.dev;
6011         struct drm_i915_private *dev_priv = to_i915(dev);
6012         enum port port = intel_dig_port->port;
6013         int type;
6014
6015         /* Initialize the work for modeset in case of link train failure */
6016         INIT_WORK(&intel_connector->modeset_retry_work,
6017                   intel_dp_modeset_retry_work_fn);
6018
6019         if (WARN(intel_dig_port->max_lanes < 1,
6020                  "Not enough lanes (%d) for DP on port %c\n",
6021                  intel_dig_port->max_lanes, port_name(port)))
6022                 return false;
6023
6024         intel_dp_set_source_rates(intel_dp);
6025
6026         intel_dp->reset_link_params = true;
6027         intel_dp->pps_pipe = INVALID_PIPE;
6028         intel_dp->active_pipe = INVALID_PIPE;
6029
6030         /* intel_dp vfuncs */
6031         if (INTEL_GEN(dev_priv) >= 9)
6032                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
6033         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6034                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6035         else if (HAS_PCH_SPLIT(dev_priv))
6036                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
6037         else
6038                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
6039
6040         if (INTEL_GEN(dev_priv) >= 9)
6041                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
6042         else
6043                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
6044
6045         if (HAS_DDI(dev_priv))
6046                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6047
6048         /* Preserve the current hw state. */
6049         intel_dp->DP = I915_READ(intel_dp->output_reg);
6050         intel_dp->attached_connector = intel_connector;
6051
6052         if (intel_dp_is_edp(dev_priv, port))
6053                 type = DRM_MODE_CONNECTOR_eDP;
6054         else
6055                 type = DRM_MODE_CONNECTOR_DisplayPort;
6056
6057         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6058                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6059
6060         /*
6061          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6062          * for DP the encoder type can be set by the caller to
6063          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6064          */
6065         if (type == DRM_MODE_CONNECTOR_eDP)
6066                 intel_encoder->type = INTEL_OUTPUT_EDP;
6067
6068         /* eDP only on port B and/or C on vlv/chv */
6069         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6070                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
6071                 return false;
6072
6073         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6074                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6075                         port_name(port));
6076
6077         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6078         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6079
6080         connector->interlace_allowed = true;
6081         connector->doublescan_allowed = 0;
6082
6083         intel_dp_init_connector_port_info(intel_dig_port);
6084
6085         intel_dp_aux_init(intel_dp);
6086
6087         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6088                           edp_panel_vdd_work);
6089
6090         intel_connector_attach_encoder(intel_connector, intel_encoder);
6091
6092         if (HAS_DDI(dev_priv))
6093                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6094         else
6095                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6096
6097         /* init MST on ports that can support it */
6098         if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
6099             (port == PORT_B || port == PORT_C || port == PORT_D))
6100                 intel_dp_mst_encoder_init(intel_dig_port,
6101                                           intel_connector->base.base.id);
6102
6103         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6104                 intel_dp_aux_fini(intel_dp);
6105                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6106                 goto fail;
6107         }
6108
6109         intel_dp_add_properties(intel_dp, connector);
6110
6111         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6112          * 0xd.  Failure to do so will result in spurious interrupts being
6113          * generated on the port when a cable is not attached.
6114          */
6115         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6116                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6117                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6118         }
6119
6120         return true;
6121
6122 fail:
6123         drm_connector_cleanup(connector);
6124
6125         return false;
6126 }
6127
6128 bool intel_dp_init(struct drm_i915_private *dev_priv,
6129                    i915_reg_t output_reg,
6130                    enum port port)
6131 {
6132         struct intel_digital_port *intel_dig_port;
6133         struct intel_encoder *intel_encoder;
6134         struct drm_encoder *encoder;
6135         struct intel_connector *intel_connector;
6136
6137         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6138         if (!intel_dig_port)
6139                 return false;
6140
6141         intel_connector = intel_connector_alloc();
6142         if (!intel_connector)
6143                 goto err_connector_alloc;
6144
6145         intel_encoder = &intel_dig_port->base;
6146         encoder = &intel_encoder->base;
6147
6148         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6149                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6150                              "DP %c", port_name(port)))
6151                 goto err_encoder_init;
6152
6153         intel_encoder->compute_config = intel_dp_compute_config;
6154         intel_encoder->disable = intel_disable_dp;
6155         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6156         intel_encoder->get_config = intel_dp_get_config;
6157         intel_encoder->suspend = intel_dp_encoder_suspend;
6158         if (IS_CHERRYVIEW(dev_priv)) {
6159                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6160                 intel_encoder->pre_enable = chv_pre_enable_dp;
6161                 intel_encoder->enable = vlv_enable_dp;
6162                 intel_encoder->post_disable = chv_post_disable_dp;
6163                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6164         } else if (IS_VALLEYVIEW(dev_priv)) {
6165                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6166                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6167                 intel_encoder->enable = vlv_enable_dp;
6168                 intel_encoder->post_disable = vlv_post_disable_dp;
6169         } else {
6170                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6171                 intel_encoder->enable = g4x_enable_dp;
6172                 if (INTEL_GEN(dev_priv) >= 5)
6173                         intel_encoder->post_disable = ilk_post_disable_dp;
6174         }
6175
6176         intel_dig_port->port = port;
6177         intel_dig_port->dp.output_reg = output_reg;
6178         intel_dig_port->max_lanes = 4;
6179
6180         intel_encoder->type = INTEL_OUTPUT_DP;
6181         intel_encoder->power_domain = intel_port_to_power_domain(port);
6182         if (IS_CHERRYVIEW(dev_priv)) {
6183                 if (port == PORT_D)
6184                         intel_encoder->crtc_mask = 1 << 2;
6185                 else
6186                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6187         } else {
6188                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6189         }
6190         intel_encoder->cloneable = 0;
6191         intel_encoder->port = port;
6192
6193         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6194         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6195
6196         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6197                 goto err_init_connector;
6198
6199         return true;
6200
6201 err_init_connector:
6202         drm_encoder_cleanup(encoder);
6203 err_encoder_init:
6204         kfree(intel_connector);
6205 err_connector_alloc:
6206         kfree(intel_dig_port);
6207         return false;
6208 }
6209
6210 void intel_dp_mst_suspend(struct drm_device *dev)
6211 {
6212         struct drm_i915_private *dev_priv = to_i915(dev);
6213         int i;
6214
6215         /* disable MST */
6216         for (i = 0; i < I915_MAX_PORTS; i++) {
6217                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6218
6219                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6220                         continue;
6221
6222                 if (intel_dig_port->dp.is_mst)
6223                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6224         }
6225 }
6226
6227 void intel_dp_mst_resume(struct drm_device *dev)
6228 {
6229         struct drm_i915_private *dev_priv = to_i915(dev);
6230         int i;
6231
6232         for (i = 0; i < I915_MAX_PORTS; i++) {
6233                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6234                 int ret;
6235
6236                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6237                         continue;
6238
6239                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6240                 if (ret)
6241                         intel_dp_check_mst_status(&intel_dig_port->dp);
6242         }
6243 }