drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_dmabuf.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct drm_device *dev,
 101                                   struct intel_framebuffer *ifb,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd,
 103                                   struct drm_i915_gem_object *obj);
 104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 108                                          struct intel_link_m_n *m_n,
 109                                          struct intel_link_m_n *m2_n2);
 110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 113 static void vlv_prepare_pll(struct intel_crtc *crtc,
 114                             const struct intel_crtc_state *pipe_config);
 115 static void chv_prepare_pll(struct intel_crtc *crtc,
 116                             const struct intel_crtc_state *pipe_config);
 117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 120         struct intel_crtc_state *crtc_state);
 121 static void skylake_pfit_enable(struct intel_crtc *crtc);
 122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 127 static int bxt_calc_cdclk(int max_pixclk);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                                   const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static int
 184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 185 {
 186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 187 }
 188
 189 static int
 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 191 {
 192         /* RAWCLK_FREQ_VLV register updated from power well code */
 193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 195 }
 196
 197 static int
 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 199 {
 200         uint32_t clkcfg;
 201
 202         /* hrawclock is 1/4 the FSB frequency */
 203         clkcfg = I915_READ(CLKCFG);
 204         switch (clkcfg & CLKCFG_FSB_MASK) {
 205         case CLKCFG_FSB_400:
 206                 return 100000;
 207         case CLKCFG_FSB_533:
 208                 return 133333;
 209         case CLKCFG_FSB_667:
 210                 return 166667;
 211         case CLKCFG_FSB_800:
 212                 return 200000;
 213         case CLKCFG_FSB_1067:
 214                 return 266667;
 215         case CLKCFG_FSB_1333:
 216                 return 333333;
 217         /* these two are just a guess; one of them might be right */
 218         case CLKCFG_FSB_1600:
 219         case CLKCFG_FSB_1600_ALT:
 220                 return 400000;
 221         default:
 222                 return 133333;
 223         }
 224 }
 225
 226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 227 {
 228         if (HAS_PCH_SPLIT(dev_priv))
 229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 234         else
 235                 return; /* no rawclk on other platforms, or no need to know it */
 236
 237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 238 }
 239
 240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 241 {
 242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 243                 return;
 244
 245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 246                                                       CCK_CZ_CLOCK_CONTROL);
 247
 248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 249 }
 250
 251 static inline u32 /* units of 100MHz */
 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 253                     const struct intel_crtc_state *pipe_config)
 254 {
 255         if (HAS_DDI(dev_priv))
 256                 return pipe_config->port_clock; /* SPLL */
 257         else if (IS_GEN5(dev_priv))
 258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 259         else
 260                 return 270000;
 261 }
 262
 263 static const struct intel_limit intel_limits_i8xx_dac = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 2 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_dvo = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 2, .max = 33 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 4, .p2_fast = 4 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i8xx_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 908000, .max = 1512000 },
 292         .n = { .min = 2, .max = 16 },
 293         .m = { .min = 96, .max = 140 },
 294         .m1 = { .min = 18, .max = 26 },
 295         .m2 = { .min = 6, .max = 16 },
 296         .p = { .min = 4, .max = 128 },
 297         .p1 = { .min = 1, .max = 6 },
 298         .p2 = { .dot_limit = 165000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_sdvo = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 200000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const struct intel_limit intel_limits_i9xx_lvds = {
 316         .dot = { .min = 20000, .max = 400000 },
 317         .vco = { .min = 1400000, .max = 2800000 },
 318         .n = { .min = 1, .max = 6 },
 319         .m = { .min = 70, .max = 120 },
 320         .m1 = { .min = 8, .max = 18 },
 321         .m2 = { .min = 3, .max = 7 },
 322         .p = { .min = 7, .max = 98 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 112000,
 325                 .p2_slow = 14, .p2_fast = 7 },
 326 };
 327
 328
 329 static const struct intel_limit intel_limits_g4x_sdvo = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 1750000, .max = 3500000},
 332         .n = { .min = 1, .max = 4 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 1, .max = 3},
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 10,
 340                 .p2_fast = 10
 341         },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_hdmi = {
 345         .dot = { .min = 22000, .max = 400000 },
 346         .vco = { .min = 1750000, .max = 3500000},
 347         .n = { .min = 1, .max = 4 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 16, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 5, .max = 80 },
 352         .p1 = { .min = 1, .max = 8},
 353         .p2 = { .dot_limit = 165000,
 354                 .p2_slow = 10, .p2_fast = 5 },
 355 };
 356
 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 358         .dot = { .min = 20000, .max = 115000 },
 359         .vco = { .min = 1750000, .max = 3500000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 104, .max = 138 },
 362         .m1 = { .min = 17, .max = 23 },
 363         .m2 = { .min = 5, .max = 11 },
 364         .p = { .min = 28, .max = 112 },
 365         .p1 = { .min = 2, .max = 8 },
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 14, .p2_fast = 14
 368         },
 369 };
 370
 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 372         .dot = { .min = 80000, .max = 224000 },
 373         .vco = { .min = 1750000, .max = 3500000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 104, .max = 138 },
 376         .m1 = { .min = 17, .max = 23 },
 377         .m2 = { .min = 5, .max = 11 },
 378         .p = { .min = 14, .max = 42 },
 379         .p1 = { .min = 2, .max = 6 },
 380         .p2 = { .dot_limit = 0,
 381                 .p2_slow = 7, .p2_fast = 7
 382         },
 383 };
 384
 385 static const struct intel_limit intel_limits_pineview_sdvo = {
 386         .dot = { .min = 20000, .max = 400000},
 387         .vco = { .min = 1700000, .max = 3500000 },
 388         /* Pineview's Ncounter is a ring counter */
 389         .n = { .min = 3, .max = 6 },
 390         .m = { .min = 2, .max = 256 },
 391         /* Pineview only has one combined m divider, which we treat as m2. */
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 5, .max = 80 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 200000,
 397                 .p2_slow = 10, .p2_fast = 5 },
 398 };
 399
 400 static const struct intel_limit intel_limits_pineview_lvds = {
 401         .dot = { .min = 20000, .max = 400000 },
 402         .vco = { .min = 1700000, .max = 3500000 },
 403         .n = { .min = 3, .max = 6 },
 404         .m = { .min = 2, .max = 256 },
 405         .m1 = { .min = 0, .max = 0 },
 406         .m2 = { .min = 0, .max = 254 },
 407         .p = { .min = 7, .max = 112 },
 408         .p1 = { .min = 1, .max = 8 },
 409         .p2 = { .dot_limit = 112000,
 410                 .p2_slow = 14, .p2_fast = 14 },
 411 };
 412
 413 /* Ironlake / Sandybridge
 414  *
 415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 416  * the range value for them is (actual_value - 2).
 417  */
 418 static const struct intel_limit intel_limits_ironlake_dac = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 5 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 5, .max = 80 },
 426         .p1 = { .min = 1, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 10, .p2_fast = 5 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 118 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 127 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 56 },
 452         .p1 = { .min = 2, .max = 8 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 /* LVDS 100mhz refclk limits. */
 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 2 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 28, .max = 112 },
 466         .p1 = { .min = 2, .max = 8 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 14, .p2_fast = 14 },
 469 };
 470
 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 472         .dot = { .min = 25000, .max = 350000 },
 473         .vco = { .min = 1760000, .max = 3510000 },
 474         .n = { .min = 1, .max = 3 },
 475         .m = { .min = 79, .max = 126 },
 476         .m1 = { .min = 12, .max = 22 },
 477         .m2 = { .min = 5, .max = 9 },
 478         .p = { .min = 14, .max = 42 },
 479         .p1 = { .min = 2, .max = 6 },
 480         .p2 = { .dot_limit = 225000,
 481                 .p2_slow = 7, .p2_fast = 7 },
 482 };
 483
 484 static const struct intel_limit intel_limits_vlv = {
 485          /*
 486           * These are the data rate limits (measured in fast clocks)
 487           * since those are the strictest limits we have. The fast
 488           * clock and actual rate limits are more relaxed, so checking
 489           * them would make no difference.
 490           */
 491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 492         .vco = { .min = 4000000, .max = 6000000 },
 493         .n = { .min = 1, .max = 7 },
 494         .m1 = { .min = 2, .max = 3 },
 495         .m2 = { .min = 11, .max = 156 },
 496         .p1 = { .min = 2, .max = 3 },
 497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 498 };
 499
 500 static const struct intel_limit intel_limits_chv = {
 501         /*
 502          * These are the data rate limits (measured in fast clocks)
 503          * since those are the strictest limits we have.  The fast
 504          * clock and actual rate limits are more relaxed, so checking
 505          * them would make no difference.
 506          */
 507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 508         .vco = { .min = 4800000, .max = 6480000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 514 };
 515
 516 static const struct intel_limit intel_limits_bxt = {
 517         /* FIXME: find real dot limits */
 518         .dot = { .min = 0, .max = INT_MAX },
 519         .vco = { .min = 4800000, .max = 6700000 },
 520         .n = { .min = 1, .max = 1 },
 521         .m1 = { .min = 2, .max = 2 },
 522         /* FIXME: find real m2 limits */
 523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 524         .p1 = { .min = 2, .max = 4 },
 525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 526 };
 527
 528 static bool
 529 needs_modeset(struct drm_crtc_state *state)
 530 {
 531         return drm_atomic_crtc_needs_modeset(state);
 532 }
 533
 534 /*
 535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 538  * The helpers' return value is the rate of the clock that is fed to the
 539  * display engine's pipe which can be the above fast dot clock rate or a
 540  * divided-down version of it.
 541  */
 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 544 {
 545         clock->m = clock->m2 + 2;
 546         clock->p = clock->p1 * clock->p2;
 547         if (WARN_ON(clock->n == 0 || clock->p == 0))
 548                 return 0;
 549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 551
 552         return clock->dot;
 553 }
 554
 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 556 {
 557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 558 }
 559
 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 561 {
 562         clock->m = i9xx_dpll_compute_m(clock);
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 565                 return 0;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568
 569         return clock->dot;
 570 }
 571
 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 573 {
 574         clock->m = clock->m1 * clock->m2;
 575         clock->p = clock->p1 * clock->p2;
 576         if (WARN_ON(clock->n == 0 || clock->p == 0))
 577                 return 0;
 578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 580
 581         return clock->dot / 5;
 582 }
 583
 584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 585 {
 586         clock->m = clock->m1 * clock->m2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 591                         clock->n << 22);
 592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 593
 594         return clock->dot / 5;
 595 }
 596
 597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 598 /**
 599  * Returns whether the given set of divisors are valid for a given refclk with
 600  * the given connectors.
 601  */
 602
 603 static bool intel_PLL_is_valid(struct drm_device *dev,
 604                                const struct intel_limit *limit,
 605                                const struct dpll *clock)
 606 {
 607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 608                 INTELPllInvalid("n out of range\n");
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 612                 INTELPllInvalid("m2 out of range\n");
 613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 614                 INTELPllInvalid("m1 out of range\n");
 615
 616         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 617             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 618                 if (clock->m1 <= clock->m2)
 619                         INTELPllInvalid("m1 <= m2\n");
 620
 621         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 622                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 623                         INTELPllInvalid("p out of range\n");
 624                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 625                         INTELPllInvalid("m out of range\n");
 626         }
 627
 628         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 629                 INTELPllInvalid("vco out of range\n");
 630         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 631          * connector, etc., rather than just a single range.
 632          */
 633         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 634                 INTELPllInvalid("dot out of range\n");
 635
 636         return true;
 637 }
 638
 639 static int
 640 i9xx_select_p2_div(const struct intel_limit *limit,
 641                    const struct intel_crtc_state *crtc_state,
 642                    int target)
 643 {
 644         struct drm_device *dev = crtc_state->base.crtc->dev;
 645
 646         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 647                 /*
 648                  * For LVDS just rely on its current settings for dual-channel.
 649                  * We haven't figured out how to reliably set up different
 650                  * single/dual channel state, if we even can.
 651                  */
 652                 if (intel_is_dual_link_lvds(dev))
 653                         return limit->p2.p2_fast;
 654                 else
 655                         return limit->p2.p2_slow;
 656         } else {
 657                 if (target < limit->p2.dot_limit)
 658                         return limit->p2.p2_slow;
 659                 else
 660                         return limit->p2.p2_fast;
 661         }
 662 }
 663
 664 /*
 665  * Returns a set of divisors for the desired target clock with the given
 666  * refclk, or FALSE.  The returned values represent the clock equation:
 667  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 668  *
 669  * Target and reference clocks are specified in kHz.
 670  *
 671  * If match_clock is provided, then best_clock P divider must match the P
 672  * divider from @match_clock used for LVDS downclocking.
 673  */
 674 static bool
 675 i9xx_find_best_dpll(const struct intel_limit *limit,
 676                     struct intel_crtc_state *crtc_state,
 677                     int target, int refclk, struct dpll *match_clock,
 678                     struct dpll *best_clock)
 679 {
 680         struct drm_device *dev = crtc_state->base.crtc->dev;
 681         struct dpll clock;
 682         int err = target;
 683
 684         memset(best_clock, 0, sizeof(*best_clock));
 685
 686         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 687
 688         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 689              clock.m1++) {
 690                 for (clock.m2 = limit->m2.min;
 691                      clock.m2 <= limit->m2.max; clock.m2++) {
 692                         if (clock.m2 >= clock.m1)
 693                                 break;
 694                         for (clock.n = limit->n.min;
 695                              clock.n <= limit->n.max; clock.n++) {
 696                                 for (clock.p1 = limit->p1.min;
 697                                         clock.p1 <= limit->p1.max; clock.p1++) {
 698                                         int this_err;
 699
 700                                         i9xx_calc_dpll_params(refclk, &clock);
 701                                         if (!intel_PLL_is_valid(dev, limit,
 702                                                                 &clock))
 703                                                 continue;
 704                                         if (match_clock &&
 705                                             clock.p != match_clock->p)
 706                                                 continue;
 707
 708                                         this_err = abs(clock.dot - target);
 709                                         if (this_err < err) {
 710                                                 *best_clock = clock;
 711                                                 err = this_err;
 712                                         }
 713                                 }
 714                         }
 715                 }
 716         }
 717
 718         return (err != target);
 719 }
 720
 721 /*
 722  * Returns a set of divisors for the desired target clock with the given
 723  * refclk, or FALSE.  The returned values represent the clock equation:
 724  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 725  *
 726  * Target and reference clocks are specified in kHz.
 727  *
 728  * If match_clock is provided, then best_clock P divider must match the P
 729  * divider from @match_clock used for LVDS downclocking.
 730  */
 731 static bool
 732 pnv_find_best_dpll(const struct intel_limit *limit,
 733                    struct intel_crtc_state *crtc_state,
 734                    int target, int refclk, struct dpll *match_clock,
 735                    struct dpll *best_clock)
 736 {
 737         struct drm_device *dev = crtc_state->base.crtc->dev;
 738         struct dpll clock;
 739         int err = target;
 740
 741         memset(best_clock, 0, sizeof(*best_clock));
 742
 743         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 744
 745         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 746              clock.m1++) {
 747                 for (clock.m2 = limit->m2.min;
 748                      clock.m2 <= limit->m2.max; clock.m2++) {
 749                         for (clock.n = limit->n.min;
 750                              clock.n <= limit->n.max; clock.n++) {
 751                                 for (clock.p1 = limit->p1.min;
 752                                         clock.p1 <= limit->p1.max; clock.p1++) {
 753                                         int this_err;
 754
 755                                         pnv_calc_dpll_params(refclk, &clock);
 756                                         if (!intel_PLL_is_valid(dev, limit,
 757                                                                 &clock))
 758                                                 continue;
 759                                         if (match_clock &&
 760                                             clock.p != match_clock->p)
 761                                                 continue;
 762
 763                                         this_err = abs(clock.dot - target);
 764                                         if (this_err < err) {
 765                                                 *best_clock = clock;
 766                                                 err = this_err;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772
 773         return (err != target);
 774 }
 775
 776 /*
 777  * Returns a set of divisors for the desired target clock with the given
 778  * refclk, or FALSE.  The returned values represent the clock equation:
 779  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 780  *
 781  * Target and reference clocks are specified in kHz.
 782  *
 783  * If match_clock is provided, then best_clock P divider must match the P
 784  * divider from @match_clock used for LVDS downclocking.
 785  */
 786 static bool
 787 g4x_find_best_dpll(const struct intel_limit *limit,
 788                    struct intel_crtc_state *crtc_state,
 789                    int target, int refclk, struct dpll *match_clock,
 790                    struct dpll *best_clock)
 791 {
 792         struct drm_device *dev = crtc_state->base.crtc->dev;
 793         struct dpll clock;
 794         int max_n;
 795         bool found = false;
 796         /* approximately equals target * 0.00585 */
 797         int err_most = (target >> 8) + (target >> 9);
 798
 799         memset(best_clock, 0, sizeof(*best_clock));
 800
 801         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 802
 803         max_n = limit->n.max;
 804         /* based on hardware requirement, prefer smaller n to precision */
 805         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 806                 /* based on hardware requirement, prefere larger m1,m2 */
 807                 for (clock.m1 = limit->m1.max;
 808                      clock.m1 >= limit->m1.min; clock.m1--) {
 809                         for (clock.m2 = limit->m2.max;
 810                              clock.m2 >= limit->m2.min; clock.m2--) {
 811                                 for (clock.p1 = limit->p1.max;
 812                                      clock.p1 >= limit->p1.min; clock.p1--) {
 813                                         int this_err;
 814
 815                                         i9xx_calc_dpll_params(refclk, &clock);
 816                                         if (!intel_PLL_is_valid(dev, limit,
 817                                                                 &clock))
 818                                                 continue;
 819
 820                                         this_err = abs(clock.dot - target);
 821                                         if (this_err < err_most) {
 822                                                 *best_clock = clock;
 823                                                 err_most = this_err;
 824                                                 max_n = clock.n;
 825                                                 found = true;
 826                                         }
 827                                 }
 828                         }
 829                 }
 830         }
 831         return found;
 832 }
 833
 834 /*
 835  * Check if the calculated PLL configuration is more optimal compared to the
 836  * best configuration and error found so far. Return the calculated error.
 837  */
 838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 839                                const struct dpll *calculated_clock,
 840                                const struct dpll *best_clock,
 841                                unsigned int best_error_ppm,
 842                                unsigned int *error_ppm)
 843 {
 844         /*
 845          * For CHV ignore the error and consider only the P value.
 846          * Prefer a bigger P value based on HW requirements.
 847          */
 848         if (IS_CHERRYVIEW(dev)) {
 849                 *error_ppm = 0;
 850
 851                 return calculated_clock->p > best_clock->p;
 852         }
 853
 854         if (WARN_ON_ONCE(!target_freq))
 855                 return false;
 856
 857         *error_ppm = div_u64(1000000ULL *
 858                                 abs(target_freq - calculated_clock->dot),
 859                              target_freq);
 860         /*
 861          * Prefer a better P value over a better (smaller) error if the error
 862          * is small. Ensure this preference for future configurations too by
 863          * setting the error to 0.
 864          */
 865         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 866                 *error_ppm = 0;
 867
 868                 return true;
 869         }
 870
 871         return *error_ppm + 10 < best_error_ppm;
 872 }
 873
 874 /*
 875  * Returns a set of divisors for the desired target clock with the given
 876  * refclk, or FALSE.  The returned values represent the clock equation:
 877  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 878  */
 879 static bool
 880 vlv_find_best_dpll(const struct intel_limit *limit,
 881                    struct intel_crtc_state *crtc_state,
 882                    int target, int refclk, struct dpll *match_clock,
 883                    struct dpll *best_clock)
 884 {
 885         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 886         struct drm_device *dev = crtc->base.dev;
 887         struct dpll clock;
 888         unsigned int bestppm = 1000000;
 889         /* min update 19.2 MHz */
 890         int max_n = min(limit->n.max, refclk / 19200);
 891         bool found = false;
 892
 893         target *= 5; /* fast clock */
 894
 895         memset(best_clock, 0, sizeof(*best_clock));
 896
 897         /* based on hardware requirement, prefer smaller n to precision */
 898         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 899                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 900                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 901                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 902                                 clock.p = clock.p1 * clock.p2;
 903                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 904                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 905                                         unsigned int ppm;
 906
 907                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 908                                                                      refclk * clock.m1);
 909
 910                                         vlv_calc_dpll_params(refclk, &clock);
 911
 912                                         if (!intel_PLL_is_valid(dev, limit,
 913                                                                 &clock))
 914                                                 continue;
 915
 916                                         if (!vlv_PLL_is_optimal(dev, target,
 917                                                                 &clock,
 918                                                                 best_clock,
 919                                                                 bestppm, &ppm))
 920                                                 continue;
 921
 922                                         *best_clock = clock;
 923                                         bestppm = ppm;
 924                                         found = true;
 925                                 }
 926                         }
 927                 }
 928         }
 929
 930         return found;
 931 }
 932
 933 /*
 934  * Returns a set of divisors for the desired target clock with the given
 935  * refclk, or FALSE.  The returned values represent the clock equation:
 936  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 937  */
 938 static bool
 939 chv_find_best_dpll(const struct intel_limit *limit,
 940                    struct intel_crtc_state *crtc_state,
 941                    int target, int refclk, struct dpll *match_clock,
 942                    struct dpll *best_clock)
 943 {
 944         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 945         struct drm_device *dev = crtc->base.dev;
 946         unsigned int best_error_ppm;
 947         struct dpll clock;
 948         uint64_t m2;
 949         int found = false;
 950
 951         memset(best_clock, 0, sizeof(*best_clock));
 952         best_error_ppm = 1000000;
 953
 954         /*
 955          * Based on hardware doc, the n always set to 1, and m1 always
 956          * set to 2.  If requires to support 200Mhz refclk, we need to
 957          * revisit this because n may not 1 anymore.
 958          */
 959         clock.n = 1, clock.m1 = 2;
 960         target *= 5;    /* fast clock */
 961
 962         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 963                 for (clock.p2 = limit->p2.p2_fast;
 964                                 clock.p2 >= limit->p2.p2_slow;
 965                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 966                         unsigned int error_ppm;
 967
 968                         clock.p = clock.p1 * clock.p2;
 969
 970                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 971                                         clock.n) << 22, refclk * clock.m1);
 972
 973                         if (m2 > INT_MAX/clock.m1)
 974                                 continue;
 975
 976                         clock.m2 = m2;
 977
 978                         chv_calc_dpll_params(refclk, &clock);
 979
 980                         if (!intel_PLL_is_valid(dev, limit, &clock))
 981                                 continue;
 982
 983                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 984                                                 best_error_ppm, &error_ppm))
 985                                 continue;
 986
 987                         *best_clock = clock;
 988                         best_error_ppm = error_ppm;
 989                         found = true;
 990                 }
 991         }
 992
 993         return found;
 994 }
 995
 996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 997                         struct dpll *best_clock)
 998 {
 999         int refclk = 100000;
1000         const struct intel_limit *limit = &intel_limits_bxt;
1001
1002         return chv_find_best_dpll(limit, crtc_state,
1003                                   target_clock, refclk, NULL, best_clock);
1004 }
1005
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1007 {
1008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
1010         /* Be paranoid as we can arrive here with only partial
1011          * state retrieved from the hardware during setup.
1012          *
1013          * We can ditch the adjusted_mode.crtc_clock check as soon
1014          * as Haswell has gained clock readout/fastboot support.
1015          *
1016          * We can ditch the crtc->primary->fb check as soon as we can
1017          * properly reconstruct framebuffers.
1018          *
1019          * FIXME: The intel_crtc->active here should be switched to
1020          * crtc->state->active once we have proper CRTC states wired up
1021          * for atomic.
1022          */
1023         return intel_crtc->active && crtc->primary->state->fb &&
1024                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1025 }
1026
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028                                              enum pipe pipe)
1029 {
1030         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1032
1033         return intel_crtc->config->cpu_transcoder;
1034 }
1035
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1037 {
1038         struct drm_i915_private *dev_priv = to_i915(dev);
1039         i915_reg_t reg = PIPEDSL(pipe);
1040         u32 line1, line2;
1041         u32 line_mask;
1042
1043         if (IS_GEN2(dev))
1044                 line_mask = DSL_LINEMASK_GEN2;
1045         else
1046                 line_mask = DSL_LINEMASK_GEN3;
1047
1048         line1 = I915_READ(reg) & line_mask;
1049         msleep(5);
1050         line2 = I915_READ(reg) & line_mask;
1051
1052         return line1 == line2;
1053 }
1054
1055 /*
1056  * intel_wait_for_pipe_off - wait for pipe to turn off
1057  * @crtc: crtc whose pipe to wait for
1058  *
1059  * After disabling a pipe, we can't wait for vblank in the usual way,
1060  * spinning on the vblank interrupt status bit, since we won't actually
1061  * see an interrupt when the pipe is disabled.
1062  *
1063  * On Gen4 and above:
1064  *   wait for the pipe register state bit to turn off
1065  *
1066  * Otherwise:
1067  *   wait for the display line value to settle (it usually
1068  *   ends up stopping at the start of the next frame).
1069  *
1070  */
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1072 {
1073         struct drm_device *dev = crtc->base.dev;
1074         struct drm_i915_private *dev_priv = to_i915(dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077
1078         if (INTEL_INFO(dev)->gen >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191                            enum pipe pipe)
1192 {
1193         struct drm_device *dev = &dev_priv->drm;
1194         i915_reg_t pp_reg;
1195         u32 val;
1196         enum pipe panel_pipe = PIPE_A;
1197         bool locked = true;
1198
1199         if (WARN_ON(HAS_DDI(dev)))
1200                 return;
1201
1202         if (HAS_PCH_SPLIT(dev)) {
1203                 u32 port_sel;
1204
1205                 pp_reg = PP_CONTROL(0);
1206                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1207
1208                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210                         panel_pipe = PIPE_B;
1211                 /* XXX: else fix for eDP */
1212         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213                 /* presumably write lock depends on pipe, not port select */
1214                 pp_reg = PP_CONTROL(pipe);
1215                 panel_pipe = pipe;
1216         } else {
1217                 pp_reg = PP_CONTROL(0);
1218                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219                         panel_pipe = PIPE_B;
1220         }
1221
1222         val = I915_READ(pp_reg);
1223         if (!(val & PANEL_POWER_ON) ||
1224             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1225                 locked = false;
1226
1227         I915_STATE_WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233                           enum pipe pipe, bool state)
1234 {
1235         struct drm_device *dev = &dev_priv->drm;
1236         bool cur_state;
1237
1238         if (IS_845G(dev) || IS_I865G(dev))
1239                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1240         else
1241                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1242
1243         I915_STATE_WARN(cur_state != state,
1244              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245                         pipe_name(pipe), onoff(state), onoff(cur_state));
1246 }
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251                  enum pipe pipe, bool state)
1252 {
1253         bool cur_state;
1254         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1255                                                                       pipe);
1256         enum intel_display_power_domain power_domain;
1257
1258         /* if we need the pipe quirk it must be always on */
1259         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1261                 state = true;
1262
1263         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266                 cur_state = !!(val & PIPECONF_ENABLE);
1267
1268                 intel_display_power_put(dev_priv, power_domain);
1269         } else {
1270                 cur_state = false;
1271         }
1272
1273         I915_STATE_WARN(cur_state != state,
1274              "pipe %c assertion failure (expected %s, current %s)\n",
1275                         pipe_name(pipe), onoff(state), onoff(cur_state));
1276 }
1277
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279                          enum plane plane, bool state)
1280 {
1281         u32 val;
1282         bool cur_state;
1283
1284         val = I915_READ(DSPCNTR(plane));
1285         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286         I915_STATE_WARN(cur_state != state,
1287              "plane %c assertion failure (expected %s, current %s)\n",
1288                         plane_name(plane), onoff(state), onoff(cur_state));
1289 }
1290
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1295                                    enum pipe pipe)
1296 {
1297         struct drm_device *dev = &dev_priv->drm;
1298         int i;
1299
1300         /* Primary planes are fixed to pipes on gen4+ */
1301         if (INTEL_INFO(dev)->gen >= 4) {
1302                 u32 val = I915_READ(DSPCNTR(pipe));
1303                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304                      "plane %c assertion failure, should be disabled but not\n",
1305                      plane_name(pipe));
1306                 return;
1307         }
1308
1309         /* Need to check both planes against the pipe */
1310         for_each_pipe(dev_priv, i) {
1311                 u32 val = I915_READ(DSPCNTR(i));
1312                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313                         DISPPLANE_SEL_PIPE_SHIFT;
1314                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316                      plane_name(i), pipe_name(pipe));
1317         }
1318 }
1319
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1321                                     enum pipe pipe)
1322 {
1323         struct drm_device *dev = &dev_priv->drm;
1324         int sprite;
1325
1326         if (INTEL_INFO(dev)->gen >= 9) {
1327                 for_each_sprite(dev_priv, pipe, sprite) {
1328                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331                              sprite, pipe_name(pipe));
1332                 }
1333         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334                 for_each_sprite(dev_priv, pipe, sprite) {
1335                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1336                         I915_STATE_WARN(val & SP_ENABLE,
1337                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338                              sprite_name(pipe, sprite), pipe_name(pipe));
1339                 }
1340         } else if (INTEL_INFO(dev)->gen >= 7) {
1341                 u32 val = I915_READ(SPRCTL(pipe));
1342                 I915_STATE_WARN(val & SPRITE_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         } else if (INTEL_INFO(dev)->gen >= 5) {
1346                 u32 val = I915_READ(DVSCNTR(pipe));
1347                 I915_STATE_WARN(val & DVS_ENABLE,
1348                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349                      plane_name(pipe), pipe_name(pipe));
1350         }
1351 }
1352
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1354 {
1355         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356                 drm_crtc_vblank_put(crtc);
1357 }
1358
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1360                                     enum pipe pipe)
1361 {
1362         u32 val;
1363         bool enabled;
1364
1365         val = I915_READ(PCH_TRANSCONF(pipe));
1366         enabled = !!(val & TRANS_ENABLE);
1367         I915_STATE_WARN(enabled,
1368              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369              pipe_name(pipe));
1370 }
1371
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373                             enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375         if ((val & DP_PORT_EN) == 0)
1376                 return false;
1377
1378         if (HAS_PCH_CPT(dev_priv)) {
1379                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381                         return false;
1382         } else if (IS_CHERRYVIEW(dev_priv)) {
1383                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384                         return false;
1385         } else {
1386                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387                         return false;
1388         }
1389         return true;
1390 }
1391
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393                               enum pipe pipe, u32 val)
1394 {
1395         if ((val & SDVO_ENABLE) == 0)
1396                 return false;
1397
1398         if (HAS_PCH_CPT(dev_priv)) {
1399                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1400                         return false;
1401         } else if (IS_CHERRYVIEW(dev_priv)) {
1402                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403                         return false;
1404         } else {
1405                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406                         return false;
1407         }
1408         return true;
1409 }
1410
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412                               enum pipe pipe, u32 val)
1413 {
1414         if ((val & LVDS_PORT_EN) == 0)
1415                 return false;
1416
1417         if (HAS_PCH_CPT(dev_priv)) {
1418                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419                         return false;
1420         } else {
1421                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422                         return false;
1423         }
1424         return true;
1425 }
1426
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428                               enum pipe pipe, u32 val)
1429 {
1430         if ((val & ADPA_DAC_ENABLE) == 0)
1431                 return false;
1432         if (HAS_PCH_CPT(dev_priv)) {
1433                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434                         return false;
1435         } else {
1436                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437                         return false;
1438         }
1439         return true;
1440 }
1441
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443                                    enum pipe pipe, i915_reg_t reg,
1444                                    u32 port_sel)
1445 {
1446         u32 val = I915_READ(reg);
1447         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449              i915_mmio_reg_offset(reg), pipe_name(pipe));
1450
1451         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452              && (val & DP_PIPEB_SELECT),
1453              "IBX PCH dp port still using transcoder B\n");
1454 }
1455
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457                                      enum pipe pipe, i915_reg_t reg)
1458 {
1459         u32 val = I915_READ(reg);
1460         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462              i915_mmio_reg_offset(reg), pipe_name(pipe));
1463
1464         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465              && (val & SDVO_PIPE_B_SELECT),
1466              "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470                                       enum pipe pipe)
1471 {
1472         u32 val;
1473
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478         val = I915_READ(PCH_ADPA);
1479         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480              "PCH VGA enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482
1483         val = I915_READ(PCH_LVDS);
1484         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486              pipe_name(pipe));
1487
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494                             const struct intel_crtc_state *pipe_config)
1495 {
1496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497         enum pipe pipe = crtc->pipe;
1498
1499         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500         POSTING_READ(DPLL(pipe));
1501         udelay(150);
1502
1503         if (intel_wait_for_register(dev_priv,
1504                                     DPLL(pipe),
1505                                     DPLL_LOCK_VLV,
1506                                     DPLL_LOCK_VLV,
1507                                     1))
1508                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1509 }
1510
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512                            const struct intel_crtc_state *pipe_config)
1513 {
1514         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515         enum pipe pipe = crtc->pipe;
1516
1517         assert_pipe_disabled(dev_priv, pipe);
1518
1519         /* PLL is protected by panel, make sure we can write it */
1520         assert_panel_unlocked(dev_priv, pipe);
1521
1522         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523                 _vlv_enable_pll(crtc, pipe_config);
1524
1525         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526         POSTING_READ(DPLL_MD(pipe));
1527 }
1528
1529
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531                             const struct intel_crtc_state *pipe_config)
1532 {
1533         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534         enum pipe pipe = crtc->pipe;
1535         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1536         u32 tmp;
1537
1538         mutex_lock(&dev_priv->sb_lock);
1539
1540         /* Enable back the 10bit clock to display controller */
1541         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542         tmp |= DPIO_DCLKP_EN;
1543         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1544
1545         mutex_unlock(&dev_priv->sb_lock);
1546
1547         /*
1548          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549          */
1550         udelay(1);
1551
1552         /* Enable PLL */
1553         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1554
1555         /* Check PLL is locked */
1556         if (intel_wait_for_register(dev_priv,
1557                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1558                                     1))
1559                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1560 }
1561
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563                            const struct intel_crtc_state *pipe_config)
1564 {
1565         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566         enum pipe pipe = crtc->pipe;
1567
1568         assert_pipe_disabled(dev_priv, pipe);
1569
1570         /* PLL is protected by panel, make sure we can write it */
1571         assert_panel_unlocked(dev_priv, pipe);
1572
1573         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574                 _chv_enable_pll(crtc, pipe_config);
1575
1576         if (pipe != PIPE_A) {
1577                 /*
1578                  * WaPixelRepeatModeFixForC0:chv
1579                  *
1580                  * DPLLCMD is AWOL. Use chicken bits to propagate
1581                  * the value from DPLLBMD to either pipe B or C.
1582                  */
1583                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585                 I915_WRITE(CBR4_VLV, 0);
1586                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1587
1588                 /*
1589                  * DPLLB VGA mode also seems to cause problems.
1590                  * We should always have it disabled.
1591                  */
1592                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1593         } else {
1594                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595                 POSTING_READ(DPLL_MD(pipe));
1596         }
1597 }
1598
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1600 {
1601         struct intel_crtc *crtc;
1602         int count = 0;
1603
1604         for_each_intel_crtc(dev, crtc) {
1605                 count += crtc->base.state->active &&
1606                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1607         }
1608
1609         return count;
1610 }
1611
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614         struct drm_device *dev = crtc->base.dev;
1615         struct drm_i915_private *dev_priv = to_i915(dev);
1616         i915_reg_t reg = DPLL(crtc->pipe);
1617         u32 dpll = crtc->config->dpll_hw_state.dpll;
1618
1619         assert_pipe_disabled(dev_priv, crtc->pipe);
1620
1621         /* PLL is protected by panel, make sure we can write it */
1622         if (IS_MOBILE(dev) && !IS_I830(dev))
1623                 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625         /* Enable DVO 2x clock on both PLLs if necessary */
1626         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1627                 /*
1628                  * It appears to be important that we don't enable this
1629                  * for the current pipe before otherwise configuring the
1630                  * PLL. No idea how this should be handled if multiple
1631                  * DVO outputs are enabled simultaneosly.
1632                  */
1633                 dpll |= DPLL_DVO_2X_MODE;
1634                 I915_WRITE(DPLL(!crtc->pipe),
1635                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1636         }
1637
1638         /*
1639          * Apparently we need to have VGA mode enabled prior to changing
1640          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641          * dividers, even though the register value does change.
1642          */
1643         I915_WRITE(reg, 0);
1644
1645         I915_WRITE(reg, dpll);
1646
1647         /* Wait for the clocks to stabilize. */
1648         POSTING_READ(reg);
1649         udelay(150);
1650
1651         if (INTEL_INFO(dev)->gen >= 4) {
1652                 I915_WRITE(DPLL_MD(crtc->pipe),
1653                            crtc->config->dpll_hw_state.dpll_md);
1654         } else {
1655                 /* The pixel multiplier can only be updated once the
1656                  * DPLL is enabled and the clocks are stable.
1657                  *
1658                  * So write it again.
1659                  */
1660                 I915_WRITE(reg, dpll);
1661         }
1662
1663         /* We do this three times for luck */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667         I915_WRITE(reg, dpll);
1668         POSTING_READ(reg);
1669         udelay(150); /* wait for warmup */
1670         I915_WRITE(reg, dpll);
1671         POSTING_READ(reg);
1672         udelay(150); /* wait for warmup */
1673 }
1674
1675 /**
1676  * i9xx_disable_pll - disable a PLL
1677  * @dev_priv: i915 private structure
1678  * @pipe: pipe PLL to disable
1679  *
1680  * Disable the PLL for @pipe, making sure the pipe is off first.
1681  *
1682  * Note!  This is for pre-ILK only.
1683  */
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1685 {
1686         struct drm_device *dev = crtc->base.dev;
1687         struct drm_i915_private *dev_priv = to_i915(dev);
1688         enum pipe pipe = crtc->pipe;
1689
1690         /* Disable DVO 2x clock on both PLLs if necessary */
1691         if (IS_I830(dev) &&
1692             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693             !intel_num_dvo_pipes(dev)) {
1694                 I915_WRITE(DPLL(PIPE_B),
1695                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696                 I915_WRITE(DPLL(PIPE_A),
1697                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1698         }
1699
1700         /* Don't disable pipe or pipe PLLs if needed */
1701         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1703                 return;
1704
1705         /* Make sure the pipe isn't still relying on us */
1706         assert_pipe_disabled(dev_priv, pipe);
1707
1708         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709         POSTING_READ(DPLL(pipe));
1710 }
1711
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         u32 val;
1715
1716         /* Make sure the pipe isn't still relying on us */
1717         assert_pipe_disabled(dev_priv, pipe);
1718
1719         val = DPLL_INTEGRATED_REF_CLK_VLV |
1720                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1721         if (pipe != PIPE_A)
1722                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1731         u32 val;
1732
1733         /* Make sure the pipe isn't still relying on us */
1734         assert_pipe_disabled(dev_priv, pipe);
1735
1736         val = DPLL_SSC_REF_CLK_CHV |
1737                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1738         if (pipe != PIPE_A)
1739                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1740
1741         I915_WRITE(DPLL(pipe), val);
1742         POSTING_READ(DPLL(pipe));
1743
1744         mutex_lock(&dev_priv->sb_lock);
1745
1746         /* Disable 10bit clock to display controller */
1747         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748         val &= ~DPIO_DCLKP_EN;
1749         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1750
1751         mutex_unlock(&dev_priv->sb_lock);
1752 }
1753
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755                          struct intel_digital_port *dport,
1756                          unsigned int expected_mask)
1757 {
1758         u32 port_mask;
1759         i915_reg_t dpll_reg;
1760
1761         switch (dport->port) {
1762         case PORT_B:
1763                 port_mask = DPLL_PORTB_READY_MASK;
1764                 dpll_reg = DPLL(0);
1765                 break;
1766         case PORT_C:
1767                 port_mask = DPLL_PORTC_READY_MASK;
1768                 dpll_reg = DPLL(0);
1769                 expected_mask <<= 4;
1770                 break;
1771         case PORT_D:
1772                 port_mask = DPLL_PORTD_READY_MASK;
1773                 dpll_reg = DPIO_PHY_STATUS;
1774                 break;
1775         default:
1776                 BUG();
1777         }
1778
1779         if (intel_wait_for_register(dev_priv,
1780                                     dpll_reg, port_mask, expected_mask,
1781                                     1000))
1782                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1784 }
1785
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1787                                            enum pipe pipe)
1788 {
1789         struct drm_device *dev = &dev_priv->drm;
1790         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792         i915_reg_t reg;
1793         uint32_t val, pipeconf_val;
1794
1795         /* Make sure PCH DPLL is enabled */
1796         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1797
1798         /* FDI must be feeding us bits for PCH ports */
1799         assert_fdi_tx_enabled(dev_priv, pipe);
1800         assert_fdi_rx_enabled(dev_priv, pipe);
1801
1802         if (HAS_PCH_CPT(dev)) {
1803                 /* Workaround: Set the timing override bit before enabling the
1804                  * pch transcoder. */
1805                 reg = TRANS_CHICKEN2(pipe);
1806                 val = I915_READ(reg);
1807                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808                 I915_WRITE(reg, val);
1809         }
1810
1811         reg = PCH_TRANSCONF(pipe);
1812         val = I915_READ(reg);
1813         pipeconf_val = I915_READ(PIPECONF(pipe));
1814
1815         if (HAS_PCH_IBX(dev_priv)) {
1816                 /*
1817                  * Make the BPC in transcoder be consistent with
1818                  * that in pipeconf reg. For HDMI we must use 8bpc
1819                  * here for both 8bpc and 12bpc.
1820                  */
1821                 val &= ~PIPECONF_BPC_MASK;
1822                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823                         val |= PIPECONF_8BPC;
1824                 else
1825                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1826         }
1827
1828         val &= ~TRANS_INTERLACE_MASK;
1829         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830                 if (HAS_PCH_IBX(dev_priv) &&
1831                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832                         val |= TRANS_LEGACY_INTERLACED_ILK;
1833                 else
1834                         val |= TRANS_INTERLACED;
1835         else
1836                 val |= TRANS_PROGRESSIVE;
1837
1838         I915_WRITE(reg, val | TRANS_ENABLE);
1839         if (intel_wait_for_register(dev_priv,
1840                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1841                                     100))
1842                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1843 }
1844
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846                                       enum transcoder cpu_transcoder)
1847 {
1848         u32 val, pipeconf_val;
1849
1850         /* FDI must be feeding us bits for PCH ports */
1851         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1853
1854         /* Workaround: set timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858
1859         val = TRANS_ENABLE;
1860         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1861
1862         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863             PIPECONF_INTERLACED_ILK)
1864                 val |= TRANS_INTERLACED;
1865         else
1866                 val |= TRANS_PROGRESSIVE;
1867
1868         I915_WRITE(LPT_TRANSCONF, val);
1869         if (intel_wait_for_register(dev_priv,
1870                                     LPT_TRANSCONF,
1871                                     TRANS_STATE_ENABLE,
1872                                     TRANS_STATE_ENABLE,
1873                                     100))
1874                 DRM_ERROR("Failed to enable PCH transcoder\n");
1875 }
1876
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1878                                             enum pipe pipe)
1879 {
1880         struct drm_device *dev = &dev_priv->drm;
1881         i915_reg_t reg;
1882         uint32_t val;
1883
1884         /* FDI relies on the transcoder */
1885         assert_fdi_tx_disabled(dev_priv, pipe);
1886         assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888         /* Ports must be off as well */
1889         assert_pch_ports_disabled(dev_priv, pipe);
1890
1891         reg = PCH_TRANSCONF(pipe);
1892         val = I915_READ(reg);
1893         val &= ~TRANS_ENABLE;
1894         I915_WRITE(reg, val);
1895         /* wait for PCH transcoder off, transcoder state */
1896         if (intel_wait_for_register(dev_priv,
1897                                     reg, TRANS_STATE_ENABLE, 0,
1898                                     50))
1899                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901         if (HAS_PCH_CPT(dev)) {
1902                 /* Workaround: Clear the timing override chicken bit again. */
1903                 reg = TRANS_CHICKEN2(pipe);
1904                 val = I915_READ(reg);
1905                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906                 I915_WRITE(reg, val);
1907         }
1908 }
1909
1910 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912         u32 val;
1913
1914         val = I915_READ(LPT_TRANSCONF);
1915         val &= ~TRANS_ENABLE;
1916         I915_WRITE(LPT_TRANSCONF, val);
1917         /* wait for PCH transcoder off, transcoder state */
1918         if (intel_wait_for_register(dev_priv,
1919                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920                                     50))
1921                 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923         /* Workaround: clear timing override bit. */
1924         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 /**
1930  * intel_enable_pipe - enable a pipe, asserting requirements
1931  * @crtc: crtc responsible for the pipe
1932  *
1933  * Enable @crtc's pipe, making sure that various hardware specific requirements
1934  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935  */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938         struct drm_device *dev = crtc->base.dev;
1939         struct drm_i915_private *dev_priv = to_i915(dev);
1940         enum pipe pipe = crtc->pipe;
1941         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942         enum pipe pch_transcoder;
1943         i915_reg_t reg;
1944         u32 val;
1945
1946         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
1948         assert_planes_disabled(dev_priv, pipe);
1949         assert_cursor_disabled(dev_priv, pipe);
1950         assert_sprites_disabled(dev_priv, pipe);
1951
1952         if (HAS_PCH_LPT(dev_priv))
1953                 pch_transcoder = TRANSCODER_A;
1954         else
1955                 pch_transcoder = pipe;
1956
1957         /*
1958          * A pipe without a PLL won't actually be able to drive bits from
1959          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1960          * need the check.
1961          */
1962         if (HAS_GMCH_DISPLAY(dev_priv)) {
1963                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964                         assert_dsi_pll_enabled(dev_priv);
1965                 else
1966                         assert_pll_enabled(dev_priv, pipe);
1967         } else {
1968                 if (crtc->config->has_pch_encoder) {
1969                         /* if driving the PCH, we need FDI enabled */
1970                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971                         assert_fdi_tx_pll_enabled(dev_priv,
1972                                                   (enum pipe) cpu_transcoder);
1973                 }
1974                 /* FIXME: assert CPU port conditions for SNB+ */
1975         }
1976
1977         reg = PIPECONF(cpu_transcoder);
1978         val = I915_READ(reg);
1979         if (val & PIPECONF_ENABLE) {
1980                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982                 return;
1983         }
1984
1985         I915_WRITE(reg, val | PIPECONF_ENABLE);
1986         POSTING_READ(reg);
1987
1988         /*
1989          * Until the pipe starts DSL will read as 0, which would cause
1990          * an apparent vblank timestamp jump, which messes up also the
1991          * frame count when it's derived from the timestamps. So let's
1992          * wait for the pipe to start properly before we call
1993          * drm_crtc_vblank_on()
1994          */
1995         if (dev->max_vblank_count == 0 &&
1996             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999
2000 /**
2001  * intel_disable_pipe - disable a pipe, asserting requirements
2002  * @crtc: crtc whose pipes is to be disabled
2003  *
2004  * Disable the pipe of @crtc, making sure that various hardware
2005  * specific requirements are met, if applicable, e.g. plane
2006  * disabled, panel fitter off, etc.
2007  *
2008  * Will wait until the pipe has shut down before returning.
2009  */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014         enum pipe pipe = crtc->pipe;
2015         i915_reg_t reg;
2016         u32 val;
2017
2018         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
2020         /*
2021          * Make sure planes won't keep trying to pump pixels to us,
2022          * or we might hang the display.
2023          */
2024         assert_planes_disabled(dev_priv, pipe);
2025         assert_cursor_disabled(dev_priv, pipe);
2026         assert_sprites_disabled(dev_priv, pipe);
2027
2028         reg = PIPECONF(cpu_transcoder);
2029         val = I915_READ(reg);
2030         if ((val & PIPECONF_ENABLE) == 0)
2031                 return;
2032
2033         /*
2034          * Double wide has implications for planes
2035          * so best keep it disabled when not needed.
2036          */
2037         if (crtc->config->double_wide)
2038                 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040         /* Don't disable pipe or pipe PLLs if needed */
2041         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043                 val &= ~PIPECONF_ENABLE;
2044
2045         I915_WRITE(reg, val);
2046         if ((val & PIPECONF_ENABLE) == 0)
2047                 intel_wait_for_pipe_off(crtc);
2048 }
2049
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052         return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056                                            uint64_t fb_modifier, unsigned int cpp)
2057 {
2058         switch (fb_modifier) {
2059         case DRM_FORMAT_MOD_NONE:
2060                 return cpp;
2061         case I915_FORMAT_MOD_X_TILED:
2062                 if (IS_GEN2(dev_priv))
2063                         return 128;
2064                 else
2065                         return 512;
2066         case I915_FORMAT_MOD_Y_TILED:
2067                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068                         return 128;
2069                 else
2070                         return 512;
2071         case I915_FORMAT_MOD_Yf_TILED:
2072                 switch (cpp) {
2073                 case 1:
2074                         return 64;
2075                 case 2:
2076                 case 4:
2077                         return 128;
2078                 case 8:
2079                 case 16:
2080                         return 256;
2081                 default:
2082                         MISSING_CASE(cpp);
2083                         return cpp;
2084                 }
2085                 break;
2086         default:
2087                 MISSING_CASE(fb_modifier);
2088                 return cpp;
2089         }
2090 }
2091
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093                                uint64_t fb_modifier, unsigned int cpp)
2094 {
2095         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096                 return 1;
2097         else
2098                 return intel_tile_size(dev_priv) /
2099                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104                             unsigned int *tile_width,
2105                             unsigned int *tile_height,
2106                             uint64_t fb_modifier,
2107                             unsigned int cpp)
2108 {
2109         unsigned int tile_width_bytes =
2110                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112         *tile_width = tile_width_bytes / cpp;
2113         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118                       uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123         return ALIGN(height, tile_height);
2124 }
2125
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128         unsigned int size = 0;
2129         int i;
2130
2131         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134         return size;
2135 }
2136
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139                         const struct drm_framebuffer *fb,
2140                         unsigned int rotation)
2141 {
2142         if (drm_rotation_90_or_270(rotation)) {
2143                 *view = i915_ggtt_view_rotated;
2144                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145         } else {
2146                 *view = i915_ggtt_view_normal;
2147         }
2148 }
2149
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152         if (INTEL_INFO(dev_priv)->gen >= 9)
2153                 return 256 * 1024;
2154         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156                 return 128 * 1024;
2157         else if (INTEL_INFO(dev_priv)->gen >= 4)
2158                 return 4 * 1024;
2159         else
2160                 return 0;
2161 }
2162
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164                                          uint64_t fb_modifier)
2165 {
2166         switch (fb_modifier) {
2167         case DRM_FORMAT_MOD_NONE:
2168                 return intel_linear_alignment(dev_priv);
2169         case I915_FORMAT_MOD_X_TILED:
2170                 if (INTEL_INFO(dev_priv)->gen >= 9)
2171                         return 256 * 1024;
2172                 return 0;
2173         case I915_FORMAT_MOD_Y_TILED:
2174         case I915_FORMAT_MOD_Yf_TILED:
2175                 return 1 * 1024 * 1024;
2176         default:
2177                 MISSING_CASE(fb_modifier);
2178                 return 0;
2179         }
2180 }
2181
2182 struct i915_vma *
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2184 {
2185         struct drm_device *dev = fb->dev;
2186         struct drm_i915_private *dev_priv = to_i915(dev);
2187         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2188         struct i915_ggtt_view view;
2189         struct i915_vma *vma;
2190         u32 alignment;
2191
2192         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2193
2194         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2195
2196         intel_fill_fb_ggtt_view(&view, fb, rotation);
2197
2198         /* Note that the w/a also requires 64 PTE of padding following the
2199          * bo. We currently fill all unused PTE with the shadow page and so
2200          * we should always have valid PTE following the scanout preventing
2201          * the VT-d warning.
2202          */
2203         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2204                 alignment = 256 * 1024;
2205
2206         /*
2207          * Global gtt pte registers are special registers which actually forward
2208          * writes to a chunk of system memory. Which means that there is no risk
2209          * that the register values disappear as soon as we call
2210          * intel_runtime_pm_put(), so it is correct to wrap only the
2211          * pin/unpin/fence and not more.
2212          */
2213         intel_runtime_pm_get(dev_priv);
2214
2215         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2216         if (IS_ERR(vma))
2217                 goto err;
2218
2219         if (i915_vma_is_map_and_fenceable(vma)) {
2220                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2221                  * fence, whereas 965+ only requires a fence if using
2222                  * framebuffer compression.  For simplicity, we always, when
2223                  * possible, install a fence as the cost is not that onerous.
2224                  *
2225                  * If we fail to fence the tiled scanout, then either the
2226                  * modeset will reject the change (which is highly unlikely as
2227                  * the affected systems, all but one, do not have unmappable
2228                  * space) or we will not be able to enable full powersaving
2229                  * techniques (also likely not to apply due to various limits
2230                  * FBC and the like impose on the size of the buffer, which
2231                  * presumably we violated anyway with this unmappable buffer).
2232                  * Anyway, it is presumably better to stumble onwards with
2233                  * something and try to run the system in a "less than optimal"
2234                  * mode that matches the user configuration.
2235                  */
2236                 if (i915_vma_get_fence(vma) == 0)
2237                         i915_vma_pin_fence(vma);
2238         }
2239
2240 err:
2241         intel_runtime_pm_put(dev_priv);
2242         return vma;
2243 }
2244
2245 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2246 {
2247         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248         struct i915_ggtt_view view;
2249         struct i915_vma *vma;
2250
2251         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2252
2253         intel_fill_fb_ggtt_view(&view, fb, rotation);
2254         vma = i915_gem_object_to_ggtt(obj, &view);
2255
2256         i915_vma_unpin_fence(vma);
2257         i915_gem_object_unpin_from_display_plane(vma);
2258 }
2259
2260 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2261                           unsigned int rotation)
2262 {
2263         if (drm_rotation_90_or_270(rotation))
2264                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2265         else
2266                 return fb->pitches[plane];
2267 }
2268
2269 /*
2270  * Convert the x/y offsets into a linear offset.
2271  * Only valid with 0/180 degree rotation, which is fine since linear
2272  * offset is only used with linear buffers on pre-hsw and tiled buffers
2273  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2274  */
2275 u32 intel_fb_xy_to_linear(int x, int y,
2276                           const struct intel_plane_state *state,
2277                           int plane)
2278 {
2279         const struct drm_framebuffer *fb = state->base.fb;
2280         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2281         unsigned int pitch = fb->pitches[plane];
2282
2283         return y * pitch + x * cpp;
2284 }
2285
2286 /*
2287  * Add the x/y offsets derived from fb->offsets[] to the user
2288  * specified plane src x/y offsets. The resulting x/y offsets
2289  * specify the start of scanout from the beginning of the gtt mapping.
2290  */
2291 void intel_add_fb_offsets(int *x, int *y,
2292                           const struct intel_plane_state *state,
2293                           int plane)
2294
2295 {
2296         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2297         unsigned int rotation = state->base.rotation;
2298
2299         if (drm_rotation_90_or_270(rotation)) {
2300                 *x += intel_fb->rotated[plane].x;
2301                 *y += intel_fb->rotated[plane].y;
2302         } else {
2303                 *x += intel_fb->normal[plane].x;
2304                 *y += intel_fb->normal[plane].y;
2305         }
2306 }
2307
2308 /*
2309  * Input tile dimensions and pitch must already be
2310  * rotated to match x and y, and in pixel units.
2311  */
2312 static u32 _intel_adjust_tile_offset(int *x, int *y,
2313                                      unsigned int tile_width,
2314                                      unsigned int tile_height,
2315                                      unsigned int tile_size,
2316                                      unsigned int pitch_tiles,
2317                                      u32 old_offset,
2318                                      u32 new_offset)
2319 {
2320         unsigned int pitch_pixels = pitch_tiles * tile_width;
2321         unsigned int tiles;
2322
2323         WARN_ON(old_offset & (tile_size - 1));
2324         WARN_ON(new_offset & (tile_size - 1));
2325         WARN_ON(new_offset > old_offset);
2326
2327         tiles = (old_offset - new_offset) / tile_size;
2328
2329         *y += tiles / pitch_tiles * tile_height;
2330         *x += tiles % pitch_tiles * tile_width;
2331
2332         /* minimize x in case it got needlessly big */
2333         *y += *x / pitch_pixels * tile_height;
2334         *x %= pitch_pixels;
2335
2336         return new_offset;
2337 }
2338
2339 /*
2340  * Adjust the tile offset by moving the difference into
2341  * the x/y offsets.
2342  */
2343 static u32 intel_adjust_tile_offset(int *x, int *y,
2344                                     const struct intel_plane_state *state, int plane,
2345                                     u32 old_offset, u32 new_offset)
2346 {
2347         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2348         const struct drm_framebuffer *fb = state->base.fb;
2349         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2350         unsigned int rotation = state->base.rotation;
2351         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2352
2353         WARN_ON(new_offset > old_offset);
2354
2355         if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2356                 unsigned int tile_size, tile_width, tile_height;
2357                 unsigned int pitch_tiles;
2358
2359                 tile_size = intel_tile_size(dev_priv);
2360                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2361                                 fb->modifier[plane], cpp);
2362
2363                 if (drm_rotation_90_or_270(rotation)) {
2364                         pitch_tiles = pitch / tile_height;
2365                         swap(tile_width, tile_height);
2366                 } else {
2367                         pitch_tiles = pitch / (tile_width * cpp);
2368                 }
2369
2370                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2371                                           tile_size, pitch_tiles,
2372                                           old_offset, new_offset);
2373         } else {
2374                 old_offset += *y * pitch + *x * cpp;
2375
2376                 *y = (old_offset - new_offset) / pitch;
2377                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2378         }
2379
2380         return new_offset;
2381 }
2382
2383 /*
2384  * Computes the linear offset to the base tile and adjusts
2385  * x, y. bytes per pixel is assumed to be a power-of-two.
2386  *
2387  * In the 90/270 rotated case, x and y are assumed
2388  * to be already rotated to match the rotated GTT view, and
2389  * pitch is the tile_height aligned framebuffer height.
2390  *
2391  * This function is used when computing the derived information
2392  * under intel_framebuffer, so using any of that information
2393  * here is not allowed. Anything under drm_framebuffer can be
2394  * used. This is why the user has to pass in the pitch since it
2395  * is specified in the rotated orientation.
2396  */
2397 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2398                                       int *x, int *y,
2399                                       const struct drm_framebuffer *fb, int plane,
2400                                       unsigned int pitch,
2401                                       unsigned int rotation,
2402                                       u32 alignment)
2403 {
2404         uint64_t fb_modifier = fb->modifier[plane];
2405         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2406         u32 offset, offset_aligned;
2407
2408         if (alignment)
2409                 alignment--;
2410
2411         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2412                 unsigned int tile_size, tile_width, tile_height;
2413                 unsigned int tile_rows, tiles, pitch_tiles;
2414
2415                 tile_size = intel_tile_size(dev_priv);
2416                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2417                                 fb_modifier, cpp);
2418
2419                 if (drm_rotation_90_or_270(rotation)) {
2420                         pitch_tiles = pitch / tile_height;
2421                         swap(tile_width, tile_height);
2422                 } else {
2423                         pitch_tiles = pitch / (tile_width * cpp);
2424                 }
2425
2426                 tile_rows = *y / tile_height;
2427                 *y %= tile_height;
2428
2429                 tiles = *x / tile_width;
2430                 *x %= tile_width;
2431
2432                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2433                 offset_aligned = offset & ~alignment;
2434
2435                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2436                                           tile_size, pitch_tiles,
2437                                           offset, offset_aligned);
2438         } else {
2439                 offset = *y * pitch + *x * cpp;
2440                 offset_aligned = offset & ~alignment;
2441
2442                 *y = (offset & alignment) / pitch;
2443                 *x = ((offset & alignment) - *y * pitch) / cpp;
2444         }
2445
2446         return offset_aligned;
2447 }
2448
2449 u32 intel_compute_tile_offset(int *x, int *y,
2450                               const struct intel_plane_state *state,
2451                               int plane)
2452 {
2453         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2454         const struct drm_framebuffer *fb = state->base.fb;
2455         unsigned int rotation = state->base.rotation;
2456         int pitch = intel_fb_pitch(fb, plane, rotation);
2457         u32 alignment;
2458
2459         /* AUX_DIST needs only 4K alignment */
2460         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2461                 alignment = 4096;
2462         else
2463                 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2464
2465         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2466                                           rotation, alignment);
2467 }
2468
2469 /* Convert the fb->offset[] linear offset into x/y offsets */
2470 static void intel_fb_offset_to_xy(int *x, int *y,
2471                                   const struct drm_framebuffer *fb, int plane)
2472 {
2473         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2474         unsigned int pitch = fb->pitches[plane];
2475         u32 linear_offset = fb->offsets[plane];
2476
2477         *y = linear_offset / pitch;
2478         *x = linear_offset % pitch / cpp;
2479 }
2480
2481 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2482 {
2483         switch (fb_modifier) {
2484         case I915_FORMAT_MOD_X_TILED:
2485                 return I915_TILING_X;
2486         case I915_FORMAT_MOD_Y_TILED:
2487                 return I915_TILING_Y;
2488         default:
2489                 return I915_TILING_NONE;
2490         }
2491 }
2492
2493 static int
2494 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2495                    struct drm_framebuffer *fb)
2496 {
2497         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2498         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2499         u32 gtt_offset_rotated = 0;
2500         unsigned int max_size = 0;
2501         uint32_t format = fb->pixel_format;
2502         int i, num_planes = drm_format_num_planes(format);
2503         unsigned int tile_size = intel_tile_size(dev_priv);
2504
2505         for (i = 0; i < num_planes; i++) {
2506                 unsigned int width, height;
2507                 unsigned int cpp, size;
2508                 u32 offset;
2509                 int x, y;
2510
2511                 cpp = drm_format_plane_cpp(format, i);
2512                 width = drm_format_plane_width(fb->width, format, i);
2513                 height = drm_format_plane_height(fb->height, format, i);
2514
2515                 intel_fb_offset_to_xy(&x, &y, fb, i);
2516
2517                 /*
2518                  * The fence (if used) is aligned to the start of the object
2519                  * so having the framebuffer wrap around across the edge of the
2520                  * fenced region doesn't really work. We have no API to configure
2521                  * the fence start offset within the object (nor could we probably
2522                  * on gen2/3). So it's just easier if we just require that the
2523                  * fb layout agrees with the fence layout. We already check that the
2524                  * fb stride matches the fence stride elsewhere.
2525                  */
2526                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2527                     (x + width) * cpp > fb->pitches[i]) {
2528                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2529                                   i, fb->offsets[i]);
2530                         return -EINVAL;
2531                 }
2532
2533                 /*
2534                  * First pixel of the framebuffer from
2535                  * the start of the normal gtt mapping.
2536                  */
2537                 intel_fb->normal[i].x = x;
2538                 intel_fb->normal[i].y = y;
2539
2540                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2541                                                     fb, 0, fb->pitches[i],
2542                                                     DRM_ROTATE_0, tile_size);
2543                 offset /= tile_size;
2544
2545                 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2546                         unsigned int tile_width, tile_height;
2547                         unsigned int pitch_tiles;
2548                         struct drm_rect r;
2549
2550                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2551                                         fb->modifier[i], cpp);
2552
2553                         rot_info->plane[i].offset = offset;
2554                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2555                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2556                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2557
2558                         intel_fb->rotated[i].pitch =
2559                                 rot_info->plane[i].height * tile_height;
2560
2561                         /* how many tiles does this plane need */
2562                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2563                         /*
2564                          * If the plane isn't horizontally tile aligned,
2565                          * we need one more tile.
2566                          */
2567                         if (x != 0)
2568                                 size++;
2569
2570                         /* rotate the x/y offsets to match the GTT view */
2571                         r.x1 = x;
2572                         r.y1 = y;
2573                         r.x2 = x + width;
2574                         r.y2 = y + height;
2575                         drm_rect_rotate(&r,
2576                                         rot_info->plane[i].width * tile_width,
2577                                         rot_info->plane[i].height * tile_height,
2578                                         DRM_ROTATE_270);
2579                         x = r.x1;
2580                         y = r.y1;
2581
2582                         /* rotate the tile dimensions to match the GTT view */
2583                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2584                         swap(tile_width, tile_height);
2585
2586                         /*
2587                          * We only keep the x/y offsets, so push all of the
2588                          * gtt offset into the x/y offsets.
2589                          */
2590                         _intel_adjust_tile_offset(&x, &y, tile_size,
2591                                                   tile_width, tile_height, pitch_tiles,
2592                                                   gtt_offset_rotated * tile_size, 0);
2593
2594                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2595
2596                         /*
2597                          * First pixel of the framebuffer from
2598                          * the start of the rotated gtt mapping.
2599                          */
2600                         intel_fb->rotated[i].x = x;
2601                         intel_fb->rotated[i].y = y;
2602                 } else {
2603                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2604                                             x * cpp, tile_size);
2605                 }
2606
2607                 /* how many tiles in total needed in the bo */
2608                 max_size = max(max_size, offset + size);
2609         }
2610
2611         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2612                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2613                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2614                 return -EINVAL;
2615         }
2616
2617         return 0;
2618 }
2619
2620 static int i9xx_format_to_fourcc(int format)
2621 {
2622         switch (format) {
2623         case DISPPLANE_8BPP:
2624                 return DRM_FORMAT_C8;
2625         case DISPPLANE_BGRX555:
2626                 return DRM_FORMAT_XRGB1555;
2627         case DISPPLANE_BGRX565:
2628                 return DRM_FORMAT_RGB565;
2629         default:
2630         case DISPPLANE_BGRX888:
2631                 return DRM_FORMAT_XRGB8888;
2632         case DISPPLANE_RGBX888:
2633                 return DRM_FORMAT_XBGR8888;
2634         case DISPPLANE_BGRX101010:
2635                 return DRM_FORMAT_XRGB2101010;
2636         case DISPPLANE_RGBX101010:
2637                 return DRM_FORMAT_XBGR2101010;
2638         }
2639 }
2640
2641 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2642 {
2643         switch (format) {
2644         case PLANE_CTL_FORMAT_RGB_565:
2645                 return DRM_FORMAT_RGB565;
2646         default:
2647         case PLANE_CTL_FORMAT_XRGB_8888:
2648                 if (rgb_order) {
2649                         if (alpha)
2650                                 return DRM_FORMAT_ABGR8888;
2651                         else
2652                                 return DRM_FORMAT_XBGR8888;
2653                 } else {
2654                         if (alpha)
2655                                 return DRM_FORMAT_ARGB8888;
2656                         else
2657                                 return DRM_FORMAT_XRGB8888;
2658                 }
2659         case PLANE_CTL_FORMAT_XRGB_2101010:
2660                 if (rgb_order)
2661                         return DRM_FORMAT_XBGR2101010;
2662                 else
2663                         return DRM_FORMAT_XRGB2101010;
2664         }
2665 }
2666
2667 static bool
2668 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2669                               struct intel_initial_plane_config *plane_config)
2670 {
2671         struct drm_device *dev = crtc->base.dev;
2672         struct drm_i915_private *dev_priv = to_i915(dev);
2673         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2674         struct drm_i915_gem_object *obj = NULL;
2675         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2676         struct drm_framebuffer *fb = &plane_config->fb->base;
2677         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2678         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2679                                     PAGE_SIZE);
2680
2681         size_aligned -= base_aligned;
2682
2683         if (plane_config->size == 0)
2684                 return false;
2685
2686         /* If the FB is too big, just don't use it since fbdev is not very
2687          * important and we should probably use that space with FBC or other
2688          * features. */
2689         if (size_aligned * 2 > ggtt->stolen_usable_size)
2690                 return false;
2691
2692         mutex_lock(&dev->struct_mutex);
2693
2694         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2695                                                              base_aligned,
2696                                                              base_aligned,
2697                                                              size_aligned);
2698         if (!obj) {
2699                 mutex_unlock(&dev->struct_mutex);
2700                 return false;
2701         }
2702
2703         if (plane_config->tiling == I915_TILING_X)
2704                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2705
2706         mode_cmd.pixel_format = fb->pixel_format;
2707         mode_cmd.width = fb->width;
2708         mode_cmd.height = fb->height;
2709         mode_cmd.pitches[0] = fb->pitches[0];
2710         mode_cmd.modifier[0] = fb->modifier[0];
2711         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2712
2713         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2714                                    &mode_cmd, obj)) {
2715                 DRM_DEBUG_KMS("intel fb init failed\n");
2716                 goto out_unref_obj;
2717         }
2718
2719         mutex_unlock(&dev->struct_mutex);
2720
2721         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2722         return true;
2723
2724 out_unref_obj:
2725         i915_gem_object_put(obj);
2726         mutex_unlock(&dev->struct_mutex);
2727         return false;
2728 }
2729
2730 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2731 static void
2732 update_state_fb(struct drm_plane *plane)
2733 {
2734         if (plane->fb == plane->state->fb)
2735                 return;
2736
2737         if (plane->state->fb)
2738                 drm_framebuffer_unreference(plane->state->fb);
2739         plane->state->fb = plane->fb;
2740         if (plane->state->fb)
2741                 drm_framebuffer_reference(plane->state->fb);
2742 }
2743
2744 static void
2745 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2746                              struct intel_initial_plane_config *plane_config)
2747 {
2748         struct drm_device *dev = intel_crtc->base.dev;
2749         struct drm_i915_private *dev_priv = to_i915(dev);
2750         struct drm_crtc *c;
2751         struct intel_crtc *i;
2752         struct drm_i915_gem_object *obj;
2753         struct drm_plane *primary = intel_crtc->base.primary;
2754         struct drm_plane_state *plane_state = primary->state;
2755         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2756         struct intel_plane *intel_plane = to_intel_plane(primary);
2757         struct intel_plane_state *intel_state =
2758                 to_intel_plane_state(plane_state);
2759         struct drm_framebuffer *fb;
2760
2761         if (!plane_config->fb)
2762                 return;
2763
2764         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2765                 fb = &plane_config->fb->base;
2766                 goto valid_fb;
2767         }
2768
2769         kfree(plane_config->fb);
2770
2771         /*
2772          * Failed to alloc the obj, check to see if we should share
2773          * an fb with another CRTC instead
2774          */
2775         for_each_crtc(dev, c) {
2776                 i = to_intel_crtc(c);
2777
2778                 if (c == &intel_crtc->base)
2779                         continue;
2780
2781                 if (!i->active)
2782                         continue;
2783
2784                 fb = c->primary->fb;
2785                 if (!fb)
2786                         continue;
2787
2788                 obj = intel_fb_obj(fb);
2789                 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2790                         drm_framebuffer_reference(fb);
2791                         goto valid_fb;
2792                 }
2793         }
2794
2795         /*
2796          * We've failed to reconstruct the BIOS FB.  Current display state
2797          * indicates that the primary plane is visible, but has a NULL FB,
2798          * which will lead to problems later if we don't fix it up.  The
2799          * simplest solution is to just disable the primary plane now and
2800          * pretend the BIOS never had it enabled.
2801          */
2802         to_intel_plane_state(plane_state)->base.visible = false;
2803         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2804         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2805         intel_plane->disable_plane(primary, &intel_crtc->base);
2806
2807         return;
2808
2809 valid_fb:
2810         plane_state->src_x = 0;
2811         plane_state->src_y = 0;
2812         plane_state->src_w = fb->width << 16;
2813         plane_state->src_h = fb->height << 16;
2814
2815         plane_state->crtc_x = 0;
2816         plane_state->crtc_y = 0;
2817         plane_state->crtc_w = fb->width;
2818         plane_state->crtc_h = fb->height;
2819
2820         intel_state->base.src.x1 = plane_state->src_x;
2821         intel_state->base.src.y1 = plane_state->src_y;
2822         intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2823         intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2824         intel_state->base.dst.x1 = plane_state->crtc_x;
2825         intel_state->base.dst.y1 = plane_state->crtc_y;
2826         intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2827         intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2828
2829         obj = intel_fb_obj(fb);
2830         if (i915_gem_object_is_tiled(obj))
2831                 dev_priv->preserve_bios_swizzle = true;
2832
2833         drm_framebuffer_reference(fb);
2834         primary->fb = primary->state->fb = fb;
2835         primary->crtc = primary->state->crtc = &intel_crtc->base;
2836         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2837         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2838                   &obj->frontbuffer_bits);
2839 }
2840
2841 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2842                                unsigned int rotation)
2843 {
2844         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2845
2846         switch (fb->modifier[plane]) {
2847         case DRM_FORMAT_MOD_NONE:
2848         case I915_FORMAT_MOD_X_TILED:
2849                 switch (cpp) {
2850                 case 8:
2851                         return 4096;
2852                 case 4:
2853                 case 2:
2854                 case 1:
2855                         return 8192;
2856                 default:
2857                         MISSING_CASE(cpp);
2858                         break;
2859                 }
2860                 break;
2861         case I915_FORMAT_MOD_Y_TILED:
2862         case I915_FORMAT_MOD_Yf_TILED:
2863                 switch (cpp) {
2864                 case 8:
2865                         return 2048;
2866                 case 4:
2867                         return 4096;
2868                 case 2:
2869                 case 1:
2870                         return 8192;
2871                 default:
2872                         MISSING_CASE(cpp);
2873                         break;
2874                 }
2875                 break;
2876         default:
2877                 MISSING_CASE(fb->modifier[plane]);
2878         }
2879
2880         return 2048;
2881 }
2882
2883 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2884 {
2885         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2886         const struct drm_framebuffer *fb = plane_state->base.fb;
2887         unsigned int rotation = plane_state->base.rotation;
2888         int x = plane_state->base.src.x1 >> 16;
2889         int y = plane_state->base.src.y1 >> 16;
2890         int w = drm_rect_width(&plane_state->base.src) >> 16;
2891         int h = drm_rect_height(&plane_state->base.src) >> 16;
2892         int max_width = skl_max_plane_width(fb, 0, rotation);
2893         int max_height = 4096;
2894         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2895
2896         if (w > max_width || h > max_height) {
2897                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2898                               w, h, max_width, max_height);
2899                 return -EINVAL;
2900         }
2901
2902         intel_add_fb_offsets(&x, &y, plane_state, 0);
2903         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2904
2905         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2906
2907         /*
2908          * AUX surface offset is specified as the distance from the
2909          * main surface offset, and it must be non-negative. Make
2910          * sure that is what we will get.
2911          */
2912         if (offset > aux_offset)
2913                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2914                                                   offset, aux_offset & ~(alignment - 1));
2915
2916         /*
2917          * When using an X-tiled surface, the plane blows up
2918          * if the x offset + width exceed the stride.
2919          *
2920          * TODO: linear and Y-tiled seem fine, Yf untested,
2921          */
2922         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2923                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2924
2925                 while ((x + w) * cpp > fb->pitches[0]) {
2926                         if (offset == 0) {
2927                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2928                                 return -EINVAL;
2929                         }
2930
2931                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2932                                                           offset, offset - alignment);
2933                 }
2934         }
2935
2936         plane_state->main.offset = offset;
2937         plane_state->main.x = x;
2938         plane_state->main.y = y;
2939
2940         return 0;
2941 }
2942
2943 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2944 {
2945         const struct drm_framebuffer *fb = plane_state->base.fb;
2946         unsigned int rotation = plane_state->base.rotation;
2947         int max_width = skl_max_plane_width(fb, 1, rotation);
2948         int max_height = 4096;
2949         int x = plane_state->base.src.x1 >> 17;
2950         int y = plane_state->base.src.y1 >> 17;
2951         int w = drm_rect_width(&plane_state->base.src) >> 17;
2952         int h = drm_rect_height(&plane_state->base.src) >> 17;
2953         u32 offset;
2954
2955         intel_add_fb_offsets(&x, &y, plane_state, 1);
2956         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2957
2958         /* FIXME not quite sure how/if these apply to the chroma plane */
2959         if (w > max_width || h > max_height) {
2960                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2961                               w, h, max_width, max_height);
2962                 return -EINVAL;
2963         }
2964
2965         plane_state->aux.offset = offset;
2966         plane_state->aux.x = x;
2967         plane_state->aux.y = y;
2968
2969         return 0;
2970 }
2971
2972 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2973 {
2974         const struct drm_framebuffer *fb = plane_state->base.fb;
2975         unsigned int rotation = plane_state->base.rotation;
2976         int ret;
2977
2978         /* Rotate src coordinates to match rotated GTT view */
2979         if (drm_rotation_90_or_270(rotation))
2980                 drm_rect_rotate(&plane_state->base.src,
2981                                 fb->width, fb->height, DRM_ROTATE_270);
2982
2983         /*
2984          * Handle the AUX surface first since
2985          * the main surface setup depends on it.
2986          */
2987         if (fb->pixel_format == DRM_FORMAT_NV12) {
2988                 ret = skl_check_nv12_aux_surface(plane_state);
2989                 if (ret)
2990                         return ret;
2991         } else {
2992                 plane_state->aux.offset = ~0xfff;
2993                 plane_state->aux.x = 0;
2994                 plane_state->aux.y = 0;
2995         }
2996
2997         ret = skl_check_main_surface(plane_state);
2998         if (ret)
2999                 return ret;
3000
3001         return 0;
3002 }
3003
3004 static void i9xx_update_primary_plane(struct drm_plane *primary,
3005                                       const struct intel_crtc_state *crtc_state,
3006                                       const struct intel_plane_state *plane_state)
3007 {
3008         struct drm_device *dev = primary->dev;
3009         struct drm_i915_private *dev_priv = to_i915(dev);
3010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3011         struct drm_framebuffer *fb = plane_state->base.fb;
3012         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3013         int plane = intel_crtc->plane;
3014         u32 linear_offset;
3015         u32 dspcntr;
3016         i915_reg_t reg = DSPCNTR(plane);
3017         unsigned int rotation = plane_state->base.rotation;
3018         int x = plane_state->base.src.x1 >> 16;
3019         int y = plane_state->base.src.y1 >> 16;
3020
3021         dspcntr = DISPPLANE_GAMMA_ENABLE;
3022
3023         dspcntr |= DISPLAY_PLANE_ENABLE;
3024
3025         if (INTEL_INFO(dev)->gen < 4) {
3026                 if (intel_crtc->pipe == PIPE_B)
3027                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3028
3029                 /* pipesrc and dspsize control the size that is scaled from,
3030                  * which should always be the user's requested size.
3031                  */
3032                 I915_WRITE(DSPSIZE(plane),
3033                            ((crtc_state->pipe_src_h - 1) << 16) |
3034                            (crtc_state->pipe_src_w - 1));
3035                 I915_WRITE(DSPPOS(plane), 0);
3036         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3037                 I915_WRITE(PRIMSIZE(plane),
3038                            ((crtc_state->pipe_src_h - 1) << 16) |
3039                            (crtc_state->pipe_src_w - 1));
3040                 I915_WRITE(PRIMPOS(plane), 0);
3041                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3042         }
3043
3044         switch (fb->pixel_format) {
3045         case DRM_FORMAT_C8:
3046                 dspcntr |= DISPPLANE_8BPP;
3047                 break;
3048         case DRM_FORMAT_XRGB1555:
3049                 dspcntr |= DISPPLANE_BGRX555;
3050                 break;
3051         case DRM_FORMAT_RGB565:
3052                 dspcntr |= DISPPLANE_BGRX565;
3053                 break;
3054         case DRM_FORMAT_XRGB8888:
3055                 dspcntr |= DISPPLANE_BGRX888;
3056                 break;
3057         case DRM_FORMAT_XBGR8888:
3058                 dspcntr |= DISPPLANE_RGBX888;
3059                 break;
3060         case DRM_FORMAT_XRGB2101010:
3061                 dspcntr |= DISPPLANE_BGRX101010;
3062                 break;
3063         case DRM_FORMAT_XBGR2101010:
3064                 dspcntr |= DISPPLANE_RGBX101010;
3065                 break;
3066         default:
3067                 BUG();
3068         }
3069
3070         if (INTEL_GEN(dev_priv) >= 4 &&
3071             fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3072                 dspcntr |= DISPPLANE_TILED;
3073
3074         if (IS_G4X(dev))
3075                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3076
3077         intel_add_fb_offsets(&x, &y, plane_state, 0);
3078
3079         if (INTEL_INFO(dev)->gen >= 4)
3080                 intel_crtc->dspaddr_offset =
3081                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3082
3083         if (rotation == DRM_ROTATE_180) {
3084                 dspcntr |= DISPPLANE_ROTATE_180;
3085
3086                 x += (crtc_state->pipe_src_w - 1);
3087                 y += (crtc_state->pipe_src_h - 1);
3088         }
3089
3090         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3091
3092         if (INTEL_INFO(dev)->gen < 4)
3093                 intel_crtc->dspaddr_offset = linear_offset;
3094
3095         intel_crtc->adjusted_x = x;
3096         intel_crtc->adjusted_y = y;
3097
3098         I915_WRITE(reg, dspcntr);
3099
3100         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3101         if (INTEL_INFO(dev)->gen >= 4) {
3102                 I915_WRITE(DSPSURF(plane),
3103                            intel_fb_gtt_offset(fb, rotation) +
3104                            intel_crtc->dspaddr_offset);
3105                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3106                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3107         } else
3108                 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
3109         POSTING_READ(reg);
3110 }
3111
3112 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3113                                        struct drm_crtc *crtc)
3114 {
3115         struct drm_device *dev = crtc->dev;
3116         struct drm_i915_private *dev_priv = to_i915(dev);
3117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3118         int plane = intel_crtc->plane;
3119
3120         I915_WRITE(DSPCNTR(plane), 0);
3121         if (INTEL_INFO(dev_priv)->gen >= 4)
3122                 I915_WRITE(DSPSURF(plane), 0);
3123         else
3124                 I915_WRITE(DSPADDR(plane), 0);
3125         POSTING_READ(DSPCNTR(plane));
3126 }
3127
3128 static void ironlake_update_primary_plane(struct drm_plane *primary,
3129                                           const struct intel_crtc_state *crtc_state,
3130                                           const struct intel_plane_state *plane_state)
3131 {
3132         struct drm_device *dev = primary->dev;
3133         struct drm_i915_private *dev_priv = to_i915(dev);
3134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3135         struct drm_framebuffer *fb = plane_state->base.fb;
3136         int plane = intel_crtc->plane;
3137         u32 linear_offset;
3138         u32 dspcntr;
3139         i915_reg_t reg = DSPCNTR(plane);
3140         unsigned int rotation = plane_state->base.rotation;
3141         int x = plane_state->base.src.x1 >> 16;
3142         int y = plane_state->base.src.y1 >> 16;
3143
3144         dspcntr = DISPPLANE_GAMMA_ENABLE;
3145         dspcntr |= DISPLAY_PLANE_ENABLE;
3146
3147         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3148                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3149
3150         switch (fb->pixel_format) {
3151         case DRM_FORMAT_C8:
3152                 dspcntr |= DISPPLANE_8BPP;
3153                 break;
3154         case DRM_FORMAT_RGB565:
3155                 dspcntr |= DISPPLANE_BGRX565;
3156                 break;
3157         case DRM_FORMAT_XRGB8888:
3158                 dspcntr |= DISPPLANE_BGRX888;
3159                 break;
3160         case DRM_FORMAT_XBGR8888:
3161                 dspcntr |= DISPPLANE_RGBX888;
3162                 break;
3163         case DRM_FORMAT_XRGB2101010:
3164                 dspcntr |= DISPPLANE_BGRX101010;
3165                 break;
3166         case DRM_FORMAT_XBGR2101010:
3167                 dspcntr |= DISPPLANE_RGBX101010;
3168                 break;
3169         default:
3170                 BUG();
3171         }
3172
3173         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3174                 dspcntr |= DISPPLANE_TILED;
3175
3176         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
3177                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3178
3179         intel_add_fb_offsets(&x, &y, plane_state, 0);
3180
3181         intel_crtc->dspaddr_offset =
3182                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3183
3184         if (rotation == DRM_ROTATE_180) {
3185                 dspcntr |= DISPPLANE_ROTATE_180;
3186
3187                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
3188                         x += (crtc_state->pipe_src_w - 1);
3189                         y += (crtc_state->pipe_src_h - 1);
3190                 }
3191         }
3192
3193         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3194
3195         intel_crtc->adjusted_x = x;
3196         intel_crtc->adjusted_y = y;
3197
3198         I915_WRITE(reg, dspcntr);
3199
3200         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3201         I915_WRITE(DSPSURF(plane),
3202                    intel_fb_gtt_offset(fb, rotation) +
3203                    intel_crtc->dspaddr_offset);
3204         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3205                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3206         } else {
3207                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3208                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3209         }
3210         POSTING_READ(reg);
3211 }
3212
3213 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3214                               uint64_t fb_modifier, uint32_t pixel_format)
3215 {
3216         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3217                 return 64;
3218         } else {
3219                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3220
3221                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3222         }
3223 }
3224
3225 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3226                         unsigned int rotation)
3227 {
3228         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3229         struct i915_ggtt_view view;
3230         struct i915_vma *vma;
3231
3232         intel_fill_fb_ggtt_view(&view, fb, rotation);
3233
3234         vma = i915_gem_object_to_ggtt(obj, &view);
3235         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3236                  view.type))
3237                 return -1;
3238
3239         return i915_ggtt_offset(vma);
3240 }
3241
3242 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3243 {
3244         struct drm_device *dev = intel_crtc->base.dev;
3245         struct drm_i915_private *dev_priv = to_i915(dev);
3246
3247         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3248         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3249         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3250 }
3251
3252 /*
3253  * This function detaches (aka. unbinds) unused scalers in hardware
3254  */
3255 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3256 {
3257         struct intel_crtc_scaler_state *scaler_state;
3258         int i;
3259
3260         scaler_state = &intel_crtc->config->scaler_state;
3261
3262         /* loop through and disable scalers that aren't in use */
3263         for (i = 0; i < intel_crtc->num_scalers; i++) {
3264                 if (!scaler_state->scalers[i].in_use)
3265                         skl_detach_scaler(intel_crtc, i);
3266         }
3267 }
3268
3269 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3270                      unsigned int rotation)
3271 {
3272         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3273         u32 stride = intel_fb_pitch(fb, plane, rotation);
3274
3275         /*
3276          * The stride is either expressed as a multiple of 64 bytes chunks for
3277          * linear buffers or in number of tiles for tiled buffers.
3278          */
3279         if (drm_rotation_90_or_270(rotation)) {
3280                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3281
3282                 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3283         } else {
3284                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3285                                                     fb->pixel_format);
3286         }
3287
3288         return stride;
3289 }
3290
3291 u32 skl_plane_ctl_format(uint32_t pixel_format)
3292 {
3293         switch (pixel_format) {
3294         case DRM_FORMAT_C8:
3295                 return PLANE_CTL_FORMAT_INDEXED;
3296         case DRM_FORMAT_RGB565:
3297                 return PLANE_CTL_FORMAT_RGB_565;
3298         case DRM_FORMAT_XBGR8888:
3299                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3300         case DRM_FORMAT_XRGB8888:
3301                 return PLANE_CTL_FORMAT_XRGB_8888;
3302         /*
3303          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3304          * to be already pre-multiplied. We need to add a knob (or a different
3305          * DRM_FORMAT) for user-space to configure that.
3306          */
3307         case DRM_FORMAT_ABGR8888:
3308                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3309                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3310         case DRM_FORMAT_ARGB8888:
3311                 return PLANE_CTL_FORMAT_XRGB_8888 |
3312                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3313         case DRM_FORMAT_XRGB2101010:
3314                 return PLANE_CTL_FORMAT_XRGB_2101010;
3315         case DRM_FORMAT_XBGR2101010:
3316                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3317         case DRM_FORMAT_YUYV:
3318                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3319         case DRM_FORMAT_YVYU:
3320                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3321         case DRM_FORMAT_UYVY:
3322                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3323         case DRM_FORMAT_VYUY:
3324                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3325         default:
3326                 MISSING_CASE(pixel_format);
3327         }
3328
3329         return 0;
3330 }
3331
3332 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3333 {
3334         switch (fb_modifier) {
3335         case DRM_FORMAT_MOD_NONE:
3336                 break;
3337         case I915_FORMAT_MOD_X_TILED:
3338                 return PLANE_CTL_TILED_X;
3339         case I915_FORMAT_MOD_Y_TILED:
3340                 return PLANE_CTL_TILED_Y;
3341         case I915_FORMAT_MOD_Yf_TILED:
3342                 return PLANE_CTL_TILED_YF;
3343         default:
3344                 MISSING_CASE(fb_modifier);
3345         }
3346
3347         return 0;
3348 }
3349
3350 u32 skl_plane_ctl_rotation(unsigned int rotation)
3351 {
3352         switch (rotation) {
3353         case DRM_ROTATE_0:
3354                 break;
3355         /*
3356          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3357          * while i915 HW rotation is clockwise, thats why this swapping.
3358          */
3359         case DRM_ROTATE_90:
3360                 return PLANE_CTL_ROTATE_270;
3361         case DRM_ROTATE_180:
3362                 return PLANE_CTL_ROTATE_180;
3363         case DRM_ROTATE_270:
3364                 return PLANE_CTL_ROTATE_90;
3365         default:
3366                 MISSING_CASE(rotation);
3367         }
3368
3369         return 0;
3370 }
3371
3372 static void skylake_update_primary_plane(struct drm_plane *plane,
3373                                          const struct intel_crtc_state *crtc_state,
3374                                          const struct intel_plane_state *plane_state)
3375 {
3376         struct drm_device *dev = plane->dev;
3377         struct drm_i915_private *dev_priv = to_i915(dev);
3378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3379         struct drm_framebuffer *fb = plane_state->base.fb;
3380         const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
3381         int pipe = intel_crtc->pipe;
3382         u32 plane_ctl;
3383         unsigned int rotation = plane_state->base.rotation;
3384         u32 stride = skl_plane_stride(fb, 0, rotation);
3385         u32 surf_addr = plane_state->main.offset;
3386         int scaler_id = plane_state->scaler_id;
3387         int src_x = plane_state->main.x;
3388         int src_y = plane_state->main.y;
3389         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3390         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3391         int dst_x = plane_state->base.dst.x1;
3392         int dst_y = plane_state->base.dst.y1;
3393         int dst_w = drm_rect_width(&plane_state->base.dst);
3394         int dst_h = drm_rect_height(&plane_state->base.dst);
3395
3396         plane_ctl = PLANE_CTL_ENABLE |
3397                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3398                     PLANE_CTL_PIPE_CSC_ENABLE;
3399
3400         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3401         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3402         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3403         plane_ctl |= skl_plane_ctl_rotation(rotation);
3404
3405         /* Sizes are 0 based */
3406         src_w--;
3407         src_h--;
3408         dst_w--;
3409         dst_h--;
3410
3411         intel_crtc->adjusted_x = src_x;
3412         intel_crtc->adjusted_y = src_y;
3413
3414         if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
3415                 skl_write_plane_wm(intel_crtc, wm, 0);
3416
3417         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3418         I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3419         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3420         I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3421
3422         if (scaler_id >= 0) {
3423                 uint32_t ps_ctrl = 0;
3424
3425                 WARN_ON(!dst_w || !dst_h);
3426                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3427                         crtc_state->scaler_state.scalers[scaler_id].mode;
3428                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3429                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3430                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3431                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3432                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3433         } else {
3434                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3435         }
3436
3437         I915_WRITE(PLANE_SURF(pipe, 0),
3438                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
3439
3440         POSTING_READ(PLANE_SURF(pipe, 0));
3441 }
3442
3443 static void skylake_disable_primary_plane(struct drm_plane *primary,
3444                                           struct drm_crtc *crtc)
3445 {
3446         struct drm_device *dev = crtc->dev;
3447         struct drm_i915_private *dev_priv = to_i915(dev);
3448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3449         int pipe = intel_crtc->pipe;
3450
3451         /*
3452          * We only populate skl_results on watermark updates, and if the
3453          * plane's visiblity isn't actually changing neither is its watermarks.
3454          */
3455         if (!crtc->primary->state->visible)
3456                 skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0);
3457
3458         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3459         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3460         POSTING_READ(PLANE_SURF(pipe, 0));
3461 }
3462
3463 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3464 static int
3465 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3466                            int x, int y, enum mode_set_atomic state)
3467 {
3468         /* Support for kgdboc is disabled, this needs a major rework. */
3469         DRM_ERROR("legacy panic handler not supported any more.\n");
3470
3471         return -ENODEV;
3472 }
3473
3474 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3475 {
3476         struct intel_crtc *crtc;
3477
3478         for_each_intel_crtc(&dev_priv->drm, crtc)
3479                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3480 }
3481
3482 static void intel_update_primary_planes(struct drm_device *dev)
3483 {
3484         struct drm_crtc *crtc;
3485
3486         for_each_crtc(dev, crtc) {
3487                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3488                 struct intel_plane_state *plane_state =
3489                         to_intel_plane_state(plane->base.state);
3490
3491                 if (plane_state->base.visible)
3492                         plane->update_plane(&plane->base,
3493                                             to_intel_crtc_state(crtc->state),
3494                                             plane_state);
3495         }
3496 }
3497
3498 static int
3499 __intel_display_resume(struct drm_device *dev,
3500                        struct drm_atomic_state *state)
3501 {
3502         struct drm_crtc_state *crtc_state;
3503         struct drm_crtc *crtc;
3504         int i, ret;
3505
3506         intel_modeset_setup_hw_state(dev);
3507         i915_redisable_vga(dev);
3508
3509         if (!state)
3510                 return 0;
3511
3512         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3513                 /*
3514                  * Force recalculation even if we restore
3515                  * current state. With fast modeset this may not result
3516                  * in a modeset when the state is compatible.
3517                  */
3518                 crtc_state->mode_changed = true;
3519         }
3520
3521         /* ignore any reset values/BIOS leftovers in the WM registers */
3522         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3523
3524         ret = drm_atomic_commit(state);
3525
3526         WARN_ON(ret == -EDEADLK);
3527         return ret;
3528 }
3529
3530 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3531 {
3532         return intel_has_gpu_reset(dev_priv) &&
3533                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3534 }
3535
3536 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3537 {
3538         struct drm_device *dev = &dev_priv->drm;
3539         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3540         struct drm_atomic_state *state;
3541         int ret;
3542
3543         /*
3544          * Need mode_config.mutex so that we don't
3545          * trample ongoing ->detect() and whatnot.
3546          */
3547         mutex_lock(&dev->mode_config.mutex);
3548         drm_modeset_acquire_init(ctx, 0);
3549         while (1) {
3550                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3551                 if (ret != -EDEADLK)
3552                         break;
3553
3554                 drm_modeset_backoff(ctx);
3555         }
3556
3557         /* reset doesn't touch the display, but flips might get nuked anyway, */
3558         if (!i915.force_reset_modeset_test &&
3559             !gpu_reset_clobbers_display(dev_priv))
3560                 return;
3561
3562         /*
3563          * Disabling the crtcs gracefully seems nicer. Also the
3564          * g33 docs say we should at least disable all the planes.
3565          */
3566         state = drm_atomic_helper_duplicate_state(dev, ctx);
3567         if (IS_ERR(state)) {
3568                 ret = PTR_ERR(state);
3569                 state = NULL;
3570                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3571                 goto err;
3572         }
3573
3574         ret = drm_atomic_helper_disable_all(dev, ctx);
3575         if (ret) {
3576                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3577                 goto err;
3578         }
3579
3580         dev_priv->modeset_restore_state = state;
3581         state->acquire_ctx = ctx;
3582         return;
3583
3584 err:
3585         drm_atomic_state_put(state);
3586 }
3587
3588 void intel_finish_reset(struct drm_i915_private *dev_priv)
3589 {
3590         struct drm_device *dev = &dev_priv->drm;
3591         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3592         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3593         int ret;
3594
3595         /*
3596          * Flips in the rings will be nuked by the reset,
3597          * so complete all pending flips so that user space
3598          * will get its events and not get stuck.
3599          */
3600         intel_complete_page_flips(dev_priv);
3601
3602         dev_priv->modeset_restore_state = NULL;
3603
3604         dev_priv->modeset_restore_state = NULL;
3605
3606         /* reset doesn't touch the display */
3607         if (!gpu_reset_clobbers_display(dev_priv)) {
3608                 if (!state) {
3609                         /*
3610                          * Flips in the rings have been nuked by the reset,
3611                          * so update the base address of all primary
3612                          * planes to the the last fb to make sure we're
3613                          * showing the correct fb after a reset.
3614                          *
3615                          * FIXME: Atomic will make this obsolete since we won't schedule
3616                          * CS-based flips (which might get lost in gpu resets) any more.
3617                          */
3618                         intel_update_primary_planes(dev);
3619                 } else {
3620                         ret = __intel_display_resume(dev, state);
3621                         if (ret)
3622                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3623                 }
3624         } else {
3625                 /*
3626                  * The display has been reset as well,
3627                  * so need a full re-initialization.
3628                  */
3629                 intel_runtime_pm_disable_interrupts(dev_priv);
3630                 intel_runtime_pm_enable_interrupts(dev_priv);
3631
3632                 intel_modeset_init_hw(dev);
3633
3634                 spin_lock_irq(&dev_priv->irq_lock);
3635                 if (dev_priv->display.hpd_irq_setup)
3636                         dev_priv->display.hpd_irq_setup(dev_priv);
3637                 spin_unlock_irq(&dev_priv->irq_lock);
3638
3639                 ret = __intel_display_resume(dev, state);
3640                 if (ret)
3641                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3642
3643                 intel_hpd_init(dev_priv);
3644         }
3645
3646         if (state)
3647                 drm_atomic_state_put(state);
3648         drm_modeset_drop_locks(ctx);
3649         drm_modeset_acquire_fini(ctx);
3650         mutex_unlock(&dev->mode_config.mutex);
3651 }
3652
3653 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3654 {
3655         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3656
3657         if (i915_reset_in_progress(error))
3658                 return true;
3659
3660         if (crtc->reset_count != i915_reset_count(error))
3661                 return true;
3662
3663         return false;
3664 }
3665
3666 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3667 {
3668         struct drm_device *dev = crtc->dev;
3669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3670         bool pending;
3671
3672         if (abort_flip_on_reset(intel_crtc))
3673                 return false;
3674
3675         spin_lock_irq(&dev->event_lock);
3676         pending = to_intel_crtc(crtc)->flip_work != NULL;
3677         spin_unlock_irq(&dev->event_lock);
3678
3679         return pending;
3680 }
3681
3682 static void intel_update_pipe_config(struct intel_crtc *crtc,
3683                                      struct intel_crtc_state *old_crtc_state)
3684 {
3685         struct drm_device *dev = crtc->base.dev;
3686         struct drm_i915_private *dev_priv = to_i915(dev);
3687         struct intel_crtc_state *pipe_config =
3688                 to_intel_crtc_state(crtc->base.state);
3689
3690         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3691         crtc->base.mode = crtc->base.state->mode;
3692
3693         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3694                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3695                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3696
3697         /*
3698          * Update pipe size and adjust fitter if needed: the reason for this is
3699          * that in compute_mode_changes we check the native mode (not the pfit
3700          * mode) to see if we can flip rather than do a full mode set. In the
3701          * fastboot case, we'll flip, but if we don't update the pipesrc and
3702          * pfit state, we'll end up with a big fb scanned out into the wrong
3703          * sized surface.
3704          */
3705
3706         I915_WRITE(PIPESRC(crtc->pipe),
3707                    ((pipe_config->pipe_src_w - 1) << 16) |
3708                    (pipe_config->pipe_src_h - 1));
3709
3710         /* on skylake this is done by detaching scalers */
3711         if (INTEL_INFO(dev)->gen >= 9) {
3712                 skl_detach_scalers(crtc);
3713
3714                 if (pipe_config->pch_pfit.enabled)
3715                         skylake_pfit_enable(crtc);
3716         } else if (HAS_PCH_SPLIT(dev)) {
3717                 if (pipe_config->pch_pfit.enabled)
3718                         ironlake_pfit_enable(crtc);
3719                 else if (old_crtc_state->pch_pfit.enabled)
3720                         ironlake_pfit_disable(crtc, true);
3721         }
3722 }
3723
3724 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3725 {
3726         struct drm_device *dev = crtc->dev;
3727         struct drm_i915_private *dev_priv = to_i915(dev);
3728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3729         int pipe = intel_crtc->pipe;
3730         i915_reg_t reg;
3731         u32 temp;
3732
3733         /* enable normal train */
3734         reg = FDI_TX_CTL(pipe);
3735         temp = I915_READ(reg);
3736         if (IS_IVYBRIDGE(dev)) {
3737                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3738                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3739         } else {
3740                 temp &= ~FDI_LINK_TRAIN_NONE;
3741                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3742         }
3743         I915_WRITE(reg, temp);
3744
3745         reg = FDI_RX_CTL(pipe);
3746         temp = I915_READ(reg);
3747         if (HAS_PCH_CPT(dev)) {
3748                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3749                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3750         } else {
3751                 temp &= ~FDI_LINK_TRAIN_NONE;
3752                 temp |= FDI_LINK_TRAIN_NONE;
3753         }
3754         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3755
3756         /* wait one idle pattern time */
3757         POSTING_READ(reg);
3758         udelay(1000);
3759
3760         /* IVB wants error correction enabled */
3761         if (IS_IVYBRIDGE(dev))
3762                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3763                            FDI_FE_ERRC_ENABLE);
3764 }
3765
3766 /* The FDI link training functions for ILK/Ibexpeak. */
3767 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3768 {
3769         struct drm_device *dev = crtc->dev;
3770         struct drm_i915_private *dev_priv = to_i915(dev);
3771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3772         int pipe = intel_crtc->pipe;
3773         i915_reg_t reg;
3774         u32 temp, tries;
3775
3776         /* FDI needs bits from pipe first */
3777         assert_pipe_enabled(dev_priv, pipe);
3778
3779         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3780            for train result */
3781         reg = FDI_RX_IMR(pipe);
3782         temp = I915_READ(reg);
3783         temp &= ~FDI_RX_SYMBOL_LOCK;
3784         temp &= ~FDI_RX_BIT_LOCK;
3785         I915_WRITE(reg, temp);
3786         I915_READ(reg);
3787         udelay(150);
3788
3789         /* enable CPU FDI TX and PCH FDI RX */
3790         reg = FDI_TX_CTL(pipe);
3791         temp = I915_READ(reg);
3792         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3793         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3794         temp &= ~FDI_LINK_TRAIN_NONE;
3795         temp |= FDI_LINK_TRAIN_PATTERN_1;
3796         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3797
3798         reg = FDI_RX_CTL(pipe);
3799         temp = I915_READ(reg);
3800         temp &= ~FDI_LINK_TRAIN_NONE;
3801         temp |= FDI_LINK_TRAIN_PATTERN_1;
3802         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3803
3804         POSTING_READ(reg);
3805         udelay(150);
3806
3807         /* Ironlake workaround, enable clock pointer after FDI enable*/
3808         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3809         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3810                    FDI_RX_PHASE_SYNC_POINTER_EN);
3811
3812         reg = FDI_RX_IIR(pipe);
3813         for (tries = 0; tries < 5; tries++) {
3814                 temp = I915_READ(reg);
3815                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3816
3817                 if ((temp & FDI_RX_BIT_LOCK)) {
3818                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3819                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3820                         break;
3821                 }
3822         }
3823         if (tries == 5)
3824                 DRM_ERROR("FDI train 1 fail!\n");
3825
3826         /* Train 2 */
3827         reg = FDI_TX_CTL(pipe);
3828         temp = I915_READ(reg);
3829         temp &= ~FDI_LINK_TRAIN_NONE;
3830         temp |= FDI_LINK_TRAIN_PATTERN_2;
3831         I915_WRITE(reg, temp);
3832
3833         reg = FDI_RX_CTL(pipe);
3834         temp = I915_READ(reg);
3835         temp &= ~FDI_LINK_TRAIN_NONE;
3836         temp |= FDI_LINK_TRAIN_PATTERN_2;
3837         I915_WRITE(reg, temp);
3838
3839         POSTING_READ(reg);
3840         udelay(150);
3841
3842         reg = FDI_RX_IIR(pipe);
3843         for (tries = 0; tries < 5; tries++) {
3844                 temp = I915_READ(reg);
3845                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3846
3847                 if (temp & FDI_RX_SYMBOL_LOCK) {
3848                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3849                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3850                         break;
3851                 }
3852         }
3853         if (tries == 5)
3854                 DRM_ERROR("FDI train 2 fail!\n");
3855
3856         DRM_DEBUG_KMS("FDI train done\n");
3857
3858 }
3859
3860 static const int snb_b_fdi_train_param[] = {
3861         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3862         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3863         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3864         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3865 };
3866
3867 /* The FDI link training functions for SNB/Cougarpoint. */
3868 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3869 {
3870         struct drm_device *dev = crtc->dev;
3871         struct drm_i915_private *dev_priv = to_i915(dev);
3872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3873         int pipe = intel_crtc->pipe;
3874         i915_reg_t reg;
3875         u32 temp, i, retry;
3876
3877         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3878            for train result */
3879         reg = FDI_RX_IMR(pipe);
3880         temp = I915_READ(reg);
3881         temp &= ~FDI_RX_SYMBOL_LOCK;
3882         temp &= ~FDI_RX_BIT_LOCK;
3883         I915_WRITE(reg, temp);
3884
3885         POSTING_READ(reg);
3886         udelay(150);
3887
3888         /* enable CPU FDI TX and PCH FDI RX */
3889         reg = FDI_TX_CTL(pipe);
3890         temp = I915_READ(reg);
3891         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3892         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3893         temp &= ~FDI_LINK_TRAIN_NONE;
3894         temp |= FDI_LINK_TRAIN_PATTERN_1;
3895         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3896         /* SNB-B */
3897         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3898         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3899
3900         I915_WRITE(FDI_RX_MISC(pipe),
3901                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3902
3903         reg = FDI_RX_CTL(pipe);
3904         temp = I915_READ(reg);
3905         if (HAS_PCH_CPT(dev)) {
3906                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3907                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3908         } else {
3909                 temp &= ~FDI_LINK_TRAIN_NONE;
3910                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3911         }
3912         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3913
3914         POSTING_READ(reg);
3915         udelay(150);
3916
3917         for (i = 0; i < 4; i++) {
3918                 reg = FDI_TX_CTL(pipe);
3919                 temp = I915_READ(reg);
3920                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3921                 temp |= snb_b_fdi_train_param[i];
3922                 I915_WRITE(reg, temp);
3923
3924                 POSTING_READ(reg);
3925                 udelay(500);
3926
3927                 for (retry = 0; retry < 5; retry++) {
3928                         reg = FDI_RX_IIR(pipe);
3929                         temp = I915_READ(reg);
3930                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3931                         if (temp & FDI_RX_BIT_LOCK) {
3932                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3933                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3934                                 break;
3935                         }
3936                         udelay(50);
3937                 }
3938                 if (retry < 5)
3939                         break;
3940         }
3941         if (i == 4)
3942                 DRM_ERROR("FDI train 1 fail!\n");
3943
3944         /* Train 2 */
3945         reg = FDI_TX_CTL(pipe);
3946         temp = I915_READ(reg);
3947         temp &= ~FDI_LINK_TRAIN_NONE;
3948         temp |= FDI_LINK_TRAIN_PATTERN_2;
3949         if (IS_GEN6(dev)) {
3950                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3951                 /* SNB-B */
3952                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3953         }
3954         I915_WRITE(reg, temp);
3955
3956         reg = FDI_RX_CTL(pipe);
3957         temp = I915_READ(reg);
3958         if (HAS_PCH_CPT(dev)) {
3959                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3960                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3961         } else {
3962                 temp &= ~FDI_LINK_TRAIN_NONE;
3963                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3964         }
3965         I915_WRITE(reg, temp);
3966
3967         POSTING_READ(reg);
3968         udelay(150);
3969
3970         for (i = 0; i < 4; i++) {
3971                 reg = FDI_TX_CTL(pipe);
3972                 temp = I915_READ(reg);
3973                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3974                 temp |= snb_b_fdi_train_param[i];
3975                 I915_WRITE(reg, temp);
3976
3977                 POSTING_READ(reg);
3978                 udelay(500);
3979
3980                 for (retry = 0; retry < 5; retry++) {
3981                         reg = FDI_RX_IIR(pipe);
3982                         temp = I915_READ(reg);
3983                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3984                         if (temp & FDI_RX_SYMBOL_LOCK) {
3985                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3986                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3987                                 break;
3988                         }
3989                         udelay(50);
3990                 }
3991                 if (retry < 5)
3992                         break;
3993         }
3994         if (i == 4)
3995                 DRM_ERROR("FDI train 2 fail!\n");
3996
3997         DRM_DEBUG_KMS("FDI train done.\n");
3998 }
3999
4000 /* Manual link training for Ivy Bridge A0 parts */
4001 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
4002 {
4003         struct drm_device *dev = crtc->dev;
4004         struct drm_i915_private *dev_priv = to_i915(dev);
4005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4006         int pipe = intel_crtc->pipe;
4007         i915_reg_t reg;
4008         u32 temp, i, j;
4009
4010         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4011            for train result */
4012         reg = FDI_RX_IMR(pipe);
4013         temp = I915_READ(reg);
4014         temp &= ~FDI_RX_SYMBOL_LOCK;
4015         temp &= ~FDI_RX_BIT_LOCK;
4016         I915_WRITE(reg, temp);
4017
4018         POSTING_READ(reg);
4019         udelay(150);
4020
4021         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4022                       I915_READ(FDI_RX_IIR(pipe)));
4023
4024         /* Try each vswing and preemphasis setting twice before moving on */
4025         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4026                 /* disable first in case we need to retry */
4027                 reg = FDI_TX_CTL(pipe);
4028                 temp = I915_READ(reg);
4029                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4030                 temp &= ~FDI_TX_ENABLE;
4031                 I915_WRITE(reg, temp);
4032
4033                 reg = FDI_RX_CTL(pipe);
4034                 temp = I915_READ(reg);
4035                 temp &= ~FDI_LINK_TRAIN_AUTO;
4036                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4037                 temp &= ~FDI_RX_ENABLE;
4038                 I915_WRITE(reg, temp);
4039
4040                 /* enable CPU FDI TX and PCH FDI RX */
4041                 reg = FDI_TX_CTL(pipe);
4042                 temp = I915_READ(reg);
4043                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4044                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4045                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4046                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4047                 temp |= snb_b_fdi_train_param[j/2];
4048                 temp |= FDI_COMPOSITE_SYNC;
4049                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4050
4051                 I915_WRITE(FDI_RX_MISC(pipe),
4052                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4053
4054                 reg = FDI_RX_CTL(pipe);
4055                 temp = I915_READ(reg);
4056                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4057                 temp |= FDI_COMPOSITE_SYNC;
4058                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4059
4060                 POSTING_READ(reg);
4061                 udelay(1); /* should be 0.5us */
4062
4063                 for (i = 0; i < 4; i++) {
4064                         reg = FDI_RX_IIR(pipe);
4065                         temp = I915_READ(reg);
4066                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4067
4068                         if (temp & FDI_RX_BIT_LOCK ||
4069                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4070                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4071                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4072                                               i);
4073                                 break;
4074                         }
4075                         udelay(1); /* should be 0.5us */
4076                 }
4077                 if (i == 4) {
4078                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4079                         continue;
4080                 }
4081
4082                 /* Train 2 */
4083                 reg = FDI_TX_CTL(pipe);
4084                 temp = I915_READ(reg);
4085                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4086                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4087                 I915_WRITE(reg, temp);
4088
4089                 reg = FDI_RX_CTL(pipe);
4090                 temp = I915_READ(reg);
4091                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4092                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4093                 I915_WRITE(reg, temp);
4094
4095                 POSTING_READ(reg);
4096                 udelay(2); /* should be 1.5us */
4097
4098                 for (i = 0; i < 4; i++) {
4099                         reg = FDI_RX_IIR(pipe);
4100                         temp = I915_READ(reg);
4101                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4102
4103                         if (temp & FDI_RX_SYMBOL_LOCK ||
4104                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4105                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4106                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4107                                               i);
4108                                 goto train_done;
4109                         }
4110                         udelay(2); /* should be 1.5us */
4111                 }
4112                 if (i == 4)
4113                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4114         }
4115
4116 train_done:
4117         DRM_DEBUG_KMS("FDI train done.\n");
4118 }
4119
4120 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4121 {
4122         struct drm_device *dev = intel_crtc->base.dev;
4123         struct drm_i915_private *dev_priv = to_i915(dev);
4124         int pipe = intel_crtc->pipe;
4125         i915_reg_t reg;
4126         u32 temp;
4127
4128         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4129         reg = FDI_RX_CTL(pipe);
4130         temp = I915_READ(reg);
4131         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4132         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4133         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4134         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4135
4136         POSTING_READ(reg);
4137         udelay(200);
4138
4139         /* Switch from Rawclk to PCDclk */
4140         temp = I915_READ(reg);
4141         I915_WRITE(reg, temp | FDI_PCDCLK);
4142
4143         POSTING_READ(reg);
4144         udelay(200);
4145
4146         /* Enable CPU FDI TX PLL, always on for Ironlake */
4147         reg = FDI_TX_CTL(pipe);
4148         temp = I915_READ(reg);
4149         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4150                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4151
4152                 POSTING_READ(reg);
4153                 udelay(100);
4154         }
4155 }
4156
4157 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4158 {
4159         struct drm_device *dev = intel_crtc->base.dev;
4160         struct drm_i915_private *dev_priv = to_i915(dev);
4161         int pipe = intel_crtc->pipe;
4162         i915_reg_t reg;
4163         u32 temp;
4164
4165         /* Switch from PCDclk to Rawclk */
4166         reg = FDI_RX_CTL(pipe);
4167         temp = I915_READ(reg);
4168         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4169
4170         /* Disable CPU FDI TX PLL */
4171         reg = FDI_TX_CTL(pipe);
4172         temp = I915_READ(reg);
4173         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4174
4175         POSTING_READ(reg);
4176         udelay(100);
4177
4178         reg = FDI_RX_CTL(pipe);
4179         temp = I915_READ(reg);
4180         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4181
4182         /* Wait for the clocks to turn off. */
4183         POSTING_READ(reg);
4184         udelay(100);
4185 }
4186
4187 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4188 {
4189         struct drm_device *dev = crtc->dev;
4190         struct drm_i915_private *dev_priv = to_i915(dev);
4191         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4192         int pipe = intel_crtc->pipe;
4193         i915_reg_t reg;
4194         u32 temp;
4195
4196         /* disable CPU FDI tx and PCH FDI rx */
4197         reg = FDI_TX_CTL(pipe);
4198         temp = I915_READ(reg);
4199         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4200         POSTING_READ(reg);
4201
4202         reg = FDI_RX_CTL(pipe);
4203         temp = I915_READ(reg);
4204         temp &= ~(0x7 << 16);
4205         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4206         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4207
4208         POSTING_READ(reg);
4209         udelay(100);
4210
4211         /* Ironlake workaround, disable clock pointer after downing FDI */
4212         if (HAS_PCH_IBX(dev))
4213                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4214
4215         /* still set train pattern 1 */
4216         reg = FDI_TX_CTL(pipe);
4217         temp = I915_READ(reg);
4218         temp &= ~FDI_LINK_TRAIN_NONE;
4219         temp |= FDI_LINK_TRAIN_PATTERN_1;
4220         I915_WRITE(reg, temp);
4221
4222         reg = FDI_RX_CTL(pipe);
4223         temp = I915_READ(reg);
4224         if (HAS_PCH_CPT(dev)) {
4225                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4226                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4227         } else {
4228                 temp &= ~FDI_LINK_TRAIN_NONE;
4229                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4230         }
4231         /* BPC in FDI rx is consistent with that in PIPECONF */
4232         temp &= ~(0x07 << 16);
4233         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4234         I915_WRITE(reg, temp);
4235
4236         POSTING_READ(reg);
4237         udelay(100);
4238 }
4239
4240 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4241 {
4242         struct intel_crtc *crtc;
4243
4244         /* Note that we don't need to be called with mode_config.lock here
4245          * as our list of CRTC objects is static for the lifetime of the
4246          * device and so cannot disappear as we iterate. Similarly, we can
4247          * happily treat the predicates as racy, atomic checks as userspace
4248          * cannot claim and pin a new fb without at least acquring the
4249          * struct_mutex and so serialising with us.
4250          */
4251         for_each_intel_crtc(dev, crtc) {
4252                 if (atomic_read(&crtc->unpin_work_count) == 0)
4253                         continue;
4254
4255                 if (crtc->flip_work)
4256                         intel_wait_for_vblank(dev, crtc->pipe);
4257
4258                 return true;
4259         }
4260
4261         return false;
4262 }
4263
4264 static void page_flip_completed(struct intel_crtc *intel_crtc)
4265 {
4266         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4267         struct intel_flip_work *work = intel_crtc->flip_work;
4268
4269         intel_crtc->flip_work = NULL;
4270
4271         if (work->event)
4272                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4273
4274         drm_crtc_vblank_put(&intel_crtc->base);
4275
4276         wake_up_all(&dev_priv->pending_flip_queue);
4277         queue_work(dev_priv->wq, &work->unpin_work);
4278
4279         trace_i915_flip_complete(intel_crtc->plane,
4280                                  work->pending_flip_obj);
4281 }
4282
4283 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4284 {
4285         struct drm_device *dev = crtc->dev;
4286         struct drm_i915_private *dev_priv = to_i915(dev);
4287         long ret;
4288
4289         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4290
4291         ret = wait_event_interruptible_timeout(
4292                                         dev_priv->pending_flip_queue,
4293                                         !intel_crtc_has_pending_flip(crtc),
4294                                         60*HZ);
4295
4296         if (ret < 0)
4297                 return ret;
4298
4299         if (ret == 0) {
4300                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4301                 struct intel_flip_work *work;
4302
4303                 spin_lock_irq(&dev->event_lock);
4304                 work = intel_crtc->flip_work;
4305                 if (work && !is_mmio_work(work)) {
4306                         WARN_ONCE(1, "Removing stuck page flip\n");
4307                         page_flip_completed(intel_crtc);
4308                 }
4309                 spin_unlock_irq(&dev->event_lock);
4310         }
4311
4312         return 0;
4313 }
4314
4315 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4316 {
4317         u32 temp;
4318
4319         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4320
4321         mutex_lock(&dev_priv->sb_lock);
4322
4323         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4324         temp |= SBI_SSCCTL_DISABLE;
4325         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4326
4327         mutex_unlock(&dev_priv->sb_lock);
4328 }
4329
4330 /* Program iCLKIP clock to the desired frequency */
4331 static void lpt_program_iclkip(struct drm_crtc *crtc)
4332 {
4333         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4334         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4335         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4336         u32 temp;
4337
4338         lpt_disable_iclkip(dev_priv);
4339
4340         /* The iCLK virtual clock root frequency is in MHz,
4341          * but the adjusted_mode->crtc_clock in in KHz. To get the
4342          * divisors, it is necessary to divide one by another, so we
4343          * convert the virtual clock precision to KHz here for higher
4344          * precision.
4345          */
4346         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4347                 u32 iclk_virtual_root_freq = 172800 * 1000;
4348                 u32 iclk_pi_range = 64;
4349                 u32 desired_divisor;
4350
4351                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4352                                                     clock << auxdiv);
4353                 divsel = (desired_divisor / iclk_pi_range) - 2;
4354                 phaseinc = desired_divisor % iclk_pi_range;
4355
4356                 /*
4357                  * Near 20MHz is a corner case which is
4358                  * out of range for the 7-bit divisor
4359                  */
4360                 if (divsel <= 0x7f)
4361                         break;
4362         }
4363
4364         /* This should not happen with any sane values */
4365         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4366                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4367         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4368                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4369
4370         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4371                         clock,
4372                         auxdiv,
4373                         divsel,
4374                         phasedir,
4375                         phaseinc);
4376
4377         mutex_lock(&dev_priv->sb_lock);
4378
4379         /* Program SSCDIVINTPHASE6 */
4380         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4381         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4382         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4383         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4384         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4385         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4386         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4387         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4388
4389         /* Program SSCAUXDIV */
4390         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4391         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4392         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4393         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4394
4395         /* Enable modulator and associated divider */
4396         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4397         temp &= ~SBI_SSCCTL_DISABLE;
4398         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4399
4400         mutex_unlock(&dev_priv->sb_lock);
4401
4402         /* Wait for initialization time */
4403         udelay(24);
4404
4405         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4406 }
4407
4408 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4409 {
4410         u32 divsel, phaseinc, auxdiv;
4411         u32 iclk_virtual_root_freq = 172800 * 1000;
4412         u32 iclk_pi_range = 64;
4413         u32 desired_divisor;
4414         u32 temp;
4415
4416         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4417                 return 0;
4418
4419         mutex_lock(&dev_priv->sb_lock);
4420
4421         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4422         if (temp & SBI_SSCCTL_DISABLE) {
4423                 mutex_unlock(&dev_priv->sb_lock);
4424                 return 0;
4425         }
4426
4427         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4428         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4429                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4430         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4431                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4432
4433         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4434         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4435                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4436
4437         mutex_unlock(&dev_priv->sb_lock);
4438
4439         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4440
4441         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4442                                  desired_divisor << auxdiv);
4443 }
4444
4445 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4446                                                 enum pipe pch_transcoder)
4447 {
4448         struct drm_device *dev = crtc->base.dev;
4449         struct drm_i915_private *dev_priv = to_i915(dev);
4450         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4451
4452         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4453                    I915_READ(HTOTAL(cpu_transcoder)));
4454         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4455                    I915_READ(HBLANK(cpu_transcoder)));
4456         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4457                    I915_READ(HSYNC(cpu_transcoder)));
4458
4459         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4460                    I915_READ(VTOTAL(cpu_transcoder)));
4461         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4462                    I915_READ(VBLANK(cpu_transcoder)));
4463         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4464                    I915_READ(VSYNC(cpu_transcoder)));
4465         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4466                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4467 }
4468
4469 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4470 {
4471         struct drm_i915_private *dev_priv = to_i915(dev);
4472         uint32_t temp;
4473
4474         temp = I915_READ(SOUTH_CHICKEN1);
4475         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4476                 return;
4477
4478         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4479         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4480
4481         temp &= ~FDI_BC_BIFURCATION_SELECT;
4482         if (enable)
4483                 temp |= FDI_BC_BIFURCATION_SELECT;
4484
4485         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4486         I915_WRITE(SOUTH_CHICKEN1, temp);
4487         POSTING_READ(SOUTH_CHICKEN1);
4488 }
4489
4490 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4491 {
4492         struct drm_device *dev = intel_crtc->base.dev;
4493
4494         switch (intel_crtc->pipe) {
4495         case PIPE_A:
4496                 break;
4497         case PIPE_B:
4498                 if (intel_crtc->config->fdi_lanes > 2)
4499                         cpt_set_fdi_bc_bifurcation(dev, false);
4500                 else
4501                         cpt_set_fdi_bc_bifurcation(dev, true);
4502
4503                 break;
4504         case PIPE_C:
4505                 cpt_set_fdi_bc_bifurcation(dev, true);
4506
4507                 break;
4508         default:
4509                 BUG();
4510         }
4511 }
4512
4513 /* Return which DP Port should be selected for Transcoder DP control */
4514 static enum port
4515 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4516 {
4517         struct drm_device *dev = crtc->dev;
4518         struct intel_encoder *encoder;
4519
4520         for_each_encoder_on_crtc(dev, crtc, encoder) {
4521                 if (encoder->type == INTEL_OUTPUT_DP ||
4522                     encoder->type == INTEL_OUTPUT_EDP)
4523                         return enc_to_dig_port(&encoder->base)->port;
4524         }
4525
4526         return -1;
4527 }
4528
4529 /*
4530  * Enable PCH resources required for PCH ports:
4531  *   - PCH PLLs
4532  *   - FDI training & RX/TX
4533  *   - update transcoder timings
4534  *   - DP transcoding bits
4535  *   - transcoder
4536  */
4537 static void ironlake_pch_enable(struct drm_crtc *crtc)
4538 {
4539         struct drm_device *dev = crtc->dev;
4540         struct drm_i915_private *dev_priv = to_i915(dev);
4541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4542         int pipe = intel_crtc->pipe;
4543         u32 temp;
4544
4545         assert_pch_transcoder_disabled(dev_priv, pipe);
4546
4547         if (IS_IVYBRIDGE(dev))
4548                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4549
4550         /* Write the TU size bits before fdi link training, so that error
4551          * detection works. */
4552         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4553                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4554
4555         /* For PCH output, training FDI link */
4556         dev_priv->display.fdi_link_train(crtc);
4557
4558         /* We need to program the right clock selection before writing the pixel
4559          * mutliplier into the DPLL. */
4560         if (HAS_PCH_CPT(dev)) {
4561                 u32 sel;
4562
4563                 temp = I915_READ(PCH_DPLL_SEL);
4564                 temp |= TRANS_DPLL_ENABLE(pipe);
4565                 sel = TRANS_DPLLB_SEL(pipe);
4566                 if (intel_crtc->config->shared_dpll ==
4567                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4568                         temp |= sel;
4569                 else
4570                         temp &= ~sel;
4571                 I915_WRITE(PCH_DPLL_SEL, temp);
4572         }
4573
4574         /* XXX: pch pll's can be enabled any time before we enable the PCH
4575          * transcoder, and we actually should do this to not upset any PCH
4576          * transcoder that already use the clock when we share it.
4577          *
4578          * Note that enable_shared_dpll tries to do the right thing, but
4579          * get_shared_dpll unconditionally resets the pll - we need that to have
4580          * the right LVDS enable sequence. */
4581         intel_enable_shared_dpll(intel_crtc);
4582
4583         /* set transcoder timing, panel must allow it */
4584         assert_panel_unlocked(dev_priv, pipe);
4585         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4586
4587         intel_fdi_normal_train(crtc);
4588
4589         /* For PCH DP, enable TRANS_DP_CTL */
4590         if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4591                 const struct drm_display_mode *adjusted_mode =
4592                         &intel_crtc->config->base.adjusted_mode;
4593                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4594                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4595                 temp = I915_READ(reg);
4596                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4597                           TRANS_DP_SYNC_MASK |
4598                           TRANS_DP_BPC_MASK);
4599                 temp |= TRANS_DP_OUTPUT_ENABLE;
4600                 temp |= bpc << 9; /* same format but at 11:9 */
4601
4602                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4603                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4604                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4605                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4606
4607                 switch (intel_trans_dp_port_sel(crtc)) {
4608                 case PORT_B:
4609                         temp |= TRANS_DP_PORT_SEL_B;
4610                         break;
4611                 case PORT_C:
4612                         temp |= TRANS_DP_PORT_SEL_C;
4613                         break;
4614                 case PORT_D:
4615                         temp |= TRANS_DP_PORT_SEL_D;
4616                         break;
4617                 default:
4618                         BUG();
4619                 }
4620
4621                 I915_WRITE(reg, temp);
4622         }
4623
4624         ironlake_enable_pch_transcoder(dev_priv, pipe);
4625 }
4626
4627 static void lpt_pch_enable(struct drm_crtc *crtc)
4628 {
4629         struct drm_device *dev = crtc->dev;
4630         struct drm_i915_private *dev_priv = to_i915(dev);
4631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4632         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4633
4634         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4635
4636         lpt_program_iclkip(crtc);
4637
4638         /* Set transcoder timing. */
4639         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4640
4641         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4642 }
4643
4644 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4645 {
4646         struct drm_i915_private *dev_priv = to_i915(dev);
4647         i915_reg_t dslreg = PIPEDSL(pipe);
4648         u32 temp;
4649
4650         temp = I915_READ(dslreg);
4651         udelay(500);
4652         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4653                 if (wait_for(I915_READ(dslreg) != temp, 5))
4654                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4655         }
4656 }
4657
4658 static int
4659 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4660                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4661                   int src_w, int src_h, int dst_w, int dst_h)
4662 {
4663         struct intel_crtc_scaler_state *scaler_state =
4664                 &crtc_state->scaler_state;
4665         struct intel_crtc *intel_crtc =
4666                 to_intel_crtc(crtc_state->base.crtc);
4667         int need_scaling;
4668
4669         need_scaling = drm_rotation_90_or_270(rotation) ?
4670                 (src_h != dst_w || src_w != dst_h):
4671                 (src_w != dst_w || src_h != dst_h);
4672
4673         /*
4674          * if plane is being disabled or scaler is no more required or force detach
4675          *  - free scaler binded to this plane/crtc
4676          *  - in order to do this, update crtc->scaler_usage
4677          *
4678          * Here scaler state in crtc_state is set free so that
4679          * scaler can be assigned to other user. Actual register
4680          * update to free the scaler is done in plane/panel-fit programming.
4681          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4682          */
4683         if (force_detach || !need_scaling) {
4684                 if (*scaler_id >= 0) {
4685                         scaler_state->scaler_users &= ~(1 << scaler_user);
4686                         scaler_state->scalers[*scaler_id].in_use = 0;
4687
4688                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4689                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4690                                 intel_crtc->pipe, scaler_user, *scaler_id,
4691                                 scaler_state->scaler_users);
4692                         *scaler_id = -1;
4693                 }
4694                 return 0;
4695         }
4696
4697         /* range checks */
4698         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4699                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4700
4701                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4702                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4703                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4704                         "size is out of scaler range\n",
4705                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4706                 return -EINVAL;
4707         }
4708
4709         /* mark this plane as a scaler user in crtc_state */
4710         scaler_state->scaler_users |= (1 << scaler_user);
4711         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4712                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4713                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4714                 scaler_state->scaler_users);
4715
4716         return 0;
4717 }
4718
4719 /**
4720  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4721  *
4722  * @state: crtc's scaler state
4723  *
4724  * Return
4725  *     0 - scaler_usage updated successfully
4726  *    error - requested scaling cannot be supported or other error condition
4727  */
4728 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4729 {
4730         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4731         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4732
4733         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4734                       intel_crtc->base.base.id, intel_crtc->base.name,
4735                       intel_crtc->pipe, SKL_CRTC_INDEX);
4736
4737         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4738                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4739                 state->pipe_src_w, state->pipe_src_h,
4740                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4741 }
4742
4743 /**
4744  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4745  *
4746  * @state: crtc's scaler state
4747  * @plane_state: atomic plane state to update
4748  *
4749  * Return
4750  *     0 - scaler_usage updated successfully
4751  *    error - requested scaling cannot be supported or other error condition
4752  */
4753 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4754                                    struct intel_plane_state *plane_state)
4755 {
4756
4757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4758         struct intel_plane *intel_plane =
4759                 to_intel_plane(plane_state->base.plane);
4760         struct drm_framebuffer *fb = plane_state->base.fb;
4761         int ret;
4762
4763         bool force_detach = !fb || !plane_state->base.visible;
4764
4765         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4766                       intel_plane->base.base.id, intel_plane->base.name,
4767                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4768
4769         ret = skl_update_scaler(crtc_state, force_detach,
4770                                 drm_plane_index(&intel_plane->base),
4771                                 &plane_state->scaler_id,
4772                                 plane_state->base.rotation,
4773                                 drm_rect_width(&plane_state->base.src) >> 16,
4774                                 drm_rect_height(&plane_state->base.src) >> 16,
4775                                 drm_rect_width(&plane_state->base.dst),
4776                                 drm_rect_height(&plane_state->base.dst));
4777
4778         if (ret || plane_state->scaler_id < 0)
4779                 return ret;
4780
4781         /* check colorkey */
4782         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4783                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4784                               intel_plane->base.base.id,
4785                               intel_plane->base.name);
4786                 return -EINVAL;
4787         }
4788
4789         /* Check src format */
4790         switch (fb->pixel_format) {
4791         case DRM_FORMAT_RGB565:
4792         case DRM_FORMAT_XBGR8888:
4793         case DRM_FORMAT_XRGB8888:
4794         case DRM_FORMAT_ABGR8888:
4795         case DRM_FORMAT_ARGB8888:
4796         case DRM_FORMAT_XRGB2101010:
4797         case DRM_FORMAT_XBGR2101010:
4798         case DRM_FORMAT_YUYV:
4799         case DRM_FORMAT_YVYU:
4800         case DRM_FORMAT_UYVY:
4801         case DRM_FORMAT_VYUY:
4802                 break;
4803         default:
4804                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4805                               intel_plane->base.base.id, intel_plane->base.name,
4806                               fb->base.id, fb->pixel_format);
4807                 return -EINVAL;
4808         }
4809
4810         return 0;
4811 }
4812
4813 static void skylake_scaler_disable(struct intel_crtc *crtc)
4814 {
4815         int i;
4816
4817         for (i = 0; i < crtc->num_scalers; i++)
4818                 skl_detach_scaler(crtc, i);
4819 }
4820
4821 static void skylake_pfit_enable(struct intel_crtc *crtc)
4822 {
4823         struct drm_device *dev = crtc->base.dev;
4824         struct drm_i915_private *dev_priv = to_i915(dev);
4825         int pipe = crtc->pipe;
4826         struct intel_crtc_scaler_state *scaler_state =
4827                 &crtc->config->scaler_state;
4828
4829         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4830
4831         if (crtc->config->pch_pfit.enabled) {
4832                 int id;
4833
4834                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4835                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4836                         return;
4837                 }
4838
4839                 id = scaler_state->scaler_id;
4840                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4841                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4842                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4843                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4844
4845                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4846         }
4847 }
4848
4849 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4850 {
4851         struct drm_device *dev = crtc->base.dev;
4852         struct drm_i915_private *dev_priv = to_i915(dev);
4853         int pipe = crtc->pipe;
4854
4855         if (crtc->config->pch_pfit.enabled) {
4856                 /* Force use of hard-coded filter coefficients
4857                  * as some pre-programmed values are broken,
4858                  * e.g. x201.
4859                  */
4860                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4861                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4862                                                  PF_PIPE_SEL_IVB(pipe));
4863                 else
4864                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4865                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4866                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4867         }
4868 }
4869
4870 void hsw_enable_ips(struct intel_crtc *crtc)
4871 {
4872         struct drm_device *dev = crtc->base.dev;
4873         struct drm_i915_private *dev_priv = to_i915(dev);
4874
4875         if (!crtc->config->ips_enabled)
4876                 return;
4877
4878         /*
4879          * We can only enable IPS after we enable a plane and wait for a vblank
4880          * This function is called from post_plane_update, which is run after
4881          * a vblank wait.
4882          */
4883
4884         assert_plane_enabled(dev_priv, crtc->plane);
4885         if (IS_BROADWELL(dev)) {
4886                 mutex_lock(&dev_priv->rps.hw_lock);
4887                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4888                 mutex_unlock(&dev_priv->rps.hw_lock);
4889                 /* Quoting Art Runyan: "its not safe to expect any particular
4890                  * value in IPS_CTL bit 31 after enabling IPS through the
4891                  * mailbox." Moreover, the mailbox may return a bogus state,
4892                  * so we need to just enable it and continue on.
4893                  */
4894         } else {
4895                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4896                 /* The bit only becomes 1 in the next vblank, so this wait here
4897                  * is essentially intel_wait_for_vblank. If we don't have this
4898                  * and don't wait for vblanks until the end of crtc_enable, then
4899                  * the HW state readout code will complain that the expected
4900                  * IPS_CTL value is not the one we read. */
4901                 if (intel_wait_for_register(dev_priv,
4902                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4903                                             50))
4904                         DRM_ERROR("Timed out waiting for IPS enable\n");
4905         }
4906 }
4907
4908 void hsw_disable_ips(struct intel_crtc *crtc)
4909 {
4910         struct drm_device *dev = crtc->base.dev;
4911         struct drm_i915_private *dev_priv = to_i915(dev);
4912
4913         if (!crtc->config->ips_enabled)
4914                 return;
4915
4916         assert_plane_enabled(dev_priv, crtc->plane);
4917         if (IS_BROADWELL(dev)) {
4918                 mutex_lock(&dev_priv->rps.hw_lock);
4919                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4920                 mutex_unlock(&dev_priv->rps.hw_lock);
4921                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4922                 if (intel_wait_for_register(dev_priv,
4923                                             IPS_CTL, IPS_ENABLE, 0,
4924                                             42))
4925                         DRM_ERROR("Timed out waiting for IPS disable\n");
4926         } else {
4927                 I915_WRITE(IPS_CTL, 0);
4928                 POSTING_READ(IPS_CTL);
4929         }
4930
4931         /* We need to wait for a vblank before we can disable the plane. */
4932         intel_wait_for_vblank(dev, crtc->pipe);
4933 }
4934
4935 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4936 {
4937         if (intel_crtc->overlay) {
4938                 struct drm_device *dev = intel_crtc->base.dev;
4939                 struct drm_i915_private *dev_priv = to_i915(dev);
4940
4941                 mutex_lock(&dev->struct_mutex);
4942                 dev_priv->mm.interruptible = false;
4943                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4944                 dev_priv->mm.interruptible = true;
4945                 mutex_unlock(&dev->struct_mutex);
4946         }
4947
4948         /* Let userspace switch the overlay on again. In most cases userspace
4949          * has to recompute where to put it anyway.
4950          */
4951 }
4952
4953 /**
4954  * intel_post_enable_primary - Perform operations after enabling primary plane
4955  * @crtc: the CRTC whose primary plane was just enabled
4956  *
4957  * Performs potentially sleeping operations that must be done after the primary
4958  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4959  * called due to an explicit primary plane update, or due to an implicit
4960  * re-enable that is caused when a sprite plane is updated to no longer
4961  * completely hide the primary plane.
4962  */
4963 static void
4964 intel_post_enable_primary(struct drm_crtc *crtc)
4965 {
4966         struct drm_device *dev = crtc->dev;
4967         struct drm_i915_private *dev_priv = to_i915(dev);
4968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969         int pipe = intel_crtc->pipe;
4970
4971         /*
4972          * FIXME IPS should be fine as long as one plane is
4973          * enabled, but in practice it seems to have problems
4974          * when going from primary only to sprite only and vice
4975          * versa.
4976          */
4977         hsw_enable_ips(intel_crtc);
4978
4979         /*
4980          * Gen2 reports pipe underruns whenever all planes are disabled.
4981          * So don't enable underrun reporting before at least some planes
4982          * are enabled.
4983          * FIXME: Need to fix the logic to work when we turn off all planes
4984          * but leave the pipe running.
4985          */
4986         if (IS_GEN2(dev))
4987                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4988
4989         /* Underruns don't always raise interrupts, so check manually. */
4990         intel_check_cpu_fifo_underruns(dev_priv);
4991         intel_check_pch_fifo_underruns(dev_priv);
4992 }
4993
4994 /* FIXME move all this to pre_plane_update() with proper state tracking */
4995 static void
4996 intel_pre_disable_primary(struct drm_crtc *crtc)
4997 {
4998         struct drm_device *dev = crtc->dev;
4999         struct drm_i915_private *dev_priv = to_i915(dev);
5000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5001         int pipe = intel_crtc->pipe;
5002
5003         /*
5004          * Gen2 reports pipe underruns whenever all planes are disabled.
5005          * So diasble underrun reporting before all the planes get disabled.
5006          * FIXME: Need to fix the logic to work when we turn off all planes
5007          * but leave the pipe running.
5008          */
5009         if (IS_GEN2(dev))
5010                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5011
5012         /*
5013          * FIXME IPS should be fine as long as one plane is
5014          * enabled, but in practice it seems to have problems
5015          * when going from primary only to sprite only and vice
5016          * versa.
5017          */
5018         hsw_disable_ips(intel_crtc);
5019 }
5020
5021 /* FIXME get rid of this and use pre_plane_update */
5022 static void
5023 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5024 {
5025         struct drm_device *dev = crtc->dev;
5026         struct drm_i915_private *dev_priv = to_i915(dev);
5027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028         int pipe = intel_crtc->pipe;
5029
5030         intel_pre_disable_primary(crtc);
5031
5032         /*
5033          * Vblank time updates from the shadow to live plane control register
5034          * are blocked if the memory self-refresh mode is active at that
5035          * moment. So to make sure the plane gets truly disabled, disable
5036          * first the self-refresh mode. The self-refresh enable bit in turn
5037          * will be checked/applied by the HW only at the next frame start
5038          * event which is after the vblank start event, so we need to have a
5039          * wait-for-vblank between disabling the plane and the pipe.
5040          */
5041         if (HAS_GMCH_DISPLAY(dev)) {
5042                 intel_set_memory_cxsr(dev_priv, false);
5043                 dev_priv->wm.vlv.cxsr = false;
5044                 intel_wait_for_vblank(dev, pipe);
5045         }
5046 }
5047
5048 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5049 {
5050         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5051         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5052         struct intel_crtc_state *pipe_config =
5053                 to_intel_crtc_state(crtc->base.state);
5054         struct drm_plane *primary = crtc->base.primary;
5055         struct drm_plane_state *old_pri_state =
5056                 drm_atomic_get_existing_plane_state(old_state, primary);
5057
5058         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5059
5060         crtc->wm.cxsr_allowed = true;
5061
5062         if (pipe_config->update_wm_post && pipe_config->base.active)
5063                 intel_update_watermarks(&crtc->base);
5064
5065         if (old_pri_state) {
5066                 struct intel_plane_state *primary_state =
5067                         to_intel_plane_state(primary->state);
5068                 struct intel_plane_state *old_primary_state =
5069                         to_intel_plane_state(old_pri_state);
5070
5071                 intel_fbc_post_update(crtc);
5072
5073                 if (primary_state->base.visible &&
5074                     (needs_modeset(&pipe_config->base) ||
5075                      !old_primary_state->base.visible))
5076                         intel_post_enable_primary(&crtc->base);
5077         }
5078 }
5079
5080 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5081 {
5082         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5083         struct drm_device *dev = crtc->base.dev;
5084         struct drm_i915_private *dev_priv = to_i915(dev);
5085         struct intel_crtc_state *pipe_config =
5086                 to_intel_crtc_state(crtc->base.state);
5087         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5088         struct drm_plane *primary = crtc->base.primary;
5089         struct drm_plane_state *old_pri_state =
5090                 drm_atomic_get_existing_plane_state(old_state, primary);
5091         bool modeset = needs_modeset(&pipe_config->base);
5092
5093         if (old_pri_state) {
5094                 struct intel_plane_state *primary_state =
5095                         to_intel_plane_state(primary->state);
5096                 struct intel_plane_state *old_primary_state =
5097                         to_intel_plane_state(old_pri_state);
5098
5099                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5100
5101                 if (old_primary_state->base.visible &&
5102                     (modeset || !primary_state->base.visible))
5103                         intel_pre_disable_primary(&crtc->base);
5104         }
5105
5106         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
5107                 crtc->wm.cxsr_allowed = false;
5108
5109                 /*
5110                  * Vblank time updates from the shadow to live plane control register
5111                  * are blocked if the memory self-refresh mode is active at that
5112                  * moment. So to make sure the plane gets truly disabled, disable
5113                  * first the self-refresh mode. The self-refresh enable bit in turn
5114                  * will be checked/applied by the HW only at the next frame start
5115                  * event which is after the vblank start event, so we need to have a
5116                  * wait-for-vblank between disabling the plane and the pipe.
5117                  */
5118                 if (old_crtc_state->base.active) {
5119                         intel_set_memory_cxsr(dev_priv, false);
5120                         dev_priv->wm.vlv.cxsr = false;
5121                         intel_wait_for_vblank(dev, crtc->pipe);
5122                 }
5123         }
5124
5125         /*
5126          * IVB workaround: must disable low power watermarks for at least
5127          * one frame before enabling scaling.  LP watermarks can be re-enabled
5128          * when scaling is disabled.
5129          *
5130          * WaCxSRDisabledForSpriteScaling:ivb
5131          */
5132         if (pipe_config->disable_lp_wm) {
5133                 ilk_disable_lp_wm(dev);
5134                 intel_wait_for_vblank(dev, crtc->pipe);
5135         }
5136
5137         /*
5138          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5139          * watermark programming here.
5140          */
5141         if (needs_modeset(&pipe_config->base))
5142                 return;
5143
5144         /*
5145          * For platforms that support atomic watermarks, program the
5146          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5147          * will be the intermediate values that are safe for both pre- and
5148          * post- vblank; when vblank happens, the 'active' values will be set
5149          * to the final 'target' values and we'll do this again to get the
5150          * optimal watermarks.  For gen9+ platforms, the values we program here
5151          * will be the final target values which will get automatically latched
5152          * at vblank time; no further programming will be necessary.
5153          *
5154          * If a platform hasn't been transitioned to atomic watermarks yet,
5155          * we'll continue to update watermarks the old way, if flags tell
5156          * us to.
5157          */
5158         if (dev_priv->display.initial_watermarks != NULL)
5159                 dev_priv->display.initial_watermarks(pipe_config);
5160         else if (pipe_config->update_wm_pre)
5161                 intel_update_watermarks(&crtc->base);
5162 }
5163
5164 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5165 {
5166         struct drm_device *dev = crtc->dev;
5167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5168         struct drm_plane *p;
5169         int pipe = intel_crtc->pipe;
5170
5171         intel_crtc_dpms_overlay_disable(intel_crtc);
5172
5173         drm_for_each_plane_mask(p, dev, plane_mask)
5174                 to_intel_plane(p)->disable_plane(p, crtc);
5175
5176         /*
5177          * FIXME: Once we grow proper nuclear flip support out of this we need
5178          * to compute the mask of flip planes precisely. For the time being
5179          * consider this a flip to a NULL plane.
5180          */
5181         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5182 }
5183
5184 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5185                                           struct intel_crtc_state *crtc_state,
5186                                           struct drm_atomic_state *old_state)
5187 {
5188         struct drm_connector_state *old_conn_state;
5189         struct drm_connector *conn;
5190         int i;
5191
5192         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5193                 struct drm_connector_state *conn_state = conn->state;
5194                 struct intel_encoder *encoder =
5195                         to_intel_encoder(conn_state->best_encoder);
5196
5197                 if (conn_state->crtc != crtc)
5198                         continue;
5199
5200                 if (encoder->pre_pll_enable)
5201                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5202         }
5203 }
5204
5205 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5206                                       struct intel_crtc_state *crtc_state,
5207                                       struct drm_atomic_state *old_state)
5208 {
5209         struct drm_connector_state *old_conn_state;
5210         struct drm_connector *conn;
5211         int i;
5212
5213         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5214                 struct drm_connector_state *conn_state = conn->state;
5215                 struct intel_encoder *encoder =
5216                         to_intel_encoder(conn_state->best_encoder);
5217
5218                 if (conn_state->crtc != crtc)
5219                         continue;
5220
5221                 if (encoder->pre_enable)
5222                         encoder->pre_enable(encoder, crtc_state, conn_state);
5223         }
5224 }
5225
5226 static void intel_encoders_enable(struct drm_crtc *crtc,
5227                                   struct intel_crtc_state *crtc_state,
5228                                   struct drm_atomic_state *old_state)
5229 {
5230         struct drm_connector_state *old_conn_state;
5231         struct drm_connector *conn;
5232         int i;
5233
5234         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5235                 struct drm_connector_state *conn_state = conn->state;
5236                 struct intel_encoder *encoder =
5237                         to_intel_encoder(conn_state->best_encoder);
5238
5239                 if (conn_state->crtc != crtc)
5240                         continue;
5241
5242                 encoder->enable(encoder, crtc_state, conn_state);
5243                 intel_opregion_notify_encoder(encoder, true);
5244         }
5245 }
5246
5247 static void intel_encoders_disable(struct drm_crtc *crtc,
5248                                    struct intel_crtc_state *old_crtc_state,
5249                                    struct drm_atomic_state *old_state)
5250 {
5251         struct drm_connector_state *old_conn_state;
5252         struct drm_connector *conn;
5253         int i;
5254
5255         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5256                 struct intel_encoder *encoder =
5257                         to_intel_encoder(old_conn_state->best_encoder);
5258
5259                 if (old_conn_state->crtc != crtc)
5260                         continue;
5261
5262                 intel_opregion_notify_encoder(encoder, false);
5263                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5264         }
5265 }
5266
5267 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5268                                         struct intel_crtc_state *old_crtc_state,
5269                                         struct drm_atomic_state *old_state)
5270 {
5271         struct drm_connector_state *old_conn_state;
5272         struct drm_connector *conn;
5273         int i;
5274
5275         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5276                 struct intel_encoder *encoder =
5277                         to_intel_encoder(old_conn_state->best_encoder);
5278
5279                 if (old_conn_state->crtc != crtc)
5280                         continue;
5281
5282                 if (encoder->post_disable)
5283                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5284         }
5285 }
5286
5287 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5288                                             struct intel_crtc_state *old_crtc_state,
5289                                             struct drm_atomic_state *old_state)
5290 {
5291         struct drm_connector_state *old_conn_state;
5292         struct drm_connector *conn;
5293         int i;
5294
5295         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5296                 struct intel_encoder *encoder =
5297                         to_intel_encoder(old_conn_state->best_encoder);
5298
5299                 if (old_conn_state->crtc != crtc)
5300                         continue;
5301
5302                 if (encoder->post_pll_disable)
5303                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5304         }
5305 }
5306
5307 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5308                                  struct drm_atomic_state *old_state)
5309 {
5310         struct drm_crtc *crtc = pipe_config->base.crtc;
5311         struct drm_device *dev = crtc->dev;
5312         struct drm_i915_private *dev_priv = to_i915(dev);
5313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5314         int pipe = intel_crtc->pipe;
5315
5316         if (WARN_ON(intel_crtc->active))
5317                 return;
5318
5319         /*
5320          * Sometimes spurious CPU pipe underruns happen during FDI
5321          * training, at least with VGA+HDMI cloning. Suppress them.
5322          *
5323          * On ILK we get an occasional spurious CPU pipe underruns
5324          * between eDP port A enable and vdd enable. Also PCH port
5325          * enable seems to result in the occasional CPU pipe underrun.
5326          *
5327          * Spurious PCH underruns also occur during PCH enabling.
5328          */
5329         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5330                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5331         if (intel_crtc->config->has_pch_encoder)
5332                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5333
5334         if (intel_crtc->config->has_pch_encoder)
5335                 intel_prepare_shared_dpll(intel_crtc);
5336
5337         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5338                 intel_dp_set_m_n(intel_crtc, M1_N1);
5339
5340         intel_set_pipe_timings(intel_crtc);
5341         intel_set_pipe_src_size(intel_crtc);
5342
5343         if (intel_crtc->config->has_pch_encoder) {
5344                 intel_cpu_transcoder_set_m_n(intel_crtc,
5345                                      &intel_crtc->config->fdi_m_n, NULL);
5346         }
5347
5348         ironlake_set_pipeconf(crtc);
5349
5350         intel_crtc->active = true;
5351
5352         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5353
5354         if (intel_crtc->config->has_pch_encoder) {
5355                 /* Note: FDI PLL enabling _must_ be done before we enable the
5356                  * cpu pipes, hence this is separate from all the other fdi/pch
5357                  * enabling. */
5358                 ironlake_fdi_pll_enable(intel_crtc);
5359         } else {
5360                 assert_fdi_tx_disabled(dev_priv, pipe);
5361                 assert_fdi_rx_disabled(dev_priv, pipe);
5362         }
5363
5364         ironlake_pfit_enable(intel_crtc);
5365
5366         /*
5367          * On ILK+ LUT must be loaded before the pipe is running but with
5368          * clocks enabled
5369          */
5370         intel_color_load_luts(&pipe_config->base);
5371
5372         if (dev_priv->display.initial_watermarks != NULL)
5373                 dev_priv->display.initial_watermarks(intel_crtc->config);
5374         intel_enable_pipe(intel_crtc);
5375
5376         if (intel_crtc->config->has_pch_encoder)
5377                 ironlake_pch_enable(crtc);
5378
5379         assert_vblank_disabled(crtc);
5380         drm_crtc_vblank_on(crtc);
5381
5382         intel_encoders_enable(crtc, pipe_config, old_state);
5383
5384         if (HAS_PCH_CPT(dev))
5385                 cpt_verify_modeset(dev, intel_crtc->pipe);
5386
5387         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5388         if (intel_crtc->config->has_pch_encoder)
5389                 intel_wait_for_vblank(dev, pipe);
5390         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5391         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5392 }
5393
5394 /* IPS only exists on ULT machines and is tied to pipe A. */
5395 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5396 {
5397         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5398 }
5399
5400 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5401                                 struct drm_atomic_state *old_state)
5402 {
5403         struct drm_crtc *crtc = pipe_config->base.crtc;
5404         struct drm_device *dev = crtc->dev;
5405         struct drm_i915_private *dev_priv = to_i915(dev);
5406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5407         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5408         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5409
5410         if (WARN_ON(intel_crtc->active))
5411                 return;
5412
5413         if (intel_crtc->config->has_pch_encoder)
5414                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5415                                                       false);
5416
5417         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5418
5419         if (intel_crtc->config->shared_dpll)
5420                 intel_enable_shared_dpll(intel_crtc);
5421
5422         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5423                 intel_dp_set_m_n(intel_crtc, M1_N1);
5424
5425         if (!transcoder_is_dsi(cpu_transcoder))
5426                 intel_set_pipe_timings(intel_crtc);
5427
5428         intel_set_pipe_src_size(intel_crtc);
5429
5430         if (cpu_transcoder != TRANSCODER_EDP &&
5431             !transcoder_is_dsi(cpu_transcoder)) {
5432                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5433                            intel_crtc->config->pixel_multiplier - 1);
5434         }
5435
5436         if (intel_crtc->config->has_pch_encoder) {
5437                 intel_cpu_transcoder_set_m_n(intel_crtc,
5438                                      &intel_crtc->config->fdi_m_n, NULL);
5439         }
5440
5441         if (!transcoder_is_dsi(cpu_transcoder))
5442                 haswell_set_pipeconf(crtc);
5443
5444         haswell_set_pipemisc(crtc);
5445
5446         intel_color_set_csc(&pipe_config->base);
5447
5448         intel_crtc->active = true;
5449
5450         if (intel_crtc->config->has_pch_encoder)
5451                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5452         else
5453                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5454
5455         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5456
5457         if (intel_crtc->config->has_pch_encoder)
5458                 dev_priv->display.fdi_link_train(crtc);
5459
5460         if (!transcoder_is_dsi(cpu_transcoder))
5461                 intel_ddi_enable_pipe_clock(intel_crtc);
5462
5463         if (INTEL_INFO(dev)->gen >= 9)
5464                 skylake_pfit_enable(intel_crtc);
5465         else
5466                 ironlake_pfit_enable(intel_crtc);
5467
5468         /*
5469          * On ILK+ LUT must be loaded before the pipe is running but with
5470          * clocks enabled
5471          */
5472         intel_color_load_luts(&pipe_config->base);
5473
5474         intel_ddi_set_pipe_settings(crtc);
5475         if (!transcoder_is_dsi(cpu_transcoder))
5476                 intel_ddi_enable_transcoder_func(crtc);
5477
5478         if (dev_priv->display.initial_watermarks != NULL)
5479                 dev_priv->display.initial_watermarks(pipe_config);
5480         else
5481                 intel_update_watermarks(crtc);
5482
5483         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5484         if (!transcoder_is_dsi(cpu_transcoder))
5485                 intel_enable_pipe(intel_crtc);
5486
5487         if (intel_crtc->config->has_pch_encoder)
5488                 lpt_pch_enable(crtc);
5489
5490         if (intel_crtc->config->dp_encoder_is_mst)
5491                 intel_ddi_set_vc_payload_alloc(crtc, true);
5492
5493         assert_vblank_disabled(crtc);
5494         drm_crtc_vblank_on(crtc);
5495
5496         intel_encoders_enable(crtc, pipe_config, old_state);
5497
5498         if (intel_crtc->config->has_pch_encoder) {
5499                 intel_wait_for_vblank(dev, pipe);
5500                 intel_wait_for_vblank(dev, pipe);
5501                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5502                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5503                                                       true);
5504         }
5505
5506         /* If we change the relative order between pipe/planes enabling, we need
5507          * to change the workaround. */
5508         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5509         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5510                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5511                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5512         }
5513 }
5514
5515 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5516 {
5517         struct drm_device *dev = crtc->base.dev;
5518         struct drm_i915_private *dev_priv = to_i915(dev);
5519         int pipe = crtc->pipe;
5520
5521         /* To avoid upsetting the power well on haswell only disable the pfit if
5522          * it's in use. The hw state code will make sure we get this right. */
5523         if (force || crtc->config->pch_pfit.enabled) {
5524                 I915_WRITE(PF_CTL(pipe), 0);
5525                 I915_WRITE(PF_WIN_POS(pipe), 0);
5526                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5527         }
5528 }
5529
5530 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5531                                   struct drm_atomic_state *old_state)
5532 {
5533         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5534         struct drm_device *dev = crtc->dev;
5535         struct drm_i915_private *dev_priv = to_i915(dev);
5536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5537         int pipe = intel_crtc->pipe;
5538
5539         /*
5540          * Sometimes spurious CPU pipe underruns happen when the
5541          * pipe is already disabled, but FDI RX/TX is still enabled.
5542          * Happens at least with VGA+HDMI cloning. Suppress them.
5543          */
5544         if (intel_crtc->config->has_pch_encoder) {
5545                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5546                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5547         }
5548
5549         intel_encoders_disable(crtc, old_crtc_state, old_state);
5550
5551         drm_crtc_vblank_off(crtc);
5552         assert_vblank_disabled(crtc);
5553
5554         intel_disable_pipe(intel_crtc);
5555
5556         ironlake_pfit_disable(intel_crtc, false);
5557
5558         if (intel_crtc->config->has_pch_encoder)
5559                 ironlake_fdi_disable(crtc);
5560
5561         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5562
5563         if (intel_crtc->config->has_pch_encoder) {
5564                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5565
5566                 if (HAS_PCH_CPT(dev)) {
5567                         i915_reg_t reg;
5568                         u32 temp;
5569
5570                         /* disable TRANS_DP_CTL */
5571                         reg = TRANS_DP_CTL(pipe);
5572                         temp = I915_READ(reg);
5573                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5574                                   TRANS_DP_PORT_SEL_MASK);
5575                         temp |= TRANS_DP_PORT_SEL_NONE;
5576                         I915_WRITE(reg, temp);
5577
5578                         /* disable DPLL_SEL */
5579                         temp = I915_READ(PCH_DPLL_SEL);
5580                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5581                         I915_WRITE(PCH_DPLL_SEL, temp);
5582                 }
5583
5584                 ironlake_fdi_pll_disable(intel_crtc);
5585         }
5586
5587         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5588         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5589 }
5590
5591 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5592                                  struct drm_atomic_state *old_state)
5593 {
5594         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5595         struct drm_device *dev = crtc->dev;
5596         struct drm_i915_private *dev_priv = to_i915(dev);
5597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5598         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5599
5600         if (intel_crtc->config->has_pch_encoder)
5601                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5602                                                       false);
5603
5604         intel_encoders_disable(crtc, old_crtc_state, old_state);
5605
5606         drm_crtc_vblank_off(crtc);
5607         assert_vblank_disabled(crtc);
5608
5609         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5610         if (!transcoder_is_dsi(cpu_transcoder))
5611                 intel_disable_pipe(intel_crtc);
5612
5613         if (intel_crtc->config->dp_encoder_is_mst)
5614                 intel_ddi_set_vc_payload_alloc(crtc, false);
5615
5616         if (!transcoder_is_dsi(cpu_transcoder))
5617                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5618
5619         if (INTEL_INFO(dev)->gen >= 9)
5620                 skylake_scaler_disable(intel_crtc);
5621         else
5622                 ironlake_pfit_disable(intel_crtc, false);
5623
5624         if (!transcoder_is_dsi(cpu_transcoder))
5625                 intel_ddi_disable_pipe_clock(intel_crtc);
5626
5627         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5628
5629         if (old_crtc_state->has_pch_encoder)
5630                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5631                                                       true);
5632 }
5633
5634 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5635 {
5636         struct drm_device *dev = crtc->base.dev;
5637         struct drm_i915_private *dev_priv = to_i915(dev);
5638         struct intel_crtc_state *pipe_config = crtc->config;
5639
5640         if (!pipe_config->gmch_pfit.control)
5641                 return;
5642
5643         /*
5644          * The panel fitter should only be adjusted whilst the pipe is disabled,
5645          * according to register description and PRM.
5646          */
5647         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5648         assert_pipe_disabled(dev_priv, crtc->pipe);
5649
5650         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5651         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5652
5653         /* Border color in case we don't scale up to the full screen. Black by
5654          * default, change to something else for debugging. */
5655         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5656 }
5657
5658 static enum intel_display_power_domain port_to_power_domain(enum port port)
5659 {
5660         switch (port) {
5661         case PORT_A:
5662                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5663         case PORT_B:
5664                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5665         case PORT_C:
5666                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5667         case PORT_D:
5668                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5669         case PORT_E:
5670                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5671         default:
5672                 MISSING_CASE(port);
5673                 return POWER_DOMAIN_PORT_OTHER;
5674         }
5675 }
5676
5677 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5678 {
5679         switch (port) {
5680         case PORT_A:
5681                 return POWER_DOMAIN_AUX_A;
5682         case PORT_B:
5683                 return POWER_DOMAIN_AUX_B;
5684         case PORT_C:
5685                 return POWER_DOMAIN_AUX_C;
5686         case PORT_D:
5687                 return POWER_DOMAIN_AUX_D;
5688         case PORT_E:
5689                 /* FIXME: Check VBT for actual wiring of PORT E */
5690                 return POWER_DOMAIN_AUX_D;
5691         default:
5692                 MISSING_CASE(port);
5693                 return POWER_DOMAIN_AUX_A;
5694         }
5695 }
5696
5697 enum intel_display_power_domain
5698 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5699 {
5700         struct drm_device *dev = intel_encoder->base.dev;
5701         struct intel_digital_port *intel_dig_port;
5702
5703         switch (intel_encoder->type) {
5704         case INTEL_OUTPUT_UNKNOWN:
5705                 /* Only DDI platforms should ever use this output type */
5706                 WARN_ON_ONCE(!HAS_DDI(dev));
5707         case INTEL_OUTPUT_DP:
5708         case INTEL_OUTPUT_HDMI:
5709         case INTEL_OUTPUT_EDP:
5710                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5711                 return port_to_power_domain(intel_dig_port->port);
5712         case INTEL_OUTPUT_DP_MST:
5713                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5714                 return port_to_power_domain(intel_dig_port->port);
5715         case INTEL_OUTPUT_ANALOG:
5716                 return POWER_DOMAIN_PORT_CRT;
5717         case INTEL_OUTPUT_DSI:
5718                 return POWER_DOMAIN_PORT_DSI;
5719         default:
5720                 return POWER_DOMAIN_PORT_OTHER;
5721         }
5722 }
5723
5724 enum intel_display_power_domain
5725 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5726 {
5727         struct drm_device *dev = intel_encoder->base.dev;
5728         struct intel_digital_port *intel_dig_port;
5729
5730         switch (intel_encoder->type) {
5731         case INTEL_OUTPUT_UNKNOWN:
5732         case INTEL_OUTPUT_HDMI:
5733                 /*
5734                  * Only DDI platforms should ever use these output types.
5735                  * We can get here after the HDMI detect code has already set
5736                  * the type of the shared encoder. Since we can't be sure
5737                  * what's the status of the given connectors, play safe and
5738                  * run the DP detection too.
5739                  */
5740                 WARN_ON_ONCE(!HAS_DDI(dev));
5741         case INTEL_OUTPUT_DP:
5742         case INTEL_OUTPUT_EDP:
5743                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5744                 return port_to_aux_power_domain(intel_dig_port->port);
5745         case INTEL_OUTPUT_DP_MST:
5746                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5747                 return port_to_aux_power_domain(intel_dig_port->port);
5748         default:
5749                 MISSING_CASE(intel_encoder->type);
5750                 return POWER_DOMAIN_AUX_A;
5751         }
5752 }
5753
5754 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5755                                             struct intel_crtc_state *crtc_state)
5756 {
5757         struct drm_device *dev = crtc->dev;
5758         struct drm_encoder *encoder;
5759         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5760         enum pipe pipe = intel_crtc->pipe;
5761         unsigned long mask;
5762         enum transcoder transcoder = crtc_state->cpu_transcoder;
5763
5764         if (!crtc_state->base.active)
5765                 return 0;
5766
5767         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5768         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5769         if (crtc_state->pch_pfit.enabled ||
5770             crtc_state->pch_pfit.force_thru)
5771                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5772
5773         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5774                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5775
5776                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5777         }
5778
5779         if (crtc_state->shared_dpll)
5780                 mask |= BIT(POWER_DOMAIN_PLLS);
5781
5782         return mask;
5783 }
5784
5785 static unsigned long
5786 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5787                                struct intel_crtc_state *crtc_state)
5788 {
5789         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5791         enum intel_display_power_domain domain;
5792         unsigned long domains, new_domains, old_domains;
5793
5794         old_domains = intel_crtc->enabled_power_domains;
5795         intel_crtc->enabled_power_domains = new_domains =
5796                 get_crtc_power_domains(crtc, crtc_state);
5797
5798         domains = new_domains & ~old_domains;
5799
5800         for_each_power_domain(domain, domains)
5801                 intel_display_power_get(dev_priv, domain);
5802
5803         return old_domains & ~new_domains;
5804 }
5805
5806 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5807                                       unsigned long domains)
5808 {
5809         enum intel_display_power_domain domain;
5810
5811         for_each_power_domain(domain, domains)
5812                 intel_display_power_put(dev_priv, domain);
5813 }
5814
5815 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5816 {
5817         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5818
5819         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5820             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5821                 return max_cdclk_freq;
5822         else if (IS_CHERRYVIEW(dev_priv))
5823                 return max_cdclk_freq*95/100;
5824         else if (INTEL_INFO(dev_priv)->gen < 4)
5825                 return 2*max_cdclk_freq*90/100;
5826         else
5827                 return max_cdclk_freq*90/100;
5828 }
5829
5830 static int skl_calc_cdclk(int max_pixclk, int vco);
5831
5832 static void intel_update_max_cdclk(struct drm_device *dev)
5833 {
5834         struct drm_i915_private *dev_priv = to_i915(dev);
5835
5836         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5837                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5838                 int max_cdclk, vco;
5839
5840                 vco = dev_priv->skl_preferred_vco_freq;
5841                 WARN_ON(vco != 8100000 && vco != 8640000);
5842
5843                 /*
5844                  * Use the lower (vco 8640) cdclk values as a
5845                  * first guess. skl_calc_cdclk() will correct it
5846                  * if the preferred vco is 8100 instead.
5847                  */
5848                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5849                         max_cdclk = 617143;
5850                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5851                         max_cdclk = 540000;
5852                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5853                         max_cdclk = 432000;
5854                 else
5855                         max_cdclk = 308571;
5856
5857                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5858         } else if (IS_BROXTON(dev)) {
5859                 dev_priv->max_cdclk_freq = 624000;
5860         } else if (IS_BROADWELL(dev))  {
5861                 /*
5862                  * FIXME with extra cooling we can allow
5863                  * 540 MHz for ULX and 675 Mhz for ULT.
5864                  * How can we know if extra cooling is
5865                  * available? PCI ID, VTB, something else?
5866                  */
5867                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5868                         dev_priv->max_cdclk_freq = 450000;
5869                 else if (IS_BDW_ULX(dev))
5870                         dev_priv->max_cdclk_freq = 450000;
5871                 else if (IS_BDW_ULT(dev))
5872                         dev_priv->max_cdclk_freq = 540000;
5873                 else
5874                         dev_priv->max_cdclk_freq = 675000;
5875         } else if (IS_CHERRYVIEW(dev)) {
5876                 dev_priv->max_cdclk_freq = 320000;
5877         } else if (IS_VALLEYVIEW(dev)) {
5878                 dev_priv->max_cdclk_freq = 400000;
5879         } else {
5880                 /* otherwise assume cdclk is fixed */
5881                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5882         }
5883
5884         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5885
5886         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5887                          dev_priv->max_cdclk_freq);
5888
5889         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5890                          dev_priv->max_dotclk_freq);
5891 }
5892
5893 static void intel_update_cdclk(struct drm_device *dev)
5894 {
5895         struct drm_i915_private *dev_priv = to_i915(dev);
5896
5897         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5898
5899         if (INTEL_GEN(dev_priv) >= 9)
5900                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5901                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5902                                  dev_priv->cdclk_pll.ref);
5903         else
5904                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5905                                  dev_priv->cdclk_freq);
5906
5907         /*
5908          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5909          * Programmng [sic] note: bit[9:2] should be programmed to the number
5910          * of cdclk that generates 4MHz reference clock freq which is used to
5911          * generate GMBus clock. This will vary with the cdclk freq.
5912          */
5913         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5914                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5915 }
5916
5917 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5918 static int skl_cdclk_decimal(int cdclk)
5919 {
5920         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5921 }
5922
5923 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5924 {
5925         int ratio;
5926
5927         if (cdclk == dev_priv->cdclk_pll.ref)
5928                 return 0;
5929
5930         switch (cdclk) {
5931         default:
5932                 MISSING_CASE(cdclk);
5933         case 144000:
5934         case 288000:
5935         case 384000:
5936         case 576000:
5937                 ratio = 60;
5938                 break;
5939         case 624000:
5940                 ratio = 65;
5941                 break;
5942         }
5943
5944         return dev_priv->cdclk_pll.ref * ratio;
5945 }
5946
5947 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5948 {
5949         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5950
5951         /* Timeout 200us */
5952         if (intel_wait_for_register(dev_priv,
5953                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5954                                     1))
5955                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5956
5957         dev_priv->cdclk_pll.vco = 0;
5958 }
5959
5960 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5961 {
5962         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5963         u32 val;
5964
5965         val = I915_READ(BXT_DE_PLL_CTL);
5966         val &= ~BXT_DE_PLL_RATIO_MASK;
5967         val |= BXT_DE_PLL_RATIO(ratio);
5968         I915_WRITE(BXT_DE_PLL_CTL, val);
5969
5970         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5971
5972         /* Timeout 200us */
5973         if (intel_wait_for_register(dev_priv,
5974                                     BXT_DE_PLL_ENABLE,
5975                                     BXT_DE_PLL_LOCK,
5976                                     BXT_DE_PLL_LOCK,
5977                                     1))
5978                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5979
5980         dev_priv->cdclk_pll.vco = vco;
5981 }
5982
5983 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5984 {
5985         u32 val, divider;
5986         int vco, ret;
5987
5988         vco = bxt_de_pll_vco(dev_priv, cdclk);
5989
5990         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5991
5992         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5993         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5994         case 8:
5995                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5996                 break;
5997         case 4:
5998                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5999                 break;
6000         case 3:
6001                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
6002                 break;
6003         case 2:
6004                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6005                 break;
6006         default:
6007                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6008                 WARN_ON(vco != 0);
6009
6010                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6011                 break;
6012         }
6013
6014         /* Inform power controller of upcoming frequency change */
6015         mutex_lock(&dev_priv->rps.hw_lock);
6016         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6017                                       0x80000000);
6018         mutex_unlock(&dev_priv->rps.hw_lock);
6019
6020         if (ret) {
6021                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6022                           ret, cdclk);
6023                 return;
6024         }
6025
6026         if (dev_priv->cdclk_pll.vco != 0 &&
6027             dev_priv->cdclk_pll.vco != vco)
6028                 bxt_de_pll_disable(dev_priv);
6029
6030         if (dev_priv->cdclk_pll.vco != vco)
6031                 bxt_de_pll_enable(dev_priv, vco);
6032
6033         val = divider | skl_cdclk_decimal(cdclk);
6034         /*
6035          * FIXME if only the cd2x divider needs changing, it could be done
6036          * without shutting off the pipe (if only one pipe is active).
6037          */
6038         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6039         /*
6040          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6041          * enable otherwise.
6042          */
6043         if (cdclk >= 500000)
6044                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6045         I915_WRITE(CDCLK_CTL, val);
6046
6047         mutex_lock(&dev_priv->rps.hw_lock);
6048         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6049                                       DIV_ROUND_UP(cdclk, 25000));
6050         mutex_unlock(&dev_priv->rps.hw_lock);
6051
6052         if (ret) {
6053                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6054                           ret, cdclk);
6055                 return;
6056         }
6057
6058         intel_update_cdclk(&dev_priv->drm);
6059 }
6060
6061 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6062 {
6063         u32 cdctl, expected;
6064
6065         intel_update_cdclk(&dev_priv->drm);
6066
6067         if (dev_priv->cdclk_pll.vco == 0 ||
6068             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6069                 goto sanitize;
6070
6071         /* DPLL okay; verify the cdclock
6072          *
6073          * Some BIOS versions leave an incorrect decimal frequency value and
6074          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6075          * so sanitize this register.
6076          */
6077         cdctl = I915_READ(CDCLK_CTL);
6078         /*
6079          * Let's ignore the pipe field, since BIOS could have configured the
6080          * dividers both synching to an active pipe, or asynchronously
6081          * (PIPE_NONE).
6082          */
6083         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6084
6085         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6086                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6087         /*
6088          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6089          * enable otherwise.
6090          */
6091         if (dev_priv->cdclk_freq >= 500000)
6092                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6093
6094         if (cdctl == expected)
6095                 /* All well; nothing to sanitize */
6096                 return;
6097
6098 sanitize:
6099         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6100
6101         /* force cdclk programming */
6102         dev_priv->cdclk_freq = 0;
6103
6104         /* force full PLL disable + enable */
6105         dev_priv->cdclk_pll.vco = -1;
6106 }
6107
6108 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6109 {
6110         bxt_sanitize_cdclk(dev_priv);
6111
6112         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6113                 return;
6114
6115         /*
6116          * FIXME:
6117          * - The initial CDCLK needs to be read from VBT.
6118          *   Need to make this change after VBT has changes for BXT.
6119          */
6120         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6121 }
6122
6123 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6124 {
6125         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6126 }
6127
6128 static int skl_calc_cdclk(int max_pixclk, int vco)
6129 {
6130         if (vco == 8640000) {
6131                 if (max_pixclk > 540000)
6132                         return 617143;
6133                 else if (max_pixclk > 432000)
6134                         return 540000;
6135                 else if (max_pixclk > 308571)
6136                         return 432000;
6137                 else
6138                         return 308571;
6139         } else {
6140                 if (max_pixclk > 540000)
6141                         return 675000;
6142                 else if (max_pixclk > 450000)
6143                         return 540000;
6144                 else if (max_pixclk > 337500)
6145                         return 450000;
6146                 else
6147                         return 337500;
6148         }
6149 }
6150
6151 static void
6152 skl_dpll0_update(struct drm_i915_private *dev_priv)
6153 {
6154         u32 val;
6155
6156         dev_priv->cdclk_pll.ref = 24000;
6157         dev_priv->cdclk_pll.vco = 0;
6158
6159         val = I915_READ(LCPLL1_CTL);
6160         if ((val & LCPLL_PLL_ENABLE) == 0)
6161                 return;
6162
6163         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6164                 return;
6165
6166         val = I915_READ(DPLL_CTRL1);
6167
6168         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6169                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6170                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6171                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6172                 return;
6173
6174         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6175         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6176         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6177         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6178         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6179                 dev_priv->cdclk_pll.vco = 8100000;
6180                 break;
6181         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6182         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6183                 dev_priv->cdclk_pll.vco = 8640000;
6184                 break;
6185         default:
6186                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6187                 break;
6188         }
6189 }
6190
6191 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6192 {
6193         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6194
6195         dev_priv->skl_preferred_vco_freq = vco;
6196
6197         if (changed)
6198                 intel_update_max_cdclk(&dev_priv->drm);
6199 }
6200
6201 static void
6202 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6203 {
6204         int min_cdclk = skl_calc_cdclk(0, vco);
6205         u32 val;
6206
6207         WARN_ON(vco != 8100000 && vco != 8640000);
6208
6209         /* select the minimum CDCLK before enabling DPLL 0 */
6210         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6211         I915_WRITE(CDCLK_CTL, val);
6212         POSTING_READ(CDCLK_CTL);
6213
6214         /*
6215          * We always enable DPLL0 with the lowest link rate possible, but still
6216          * taking into account the VCO required to operate the eDP panel at the
6217          * desired frequency. The usual DP link rates operate with a VCO of
6218          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6219          * The modeset code is responsible for the selection of the exact link
6220          * rate later on, with the constraint of choosing a frequency that
6221          * works with vco.
6222          */
6223         val = I915_READ(DPLL_CTRL1);
6224
6225         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6226                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6227         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6228         if (vco == 8640000)
6229                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6230                                             SKL_DPLL0);
6231         else
6232                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6233                                             SKL_DPLL0);
6234
6235         I915_WRITE(DPLL_CTRL1, val);
6236         POSTING_READ(DPLL_CTRL1);
6237
6238         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6239
6240         if (intel_wait_for_register(dev_priv,
6241                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6242                                     5))
6243                 DRM_ERROR("DPLL0 not locked\n");
6244
6245         dev_priv->cdclk_pll.vco = vco;
6246
6247         /* We'll want to keep using the current vco from now on. */
6248         skl_set_preferred_cdclk_vco(dev_priv, vco);
6249 }
6250
6251 static void
6252 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6253 {
6254         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6255         if (intel_wait_for_register(dev_priv,
6256                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6257                                    1))
6258                 DRM_ERROR("Couldn't disable DPLL0\n");
6259
6260         dev_priv->cdclk_pll.vco = 0;
6261 }
6262
6263 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6264 {
6265         int ret;
6266         u32 val;
6267
6268         /* inform PCU we want to change CDCLK */
6269         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6270         mutex_lock(&dev_priv->rps.hw_lock);
6271         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6272         mutex_unlock(&dev_priv->rps.hw_lock);
6273
6274         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6275 }
6276
6277 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6278 {
6279         return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6280 }
6281
6282 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6283 {
6284         struct drm_device *dev = &dev_priv->drm;
6285         u32 freq_select, pcu_ack;
6286
6287         WARN_ON((cdclk == 24000) != (vco == 0));
6288
6289         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6290
6291         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6292                 DRM_ERROR("failed to inform PCU about cdclk change\n");
6293                 return;
6294         }
6295
6296         /* set CDCLK_CTL */
6297         switch (cdclk) {
6298         case 450000:
6299         case 432000:
6300                 freq_select = CDCLK_FREQ_450_432;
6301                 pcu_ack = 1;
6302                 break;
6303         case 540000:
6304                 freq_select = CDCLK_FREQ_540;
6305                 pcu_ack = 2;
6306                 break;
6307         case 308571:
6308         case 337500:
6309         default:
6310                 freq_select = CDCLK_FREQ_337_308;
6311                 pcu_ack = 0;
6312                 break;
6313         case 617143:
6314         case 675000:
6315                 freq_select = CDCLK_FREQ_675_617;
6316                 pcu_ack = 3;
6317                 break;
6318         }
6319
6320         if (dev_priv->cdclk_pll.vco != 0 &&
6321             dev_priv->cdclk_pll.vco != vco)
6322                 skl_dpll0_disable(dev_priv);
6323
6324         if (dev_priv->cdclk_pll.vco != vco)
6325                 skl_dpll0_enable(dev_priv, vco);
6326
6327         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6328         POSTING_READ(CDCLK_CTL);
6329
6330         /* inform PCU of the change */
6331         mutex_lock(&dev_priv->rps.hw_lock);
6332         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6333         mutex_unlock(&dev_priv->rps.hw_lock);
6334
6335         intel_update_cdclk(dev);
6336 }
6337
6338 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6339
6340 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6341 {
6342         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6343 }
6344
6345 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6346 {
6347         int cdclk, vco;
6348
6349         skl_sanitize_cdclk(dev_priv);
6350
6351         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6352                 /*
6353                  * Use the current vco as our initial
6354                  * guess as to what the preferred vco is.
6355                  */
6356                 if (dev_priv->skl_preferred_vco_freq == 0)
6357                         skl_set_preferred_cdclk_vco(dev_priv,
6358                                                     dev_priv->cdclk_pll.vco);
6359                 return;
6360         }
6361
6362         vco = dev_priv->skl_preferred_vco_freq;
6363         if (vco == 0)
6364                 vco = 8100000;
6365         cdclk = skl_calc_cdclk(0, vco);
6366
6367         skl_set_cdclk(dev_priv, cdclk, vco);
6368 }
6369
6370 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6371 {
6372         uint32_t cdctl, expected;
6373
6374         /*
6375          * check if the pre-os intialized the display
6376          * There is SWF18 scratchpad register defined which is set by the
6377          * pre-os which can be used by the OS drivers to check the status
6378          */
6379         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6380                 goto sanitize;
6381
6382         intel_update_cdclk(&dev_priv->drm);
6383         /* Is PLL enabled and locked ? */
6384         if (dev_priv->cdclk_pll.vco == 0 ||
6385             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6386                 goto sanitize;
6387
6388         /* DPLL okay; verify the cdclock
6389          *
6390          * Noticed in some instances that the freq selection is correct but
6391          * decimal part is programmed wrong from BIOS where pre-os does not
6392          * enable display. Verify the same as well.
6393          */
6394         cdctl = I915_READ(CDCLK_CTL);
6395         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6396                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6397         if (cdctl == expected)
6398                 /* All well; nothing to sanitize */
6399                 return;
6400
6401 sanitize:
6402         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6403
6404         /* force cdclk programming */
6405         dev_priv->cdclk_freq = 0;
6406         /* force full PLL disable + enable */
6407         dev_priv->cdclk_pll.vco = -1;
6408 }
6409
6410 /* Adjust CDclk dividers to allow high res or save power if possible */
6411 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6412 {
6413         struct drm_i915_private *dev_priv = to_i915(dev);
6414         u32 val, cmd;
6415
6416         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6417                                         != dev_priv->cdclk_freq);
6418
6419         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6420                 cmd = 2;
6421         else if (cdclk == 266667)
6422                 cmd = 1;
6423         else
6424                 cmd = 0;
6425
6426         mutex_lock(&dev_priv->rps.hw_lock);
6427         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6428         val &= ~DSPFREQGUAR_MASK;
6429         val |= (cmd << DSPFREQGUAR_SHIFT);
6430         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6431         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6432                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6433                      50)) {
6434                 DRM_ERROR("timed out waiting for CDclk change\n");
6435         }
6436         mutex_unlock(&dev_priv->rps.hw_lock);
6437
6438         mutex_lock(&dev_priv->sb_lock);
6439
6440         if (cdclk == 400000) {
6441                 u32 divider;
6442
6443                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6444
6445                 /* adjust cdclk divider */
6446                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6447                 val &= ~CCK_FREQUENCY_VALUES;
6448                 val |= divider;
6449                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6450
6451                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6452                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6453                              50))
6454                         DRM_ERROR("timed out waiting for CDclk change\n");
6455         }
6456
6457         /* adjust self-refresh exit latency value */
6458         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6459         val &= ~0x7f;
6460
6461         /*
6462          * For high bandwidth configs, we set a higher latency in the bunit
6463          * so that the core display fetch happens in time to avoid underruns.
6464          */
6465         if (cdclk == 400000)
6466                 val |= 4500 / 250; /* 4.5 usec */
6467         else
6468                 val |= 3000 / 250; /* 3.0 usec */
6469         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6470
6471         mutex_unlock(&dev_priv->sb_lock);
6472
6473         intel_update_cdclk(dev);
6474 }
6475
6476 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6477 {
6478         struct drm_i915_private *dev_priv = to_i915(dev);
6479         u32 val, cmd;
6480
6481         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6482                                                 != dev_priv->cdclk_freq);
6483
6484         switch (cdclk) {
6485         case 333333:
6486         case 320000:
6487         case 266667:
6488         case 200000:
6489                 break;
6490         default:
6491                 MISSING_CASE(cdclk);
6492                 return;
6493         }
6494
6495         /*
6496          * Specs are full of misinformation, but testing on actual
6497          * hardware has shown that we just need to write the desired
6498          * CCK divider into the Punit register.
6499          */
6500         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6501
6502         mutex_lock(&dev_priv->rps.hw_lock);
6503         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6504         val &= ~DSPFREQGUAR_MASK_CHV;
6505         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6506         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6507         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6508                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6509                      50)) {
6510                 DRM_ERROR("timed out waiting for CDclk change\n");
6511         }
6512         mutex_unlock(&dev_priv->rps.hw_lock);
6513
6514         intel_update_cdclk(dev);
6515 }
6516
6517 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6518                                  int max_pixclk)
6519 {
6520         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6521         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6522
6523         /*
6524          * Really only a few cases to deal with, as only 4 CDclks are supported:
6525          *   200MHz
6526          *   267MHz
6527          *   320/333MHz (depends on HPLL freq)
6528          *   400MHz (VLV only)
6529          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6530          * of the lower bin and adjust if needed.
6531          *
6532          * We seem to get an unstable or solid color picture at 200MHz.
6533          * Not sure what's wrong. For now use 200MHz only when all pipes
6534          * are off.
6535          */
6536         if (!IS_CHERRYVIEW(dev_priv) &&
6537             max_pixclk > freq_320*limit/100)
6538                 return 400000;
6539         else if (max_pixclk > 266667*limit/100)
6540                 return freq_320;
6541         else if (max_pixclk > 0)
6542                 return 266667;
6543         else
6544                 return 200000;
6545 }
6546
6547 static int bxt_calc_cdclk(int max_pixclk)
6548 {
6549         if (max_pixclk > 576000)
6550                 return 624000;
6551         else if (max_pixclk > 384000)
6552                 return 576000;
6553         else if (max_pixclk > 288000)
6554                 return 384000;
6555         else if (max_pixclk > 144000)
6556                 return 288000;
6557         else
6558                 return 144000;
6559 }
6560
6561 /* Compute the max pixel clock for new configuration. */
6562 static int intel_mode_max_pixclk(struct drm_device *dev,
6563                                  struct drm_atomic_state *state)
6564 {
6565         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6566         struct drm_i915_private *dev_priv = to_i915(dev);
6567         struct drm_crtc *crtc;
6568         struct drm_crtc_state *crtc_state;
6569         unsigned max_pixclk = 0, i;
6570         enum pipe pipe;
6571
6572         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6573                sizeof(intel_state->min_pixclk));
6574
6575         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6576                 int pixclk = 0;
6577
6578                 if (crtc_state->enable)
6579                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6580
6581                 intel_state->min_pixclk[i] = pixclk;
6582         }
6583
6584         for_each_pipe(dev_priv, pipe)
6585                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6586
6587         return max_pixclk;
6588 }
6589
6590 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6591 {
6592         struct drm_device *dev = state->dev;
6593         struct drm_i915_private *dev_priv = to_i915(dev);
6594         int max_pixclk = intel_mode_max_pixclk(dev, state);
6595         struct intel_atomic_state *intel_state =
6596                 to_intel_atomic_state(state);
6597
6598         intel_state->cdclk = intel_state->dev_cdclk =
6599                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6600
6601         if (!intel_state->active_crtcs)
6602                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6603
6604         return 0;
6605 }
6606
6607 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6608 {
6609         int max_pixclk = ilk_max_pixel_rate(state);
6610         struct intel_atomic_state *intel_state =
6611                 to_intel_atomic_state(state);
6612
6613         intel_state->cdclk = intel_state->dev_cdclk =
6614                 bxt_calc_cdclk(max_pixclk);
6615
6616         if (!intel_state->active_crtcs)
6617                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6618
6619         return 0;
6620 }
6621
6622 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6623 {
6624         unsigned int credits, default_credits;
6625
6626         if (IS_CHERRYVIEW(dev_priv))
6627                 default_credits = PFI_CREDIT(12);
6628         else
6629                 default_credits = PFI_CREDIT(8);
6630
6631         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6632                 /* CHV suggested value is 31 or 63 */
6633                 if (IS_CHERRYVIEW(dev_priv))
6634                         credits = PFI_CREDIT_63;
6635                 else
6636                         credits = PFI_CREDIT(15);
6637         } else {
6638                 credits = default_credits;
6639         }
6640
6641         /*
6642          * WA - write default credits before re-programming
6643          * FIXME: should we also set the resend bit here?
6644          */
6645         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6646                    default_credits);
6647
6648         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6649                    credits | PFI_CREDIT_RESEND);
6650
6651         /*
6652          * FIXME is this guaranteed to clear
6653          * immediately or should we poll for it?
6654          */
6655         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6656 }
6657
6658 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6659 {
6660         struct drm_device *dev = old_state->dev;
6661         struct drm_i915_private *dev_priv = to_i915(dev);
6662         struct intel_atomic_state *old_intel_state =
6663                 to_intel_atomic_state(old_state);
6664         unsigned req_cdclk = old_intel_state->dev_cdclk;
6665
6666         /*
6667          * FIXME: We can end up here with all power domains off, yet
6668          * with a CDCLK frequency other than the minimum. To account
6669          * for this take the PIPE-A power domain, which covers the HW
6670          * blocks needed for the following programming. This can be
6671          * removed once it's guaranteed that we get here either with
6672          * the minimum CDCLK set, or the required power domains
6673          * enabled.
6674          */
6675         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6676
6677         if (IS_CHERRYVIEW(dev))
6678                 cherryview_set_cdclk(dev, req_cdclk);
6679         else
6680                 valleyview_set_cdclk(dev, req_cdclk);
6681
6682         vlv_program_pfi_credits(dev_priv);
6683
6684         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6685 }
6686
6687 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6688                                    struct drm_atomic_state *old_state)
6689 {
6690         struct drm_crtc *crtc = pipe_config->base.crtc;
6691         struct drm_device *dev = crtc->dev;
6692         struct drm_i915_private *dev_priv = to_i915(dev);
6693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6694         int pipe = intel_crtc->pipe;
6695
6696         if (WARN_ON(intel_crtc->active))
6697                 return;
6698
6699         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6700                 intel_dp_set_m_n(intel_crtc, M1_N1);
6701
6702         intel_set_pipe_timings(intel_crtc);
6703         intel_set_pipe_src_size(intel_crtc);
6704
6705         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6706                 struct drm_i915_private *dev_priv = to_i915(dev);
6707
6708                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6709                 I915_WRITE(CHV_CANVAS(pipe), 0);
6710         }
6711
6712         i9xx_set_pipeconf(intel_crtc);
6713
6714         intel_crtc->active = true;
6715
6716         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6717
6718         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6719
6720         if (IS_CHERRYVIEW(dev)) {
6721                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6722                 chv_enable_pll(intel_crtc, intel_crtc->config);
6723         } else {
6724                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6725                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6726         }
6727
6728         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6729
6730         i9xx_pfit_enable(intel_crtc);
6731
6732         intel_color_load_luts(&pipe_config->base);
6733
6734         intel_update_watermarks(crtc);
6735         intel_enable_pipe(intel_crtc);
6736
6737         assert_vblank_disabled(crtc);
6738         drm_crtc_vblank_on(crtc);
6739
6740         intel_encoders_enable(crtc, pipe_config, old_state);
6741 }
6742
6743 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6744 {
6745         struct drm_device *dev = crtc->base.dev;
6746         struct drm_i915_private *dev_priv = to_i915(dev);
6747
6748         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6749         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6750 }
6751
6752 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6753                              struct drm_atomic_state *old_state)
6754 {
6755         struct drm_crtc *crtc = pipe_config->base.crtc;
6756         struct drm_device *dev = crtc->dev;
6757         struct drm_i915_private *dev_priv = to_i915(dev);
6758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6759         enum pipe pipe = intel_crtc->pipe;
6760
6761         if (WARN_ON(intel_crtc->active))
6762                 return;
6763
6764         i9xx_set_pll_dividers(intel_crtc);
6765
6766         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6767                 intel_dp_set_m_n(intel_crtc, M1_N1);
6768
6769         intel_set_pipe_timings(intel_crtc);
6770         intel_set_pipe_src_size(intel_crtc);
6771
6772         i9xx_set_pipeconf(intel_crtc);
6773
6774         intel_crtc->active = true;
6775
6776         if (!IS_GEN2(dev))
6777                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6778
6779         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6780
6781         i9xx_enable_pll(intel_crtc);
6782
6783         i9xx_pfit_enable(intel_crtc);
6784
6785         intel_color_load_luts(&pipe_config->base);
6786
6787         intel_update_watermarks(crtc);
6788         intel_enable_pipe(intel_crtc);
6789
6790         assert_vblank_disabled(crtc);
6791         drm_crtc_vblank_on(crtc);
6792
6793         intel_encoders_enable(crtc, pipe_config, old_state);
6794 }
6795
6796 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6797 {
6798         struct drm_device *dev = crtc->base.dev;
6799         struct drm_i915_private *dev_priv = to_i915(dev);
6800
6801         if (!crtc->config->gmch_pfit.control)
6802                 return;
6803
6804         assert_pipe_disabled(dev_priv, crtc->pipe);
6805
6806         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6807                          I915_READ(PFIT_CONTROL));
6808         I915_WRITE(PFIT_CONTROL, 0);
6809 }
6810
6811 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6812                               struct drm_atomic_state *old_state)
6813 {
6814         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6815         struct drm_device *dev = crtc->dev;
6816         struct drm_i915_private *dev_priv = to_i915(dev);
6817         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6818         int pipe = intel_crtc->pipe;
6819
6820         /*
6821          * On gen2 planes are double buffered but the pipe isn't, so we must
6822          * wait for planes to fully turn off before disabling the pipe.
6823          */
6824         if (IS_GEN2(dev))
6825                 intel_wait_for_vblank(dev, pipe);
6826
6827         intel_encoders_disable(crtc, old_crtc_state, old_state);
6828
6829         drm_crtc_vblank_off(crtc);
6830         assert_vblank_disabled(crtc);
6831
6832         intel_disable_pipe(intel_crtc);
6833
6834         i9xx_pfit_disable(intel_crtc);
6835
6836         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6837
6838         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6839                 if (IS_CHERRYVIEW(dev))
6840                         chv_disable_pll(dev_priv, pipe);
6841                 else if (IS_VALLEYVIEW(dev))
6842                         vlv_disable_pll(dev_priv, pipe);
6843                 else
6844                         i9xx_disable_pll(intel_crtc);
6845         }
6846
6847         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6848
6849         if (!IS_GEN2(dev))
6850                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6851 }
6852
6853 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6854 {
6855         struct intel_encoder *encoder;
6856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6857         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6858         enum intel_display_power_domain domain;
6859         unsigned long domains;
6860         struct drm_atomic_state *state;
6861         struct intel_crtc_state *crtc_state;
6862         int ret;
6863
6864         if (!intel_crtc->active)
6865                 return;
6866
6867         if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6868                 WARN_ON(intel_crtc->flip_work);
6869
6870                 intel_pre_disable_primary_noatomic(crtc);
6871
6872                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6873                 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6874         }
6875
6876         state = drm_atomic_state_alloc(crtc->dev);
6877         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6878
6879         /* Everything's already locked, -EDEADLK can't happen. */
6880         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6881         ret = drm_atomic_add_affected_connectors(state, crtc);
6882
6883         WARN_ON(IS_ERR(crtc_state) || ret);
6884
6885         dev_priv->display.crtc_disable(crtc_state, state);
6886
6887         drm_atomic_state_put(state);
6888
6889         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6890                       crtc->base.id, crtc->name);
6891
6892         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6893         crtc->state->active = false;
6894         intel_crtc->active = false;
6895         crtc->enabled = false;
6896         crtc->state->connector_mask = 0;
6897         crtc->state->encoder_mask = 0;
6898
6899         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6900                 encoder->base.crtc = NULL;
6901
6902         intel_fbc_disable(intel_crtc);
6903         intel_update_watermarks(crtc);
6904         intel_disable_shared_dpll(intel_crtc);
6905
6906         domains = intel_crtc->enabled_power_domains;
6907         for_each_power_domain(domain, domains)
6908                 intel_display_power_put(dev_priv, domain);
6909         intel_crtc->enabled_power_domains = 0;
6910
6911         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6912         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6913 }
6914
6915 /*
6916  * turn all crtc's off, but do not adjust state
6917  * This has to be paired with a call to intel_modeset_setup_hw_state.
6918  */
6919 int intel_display_suspend(struct drm_device *dev)
6920 {
6921         struct drm_i915_private *dev_priv = to_i915(dev);
6922         struct drm_atomic_state *state;
6923         int ret;
6924
6925         state = drm_atomic_helper_suspend(dev);
6926         ret = PTR_ERR_OR_ZERO(state);
6927         if (ret)
6928                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6929         else
6930                 dev_priv->modeset_restore_state = state;
6931         return ret;
6932 }
6933
6934 void intel_encoder_destroy(struct drm_encoder *encoder)
6935 {
6936         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6937
6938         drm_encoder_cleanup(encoder);
6939         kfree(intel_encoder);
6940 }
6941
6942 /* Cross check the actual hw state with our own modeset state tracking (and it's
6943  * internal consistency). */
6944 static void intel_connector_verify_state(struct intel_connector *connector)
6945 {
6946         struct drm_crtc *crtc = connector->base.state->crtc;
6947
6948         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6949                       connector->base.base.id,
6950                       connector->base.name);
6951
6952         if (connector->get_hw_state(connector)) {
6953                 struct intel_encoder *encoder = connector->encoder;
6954                 struct drm_connector_state *conn_state = connector->base.state;
6955
6956                 I915_STATE_WARN(!crtc,
6957                          "connector enabled without attached crtc\n");
6958
6959                 if (!crtc)
6960                         return;
6961
6962                 I915_STATE_WARN(!crtc->state->active,
6963                       "connector is active, but attached crtc isn't\n");
6964
6965                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6966                         return;
6967
6968                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6969                         "atomic encoder doesn't match attached encoder\n");
6970
6971                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6972                         "attached encoder crtc differs from connector crtc\n");
6973         } else {
6974                 I915_STATE_WARN(crtc && crtc->state->active,
6975                         "attached crtc is active, but connector isn't\n");
6976                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6977                         "best encoder set without crtc!\n");
6978         }
6979 }
6980
6981 int intel_connector_init(struct intel_connector *connector)
6982 {
6983         drm_atomic_helper_connector_reset(&connector->base);
6984
6985         if (!connector->base.state)
6986                 return -ENOMEM;
6987
6988         return 0;
6989 }
6990
6991 struct intel_connector *intel_connector_alloc(void)
6992 {
6993         struct intel_connector *connector;
6994
6995         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6996         if (!connector)
6997                 return NULL;
6998
6999         if (intel_connector_init(connector) < 0) {
7000                 kfree(connector);
7001                 return NULL;
7002         }
7003
7004         return connector;
7005 }
7006
7007 /* Simple connector->get_hw_state implementation for encoders that support only
7008  * one connector and no cloning and hence the encoder state determines the state
7009  * of the connector. */
7010 bool intel_connector_get_hw_state(struct intel_connector *connector)
7011 {
7012         enum pipe pipe = 0;
7013         struct intel_encoder *encoder = connector->encoder;
7014
7015         return encoder->get_hw_state(encoder, &pipe);
7016 }
7017
7018 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7019 {
7020         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7021                 return crtc_state->fdi_lanes;
7022
7023         return 0;
7024 }
7025
7026 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7027                                      struct intel_crtc_state *pipe_config)
7028 {
7029         struct drm_atomic_state *state = pipe_config->base.state;
7030         struct intel_crtc *other_crtc;
7031         struct intel_crtc_state *other_crtc_state;
7032
7033         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7034                       pipe_name(pipe), pipe_config->fdi_lanes);
7035         if (pipe_config->fdi_lanes > 4) {
7036                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7037                               pipe_name(pipe), pipe_config->fdi_lanes);
7038                 return -EINVAL;
7039         }
7040
7041         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7042                 if (pipe_config->fdi_lanes > 2) {
7043                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7044                                       pipe_config->fdi_lanes);
7045                         return -EINVAL;
7046                 } else {
7047                         return 0;
7048                 }
7049         }
7050
7051         if (INTEL_INFO(dev)->num_pipes == 2)
7052                 return 0;
7053
7054         /* Ivybridge 3 pipe is really complicated */
7055         switch (pipe) {
7056         case PIPE_A:
7057                 return 0;
7058         case PIPE_B:
7059                 if (pipe_config->fdi_lanes <= 2)
7060                         return 0;
7061
7062                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
7063                 other_crtc_state =
7064                         intel_atomic_get_crtc_state(state, other_crtc);
7065                 if (IS_ERR(other_crtc_state))
7066                         return PTR_ERR(other_crtc_state);
7067
7068                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7069                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7070                                       pipe_name(pipe), pipe_config->fdi_lanes);
7071                         return -EINVAL;
7072                 }
7073                 return 0;
7074         case PIPE_C:
7075                 if (pipe_config->fdi_lanes > 2) {
7076                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7077                                       pipe_name(pipe), pipe_config->fdi_lanes);
7078                         return -EINVAL;
7079                 }
7080
7081                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
7082                 other_crtc_state =
7083                         intel_atomic_get_crtc_state(state, other_crtc);
7084                 if (IS_ERR(other_crtc_state))
7085                         return PTR_ERR(other_crtc_state);
7086
7087                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7088                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7089                         return -EINVAL;
7090                 }
7091                 return 0;
7092         default:
7093                 BUG();
7094         }
7095 }
7096
7097 #define RETRY 1
7098 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7099                                        struct intel_crtc_state *pipe_config)
7100 {
7101         struct drm_device *dev = intel_crtc->base.dev;
7102         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7103         int lane, link_bw, fdi_dotclock, ret;
7104         bool needs_recompute = false;
7105
7106 retry:
7107         /* FDI is a binary signal running at ~2.7GHz, encoding
7108          * each output octet as 10 bits. The actual frequency
7109          * is stored as a divider into a 100MHz clock, and the
7110          * mode pixel clock is stored in units of 1KHz.
7111          * Hence the bw of each lane in terms of the mode signal
7112          * is:
7113          */
7114         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7115
7116         fdi_dotclock = adjusted_mode->crtc_clock;
7117
7118         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7119                                            pipe_config->pipe_bpp);
7120
7121         pipe_config->fdi_lanes = lane;
7122
7123         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7124                                link_bw, &pipe_config->fdi_m_n);
7125
7126         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7127         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7128                 pipe_config->pipe_bpp -= 2*3;
7129                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7130                               pipe_config->pipe_bpp);
7131                 needs_recompute = true;
7132                 pipe_config->bw_constrained = true;
7133
7134                 goto retry;
7135         }
7136
7137         if (needs_recompute)
7138                 return RETRY;
7139
7140         return ret;
7141 }
7142
7143 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7144                                      struct intel_crtc_state *pipe_config)
7145 {
7146         if (pipe_config->pipe_bpp > 24)
7147                 return false;
7148
7149         /* HSW can handle pixel rate up to cdclk? */
7150         if (IS_HASWELL(dev_priv))
7151                 return true;
7152
7153         /*
7154          * We compare against max which means we must take
7155          * the increased cdclk requirement into account when
7156          * calculating the new cdclk.
7157          *
7158          * Should measure whether using a lower cdclk w/o IPS
7159          */
7160         return ilk_pipe_pixel_rate(pipe_config) <=
7161                 dev_priv->max_cdclk_freq * 95 / 100;
7162 }
7163
7164 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7165                                    struct intel_crtc_state *pipe_config)
7166 {
7167         struct drm_device *dev = crtc->base.dev;
7168         struct drm_i915_private *dev_priv = to_i915(dev);
7169
7170         pipe_config->ips_enabled = i915.enable_ips &&
7171                 hsw_crtc_supports_ips(crtc) &&
7172                 pipe_config_supports_ips(dev_priv, pipe_config);
7173 }
7174
7175 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7176 {
7177         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7178
7179         /* GDG double wide on either pipe, otherwise pipe A only */
7180         return INTEL_INFO(dev_priv)->gen < 4 &&
7181                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7182 }
7183
7184 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7185                                      struct intel_crtc_state *pipe_config)
7186 {
7187         struct drm_device *dev = crtc->base.dev;
7188         struct drm_i915_private *dev_priv = to_i915(dev);
7189         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7190         int clock_limit = dev_priv->max_dotclk_freq;
7191
7192         if (INTEL_INFO(dev)->gen < 4) {
7193                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7194
7195                 /*
7196                  * Enable double wide mode when the dot clock
7197                  * is > 90% of the (display) core speed.
7198                  */
7199                 if (intel_crtc_supports_double_wide(crtc) &&
7200                     adjusted_mode->crtc_clock > clock_limit) {
7201                         clock_limit = dev_priv->max_dotclk_freq;
7202                         pipe_config->double_wide = true;
7203                 }
7204         }
7205
7206         if (adjusted_mode->crtc_clock > clock_limit) {
7207                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7208                               adjusted_mode->crtc_clock, clock_limit,
7209                               yesno(pipe_config->double_wide));
7210                 return -EINVAL;
7211         }
7212
7213         /*
7214          * Pipe horizontal size must be even in:
7215          * - DVO ganged mode
7216          * - LVDS dual channel mode
7217          * - Double wide pipe
7218          */
7219         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7220              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7221                 pipe_config->pipe_src_w &= ~1;
7222
7223         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7224          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7225          */
7226         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
7227                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7228                 return -EINVAL;
7229
7230         if (HAS_IPS(dev))
7231                 hsw_compute_ips_config(crtc, pipe_config);
7232
7233         if (pipe_config->has_pch_encoder)
7234                 return ironlake_fdi_compute_config(crtc, pipe_config);
7235
7236         return 0;
7237 }
7238
7239 static int skylake_get_display_clock_speed(struct drm_device *dev)
7240 {
7241         struct drm_i915_private *dev_priv = to_i915(dev);
7242         uint32_t cdctl;
7243
7244         skl_dpll0_update(dev_priv);
7245
7246         if (dev_priv->cdclk_pll.vco == 0)
7247                 return dev_priv->cdclk_pll.ref;
7248
7249         cdctl = I915_READ(CDCLK_CTL);
7250
7251         if (dev_priv->cdclk_pll.vco == 8640000) {
7252                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7253                 case CDCLK_FREQ_450_432:
7254                         return 432000;
7255                 case CDCLK_FREQ_337_308:
7256                         return 308571;
7257                 case CDCLK_FREQ_540:
7258                         return 540000;
7259                 case CDCLK_FREQ_675_617:
7260                         return 617143;
7261                 default:
7262                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7263                 }
7264         } else {
7265                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7266                 case CDCLK_FREQ_450_432:
7267                         return 450000;
7268                 case CDCLK_FREQ_337_308:
7269                         return 337500;
7270                 case CDCLK_FREQ_540:
7271                         return 540000;
7272                 case CDCLK_FREQ_675_617:
7273                         return 675000;
7274                 default:
7275                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7276                 }
7277         }
7278
7279         return dev_priv->cdclk_pll.ref;
7280 }
7281
7282 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7283 {
7284         u32 val;
7285
7286         dev_priv->cdclk_pll.ref = 19200;
7287         dev_priv->cdclk_pll.vco = 0;
7288
7289         val = I915_READ(BXT_DE_PLL_ENABLE);
7290         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7291                 return;
7292
7293         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7294                 return;
7295
7296         val = I915_READ(BXT_DE_PLL_CTL);
7297         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7298                 dev_priv->cdclk_pll.ref;
7299 }
7300
7301 static int broxton_get_display_clock_speed(struct drm_device *dev)
7302 {
7303         struct drm_i915_private *dev_priv = to_i915(dev);
7304         u32 divider;
7305         int div, vco;
7306
7307         bxt_de_pll_update(dev_priv);
7308
7309         vco = dev_priv->cdclk_pll.vco;
7310         if (vco == 0)
7311                 return dev_priv->cdclk_pll.ref;
7312
7313         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7314
7315         switch (divider) {
7316         case BXT_CDCLK_CD2X_DIV_SEL_1:
7317                 div = 2;
7318                 break;
7319         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7320                 div = 3;
7321                 break;
7322         case BXT_CDCLK_CD2X_DIV_SEL_2:
7323                 div = 4;
7324                 break;
7325         case BXT_CDCLK_CD2X_DIV_SEL_4:
7326                 div = 8;
7327                 break;
7328         default:
7329                 MISSING_CASE(divider);
7330                 return dev_priv->cdclk_pll.ref;
7331         }
7332
7333         return DIV_ROUND_CLOSEST(vco, div);
7334 }
7335
7336 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7337 {
7338         struct drm_i915_private *dev_priv = to_i915(dev);
7339         uint32_t lcpll = I915_READ(LCPLL_CTL);
7340         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7341
7342         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7343                 return 800000;
7344         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7345                 return 450000;
7346         else if (freq == LCPLL_CLK_FREQ_450)
7347                 return 450000;
7348         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7349                 return 540000;
7350         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7351                 return 337500;
7352         else
7353                 return 675000;
7354 }
7355
7356 static int haswell_get_display_clock_speed(struct drm_device *dev)
7357 {
7358         struct drm_i915_private *dev_priv = to_i915(dev);
7359         uint32_t lcpll = I915_READ(LCPLL_CTL);
7360         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7361
7362         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7363                 return 800000;
7364         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7365                 return 450000;
7366         else if (freq == LCPLL_CLK_FREQ_450)
7367                 return 450000;
7368         else if (IS_HSW_ULT(dev))
7369                 return 337500;
7370         else
7371                 return 540000;
7372 }
7373
7374 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7375 {
7376         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7377                                       CCK_DISPLAY_CLOCK_CONTROL);
7378 }
7379
7380 static int ilk_get_display_clock_speed(struct drm_device *dev)
7381 {
7382         return 450000;
7383 }
7384
7385 static int i945_get_display_clock_speed(struct drm_device *dev)
7386 {
7387         return 400000;
7388 }
7389
7390 static int i915_get_display_clock_speed(struct drm_device *dev)
7391 {
7392         return 333333;
7393 }
7394
7395 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7396 {
7397         return 200000;
7398 }
7399
7400 static int pnv_get_display_clock_speed(struct drm_device *dev)
7401 {
7402         struct pci_dev *pdev = dev->pdev;
7403         u16 gcfgc = 0;
7404
7405         pci_read_config_word(pdev, GCFGC, &gcfgc);
7406
7407         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7408         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7409                 return 266667;
7410         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7411                 return 333333;
7412         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7413                 return 444444;
7414         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7415                 return 200000;
7416         default:
7417                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7418         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7419                 return 133333;
7420         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7421                 return 166667;
7422         }
7423 }
7424
7425 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7426 {
7427         struct pci_dev *pdev = dev->pdev;
7428         u16 gcfgc = 0;
7429
7430         pci_read_config_word(pdev, GCFGC, &gcfgc);
7431
7432         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7433                 return 133333;
7434         else {
7435                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7436                 case GC_DISPLAY_CLOCK_333_MHZ:
7437                         return 333333;
7438                 default:
7439                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7440                         return 190000;
7441                 }
7442         }
7443 }
7444
7445 static int i865_get_display_clock_speed(struct drm_device *dev)
7446 {
7447         return 266667;
7448 }
7449
7450 static int i85x_get_display_clock_speed(struct drm_device *dev)
7451 {
7452         struct pci_dev *pdev = dev->pdev;
7453         u16 hpllcc = 0;
7454
7455         /*
7456          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7457          * encoding is different :(
7458          * FIXME is this the right way to detect 852GM/852GMV?
7459          */
7460         if (pdev->revision == 0x1)
7461                 return 133333;
7462
7463         pci_bus_read_config_word(pdev->bus,
7464                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7465
7466         /* Assume that the hardware is in the high speed state.  This
7467          * should be the default.
7468          */
7469         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7470         case GC_CLOCK_133_200:
7471         case GC_CLOCK_133_200_2:
7472         case GC_CLOCK_100_200:
7473                 return 200000;
7474         case GC_CLOCK_166_250:
7475                 return 250000;
7476         case GC_CLOCK_100_133:
7477                 return 133333;
7478         case GC_CLOCK_133_266:
7479         case GC_CLOCK_133_266_2:
7480         case GC_CLOCK_166_266:
7481                 return 266667;
7482         }
7483
7484         /* Shouldn't happen */
7485         return 0;
7486 }
7487
7488 static int i830_get_display_clock_speed(struct drm_device *dev)
7489 {
7490         return 133333;
7491 }
7492
7493 static unsigned int intel_hpll_vco(struct drm_device *dev)
7494 {
7495         struct drm_i915_private *dev_priv = to_i915(dev);
7496         static const unsigned int blb_vco[8] = {
7497                 [0] = 3200000,
7498                 [1] = 4000000,
7499                 [2] = 5333333,
7500                 [3] = 4800000,
7501                 [4] = 6400000,
7502         };
7503         static const unsigned int pnv_vco[8] = {
7504                 [0] = 3200000,
7505                 [1] = 4000000,
7506                 [2] = 5333333,
7507                 [3] = 4800000,
7508                 [4] = 2666667,
7509         };
7510         static const unsigned int cl_vco[8] = {
7511                 [0] = 3200000,
7512                 [1] = 4000000,
7513                 [2] = 5333333,
7514                 [3] = 6400000,
7515                 [4] = 3333333,
7516                 [5] = 3566667,
7517                 [6] = 4266667,
7518         };
7519         static const unsigned int elk_vco[8] = {
7520                 [0] = 3200000,
7521                 [1] = 4000000,
7522                 [2] = 5333333,
7523                 [3] = 4800000,
7524         };
7525         static const unsigned int ctg_vco[8] = {
7526                 [0] = 3200000,
7527                 [1] = 4000000,
7528                 [2] = 5333333,
7529                 [3] = 6400000,
7530                 [4] = 2666667,
7531                 [5] = 4266667,
7532         };
7533         const unsigned int *vco_table;
7534         unsigned int vco;
7535         uint8_t tmp = 0;
7536
7537         /* FIXME other chipsets? */
7538         if (IS_GM45(dev))
7539                 vco_table = ctg_vco;
7540         else if (IS_G4X(dev))
7541                 vco_table = elk_vco;
7542         else if (IS_CRESTLINE(dev))
7543                 vco_table = cl_vco;
7544         else if (IS_PINEVIEW(dev))
7545                 vco_table = pnv_vco;
7546         else if (IS_G33(dev))
7547                 vco_table = blb_vco;
7548         else
7549                 return 0;
7550
7551         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7552
7553         vco = vco_table[tmp & 0x7];
7554         if (vco == 0)
7555                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7556         else
7557                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7558
7559         return vco;
7560 }
7561
7562 static int gm45_get_display_clock_speed(struct drm_device *dev)
7563 {
7564         struct pci_dev *pdev = dev->pdev;
7565         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7566         uint16_t tmp = 0;
7567
7568         pci_read_config_word(pdev, GCFGC, &tmp);
7569
7570         cdclk_sel = (tmp >> 12) & 0x1;
7571
7572         switch (vco) {
7573         case 2666667:
7574         case 4000000:
7575         case 5333333:
7576                 return cdclk_sel ? 333333 : 222222;
7577         case 3200000:
7578                 return cdclk_sel ? 320000 : 228571;
7579         default:
7580                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7581                 return 222222;
7582         }
7583 }
7584
7585 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7586 {
7587         struct pci_dev *pdev = dev->pdev;
7588         static const uint8_t div_3200[] = { 16, 10,  8 };
7589         static const uint8_t div_4000[] = { 20, 12, 10 };
7590         static const uint8_t div_5333[] = { 24, 16, 14 };
7591         const uint8_t *div_table;
7592         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7593         uint16_t tmp = 0;
7594
7595         pci_read_config_word(pdev, GCFGC, &tmp);
7596
7597         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7598
7599         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7600                 goto fail;
7601
7602         switch (vco) {
7603         case 3200000:
7604                 div_table = div_3200;
7605                 break;
7606         case 4000000:
7607                 div_table = div_4000;
7608                 break;
7609         case 5333333:
7610                 div_table = div_5333;
7611                 break;
7612         default:
7613                 goto fail;
7614         }
7615
7616         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7617
7618 fail:
7619         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7620         return 200000;
7621 }
7622
7623 static int g33_get_display_clock_speed(struct drm_device *dev)
7624 {
7625         struct pci_dev *pdev = dev->pdev;
7626         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7627         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7628         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7629         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7630         const uint8_t *div_table;
7631         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7632         uint16_t tmp = 0;
7633
7634         pci_read_config_word(pdev, GCFGC, &tmp);
7635
7636         cdclk_sel = (tmp >> 4) & 0x7;
7637
7638         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7639                 goto fail;
7640
7641         switch (vco) {
7642         case 3200000:
7643                 div_table = div_3200;
7644                 break;
7645         case 4000000:
7646                 div_table = div_4000;
7647                 break;
7648         case 4800000:
7649                 div_table = div_4800;
7650                 break;
7651         case 5333333:
7652                 div_table = div_5333;
7653                 break;
7654         default:
7655                 goto fail;
7656         }
7657
7658         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7659
7660 fail:
7661         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7662         return 190476;
7663 }
7664
7665 static void
7666 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7667 {
7668         while (*num > DATA_LINK_M_N_MASK ||
7669                *den > DATA_LINK_M_N_MASK) {
7670                 *num >>= 1;
7671                 *den >>= 1;
7672         }
7673 }
7674
7675 static void compute_m_n(unsigned int m, unsigned int n,
7676                         uint32_t *ret_m, uint32_t *ret_n)
7677 {
7678         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7679         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7680         intel_reduce_m_n_ratio(ret_m, ret_n);
7681 }
7682
7683 void
7684 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7685                        int pixel_clock, int link_clock,
7686                        struct intel_link_m_n *m_n)
7687 {
7688         m_n->tu = 64;
7689
7690         compute_m_n(bits_per_pixel * pixel_clock,
7691                     link_clock * nlanes * 8,
7692                     &m_n->gmch_m, &m_n->gmch_n);
7693
7694         compute_m_n(pixel_clock, link_clock,
7695                     &m_n->link_m, &m_n->link_n);
7696 }
7697
7698 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7699 {
7700         if (i915.panel_use_ssc >= 0)
7701                 return i915.panel_use_ssc != 0;
7702         return dev_priv->vbt.lvds_use_ssc
7703                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7704 }
7705
7706 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7707 {
7708         return (1 << dpll->n) << 16 | dpll->m2;
7709 }
7710
7711 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7712 {
7713         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7714 }
7715
7716 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7717                                      struct intel_crtc_state *crtc_state,
7718                                      struct dpll *reduced_clock)
7719 {
7720         struct drm_device *dev = crtc->base.dev;
7721         u32 fp, fp2 = 0;
7722
7723         if (IS_PINEVIEW(dev)) {
7724                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7725                 if (reduced_clock)
7726                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7727         } else {
7728                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7729                 if (reduced_clock)
7730                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7731         }
7732
7733         crtc_state->dpll_hw_state.fp0 = fp;
7734
7735         crtc->lowfreq_avail = false;
7736         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7737             reduced_clock) {
7738                 crtc_state->dpll_hw_state.fp1 = fp2;
7739                 crtc->lowfreq_avail = true;
7740         } else {
7741                 crtc_state->dpll_hw_state.fp1 = fp;
7742         }
7743 }
7744
7745 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7746                 pipe)
7747 {
7748         u32 reg_val;
7749
7750         /*
7751          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7752          * and set it to a reasonable value instead.
7753          */
7754         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7755         reg_val &= 0xffffff00;
7756         reg_val |= 0x00000030;
7757         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7758
7759         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7760         reg_val &= 0x8cffffff;
7761         reg_val = 0x8c000000;
7762         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7763
7764         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7765         reg_val &= 0xffffff00;
7766         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7767
7768         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7769         reg_val &= 0x00ffffff;
7770         reg_val |= 0xb0000000;
7771         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7772 }
7773
7774 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7775                                          struct intel_link_m_n *m_n)
7776 {
7777         struct drm_device *dev = crtc->base.dev;
7778         struct drm_i915_private *dev_priv = to_i915(dev);
7779         int pipe = crtc->pipe;
7780
7781         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7782         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7783         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7784         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7785 }
7786
7787 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7788                                          struct intel_link_m_n *m_n,
7789                                          struct intel_link_m_n *m2_n2)
7790 {
7791         struct drm_device *dev = crtc->base.dev;
7792         struct drm_i915_private *dev_priv = to_i915(dev);
7793         int pipe = crtc->pipe;
7794         enum transcoder transcoder = crtc->config->cpu_transcoder;
7795
7796         if (INTEL_INFO(dev)->gen >= 5) {
7797                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7798                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7799                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7800                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7801                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7802                  * for gen < 8) and if DRRS is supported (to make sure the
7803                  * registers are not unnecessarily accessed).
7804                  */
7805                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7806                         crtc->config->has_drrs) {
7807                         I915_WRITE(PIPE_DATA_M2(transcoder),
7808                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7809                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7810                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7811                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7812                 }
7813         } else {
7814                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7815                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7816                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7817                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7818         }
7819 }
7820
7821 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7822 {
7823         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7824
7825         if (m_n == M1_N1) {
7826                 dp_m_n = &crtc->config->dp_m_n;
7827                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7828         } else if (m_n == M2_N2) {
7829
7830                 /*
7831                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7832                  * needs to be programmed into M1_N1.
7833                  */
7834                 dp_m_n = &crtc->config->dp_m2_n2;
7835         } else {
7836                 DRM_ERROR("Unsupported divider value\n");
7837                 return;
7838         }
7839
7840         if (crtc->config->has_pch_encoder)
7841                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7842         else
7843                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7844 }
7845
7846 static void vlv_compute_dpll(struct intel_crtc *crtc,
7847                              struct intel_crtc_state *pipe_config)
7848 {
7849         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7850                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7851         if (crtc->pipe != PIPE_A)
7852                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7853
7854         /* DPLL not used with DSI, but still need the rest set up */
7855         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7856                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7857                         DPLL_EXT_BUFFER_ENABLE_VLV;
7858
7859         pipe_config->dpll_hw_state.dpll_md =
7860                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7861 }
7862
7863 static void chv_compute_dpll(struct intel_crtc *crtc,
7864                              struct intel_crtc_state *pipe_config)
7865 {
7866         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7867                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7868         if (crtc->pipe != PIPE_A)
7869                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7870
7871         /* DPLL not used with DSI, but still need the rest set up */
7872         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7873                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7874
7875         pipe_config->dpll_hw_state.dpll_md =
7876                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7877 }
7878
7879 static void vlv_prepare_pll(struct intel_crtc *crtc,
7880                             const struct intel_crtc_state *pipe_config)
7881 {
7882         struct drm_device *dev = crtc->base.dev;
7883         struct drm_i915_private *dev_priv = to_i915(dev);
7884         enum pipe pipe = crtc->pipe;
7885         u32 mdiv;
7886         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7887         u32 coreclk, reg_val;
7888
7889         /* Enable Refclk */
7890         I915_WRITE(DPLL(pipe),
7891                    pipe_config->dpll_hw_state.dpll &
7892                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7893
7894         /* No need to actually set up the DPLL with DSI */
7895         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7896                 return;
7897
7898         mutex_lock(&dev_priv->sb_lock);
7899
7900         bestn = pipe_config->dpll.n;
7901         bestm1 = pipe_config->dpll.m1;
7902         bestm2 = pipe_config->dpll.m2;
7903         bestp1 = pipe_config->dpll.p1;
7904         bestp2 = pipe_config->dpll.p2;
7905
7906         /* See eDP HDMI DPIO driver vbios notes doc */
7907
7908         /* PLL B needs special handling */
7909         if (pipe == PIPE_B)
7910                 vlv_pllb_recal_opamp(dev_priv, pipe);
7911
7912         /* Set up Tx target for periodic Rcomp update */
7913         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7914
7915         /* Disable target IRef on PLL */
7916         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7917         reg_val &= 0x00ffffff;
7918         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7919
7920         /* Disable fast lock */
7921         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7922
7923         /* Set idtafcrecal before PLL is enabled */
7924         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7925         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7926         mdiv |= ((bestn << DPIO_N_SHIFT));
7927         mdiv |= (1 << DPIO_K_SHIFT);
7928
7929         /*
7930          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7931          * but we don't support that).
7932          * Note: don't use the DAC post divider as it seems unstable.
7933          */
7934         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7935         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7936
7937         mdiv |= DPIO_ENABLE_CALIBRATION;
7938         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7939
7940         /* Set HBR and RBR LPF coefficients */
7941         if (pipe_config->port_clock == 162000 ||
7942             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7943             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7944                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7945                                  0x009f0003);
7946         else
7947                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7948                                  0x00d0000f);
7949
7950         if (intel_crtc_has_dp_encoder(pipe_config)) {
7951                 /* Use SSC source */
7952                 if (pipe == PIPE_A)
7953                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7954                                          0x0df40000);
7955                 else
7956                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7957                                          0x0df70000);
7958         } else { /* HDMI or VGA */
7959                 /* Use bend source */
7960                 if (pipe == PIPE_A)
7961                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7962                                          0x0df70000);
7963                 else
7964                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7965                                          0x0df40000);
7966         }
7967
7968         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7969         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7970         if (intel_crtc_has_dp_encoder(crtc->config))
7971                 coreclk |= 0x01000000;
7972         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7973
7974         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7975         mutex_unlock(&dev_priv->sb_lock);
7976 }
7977
7978 static void chv_prepare_pll(struct intel_crtc *crtc,
7979                             const struct intel_crtc_state *pipe_config)
7980 {
7981         struct drm_device *dev = crtc->base.dev;
7982         struct drm_i915_private *dev_priv = to_i915(dev);
7983         enum pipe pipe = crtc->pipe;
7984         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7985         u32 loopfilter, tribuf_calcntr;
7986         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7987         u32 dpio_val;
7988         int vco;
7989
7990         /* Enable Refclk and SSC */
7991         I915_WRITE(DPLL(pipe),
7992                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7993
7994         /* No need to actually set up the DPLL with DSI */
7995         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7996                 return;
7997
7998         bestn = pipe_config->dpll.n;
7999         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8000         bestm1 = pipe_config->dpll.m1;
8001         bestm2 = pipe_config->dpll.m2 >> 22;
8002         bestp1 = pipe_config->dpll.p1;
8003         bestp2 = pipe_config->dpll.p2;
8004         vco = pipe_config->dpll.vco;
8005         dpio_val = 0;
8006         loopfilter = 0;
8007
8008         mutex_lock(&dev_priv->sb_lock);
8009
8010         /* p1 and p2 divider */
8011         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8012                         5 << DPIO_CHV_S1_DIV_SHIFT |
8013                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8014                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8015                         1 << DPIO_CHV_K_DIV_SHIFT);
8016
8017         /* Feedback post-divider - m2 */
8018         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8019
8020         /* Feedback refclk divider - n and m1 */
8021         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8022                         DPIO_CHV_M1_DIV_BY_2 |
8023                         1 << DPIO_CHV_N_DIV_SHIFT);
8024
8025         /* M2 fraction division */
8026         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8027
8028         /* M2 fraction division enable */
8029         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8030         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8031         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8032         if (bestm2_frac)
8033                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8034         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8035
8036         /* Program digital lock detect threshold */
8037         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8038         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8039                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8040         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8041         if (!bestm2_frac)
8042                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8043         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8044
8045         /* Loop filter */
8046         if (vco == 5400000) {
8047                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8048                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8049                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8050                 tribuf_calcntr = 0x9;
8051         } else if (vco <= 6200000) {
8052                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8053                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8054                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8055                 tribuf_calcntr = 0x9;
8056         } else if (vco <= 6480000) {
8057                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8058                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8059                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8060                 tribuf_calcntr = 0x8;
8061         } else {
8062                 /* Not supported. Apply the same limits as in the max case */
8063                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8064                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8065                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8066                 tribuf_calcntr = 0;
8067         }
8068         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8069
8070         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8071         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8072         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8073         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8074
8075         /* AFC Recal */
8076         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8077                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8078                         DPIO_AFC_RECAL);
8079
8080         mutex_unlock(&dev_priv->sb_lock);
8081 }
8082
8083 /**
8084  * vlv_force_pll_on - forcibly enable just the PLL
8085  * @dev_priv: i915 private structure
8086  * @pipe: pipe PLL to enable
8087  * @dpll: PLL configuration
8088  *
8089  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8090  * in cases where we need the PLL enabled even when @pipe is not going to
8091  * be enabled.
8092  */
8093 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
8094                      const struct dpll *dpll)
8095 {
8096         struct intel_crtc *crtc =
8097                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
8098         struct intel_crtc_state *pipe_config;
8099
8100         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8101         if (!pipe_config)
8102                 return -ENOMEM;
8103
8104         pipe_config->base.crtc = &crtc->base;
8105         pipe_config->pixel_multiplier = 1;
8106         pipe_config->dpll = *dpll;
8107
8108         if (IS_CHERRYVIEW(dev)) {
8109                 chv_compute_dpll(crtc, pipe_config);
8110                 chv_prepare_pll(crtc, pipe_config);
8111                 chv_enable_pll(crtc, pipe_config);
8112         } else {
8113                 vlv_compute_dpll(crtc, pipe_config);
8114                 vlv_prepare_pll(crtc, pipe_config);
8115                 vlv_enable_pll(crtc, pipe_config);
8116         }
8117
8118         kfree(pipe_config);
8119
8120         return 0;
8121 }
8122
8123 /**
8124  * vlv_force_pll_off - forcibly disable just the PLL
8125  * @dev_priv: i915 private structure
8126  * @pipe: pipe PLL to disable
8127  *
8128  * Disable the PLL for @pipe. To be used in cases where we need
8129  * the PLL enabled even when @pipe is not going to be enabled.
8130  */
8131 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8132 {
8133         if (IS_CHERRYVIEW(dev))
8134                 chv_disable_pll(to_i915(dev), pipe);
8135         else
8136                 vlv_disable_pll(to_i915(dev), pipe);
8137 }
8138
8139 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8140                               struct intel_crtc_state *crtc_state,
8141                               struct dpll *reduced_clock)
8142 {
8143         struct drm_device *dev = crtc->base.dev;
8144         struct drm_i915_private *dev_priv = to_i915(dev);
8145         u32 dpll;
8146         struct dpll *clock = &crtc_state->dpll;
8147
8148         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8149
8150         dpll = DPLL_VGA_MODE_DIS;
8151
8152         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8153                 dpll |= DPLLB_MODE_LVDS;
8154         else
8155                 dpll |= DPLLB_MODE_DAC_SERIAL;
8156
8157         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8158                 dpll |= (crtc_state->pixel_multiplier - 1)
8159                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8160         }
8161
8162         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8163             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8164                 dpll |= DPLL_SDVO_HIGH_SPEED;
8165
8166         if (intel_crtc_has_dp_encoder(crtc_state))
8167                 dpll |= DPLL_SDVO_HIGH_SPEED;
8168
8169         /* compute bitmask from p1 value */
8170         if (IS_PINEVIEW(dev))
8171                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8172         else {
8173                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8174                 if (IS_G4X(dev) && reduced_clock)
8175                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8176         }
8177         switch (clock->p2) {
8178         case 5:
8179                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8180                 break;
8181         case 7:
8182                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8183                 break;
8184         case 10:
8185                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8186                 break;
8187         case 14:
8188                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8189                 break;
8190         }
8191         if (INTEL_INFO(dev)->gen >= 4)
8192                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8193
8194         if (crtc_state->sdvo_tv_clock)
8195                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8196         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8197                  intel_panel_use_ssc(dev_priv))
8198                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8199         else
8200                 dpll |= PLL_REF_INPUT_DREFCLK;
8201
8202         dpll |= DPLL_VCO_ENABLE;
8203         crtc_state->dpll_hw_state.dpll = dpll;
8204
8205         if (INTEL_INFO(dev)->gen >= 4) {
8206                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8207                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8208                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8209         }
8210 }
8211
8212 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8213                               struct intel_crtc_state *crtc_state,
8214                               struct dpll *reduced_clock)
8215 {
8216         struct drm_device *dev = crtc->base.dev;
8217         struct drm_i915_private *dev_priv = to_i915(dev);
8218         u32 dpll;
8219         struct dpll *clock = &crtc_state->dpll;
8220
8221         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8222
8223         dpll = DPLL_VGA_MODE_DIS;
8224
8225         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8226                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8227         } else {
8228                 if (clock->p1 == 2)
8229                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8230                 else
8231                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8232                 if (clock->p2 == 4)
8233                         dpll |= PLL_P2_DIVIDE_BY_4;
8234         }
8235
8236         if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8237                 dpll |= DPLL_DVO_2X_MODE;
8238
8239         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8240             intel_panel_use_ssc(dev_priv))
8241                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8242         else
8243                 dpll |= PLL_REF_INPUT_DREFCLK;
8244
8245         dpll |= DPLL_VCO_ENABLE;
8246         crtc_state->dpll_hw_state.dpll = dpll;
8247 }
8248
8249 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8250 {
8251         struct drm_device *dev = intel_crtc->base.dev;
8252         struct drm_i915_private *dev_priv = to_i915(dev);
8253         enum pipe pipe = intel_crtc->pipe;
8254         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8255         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8256         uint32_t crtc_vtotal, crtc_vblank_end;
8257         int vsyncshift = 0;
8258
8259         /* We need to be careful not to changed the adjusted mode, for otherwise
8260          * the hw state checker will get angry at the mismatch. */
8261         crtc_vtotal = adjusted_mode->crtc_vtotal;
8262         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8263
8264         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8265                 /* the chip adds 2 halflines automatically */
8266                 crtc_vtotal -= 1;
8267                 crtc_vblank_end -= 1;
8268
8269                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8270                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8271                 else
8272                         vsyncshift = adjusted_mode->crtc_hsync_start -
8273                                 adjusted_mode->crtc_htotal / 2;
8274                 if (vsyncshift < 0)
8275                         vsyncshift += adjusted_mode->crtc_htotal;
8276         }
8277
8278         if (INTEL_INFO(dev)->gen > 3)
8279                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8280
8281         I915_WRITE(HTOTAL(cpu_transcoder),
8282                    (adjusted_mode->crtc_hdisplay - 1) |
8283                    ((adjusted_mode->crtc_htotal - 1) << 16));
8284         I915_WRITE(HBLANK(cpu_transcoder),
8285                    (adjusted_mode->crtc_hblank_start - 1) |
8286                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8287         I915_WRITE(HSYNC(cpu_transcoder),
8288                    (adjusted_mode->crtc_hsync_start - 1) |
8289                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8290
8291         I915_WRITE(VTOTAL(cpu_transcoder),
8292                    (adjusted_mode->crtc_vdisplay - 1) |
8293                    ((crtc_vtotal - 1) << 16));
8294         I915_WRITE(VBLANK(cpu_transcoder),
8295                    (adjusted_mode->crtc_vblank_start - 1) |
8296                    ((crtc_vblank_end - 1) << 16));
8297         I915_WRITE(VSYNC(cpu_transcoder),
8298                    (adjusted_mode->crtc_vsync_start - 1) |
8299                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8300
8301         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8302          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8303          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8304          * bits. */
8305         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
8306             (pipe == PIPE_B || pipe == PIPE_C))
8307                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8308
8309 }
8310
8311 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8312 {
8313         struct drm_device *dev = intel_crtc->base.dev;
8314         struct drm_i915_private *dev_priv = to_i915(dev);
8315         enum pipe pipe = intel_crtc->pipe;
8316
8317         /* pipesrc controls the size that is scaled from, which should
8318          * always be the user's requested size.
8319          */
8320         I915_WRITE(PIPESRC(pipe),
8321                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8322                    (intel_crtc->config->pipe_src_h - 1));
8323 }
8324
8325 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8326                                    struct intel_crtc_state *pipe_config)
8327 {
8328         struct drm_device *dev = crtc->base.dev;
8329         struct drm_i915_private *dev_priv = to_i915(dev);
8330         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8331         uint32_t tmp;
8332
8333         tmp = I915_READ(HTOTAL(cpu_transcoder));
8334         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8335         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8336         tmp = I915_READ(HBLANK(cpu_transcoder));
8337         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8338         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8339         tmp = I915_READ(HSYNC(cpu_transcoder));
8340         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8341         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8342
8343         tmp = I915_READ(VTOTAL(cpu_transcoder));
8344         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8345         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8346         tmp = I915_READ(VBLANK(cpu_transcoder));
8347         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8348         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8349         tmp = I915_READ(VSYNC(cpu_transcoder));
8350         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8351         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8352
8353         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8354                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8355                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8356                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8357         }
8358 }
8359
8360 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8361                                     struct intel_crtc_state *pipe_config)
8362 {
8363         struct drm_device *dev = crtc->base.dev;
8364         struct drm_i915_private *dev_priv = to_i915(dev);
8365         u32 tmp;
8366
8367         tmp = I915_READ(PIPESRC(crtc->pipe));
8368         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8369         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8370
8371         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8372         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8373 }
8374
8375 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8376                                  struct intel_crtc_state *pipe_config)
8377 {
8378         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8379         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8380         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8381         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8382
8383         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8384         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8385         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8386         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8387
8388         mode->flags = pipe_config->base.adjusted_mode.flags;
8389         mode->type = DRM_MODE_TYPE_DRIVER;
8390
8391         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8392         mode->flags |= pipe_config->base.adjusted_mode.flags;
8393
8394         mode->hsync = drm_mode_hsync(mode);
8395         mode->vrefresh = drm_mode_vrefresh(mode);
8396         drm_mode_set_name(mode);
8397 }
8398
8399 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8400 {
8401         struct drm_device *dev = intel_crtc->base.dev;
8402         struct drm_i915_private *dev_priv = to_i915(dev);
8403         uint32_t pipeconf;
8404
8405         pipeconf = 0;
8406
8407         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8408             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8409                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8410
8411         if (intel_crtc->config->double_wide)
8412                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8413
8414         /* only g4x and later have fancy bpc/dither controls */
8415         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8416                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8417                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8418                         pipeconf |= PIPECONF_DITHER_EN |
8419                                     PIPECONF_DITHER_TYPE_SP;
8420
8421                 switch (intel_crtc->config->pipe_bpp) {
8422                 case 18:
8423                         pipeconf |= PIPECONF_6BPC;
8424                         break;
8425                 case 24:
8426                         pipeconf |= PIPECONF_8BPC;
8427                         break;
8428                 case 30:
8429                         pipeconf |= PIPECONF_10BPC;
8430                         break;
8431                 default:
8432                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8433                         BUG();
8434                 }
8435         }
8436
8437         if (HAS_PIPE_CXSR(dev)) {
8438                 if (intel_crtc->lowfreq_avail) {
8439                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8440                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8441                 } else {
8442                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8443                 }
8444         }
8445
8446         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8447                 if (INTEL_INFO(dev)->gen < 4 ||
8448                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8449                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8450                 else
8451                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8452         } else
8453                 pipeconf |= PIPECONF_PROGRESSIVE;
8454
8455         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8456              intel_crtc->config->limited_color_range)
8457                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8458
8459         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8460         POSTING_READ(PIPECONF(intel_crtc->pipe));
8461 }
8462
8463 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8464                                    struct intel_crtc_state *crtc_state)
8465 {
8466         struct drm_device *dev = crtc->base.dev;
8467         struct drm_i915_private *dev_priv = to_i915(dev);
8468         const struct intel_limit *limit;
8469         int refclk = 48000;
8470
8471         memset(&crtc_state->dpll_hw_state, 0,
8472                sizeof(crtc_state->dpll_hw_state));
8473
8474         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8475                 if (intel_panel_use_ssc(dev_priv)) {
8476                         refclk = dev_priv->vbt.lvds_ssc_freq;
8477                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8478                 }
8479
8480                 limit = &intel_limits_i8xx_lvds;
8481         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8482                 limit = &intel_limits_i8xx_dvo;
8483         } else {
8484                 limit = &intel_limits_i8xx_dac;
8485         }
8486
8487         if (!crtc_state->clock_set &&
8488             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8489                                  refclk, NULL, &crtc_state->dpll)) {
8490                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8491                 return -EINVAL;
8492         }
8493
8494         i8xx_compute_dpll(crtc, crtc_state, NULL);
8495
8496         return 0;
8497 }
8498
8499 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8500                                   struct intel_crtc_state *crtc_state)
8501 {
8502         struct drm_device *dev = crtc->base.dev;
8503         struct drm_i915_private *dev_priv = to_i915(dev);
8504         const struct intel_limit *limit;
8505         int refclk = 96000;
8506
8507         memset(&crtc_state->dpll_hw_state, 0,
8508                sizeof(crtc_state->dpll_hw_state));
8509
8510         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8511                 if (intel_panel_use_ssc(dev_priv)) {
8512                         refclk = dev_priv->vbt.lvds_ssc_freq;
8513                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8514                 }
8515
8516                 if (intel_is_dual_link_lvds(dev))
8517                         limit = &intel_limits_g4x_dual_channel_lvds;
8518                 else
8519                         limit = &intel_limits_g4x_single_channel_lvds;
8520         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8521                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8522                 limit = &intel_limits_g4x_hdmi;
8523         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8524                 limit = &intel_limits_g4x_sdvo;
8525         } else {
8526                 /* The option is for other outputs */
8527                 limit = &intel_limits_i9xx_sdvo;
8528         }
8529
8530         if (!crtc_state->clock_set &&
8531             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8532                                 refclk, NULL, &crtc_state->dpll)) {
8533                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8534                 return -EINVAL;
8535         }
8536
8537         i9xx_compute_dpll(crtc, crtc_state, NULL);
8538
8539         return 0;
8540 }
8541
8542 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8543                                   struct intel_crtc_state *crtc_state)
8544 {
8545         struct drm_device *dev = crtc->base.dev;
8546         struct drm_i915_private *dev_priv = to_i915(dev);
8547         const struct intel_limit *limit;
8548         int refclk = 96000;
8549
8550         memset(&crtc_state->dpll_hw_state, 0,
8551                sizeof(crtc_state->dpll_hw_state));
8552
8553         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8554                 if (intel_panel_use_ssc(dev_priv)) {
8555                         refclk = dev_priv->vbt.lvds_ssc_freq;
8556                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8557                 }
8558
8559                 limit = &intel_limits_pineview_lvds;
8560         } else {
8561                 limit = &intel_limits_pineview_sdvo;
8562         }
8563
8564         if (!crtc_state->clock_set &&
8565             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8566                                 refclk, NULL, &crtc_state->dpll)) {
8567                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8568                 return -EINVAL;
8569         }
8570
8571         i9xx_compute_dpll(crtc, crtc_state, NULL);
8572
8573         return 0;
8574 }
8575
8576 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8577                                    struct intel_crtc_state *crtc_state)
8578 {
8579         struct drm_device *dev = crtc->base.dev;
8580         struct drm_i915_private *dev_priv = to_i915(dev);
8581         const struct intel_limit *limit;
8582         int refclk = 96000;
8583
8584         memset(&crtc_state->dpll_hw_state, 0,
8585                sizeof(crtc_state->dpll_hw_state));
8586
8587         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8588                 if (intel_panel_use_ssc(dev_priv)) {
8589                         refclk = dev_priv->vbt.lvds_ssc_freq;
8590                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8591                 }
8592
8593                 limit = &intel_limits_i9xx_lvds;
8594         } else {
8595                 limit = &intel_limits_i9xx_sdvo;
8596         }
8597
8598         if (!crtc_state->clock_set &&
8599             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8600                                  refclk, NULL, &crtc_state->dpll)) {
8601                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8602                 return -EINVAL;
8603         }
8604
8605         i9xx_compute_dpll(crtc, crtc_state, NULL);
8606
8607         return 0;
8608 }
8609
8610 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8611                                   struct intel_crtc_state *crtc_state)
8612 {
8613         int refclk = 100000;
8614         const struct intel_limit *limit = &intel_limits_chv;
8615
8616         memset(&crtc_state->dpll_hw_state, 0,
8617                sizeof(crtc_state->dpll_hw_state));
8618
8619         if (!crtc_state->clock_set &&
8620             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8621                                 refclk, NULL, &crtc_state->dpll)) {
8622                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8623                 return -EINVAL;
8624         }
8625
8626         chv_compute_dpll(crtc, crtc_state);
8627
8628         return 0;
8629 }
8630
8631 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8632                                   struct intel_crtc_state *crtc_state)
8633 {
8634         int refclk = 100000;
8635         const struct intel_limit *limit = &intel_limits_vlv;
8636
8637         memset(&crtc_state->dpll_hw_state, 0,
8638                sizeof(crtc_state->dpll_hw_state));
8639
8640         if (!crtc_state->clock_set &&
8641             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8642                                 refclk, NULL, &crtc_state->dpll)) {
8643                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8644                 return -EINVAL;
8645         }
8646
8647         vlv_compute_dpll(crtc, crtc_state);
8648
8649         return 0;
8650 }
8651
8652 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8653                                  struct intel_crtc_state *pipe_config)
8654 {
8655         struct drm_device *dev = crtc->base.dev;
8656         struct drm_i915_private *dev_priv = to_i915(dev);
8657         uint32_t tmp;
8658
8659         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8660                 return;
8661
8662         tmp = I915_READ(PFIT_CONTROL);
8663         if (!(tmp & PFIT_ENABLE))
8664                 return;
8665
8666         /* Check whether the pfit is attached to our pipe. */
8667         if (INTEL_INFO(dev)->gen < 4) {
8668                 if (crtc->pipe != PIPE_B)
8669                         return;
8670         } else {
8671                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8672                         return;
8673         }
8674
8675         pipe_config->gmch_pfit.control = tmp;
8676         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8677 }
8678
8679 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8680                                struct intel_crtc_state *pipe_config)
8681 {
8682         struct drm_device *dev = crtc->base.dev;
8683         struct drm_i915_private *dev_priv = to_i915(dev);
8684         int pipe = pipe_config->cpu_transcoder;
8685         struct dpll clock;
8686         u32 mdiv;
8687         int refclk = 100000;
8688
8689         /* In case of DSI, DPLL will not be used */
8690         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8691                 return;
8692
8693         mutex_lock(&dev_priv->sb_lock);
8694         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8695         mutex_unlock(&dev_priv->sb_lock);
8696
8697         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8698         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8699         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8700         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8701         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8702
8703         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8704 }
8705
8706 static void
8707 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8708                               struct intel_initial_plane_config *plane_config)
8709 {
8710         struct drm_device *dev = crtc->base.dev;
8711         struct drm_i915_private *dev_priv = to_i915(dev);
8712         u32 val, base, offset;
8713         int pipe = crtc->pipe, plane = crtc->plane;
8714         int fourcc, pixel_format;
8715         unsigned int aligned_height;
8716         struct drm_framebuffer *fb;
8717         struct intel_framebuffer *intel_fb;
8718
8719         val = I915_READ(DSPCNTR(plane));
8720         if (!(val & DISPLAY_PLANE_ENABLE))
8721                 return;
8722
8723         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8724         if (!intel_fb) {
8725                 DRM_DEBUG_KMS("failed to alloc fb\n");
8726                 return;
8727         }
8728
8729         fb = &intel_fb->base;
8730
8731         if (INTEL_INFO(dev)->gen >= 4) {
8732                 if (val & DISPPLANE_TILED) {
8733                         plane_config->tiling = I915_TILING_X;
8734                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8735                 }
8736         }
8737
8738         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8739         fourcc = i9xx_format_to_fourcc(pixel_format);
8740         fb->pixel_format = fourcc;
8741         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8742
8743         if (INTEL_INFO(dev)->gen >= 4) {
8744                 if (plane_config->tiling)
8745                         offset = I915_READ(DSPTILEOFF(plane));
8746                 else
8747                         offset = I915_READ(DSPLINOFF(plane));
8748                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8749         } else {
8750                 base = I915_READ(DSPADDR(plane));
8751         }
8752         plane_config->base = base;
8753
8754         val = I915_READ(PIPESRC(pipe));
8755         fb->width = ((val >> 16) & 0xfff) + 1;
8756         fb->height = ((val >> 0) & 0xfff) + 1;
8757
8758         val = I915_READ(DSPSTRIDE(pipe));
8759         fb->pitches[0] = val & 0xffffffc0;
8760
8761         aligned_height = intel_fb_align_height(dev, fb->height,
8762                                                fb->pixel_format,
8763                                                fb->modifier[0]);
8764
8765         plane_config->size = fb->pitches[0] * aligned_height;
8766
8767         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8768                       pipe_name(pipe), plane, fb->width, fb->height,
8769                       fb->bits_per_pixel, base, fb->pitches[0],
8770                       plane_config->size);
8771
8772         plane_config->fb = intel_fb;
8773 }
8774
8775 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8776                                struct intel_crtc_state *pipe_config)
8777 {
8778         struct drm_device *dev = crtc->base.dev;
8779         struct drm_i915_private *dev_priv = to_i915(dev);
8780         int pipe = pipe_config->cpu_transcoder;
8781         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8782         struct dpll clock;
8783         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8784         int refclk = 100000;
8785
8786         /* In case of DSI, DPLL will not be used */
8787         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8788                 return;
8789
8790         mutex_lock(&dev_priv->sb_lock);
8791         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8792         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8793         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8794         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8795         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8796         mutex_unlock(&dev_priv->sb_lock);
8797
8798         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8799         clock.m2 = (pll_dw0 & 0xff) << 22;
8800         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8801                 clock.m2 |= pll_dw2 & 0x3fffff;
8802         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8803         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8804         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8805
8806         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8807 }
8808
8809 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8810                                  struct intel_crtc_state *pipe_config)
8811 {
8812         struct drm_device *dev = crtc->base.dev;
8813         struct drm_i915_private *dev_priv = to_i915(dev);
8814         enum intel_display_power_domain power_domain;
8815         uint32_t tmp;
8816         bool ret;
8817
8818         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8819         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8820                 return false;
8821
8822         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8823         pipe_config->shared_dpll = NULL;
8824
8825         ret = false;
8826
8827         tmp = I915_READ(PIPECONF(crtc->pipe));
8828         if (!(tmp & PIPECONF_ENABLE))
8829                 goto out;
8830
8831         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8832                 switch (tmp & PIPECONF_BPC_MASK) {
8833                 case PIPECONF_6BPC:
8834                         pipe_config->pipe_bpp = 18;
8835                         break;
8836                 case PIPECONF_8BPC:
8837                         pipe_config->pipe_bpp = 24;
8838                         break;
8839                 case PIPECONF_10BPC:
8840                         pipe_config->pipe_bpp = 30;
8841                         break;
8842                 default:
8843                         break;
8844                 }
8845         }
8846
8847         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8848             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8849                 pipe_config->limited_color_range = true;
8850
8851         if (INTEL_INFO(dev)->gen < 4)
8852                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8853
8854         intel_get_pipe_timings(crtc, pipe_config);
8855         intel_get_pipe_src_size(crtc, pipe_config);
8856
8857         i9xx_get_pfit_config(crtc, pipe_config);
8858
8859         if (INTEL_INFO(dev)->gen >= 4) {
8860                 /* No way to read it out on pipes B and C */
8861                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8862                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8863                 else
8864                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8865                 pipe_config->pixel_multiplier =
8866                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8867                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8868                 pipe_config->dpll_hw_state.dpll_md = tmp;
8869         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8870                 tmp = I915_READ(DPLL(crtc->pipe));
8871                 pipe_config->pixel_multiplier =
8872                         ((tmp & SDVO_MULTIPLIER_MASK)
8873                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8874         } else {
8875                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8876                  * port and will be fixed up in the encoder->get_config
8877                  * function. */
8878                 pipe_config->pixel_multiplier = 1;
8879         }
8880         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8881         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8882                 /*
8883                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8884                  * on 830. Filter it out here so that we don't
8885                  * report errors due to that.
8886                  */
8887                 if (IS_I830(dev))
8888                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8889
8890                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8891                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8892         } else {
8893                 /* Mask out read-only status bits. */
8894                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8895                                                      DPLL_PORTC_READY_MASK |
8896                                                      DPLL_PORTB_READY_MASK);
8897         }
8898
8899         if (IS_CHERRYVIEW(dev))
8900                 chv_crtc_clock_get(crtc, pipe_config);
8901         else if (IS_VALLEYVIEW(dev))
8902                 vlv_crtc_clock_get(crtc, pipe_config);
8903         else
8904                 i9xx_crtc_clock_get(crtc, pipe_config);
8905
8906         /*
8907          * Normally the dotclock is filled in by the encoder .get_config()
8908          * but in case the pipe is enabled w/o any ports we need a sane
8909          * default.
8910          */
8911         pipe_config->base.adjusted_mode.crtc_clock =
8912                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8913
8914         ret = true;
8915
8916 out:
8917         intel_display_power_put(dev_priv, power_domain);
8918
8919         return ret;
8920 }
8921
8922 static void ironlake_init_pch_refclk(struct drm_device *dev)
8923 {
8924         struct drm_i915_private *dev_priv = to_i915(dev);
8925         struct intel_encoder *encoder;
8926         int i;
8927         u32 val, final;
8928         bool has_lvds = false;
8929         bool has_cpu_edp = false;
8930         bool has_panel = false;
8931         bool has_ck505 = false;
8932         bool can_ssc = false;
8933         bool using_ssc_source = false;
8934
8935         /* We need to take the global config into account */
8936         for_each_intel_encoder(dev, encoder) {
8937                 switch (encoder->type) {
8938                 case INTEL_OUTPUT_LVDS:
8939                         has_panel = true;
8940                         has_lvds = true;
8941                         break;
8942                 case INTEL_OUTPUT_EDP:
8943                         has_panel = true;
8944                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8945                                 has_cpu_edp = true;
8946                         break;
8947                 default:
8948                         break;
8949                 }
8950         }
8951
8952         if (HAS_PCH_IBX(dev)) {
8953                 has_ck505 = dev_priv->vbt.display_clock_mode;
8954                 can_ssc = has_ck505;
8955         } else {
8956                 has_ck505 = false;
8957                 can_ssc = true;
8958         }
8959
8960         /* Check if any DPLLs are using the SSC source */
8961         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8962                 u32 temp = I915_READ(PCH_DPLL(i));
8963
8964                 if (!(temp & DPLL_VCO_ENABLE))
8965                         continue;
8966
8967                 if ((temp & PLL_REF_INPUT_MASK) ==
8968                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8969                         using_ssc_source = true;
8970                         break;
8971                 }
8972         }
8973
8974         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8975                       has_panel, has_lvds, has_ck505, using_ssc_source);
8976
8977         /* Ironlake: try to setup display ref clock before DPLL
8978          * enabling. This is only under driver's control after
8979          * PCH B stepping, previous chipset stepping should be
8980          * ignoring this setting.
8981          */
8982         val = I915_READ(PCH_DREF_CONTROL);
8983
8984         /* As we must carefully and slowly disable/enable each source in turn,
8985          * compute the final state we want first and check if we need to
8986          * make any changes at all.
8987          */
8988         final = val;
8989         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8990         if (has_ck505)
8991                 final |= DREF_NONSPREAD_CK505_ENABLE;
8992         else
8993                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8994
8995         final &= ~DREF_SSC_SOURCE_MASK;
8996         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8997         final &= ~DREF_SSC1_ENABLE;
8998
8999         if (has_panel) {
9000                 final |= DREF_SSC_SOURCE_ENABLE;
9001
9002                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9003                         final |= DREF_SSC1_ENABLE;
9004
9005                 if (has_cpu_edp) {
9006                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9007                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9008                         else
9009                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9010                 } else
9011                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9012         } else if (using_ssc_source) {
9013                 final |= DREF_SSC_SOURCE_ENABLE;
9014                 final |= DREF_SSC1_ENABLE;
9015         }
9016
9017         if (final == val)
9018                 return;
9019
9020         /* Always enable nonspread source */
9021         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9022
9023         if (has_ck505)
9024                 val |= DREF_NONSPREAD_CK505_ENABLE;
9025         else
9026                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9027
9028         if (has_panel) {
9029                 val &= ~DREF_SSC_SOURCE_MASK;
9030                 val |= DREF_SSC_SOURCE_ENABLE;
9031
9032                 /* SSC must be turned on before enabling the CPU output  */
9033                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9034                         DRM_DEBUG_KMS("Using SSC on panel\n");
9035                         val |= DREF_SSC1_ENABLE;
9036                 } else
9037                         val &= ~DREF_SSC1_ENABLE;
9038
9039                 /* Get SSC going before enabling the outputs */
9040                 I915_WRITE(PCH_DREF_CONTROL, val);
9041                 POSTING_READ(PCH_DREF_CONTROL);
9042                 udelay(200);
9043
9044                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9045
9046                 /* Enable CPU source on CPU attached eDP */
9047                 if (has_cpu_edp) {
9048                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9049                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9050                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9051                         } else
9052                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9053                 } else
9054                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9055
9056                 I915_WRITE(PCH_DREF_CONTROL, val);
9057                 POSTING_READ(PCH_DREF_CONTROL);
9058                 udelay(200);
9059         } else {
9060                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9061
9062                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9063
9064                 /* Turn off CPU output */
9065                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9066
9067                 I915_WRITE(PCH_DREF_CONTROL, val);
9068                 POSTING_READ(PCH_DREF_CONTROL);
9069                 udelay(200);
9070
9071                 if (!using_ssc_source) {
9072                         DRM_DEBUG_KMS("Disabling SSC source\n");
9073
9074                         /* Turn off the SSC source */
9075                         val &= ~DREF_SSC_SOURCE_MASK;
9076                         val |= DREF_SSC_SOURCE_DISABLE;
9077
9078                         /* Turn off SSC1 */
9079                         val &= ~DREF_SSC1_ENABLE;
9080
9081                         I915_WRITE(PCH_DREF_CONTROL, val);
9082                         POSTING_READ(PCH_DREF_CONTROL);
9083                         udelay(200);
9084                 }
9085         }
9086
9087         BUG_ON(val != final);
9088 }
9089
9090 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9091 {
9092         uint32_t tmp;
9093
9094         tmp = I915_READ(SOUTH_CHICKEN2);
9095         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9096         I915_WRITE(SOUTH_CHICKEN2, tmp);
9097
9098         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9099                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9100                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9101
9102         tmp = I915_READ(SOUTH_CHICKEN2);
9103         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9104         I915_WRITE(SOUTH_CHICKEN2, tmp);
9105
9106         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9107                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9108                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9109 }
9110
9111 /* WaMPhyProgramming:hsw */
9112 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9113 {
9114         uint32_t tmp;
9115
9116         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9117         tmp &= ~(0xFF << 24);
9118         tmp |= (0x12 << 24);
9119         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9120
9121         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9122         tmp |= (1 << 11);
9123         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9124
9125         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9126         tmp |= (1 << 11);
9127         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9128
9129         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9130         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9131         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9132
9133         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9134         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9135         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9136
9137         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9138         tmp &= ~(7 << 13);
9139         tmp |= (5 << 13);
9140         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9141
9142         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9143         tmp &= ~(7 << 13);
9144         tmp |= (5 << 13);
9145         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9146
9147         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9148         tmp &= ~0xFF;
9149         tmp |= 0x1C;
9150         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9151
9152         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9153         tmp &= ~0xFF;
9154         tmp |= 0x1C;
9155         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9156
9157         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9158         tmp &= ~(0xFF << 16);
9159         tmp |= (0x1C << 16);
9160         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9161
9162         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9163         tmp &= ~(0xFF << 16);
9164         tmp |= (0x1C << 16);
9165         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9166
9167         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9168         tmp |= (1 << 27);
9169         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9170
9171         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9172         tmp |= (1 << 27);
9173         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9174
9175         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9176         tmp &= ~(0xF << 28);
9177         tmp |= (4 << 28);
9178         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9179
9180         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9181         tmp &= ~(0xF << 28);
9182         tmp |= (4 << 28);
9183         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9184 }
9185
9186 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9187  * Programming" based on the parameters passed:
9188  * - Sequence to enable CLKOUT_DP
9189  * - Sequence to enable CLKOUT_DP without spread
9190  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9191  */
9192 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9193                                  bool with_fdi)
9194 {
9195         struct drm_i915_private *dev_priv = to_i915(dev);
9196         uint32_t reg, tmp;
9197
9198         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9199                 with_spread = true;
9200         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
9201                 with_fdi = false;
9202
9203         mutex_lock(&dev_priv->sb_lock);
9204
9205         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9206         tmp &= ~SBI_SSCCTL_DISABLE;
9207         tmp |= SBI_SSCCTL_PATHALT;
9208         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9209
9210         udelay(24);
9211
9212         if (with_spread) {
9213                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9214                 tmp &= ~SBI_SSCCTL_PATHALT;
9215                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9216
9217                 if (with_fdi) {
9218                         lpt_reset_fdi_mphy(dev_priv);
9219                         lpt_program_fdi_mphy(dev_priv);
9220                 }
9221         }
9222
9223         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9224         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9225         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9226         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9227
9228         mutex_unlock(&dev_priv->sb_lock);
9229 }
9230
9231 /* Sequence to disable CLKOUT_DP */
9232 static void lpt_disable_clkout_dp(struct drm_device *dev)
9233 {
9234         struct drm_i915_private *dev_priv = to_i915(dev);
9235         uint32_t reg, tmp;
9236
9237         mutex_lock(&dev_priv->sb_lock);
9238
9239         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9240         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9241         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9242         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9243
9244         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9245         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9246                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9247                         tmp |= SBI_SSCCTL_PATHALT;
9248                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9249                         udelay(32);
9250                 }
9251                 tmp |= SBI_SSCCTL_DISABLE;
9252                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9253         }
9254
9255         mutex_unlock(&dev_priv->sb_lock);
9256 }
9257
9258 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9259
9260 static const uint16_t sscdivintphase[] = {
9261         [BEND_IDX( 50)] = 0x3B23,
9262         [BEND_IDX( 45)] = 0x3B23,
9263         [BEND_IDX( 40)] = 0x3C23,
9264         [BEND_IDX( 35)] = 0x3C23,
9265         [BEND_IDX( 30)] = 0x3D23,
9266         [BEND_IDX( 25)] = 0x3D23,
9267         [BEND_IDX( 20)] = 0x3E23,
9268         [BEND_IDX( 15)] = 0x3E23,
9269         [BEND_IDX( 10)] = 0x3F23,
9270         [BEND_IDX(  5)] = 0x3F23,
9271         [BEND_IDX(  0)] = 0x0025,
9272         [BEND_IDX( -5)] = 0x0025,
9273         [BEND_IDX(-10)] = 0x0125,
9274         [BEND_IDX(-15)] = 0x0125,
9275         [BEND_IDX(-20)] = 0x0225,
9276         [BEND_IDX(-25)] = 0x0225,
9277         [BEND_IDX(-30)] = 0x0325,
9278         [BEND_IDX(-35)] = 0x0325,
9279         [BEND_IDX(-40)] = 0x0425,
9280         [BEND_IDX(-45)] = 0x0425,
9281         [BEND_IDX(-50)] = 0x0525,
9282 };
9283
9284 /*
9285  * Bend CLKOUT_DP
9286  * steps -50 to 50 inclusive, in steps of 5
9287  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9288  * change in clock period = -(steps / 10) * 5.787 ps
9289  */
9290 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9291 {
9292         uint32_t tmp;
9293         int idx = BEND_IDX(steps);
9294
9295         if (WARN_ON(steps % 5 != 0))
9296                 return;
9297
9298         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9299                 return;
9300
9301         mutex_lock(&dev_priv->sb_lock);
9302
9303         if (steps % 10 != 0)
9304                 tmp = 0xAAAAAAAB;
9305         else
9306                 tmp = 0x00000000;
9307         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9308
9309         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9310         tmp &= 0xffff0000;
9311         tmp |= sscdivintphase[idx];
9312         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9313
9314         mutex_unlock(&dev_priv->sb_lock);
9315 }
9316
9317 #undef BEND_IDX
9318
9319 static void lpt_init_pch_refclk(struct drm_device *dev)
9320 {
9321         struct intel_encoder *encoder;
9322         bool has_vga = false;
9323
9324         for_each_intel_encoder(dev, encoder) {
9325                 switch (encoder->type) {
9326                 case INTEL_OUTPUT_ANALOG:
9327                         has_vga = true;
9328                         break;
9329                 default:
9330                         break;
9331                 }
9332         }
9333
9334         if (has_vga) {
9335                 lpt_bend_clkout_dp(to_i915(dev), 0);
9336                 lpt_enable_clkout_dp(dev, true, true);
9337         } else {
9338                 lpt_disable_clkout_dp(dev);
9339         }
9340 }
9341
9342 /*
9343  * Initialize reference clocks when the driver loads
9344  */
9345 void intel_init_pch_refclk(struct drm_device *dev)
9346 {
9347         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9348                 ironlake_init_pch_refclk(dev);
9349         else if (HAS_PCH_LPT(dev))
9350                 lpt_init_pch_refclk(dev);
9351 }
9352
9353 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9354 {
9355         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9357         int pipe = intel_crtc->pipe;
9358         uint32_t val;
9359
9360         val = 0;
9361
9362         switch (intel_crtc->config->pipe_bpp) {
9363         case 18:
9364                 val |= PIPECONF_6BPC;
9365                 break;
9366         case 24:
9367                 val |= PIPECONF_8BPC;
9368                 break;
9369         case 30:
9370                 val |= PIPECONF_10BPC;
9371                 break;
9372         case 36:
9373                 val |= PIPECONF_12BPC;
9374                 break;
9375         default:
9376                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9377                 BUG();
9378         }
9379
9380         if (intel_crtc->config->dither)
9381                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9382
9383         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9384                 val |= PIPECONF_INTERLACED_ILK;
9385         else
9386                 val |= PIPECONF_PROGRESSIVE;
9387
9388         if (intel_crtc->config->limited_color_range)
9389                 val |= PIPECONF_COLOR_RANGE_SELECT;
9390
9391         I915_WRITE(PIPECONF(pipe), val);
9392         POSTING_READ(PIPECONF(pipe));
9393 }
9394
9395 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9396 {
9397         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9399         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9400         u32 val = 0;
9401
9402         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9403                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9404
9405         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9406                 val |= PIPECONF_INTERLACED_ILK;
9407         else
9408                 val |= PIPECONF_PROGRESSIVE;
9409
9410         I915_WRITE(PIPECONF(cpu_transcoder), val);
9411         POSTING_READ(PIPECONF(cpu_transcoder));
9412 }
9413
9414 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9415 {
9416         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9418
9419         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9420                 u32 val = 0;
9421
9422                 switch (intel_crtc->config->pipe_bpp) {
9423                 case 18:
9424                         val |= PIPEMISC_DITHER_6_BPC;
9425                         break;
9426                 case 24:
9427                         val |= PIPEMISC_DITHER_8_BPC;
9428                         break;
9429                 case 30:
9430                         val |= PIPEMISC_DITHER_10_BPC;
9431                         break;
9432                 case 36:
9433                         val |= PIPEMISC_DITHER_12_BPC;
9434                         break;
9435                 default:
9436                         /* Case prevented by pipe_config_set_bpp. */
9437                         BUG();
9438                 }
9439
9440                 if (intel_crtc->config->dither)
9441                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9442
9443                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9444         }
9445 }
9446
9447 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9448 {
9449         /*
9450          * Account for spread spectrum to avoid
9451          * oversubscribing the link. Max center spread
9452          * is 2.5%; use 5% for safety's sake.
9453          */
9454         u32 bps = target_clock * bpp * 21 / 20;
9455         return DIV_ROUND_UP(bps, link_bw * 8);
9456 }
9457
9458 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9459 {
9460         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9461 }
9462
9463 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9464                                   struct intel_crtc_state *crtc_state,
9465                                   struct dpll *reduced_clock)
9466 {
9467         struct drm_crtc *crtc = &intel_crtc->base;
9468         struct drm_device *dev = crtc->dev;
9469         struct drm_i915_private *dev_priv = to_i915(dev);
9470         u32 dpll, fp, fp2;
9471         int factor;
9472
9473         /* Enable autotuning of the PLL clock (if permissible) */
9474         factor = 21;
9475         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9476                 if ((intel_panel_use_ssc(dev_priv) &&
9477                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9478                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9479                         factor = 25;
9480         } else if (crtc_state->sdvo_tv_clock)
9481                 factor = 20;
9482
9483         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9484
9485         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9486                 fp |= FP_CB_TUNE;
9487
9488         if (reduced_clock) {
9489                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9490
9491                 if (reduced_clock->m < factor * reduced_clock->n)
9492                         fp2 |= FP_CB_TUNE;
9493         } else {
9494                 fp2 = fp;
9495         }
9496
9497         dpll = 0;
9498
9499         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9500                 dpll |= DPLLB_MODE_LVDS;
9501         else
9502                 dpll |= DPLLB_MODE_DAC_SERIAL;
9503
9504         dpll |= (crtc_state->pixel_multiplier - 1)
9505                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9506
9507         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9508             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9509                 dpll |= DPLL_SDVO_HIGH_SPEED;
9510
9511         if (intel_crtc_has_dp_encoder(crtc_state))
9512                 dpll |= DPLL_SDVO_HIGH_SPEED;
9513
9514         /* compute bitmask from p1 value */
9515         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9516         /* also FPA1 */
9517         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9518
9519         switch (crtc_state->dpll.p2) {
9520         case 5:
9521                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9522                 break;
9523         case 7:
9524                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9525                 break;
9526         case 10:
9527                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9528                 break;
9529         case 14:
9530                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9531                 break;
9532         }
9533
9534         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9535             intel_panel_use_ssc(dev_priv))
9536                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9537         else
9538                 dpll |= PLL_REF_INPUT_DREFCLK;
9539
9540         dpll |= DPLL_VCO_ENABLE;
9541
9542         crtc_state->dpll_hw_state.dpll = dpll;
9543         crtc_state->dpll_hw_state.fp0 = fp;
9544         crtc_state->dpll_hw_state.fp1 = fp2;
9545 }
9546
9547 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9548                                        struct intel_crtc_state *crtc_state)
9549 {
9550         struct drm_device *dev = crtc->base.dev;
9551         struct drm_i915_private *dev_priv = to_i915(dev);
9552         struct dpll reduced_clock;
9553         bool has_reduced_clock = false;
9554         struct intel_shared_dpll *pll;
9555         const struct intel_limit *limit;
9556         int refclk = 120000;
9557
9558         memset(&crtc_state->dpll_hw_state, 0,
9559                sizeof(crtc_state->dpll_hw_state));
9560
9561         crtc->lowfreq_avail = false;
9562
9563         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9564         if (!crtc_state->has_pch_encoder)
9565                 return 0;
9566
9567         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9568                 if (intel_panel_use_ssc(dev_priv)) {
9569                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9570                                       dev_priv->vbt.lvds_ssc_freq);
9571                         refclk = dev_priv->vbt.lvds_ssc_freq;
9572                 }
9573
9574                 if (intel_is_dual_link_lvds(dev)) {
9575                         if (refclk == 100000)
9576                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9577                         else
9578                                 limit = &intel_limits_ironlake_dual_lvds;
9579                 } else {
9580                         if (refclk == 100000)
9581                                 limit = &intel_limits_ironlake_single_lvds_100m;
9582                         else
9583                                 limit = &intel_limits_ironlake_single_lvds;
9584                 }
9585         } else {
9586                 limit = &intel_limits_ironlake_dac;
9587         }
9588
9589         if (!crtc_state->clock_set &&
9590             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9591                                 refclk, NULL, &crtc_state->dpll)) {
9592                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9593                 return -EINVAL;
9594         }
9595
9596         ironlake_compute_dpll(crtc, crtc_state,
9597                               has_reduced_clock ? &reduced_clock : NULL);
9598
9599         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9600         if (pll == NULL) {
9601                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9602                                  pipe_name(crtc->pipe));
9603                 return -EINVAL;
9604         }
9605
9606         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9607             has_reduced_clock)
9608                 crtc->lowfreq_avail = true;
9609
9610         return 0;
9611 }
9612
9613 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9614                                          struct intel_link_m_n *m_n)
9615 {
9616         struct drm_device *dev = crtc->base.dev;
9617         struct drm_i915_private *dev_priv = to_i915(dev);
9618         enum pipe pipe = crtc->pipe;
9619
9620         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9621         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9622         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9623                 & ~TU_SIZE_MASK;
9624         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9625         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9626                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9627 }
9628
9629 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9630                                          enum transcoder transcoder,
9631                                          struct intel_link_m_n *m_n,
9632                                          struct intel_link_m_n *m2_n2)
9633 {
9634         struct drm_device *dev = crtc->base.dev;
9635         struct drm_i915_private *dev_priv = to_i915(dev);
9636         enum pipe pipe = crtc->pipe;
9637
9638         if (INTEL_INFO(dev)->gen >= 5) {
9639                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9640                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9641                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9642                         & ~TU_SIZE_MASK;
9643                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9644                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9645                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9646                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9647                  * gen < 8) and if DRRS is supported (to make sure the
9648                  * registers are not unnecessarily read).
9649                  */
9650                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9651                         crtc->config->has_drrs) {
9652                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9653                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9654                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9655                                         & ~TU_SIZE_MASK;
9656                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9657                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9658                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9659                 }
9660         } else {
9661                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9662                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9663                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9664                         & ~TU_SIZE_MASK;
9665                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9666                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9667                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9668         }
9669 }
9670
9671 void intel_dp_get_m_n(struct intel_crtc *crtc,
9672                       struct intel_crtc_state *pipe_config)
9673 {
9674         if (pipe_config->has_pch_encoder)
9675                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9676         else
9677                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9678                                              &pipe_config->dp_m_n,
9679                                              &pipe_config->dp_m2_n2);
9680 }
9681
9682 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9683                                         struct intel_crtc_state *pipe_config)
9684 {
9685         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9686                                      &pipe_config->fdi_m_n, NULL);
9687 }
9688
9689 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9690                                     struct intel_crtc_state *pipe_config)
9691 {
9692         struct drm_device *dev = crtc->base.dev;
9693         struct drm_i915_private *dev_priv = to_i915(dev);
9694         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9695         uint32_t ps_ctrl = 0;
9696         int id = -1;
9697         int i;
9698
9699         /* find scaler attached to this pipe */
9700         for (i = 0; i < crtc->num_scalers; i++) {
9701                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9702                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9703                         id = i;
9704                         pipe_config->pch_pfit.enabled = true;
9705                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9706                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9707                         break;
9708                 }
9709         }
9710
9711         scaler_state->scaler_id = id;
9712         if (id >= 0) {
9713                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9714         } else {
9715                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9716         }
9717 }
9718
9719 static void
9720 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9721                                  struct intel_initial_plane_config *plane_config)
9722 {
9723         struct drm_device *dev = crtc->base.dev;
9724         struct drm_i915_private *dev_priv = to_i915(dev);
9725         u32 val, base, offset, stride_mult, tiling;
9726         int pipe = crtc->pipe;
9727         int fourcc, pixel_format;
9728         unsigned int aligned_height;
9729         struct drm_framebuffer *fb;
9730         struct intel_framebuffer *intel_fb;
9731
9732         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9733         if (!intel_fb) {
9734                 DRM_DEBUG_KMS("failed to alloc fb\n");
9735                 return;
9736         }
9737
9738         fb = &intel_fb->base;
9739
9740         val = I915_READ(PLANE_CTL(pipe, 0));
9741         if (!(val & PLANE_CTL_ENABLE))
9742                 goto error;
9743
9744         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9745         fourcc = skl_format_to_fourcc(pixel_format,
9746                                       val & PLANE_CTL_ORDER_RGBX,
9747                                       val & PLANE_CTL_ALPHA_MASK);
9748         fb->pixel_format = fourcc;
9749         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9750
9751         tiling = val & PLANE_CTL_TILED_MASK;
9752         switch (tiling) {
9753         case PLANE_CTL_TILED_LINEAR:
9754                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9755                 break;
9756         case PLANE_CTL_TILED_X:
9757                 plane_config->tiling = I915_TILING_X;
9758                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9759                 break;
9760         case PLANE_CTL_TILED_Y:
9761                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9762                 break;
9763         case PLANE_CTL_TILED_YF:
9764                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9765                 break;
9766         default:
9767                 MISSING_CASE(tiling);
9768                 goto error;
9769         }
9770
9771         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9772         plane_config->base = base;
9773
9774         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9775
9776         val = I915_READ(PLANE_SIZE(pipe, 0));
9777         fb->height = ((val >> 16) & 0xfff) + 1;
9778         fb->width = ((val >> 0) & 0x1fff) + 1;
9779
9780         val = I915_READ(PLANE_STRIDE(pipe, 0));
9781         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9782                                                 fb->pixel_format);
9783         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9784
9785         aligned_height = intel_fb_align_height(dev, fb->height,
9786                                                fb->pixel_format,
9787                                                fb->modifier[0]);
9788
9789         plane_config->size = fb->pitches[0] * aligned_height;
9790
9791         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9792                       pipe_name(pipe), fb->width, fb->height,
9793                       fb->bits_per_pixel, base, fb->pitches[0],
9794                       plane_config->size);
9795
9796         plane_config->fb = intel_fb;
9797         return;
9798
9799 error:
9800         kfree(intel_fb);
9801 }
9802
9803 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9804                                      struct intel_crtc_state *pipe_config)
9805 {
9806         struct drm_device *dev = crtc->base.dev;
9807         struct drm_i915_private *dev_priv = to_i915(dev);
9808         uint32_t tmp;
9809
9810         tmp = I915_READ(PF_CTL(crtc->pipe));
9811
9812         if (tmp & PF_ENABLE) {
9813                 pipe_config->pch_pfit.enabled = true;
9814                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9815                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9816
9817                 /* We currently do not free assignements of panel fitters on
9818                  * ivb/hsw (since we don't use the higher upscaling modes which
9819                  * differentiates them) so just WARN about this case for now. */
9820                 if (IS_GEN7(dev)) {
9821                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9822                                 PF_PIPE_SEL_IVB(crtc->pipe));
9823                 }
9824         }
9825 }
9826
9827 static void
9828 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9829                                   struct intel_initial_plane_config *plane_config)
9830 {
9831         struct drm_device *dev = crtc->base.dev;
9832         struct drm_i915_private *dev_priv = to_i915(dev);
9833         u32 val, base, offset;
9834         int pipe = crtc->pipe;
9835         int fourcc, pixel_format;
9836         unsigned int aligned_height;
9837         struct drm_framebuffer *fb;
9838         struct intel_framebuffer *intel_fb;
9839
9840         val = I915_READ(DSPCNTR(pipe));
9841         if (!(val & DISPLAY_PLANE_ENABLE))
9842                 return;
9843
9844         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9845         if (!intel_fb) {
9846                 DRM_DEBUG_KMS("failed to alloc fb\n");
9847                 return;
9848         }
9849
9850         fb = &intel_fb->base;
9851
9852         if (INTEL_INFO(dev)->gen >= 4) {
9853                 if (val & DISPPLANE_TILED) {
9854                         plane_config->tiling = I915_TILING_X;
9855                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9856                 }
9857         }
9858
9859         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9860         fourcc = i9xx_format_to_fourcc(pixel_format);
9861         fb->pixel_format = fourcc;
9862         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9863
9864         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9865         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9866                 offset = I915_READ(DSPOFFSET(pipe));
9867         } else {
9868                 if (plane_config->tiling)
9869                         offset = I915_READ(DSPTILEOFF(pipe));
9870                 else
9871                         offset = I915_READ(DSPLINOFF(pipe));
9872         }
9873         plane_config->base = base;
9874
9875         val = I915_READ(PIPESRC(pipe));
9876         fb->width = ((val >> 16) & 0xfff) + 1;
9877         fb->height = ((val >> 0) & 0xfff) + 1;
9878
9879         val = I915_READ(DSPSTRIDE(pipe));
9880         fb->pitches[0] = val & 0xffffffc0;
9881
9882         aligned_height = intel_fb_align_height(dev, fb->height,
9883                                                fb->pixel_format,
9884                                                fb->modifier[0]);
9885
9886         plane_config->size = fb->pitches[0] * aligned_height;
9887
9888         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9889                       pipe_name(pipe), fb->width, fb->height,
9890                       fb->bits_per_pixel, base, fb->pitches[0],
9891                       plane_config->size);
9892
9893         plane_config->fb = intel_fb;
9894 }
9895
9896 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9897                                      struct intel_crtc_state *pipe_config)
9898 {
9899         struct drm_device *dev = crtc->base.dev;
9900         struct drm_i915_private *dev_priv = to_i915(dev);
9901         enum intel_display_power_domain power_domain;
9902         uint32_t tmp;
9903         bool ret;
9904
9905         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9906         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9907                 return false;
9908
9909         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9910         pipe_config->shared_dpll = NULL;
9911
9912         ret = false;
9913         tmp = I915_READ(PIPECONF(crtc->pipe));
9914         if (!(tmp & PIPECONF_ENABLE))
9915                 goto out;
9916
9917         switch (tmp & PIPECONF_BPC_MASK) {
9918         case PIPECONF_6BPC:
9919                 pipe_config->pipe_bpp = 18;
9920                 break;
9921         case PIPECONF_8BPC:
9922                 pipe_config->pipe_bpp = 24;
9923                 break;
9924         case PIPECONF_10BPC:
9925                 pipe_config->pipe_bpp = 30;
9926                 break;
9927         case PIPECONF_12BPC:
9928                 pipe_config->pipe_bpp = 36;
9929                 break;
9930         default:
9931                 break;
9932         }
9933
9934         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9935                 pipe_config->limited_color_range = true;
9936
9937         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9938                 struct intel_shared_dpll *pll;
9939                 enum intel_dpll_id pll_id;
9940
9941                 pipe_config->has_pch_encoder = true;
9942
9943                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9944                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9945                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9946
9947                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9948
9949                 if (HAS_PCH_IBX(dev_priv)) {
9950                         /*
9951                          * The pipe->pch transcoder and pch transcoder->pll
9952                          * mapping is fixed.
9953                          */
9954                         pll_id = (enum intel_dpll_id) crtc->pipe;
9955                 } else {
9956                         tmp = I915_READ(PCH_DPLL_SEL);
9957                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9958                                 pll_id = DPLL_ID_PCH_PLL_B;
9959                         else
9960                                 pll_id= DPLL_ID_PCH_PLL_A;
9961                 }
9962
9963                 pipe_config->shared_dpll =
9964                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9965                 pll = pipe_config->shared_dpll;
9966
9967                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9968                                                  &pipe_config->dpll_hw_state));
9969
9970                 tmp = pipe_config->dpll_hw_state.dpll;
9971                 pipe_config->pixel_multiplier =
9972                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9973                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9974
9975                 ironlake_pch_clock_get(crtc, pipe_config);
9976         } else {
9977                 pipe_config->pixel_multiplier = 1;
9978         }
9979
9980         intel_get_pipe_timings(crtc, pipe_config);
9981         intel_get_pipe_src_size(crtc, pipe_config);
9982
9983         ironlake_get_pfit_config(crtc, pipe_config);
9984
9985         ret = true;
9986
9987 out:
9988         intel_display_power_put(dev_priv, power_domain);
9989
9990         return ret;
9991 }
9992
9993 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9994 {
9995         struct drm_device *dev = &dev_priv->drm;
9996         struct intel_crtc *crtc;
9997
9998         for_each_intel_crtc(dev, crtc)
9999                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
10000                      pipe_name(crtc->pipe));
10001
10002         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10003         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10004         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10005         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10006         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10007         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10008              "CPU PWM1 enabled\n");
10009         if (IS_HASWELL(dev))
10010                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10011                      "CPU PWM2 enabled\n");
10012         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10013              "PCH PWM1 enabled\n");
10014         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10015              "Utility pin enabled\n");
10016         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10017
10018         /*
10019          * In theory we can still leave IRQs enabled, as long as only the HPD
10020          * interrupts remain enabled. We used to check for that, but since it's
10021          * gen-specific and since we only disable LCPLL after we fully disable
10022          * the interrupts, the check below should be enough.
10023          */
10024         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10025 }
10026
10027 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10028 {
10029         struct drm_device *dev = &dev_priv->drm;
10030
10031         if (IS_HASWELL(dev))
10032                 return I915_READ(D_COMP_HSW);
10033         else
10034                 return I915_READ(D_COMP_BDW);
10035 }
10036
10037 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10038 {
10039         struct drm_device *dev = &dev_priv->drm;
10040
10041         if (IS_HASWELL(dev)) {
10042                 mutex_lock(&dev_priv->rps.hw_lock);
10043                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10044                                             val))
10045                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10046                 mutex_unlock(&dev_priv->rps.hw_lock);
10047         } else {
10048                 I915_WRITE(D_COMP_BDW, val);
10049                 POSTING_READ(D_COMP_BDW);
10050         }
10051 }
10052
10053 /*
10054  * This function implements pieces of two sequences from BSpec:
10055  * - Sequence for display software to disable LCPLL
10056  * - Sequence for display software to allow package C8+
10057  * The steps implemented here are just the steps that actually touch the LCPLL
10058  * register. Callers should take care of disabling all the display engine
10059  * functions, doing the mode unset, fixing interrupts, etc.
10060  */
10061 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10062                               bool switch_to_fclk, bool allow_power_down)
10063 {
10064         uint32_t val;
10065
10066         assert_can_disable_lcpll(dev_priv);
10067
10068         val = I915_READ(LCPLL_CTL);
10069
10070         if (switch_to_fclk) {
10071                 val |= LCPLL_CD_SOURCE_FCLK;
10072                 I915_WRITE(LCPLL_CTL, val);
10073
10074                 if (wait_for_us(I915_READ(LCPLL_CTL) &
10075                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10076                         DRM_ERROR("Switching to FCLK failed\n");
10077
10078                 val = I915_READ(LCPLL_CTL);
10079         }
10080
10081         val |= LCPLL_PLL_DISABLE;
10082         I915_WRITE(LCPLL_CTL, val);
10083         POSTING_READ(LCPLL_CTL);
10084
10085         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10086                 DRM_ERROR("LCPLL still locked\n");
10087
10088         val = hsw_read_dcomp(dev_priv);
10089         val |= D_COMP_COMP_DISABLE;
10090         hsw_write_dcomp(dev_priv, val);
10091         ndelay(100);
10092
10093         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10094                      1))
10095                 DRM_ERROR("D_COMP RCOMP still in progress\n");
10096
10097         if (allow_power_down) {
10098                 val = I915_READ(LCPLL_CTL);
10099                 val |= LCPLL_POWER_DOWN_ALLOW;
10100                 I915_WRITE(LCPLL_CTL, val);
10101                 POSTING_READ(LCPLL_CTL);
10102         }
10103 }
10104
10105 /*
10106  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10107  * source.
10108  */
10109 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10110 {
10111         uint32_t val;
10112
10113         val = I915_READ(LCPLL_CTL);
10114
10115         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10116                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10117                 return;
10118
10119         /*
10120          * Make sure we're not on PC8 state before disabling PC8, otherwise
10121          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10122          */
10123         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10124
10125         if (val & LCPLL_POWER_DOWN_ALLOW) {
10126                 val &= ~LCPLL_POWER_DOWN_ALLOW;
10127                 I915_WRITE(LCPLL_CTL, val);
10128                 POSTING_READ(LCPLL_CTL);
10129         }
10130
10131         val = hsw_read_dcomp(dev_priv);
10132         val |= D_COMP_COMP_FORCE;
10133         val &= ~D_COMP_COMP_DISABLE;
10134         hsw_write_dcomp(dev_priv, val);
10135
10136         val = I915_READ(LCPLL_CTL);
10137         val &= ~LCPLL_PLL_DISABLE;
10138         I915_WRITE(LCPLL_CTL, val);
10139
10140         if (intel_wait_for_register(dev_priv,
10141                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10142                                     5))
10143                 DRM_ERROR("LCPLL not locked yet\n");
10144
10145         if (val & LCPLL_CD_SOURCE_FCLK) {
10146                 val = I915_READ(LCPLL_CTL);
10147                 val &= ~LCPLL_CD_SOURCE_FCLK;
10148                 I915_WRITE(LCPLL_CTL, val);
10149
10150                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10151                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10152                         DRM_ERROR("Switching back to LCPLL failed\n");
10153         }
10154
10155         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10156         intel_update_cdclk(&dev_priv->drm);
10157 }
10158
10159 /*
10160  * Package states C8 and deeper are really deep PC states that can only be
10161  * reached when all the devices on the system allow it, so even if the graphics
10162  * device allows PC8+, it doesn't mean the system will actually get to these
10163  * states. Our driver only allows PC8+ when going into runtime PM.
10164  *
10165  * The requirements for PC8+ are that all the outputs are disabled, the power
10166  * well is disabled and most interrupts are disabled, and these are also
10167  * requirements for runtime PM. When these conditions are met, we manually do
10168  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10169  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10170  * hang the machine.
10171  *
10172  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10173  * the state of some registers, so when we come back from PC8+ we need to
10174  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10175  * need to take care of the registers kept by RC6. Notice that this happens even
10176  * if we don't put the device in PCI D3 state (which is what currently happens
10177  * because of the runtime PM support).
10178  *
10179  * For more, read "Display Sequences for Package C8" on the hardware
10180  * documentation.
10181  */
10182 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10183 {
10184         struct drm_device *dev = &dev_priv->drm;
10185         uint32_t val;
10186
10187         DRM_DEBUG_KMS("Enabling package C8+\n");
10188
10189         if (HAS_PCH_LPT_LP(dev)) {
10190                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10191                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10192                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10193         }
10194
10195         lpt_disable_clkout_dp(dev);
10196         hsw_disable_lcpll(dev_priv, true, true);
10197 }
10198
10199 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10200 {
10201         struct drm_device *dev = &dev_priv->drm;
10202         uint32_t val;
10203
10204         DRM_DEBUG_KMS("Disabling package C8+\n");
10205
10206         hsw_restore_lcpll(dev_priv);
10207         lpt_init_pch_refclk(dev);
10208
10209         if (HAS_PCH_LPT_LP(dev)) {
10210                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10211                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10212                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10213         }
10214 }
10215
10216 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10217 {
10218         struct drm_device *dev = old_state->dev;
10219         struct intel_atomic_state *old_intel_state =
10220                 to_intel_atomic_state(old_state);
10221         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10222
10223         bxt_set_cdclk(to_i915(dev), req_cdclk);
10224 }
10225
10226 /* compute the max rate for new configuration */
10227 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10228 {
10229         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10230         struct drm_i915_private *dev_priv = to_i915(state->dev);
10231         struct drm_crtc *crtc;
10232         struct drm_crtc_state *cstate;
10233         struct intel_crtc_state *crtc_state;
10234         unsigned max_pixel_rate = 0, i;
10235         enum pipe pipe;
10236
10237         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10238                sizeof(intel_state->min_pixclk));
10239
10240         for_each_crtc_in_state(state, crtc, cstate, i) {
10241                 int pixel_rate;
10242
10243                 crtc_state = to_intel_crtc_state(cstate);
10244                 if (!crtc_state->base.enable) {
10245                         intel_state->min_pixclk[i] = 0;
10246                         continue;
10247                 }
10248
10249                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10250
10251                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10252                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10253                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10254
10255                 intel_state->min_pixclk[i] = pixel_rate;
10256         }
10257
10258         for_each_pipe(dev_priv, pipe)
10259                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10260
10261         return max_pixel_rate;
10262 }
10263
10264 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10265 {
10266         struct drm_i915_private *dev_priv = to_i915(dev);
10267         uint32_t val, data;
10268         int ret;
10269
10270         if (WARN((I915_READ(LCPLL_CTL) &
10271                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10272                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10273                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10274                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10275                  "trying to change cdclk frequency with cdclk not enabled\n"))
10276                 return;
10277
10278         mutex_lock(&dev_priv->rps.hw_lock);
10279         ret = sandybridge_pcode_write(dev_priv,
10280                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10281         mutex_unlock(&dev_priv->rps.hw_lock);
10282         if (ret) {
10283                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10284                 return;
10285         }
10286
10287         val = I915_READ(LCPLL_CTL);
10288         val |= LCPLL_CD_SOURCE_FCLK;
10289         I915_WRITE(LCPLL_CTL, val);
10290
10291         if (wait_for_us(I915_READ(LCPLL_CTL) &
10292                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10293                 DRM_ERROR("Switching to FCLK failed\n");
10294
10295         val = I915_READ(LCPLL_CTL);
10296         val &= ~LCPLL_CLK_FREQ_MASK;
10297
10298         switch (cdclk) {
10299         case 450000:
10300                 val |= LCPLL_CLK_FREQ_450;
10301                 data = 0;
10302                 break;
10303         case 540000:
10304                 val |= LCPLL_CLK_FREQ_54O_BDW;
10305                 data = 1;
10306                 break;
10307         case 337500:
10308                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10309                 data = 2;
10310                 break;
10311         case 675000:
10312                 val |= LCPLL_CLK_FREQ_675_BDW;
10313                 data = 3;
10314                 break;
10315         default:
10316                 WARN(1, "invalid cdclk frequency\n");
10317                 return;
10318         }
10319
10320         I915_WRITE(LCPLL_CTL, val);
10321
10322         val = I915_READ(LCPLL_CTL);
10323         val &= ~LCPLL_CD_SOURCE_FCLK;
10324         I915_WRITE(LCPLL_CTL, val);
10325
10326         if (wait_for_us((I915_READ(LCPLL_CTL) &
10327                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10328                 DRM_ERROR("Switching back to LCPLL failed\n");
10329
10330         mutex_lock(&dev_priv->rps.hw_lock);
10331         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10332         mutex_unlock(&dev_priv->rps.hw_lock);
10333
10334         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10335
10336         intel_update_cdclk(dev);
10337
10338         WARN(cdclk != dev_priv->cdclk_freq,
10339              "cdclk requested %d kHz but got %d kHz\n",
10340              cdclk, dev_priv->cdclk_freq);
10341 }
10342
10343 static int broadwell_calc_cdclk(int max_pixclk)
10344 {
10345         if (max_pixclk > 540000)
10346                 return 675000;
10347         else if (max_pixclk > 450000)
10348                 return 540000;
10349         else if (max_pixclk > 337500)
10350                 return 450000;
10351         else
10352                 return 337500;
10353 }
10354
10355 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10356 {
10357         struct drm_i915_private *dev_priv = to_i915(state->dev);
10358         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10359         int max_pixclk = ilk_max_pixel_rate(state);
10360         int cdclk;
10361
10362         /*
10363          * FIXME should also account for plane ratio
10364          * once 64bpp pixel formats are supported.
10365          */
10366         cdclk = broadwell_calc_cdclk(max_pixclk);
10367
10368         if (cdclk > dev_priv->max_cdclk_freq) {
10369                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10370                               cdclk, dev_priv->max_cdclk_freq);
10371                 return -EINVAL;
10372         }
10373
10374         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10375         if (!intel_state->active_crtcs)
10376                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10377
10378         return 0;
10379 }
10380
10381 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10382 {
10383         struct drm_device *dev = old_state->dev;
10384         struct intel_atomic_state *old_intel_state =
10385                 to_intel_atomic_state(old_state);
10386         unsigned req_cdclk = old_intel_state->dev_cdclk;
10387
10388         broadwell_set_cdclk(dev, req_cdclk);
10389 }
10390
10391 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10392 {
10393         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10394         struct drm_i915_private *dev_priv = to_i915(state->dev);
10395         const int max_pixclk = ilk_max_pixel_rate(state);
10396         int vco = intel_state->cdclk_pll_vco;
10397         int cdclk;
10398
10399         /*
10400          * FIXME should also account for plane ratio
10401          * once 64bpp pixel formats are supported.
10402          */
10403         cdclk = skl_calc_cdclk(max_pixclk, vco);
10404
10405         /*
10406          * FIXME move the cdclk caclulation to
10407          * compute_config() so we can fail gracegully.
10408          */
10409         if (cdclk > dev_priv->max_cdclk_freq) {
10410                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10411                           cdclk, dev_priv->max_cdclk_freq);
10412                 cdclk = dev_priv->max_cdclk_freq;
10413         }
10414
10415         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10416         if (!intel_state->active_crtcs)
10417                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10418
10419         return 0;
10420 }
10421
10422 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10423 {
10424         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10425         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10426         unsigned int req_cdclk = intel_state->dev_cdclk;
10427         unsigned int req_vco = intel_state->cdclk_pll_vco;
10428
10429         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10430 }
10431
10432 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10433                                       struct intel_crtc_state *crtc_state)
10434 {
10435         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10436                 if (!intel_ddi_pll_select(crtc, crtc_state))
10437                         return -EINVAL;
10438         }
10439
10440         crtc->lowfreq_avail = false;
10441
10442         return 0;
10443 }
10444
10445 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10446                                 enum port port,
10447                                 struct intel_crtc_state *pipe_config)
10448 {
10449         enum intel_dpll_id id;
10450
10451         switch (port) {
10452         case PORT_A:
10453                 id = DPLL_ID_SKL_DPLL0;
10454                 break;
10455         case PORT_B:
10456                 id = DPLL_ID_SKL_DPLL1;
10457                 break;
10458         case PORT_C:
10459                 id = DPLL_ID_SKL_DPLL2;
10460                 break;
10461         default:
10462                 DRM_ERROR("Incorrect port type\n");
10463                 return;
10464         }
10465
10466         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10467 }
10468
10469 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10470                                 enum port port,
10471                                 struct intel_crtc_state *pipe_config)
10472 {
10473         enum intel_dpll_id id;
10474         u32 temp;
10475
10476         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10477         id = temp >> (port * 3 + 1);
10478
10479         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10480                 return;
10481
10482         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10483 }
10484
10485 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10486                                 enum port port,
10487                                 struct intel_crtc_state *pipe_config)
10488 {
10489         enum intel_dpll_id id;
10490         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10491
10492         switch (ddi_pll_sel) {
10493         case PORT_CLK_SEL_WRPLL1:
10494                 id = DPLL_ID_WRPLL1;
10495                 break;
10496         case PORT_CLK_SEL_WRPLL2:
10497                 id = DPLL_ID_WRPLL2;
10498                 break;
10499         case PORT_CLK_SEL_SPLL:
10500                 id = DPLL_ID_SPLL;
10501                 break;
10502         case PORT_CLK_SEL_LCPLL_810:
10503                 id = DPLL_ID_LCPLL_810;
10504                 break;
10505         case PORT_CLK_SEL_LCPLL_1350:
10506                 id = DPLL_ID_LCPLL_1350;
10507                 break;
10508         case PORT_CLK_SEL_LCPLL_2700:
10509                 id = DPLL_ID_LCPLL_2700;
10510                 break;
10511         default:
10512                 MISSING_CASE(ddi_pll_sel);
10513                 /* fall through */
10514         case PORT_CLK_SEL_NONE:
10515                 return;
10516         }
10517
10518         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10519 }
10520
10521 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10522                                      struct intel_crtc_state *pipe_config,
10523                                      unsigned long *power_domain_mask)
10524 {
10525         struct drm_device *dev = crtc->base.dev;
10526         struct drm_i915_private *dev_priv = to_i915(dev);
10527         enum intel_display_power_domain power_domain;
10528         u32 tmp;
10529
10530         /*
10531          * The pipe->transcoder mapping is fixed with the exception of the eDP
10532          * transcoder handled below.
10533          */
10534         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10535
10536         /*
10537          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10538          * consistency and less surprising code; it's in always on power).
10539          */
10540         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10541         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10542                 enum pipe trans_edp_pipe;
10543                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10544                 default:
10545                         WARN(1, "unknown pipe linked to edp transcoder\n");
10546                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10547                 case TRANS_DDI_EDP_INPUT_A_ON:
10548                         trans_edp_pipe = PIPE_A;
10549                         break;
10550                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10551                         trans_edp_pipe = PIPE_B;
10552                         break;
10553                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10554                         trans_edp_pipe = PIPE_C;
10555                         break;
10556                 }
10557
10558                 if (trans_edp_pipe == crtc->pipe)
10559                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10560         }
10561
10562         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10563         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10564                 return false;
10565         *power_domain_mask |= BIT(power_domain);
10566
10567         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10568
10569         return tmp & PIPECONF_ENABLE;
10570 }
10571
10572 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10573                                          struct intel_crtc_state *pipe_config,
10574                                          unsigned long *power_domain_mask)
10575 {
10576         struct drm_device *dev = crtc->base.dev;
10577         struct drm_i915_private *dev_priv = to_i915(dev);
10578         enum intel_display_power_domain power_domain;
10579         enum port port;
10580         enum transcoder cpu_transcoder;
10581         u32 tmp;
10582
10583         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10584                 if (port == PORT_A)
10585                         cpu_transcoder = TRANSCODER_DSI_A;
10586                 else
10587                         cpu_transcoder = TRANSCODER_DSI_C;
10588
10589                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10590                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10591                         continue;
10592                 *power_domain_mask |= BIT(power_domain);
10593
10594                 /*
10595                  * The PLL needs to be enabled with a valid divider
10596                  * configuration, otherwise accessing DSI registers will hang
10597                  * the machine. See BSpec North Display Engine
10598                  * registers/MIPI[BXT]. We can break out here early, since we
10599                  * need the same DSI PLL to be enabled for both DSI ports.
10600                  */
10601                 if (!intel_dsi_pll_is_enabled(dev_priv))
10602                         break;
10603
10604                 /* XXX: this works for video mode only */
10605                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10606                 if (!(tmp & DPI_ENABLE))
10607                         continue;
10608
10609                 tmp = I915_READ(MIPI_CTRL(port));
10610                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10611                         continue;
10612
10613                 pipe_config->cpu_transcoder = cpu_transcoder;
10614                 break;
10615         }
10616
10617         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10618 }
10619
10620 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10621                                        struct intel_crtc_state *pipe_config)
10622 {
10623         struct drm_device *dev = crtc->base.dev;
10624         struct drm_i915_private *dev_priv = to_i915(dev);
10625         struct intel_shared_dpll *pll;
10626         enum port port;
10627         uint32_t tmp;
10628
10629         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10630
10631         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10632
10633         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10634                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10635         else if (IS_BROXTON(dev))
10636                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10637         else
10638                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10639
10640         pll = pipe_config->shared_dpll;
10641         if (pll) {
10642                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10643                                                  &pipe_config->dpll_hw_state));
10644         }
10645
10646         /*
10647          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10648          * DDI E. So just check whether this pipe is wired to DDI E and whether
10649          * the PCH transcoder is on.
10650          */
10651         if (INTEL_INFO(dev)->gen < 9 &&
10652             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10653                 pipe_config->has_pch_encoder = true;
10654
10655                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10656                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10657                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10658
10659                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10660         }
10661 }
10662
10663 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10664                                     struct intel_crtc_state *pipe_config)
10665 {
10666         struct drm_device *dev = crtc->base.dev;
10667         struct drm_i915_private *dev_priv = to_i915(dev);
10668         enum intel_display_power_domain power_domain;
10669         unsigned long power_domain_mask;
10670         bool active;
10671
10672         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10673         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10674                 return false;
10675         power_domain_mask = BIT(power_domain);
10676
10677         pipe_config->shared_dpll = NULL;
10678
10679         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10680
10681         if (IS_BROXTON(dev_priv) &&
10682             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10683                 WARN_ON(active);
10684                 active = true;
10685         }
10686
10687         if (!active)
10688                 goto out;
10689
10690         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10691                 haswell_get_ddi_port_state(crtc, pipe_config);
10692                 intel_get_pipe_timings(crtc, pipe_config);
10693         }
10694
10695         intel_get_pipe_src_size(crtc, pipe_config);
10696
10697         pipe_config->gamma_mode =
10698                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10699
10700         if (INTEL_INFO(dev)->gen >= 9) {
10701                 skl_init_scalers(dev, crtc, pipe_config);
10702         }
10703
10704         if (INTEL_INFO(dev)->gen >= 9) {
10705                 pipe_config->scaler_state.scaler_id = -1;
10706                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10707         }
10708
10709         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10710         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10711                 power_domain_mask |= BIT(power_domain);
10712                 if (INTEL_INFO(dev)->gen >= 9)
10713                         skylake_get_pfit_config(crtc, pipe_config);
10714                 else
10715                         ironlake_get_pfit_config(crtc, pipe_config);
10716         }
10717
10718         if (IS_HASWELL(dev))
10719                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10720                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10721
10722         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10723             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10724                 pipe_config->pixel_multiplier =
10725                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10726         } else {
10727                 pipe_config->pixel_multiplier = 1;
10728         }
10729
10730 out:
10731         for_each_power_domain(power_domain, power_domain_mask)
10732                 intel_display_power_put(dev_priv, power_domain);
10733
10734         return active;
10735 }
10736
10737 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10738                                const struct intel_plane_state *plane_state)
10739 {
10740         struct drm_device *dev = crtc->dev;
10741         struct drm_i915_private *dev_priv = to_i915(dev);
10742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10743         uint32_t cntl = 0, size = 0;
10744
10745         if (plane_state && plane_state->base.visible) {
10746                 unsigned int width = plane_state->base.crtc_w;
10747                 unsigned int height = plane_state->base.crtc_h;
10748                 unsigned int stride = roundup_pow_of_two(width) * 4;
10749
10750                 switch (stride) {
10751                 default:
10752                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10753                                   width, stride);
10754                         stride = 256;
10755                         /* fallthrough */
10756                 case 256:
10757                 case 512:
10758                 case 1024:
10759                 case 2048:
10760                         break;
10761                 }
10762
10763                 cntl |= CURSOR_ENABLE |
10764                         CURSOR_GAMMA_ENABLE |
10765                         CURSOR_FORMAT_ARGB |
10766                         CURSOR_STRIDE(stride);
10767
10768                 size = (height << 12) | width;
10769         }
10770
10771         if (intel_crtc->cursor_cntl != 0 &&
10772             (intel_crtc->cursor_base != base ||
10773              intel_crtc->cursor_size != size ||
10774              intel_crtc->cursor_cntl != cntl)) {
10775                 /* On these chipsets we can only modify the base/size/stride
10776                  * whilst the cursor is disabled.
10777                  */
10778                 I915_WRITE(CURCNTR(PIPE_A), 0);
10779                 POSTING_READ(CURCNTR(PIPE_A));
10780                 intel_crtc->cursor_cntl = 0;
10781         }
10782
10783         if (intel_crtc->cursor_base != base) {
10784                 I915_WRITE(CURBASE(PIPE_A), base);
10785                 intel_crtc->cursor_base = base;
10786         }
10787
10788         if (intel_crtc->cursor_size != size) {
10789                 I915_WRITE(CURSIZE, size);
10790                 intel_crtc->cursor_size = size;
10791         }
10792
10793         if (intel_crtc->cursor_cntl != cntl) {
10794                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10795                 POSTING_READ(CURCNTR(PIPE_A));
10796                 intel_crtc->cursor_cntl = cntl;
10797         }
10798 }
10799
10800 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10801                                const struct intel_plane_state *plane_state)
10802 {
10803         struct drm_device *dev = crtc->dev;
10804         struct drm_i915_private *dev_priv = to_i915(dev);
10805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10806         const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
10807         int pipe = intel_crtc->pipe;
10808         uint32_t cntl = 0;
10809
10810         if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
10811                 skl_write_cursor_wm(intel_crtc, wm);
10812
10813         if (plane_state && plane_state->base.visible) {
10814                 cntl = MCURSOR_GAMMA_ENABLE;
10815                 switch (plane_state->base.crtc_w) {
10816                         case 64:
10817                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10818                                 break;
10819                         case 128:
10820                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10821                                 break;
10822                         case 256:
10823                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10824                                 break;
10825                         default:
10826                                 MISSING_CASE(plane_state->base.crtc_w);
10827                                 return;
10828                 }
10829                 cntl |= pipe << 28; /* Connect to correct pipe */
10830
10831                 if (HAS_DDI(dev))
10832                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10833
10834                 if (plane_state->base.rotation == DRM_ROTATE_180)
10835                         cntl |= CURSOR_ROTATE_180;
10836         }
10837
10838         if (intel_crtc->cursor_cntl != cntl) {
10839                 I915_WRITE(CURCNTR(pipe), cntl);
10840                 POSTING_READ(CURCNTR(pipe));
10841                 intel_crtc->cursor_cntl = cntl;
10842         }
10843
10844         /* and commit changes on next vblank */
10845         I915_WRITE(CURBASE(pipe), base);
10846         POSTING_READ(CURBASE(pipe));
10847
10848         intel_crtc->cursor_base = base;
10849 }
10850
10851 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10852 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10853                                      const struct intel_plane_state *plane_state)
10854 {
10855         struct drm_device *dev = crtc->dev;
10856         struct drm_i915_private *dev_priv = to_i915(dev);
10857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10858         int pipe = intel_crtc->pipe;
10859         u32 base = intel_crtc->cursor_addr;
10860         u32 pos = 0;
10861
10862         if (plane_state) {
10863                 int x = plane_state->base.crtc_x;
10864                 int y = plane_state->base.crtc_y;
10865
10866                 if (x < 0) {
10867                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10868                         x = -x;
10869                 }
10870                 pos |= x << CURSOR_X_SHIFT;
10871
10872                 if (y < 0) {
10873                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10874                         y = -y;
10875                 }
10876                 pos |= y << CURSOR_Y_SHIFT;
10877
10878                 /* ILK+ do this automagically */
10879                 if (HAS_GMCH_DISPLAY(dev) &&
10880                     plane_state->base.rotation == DRM_ROTATE_180) {
10881                         base += (plane_state->base.crtc_h *
10882                                  plane_state->base.crtc_w - 1) * 4;
10883                 }
10884         }
10885
10886         I915_WRITE(CURPOS(pipe), pos);
10887
10888         if (IS_845G(dev) || IS_I865G(dev))
10889                 i845_update_cursor(crtc, base, plane_state);
10890         else
10891                 i9xx_update_cursor(crtc, base, plane_state);
10892 }
10893
10894 static bool cursor_size_ok(struct drm_device *dev,
10895                            uint32_t width, uint32_t height)
10896 {
10897         if (width == 0 || height == 0)
10898                 return false;
10899
10900         /*
10901          * 845g/865g are special in that they are only limited by
10902          * the width of their cursors, the height is arbitrary up to
10903          * the precision of the register. Everything else requires
10904          * square cursors, limited to a few power-of-two sizes.
10905          */
10906         if (IS_845G(dev) || IS_I865G(dev)) {
10907                 if ((width & 63) != 0)
10908                         return false;
10909
10910                 if (width > (IS_845G(dev) ? 64 : 512))
10911                         return false;
10912
10913                 if (height > 1023)
10914                         return false;
10915         } else {
10916                 switch (width | height) {
10917                 case 256:
10918                 case 128:
10919                         if (IS_GEN2(dev))
10920                                 return false;
10921                 case 64:
10922                         break;
10923                 default:
10924                         return false;
10925                 }
10926         }
10927
10928         return true;
10929 }
10930
10931 /* VESA 640x480x72Hz mode to set on the pipe */
10932 static struct drm_display_mode load_detect_mode = {
10933         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10934                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10935 };
10936
10937 struct drm_framebuffer *
10938 __intel_framebuffer_create(struct drm_device *dev,
10939                            struct drm_mode_fb_cmd2 *mode_cmd,
10940                            struct drm_i915_gem_object *obj)
10941 {
10942         struct intel_framebuffer *intel_fb;
10943         int ret;
10944
10945         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10946         if (!intel_fb)
10947                 return ERR_PTR(-ENOMEM);
10948
10949         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10950         if (ret)
10951                 goto err;
10952
10953         return &intel_fb->base;
10954
10955 err:
10956         kfree(intel_fb);
10957         return ERR_PTR(ret);
10958 }
10959
10960 static struct drm_framebuffer *
10961 intel_framebuffer_create(struct drm_device *dev,
10962                          struct drm_mode_fb_cmd2 *mode_cmd,
10963                          struct drm_i915_gem_object *obj)
10964 {
10965         struct drm_framebuffer *fb;
10966         int ret;
10967
10968         ret = i915_mutex_lock_interruptible(dev);
10969         if (ret)
10970                 return ERR_PTR(ret);
10971         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10972         mutex_unlock(&dev->struct_mutex);
10973
10974         return fb;
10975 }
10976
10977 static u32
10978 intel_framebuffer_pitch_for_width(int width, int bpp)
10979 {
10980         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10981         return ALIGN(pitch, 64);
10982 }
10983
10984 static u32
10985 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10986 {
10987         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10988         return PAGE_ALIGN(pitch * mode->vdisplay);
10989 }
10990
10991 static struct drm_framebuffer *
10992 intel_framebuffer_create_for_mode(struct drm_device *dev,
10993                                   struct drm_display_mode *mode,
10994                                   int depth, int bpp)
10995 {
10996         struct drm_framebuffer *fb;
10997         struct drm_i915_gem_object *obj;
10998         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10999
11000         obj = i915_gem_object_create(dev,
11001                                     intel_framebuffer_size_for_mode(mode, bpp));
11002         if (IS_ERR(obj))
11003                 return ERR_CAST(obj);
11004
11005         mode_cmd.width = mode->hdisplay;
11006         mode_cmd.height = mode->vdisplay;
11007         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11008                                                                 bpp);
11009         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11010
11011         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11012         if (IS_ERR(fb))
11013                 i915_gem_object_put_unlocked(obj);
11014
11015         return fb;
11016 }
11017
11018 static struct drm_framebuffer *
11019 mode_fits_in_fbdev(struct drm_device *dev,
11020                    struct drm_display_mode *mode)
11021 {
11022 #ifdef CONFIG_DRM_FBDEV_EMULATION
11023         struct drm_i915_private *dev_priv = to_i915(dev);
11024         struct drm_i915_gem_object *obj;
11025         struct drm_framebuffer *fb;
11026
11027         if (!dev_priv->fbdev)
11028                 return NULL;
11029
11030         if (!dev_priv->fbdev->fb)
11031                 return NULL;
11032
11033         obj = dev_priv->fbdev->fb->obj;
11034         BUG_ON(!obj);
11035
11036         fb = &dev_priv->fbdev->fb->base;
11037         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11038                                                                fb->bits_per_pixel))
11039                 return NULL;
11040
11041         if (obj->base.size < mode->vdisplay * fb->pitches[0])
11042                 return NULL;
11043
11044         drm_framebuffer_reference(fb);
11045         return fb;
11046 #else
11047         return NULL;
11048 #endif
11049 }
11050
11051 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11052                                            struct drm_crtc *crtc,
11053                                            struct drm_display_mode *mode,
11054                                            struct drm_framebuffer *fb,
11055                                            int x, int y)
11056 {
11057         struct drm_plane_state *plane_state;
11058         int hdisplay, vdisplay;
11059         int ret;
11060
11061         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11062         if (IS_ERR(plane_state))
11063                 return PTR_ERR(plane_state);
11064
11065         if (mode)
11066                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11067         else
11068                 hdisplay = vdisplay = 0;
11069
11070         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11071         if (ret)
11072                 return ret;
11073         drm_atomic_set_fb_for_plane(plane_state, fb);
11074         plane_state->crtc_x = 0;
11075         plane_state->crtc_y = 0;
11076         plane_state->crtc_w = hdisplay;
11077         plane_state->crtc_h = vdisplay;
11078         plane_state->src_x = x << 16;
11079         plane_state->src_y = y << 16;
11080         plane_state->src_w = hdisplay << 16;
11081         plane_state->src_h = vdisplay << 16;
11082
11083         return 0;
11084 }
11085
11086 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11087                                 struct drm_display_mode *mode,
11088                                 struct intel_load_detect_pipe *old,
11089                                 struct drm_modeset_acquire_ctx *ctx)
11090 {
11091         struct intel_crtc *intel_crtc;
11092         struct intel_encoder *intel_encoder =
11093                 intel_attached_encoder(connector);
11094         struct drm_crtc *possible_crtc;
11095         struct drm_encoder *encoder = &intel_encoder->base;
11096         struct drm_crtc *crtc = NULL;
11097         struct drm_device *dev = encoder->dev;
11098         struct drm_framebuffer *fb;
11099         struct drm_mode_config *config = &dev->mode_config;
11100         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11101         struct drm_connector_state *connector_state;
11102         struct intel_crtc_state *crtc_state;
11103         int ret, i = -1;
11104
11105         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11106                       connector->base.id, connector->name,
11107                       encoder->base.id, encoder->name);
11108
11109         old->restore_state = NULL;
11110
11111 retry:
11112         ret = drm_modeset_lock(&config->connection_mutex, ctx);
11113         if (ret)
11114                 goto fail;
11115
11116         /*
11117          * Algorithm gets a little messy:
11118          *
11119          *   - if the connector already has an assigned crtc, use it (but make
11120          *     sure it's on first)
11121          *
11122          *   - try to find the first unused crtc that can drive this connector,
11123          *     and use that if we find one
11124          */
11125
11126         /* See if we already have a CRTC for this connector */
11127         if (connector->state->crtc) {
11128                 crtc = connector->state->crtc;
11129
11130                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11131                 if (ret)
11132                         goto fail;
11133
11134                 /* Make sure the crtc and connector are running */
11135                 goto found;
11136         }
11137
11138         /* Find an unused one (if possible) */
11139         for_each_crtc(dev, possible_crtc) {
11140                 i++;
11141                 if (!(encoder->possible_crtcs & (1 << i)))
11142                         continue;
11143
11144                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11145                 if (ret)
11146                         goto fail;
11147
11148                 if (possible_crtc->state->enable) {
11149                         drm_modeset_unlock(&possible_crtc->mutex);
11150                         continue;
11151                 }
11152
11153                 crtc = possible_crtc;
11154                 break;
11155         }
11156
11157         /*
11158          * If we didn't find an unused CRTC, don't use any.
11159          */
11160         if (!crtc) {
11161                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11162                 goto fail;
11163         }
11164
11165 found:
11166         intel_crtc = to_intel_crtc(crtc);
11167
11168         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11169         if (ret)
11170                 goto fail;
11171
11172         state = drm_atomic_state_alloc(dev);
11173         restore_state = drm_atomic_state_alloc(dev);
11174         if (!state || !restore_state) {
11175                 ret = -ENOMEM;
11176                 goto fail;
11177         }
11178
11179         state->acquire_ctx = ctx;
11180         restore_state->acquire_ctx = ctx;
11181
11182         connector_state = drm_atomic_get_connector_state(state, connector);
11183         if (IS_ERR(connector_state)) {
11184                 ret = PTR_ERR(connector_state);
11185                 goto fail;
11186         }
11187
11188         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11189         if (ret)
11190                 goto fail;
11191
11192         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11193         if (IS_ERR(crtc_state)) {
11194                 ret = PTR_ERR(crtc_state);
11195                 goto fail;
11196         }
11197
11198         crtc_state->base.active = crtc_state->base.enable = true;
11199
11200         if (!mode)
11201                 mode = &load_detect_mode;
11202
11203         /* We need a framebuffer large enough to accommodate all accesses
11204          * that the plane may generate whilst we perform load detection.
11205          * We can not rely on the fbcon either being present (we get called
11206          * during its initialisation to detect all boot displays, or it may
11207          * not even exist) or that it is large enough to satisfy the
11208          * requested mode.
11209          */
11210         fb = mode_fits_in_fbdev(dev, mode);
11211         if (fb == NULL) {
11212                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11213                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11214         } else
11215                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11216         if (IS_ERR(fb)) {
11217                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11218                 goto fail;
11219         }
11220
11221         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11222         if (ret)
11223                 goto fail;
11224
11225         drm_framebuffer_unreference(fb);
11226
11227         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11228         if (ret)
11229                 goto fail;
11230
11231         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11232         if (!ret)
11233                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11234         if (!ret)
11235                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11236         if (ret) {
11237                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11238                 goto fail;
11239         }
11240
11241         ret = drm_atomic_commit(state);
11242         if (ret) {
11243                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11244                 goto fail;
11245         }
11246
11247         old->restore_state = restore_state;
11248
11249         /* let the connector get through one full cycle before testing */
11250         intel_wait_for_vblank(dev, intel_crtc->pipe);
11251         return true;
11252
11253 fail:
11254         if (state) {
11255                 drm_atomic_state_put(state);
11256                 state = NULL;
11257         }
11258         if (restore_state) {
11259                 drm_atomic_state_put(restore_state);
11260                 restore_state = NULL;
11261         }
11262
11263         if (ret == -EDEADLK) {
11264                 drm_modeset_backoff(ctx);
11265                 goto retry;
11266         }
11267
11268         return false;
11269 }
11270
11271 void intel_release_load_detect_pipe(struct drm_connector *connector,
11272                                     struct intel_load_detect_pipe *old,
11273                                     struct drm_modeset_acquire_ctx *ctx)
11274 {
11275         struct intel_encoder *intel_encoder =
11276                 intel_attached_encoder(connector);
11277         struct drm_encoder *encoder = &intel_encoder->base;
11278         struct drm_atomic_state *state = old->restore_state;
11279         int ret;
11280
11281         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11282                       connector->base.id, connector->name,
11283                       encoder->base.id, encoder->name);
11284
11285         if (!state)
11286                 return;
11287
11288         ret = drm_atomic_commit(state);
11289         if (ret)
11290                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11291         drm_atomic_state_put(state);
11292 }
11293
11294 static int i9xx_pll_refclk(struct drm_device *dev,
11295                            const struct intel_crtc_state *pipe_config)
11296 {
11297         struct drm_i915_private *dev_priv = to_i915(dev);
11298         u32 dpll = pipe_config->dpll_hw_state.dpll;
11299
11300         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11301                 return dev_priv->vbt.lvds_ssc_freq;
11302         else if (HAS_PCH_SPLIT(dev))
11303                 return 120000;
11304         else if (!IS_GEN2(dev))
11305                 return 96000;
11306         else
11307                 return 48000;
11308 }
11309
11310 /* Returns the clock of the currently programmed mode of the given pipe. */
11311 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11312                                 struct intel_crtc_state *pipe_config)
11313 {
11314         struct drm_device *dev = crtc->base.dev;
11315         struct drm_i915_private *dev_priv = to_i915(dev);
11316         int pipe = pipe_config->cpu_transcoder;
11317         u32 dpll = pipe_config->dpll_hw_state.dpll;
11318         u32 fp;
11319         struct dpll clock;
11320         int port_clock;
11321         int refclk = i9xx_pll_refclk(dev, pipe_config);
11322
11323         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11324                 fp = pipe_config->dpll_hw_state.fp0;
11325         else
11326                 fp = pipe_config->dpll_hw_state.fp1;
11327
11328         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11329         if (IS_PINEVIEW(dev)) {
11330                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11331                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11332         } else {
11333                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11334                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11335         }
11336
11337         if (!IS_GEN2(dev)) {
11338                 if (IS_PINEVIEW(dev))
11339                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11340                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11341                 else
11342                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11343                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11344
11345                 switch (dpll & DPLL_MODE_MASK) {
11346                 case DPLLB_MODE_DAC_SERIAL:
11347                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11348                                 5 : 10;
11349                         break;
11350                 case DPLLB_MODE_LVDS:
11351                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11352                                 7 : 14;
11353                         break;
11354                 default:
11355                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11356                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11357                         return;
11358                 }
11359
11360                 if (IS_PINEVIEW(dev))
11361                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11362                 else
11363                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11364         } else {
11365                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
11366                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11367
11368                 if (is_lvds) {
11369                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11370                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11371
11372                         if (lvds & LVDS_CLKB_POWER_UP)
11373                                 clock.p2 = 7;
11374                         else
11375                                 clock.p2 = 14;
11376                 } else {
11377                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11378                                 clock.p1 = 2;
11379                         else {
11380                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11381                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11382                         }
11383                         if (dpll & PLL_P2_DIVIDE_BY_4)
11384                                 clock.p2 = 4;
11385                         else
11386                                 clock.p2 = 2;
11387                 }
11388
11389                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11390         }
11391
11392         /*
11393          * This value includes pixel_multiplier. We will use
11394          * port_clock to compute adjusted_mode.crtc_clock in the
11395          * encoder's get_config() function.
11396          */
11397         pipe_config->port_clock = port_clock;
11398 }
11399
11400 int intel_dotclock_calculate(int link_freq,
11401                              const struct intel_link_m_n *m_n)
11402 {
11403         /*
11404          * The calculation for the data clock is:
11405          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11406          * But we want to avoid losing precison if possible, so:
11407          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11408          *
11409          * and the link clock is simpler:
11410          * link_clock = (m * link_clock) / n
11411          */
11412
11413         if (!m_n->link_n)
11414                 return 0;
11415
11416         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11417 }
11418
11419 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11420                                    struct intel_crtc_state *pipe_config)
11421 {
11422         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11423
11424         /* read out port_clock from the DPLL */
11425         i9xx_crtc_clock_get(crtc, pipe_config);
11426
11427         /*
11428          * In case there is an active pipe without active ports,
11429          * we may need some idea for the dotclock anyway.
11430          * Calculate one based on the FDI configuration.
11431          */
11432         pipe_config->base.adjusted_mode.crtc_clock =
11433                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11434                                          &pipe_config->fdi_m_n);
11435 }
11436
11437 /** Returns the currently programmed mode of the given pipe. */
11438 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11439                                              struct drm_crtc *crtc)
11440 {
11441         struct drm_i915_private *dev_priv = to_i915(dev);
11442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11443         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11444         struct drm_display_mode *mode;
11445         struct intel_crtc_state *pipe_config;
11446         int htot = I915_READ(HTOTAL(cpu_transcoder));
11447         int hsync = I915_READ(HSYNC(cpu_transcoder));
11448         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11449         int vsync = I915_READ(VSYNC(cpu_transcoder));
11450         enum pipe pipe = intel_crtc->pipe;
11451
11452         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11453         if (!mode)
11454                 return NULL;
11455
11456         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11457         if (!pipe_config) {
11458                 kfree(mode);
11459                 return NULL;
11460         }
11461
11462         /*
11463          * Construct a pipe_config sufficient for getting the clock info
11464          * back out of crtc_clock_get.
11465          *
11466          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11467          * to use a real value here instead.
11468          */
11469         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11470         pipe_config->pixel_multiplier = 1;
11471         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11472         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11473         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11474         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11475
11476         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11477         mode->hdisplay = (htot & 0xffff) + 1;
11478         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11479         mode->hsync_start = (hsync & 0xffff) + 1;
11480         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11481         mode->vdisplay = (vtot & 0xffff) + 1;
11482         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11483         mode->vsync_start = (vsync & 0xffff) + 1;
11484         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11485
11486         drm_mode_set_name(mode);
11487
11488         kfree(pipe_config);
11489
11490         return mode;
11491 }
11492
11493 static void intel_crtc_destroy(struct drm_crtc *crtc)
11494 {
11495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11496         struct drm_device *dev = crtc->dev;
11497         struct intel_flip_work *work;
11498
11499         spin_lock_irq(&dev->event_lock);
11500         work = intel_crtc->flip_work;
11501         intel_crtc->flip_work = NULL;
11502         spin_unlock_irq(&dev->event_lock);
11503
11504         if (work) {
11505                 cancel_work_sync(&work->mmio_work);
11506                 cancel_work_sync(&work->unpin_work);
11507                 kfree(work);
11508         }
11509
11510         drm_crtc_cleanup(crtc);
11511
11512         kfree(intel_crtc);
11513 }
11514
11515 static void intel_unpin_work_fn(struct work_struct *__work)
11516 {
11517         struct intel_flip_work *work =
11518                 container_of(__work, struct intel_flip_work, unpin_work);
11519         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11520         struct drm_device *dev = crtc->base.dev;
11521         struct drm_plane *primary = crtc->base.primary;
11522
11523         if (is_mmio_work(work))
11524                 flush_work(&work->mmio_work);
11525
11526         mutex_lock(&dev->struct_mutex);
11527         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11528         i915_gem_object_put(work->pending_flip_obj);
11529         mutex_unlock(&dev->struct_mutex);
11530
11531         i915_gem_request_put(work->flip_queued_req);
11532
11533         intel_frontbuffer_flip_complete(to_i915(dev),
11534                                         to_intel_plane(primary)->frontbuffer_bit);
11535         intel_fbc_post_update(crtc);
11536         drm_framebuffer_unreference(work->old_fb);
11537
11538         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11539         atomic_dec(&crtc->unpin_work_count);
11540
11541         kfree(work);
11542 }
11543
11544 /* Is 'a' after or equal to 'b'? */
11545 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11546 {
11547         return !((a - b) & 0x80000000);
11548 }
11549
11550 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11551                                    struct intel_flip_work *work)
11552 {
11553         struct drm_device *dev = crtc->base.dev;
11554         struct drm_i915_private *dev_priv = to_i915(dev);
11555
11556         if (abort_flip_on_reset(crtc))
11557                 return true;
11558
11559         /*
11560          * The relevant registers doen't exist on pre-ctg.
11561          * As the flip done interrupt doesn't trigger for mmio
11562          * flips on gmch platforms, a flip count check isn't
11563          * really needed there. But since ctg has the registers,
11564          * include it in the check anyway.
11565          */
11566         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11567                 return true;
11568
11569         /*
11570          * BDW signals flip done immediately if the plane
11571          * is disabled, even if the plane enable is already
11572          * armed to occur at the next vblank :(
11573          */
11574
11575         /*
11576          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11577          * used the same base address. In that case the mmio flip might
11578          * have completed, but the CS hasn't even executed the flip yet.
11579          *
11580          * A flip count check isn't enough as the CS might have updated
11581          * the base address just after start of vblank, but before we
11582          * managed to process the interrupt. This means we'd complete the
11583          * CS flip too soon.
11584          *
11585          * Combining both checks should get us a good enough result. It may
11586          * still happen that the CS flip has been executed, but has not
11587          * yet actually completed. But in case the base address is the same
11588          * anyway, we don't really care.
11589          */
11590         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11591                 crtc->flip_work->gtt_offset &&
11592                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11593                                     crtc->flip_work->flip_count);
11594 }
11595
11596 static bool
11597 __pageflip_finished_mmio(struct intel_crtc *crtc,
11598                                struct intel_flip_work *work)
11599 {
11600         /*
11601          * MMIO work completes when vblank is different from
11602          * flip_queued_vblank.
11603          *
11604          * Reset counter value doesn't matter, this is handled by
11605          * i915_wait_request finishing early, so no need to handle
11606          * reset here.
11607          */
11608         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11609 }
11610
11611
11612 static bool pageflip_finished(struct intel_crtc *crtc,
11613                               struct intel_flip_work *work)
11614 {
11615         if (!atomic_read(&work->pending))
11616                 return false;
11617
11618         smp_rmb();
11619
11620         if (is_mmio_work(work))
11621                 return __pageflip_finished_mmio(crtc, work);
11622         else
11623                 return __pageflip_finished_cs(crtc, work);
11624 }
11625
11626 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11627 {
11628         struct drm_device *dev = &dev_priv->drm;
11629         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11631         struct intel_flip_work *work;
11632         unsigned long flags;
11633
11634         /* Ignore early vblank irqs */
11635         if (!crtc)
11636                 return;
11637
11638         /*
11639          * This is called both by irq handlers and the reset code (to complete
11640          * lost pageflips) so needs the full irqsave spinlocks.
11641          */
11642         spin_lock_irqsave(&dev->event_lock, flags);
11643         work = intel_crtc->flip_work;
11644
11645         if (work != NULL &&
11646             !is_mmio_work(work) &&
11647             pageflip_finished(intel_crtc, work))
11648                 page_flip_completed(intel_crtc);
11649
11650         spin_unlock_irqrestore(&dev->event_lock, flags);
11651 }
11652
11653 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11654 {
11655         struct drm_device *dev = &dev_priv->drm;
11656         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11658         struct intel_flip_work *work;
11659         unsigned long flags;
11660
11661         /* Ignore early vblank irqs */
11662         if (!crtc)
11663                 return;
11664
11665         /*
11666          * This is called both by irq handlers and the reset code (to complete
11667          * lost pageflips) so needs the full irqsave spinlocks.
11668          */
11669         spin_lock_irqsave(&dev->event_lock, flags);
11670         work = intel_crtc->flip_work;
11671
11672         if (work != NULL &&
11673             is_mmio_work(work) &&
11674             pageflip_finished(intel_crtc, work))
11675                 page_flip_completed(intel_crtc);
11676
11677         spin_unlock_irqrestore(&dev->event_lock, flags);
11678 }
11679
11680 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11681                                                struct intel_flip_work *work)
11682 {
11683         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11684
11685         /* Ensure that the work item is consistent when activating it ... */
11686         smp_mb__before_atomic();
11687         atomic_set(&work->pending, 1);
11688 }
11689
11690 static int intel_gen2_queue_flip(struct drm_device *dev,
11691                                  struct drm_crtc *crtc,
11692                                  struct drm_framebuffer *fb,
11693                                  struct drm_i915_gem_object *obj,
11694                                  struct drm_i915_gem_request *req,
11695                                  uint32_t flags)
11696 {
11697         struct intel_ring *ring = req->ring;
11698         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11699         u32 flip_mask;
11700         int ret;
11701
11702         ret = intel_ring_begin(req, 6);
11703         if (ret)
11704                 return ret;
11705
11706         /* Can't queue multiple flips, so wait for the previous
11707          * one to finish before executing the next.
11708          */
11709         if (intel_crtc->plane)
11710                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11711         else
11712                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11713         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11714         intel_ring_emit(ring, MI_NOOP);
11715         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11716                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11717         intel_ring_emit(ring, fb->pitches[0]);
11718         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11719         intel_ring_emit(ring, 0); /* aux display base address, unused */
11720
11721         return 0;
11722 }
11723
11724 static int intel_gen3_queue_flip(struct drm_device *dev,
11725                                  struct drm_crtc *crtc,
11726                                  struct drm_framebuffer *fb,
11727                                  struct drm_i915_gem_object *obj,
11728                                  struct drm_i915_gem_request *req,
11729                                  uint32_t flags)
11730 {
11731         struct intel_ring *ring = req->ring;
11732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11733         u32 flip_mask;
11734         int ret;
11735
11736         ret = intel_ring_begin(req, 6);
11737         if (ret)
11738                 return ret;
11739
11740         if (intel_crtc->plane)
11741                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11742         else
11743                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11744         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11745         intel_ring_emit(ring, MI_NOOP);
11746         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11747                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11748         intel_ring_emit(ring, fb->pitches[0]);
11749         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11750         intel_ring_emit(ring, MI_NOOP);
11751
11752         return 0;
11753 }
11754
11755 static int intel_gen4_queue_flip(struct drm_device *dev,
11756                                  struct drm_crtc *crtc,
11757                                  struct drm_framebuffer *fb,
11758                                  struct drm_i915_gem_object *obj,
11759                                  struct drm_i915_gem_request *req,
11760                                  uint32_t flags)
11761 {
11762         struct intel_ring *ring = req->ring;
11763         struct drm_i915_private *dev_priv = to_i915(dev);
11764         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11765         uint32_t pf, pipesrc;
11766         int ret;
11767
11768         ret = intel_ring_begin(req, 4);
11769         if (ret)
11770                 return ret;
11771
11772         /* i965+ uses the linear or tiled offsets from the
11773          * Display Registers (which do not change across a page-flip)
11774          * so we need only reprogram the base address.
11775          */
11776         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11777                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11778         intel_ring_emit(ring, fb->pitches[0]);
11779         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11780                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11781
11782         /* XXX Enabling the panel-fitter across page-flip is so far
11783          * untested on non-native modes, so ignore it for now.
11784          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11785          */
11786         pf = 0;
11787         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11788         intel_ring_emit(ring, pf | pipesrc);
11789
11790         return 0;
11791 }
11792
11793 static int intel_gen6_queue_flip(struct drm_device *dev,
11794                                  struct drm_crtc *crtc,
11795                                  struct drm_framebuffer *fb,
11796                                  struct drm_i915_gem_object *obj,
11797                                  struct drm_i915_gem_request *req,
11798                                  uint32_t flags)
11799 {
11800         struct intel_ring *ring = req->ring;
11801         struct drm_i915_private *dev_priv = to_i915(dev);
11802         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11803         uint32_t pf, pipesrc;
11804         int ret;
11805
11806         ret = intel_ring_begin(req, 4);
11807         if (ret)
11808                 return ret;
11809
11810         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11811                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11812         intel_ring_emit(ring, fb->pitches[0] |
11813                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11814         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11815
11816         /* Contrary to the suggestions in the documentation,
11817          * "Enable Panel Fitter" does not seem to be required when page
11818          * flipping with a non-native mode, and worse causes a normal
11819          * modeset to fail.
11820          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11821          */
11822         pf = 0;
11823         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11824         intel_ring_emit(ring, pf | pipesrc);
11825
11826         return 0;
11827 }
11828
11829 static int intel_gen7_queue_flip(struct drm_device *dev,
11830                                  struct drm_crtc *crtc,
11831                                  struct drm_framebuffer *fb,
11832                                  struct drm_i915_gem_object *obj,
11833                                  struct drm_i915_gem_request *req,
11834                                  uint32_t flags)
11835 {
11836         struct intel_ring *ring = req->ring;
11837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11838         uint32_t plane_bit = 0;
11839         int len, ret;
11840
11841         switch (intel_crtc->plane) {
11842         case PLANE_A:
11843                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11844                 break;
11845         case PLANE_B:
11846                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11847                 break;
11848         case PLANE_C:
11849                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11850                 break;
11851         default:
11852                 WARN_ONCE(1, "unknown plane in flip command\n");
11853                 return -ENODEV;
11854         }
11855
11856         len = 4;
11857         if (req->engine->id == RCS) {
11858                 len += 6;
11859                 /*
11860                  * On Gen 8, SRM is now taking an extra dword to accommodate
11861                  * 48bits addresses, and we need a NOOP for the batch size to
11862                  * stay even.
11863                  */
11864                 if (IS_GEN8(dev))
11865                         len += 2;
11866         }
11867
11868         /*
11869          * BSpec MI_DISPLAY_FLIP for IVB:
11870          * "The full packet must be contained within the same cache line."
11871          *
11872          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11873          * cacheline, if we ever start emitting more commands before
11874          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11875          * then do the cacheline alignment, and finally emit the
11876          * MI_DISPLAY_FLIP.
11877          */
11878         ret = intel_ring_cacheline_align(req);
11879         if (ret)
11880                 return ret;
11881
11882         ret = intel_ring_begin(req, len);
11883         if (ret)
11884                 return ret;
11885
11886         /* Unmask the flip-done completion message. Note that the bspec says that
11887          * we should do this for both the BCS and RCS, and that we must not unmask
11888          * more than one flip event at any time (or ensure that one flip message
11889          * can be sent by waiting for flip-done prior to queueing new flips).
11890          * Experimentation says that BCS works despite DERRMR masking all
11891          * flip-done completion events and that unmasking all planes at once
11892          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11893          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11894          */
11895         if (req->engine->id == RCS) {
11896                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11897                 intel_ring_emit_reg(ring, DERRMR);
11898                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11899                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11900                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11901                 if (IS_GEN8(dev))
11902                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11903                                               MI_SRM_LRM_GLOBAL_GTT);
11904                 else
11905                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11906                                               MI_SRM_LRM_GLOBAL_GTT);
11907                 intel_ring_emit_reg(ring, DERRMR);
11908                 intel_ring_emit(ring,
11909                                 i915_ggtt_offset(req->engine->scratch) + 256);
11910                 if (IS_GEN8(dev)) {
11911                         intel_ring_emit(ring, 0);
11912                         intel_ring_emit(ring, MI_NOOP);
11913                 }
11914         }
11915
11916         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11917         intel_ring_emit(ring, fb->pitches[0] |
11918                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11919         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11920         intel_ring_emit(ring, (MI_NOOP));
11921
11922         return 0;
11923 }
11924
11925 static bool use_mmio_flip(struct intel_engine_cs *engine,
11926                           struct drm_i915_gem_object *obj)
11927 {
11928         struct reservation_object *resv;
11929
11930         /*
11931          * This is not being used for older platforms, because
11932          * non-availability of flip done interrupt forces us to use
11933          * CS flips. Older platforms derive flip done using some clever
11934          * tricks involving the flip_pending status bits and vblank irqs.
11935          * So using MMIO flips there would disrupt this mechanism.
11936          */
11937
11938         if (engine == NULL)
11939                 return true;
11940
11941         if (INTEL_GEN(engine->i915) < 5)
11942                 return false;
11943
11944         if (i915.use_mmio_flip < 0)
11945                 return false;
11946         else if (i915.use_mmio_flip > 0)
11947                 return true;
11948         else if (i915.enable_execlists)
11949                 return true;
11950
11951         resv = i915_gem_object_get_dmabuf_resv(obj);
11952         if (resv && !reservation_object_test_signaled_rcu(resv, false))
11953                 return true;
11954
11955         return engine != i915_gem_active_get_engine(&obj->last_write,
11956                                                     &obj->base.dev->struct_mutex);
11957 }
11958
11959 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11960                              unsigned int rotation,
11961                              struct intel_flip_work *work)
11962 {
11963         struct drm_device *dev = intel_crtc->base.dev;
11964         struct drm_i915_private *dev_priv = to_i915(dev);
11965         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11966         const enum pipe pipe = intel_crtc->pipe;
11967         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11968
11969         ctl = I915_READ(PLANE_CTL(pipe, 0));
11970         ctl &= ~PLANE_CTL_TILED_MASK;
11971         switch (fb->modifier[0]) {
11972         case DRM_FORMAT_MOD_NONE:
11973                 break;
11974         case I915_FORMAT_MOD_X_TILED:
11975                 ctl |= PLANE_CTL_TILED_X;
11976                 break;
11977         case I915_FORMAT_MOD_Y_TILED:
11978                 ctl |= PLANE_CTL_TILED_Y;
11979                 break;
11980         case I915_FORMAT_MOD_Yf_TILED:
11981                 ctl |= PLANE_CTL_TILED_YF;
11982                 break;
11983         default:
11984                 MISSING_CASE(fb->modifier[0]);
11985         }
11986
11987         /*
11988          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11989          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11990          */
11991         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11992         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11993
11994         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11995         POSTING_READ(PLANE_SURF(pipe, 0));
11996 }
11997
11998 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11999                              struct intel_flip_work *work)
12000 {
12001         struct drm_device *dev = intel_crtc->base.dev;
12002         struct drm_i915_private *dev_priv = to_i915(dev);
12003         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12004         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12005         u32 dspcntr;
12006
12007         dspcntr = I915_READ(reg);
12008
12009         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
12010                 dspcntr |= DISPPLANE_TILED;
12011         else
12012                 dspcntr &= ~DISPPLANE_TILED;
12013
12014         I915_WRITE(reg, dspcntr);
12015
12016         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12017         POSTING_READ(DSPSURF(intel_crtc->plane));
12018 }
12019
12020 static void intel_mmio_flip_work_func(struct work_struct *w)
12021 {
12022         struct intel_flip_work *work =
12023                 container_of(w, struct intel_flip_work, mmio_work);
12024         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12025         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12026         struct intel_framebuffer *intel_fb =
12027                 to_intel_framebuffer(crtc->base.primary->fb);
12028         struct drm_i915_gem_object *obj = intel_fb->obj;
12029         struct reservation_object *resv;
12030
12031         if (work->flip_queued_req)
12032                 WARN_ON(i915_wait_request(work->flip_queued_req,
12033                                           0, NULL, NO_WAITBOOST));
12034
12035         /* For framebuffer backed by dmabuf, wait for fence */
12036         resv = i915_gem_object_get_dmabuf_resv(obj);
12037         if (resv)
12038                 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
12039                                                             MAX_SCHEDULE_TIMEOUT) < 0);
12040
12041         intel_pipe_update_start(crtc);
12042
12043         if (INTEL_GEN(dev_priv) >= 9)
12044                 skl_do_mmio_flip(crtc, work->rotation, work);
12045         else
12046                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12047                 ilk_do_mmio_flip(crtc, work);
12048
12049         intel_pipe_update_end(crtc, work);
12050 }
12051
12052 static int intel_default_queue_flip(struct drm_device *dev,
12053                                     struct drm_crtc *crtc,
12054                                     struct drm_framebuffer *fb,
12055                                     struct drm_i915_gem_object *obj,
12056                                     struct drm_i915_gem_request *req,
12057                                     uint32_t flags)
12058 {
12059         return -ENODEV;
12060 }
12061
12062 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12063                                       struct intel_crtc *intel_crtc,
12064                                       struct intel_flip_work *work)
12065 {
12066         u32 addr, vblank;
12067
12068         if (!atomic_read(&work->pending))
12069                 return false;
12070
12071         smp_rmb();
12072
12073         vblank = intel_crtc_get_vblank_counter(intel_crtc);
12074         if (work->flip_ready_vblank == 0) {
12075                 if (work->flip_queued_req &&
12076                     !i915_gem_request_completed(work->flip_queued_req))
12077                         return false;
12078
12079                 work->flip_ready_vblank = vblank;
12080         }
12081
12082         if (vblank - work->flip_ready_vblank < 3)
12083                 return false;
12084
12085         /* Potential stall - if we see that the flip has happened,
12086          * assume a missed interrupt. */
12087         if (INTEL_GEN(dev_priv) >= 4)
12088                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12089         else
12090                 addr = I915_READ(DSPADDR(intel_crtc->plane));
12091
12092         /* There is a potential issue here with a false positive after a flip
12093          * to the same address. We could address this by checking for a
12094          * non-incrementing frame counter.
12095          */
12096         return addr == work->gtt_offset;
12097 }
12098
12099 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12100 {
12101         struct drm_device *dev = &dev_priv->drm;
12102         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
12103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12104         struct intel_flip_work *work;
12105
12106         WARN_ON(!in_interrupt());
12107
12108         if (crtc == NULL)
12109                 return;
12110
12111         spin_lock(&dev->event_lock);
12112         work = intel_crtc->flip_work;
12113
12114         if (work != NULL && !is_mmio_work(work) &&
12115             __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12116                 WARN_ONCE(1,
12117                           "Kicking stuck page flip: queued at %d, now %d\n",
12118                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12119                 page_flip_completed(intel_crtc);
12120                 work = NULL;
12121         }
12122
12123         if (work != NULL && !is_mmio_work(work) &&
12124             intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12125                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12126         spin_unlock(&dev->event_lock);
12127 }
12128
12129 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12130                                 struct drm_framebuffer *fb,
12131                                 struct drm_pending_vblank_event *event,
12132                                 uint32_t page_flip_flags)
12133 {
12134         struct drm_device *dev = crtc->dev;
12135         struct drm_i915_private *dev_priv = to_i915(dev);
12136         struct drm_framebuffer *old_fb = crtc->primary->fb;
12137         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12139         struct drm_plane *primary = crtc->primary;
12140         enum pipe pipe = intel_crtc->pipe;
12141         struct intel_flip_work *work;
12142         struct intel_engine_cs *engine;
12143         bool mmio_flip;
12144         struct drm_i915_gem_request *request;
12145         struct i915_vma *vma;
12146         int ret;
12147
12148         /*
12149          * drm_mode_page_flip_ioctl() should already catch this, but double
12150          * check to be safe.  In the future we may enable pageflipping from
12151          * a disabled primary plane.
12152          */
12153         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12154                 return -EBUSY;
12155
12156         /* Can't change pixel format via MI display flips. */
12157         if (fb->pixel_format != crtc->primary->fb->pixel_format)
12158                 return -EINVAL;
12159
12160         /*
12161          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12162          * Note that pitch changes could also affect these register.
12163          */
12164         if (INTEL_INFO(dev)->gen > 3 &&
12165             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12166              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12167                 return -EINVAL;
12168
12169         if (i915_terminally_wedged(&dev_priv->gpu_error))
12170                 goto out_hang;
12171
12172         work = kzalloc(sizeof(*work), GFP_KERNEL);
12173         if (work == NULL)
12174                 return -ENOMEM;
12175
12176         work->event = event;
12177         work->crtc = crtc;
12178         work->old_fb = old_fb;
12179         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12180
12181         ret = drm_crtc_vblank_get(crtc);
12182         if (ret)
12183                 goto free_work;
12184
12185         /* We borrow the event spin lock for protecting flip_work */
12186         spin_lock_irq(&dev->event_lock);
12187         if (intel_crtc->flip_work) {
12188                 /* Before declaring the flip queue wedged, check if
12189                  * the hardware completed the operation behind our backs.
12190                  */
12191                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12192                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12193                         page_flip_completed(intel_crtc);
12194                 } else {
12195                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12196                         spin_unlock_irq(&dev->event_lock);
12197
12198                         drm_crtc_vblank_put(crtc);
12199                         kfree(work);
12200                         return -EBUSY;
12201                 }
12202         }
12203         intel_crtc->flip_work = work;
12204         spin_unlock_irq(&dev->event_lock);
12205
12206         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12207                 flush_workqueue(dev_priv->wq);
12208
12209         /* Reference the objects for the scheduled work. */
12210         drm_framebuffer_reference(work->old_fb);
12211
12212         crtc->primary->fb = fb;
12213         update_state_fb(crtc->primary);
12214
12215         work->pending_flip_obj = i915_gem_object_get(obj);
12216
12217         ret = i915_mutex_lock_interruptible(dev);
12218         if (ret)
12219                 goto cleanup;
12220
12221         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12222         if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12223                 ret = -EIO;
12224                 goto cleanup;
12225         }
12226
12227         atomic_inc(&intel_crtc->unpin_work_count);
12228
12229         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12230                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12231
12232         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12233                 engine = &dev_priv->engine[BCS];
12234                 if (fb->modifier[0] != old_fb->modifier[0])
12235                         /* vlv: DISPLAY_FLIP fails to change tiling */
12236                         engine = NULL;
12237         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
12238                 engine = &dev_priv->engine[BCS];
12239         } else if (INTEL_INFO(dev)->gen >= 7) {
12240                 engine = i915_gem_active_get_engine(&obj->last_write,
12241                                                     &obj->base.dev->struct_mutex);
12242                 if (engine == NULL || engine->id != RCS)
12243                         engine = &dev_priv->engine[BCS];
12244         } else {
12245                 engine = &dev_priv->engine[RCS];
12246         }
12247
12248         mmio_flip = use_mmio_flip(engine, obj);
12249
12250         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12251         if (IS_ERR(vma)) {
12252                 ret = PTR_ERR(vma);
12253                 goto cleanup_pending;
12254         }
12255
12256         work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12257         work->gtt_offset += intel_crtc->dspaddr_offset;
12258         work->rotation = crtc->primary->state->rotation;
12259
12260         /*
12261          * There's the potential that the next frame will not be compatible with
12262          * FBC, so we want to call pre_update() before the actual page flip.
12263          * The problem is that pre_update() caches some information about the fb
12264          * object, so we want to do this only after the object is pinned. Let's
12265          * be on the safe side and do this immediately before scheduling the
12266          * flip.
12267          */
12268         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12269                              to_intel_plane_state(primary->state));
12270
12271         if (mmio_flip) {
12272                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12273
12274                 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12275                                                             &obj->base.dev->struct_mutex);
12276                 schedule_work(&work->mmio_work);
12277         } else {
12278                 request = i915_gem_request_alloc(engine, engine->last_context);
12279                 if (IS_ERR(request)) {
12280                         ret = PTR_ERR(request);
12281                         goto cleanup_unpin;
12282                 }
12283
12284                 ret = i915_gem_request_await_object(request, obj, false);
12285                 if (ret)
12286                         goto cleanup_request;
12287
12288                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12289                                                    page_flip_flags);
12290                 if (ret)
12291                         goto cleanup_request;
12292
12293                 intel_mark_page_flip_active(intel_crtc, work);
12294
12295                 work->flip_queued_req = i915_gem_request_get(request);
12296                 i915_add_request_no_flush(request);
12297         }
12298
12299         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12300                           to_intel_plane(primary)->frontbuffer_bit);
12301         mutex_unlock(&dev->struct_mutex);
12302
12303         intel_frontbuffer_flip_prepare(to_i915(dev),
12304                                        to_intel_plane(primary)->frontbuffer_bit);
12305
12306         trace_i915_flip_request(intel_crtc->plane, obj);
12307
12308         return 0;
12309
12310 cleanup_request:
12311         i915_add_request_no_flush(request);
12312 cleanup_unpin:
12313         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12314 cleanup_pending:
12315         atomic_dec(&intel_crtc->unpin_work_count);
12316         mutex_unlock(&dev->struct_mutex);
12317 cleanup:
12318         crtc->primary->fb = old_fb;
12319         update_state_fb(crtc->primary);
12320
12321         i915_gem_object_put_unlocked(obj);
12322         drm_framebuffer_unreference(work->old_fb);
12323
12324         spin_lock_irq(&dev->event_lock);
12325         intel_crtc->flip_work = NULL;
12326         spin_unlock_irq(&dev->event_lock);
12327
12328         drm_crtc_vblank_put(crtc);
12329 free_work:
12330         kfree(work);
12331
12332         if (ret == -EIO) {
12333                 struct drm_atomic_state *state;
12334                 struct drm_plane_state *plane_state;
12335
12336 out_hang:
12337                 state = drm_atomic_state_alloc(dev);
12338                 if (!state)
12339                         return -ENOMEM;
12340                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12341
12342 retry:
12343                 plane_state = drm_atomic_get_plane_state(state, primary);
12344                 ret = PTR_ERR_OR_ZERO(plane_state);
12345                 if (!ret) {
12346                         drm_atomic_set_fb_for_plane(plane_state, fb);
12347
12348                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12349                         if (!ret)
12350                                 ret = drm_atomic_commit(state);
12351                 }
12352
12353                 if (ret == -EDEADLK) {
12354                         drm_modeset_backoff(state->acquire_ctx);
12355                         drm_atomic_state_clear(state);
12356                         goto retry;
12357                 }
12358
12359                 drm_atomic_state_put(state);
12360
12361                 if (ret == 0 && event) {
12362                         spin_lock_irq(&dev->event_lock);
12363                         drm_crtc_send_vblank_event(crtc, event);
12364                         spin_unlock_irq(&dev->event_lock);
12365                 }
12366         }
12367         return ret;
12368 }
12369
12370
12371 /**
12372  * intel_wm_need_update - Check whether watermarks need updating
12373  * @plane: drm plane
12374  * @state: new plane state
12375  *
12376  * Check current plane state versus the new one to determine whether
12377  * watermarks need to be recalculated.
12378  *
12379  * Returns true or false.
12380  */
12381 static bool intel_wm_need_update(struct drm_plane *plane,
12382                                  struct drm_plane_state *state)
12383 {
12384         struct intel_plane_state *new = to_intel_plane_state(state);
12385         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12386
12387         /* Update watermarks on tiling or size changes. */
12388         if (new->base.visible != cur->base.visible)
12389                 return true;
12390
12391         if (!cur->base.fb || !new->base.fb)
12392                 return false;
12393
12394         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12395             cur->base.rotation != new->base.rotation ||
12396             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12397             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12398             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12399             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12400                 return true;
12401
12402         return false;
12403 }
12404
12405 static bool needs_scaling(struct intel_plane_state *state)
12406 {
12407         int src_w = drm_rect_width(&state->base.src) >> 16;
12408         int src_h = drm_rect_height(&state->base.src) >> 16;
12409         int dst_w = drm_rect_width(&state->base.dst);
12410         int dst_h = drm_rect_height(&state->base.dst);
12411
12412         return (src_w != dst_w || src_h != dst_h);
12413 }
12414
12415 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12416                                     struct drm_plane_state *plane_state)
12417 {
12418         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12419         struct drm_crtc *crtc = crtc_state->crtc;
12420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12421         struct drm_plane *plane = plane_state->plane;
12422         struct drm_device *dev = crtc->dev;
12423         struct drm_i915_private *dev_priv = to_i915(dev);
12424         struct intel_plane_state *old_plane_state =
12425                 to_intel_plane_state(plane->state);
12426         bool mode_changed = needs_modeset(crtc_state);
12427         bool was_crtc_enabled = crtc->state->active;
12428         bool is_crtc_enabled = crtc_state->active;
12429         bool turn_off, turn_on, visible, was_visible;
12430         struct drm_framebuffer *fb = plane_state->fb;
12431         int ret;
12432
12433         if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12434                 ret = skl_update_scaler_plane(
12435                         to_intel_crtc_state(crtc_state),
12436                         to_intel_plane_state(plane_state));
12437                 if (ret)
12438                         return ret;
12439         }
12440
12441         was_visible = old_plane_state->base.visible;
12442         visible = to_intel_plane_state(plane_state)->base.visible;
12443
12444         if (!was_crtc_enabled && WARN_ON(was_visible))
12445                 was_visible = false;
12446
12447         /*
12448          * Visibility is calculated as if the crtc was on, but
12449          * after scaler setup everything depends on it being off
12450          * when the crtc isn't active.
12451          *
12452          * FIXME this is wrong for watermarks. Watermarks should also
12453          * be computed as if the pipe would be active. Perhaps move
12454          * per-plane wm computation to the .check_plane() hook, and
12455          * only combine the results from all planes in the current place?
12456          */
12457         if (!is_crtc_enabled)
12458                 to_intel_plane_state(plane_state)->base.visible = visible = false;
12459
12460         if (!was_visible && !visible)
12461                 return 0;
12462
12463         if (fb != old_plane_state->base.fb)
12464                 pipe_config->fb_changed = true;
12465
12466         turn_off = was_visible && (!visible || mode_changed);
12467         turn_on = visible && (!was_visible || mode_changed);
12468
12469         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12470                          intel_crtc->base.base.id,
12471                          intel_crtc->base.name,
12472                          plane->base.id, plane->name,
12473                          fb ? fb->base.id : -1);
12474
12475         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12476                          plane->base.id, plane->name,
12477                          was_visible, visible,
12478                          turn_off, turn_on, mode_changed);
12479
12480         if (turn_on) {
12481                 pipe_config->update_wm_pre = true;
12482
12483                 /* must disable cxsr around plane enable/disable */
12484                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12485                         pipe_config->disable_cxsr = true;
12486         } else if (turn_off) {
12487                 pipe_config->update_wm_post = true;
12488
12489                 /* must disable cxsr around plane enable/disable */
12490                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12491                         pipe_config->disable_cxsr = true;
12492         } else if (intel_wm_need_update(plane, plane_state)) {
12493                 /* FIXME bollocks */
12494                 pipe_config->update_wm_pre = true;
12495                 pipe_config->update_wm_post = true;
12496         }
12497
12498         /* Pre-gen9 platforms need two-step watermark updates */
12499         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12500             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12501                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12502
12503         if (visible || was_visible)
12504                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12505
12506         /*
12507          * WaCxSRDisabledForSpriteScaling:ivb
12508          *
12509          * cstate->update_wm was already set above, so this flag will
12510          * take effect when we commit and program watermarks.
12511          */
12512         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12513             needs_scaling(to_intel_plane_state(plane_state)) &&
12514             !needs_scaling(old_plane_state))
12515                 pipe_config->disable_lp_wm = true;
12516
12517         return 0;
12518 }
12519
12520 static bool encoders_cloneable(const struct intel_encoder *a,
12521                                const struct intel_encoder *b)
12522 {
12523         /* masks could be asymmetric, so check both ways */
12524         return a == b || (a->cloneable & (1 << b->type) &&
12525                           b->cloneable & (1 << a->type));
12526 }
12527
12528 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12529                                          struct intel_crtc *crtc,
12530                                          struct intel_encoder *encoder)
12531 {
12532         struct intel_encoder *source_encoder;
12533         struct drm_connector *connector;
12534         struct drm_connector_state *connector_state;
12535         int i;
12536
12537         for_each_connector_in_state(state, connector, connector_state, i) {
12538                 if (connector_state->crtc != &crtc->base)
12539                         continue;
12540
12541                 source_encoder =
12542                         to_intel_encoder(connector_state->best_encoder);
12543                 if (!encoders_cloneable(encoder, source_encoder))
12544                         return false;
12545         }
12546
12547         return true;
12548 }
12549
12550 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12551                                    struct drm_crtc_state *crtc_state)
12552 {
12553         struct drm_device *dev = crtc->dev;
12554         struct drm_i915_private *dev_priv = to_i915(dev);
12555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12556         struct intel_crtc_state *pipe_config =
12557                 to_intel_crtc_state(crtc_state);
12558         struct drm_atomic_state *state = crtc_state->state;
12559         int ret;
12560         bool mode_changed = needs_modeset(crtc_state);
12561
12562         if (mode_changed && !crtc_state->active)
12563                 pipe_config->update_wm_post = true;
12564
12565         if (mode_changed && crtc_state->enable &&
12566             dev_priv->display.crtc_compute_clock &&
12567             !WARN_ON(pipe_config->shared_dpll)) {
12568                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12569                                                            pipe_config);
12570                 if (ret)
12571                         return ret;
12572         }
12573
12574         if (crtc_state->color_mgmt_changed) {
12575                 ret = intel_color_check(crtc, crtc_state);
12576                 if (ret)
12577                         return ret;
12578
12579                 /*
12580                  * Changing color management on Intel hardware is
12581                  * handled as part of planes update.
12582                  */
12583                 crtc_state->planes_changed = true;
12584         }
12585
12586         ret = 0;
12587         if (dev_priv->display.compute_pipe_wm) {
12588                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12589                 if (ret) {
12590                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12591                         return ret;
12592                 }
12593         }
12594
12595         if (dev_priv->display.compute_intermediate_wm &&
12596             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12597                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12598                         return 0;
12599
12600                 /*
12601                  * Calculate 'intermediate' watermarks that satisfy both the
12602                  * old state and the new state.  We can program these
12603                  * immediately.
12604                  */
12605                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12606                                                                 intel_crtc,
12607                                                                 pipe_config);
12608                 if (ret) {
12609                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12610                         return ret;
12611                 }
12612         } else if (dev_priv->display.compute_intermediate_wm) {
12613                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12614                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12615         }
12616
12617         if (INTEL_INFO(dev)->gen >= 9) {
12618                 if (mode_changed)
12619                         ret = skl_update_scaler_crtc(pipe_config);
12620
12621                 if (!ret)
12622                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12623                                                          pipe_config);
12624         }
12625
12626         return ret;
12627 }
12628
12629 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12630         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12631         .atomic_begin = intel_begin_crtc_commit,
12632         .atomic_flush = intel_finish_crtc_commit,
12633         .atomic_check = intel_crtc_atomic_check,
12634 };
12635
12636 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12637 {
12638         struct intel_connector *connector;
12639
12640         for_each_intel_connector(dev, connector) {
12641                 if (connector->base.state->crtc)
12642                         drm_connector_unreference(&connector->base);
12643
12644                 if (connector->base.encoder) {
12645                         connector->base.state->best_encoder =
12646                                 connector->base.encoder;
12647                         connector->base.state->crtc =
12648                                 connector->base.encoder->crtc;
12649
12650                         drm_connector_reference(&connector->base);
12651                 } else {
12652                         connector->base.state->best_encoder = NULL;
12653                         connector->base.state->crtc = NULL;
12654                 }
12655         }
12656 }
12657
12658 static void
12659 connected_sink_compute_bpp(struct intel_connector *connector,
12660                            struct intel_crtc_state *pipe_config)
12661 {
12662         const struct drm_display_info *info = &connector->base.display_info;
12663         int bpp = pipe_config->pipe_bpp;
12664
12665         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12666                       connector->base.base.id,
12667                       connector->base.name);
12668
12669         /* Don't use an invalid EDID bpc value */
12670         if (info->bpc != 0 && info->bpc * 3 < bpp) {
12671                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12672                               bpp, info->bpc * 3);
12673                 pipe_config->pipe_bpp = info->bpc * 3;
12674         }
12675
12676         /* Clamp bpp to 8 on screens without EDID 1.4 */
12677         if (info->bpc == 0 && bpp > 24) {
12678                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12679                               bpp);
12680                 pipe_config->pipe_bpp = 24;
12681         }
12682 }
12683
12684 static int
12685 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12686                           struct intel_crtc_state *pipe_config)
12687 {
12688         struct drm_device *dev = crtc->base.dev;
12689         struct drm_atomic_state *state;
12690         struct drm_connector *connector;
12691         struct drm_connector_state *connector_state;
12692         int bpp, i;
12693
12694         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12695                 bpp = 10*3;
12696         else if (INTEL_INFO(dev)->gen >= 5)
12697                 bpp = 12*3;
12698         else
12699                 bpp = 8*3;
12700
12701
12702         pipe_config->pipe_bpp = bpp;
12703
12704         state = pipe_config->base.state;
12705
12706         /* Clamp display bpp to EDID value */
12707         for_each_connector_in_state(state, connector, connector_state, i) {
12708                 if (connector_state->crtc != &crtc->base)
12709                         continue;
12710
12711                 connected_sink_compute_bpp(to_intel_connector(connector),
12712                                            pipe_config);
12713         }
12714
12715         return bpp;
12716 }
12717
12718 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12719 {
12720         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12721                         "type: 0x%x flags: 0x%x\n",
12722                 mode->crtc_clock,
12723                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12724                 mode->crtc_hsync_end, mode->crtc_htotal,
12725                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12726                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12727 }
12728
12729 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12730                                    struct intel_crtc_state *pipe_config,
12731                                    const char *context)
12732 {
12733         struct drm_device *dev = crtc->base.dev;
12734         struct drm_plane *plane;
12735         struct intel_plane *intel_plane;
12736         struct intel_plane_state *state;
12737         struct drm_framebuffer *fb;
12738
12739         DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12740                       crtc->base.base.id, crtc->base.name,
12741                       context, pipe_config, pipe_name(crtc->pipe));
12742
12743         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12744         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12745                       pipe_config->pipe_bpp, pipe_config->dither);
12746         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12747                       pipe_config->has_pch_encoder,
12748                       pipe_config->fdi_lanes,
12749                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12750                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12751                       pipe_config->fdi_m_n.tu);
12752         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12753                       intel_crtc_has_dp_encoder(pipe_config),
12754                       pipe_config->lane_count,
12755                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12756                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12757                       pipe_config->dp_m_n.tu);
12758
12759         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12760                       intel_crtc_has_dp_encoder(pipe_config),
12761                       pipe_config->lane_count,
12762                       pipe_config->dp_m2_n2.gmch_m,
12763                       pipe_config->dp_m2_n2.gmch_n,
12764                       pipe_config->dp_m2_n2.link_m,
12765                       pipe_config->dp_m2_n2.link_n,
12766                       pipe_config->dp_m2_n2.tu);
12767
12768         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12769                       pipe_config->has_audio,
12770                       pipe_config->has_infoframe);
12771
12772         DRM_DEBUG_KMS("requested mode:\n");
12773         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12774         DRM_DEBUG_KMS("adjusted mode:\n");
12775         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12776         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12777         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12778         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12779                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12780         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12781                       crtc->num_scalers,
12782                       pipe_config->scaler_state.scaler_users,
12783                       pipe_config->scaler_state.scaler_id);
12784         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12785                       pipe_config->gmch_pfit.control,
12786                       pipe_config->gmch_pfit.pgm_ratios,
12787                       pipe_config->gmch_pfit.lvds_border_bits);
12788         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12789                       pipe_config->pch_pfit.pos,
12790                       pipe_config->pch_pfit.size,
12791                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12792         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12793         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12794
12795         if (IS_BROXTON(dev)) {
12796                 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12797                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12798                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12799                               pipe_config->dpll_hw_state.ebb0,
12800                               pipe_config->dpll_hw_state.ebb4,
12801                               pipe_config->dpll_hw_state.pll0,
12802                               pipe_config->dpll_hw_state.pll1,
12803                               pipe_config->dpll_hw_state.pll2,
12804                               pipe_config->dpll_hw_state.pll3,
12805                               pipe_config->dpll_hw_state.pll6,
12806                               pipe_config->dpll_hw_state.pll8,
12807                               pipe_config->dpll_hw_state.pll9,
12808                               pipe_config->dpll_hw_state.pll10,
12809                               pipe_config->dpll_hw_state.pcsdw12);
12810         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12811                 DRM_DEBUG_KMS("dpll_hw_state: "
12812                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12813                               pipe_config->dpll_hw_state.ctrl1,
12814                               pipe_config->dpll_hw_state.cfgcr1,
12815                               pipe_config->dpll_hw_state.cfgcr2);
12816         } else if (HAS_DDI(dev)) {
12817                 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12818                               pipe_config->dpll_hw_state.wrpll,
12819                               pipe_config->dpll_hw_state.spll);
12820         } else {
12821                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12822                               "fp0: 0x%x, fp1: 0x%x\n",
12823                               pipe_config->dpll_hw_state.dpll,
12824                               pipe_config->dpll_hw_state.dpll_md,
12825                               pipe_config->dpll_hw_state.fp0,
12826                               pipe_config->dpll_hw_state.fp1);
12827         }
12828
12829         DRM_DEBUG_KMS("planes on this crtc\n");
12830         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12831                 char *format_name;
12832                 intel_plane = to_intel_plane(plane);
12833                 if (intel_plane->pipe != crtc->pipe)
12834                         continue;
12835
12836                 state = to_intel_plane_state(plane->state);
12837                 fb = state->base.fb;
12838                 if (!fb) {
12839                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12840                                       plane->base.id, plane->name, state->scaler_id);
12841                         continue;
12842                 }
12843
12844                 format_name = drm_get_format_name(fb->pixel_format);
12845
12846                 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12847                               plane->base.id, plane->name);
12848                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12849                               fb->base.id, fb->width, fb->height, format_name);
12850                 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12851                               state->scaler_id,
12852                               state->base.src.x1 >> 16,
12853                               state->base.src.y1 >> 16,
12854                               drm_rect_width(&state->base.src) >> 16,
12855                               drm_rect_height(&state->base.src) >> 16,
12856                               state->base.dst.x1, state->base.dst.y1,
12857                               drm_rect_width(&state->base.dst),
12858                               drm_rect_height(&state->base.dst));
12859
12860                 kfree(format_name);
12861         }
12862 }
12863
12864 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12865 {
12866         struct drm_device *dev = state->dev;
12867         struct drm_connector *connector;
12868         unsigned int used_ports = 0;
12869         unsigned int used_mst_ports = 0;
12870
12871         /*
12872          * Walk the connector list instead of the encoder
12873          * list to detect the problem on ddi platforms
12874          * where there's just one encoder per digital port.
12875          */
12876         drm_for_each_connector(connector, dev) {
12877                 struct drm_connector_state *connector_state;
12878                 struct intel_encoder *encoder;
12879
12880                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12881                 if (!connector_state)
12882                         connector_state = connector->state;
12883
12884                 if (!connector_state->best_encoder)
12885                         continue;
12886
12887                 encoder = to_intel_encoder(connector_state->best_encoder);
12888
12889                 WARN_ON(!connector_state->crtc);
12890
12891                 switch (encoder->type) {
12892                         unsigned int port_mask;
12893                 case INTEL_OUTPUT_UNKNOWN:
12894                         if (WARN_ON(!HAS_DDI(dev)))
12895                                 break;
12896                 case INTEL_OUTPUT_DP:
12897                 case INTEL_OUTPUT_HDMI:
12898                 case INTEL_OUTPUT_EDP:
12899                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12900
12901                         /* the same port mustn't appear more than once */
12902                         if (used_ports & port_mask)
12903                                 return false;
12904
12905                         used_ports |= port_mask;
12906                         break;
12907                 case INTEL_OUTPUT_DP_MST:
12908                         used_mst_ports |=
12909                                 1 << enc_to_mst(&encoder->base)->primary->port;
12910                         break;
12911                 default:
12912                         break;
12913                 }
12914         }
12915
12916         /* can't mix MST and SST/HDMI on the same port */
12917         if (used_ports & used_mst_ports)
12918                 return false;
12919
12920         return true;
12921 }
12922
12923 static void
12924 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12925 {
12926         struct drm_crtc_state tmp_state;
12927         struct intel_crtc_scaler_state scaler_state;
12928         struct intel_dpll_hw_state dpll_hw_state;
12929         struct intel_shared_dpll *shared_dpll;
12930         bool force_thru;
12931
12932         /* FIXME: before the switch to atomic started, a new pipe_config was
12933          * kzalloc'd. Code that depends on any field being zero should be
12934          * fixed, so that the crtc_state can be safely duplicated. For now,
12935          * only fields that are know to not cause problems are preserved. */
12936
12937         tmp_state = crtc_state->base;
12938         scaler_state = crtc_state->scaler_state;
12939         shared_dpll = crtc_state->shared_dpll;
12940         dpll_hw_state = crtc_state->dpll_hw_state;
12941         force_thru = crtc_state->pch_pfit.force_thru;
12942
12943         memset(crtc_state, 0, sizeof *crtc_state);
12944
12945         crtc_state->base = tmp_state;
12946         crtc_state->scaler_state = scaler_state;
12947         crtc_state->shared_dpll = shared_dpll;
12948         crtc_state->dpll_hw_state = dpll_hw_state;
12949         crtc_state->pch_pfit.force_thru = force_thru;
12950 }
12951
12952 static int
12953 intel_modeset_pipe_config(struct drm_crtc *crtc,
12954                           struct intel_crtc_state *pipe_config)
12955 {
12956         struct drm_atomic_state *state = pipe_config->base.state;
12957         struct intel_encoder *encoder;
12958         struct drm_connector *connector;
12959         struct drm_connector_state *connector_state;
12960         int base_bpp, ret = -EINVAL;
12961         int i;
12962         bool retry = true;
12963
12964         clear_intel_crtc_state(pipe_config);
12965
12966         pipe_config->cpu_transcoder =
12967                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12968
12969         /*
12970          * Sanitize sync polarity flags based on requested ones. If neither
12971          * positive or negative polarity is requested, treat this as meaning
12972          * negative polarity.
12973          */
12974         if (!(pipe_config->base.adjusted_mode.flags &
12975               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12976                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12977
12978         if (!(pipe_config->base.adjusted_mode.flags &
12979               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12980                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12981
12982         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12983                                              pipe_config);
12984         if (base_bpp < 0)
12985                 goto fail;
12986
12987         /*
12988          * Determine the real pipe dimensions. Note that stereo modes can
12989          * increase the actual pipe size due to the frame doubling and
12990          * insertion of additional space for blanks between the frame. This
12991          * is stored in the crtc timings. We use the requested mode to do this
12992          * computation to clearly distinguish it from the adjusted mode, which
12993          * can be changed by the connectors in the below retry loop.
12994          */
12995         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12996                                &pipe_config->pipe_src_w,
12997                                &pipe_config->pipe_src_h);
12998
12999         for_each_connector_in_state(state, connector, connector_state, i) {
13000                 if (connector_state->crtc != crtc)
13001                         continue;
13002
13003                 encoder = to_intel_encoder(connector_state->best_encoder);
13004
13005                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13006                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13007                         goto fail;
13008                 }
13009
13010                 /*
13011                  * Determine output_types before calling the .compute_config()
13012                  * hooks so that the hooks can use this information safely.
13013                  */
13014                 pipe_config->output_types |= 1 << encoder->type;
13015         }
13016
13017 encoder_retry:
13018         /* Ensure the port clock defaults are reset when retrying. */
13019         pipe_config->port_clock = 0;
13020         pipe_config->pixel_multiplier = 1;
13021
13022         /* Fill in default crtc timings, allow encoders to overwrite them. */
13023         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13024                               CRTC_STEREO_DOUBLE);
13025
13026         /* Pass our mode to the connectors and the CRTC to give them a chance to
13027          * adjust it according to limitations or connector properties, and also
13028          * a chance to reject the mode entirely.
13029          */
13030         for_each_connector_in_state(state, connector, connector_state, i) {
13031                 if (connector_state->crtc != crtc)
13032                         continue;
13033
13034                 encoder = to_intel_encoder(connector_state->best_encoder);
13035
13036                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13037                         DRM_DEBUG_KMS("Encoder config failure\n");
13038                         goto fail;
13039                 }
13040         }
13041
13042         /* Set default port clock if not overwritten by the encoder. Needs to be
13043          * done afterwards in case the encoder adjusts the mode. */
13044         if (!pipe_config->port_clock)
13045                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13046                         * pipe_config->pixel_multiplier;
13047
13048         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13049         if (ret < 0) {
13050                 DRM_DEBUG_KMS("CRTC fixup failed\n");
13051                 goto fail;
13052         }
13053
13054         if (ret == RETRY) {
13055                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13056                         ret = -EINVAL;
13057                         goto fail;
13058                 }
13059
13060                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13061                 retry = false;
13062                 goto encoder_retry;
13063         }
13064
13065         /* Dithering seems to not pass-through bits correctly when it should, so
13066          * only enable it on 6bpc panels. */
13067         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13068         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13069                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13070
13071 fail:
13072         return ret;
13073 }
13074
13075 static void
13076 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13077 {
13078         struct drm_crtc *crtc;
13079         struct drm_crtc_state *crtc_state;
13080         int i;
13081
13082         /* Double check state. */
13083         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13084                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13085
13086                 /* Update hwmode for vblank functions */
13087                 if (crtc->state->active)
13088                         crtc->hwmode = crtc->state->adjusted_mode;
13089                 else
13090                         crtc->hwmode.crtc_clock = 0;
13091
13092                 /*
13093                  * Update legacy state to satisfy fbc code. This can
13094                  * be removed when fbc uses the atomic state.
13095                  */
13096                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13097                         struct drm_plane_state *plane_state = crtc->primary->state;
13098
13099                         crtc->primary->fb = plane_state->fb;
13100                         crtc->x = plane_state->src_x >> 16;
13101                         crtc->y = plane_state->src_y >> 16;
13102                 }
13103         }
13104 }
13105
13106 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13107 {
13108         int diff;
13109
13110         if (clock1 == clock2)
13111                 return true;
13112
13113         if (!clock1 || !clock2)
13114                 return false;
13115
13116         diff = abs(clock1 - clock2);
13117
13118         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13119                 return true;
13120
13121         return false;
13122 }
13123
13124 static bool
13125 intel_compare_m_n(unsigned int m, unsigned int n,
13126                   unsigned int m2, unsigned int n2,
13127                   bool exact)
13128 {
13129         if (m == m2 && n == n2)
13130                 return true;
13131
13132         if (exact || !m || !n || !m2 || !n2)
13133                 return false;
13134
13135         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13136
13137         if (n > n2) {
13138                 while (n > n2) {
13139                         m2 <<= 1;
13140                         n2 <<= 1;
13141                 }
13142         } else if (n < n2) {
13143                 while (n < n2) {
13144                         m <<= 1;
13145                         n <<= 1;
13146                 }
13147         }
13148
13149         if (n != n2)
13150                 return false;
13151
13152         return intel_fuzzy_clock_check(m, m2);
13153 }
13154
13155 static bool
13156 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13157                        struct intel_link_m_n *m2_n2,
13158                        bool adjust)
13159 {
13160         if (m_n->tu == m2_n2->tu &&
13161             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13162                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13163             intel_compare_m_n(m_n->link_m, m_n->link_n,
13164                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13165                 if (adjust)
13166                         *m2_n2 = *m_n;
13167
13168                 return true;
13169         }
13170
13171         return false;
13172 }
13173
13174 static bool
13175 intel_pipe_config_compare(struct drm_device *dev,
13176                           struct intel_crtc_state *current_config,
13177                           struct intel_crtc_state *pipe_config,
13178                           bool adjust)
13179 {
13180         bool ret = true;
13181
13182 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13183         do { \
13184                 if (!adjust) \
13185                         DRM_ERROR(fmt, ##__VA_ARGS__); \
13186                 else \
13187                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13188         } while (0)
13189
13190 #define PIPE_CONF_CHECK_X(name) \
13191         if (current_config->name != pipe_config->name) { \
13192                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13193                           "(expected 0x%08x, found 0x%08x)\n", \
13194                           current_config->name, \
13195                           pipe_config->name); \
13196                 ret = false; \
13197         }
13198
13199 #define PIPE_CONF_CHECK_I(name) \
13200         if (current_config->name != pipe_config->name) { \
13201                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13202                           "(expected %i, found %i)\n", \
13203                           current_config->name, \
13204                           pipe_config->name); \
13205                 ret = false; \
13206         }
13207
13208 #define PIPE_CONF_CHECK_P(name) \
13209         if (current_config->name != pipe_config->name) { \
13210                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13211                           "(expected %p, found %p)\n", \
13212                           current_config->name, \
13213                           pipe_config->name); \
13214                 ret = false; \
13215         }
13216
13217 #define PIPE_CONF_CHECK_M_N(name) \
13218         if (!intel_compare_link_m_n(&current_config->name, \
13219                                     &pipe_config->name,\
13220                                     adjust)) { \
13221                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13222                           "(expected tu %i gmch %i/%i link %i/%i, " \
13223                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13224                           current_config->name.tu, \
13225                           current_config->name.gmch_m, \
13226                           current_config->name.gmch_n, \
13227                           current_config->name.link_m, \
13228                           current_config->name.link_n, \
13229                           pipe_config->name.tu, \
13230                           pipe_config->name.gmch_m, \
13231                           pipe_config->name.gmch_n, \
13232                           pipe_config->name.link_m, \
13233                           pipe_config->name.link_n); \
13234                 ret = false; \
13235         }
13236
13237 /* This is required for BDW+ where there is only one set of registers for
13238  * switching between high and low RR.
13239  * This macro can be used whenever a comparison has to be made between one
13240  * hw state and multiple sw state variables.
13241  */
13242 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13243         if (!intel_compare_link_m_n(&current_config->name, \
13244                                     &pipe_config->name, adjust) && \
13245             !intel_compare_link_m_n(&current_config->alt_name, \
13246                                     &pipe_config->name, adjust)) { \
13247                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13248                           "(expected tu %i gmch %i/%i link %i/%i, " \
13249                           "or tu %i gmch %i/%i link %i/%i, " \
13250                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13251                           current_config->name.tu, \
13252                           current_config->name.gmch_m, \
13253                           current_config->name.gmch_n, \
13254                           current_config->name.link_m, \
13255                           current_config->name.link_n, \
13256                           current_config->alt_name.tu, \
13257                           current_config->alt_name.gmch_m, \
13258                           current_config->alt_name.gmch_n, \
13259                           current_config->alt_name.link_m, \
13260                           current_config->alt_name.link_n, \
13261                           pipe_config->name.tu, \
13262                           pipe_config->name.gmch_m, \
13263                           pipe_config->name.gmch_n, \
13264                           pipe_config->name.link_m, \
13265                           pipe_config->name.link_n); \
13266                 ret = false; \
13267         }
13268
13269 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13270         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13271                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13272                           "(expected %i, found %i)\n", \
13273                           current_config->name & (mask), \
13274                           pipe_config->name & (mask)); \
13275                 ret = false; \
13276         }
13277
13278 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13279         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13280                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13281                           "(expected %i, found %i)\n", \
13282                           current_config->name, \
13283                           pipe_config->name); \
13284                 ret = false; \
13285         }
13286
13287 #define PIPE_CONF_QUIRK(quirk)  \
13288         ((current_config->quirks | pipe_config->quirks) & (quirk))
13289
13290         PIPE_CONF_CHECK_I(cpu_transcoder);
13291
13292         PIPE_CONF_CHECK_I(has_pch_encoder);
13293         PIPE_CONF_CHECK_I(fdi_lanes);
13294         PIPE_CONF_CHECK_M_N(fdi_m_n);
13295
13296         PIPE_CONF_CHECK_I(lane_count);
13297         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13298
13299         if (INTEL_INFO(dev)->gen < 8) {
13300                 PIPE_CONF_CHECK_M_N(dp_m_n);
13301
13302                 if (current_config->has_drrs)
13303                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13304         } else
13305                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13306
13307         PIPE_CONF_CHECK_X(output_types);
13308
13309         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13310         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13311         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13312         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13313         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13314         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13315
13316         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13317         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13318         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13319         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13320         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13321         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13322
13323         PIPE_CONF_CHECK_I(pixel_multiplier);
13324         PIPE_CONF_CHECK_I(has_hdmi_sink);
13325         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
13326             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
13327                 PIPE_CONF_CHECK_I(limited_color_range);
13328         PIPE_CONF_CHECK_I(has_infoframe);
13329
13330         PIPE_CONF_CHECK_I(has_audio);
13331
13332         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13333                               DRM_MODE_FLAG_INTERLACE);
13334
13335         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13336                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13337                                       DRM_MODE_FLAG_PHSYNC);
13338                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13339                                       DRM_MODE_FLAG_NHSYNC);
13340                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13341                                       DRM_MODE_FLAG_PVSYNC);
13342                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13343                                       DRM_MODE_FLAG_NVSYNC);
13344         }
13345
13346         PIPE_CONF_CHECK_X(gmch_pfit.control);
13347         /* pfit ratios are autocomputed by the hw on gen4+ */
13348         if (INTEL_INFO(dev)->gen < 4)
13349                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13350         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13351
13352         if (!adjust) {
13353                 PIPE_CONF_CHECK_I(pipe_src_w);
13354                 PIPE_CONF_CHECK_I(pipe_src_h);
13355
13356                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13357                 if (current_config->pch_pfit.enabled) {
13358                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13359                         PIPE_CONF_CHECK_X(pch_pfit.size);
13360                 }
13361
13362                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13363         }
13364
13365         /* BDW+ don't expose a synchronous way to read the state */
13366         if (IS_HASWELL(dev))
13367                 PIPE_CONF_CHECK_I(ips_enabled);
13368
13369         PIPE_CONF_CHECK_I(double_wide);
13370
13371         PIPE_CONF_CHECK_P(shared_dpll);
13372         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13373         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13374         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13375         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13376         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13377         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13378         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13379         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13380         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13381
13382         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13383         PIPE_CONF_CHECK_X(dsi_pll.div);
13384
13385         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13386                 PIPE_CONF_CHECK_I(pipe_bpp);
13387
13388         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13389         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13390
13391 #undef PIPE_CONF_CHECK_X
13392 #undef PIPE_CONF_CHECK_I
13393 #undef PIPE_CONF_CHECK_P
13394 #undef PIPE_CONF_CHECK_FLAGS
13395 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13396 #undef PIPE_CONF_QUIRK
13397 #undef INTEL_ERR_OR_DBG_KMS
13398
13399         return ret;
13400 }
13401
13402 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13403                                            const struct intel_crtc_state *pipe_config)
13404 {
13405         if (pipe_config->has_pch_encoder) {
13406                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13407                                                             &pipe_config->fdi_m_n);
13408                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13409
13410                 /*
13411                  * FDI already provided one idea for the dotclock.
13412                  * Yell if the encoder disagrees.
13413                  */
13414                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13415                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13416                      fdi_dotclock, dotclock);
13417         }
13418 }
13419
13420 static void verify_wm_state(struct drm_crtc *crtc,
13421                             struct drm_crtc_state *new_state)
13422 {
13423         struct drm_device *dev = crtc->dev;
13424         struct drm_i915_private *dev_priv = to_i915(dev);
13425         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13426         struct skl_ddb_entry *hw_entry, *sw_entry;
13427         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13428         const enum pipe pipe = intel_crtc->pipe;
13429         int plane;
13430
13431         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13432                 return;
13433
13434         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13435         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13436
13437         /* planes */
13438         for_each_plane(dev_priv, pipe, plane) {
13439                 hw_entry = &hw_ddb.plane[pipe][plane];
13440                 sw_entry = &sw_ddb->plane[pipe][plane];
13441
13442                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13443                         continue;
13444
13445                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13446                           "(expected (%u,%u), found (%u,%u))\n",
13447                           pipe_name(pipe), plane + 1,
13448                           sw_entry->start, sw_entry->end,
13449                           hw_entry->start, hw_entry->end);
13450         }
13451
13452         /*
13453          * cursor
13454          * If the cursor plane isn't active, we may not have updated it's ddb
13455          * allocation. In that case since the ddb allocation will be updated
13456          * once the plane becomes visible, we can skip this check
13457          */
13458         if (intel_crtc->cursor_addr) {
13459                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13460                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13461
13462                 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13463                         DRM_ERROR("mismatch in DDB state pipe %c cursor "
13464                                   "(expected (%u,%u), found (%u,%u))\n",
13465                                   pipe_name(pipe),
13466                                   sw_entry->start, sw_entry->end,
13467                                   hw_entry->start, hw_entry->end);
13468                 }
13469         }
13470 }
13471
13472 static void
13473 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13474 {
13475         struct drm_connector *connector;
13476
13477         drm_for_each_connector(connector, dev) {
13478                 struct drm_encoder *encoder = connector->encoder;
13479                 struct drm_connector_state *state = connector->state;
13480
13481                 if (state->crtc != crtc)
13482                         continue;
13483
13484                 intel_connector_verify_state(to_intel_connector(connector));
13485
13486                 I915_STATE_WARN(state->best_encoder != encoder,
13487                      "connector's atomic encoder doesn't match legacy encoder\n");
13488         }
13489 }
13490
13491 static void
13492 verify_encoder_state(struct drm_device *dev)
13493 {
13494         struct intel_encoder *encoder;
13495         struct intel_connector *connector;
13496
13497         for_each_intel_encoder(dev, encoder) {
13498                 bool enabled = false;
13499                 enum pipe pipe;
13500
13501                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13502                               encoder->base.base.id,
13503                               encoder->base.name);
13504
13505                 for_each_intel_connector(dev, connector) {
13506                         if (connector->base.state->best_encoder != &encoder->base)
13507                                 continue;
13508                         enabled = true;
13509
13510                         I915_STATE_WARN(connector->base.state->crtc !=
13511                                         encoder->base.crtc,
13512                              "connector's crtc doesn't match encoder crtc\n");
13513                 }
13514
13515                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13516                      "encoder's enabled state mismatch "
13517                      "(expected %i, found %i)\n",
13518                      !!encoder->base.crtc, enabled);
13519
13520                 if (!encoder->base.crtc) {
13521                         bool active;
13522
13523                         active = encoder->get_hw_state(encoder, &pipe);
13524                         I915_STATE_WARN(active,
13525                              "encoder detached but still enabled on pipe %c.\n",
13526                              pipe_name(pipe));
13527                 }
13528         }
13529 }
13530
13531 static void
13532 verify_crtc_state(struct drm_crtc *crtc,
13533                   struct drm_crtc_state *old_crtc_state,
13534                   struct drm_crtc_state *new_crtc_state)
13535 {
13536         struct drm_device *dev = crtc->dev;
13537         struct drm_i915_private *dev_priv = to_i915(dev);
13538         struct intel_encoder *encoder;
13539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13540         struct intel_crtc_state *pipe_config, *sw_config;
13541         struct drm_atomic_state *old_state;
13542         bool active;
13543
13544         old_state = old_crtc_state->state;
13545         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13546         pipe_config = to_intel_crtc_state(old_crtc_state);
13547         memset(pipe_config, 0, sizeof(*pipe_config));
13548         pipe_config->base.crtc = crtc;
13549         pipe_config->base.state = old_state;
13550
13551         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13552
13553         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13554
13555         /* hw state is inconsistent with the pipe quirk */
13556         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13557             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13558                 active = new_crtc_state->active;
13559
13560         I915_STATE_WARN(new_crtc_state->active != active,
13561              "crtc active state doesn't match with hw state "
13562              "(expected %i, found %i)\n", new_crtc_state->active, active);
13563
13564         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13565              "transitional active state does not match atomic hw state "
13566              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13567
13568         for_each_encoder_on_crtc(dev, crtc, encoder) {
13569                 enum pipe pipe;
13570
13571                 active = encoder->get_hw_state(encoder, &pipe);
13572                 I915_STATE_WARN(active != new_crtc_state->active,
13573                         "[ENCODER:%i] active %i with crtc active %i\n",
13574                         encoder->base.base.id, active, new_crtc_state->active);
13575
13576                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13577                                 "Encoder connected to wrong pipe %c\n",
13578                                 pipe_name(pipe));
13579
13580                 if (active) {
13581                         pipe_config->output_types |= 1 << encoder->type;
13582                         encoder->get_config(encoder, pipe_config);
13583                 }
13584         }
13585
13586         if (!new_crtc_state->active)
13587                 return;
13588
13589         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13590
13591         sw_config = to_intel_crtc_state(crtc->state);
13592         if (!intel_pipe_config_compare(dev, sw_config,
13593                                        pipe_config, false)) {
13594                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13595                 intel_dump_pipe_config(intel_crtc, pipe_config,
13596                                        "[hw state]");
13597                 intel_dump_pipe_config(intel_crtc, sw_config,
13598                                        "[sw state]");
13599         }
13600 }
13601
13602 static void
13603 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13604                          struct intel_shared_dpll *pll,
13605                          struct drm_crtc *crtc,
13606                          struct drm_crtc_state *new_state)
13607 {
13608         struct intel_dpll_hw_state dpll_hw_state;
13609         unsigned crtc_mask;
13610         bool active;
13611
13612         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13613
13614         DRM_DEBUG_KMS("%s\n", pll->name);
13615
13616         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13617
13618         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13619                 I915_STATE_WARN(!pll->on && pll->active_mask,
13620                      "pll in active use but not on in sw tracking\n");
13621                 I915_STATE_WARN(pll->on && !pll->active_mask,
13622                      "pll is on but not used by any active crtc\n");
13623                 I915_STATE_WARN(pll->on != active,
13624                      "pll on state mismatch (expected %i, found %i)\n",
13625                      pll->on, active);
13626         }
13627
13628         if (!crtc) {
13629                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13630                                 "more active pll users than references: %x vs %x\n",
13631                                 pll->active_mask, pll->config.crtc_mask);
13632
13633                 return;
13634         }
13635
13636         crtc_mask = 1 << drm_crtc_index(crtc);
13637
13638         if (new_state->active)
13639                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13640                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13641                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13642         else
13643                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13644                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13645                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13646
13647         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13648                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13649                         crtc_mask, pll->config.crtc_mask);
13650
13651         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13652                                           &dpll_hw_state,
13653                                           sizeof(dpll_hw_state)),
13654                         "pll hw state mismatch\n");
13655 }
13656
13657 static void
13658 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13659                          struct drm_crtc_state *old_crtc_state,
13660                          struct drm_crtc_state *new_crtc_state)
13661 {
13662         struct drm_i915_private *dev_priv = to_i915(dev);
13663         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13664         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13665
13666         if (new_state->shared_dpll)
13667                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13668
13669         if (old_state->shared_dpll &&
13670             old_state->shared_dpll != new_state->shared_dpll) {
13671                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13672                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13673
13674                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13675                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13676                                 pipe_name(drm_crtc_index(crtc)));
13677                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13678                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13679                                 pipe_name(drm_crtc_index(crtc)));
13680         }
13681 }
13682
13683 static void
13684 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13685                          struct drm_crtc_state *old_state,
13686                          struct drm_crtc_state *new_state)
13687 {
13688         if (!needs_modeset(new_state) &&
13689             !to_intel_crtc_state(new_state)->update_pipe)
13690                 return;
13691
13692         verify_wm_state(crtc, new_state);
13693         verify_connector_state(crtc->dev, crtc);
13694         verify_crtc_state(crtc, old_state, new_state);
13695         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13696 }
13697
13698 static void
13699 verify_disabled_dpll_state(struct drm_device *dev)
13700 {
13701         struct drm_i915_private *dev_priv = to_i915(dev);
13702         int i;
13703
13704         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13705                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13706 }
13707
13708 static void
13709 intel_modeset_verify_disabled(struct drm_device *dev)
13710 {
13711         verify_encoder_state(dev);
13712         verify_connector_state(dev, NULL);
13713         verify_disabled_dpll_state(dev);
13714 }
13715
13716 static void update_scanline_offset(struct intel_crtc *crtc)
13717 {
13718         struct drm_device *dev = crtc->base.dev;
13719
13720         /*
13721          * The scanline counter increments at the leading edge of hsync.
13722          *
13723          * On most platforms it starts counting from vtotal-1 on the
13724          * first active line. That means the scanline counter value is
13725          * always one less than what we would expect. Ie. just after
13726          * start of vblank, which also occurs at start of hsync (on the
13727          * last active line), the scanline counter will read vblank_start-1.
13728          *
13729          * On gen2 the scanline counter starts counting from 1 instead
13730          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13731          * to keep the value positive), instead of adding one.
13732          *
13733          * On HSW+ the behaviour of the scanline counter depends on the output
13734          * type. For DP ports it behaves like most other platforms, but on HDMI
13735          * there's an extra 1 line difference. So we need to add two instead of
13736          * one to the value.
13737          */
13738         if (IS_GEN2(dev)) {
13739                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13740                 int vtotal;
13741
13742                 vtotal = adjusted_mode->crtc_vtotal;
13743                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13744                         vtotal /= 2;
13745
13746                 crtc->scanline_offset = vtotal - 1;
13747         } else if (HAS_DDI(dev) &&
13748                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13749                 crtc->scanline_offset = 2;
13750         } else
13751                 crtc->scanline_offset = 1;
13752 }
13753
13754 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13755 {
13756         struct drm_device *dev = state->dev;
13757         struct drm_i915_private *dev_priv = to_i915(dev);
13758         struct intel_shared_dpll_config *shared_dpll = NULL;
13759         struct drm_crtc *crtc;
13760         struct drm_crtc_state *crtc_state;
13761         int i;
13762
13763         if (!dev_priv->display.crtc_compute_clock)
13764                 return;
13765
13766         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13767                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13768                 struct intel_shared_dpll *old_dpll =
13769                         to_intel_crtc_state(crtc->state)->shared_dpll;
13770
13771                 if (!needs_modeset(crtc_state))
13772                         continue;
13773
13774                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13775
13776                 if (!old_dpll)
13777                         continue;
13778
13779                 if (!shared_dpll)
13780                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13781
13782                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13783         }
13784 }
13785
13786 /*
13787  * This implements the workaround described in the "notes" section of the mode
13788  * set sequence documentation. When going from no pipes or single pipe to
13789  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13790  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13791  */
13792 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13793 {
13794         struct drm_crtc_state *crtc_state;
13795         struct intel_crtc *intel_crtc;
13796         struct drm_crtc *crtc;
13797         struct intel_crtc_state *first_crtc_state = NULL;
13798         struct intel_crtc_state *other_crtc_state = NULL;
13799         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13800         int i;
13801
13802         /* look at all crtc's that are going to be enabled in during modeset */
13803         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13804                 intel_crtc = to_intel_crtc(crtc);
13805
13806                 if (!crtc_state->active || !needs_modeset(crtc_state))
13807                         continue;
13808
13809                 if (first_crtc_state) {
13810                         other_crtc_state = to_intel_crtc_state(crtc_state);
13811                         break;
13812                 } else {
13813                         first_crtc_state = to_intel_crtc_state(crtc_state);
13814                         first_pipe = intel_crtc->pipe;
13815                 }
13816         }
13817
13818         /* No workaround needed? */
13819         if (!first_crtc_state)
13820                 return 0;
13821
13822         /* w/a possibly needed, check how many crtc's are already enabled. */
13823         for_each_intel_crtc(state->dev, intel_crtc) {
13824                 struct intel_crtc_state *pipe_config;
13825
13826                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13827                 if (IS_ERR(pipe_config))
13828                         return PTR_ERR(pipe_config);
13829
13830                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13831
13832                 if (!pipe_config->base.active ||
13833                     needs_modeset(&pipe_config->base))
13834                         continue;
13835
13836                 /* 2 or more enabled crtcs means no need for w/a */
13837                 if (enabled_pipe != INVALID_PIPE)
13838                         return 0;
13839
13840                 enabled_pipe = intel_crtc->pipe;
13841         }
13842
13843         if (enabled_pipe != INVALID_PIPE)
13844                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13845         else if (other_crtc_state)
13846                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13847
13848         return 0;
13849 }
13850
13851 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13852 {
13853         struct drm_crtc *crtc;
13854         struct drm_crtc_state *crtc_state;
13855         int ret = 0;
13856
13857         /* add all active pipes to the state */
13858         for_each_crtc(state->dev, crtc) {
13859                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13860                 if (IS_ERR(crtc_state))
13861                         return PTR_ERR(crtc_state);
13862
13863                 if (!crtc_state->active || needs_modeset(crtc_state))
13864                         continue;
13865
13866                 crtc_state->mode_changed = true;
13867
13868                 ret = drm_atomic_add_affected_connectors(state, crtc);
13869                 if (ret)
13870                         break;
13871
13872                 ret = drm_atomic_add_affected_planes(state, crtc);
13873                 if (ret)
13874                         break;
13875         }
13876
13877         return ret;
13878 }
13879
13880 static int intel_modeset_checks(struct drm_atomic_state *state)
13881 {
13882         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13883         struct drm_i915_private *dev_priv = to_i915(state->dev);
13884         struct drm_crtc *crtc;
13885         struct drm_crtc_state *crtc_state;
13886         int ret = 0, i;
13887
13888         if (!check_digital_port_conflicts(state)) {
13889                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13890                 return -EINVAL;
13891         }
13892
13893         intel_state->modeset = true;
13894         intel_state->active_crtcs = dev_priv->active_crtcs;
13895
13896         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13897                 if (crtc_state->active)
13898                         intel_state->active_crtcs |= 1 << i;
13899                 else
13900                         intel_state->active_crtcs &= ~(1 << i);
13901
13902                 if (crtc_state->active != crtc->state->active)
13903                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13904         }
13905
13906         /*
13907          * See if the config requires any additional preparation, e.g.
13908          * to adjust global state with pipes off.  We need to do this
13909          * here so we can get the modeset_pipe updated config for the new
13910          * mode set on this crtc.  For other crtcs we need to use the
13911          * adjusted_mode bits in the crtc directly.
13912          */
13913         if (dev_priv->display.modeset_calc_cdclk) {
13914                 if (!intel_state->cdclk_pll_vco)
13915                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13916                 if (!intel_state->cdclk_pll_vco)
13917                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13918
13919                 ret = dev_priv->display.modeset_calc_cdclk(state);
13920                 if (ret < 0)
13921                         return ret;
13922
13923                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13924                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13925                         ret = intel_modeset_all_pipes(state);
13926
13927                 if (ret < 0)
13928                         return ret;
13929
13930                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13931                               intel_state->cdclk, intel_state->dev_cdclk);
13932         } else
13933                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13934
13935         intel_modeset_clear_plls(state);
13936
13937         if (IS_HASWELL(dev_priv))
13938                 return haswell_mode_set_planes_workaround(state);
13939
13940         return 0;
13941 }
13942
13943 /*
13944  * Handle calculation of various watermark data at the end of the atomic check
13945  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13946  * handlers to ensure that all derived state has been updated.
13947  */
13948 static int calc_watermark_data(struct drm_atomic_state *state)
13949 {
13950         struct drm_device *dev = state->dev;
13951         struct drm_i915_private *dev_priv = to_i915(dev);
13952
13953         /* Is there platform-specific watermark information to calculate? */
13954         if (dev_priv->display.compute_global_watermarks)
13955                 return dev_priv->display.compute_global_watermarks(state);
13956
13957         return 0;
13958 }
13959
13960 /**
13961  * intel_atomic_check - validate state object
13962  * @dev: drm device
13963  * @state: state to validate
13964  */
13965 static int intel_atomic_check(struct drm_device *dev,
13966                               struct drm_atomic_state *state)
13967 {
13968         struct drm_i915_private *dev_priv = to_i915(dev);
13969         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13970         struct drm_crtc *crtc;
13971         struct drm_crtc_state *crtc_state;
13972         int ret, i;
13973         bool any_ms = false;
13974
13975         ret = drm_atomic_helper_check_modeset(dev, state);
13976         if (ret)
13977                 return ret;
13978
13979         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13980                 struct intel_crtc_state *pipe_config =
13981                         to_intel_crtc_state(crtc_state);
13982
13983                 /* Catch I915_MODE_FLAG_INHERITED */
13984                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13985                         crtc_state->mode_changed = true;
13986
13987                 if (!needs_modeset(crtc_state))
13988                         continue;
13989
13990                 if (!crtc_state->enable) {
13991                         any_ms = true;
13992                         continue;
13993                 }
13994
13995                 /* FIXME: For only active_changed we shouldn't need to do any
13996                  * state recomputation at all. */
13997
13998                 ret = drm_atomic_add_affected_connectors(state, crtc);
13999                 if (ret)
14000                         return ret;
14001
14002                 ret = intel_modeset_pipe_config(crtc, pipe_config);
14003                 if (ret) {
14004                         intel_dump_pipe_config(to_intel_crtc(crtc),
14005                                                pipe_config, "[failed]");
14006                         return ret;
14007                 }
14008
14009                 if (i915.fastboot &&
14010                     intel_pipe_config_compare(dev,
14011                                         to_intel_crtc_state(crtc->state),
14012                                         pipe_config, true)) {
14013                         crtc_state->mode_changed = false;
14014                         to_intel_crtc_state(crtc_state)->update_pipe = true;
14015                 }
14016
14017                 if (needs_modeset(crtc_state))
14018                         any_ms = true;
14019
14020                 ret = drm_atomic_add_affected_planes(state, crtc);
14021                 if (ret)
14022                         return ret;
14023
14024                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14025                                        needs_modeset(crtc_state) ?
14026                                        "[modeset]" : "[fastset]");
14027         }
14028
14029         if (any_ms) {
14030                 ret = intel_modeset_checks(state);
14031
14032                 if (ret)
14033                         return ret;
14034         } else
14035                 intel_state->cdclk = dev_priv->cdclk_freq;
14036
14037         ret = drm_atomic_helper_check_planes(dev, state);
14038         if (ret)
14039                 return ret;
14040
14041         intel_fbc_choose_crtc(dev_priv, state);
14042         return calc_watermark_data(state);
14043 }
14044
14045 static int intel_atomic_prepare_commit(struct drm_device *dev,
14046                                        struct drm_atomic_state *state,
14047                                        bool nonblock)
14048 {
14049         struct drm_i915_private *dev_priv = to_i915(dev);
14050         struct drm_plane_state *plane_state;
14051         struct drm_crtc_state *crtc_state;
14052         struct drm_plane *plane;
14053         struct drm_crtc *crtc;
14054         int i, ret;
14055
14056         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14057                 if (state->legacy_cursor_update)
14058                         continue;
14059
14060                 ret = intel_crtc_wait_for_pending_flips(crtc);
14061                 if (ret)
14062                         return ret;
14063
14064                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14065                         flush_workqueue(dev_priv->wq);
14066         }
14067
14068         ret = mutex_lock_interruptible(&dev->struct_mutex);
14069         if (ret)
14070                 return ret;
14071
14072         ret = drm_atomic_helper_prepare_planes(dev, state);
14073         mutex_unlock(&dev->struct_mutex);
14074
14075         if (!ret && !nonblock) {
14076                 for_each_plane_in_state(state, plane, plane_state, i) {
14077                         struct intel_plane_state *intel_plane_state =
14078                                 to_intel_plane_state(plane_state);
14079
14080                         if (!intel_plane_state->wait_req)
14081                                 continue;
14082
14083                         ret = i915_wait_request(intel_plane_state->wait_req,
14084                                                 I915_WAIT_INTERRUPTIBLE,
14085                                                 NULL, NULL);
14086                         if (ret) {
14087                                 /* Any hang should be swallowed by the wait */
14088                                 WARN_ON(ret == -EIO);
14089                                 mutex_lock(&dev->struct_mutex);
14090                                 drm_atomic_helper_cleanup_planes(dev, state);
14091                                 mutex_unlock(&dev->struct_mutex);
14092                                 break;
14093                         }
14094                 }
14095         }
14096
14097         return ret;
14098 }
14099
14100 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14101 {
14102         struct drm_device *dev = crtc->base.dev;
14103
14104         if (!dev->max_vblank_count)
14105                 return drm_accurate_vblank_count(&crtc->base);
14106
14107         return dev->driver->get_vblank_counter(dev, crtc->pipe);
14108 }
14109
14110 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14111                                           struct drm_i915_private *dev_priv,
14112                                           unsigned crtc_mask)
14113 {
14114         unsigned last_vblank_count[I915_MAX_PIPES];
14115         enum pipe pipe;
14116         int ret;
14117
14118         if (!crtc_mask)
14119                 return;
14120
14121         for_each_pipe(dev_priv, pipe) {
14122                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14123
14124                 if (!((1 << pipe) & crtc_mask))
14125                         continue;
14126
14127                 ret = drm_crtc_vblank_get(crtc);
14128                 if (WARN_ON(ret != 0)) {
14129                         crtc_mask &= ~(1 << pipe);
14130                         continue;
14131                 }
14132
14133                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14134         }
14135
14136         for_each_pipe(dev_priv, pipe) {
14137                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14138                 long lret;
14139
14140                 if (!((1 << pipe) & crtc_mask))
14141                         continue;
14142
14143                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14144                                 last_vblank_count[pipe] !=
14145                                         drm_crtc_vblank_count(crtc),
14146                                 msecs_to_jiffies(50));
14147
14148                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14149
14150                 drm_crtc_vblank_put(crtc);
14151         }
14152 }
14153
14154 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14155 {
14156         /* fb updated, need to unpin old fb */
14157         if (crtc_state->fb_changed)
14158                 return true;
14159
14160         /* wm changes, need vblank before final wm's */
14161         if (crtc_state->update_wm_post)
14162                 return true;
14163
14164         /*
14165          * cxsr is re-enabled after vblank.
14166          * This is already handled by crtc_state->update_wm_post,
14167          * but added for clarity.
14168          */
14169         if (crtc_state->disable_cxsr)
14170                 return true;
14171
14172         return false;
14173 }
14174
14175 static void intel_update_crtc(struct drm_crtc *crtc,
14176                               struct drm_atomic_state *state,
14177                               struct drm_crtc_state *old_crtc_state,
14178                               unsigned int *crtc_vblank_mask)
14179 {
14180         struct drm_device *dev = crtc->dev;
14181         struct drm_i915_private *dev_priv = to_i915(dev);
14182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14183         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14184         bool modeset = needs_modeset(crtc->state);
14185
14186         if (modeset) {
14187                 update_scanline_offset(intel_crtc);
14188                 dev_priv->display.crtc_enable(pipe_config, state);
14189         } else {
14190                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14191         }
14192
14193         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14194                 intel_fbc_enable(
14195                     intel_crtc, pipe_config,
14196                     to_intel_plane_state(crtc->primary->state));
14197         }
14198
14199         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14200
14201         if (needs_vblank_wait(pipe_config))
14202                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14203 }
14204
14205 static void intel_update_crtcs(struct drm_atomic_state *state,
14206                                unsigned int *crtc_vblank_mask)
14207 {
14208         struct drm_crtc *crtc;
14209         struct drm_crtc_state *old_crtc_state;
14210         int i;
14211
14212         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14213                 if (!crtc->state->active)
14214                         continue;
14215
14216                 intel_update_crtc(crtc, state, old_crtc_state,
14217                                   crtc_vblank_mask);
14218         }
14219 }
14220
14221 static void skl_update_crtcs(struct drm_atomic_state *state,
14222                              unsigned int *crtc_vblank_mask)
14223 {
14224         struct drm_device *dev = state->dev;
14225         struct drm_i915_private *dev_priv = to_i915(dev);
14226         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14227         struct drm_crtc *crtc;
14228         struct drm_crtc_state *old_crtc_state;
14229         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
14230         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
14231         unsigned int updated = 0;
14232         bool progress;
14233         enum pipe pipe;
14234
14235         /*
14236          * Whenever the number of active pipes changes, we need to make sure we
14237          * update the pipes in the right order so that their ddb allocations
14238          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14239          * cause pipe underruns and other bad stuff.
14240          */
14241         do {
14242                 int i;
14243                 progress = false;
14244
14245                 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14246                         bool vbl_wait = false;
14247                         unsigned int cmask = drm_crtc_mask(crtc);
14248                         pipe = to_intel_crtc(crtc)->pipe;
14249
14250                         if (updated & cmask || !crtc->state->active)
14251                                 continue;
14252                         if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb,
14253                                                         pipe))
14254                                 continue;
14255
14256                         updated |= cmask;
14257
14258                         /*
14259                          * If this is an already active pipe, it's DDB changed,
14260                          * and this isn't the last pipe that needs updating
14261                          * then we need to wait for a vblank to pass for the
14262                          * new ddb allocation to take effect.
14263                          */
14264                         if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) &&
14265                             !crtc->state->active_changed &&
14266                             intel_state->wm_results.dirty_pipes != updated)
14267                                 vbl_wait = true;
14268
14269                         intel_update_crtc(crtc, state, old_crtc_state,
14270                                           crtc_vblank_mask);
14271
14272                         if (vbl_wait)
14273                                 intel_wait_for_vblank(dev, pipe);
14274
14275                         progress = true;
14276                 }
14277         } while (progress);
14278 }
14279
14280 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14281 {
14282         struct drm_device *dev = state->dev;
14283         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14284         struct drm_i915_private *dev_priv = to_i915(dev);
14285         struct drm_crtc_state *old_crtc_state;
14286         struct drm_crtc *crtc;
14287         struct intel_crtc_state *intel_cstate;
14288         struct drm_plane *plane;
14289         struct drm_plane_state *plane_state;
14290         bool hw_check = intel_state->modeset;
14291         unsigned long put_domains[I915_MAX_PIPES] = {};
14292         unsigned crtc_vblank_mask = 0;
14293         int i, ret;
14294
14295         for_each_plane_in_state(state, plane, plane_state, i) {
14296                 struct intel_plane_state *intel_plane_state =
14297                         to_intel_plane_state(plane_state);
14298
14299                 if (!intel_plane_state->wait_req)
14300                         continue;
14301
14302                 ret = i915_wait_request(intel_plane_state->wait_req,
14303                                         0, NULL, NULL);
14304                 /* EIO should be eaten, and we can't get interrupted in the
14305                  * worker, and blocking commits have waited already. */
14306                 WARN_ON(ret);
14307         }
14308
14309         drm_atomic_helper_wait_for_dependencies(state);
14310
14311         if (intel_state->modeset) {
14312                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14313                        sizeof(intel_state->min_pixclk));
14314                 dev_priv->active_crtcs = intel_state->active_crtcs;
14315                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14316
14317                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14318         }
14319
14320         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14321                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14322
14323                 if (needs_modeset(crtc->state) ||
14324                     to_intel_crtc_state(crtc->state)->update_pipe) {
14325                         hw_check = true;
14326
14327                         put_domains[to_intel_crtc(crtc)->pipe] =
14328                                 modeset_get_crtc_power_domains(crtc,
14329                                         to_intel_crtc_state(crtc->state));
14330                 }
14331
14332                 if (!needs_modeset(crtc->state))
14333                         continue;
14334
14335                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14336
14337                 if (old_crtc_state->active) {
14338                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14339                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14340                         intel_crtc->active = false;
14341                         intel_fbc_disable(intel_crtc);
14342                         intel_disable_shared_dpll(intel_crtc);
14343
14344                         /*
14345                          * Underruns don't always raise
14346                          * interrupts, so check manually.
14347                          */
14348                         intel_check_cpu_fifo_underruns(dev_priv);
14349                         intel_check_pch_fifo_underruns(dev_priv);
14350
14351                         if (!crtc->state->active)
14352                                 intel_update_watermarks(crtc);
14353                 }
14354         }
14355
14356         /* Only after disabling all output pipelines that will be changed can we
14357          * update the the output configuration. */
14358         intel_modeset_update_crtc_state(state);
14359
14360         if (intel_state->modeset) {
14361                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14362
14363                 if (dev_priv->display.modeset_commit_cdclk &&
14364                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14365                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14366                         dev_priv->display.modeset_commit_cdclk(state);
14367
14368                 /*
14369                  * SKL workaround: bspec recommends we disable the SAGV when we
14370                  * have more then one pipe enabled
14371                  */
14372                 if (IS_SKYLAKE(dev_priv) && !skl_can_enable_sagv(state))
14373                         skl_disable_sagv(dev_priv);
14374
14375                 intel_modeset_verify_disabled(dev);
14376         }
14377
14378         /* Complete the events for pipes that have now been disabled */
14379         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14380                 bool modeset = needs_modeset(crtc->state);
14381
14382                 /* Complete events for now disable pipes here. */
14383                 if (modeset && !crtc->state->active && crtc->state->event) {
14384                         spin_lock_irq(&dev->event_lock);
14385                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14386                         spin_unlock_irq(&dev->event_lock);
14387
14388                         crtc->state->event = NULL;
14389                 }
14390         }
14391
14392         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14393         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14394
14395         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14396          * already, but still need the state for the delayed optimization. To
14397          * fix this:
14398          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14399          * - schedule that vblank worker _before_ calling hw_done
14400          * - at the start of commit_tail, cancel it _synchrously
14401          * - switch over to the vblank wait helper in the core after that since
14402          *   we don't need out special handling any more.
14403          */
14404         if (!state->legacy_cursor_update)
14405                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14406
14407         /*
14408          * Now that the vblank has passed, we can go ahead and program the
14409          * optimal watermarks on platforms that need two-step watermark
14410          * programming.
14411          *
14412          * TODO: Move this (and other cleanup) to an async worker eventually.
14413          */
14414         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14415                 intel_cstate = to_intel_crtc_state(crtc->state);
14416
14417                 if (dev_priv->display.optimize_watermarks)
14418                         dev_priv->display.optimize_watermarks(intel_cstate);
14419         }
14420
14421         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14422                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14423
14424                 if (put_domains[i])
14425                         modeset_put_power_domains(dev_priv, put_domains[i]);
14426
14427                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14428         }
14429
14430         if (IS_SKYLAKE(dev_priv) && intel_state->modeset &&
14431             skl_can_enable_sagv(state))
14432                 skl_enable_sagv(dev_priv);
14433
14434         drm_atomic_helper_commit_hw_done(state);
14435
14436         if (intel_state->modeset)
14437                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14438
14439         mutex_lock(&dev->struct_mutex);
14440         drm_atomic_helper_cleanup_planes(dev, state);
14441         mutex_unlock(&dev->struct_mutex);
14442
14443         drm_atomic_helper_commit_cleanup_done(state);
14444
14445         drm_atomic_state_put(state);
14446
14447         /* As one of the primary mmio accessors, KMS has a high likelihood
14448          * of triggering bugs in unclaimed access. After we finish
14449          * modesetting, see if an error has been flagged, and if so
14450          * enable debugging for the next modeset - and hope we catch
14451          * the culprit.
14452          *
14453          * XXX note that we assume display power is on at this point.
14454          * This might hold true now but we need to add pm helper to check
14455          * unclaimed only when the hardware is on, as atomic commits
14456          * can happen also when the device is completely off.
14457          */
14458         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14459 }
14460
14461 static void intel_atomic_commit_work(struct work_struct *work)
14462 {
14463         struct drm_atomic_state *state = container_of(work,
14464                                                       struct drm_atomic_state,
14465                                                       commit_work);
14466         intel_atomic_commit_tail(state);
14467 }
14468
14469 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14470 {
14471         struct drm_plane_state *old_plane_state;
14472         struct drm_plane *plane;
14473         int i;
14474
14475         for_each_plane_in_state(state, plane, old_plane_state, i)
14476                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14477                                   intel_fb_obj(plane->state->fb),
14478                                   to_intel_plane(plane)->frontbuffer_bit);
14479 }
14480
14481 /**
14482  * intel_atomic_commit - commit validated state object
14483  * @dev: DRM device
14484  * @state: the top-level driver state object
14485  * @nonblock: nonblocking commit
14486  *
14487  * This function commits a top-level state object that has been validated
14488  * with drm_atomic_helper_check().
14489  *
14490  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
14491  * nonblocking commits are only safe for pure plane updates. Everything else
14492  * should work though.
14493  *
14494  * RETURNS
14495  * Zero for success or -errno.
14496  */
14497 static int intel_atomic_commit(struct drm_device *dev,
14498                                struct drm_atomic_state *state,
14499                                bool nonblock)
14500 {
14501         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14502         struct drm_i915_private *dev_priv = to_i915(dev);
14503         int ret = 0;
14504
14505         if (intel_state->modeset && nonblock) {
14506                 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14507                 return -EINVAL;
14508         }
14509
14510         ret = drm_atomic_helper_setup_commit(state, nonblock);
14511         if (ret)
14512                 return ret;
14513
14514         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14515
14516         ret = intel_atomic_prepare_commit(dev, state, nonblock);
14517         if (ret) {
14518                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14519                 return ret;
14520         }
14521
14522         drm_atomic_helper_swap_state(state, true);
14523         dev_priv->wm.distrust_bios_wm = false;
14524         dev_priv->wm.skl_results = intel_state->wm_results;
14525         intel_shared_dpll_commit(state);
14526         intel_atomic_track_fbs(state);
14527
14528         drm_atomic_state_get(state);
14529         if (nonblock)
14530                 queue_work(system_unbound_wq, &state->commit_work);
14531         else
14532                 intel_atomic_commit_tail(state);
14533
14534         return 0;
14535 }
14536
14537 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14538 {
14539         struct drm_device *dev = crtc->dev;
14540         struct drm_atomic_state *state;
14541         struct drm_crtc_state *crtc_state;
14542         int ret;
14543
14544         state = drm_atomic_state_alloc(dev);
14545         if (!state) {
14546                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14547                               crtc->base.id, crtc->name);
14548                 return;
14549         }
14550
14551         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14552
14553 retry:
14554         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14555         ret = PTR_ERR_OR_ZERO(crtc_state);
14556         if (!ret) {
14557                 if (!crtc_state->active)
14558                         goto out;
14559
14560                 crtc_state->mode_changed = true;
14561                 ret = drm_atomic_commit(state);
14562         }
14563
14564         if (ret == -EDEADLK) {
14565                 drm_atomic_state_clear(state);
14566                 drm_modeset_backoff(state->acquire_ctx);
14567                 goto retry;
14568         }
14569
14570 out:
14571         drm_atomic_state_put(state);
14572 }
14573
14574 /*
14575  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14576  *        drm_atomic_helper_legacy_gamma_set() directly.
14577  */
14578 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14579                                          u16 *red, u16 *green, u16 *blue,
14580                                          uint32_t size)
14581 {
14582         struct drm_device *dev = crtc->dev;
14583         struct drm_mode_config *config = &dev->mode_config;
14584         struct drm_crtc_state *state;
14585         int ret;
14586
14587         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14588         if (ret)
14589                 return ret;
14590
14591         /*
14592          * Make sure we update the legacy properties so this works when
14593          * atomic is not enabled.
14594          */
14595
14596         state = crtc->state;
14597
14598         drm_object_property_set_value(&crtc->base,
14599                                       config->degamma_lut_property,
14600                                       (state->degamma_lut) ?
14601                                       state->degamma_lut->base.id : 0);
14602
14603         drm_object_property_set_value(&crtc->base,
14604                                       config->ctm_property,
14605                                       (state->ctm) ?
14606                                       state->ctm->base.id : 0);
14607
14608         drm_object_property_set_value(&crtc->base,
14609                                       config->gamma_lut_property,
14610                                       (state->gamma_lut) ?
14611                                       state->gamma_lut->base.id : 0);
14612
14613         return 0;
14614 }
14615
14616 static const struct drm_crtc_funcs intel_crtc_funcs = {
14617         .gamma_set = intel_atomic_legacy_gamma_set,
14618         .set_config = drm_atomic_helper_set_config,
14619         .set_property = drm_atomic_helper_crtc_set_property,
14620         .destroy = intel_crtc_destroy,
14621         .page_flip = intel_crtc_page_flip,
14622         .atomic_duplicate_state = intel_crtc_duplicate_state,
14623         .atomic_destroy_state = intel_crtc_destroy_state,
14624 };
14625
14626 /**
14627  * intel_prepare_plane_fb - Prepare fb for usage on plane
14628  * @plane: drm plane to prepare for
14629  * @fb: framebuffer to prepare for presentation
14630  *
14631  * Prepares a framebuffer for usage on a display plane.  Generally this
14632  * involves pinning the underlying object and updating the frontbuffer tracking
14633  * bits.  Some older platforms need special physical address handling for
14634  * cursor planes.
14635  *
14636  * Must be called with struct_mutex held.
14637  *
14638  * Returns 0 on success, negative error code on failure.
14639  */
14640 int
14641 intel_prepare_plane_fb(struct drm_plane *plane,
14642                        struct drm_plane_state *new_state)
14643 {
14644         struct drm_device *dev = plane->dev;
14645         struct drm_framebuffer *fb = new_state->fb;
14646         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14647         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14648         struct reservation_object *resv;
14649         int ret = 0;
14650
14651         if (!obj && !old_obj)
14652                 return 0;
14653
14654         if (old_obj) {
14655                 struct drm_crtc_state *crtc_state =
14656                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14657
14658                 /* Big Hammer, we also need to ensure that any pending
14659                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14660                  * current scanout is retired before unpinning the old
14661                  * framebuffer. Note that we rely on userspace rendering
14662                  * into the buffer attached to the pipe they are waiting
14663                  * on. If not, userspace generates a GPU hang with IPEHR
14664                  * point to the MI_WAIT_FOR_EVENT.
14665                  *
14666                  * This should only fail upon a hung GPU, in which case we
14667                  * can safely continue.
14668                  */
14669                 if (needs_modeset(crtc_state))
14670                         ret = i915_gem_object_wait_rendering(old_obj, true);
14671                 if (ret) {
14672                         /* GPU hangs should have been swallowed by the wait */
14673                         WARN_ON(ret == -EIO);
14674                         return ret;
14675                 }
14676         }
14677
14678         if (!obj)
14679                 return 0;
14680
14681         /* For framebuffer backed by dmabuf, wait for fence */
14682         resv = i915_gem_object_get_dmabuf_resv(obj);
14683         if (resv) {
14684                 long lret;
14685
14686                 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14687                                                            MAX_SCHEDULE_TIMEOUT);
14688                 if (lret == -ERESTARTSYS)
14689                         return lret;
14690
14691                 WARN(lret < 0, "waiting returns %li\n", lret);
14692         }
14693
14694         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14695             INTEL_INFO(dev)->cursor_needs_physical) {
14696                 int align = IS_I830(dev) ? 16 * 1024 : 256;
14697                 ret = i915_gem_object_attach_phys(obj, align);
14698                 if (ret)
14699                         DRM_DEBUG_KMS("failed to attach phys object\n");
14700         } else {
14701                 struct i915_vma *vma;
14702
14703                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14704                 if (IS_ERR(vma))
14705                         ret = PTR_ERR(vma);
14706         }
14707
14708         if (ret == 0) {
14709                 to_intel_plane_state(new_state)->wait_req =
14710                         i915_gem_active_get(&obj->last_write,
14711                                             &obj->base.dev->struct_mutex);
14712         }
14713
14714         return ret;
14715 }
14716
14717 /**
14718  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14719  * @plane: drm plane to clean up for
14720  * @fb: old framebuffer that was on plane
14721  *
14722  * Cleans up a framebuffer that has just been removed from a plane.
14723  *
14724  * Must be called with struct_mutex held.
14725  */
14726 void
14727 intel_cleanup_plane_fb(struct drm_plane *plane,
14728                        struct drm_plane_state *old_state)
14729 {
14730         struct drm_device *dev = plane->dev;
14731         struct intel_plane_state *old_intel_state;
14732         struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14733         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14734         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14735
14736         old_intel_state = to_intel_plane_state(old_state);
14737
14738         if (!obj && !old_obj)
14739                 return;
14740
14741         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14742             !INTEL_INFO(dev)->cursor_needs_physical))
14743                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14744
14745         i915_gem_request_assign(&intel_state->wait_req, NULL);
14746         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14747 }
14748
14749 int
14750 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14751 {
14752         int max_scale;
14753         int crtc_clock, cdclk;
14754
14755         if (!intel_crtc || !crtc_state->base.enable)
14756                 return DRM_PLANE_HELPER_NO_SCALING;
14757
14758         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14759         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14760
14761         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14762                 return DRM_PLANE_HELPER_NO_SCALING;
14763
14764         /*
14765          * skl max scale is lower of:
14766          *    close to 3 but not 3, -1 is for that purpose
14767          *            or
14768          *    cdclk/crtc_clock
14769          */
14770         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14771
14772         return max_scale;
14773 }
14774
14775 static int
14776 intel_check_primary_plane(struct drm_plane *plane,
14777                           struct intel_crtc_state *crtc_state,
14778                           struct intel_plane_state *state)
14779 {
14780         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14781         struct drm_crtc *crtc = state->base.crtc;
14782         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14783         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14784         bool can_position = false;
14785         int ret;
14786
14787         if (INTEL_GEN(dev_priv) >= 9) {
14788                 /* use scaler when colorkey is not required */
14789                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14790                         min_scale = 1;
14791                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14792                 }
14793                 can_position = true;
14794         }
14795
14796         ret = drm_plane_helper_check_state(&state->base,
14797                                            &state->clip,
14798                                            min_scale, max_scale,
14799                                            can_position, true);
14800         if (ret)
14801                 return ret;
14802
14803         if (!state->base.fb)
14804                 return 0;
14805
14806         if (INTEL_GEN(dev_priv) >= 9) {
14807                 ret = skl_check_plane_surface(state);
14808                 if (ret)
14809                         return ret;
14810         }
14811
14812         return 0;
14813 }
14814
14815 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14816                                     struct drm_crtc_state *old_crtc_state)
14817 {
14818         struct drm_device *dev = crtc->dev;
14819         struct drm_i915_private *dev_priv = to_i915(dev);
14820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14821         struct intel_crtc_state *old_intel_state =
14822                 to_intel_crtc_state(old_crtc_state);
14823         bool modeset = needs_modeset(crtc->state);
14824         enum pipe pipe = intel_crtc->pipe;
14825
14826         /* Perform vblank evasion around commit operation */
14827         intel_pipe_update_start(intel_crtc);
14828
14829         if (modeset)
14830                 return;
14831
14832         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14833                 intel_color_set_csc(crtc->state);
14834                 intel_color_load_luts(crtc->state);
14835         }
14836
14837         if (to_intel_crtc_state(crtc->state)->update_pipe)
14838                 intel_update_pipe_config(intel_crtc, old_intel_state);
14839         else if (INTEL_GEN(dev_priv) >= 9) {
14840                 skl_detach_scalers(intel_crtc);
14841
14842                 I915_WRITE(PIPE_WM_LINETIME(pipe),
14843                            dev_priv->wm.skl_hw.wm_linetime[pipe]);
14844         }
14845 }
14846
14847 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14848                                      struct drm_crtc_state *old_crtc_state)
14849 {
14850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14851
14852         intel_pipe_update_end(intel_crtc, NULL);
14853 }
14854
14855 /**
14856  * intel_plane_destroy - destroy a plane
14857  * @plane: plane to destroy
14858  *
14859  * Common destruction function for all types of planes (primary, cursor,
14860  * sprite).
14861  */
14862 void intel_plane_destroy(struct drm_plane *plane)
14863 {
14864         if (!plane)
14865                 return;
14866
14867         drm_plane_cleanup(plane);
14868         kfree(to_intel_plane(plane));
14869 }
14870
14871 const struct drm_plane_funcs intel_plane_funcs = {
14872         .update_plane = drm_atomic_helper_update_plane,
14873         .disable_plane = drm_atomic_helper_disable_plane,
14874         .destroy = intel_plane_destroy,
14875         .set_property = drm_atomic_helper_plane_set_property,
14876         .atomic_get_property = intel_plane_atomic_get_property,
14877         .atomic_set_property = intel_plane_atomic_set_property,
14878         .atomic_duplicate_state = intel_plane_duplicate_state,
14879         .atomic_destroy_state = intel_plane_destroy_state,
14880
14881 };
14882
14883 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14884                                                     int pipe)
14885 {
14886         struct intel_plane *primary = NULL;
14887         struct intel_plane_state *state = NULL;
14888         const uint32_t *intel_primary_formats;
14889         unsigned int num_formats;
14890         int ret;
14891
14892         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14893         if (!primary)
14894                 goto fail;
14895
14896         state = intel_create_plane_state(&primary->base);
14897         if (!state)
14898                 goto fail;
14899         primary->base.state = &state->base;
14900
14901         primary->can_scale = false;
14902         primary->max_downscale = 1;
14903         if (INTEL_INFO(dev)->gen >= 9) {
14904                 primary->can_scale = true;
14905                 state->scaler_id = -1;
14906         }
14907         primary->pipe = pipe;
14908         primary->plane = pipe;
14909         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14910         primary->check_plane = intel_check_primary_plane;
14911         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14912                 primary->plane = !pipe;
14913
14914         if (INTEL_INFO(dev)->gen >= 9) {
14915                 intel_primary_formats = skl_primary_formats;
14916                 num_formats = ARRAY_SIZE(skl_primary_formats);
14917
14918                 primary->update_plane = skylake_update_primary_plane;
14919                 primary->disable_plane = skylake_disable_primary_plane;
14920         } else if (HAS_PCH_SPLIT(dev)) {
14921                 intel_primary_formats = i965_primary_formats;
14922                 num_formats = ARRAY_SIZE(i965_primary_formats);
14923
14924                 primary->update_plane = ironlake_update_primary_plane;
14925                 primary->disable_plane = i9xx_disable_primary_plane;
14926         } else if (INTEL_INFO(dev)->gen >= 4) {
14927                 intel_primary_formats = i965_primary_formats;
14928                 num_formats = ARRAY_SIZE(i965_primary_formats);
14929
14930                 primary->update_plane = i9xx_update_primary_plane;
14931                 primary->disable_plane = i9xx_disable_primary_plane;
14932         } else {
14933                 intel_primary_formats = i8xx_primary_formats;
14934                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14935
14936                 primary->update_plane = i9xx_update_primary_plane;
14937                 primary->disable_plane = i9xx_disable_primary_plane;
14938         }
14939
14940         if (INTEL_INFO(dev)->gen >= 9)
14941                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14942                                                &intel_plane_funcs,
14943                                                intel_primary_formats, num_formats,
14944                                                DRM_PLANE_TYPE_PRIMARY,
14945                                                "plane 1%c", pipe_name(pipe));
14946         else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14947                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14948                                                &intel_plane_funcs,
14949                                                intel_primary_formats, num_formats,
14950                                                DRM_PLANE_TYPE_PRIMARY,
14951                                                "primary %c", pipe_name(pipe));
14952         else
14953                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14954                                                &intel_plane_funcs,
14955                                                intel_primary_formats, num_formats,
14956                                                DRM_PLANE_TYPE_PRIMARY,
14957                                                "plane %c", plane_name(primary->plane));
14958         if (ret)
14959                 goto fail;
14960
14961         if (INTEL_INFO(dev)->gen >= 4)
14962                 intel_create_rotation_property(dev, primary);
14963
14964         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14965
14966         return &primary->base;
14967
14968 fail:
14969         kfree(state);
14970         kfree(primary);
14971
14972         return NULL;
14973 }
14974
14975 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14976 {
14977         if (!dev->mode_config.rotation_property) {
14978                 unsigned long flags = DRM_ROTATE_0 |
14979                         DRM_ROTATE_180;
14980
14981                 if (INTEL_INFO(dev)->gen >= 9)
14982                         flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
14983
14984                 dev->mode_config.rotation_property =
14985                         drm_mode_create_rotation_property(dev, flags);
14986         }
14987         if (dev->mode_config.rotation_property)
14988                 drm_object_attach_property(&plane->base.base,
14989                                 dev->mode_config.rotation_property,
14990                                 plane->base.state->rotation);
14991 }
14992
14993 static int
14994 intel_check_cursor_plane(struct drm_plane *plane,
14995                          struct intel_crtc_state *crtc_state,
14996                          struct intel_plane_state *state)
14997 {
14998         struct drm_framebuffer *fb = state->base.fb;
14999         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15000         enum pipe pipe = to_intel_plane(plane)->pipe;
15001         unsigned stride;
15002         int ret;
15003
15004         ret = drm_plane_helper_check_state(&state->base,
15005                                            &state->clip,
15006                                            DRM_PLANE_HELPER_NO_SCALING,
15007                                            DRM_PLANE_HELPER_NO_SCALING,
15008                                            true, true);
15009         if (ret)
15010                 return ret;
15011
15012         /* if we want to turn off the cursor ignore width and height */
15013         if (!obj)
15014                 return 0;
15015
15016         /* Check for which cursor types we support */
15017         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
15018                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15019                           state->base.crtc_w, state->base.crtc_h);
15020                 return -EINVAL;
15021         }
15022
15023         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15024         if (obj->base.size < stride * state->base.crtc_h) {
15025                 DRM_DEBUG_KMS("buffer is too small\n");
15026                 return -ENOMEM;
15027         }
15028
15029         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
15030                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15031                 return -EINVAL;
15032         }
15033
15034         /*
15035          * There's something wrong with the cursor on CHV pipe C.
15036          * If it straddles the left edge of the screen then
15037          * moving it away from the edge or disabling it often
15038          * results in a pipe underrun, and often that can lead to
15039          * dead pipe (constant underrun reported, and it scans
15040          * out just a solid color). To recover from that, the
15041          * display power well must be turned off and on again.
15042          * Refuse the put the cursor into that compromised position.
15043          */
15044         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
15045             state->base.visible && state->base.crtc_x < 0) {
15046                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15047                 return -EINVAL;
15048         }
15049
15050         return 0;
15051 }
15052
15053 static void
15054 intel_disable_cursor_plane(struct drm_plane *plane,
15055                            struct drm_crtc *crtc)
15056 {
15057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15058
15059         intel_crtc->cursor_addr = 0;
15060         intel_crtc_update_cursor(crtc, NULL);
15061 }
15062
15063 static void
15064 intel_update_cursor_plane(struct drm_plane *plane,
15065                           const struct intel_crtc_state *crtc_state,
15066                           const struct intel_plane_state *state)
15067 {
15068         struct drm_crtc *crtc = crtc_state->base.crtc;
15069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15070         struct drm_device *dev = plane->dev;
15071         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15072         uint32_t addr;
15073
15074         if (!obj)
15075                 addr = 0;
15076         else if (!INTEL_INFO(dev)->cursor_needs_physical)
15077                 addr = i915_gem_object_ggtt_offset(obj, NULL);
15078         else
15079                 addr = obj->phys_handle->busaddr;
15080
15081         intel_crtc->cursor_addr = addr;
15082         intel_crtc_update_cursor(crtc, state);
15083 }
15084
15085 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
15086                                                    int pipe)
15087 {
15088         struct intel_plane *cursor = NULL;
15089         struct intel_plane_state *state = NULL;
15090         int ret;
15091
15092         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15093         if (!cursor)
15094                 goto fail;
15095
15096         state = intel_create_plane_state(&cursor->base);
15097         if (!state)
15098                 goto fail;
15099         cursor->base.state = &state->base;
15100
15101         cursor->can_scale = false;
15102         cursor->max_downscale = 1;
15103         cursor->pipe = pipe;
15104         cursor->plane = pipe;
15105         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15106         cursor->check_plane = intel_check_cursor_plane;
15107         cursor->update_plane = intel_update_cursor_plane;
15108         cursor->disable_plane = intel_disable_cursor_plane;
15109
15110         ret = drm_universal_plane_init(dev, &cursor->base, 0,
15111                                        &intel_plane_funcs,
15112                                        intel_cursor_formats,
15113                                        ARRAY_SIZE(intel_cursor_formats),
15114                                        DRM_PLANE_TYPE_CURSOR,
15115                                        "cursor %c", pipe_name(pipe));
15116         if (ret)
15117                 goto fail;
15118
15119         if (INTEL_INFO(dev)->gen >= 4) {
15120                 if (!dev->mode_config.rotation_property)
15121                         dev->mode_config.rotation_property =
15122                                 drm_mode_create_rotation_property(dev,
15123                                                         DRM_ROTATE_0 |
15124                                                         DRM_ROTATE_180);
15125                 if (dev->mode_config.rotation_property)
15126                         drm_object_attach_property(&cursor->base.base,
15127                                 dev->mode_config.rotation_property,
15128                                 state->base.rotation);
15129         }
15130
15131         if (INTEL_INFO(dev)->gen >=9)
15132                 state->scaler_id = -1;
15133
15134         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15135
15136         return &cursor->base;
15137
15138 fail:
15139         kfree(state);
15140         kfree(cursor);
15141
15142         return NULL;
15143 }
15144
15145 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
15146         struct intel_crtc_state *crtc_state)
15147 {
15148         int i;
15149         struct intel_scaler *intel_scaler;
15150         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
15151
15152         for (i = 0; i < intel_crtc->num_scalers; i++) {
15153                 intel_scaler = &scaler_state->scalers[i];
15154                 intel_scaler->in_use = 0;
15155                 intel_scaler->mode = PS_SCALER_MODE_DYN;
15156         }
15157
15158         scaler_state->scaler_id = -1;
15159 }
15160
15161 static void intel_crtc_init(struct drm_device *dev, int pipe)
15162 {
15163         struct drm_i915_private *dev_priv = to_i915(dev);
15164         struct intel_crtc *intel_crtc;
15165         struct intel_crtc_state *crtc_state = NULL;
15166         struct drm_plane *primary = NULL;
15167         struct drm_plane *cursor = NULL;
15168         int ret;
15169
15170         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15171         if (intel_crtc == NULL)
15172                 return;
15173
15174         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15175         if (!crtc_state)
15176                 goto fail;
15177         intel_crtc->config = crtc_state;
15178         intel_crtc->base.state = &crtc_state->base;
15179         crtc_state->base.crtc = &intel_crtc->base;
15180
15181         /* initialize shared scalers */
15182         if (INTEL_INFO(dev)->gen >= 9) {
15183                 if (pipe == PIPE_C)
15184                         intel_crtc->num_scalers = 1;
15185                 else
15186                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
15187
15188                 skl_init_scalers(dev, intel_crtc, crtc_state);
15189         }
15190
15191         primary = intel_primary_plane_create(dev, pipe);
15192         if (!primary)
15193                 goto fail;
15194
15195         cursor = intel_cursor_plane_create(dev, pipe);
15196         if (!cursor)
15197                 goto fail;
15198
15199         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
15200                                         cursor, &intel_crtc_funcs,
15201                                         "pipe %c", pipe_name(pipe));
15202         if (ret)
15203                 goto fail;
15204
15205         /*
15206          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
15207          * is hooked to pipe B. Hence we want plane A feeding pipe B.
15208          */
15209         intel_crtc->pipe = pipe;
15210         intel_crtc->plane = pipe;
15211         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
15212                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
15213                 intel_crtc->plane = !pipe;
15214         }
15215
15216         intel_crtc->cursor_base = ~0;
15217         intel_crtc->cursor_cntl = ~0;
15218         intel_crtc->cursor_size = ~0;
15219
15220         intel_crtc->wm.cxsr_allowed = true;
15221
15222         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15223                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15224         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15225         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15226
15227         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15228
15229         intel_color_init(&intel_crtc->base);
15230
15231         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15232         return;
15233
15234 fail:
15235         intel_plane_destroy(primary);
15236         intel_plane_destroy(cursor);
15237         kfree(crtc_state);
15238         kfree(intel_crtc);
15239 }
15240
15241 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15242 {
15243         struct drm_encoder *encoder = connector->base.encoder;
15244         struct drm_device *dev = connector->base.dev;
15245
15246         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15247
15248         if (!encoder || WARN_ON(!encoder->crtc))
15249                 return INVALID_PIPE;
15250
15251         return to_intel_crtc(encoder->crtc)->pipe;
15252 }
15253
15254 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15255                                 struct drm_file *file)
15256 {
15257         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15258         struct drm_crtc *drmmode_crtc;
15259         struct intel_crtc *crtc;
15260
15261         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15262         if (!drmmode_crtc)
15263                 return -ENOENT;
15264
15265         crtc = to_intel_crtc(drmmode_crtc);
15266         pipe_from_crtc_id->pipe = crtc->pipe;
15267
15268         return 0;
15269 }
15270
15271 static int intel_encoder_clones(struct intel_encoder *encoder)
15272 {
15273         struct drm_device *dev = encoder->base.dev;
15274         struct intel_encoder *source_encoder;
15275         int index_mask = 0;
15276         int entry = 0;
15277
15278         for_each_intel_encoder(dev, source_encoder) {
15279                 if (encoders_cloneable(encoder, source_encoder))
15280                         index_mask |= (1 << entry);
15281
15282                 entry++;
15283         }
15284
15285         return index_mask;
15286 }
15287
15288 static bool has_edp_a(struct drm_device *dev)
15289 {
15290         struct drm_i915_private *dev_priv = to_i915(dev);
15291
15292         if (!IS_MOBILE(dev))
15293                 return false;
15294
15295         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15296                 return false;
15297
15298         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15299                 return false;
15300
15301         return true;
15302 }
15303
15304 static bool intel_crt_present(struct drm_device *dev)
15305 {
15306         struct drm_i915_private *dev_priv = to_i915(dev);
15307
15308         if (INTEL_INFO(dev)->gen >= 9)
15309                 return false;
15310
15311         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
15312                 return false;
15313
15314         if (IS_CHERRYVIEW(dev))
15315                 return false;
15316
15317         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15318                 return false;
15319
15320         /* DDI E can't be used if DDI A requires 4 lanes */
15321         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15322                 return false;
15323
15324         if (!dev_priv->vbt.int_crt_support)
15325                 return false;
15326
15327         return true;
15328 }
15329
15330 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15331 {
15332         int pps_num;
15333         int pps_idx;
15334
15335         if (HAS_DDI(dev_priv))
15336                 return;
15337         /*
15338          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15339          * everywhere where registers can be write protected.
15340          */
15341         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15342                 pps_num = 2;
15343         else
15344                 pps_num = 1;
15345
15346         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15347                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15348
15349                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15350                 I915_WRITE(PP_CONTROL(pps_idx), val);
15351         }
15352 }
15353
15354 static void intel_pps_init(struct drm_i915_private *dev_priv)
15355 {
15356         if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15357                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15358         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15359                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15360         else
15361                 dev_priv->pps_mmio_base = PPS_BASE;
15362
15363         intel_pps_unlock_regs_wa(dev_priv);
15364 }
15365
15366 static void intel_setup_outputs(struct drm_device *dev)
15367 {
15368         struct drm_i915_private *dev_priv = to_i915(dev);
15369         struct intel_encoder *encoder;
15370         bool dpd_is_edp = false;
15371
15372         intel_pps_init(dev_priv);
15373
15374         /*
15375          * intel_edp_init_connector() depends on this completing first, to
15376          * prevent the registeration of both eDP and LVDS and the incorrect
15377          * sharing of the PPS.
15378          */
15379         intel_lvds_init(dev);
15380
15381         if (intel_crt_present(dev))
15382                 intel_crt_init(dev);
15383
15384         if (IS_BROXTON(dev)) {
15385                 /*
15386                  * FIXME: Broxton doesn't support port detection via the
15387                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15388                  * detect the ports.
15389                  */
15390                 intel_ddi_init(dev, PORT_A);
15391                 intel_ddi_init(dev, PORT_B);
15392                 intel_ddi_init(dev, PORT_C);
15393
15394                 intel_dsi_init(dev);
15395         } else if (HAS_DDI(dev)) {
15396                 int found;
15397
15398                 /*
15399                  * Haswell uses DDI functions to detect digital outputs.
15400                  * On SKL pre-D0 the strap isn't connected, so we assume
15401                  * it's there.
15402                  */
15403                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15404                 /* WaIgnoreDDIAStrap: skl */
15405                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15406                         intel_ddi_init(dev, PORT_A);
15407
15408                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15409                  * register */
15410                 found = I915_READ(SFUSE_STRAP);
15411
15412                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15413                         intel_ddi_init(dev, PORT_B);
15414                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15415                         intel_ddi_init(dev, PORT_C);
15416                 if (found & SFUSE_STRAP_DDID_DETECTED)
15417                         intel_ddi_init(dev, PORT_D);
15418                 /*
15419                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15420                  */
15421                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
15422                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15423                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15424                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15425                         intel_ddi_init(dev, PORT_E);
15426
15427         } else if (HAS_PCH_SPLIT(dev)) {
15428                 int found;
15429                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15430
15431                 if (has_edp_a(dev))
15432                         intel_dp_init(dev, DP_A, PORT_A);
15433
15434                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15435                         /* PCH SDVOB multiplex with HDMIB */
15436                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15437                         if (!found)
15438                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15439                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15440                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
15441                 }
15442
15443                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15444                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15445
15446                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15447                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15448
15449                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15450                         intel_dp_init(dev, PCH_DP_C, PORT_C);
15451
15452                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15453                         intel_dp_init(dev, PCH_DP_D, PORT_D);
15454         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15455                 bool has_edp, has_port;
15456
15457                 /*
15458                  * The DP_DETECTED bit is the latched state of the DDC
15459                  * SDA pin at boot. However since eDP doesn't require DDC
15460                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15461                  * eDP ports may have been muxed to an alternate function.
15462                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15463                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15464                  * detect eDP ports.
15465                  *
15466                  * Sadly the straps seem to be missing sometimes even for HDMI
15467                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15468                  * and VBT for the presence of the port. Additionally we can't
15469                  * trust the port type the VBT declares as we've seen at least
15470                  * HDMI ports that the VBT claim are DP or eDP.
15471                  */
15472                 has_edp = intel_dp_is_edp(dev, PORT_B);
15473                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15474                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15475                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15476                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15477                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15478
15479                 has_edp = intel_dp_is_edp(dev, PORT_C);
15480                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15481                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15482                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15483                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15484                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15485
15486                 if (IS_CHERRYVIEW(dev)) {
15487                         /*
15488                          * eDP not supported on port D,
15489                          * so no need to worry about it
15490                          */
15491                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15492                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15493                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
15494                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15495                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15496                 }
15497
15498                 intel_dsi_init(dev);
15499         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15500                 bool found = false;
15501
15502                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15503                         DRM_DEBUG_KMS("probing SDVOB\n");
15504                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15505                         if (!found && IS_G4X(dev)) {
15506                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15507                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15508                         }
15509
15510                         if (!found && IS_G4X(dev))
15511                                 intel_dp_init(dev, DP_B, PORT_B);
15512                 }
15513
15514                 /* Before G4X SDVOC doesn't have its own detect register */
15515
15516                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15517                         DRM_DEBUG_KMS("probing SDVOC\n");
15518                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15519                 }
15520
15521                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15522
15523                         if (IS_G4X(dev)) {
15524                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15525                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15526                         }
15527                         if (IS_G4X(dev))
15528                                 intel_dp_init(dev, DP_C, PORT_C);
15529                 }
15530
15531                 if (IS_G4X(dev) &&
15532                     (I915_READ(DP_D) & DP_DETECTED))
15533                         intel_dp_init(dev, DP_D, PORT_D);
15534         } else if (IS_GEN2(dev))
15535                 intel_dvo_init(dev);
15536
15537         if (SUPPORTS_TV(dev))
15538                 intel_tv_init(dev);
15539
15540         intel_psr_init(dev);
15541
15542         for_each_intel_encoder(dev, encoder) {
15543                 encoder->base.possible_crtcs = encoder->crtc_mask;
15544                 encoder->base.possible_clones =
15545                         intel_encoder_clones(encoder);
15546         }
15547
15548         intel_init_pch_refclk(dev);
15549
15550         drm_helper_move_panel_connectors_to_head(dev);
15551 }
15552
15553 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15554 {
15555         struct drm_device *dev = fb->dev;
15556         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15557
15558         drm_framebuffer_cleanup(fb);
15559         mutex_lock(&dev->struct_mutex);
15560         WARN_ON(!intel_fb->obj->framebuffer_references--);
15561         i915_gem_object_put(intel_fb->obj);
15562         mutex_unlock(&dev->struct_mutex);
15563         kfree(intel_fb);
15564 }
15565
15566 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15567                                                 struct drm_file *file,
15568                                                 unsigned int *handle)
15569 {
15570         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15571         struct drm_i915_gem_object *obj = intel_fb->obj;
15572
15573         if (obj->userptr.mm) {
15574                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15575                 return -EINVAL;
15576         }
15577
15578         return drm_gem_handle_create(file, &obj->base, handle);
15579 }
15580
15581 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15582                                         struct drm_file *file,
15583                                         unsigned flags, unsigned color,
15584                                         struct drm_clip_rect *clips,
15585                                         unsigned num_clips)
15586 {
15587         struct drm_device *dev = fb->dev;
15588         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15589         struct drm_i915_gem_object *obj = intel_fb->obj;
15590
15591         mutex_lock(&dev->struct_mutex);
15592         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15593         mutex_unlock(&dev->struct_mutex);
15594
15595         return 0;
15596 }
15597
15598 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15599         .destroy = intel_user_framebuffer_destroy,
15600         .create_handle = intel_user_framebuffer_create_handle,
15601         .dirty = intel_user_framebuffer_dirty,
15602 };
15603
15604 static
15605 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15606                          uint32_t pixel_format)
15607 {
15608         u32 gen = INTEL_INFO(dev)->gen;
15609
15610         if (gen >= 9) {
15611                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15612
15613                 /* "The stride in bytes must not exceed the of the size of 8K
15614                  *  pixels and 32K bytes."
15615                  */
15616                 return min(8192 * cpp, 32768);
15617         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15618                 return 32*1024;
15619         } else if (gen >= 4) {
15620                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15621                         return 16*1024;
15622                 else
15623                         return 32*1024;
15624         } else if (gen >= 3) {
15625                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15626                         return 8*1024;
15627                 else
15628                         return 16*1024;
15629         } else {
15630                 /* XXX DSPC is limited to 4k tiled */
15631                 return 8*1024;
15632         }
15633 }
15634
15635 static int intel_framebuffer_init(struct drm_device *dev,
15636                                   struct intel_framebuffer *intel_fb,
15637                                   struct drm_mode_fb_cmd2 *mode_cmd,
15638                                   struct drm_i915_gem_object *obj)
15639 {
15640         struct drm_i915_private *dev_priv = to_i915(dev);
15641         unsigned int tiling = i915_gem_object_get_tiling(obj);
15642         int ret;
15643         u32 pitch_limit, stride_alignment;
15644         char *format_name;
15645
15646         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15647
15648         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15649                 /*
15650                  * If there's a fence, enforce that
15651                  * the fb modifier and tiling mode match.
15652                  */
15653                 if (tiling != I915_TILING_NONE &&
15654                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15655                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15656                         return -EINVAL;
15657                 }
15658         } else {
15659                 if (tiling == I915_TILING_X) {
15660                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15661                 } else if (tiling == I915_TILING_Y) {
15662                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15663                         return -EINVAL;
15664                 }
15665         }
15666
15667         /* Passed in modifier sanity checking. */
15668         switch (mode_cmd->modifier[0]) {
15669         case I915_FORMAT_MOD_Y_TILED:
15670         case I915_FORMAT_MOD_Yf_TILED:
15671                 if (INTEL_INFO(dev)->gen < 9) {
15672                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15673                                   mode_cmd->modifier[0]);
15674                         return -EINVAL;
15675                 }
15676         case DRM_FORMAT_MOD_NONE:
15677         case I915_FORMAT_MOD_X_TILED:
15678                 break;
15679         default:
15680                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15681                           mode_cmd->modifier[0]);
15682                 return -EINVAL;
15683         }
15684
15685         /*
15686          * gen2/3 display engine uses the fence if present,
15687          * so the tiling mode must match the fb modifier exactly.
15688          */
15689         if (INTEL_INFO(dev_priv)->gen < 4 &&
15690             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15691                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15692                 return -EINVAL;
15693         }
15694
15695         stride_alignment = intel_fb_stride_alignment(dev_priv,
15696                                                      mode_cmd->modifier[0],
15697                                                      mode_cmd->pixel_format);
15698         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15699                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15700                           mode_cmd->pitches[0], stride_alignment);
15701                 return -EINVAL;
15702         }
15703
15704         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15705                                            mode_cmd->pixel_format);
15706         if (mode_cmd->pitches[0] > pitch_limit) {
15707                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15708                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15709                           "tiled" : "linear",
15710                           mode_cmd->pitches[0], pitch_limit);
15711                 return -EINVAL;
15712         }
15713
15714         /*
15715          * If there's a fence, enforce that
15716          * the fb pitch and fence stride match.
15717          */
15718         if (tiling != I915_TILING_NONE &&
15719             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15720                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15721                           mode_cmd->pitches[0],
15722                           i915_gem_object_get_stride(obj));
15723                 return -EINVAL;
15724         }
15725
15726         /* Reject formats not supported by any plane early. */
15727         switch (mode_cmd->pixel_format) {
15728         case DRM_FORMAT_C8:
15729         case DRM_FORMAT_RGB565:
15730         case DRM_FORMAT_XRGB8888:
15731         case DRM_FORMAT_ARGB8888:
15732                 break;
15733         case DRM_FORMAT_XRGB1555:
15734                 if (INTEL_INFO(dev)->gen > 3) {
15735                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15736                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15737                         kfree(format_name);
15738                         return -EINVAL;
15739                 }
15740                 break;
15741         case DRM_FORMAT_ABGR8888:
15742                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15743                     INTEL_INFO(dev)->gen < 9) {
15744                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15745                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15746                         kfree(format_name);
15747                         return -EINVAL;
15748                 }
15749                 break;
15750         case DRM_FORMAT_XBGR8888:
15751         case DRM_FORMAT_XRGB2101010:
15752         case DRM_FORMAT_XBGR2101010:
15753                 if (INTEL_INFO(dev)->gen < 4) {
15754                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15755                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15756                         kfree(format_name);
15757                         return -EINVAL;
15758                 }
15759                 break;
15760         case DRM_FORMAT_ABGR2101010:
15761                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15762                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15763                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15764                         kfree(format_name);
15765                         return -EINVAL;
15766                 }
15767                 break;
15768         case DRM_FORMAT_YUYV:
15769         case DRM_FORMAT_UYVY:
15770         case DRM_FORMAT_YVYU:
15771         case DRM_FORMAT_VYUY:
15772                 if (INTEL_INFO(dev)->gen < 5) {
15773                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15774                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15775                         kfree(format_name);
15776                         return -EINVAL;
15777                 }
15778                 break;
15779         default:
15780                 format_name = drm_get_format_name(mode_cmd->pixel_format);
15781                 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15782                 kfree(format_name);
15783                 return -EINVAL;
15784         }
15785
15786         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15787         if (mode_cmd->offsets[0] != 0)
15788                 return -EINVAL;
15789
15790         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15791         intel_fb->obj = obj;
15792
15793         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15794         if (ret)
15795                 return ret;
15796
15797         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15798         if (ret) {
15799                 DRM_ERROR("framebuffer init failed %d\n", ret);
15800                 return ret;
15801         }
15802
15803         intel_fb->obj->framebuffer_references++;
15804
15805         return 0;
15806 }
15807
15808 static struct drm_framebuffer *
15809 intel_user_framebuffer_create(struct drm_device *dev,
15810                               struct drm_file *filp,
15811                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15812 {
15813         struct drm_framebuffer *fb;
15814         struct drm_i915_gem_object *obj;
15815         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15816
15817         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15818         if (!obj)
15819                 return ERR_PTR(-ENOENT);
15820
15821         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15822         if (IS_ERR(fb))
15823                 i915_gem_object_put_unlocked(obj);
15824
15825         return fb;
15826 }
15827
15828 #ifndef CONFIG_DRM_FBDEV_EMULATION
15829 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15830 {
15831 }
15832 #endif
15833
15834 static const struct drm_mode_config_funcs intel_mode_funcs = {
15835         .fb_create = intel_user_framebuffer_create,
15836         .output_poll_changed = intel_fbdev_output_poll_changed,
15837         .atomic_check = intel_atomic_check,
15838         .atomic_commit = intel_atomic_commit,
15839         .atomic_state_alloc = intel_atomic_state_alloc,
15840         .atomic_state_clear = intel_atomic_state_clear,
15841 };
15842
15843 /**
15844  * intel_init_display_hooks - initialize the display modesetting hooks
15845  * @dev_priv: device private
15846  */
15847 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15848 {
15849         if (INTEL_INFO(dev_priv)->gen >= 9) {
15850                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15851                 dev_priv->display.get_initial_plane_config =
15852                         skylake_get_initial_plane_config;
15853                 dev_priv->display.crtc_compute_clock =
15854                         haswell_crtc_compute_clock;
15855                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15856                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15857         } else if (HAS_DDI(dev_priv)) {
15858                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15859                 dev_priv->display.get_initial_plane_config =
15860                         ironlake_get_initial_plane_config;
15861                 dev_priv->display.crtc_compute_clock =
15862                         haswell_crtc_compute_clock;
15863                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15864                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15865         } else if (HAS_PCH_SPLIT(dev_priv)) {
15866                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15867                 dev_priv->display.get_initial_plane_config =
15868                         ironlake_get_initial_plane_config;
15869                 dev_priv->display.crtc_compute_clock =
15870                         ironlake_crtc_compute_clock;
15871                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15872                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15873         } else if (IS_CHERRYVIEW(dev_priv)) {
15874                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15875                 dev_priv->display.get_initial_plane_config =
15876                         i9xx_get_initial_plane_config;
15877                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15878                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15879                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15880         } else if (IS_VALLEYVIEW(dev_priv)) {
15881                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15882                 dev_priv->display.get_initial_plane_config =
15883                         i9xx_get_initial_plane_config;
15884                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15885                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15886                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15887         } else if (IS_G4X(dev_priv)) {
15888                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15889                 dev_priv->display.get_initial_plane_config =
15890                         i9xx_get_initial_plane_config;
15891                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15892                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15893                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15894         } else if (IS_PINEVIEW(dev_priv)) {
15895                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15896                 dev_priv->display.get_initial_plane_config =
15897                         i9xx_get_initial_plane_config;
15898                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15899                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15900                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15901         } else if (!IS_GEN2(dev_priv)) {
15902                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15903                 dev_priv->display.get_initial_plane_config =
15904                         i9xx_get_initial_plane_config;
15905                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15906                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15907                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15908         } else {
15909                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15910                 dev_priv->display.get_initial_plane_config =
15911                         i9xx_get_initial_plane_config;
15912                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15913                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15914                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15915         }
15916
15917         /* Returns the core display clock speed */
15918         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15919                 dev_priv->display.get_display_clock_speed =
15920                         skylake_get_display_clock_speed;
15921         else if (IS_BROXTON(dev_priv))
15922                 dev_priv->display.get_display_clock_speed =
15923                         broxton_get_display_clock_speed;
15924         else if (IS_BROADWELL(dev_priv))
15925                 dev_priv->display.get_display_clock_speed =
15926                         broadwell_get_display_clock_speed;
15927         else if (IS_HASWELL(dev_priv))
15928                 dev_priv->display.get_display_clock_speed =
15929                         haswell_get_display_clock_speed;
15930         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15931                 dev_priv->display.get_display_clock_speed =
15932                         valleyview_get_display_clock_speed;
15933         else if (IS_GEN5(dev_priv))
15934                 dev_priv->display.get_display_clock_speed =
15935                         ilk_get_display_clock_speed;
15936         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15937                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15938                 dev_priv->display.get_display_clock_speed =
15939                         i945_get_display_clock_speed;
15940         else if (IS_GM45(dev_priv))
15941                 dev_priv->display.get_display_clock_speed =
15942                         gm45_get_display_clock_speed;
15943         else if (IS_CRESTLINE(dev_priv))
15944                 dev_priv->display.get_display_clock_speed =
15945                         i965gm_get_display_clock_speed;
15946         else if (IS_PINEVIEW(dev_priv))
15947                 dev_priv->display.get_display_clock_speed =
15948                         pnv_get_display_clock_speed;
15949         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15950                 dev_priv->display.get_display_clock_speed =
15951                         g33_get_display_clock_speed;
15952         else if (IS_I915G(dev_priv))
15953                 dev_priv->display.get_display_clock_speed =
15954                         i915_get_display_clock_speed;
15955         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15956                 dev_priv->display.get_display_clock_speed =
15957                         i9xx_misc_get_display_clock_speed;
15958         else if (IS_I915GM(dev_priv))
15959                 dev_priv->display.get_display_clock_speed =
15960                         i915gm_get_display_clock_speed;
15961         else if (IS_I865G(dev_priv))
15962                 dev_priv->display.get_display_clock_speed =
15963                         i865_get_display_clock_speed;
15964         else if (IS_I85X(dev_priv))
15965                 dev_priv->display.get_display_clock_speed =
15966                         i85x_get_display_clock_speed;
15967         else { /* 830 */
15968                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15969                 dev_priv->display.get_display_clock_speed =
15970                         i830_get_display_clock_speed;
15971         }
15972
15973         if (IS_GEN5(dev_priv)) {
15974                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15975         } else if (IS_GEN6(dev_priv)) {
15976                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15977         } else if (IS_IVYBRIDGE(dev_priv)) {
15978                 /* FIXME: detect B0+ stepping and use auto training */
15979                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15980         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15981                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15982         }
15983
15984         if (IS_BROADWELL(dev_priv)) {
15985                 dev_priv->display.modeset_commit_cdclk =
15986                         broadwell_modeset_commit_cdclk;
15987                 dev_priv->display.modeset_calc_cdclk =
15988                         broadwell_modeset_calc_cdclk;
15989         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15990                 dev_priv->display.modeset_commit_cdclk =
15991                         valleyview_modeset_commit_cdclk;
15992                 dev_priv->display.modeset_calc_cdclk =
15993                         valleyview_modeset_calc_cdclk;
15994         } else if (IS_BROXTON(dev_priv)) {
15995                 dev_priv->display.modeset_commit_cdclk =
15996                         bxt_modeset_commit_cdclk;
15997                 dev_priv->display.modeset_calc_cdclk =
15998                         bxt_modeset_calc_cdclk;
15999         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16000                 dev_priv->display.modeset_commit_cdclk =
16001                         skl_modeset_commit_cdclk;
16002                 dev_priv->display.modeset_calc_cdclk =
16003                         skl_modeset_calc_cdclk;
16004         }
16005
16006         if (dev_priv->info.gen >= 9)
16007                 dev_priv->display.update_crtcs = skl_update_crtcs;
16008         else
16009                 dev_priv->display.update_crtcs = intel_update_crtcs;
16010
16011         switch (INTEL_INFO(dev_priv)->gen) {
16012         case 2:
16013                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16014                 break;
16015
16016         case 3:
16017                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16018                 break;
16019
16020         case 4:
16021         case 5:
16022                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16023                 break;
16024
16025         case 6:
16026                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16027                 break;
16028         case 7:
16029         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16030                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16031                 break;
16032         case 9:
16033                 /* Drop through - unsupported since execlist only. */
16034         default:
16035                 /* Default just returns -ENODEV to indicate unsupported */
16036                 dev_priv->display.queue_flip = intel_default_queue_flip;
16037         }
16038 }
16039
16040 /*
16041  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16042  * resume, or other times.  This quirk makes sure that's the case for
16043  * affected systems.
16044  */
16045 static void quirk_pipea_force(struct drm_device *dev)
16046 {
16047         struct drm_i915_private *dev_priv = to_i915(dev);
16048
16049         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16050         DRM_INFO("applying pipe a force quirk\n");
16051 }
16052
16053 static void quirk_pipeb_force(struct drm_device *dev)
16054 {
16055         struct drm_i915_private *dev_priv = to_i915(dev);
16056
16057         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16058         DRM_INFO("applying pipe b force quirk\n");
16059 }
16060
16061 /*
16062  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16063  */
16064 static void quirk_ssc_force_disable(struct drm_device *dev)
16065 {
16066         struct drm_i915_private *dev_priv = to_i915(dev);
16067         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16068         DRM_INFO("applying lvds SSC disable quirk\n");
16069 }
16070
16071 /*
16072  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16073  * brightness value
16074  */
16075 static void quirk_invert_brightness(struct drm_device *dev)
16076 {
16077         struct drm_i915_private *dev_priv = to_i915(dev);
16078         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16079         DRM_INFO("applying inverted panel brightness quirk\n");
16080 }
16081
16082 /* Some VBT's incorrectly indicate no backlight is present */
16083 static void quirk_backlight_present(struct drm_device *dev)
16084 {
16085         struct drm_i915_private *dev_priv = to_i915(dev);
16086         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16087         DRM_INFO("applying backlight present quirk\n");
16088 }
16089
16090 struct intel_quirk {
16091         int device;
16092         int subsystem_vendor;
16093         int subsystem_device;
16094         void (*hook)(struct drm_device *dev);
16095 };
16096
16097 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16098 struct intel_dmi_quirk {
16099         void (*hook)(struct drm_device *dev);
16100         const struct dmi_system_id (*dmi_id_list)[];
16101 };
16102
16103 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16104 {
16105         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16106         return 1;
16107 }
16108
16109 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16110         {
16111                 .dmi_id_list = &(const struct dmi_system_id[]) {
16112                         {
16113                                 .callback = intel_dmi_reverse_brightness,
16114                                 .ident = "NCR Corporation",
16115                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16116                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
16117                                 },
16118                         },
16119                         { }  /* terminating entry */
16120                 },
16121                 .hook = quirk_invert_brightness,
16122         },
16123 };
16124
16125 static struct intel_quirk intel_quirks[] = {
16126         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16127         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16128
16129         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16130         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16131
16132         /* 830 needs to leave pipe A & dpll A up */
16133         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16134
16135         /* 830 needs to leave pipe B & dpll B up */
16136         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16137
16138         /* Lenovo U160 cannot use SSC on LVDS */
16139         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16140
16141         /* Sony Vaio Y cannot use SSC on LVDS */
16142         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16143
16144         /* Acer Aspire 5734Z must invert backlight brightness */
16145         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16146
16147         /* Acer/eMachines G725 */
16148         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16149
16150         /* Acer/eMachines e725 */
16151         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16152
16153         /* Acer/Packard Bell NCL20 */
16154         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16155
16156         /* Acer Aspire 4736Z */
16157         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16158
16159         /* Acer Aspire 5336 */
16160         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16161
16162         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16163         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16164
16165         /* Acer C720 Chromebook (Core i3 4005U) */
16166         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16167
16168         /* Apple Macbook 2,1 (Core 2 T7400) */
16169         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16170
16171         /* Apple Macbook 4,1 */
16172         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16173
16174         /* Toshiba CB35 Chromebook (Celeron 2955U) */
16175         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16176
16177         /* HP Chromebook 14 (Celeron 2955U) */
16178         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16179
16180         /* Dell Chromebook 11 */
16181         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16182
16183         /* Dell Chromebook 11 (2015 version) */
16184         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16185 };
16186
16187 static void intel_init_quirks(struct drm_device *dev)
16188 {
16189         struct pci_dev *d = dev->pdev;
16190         int i;
16191
16192         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16193                 struct intel_quirk *q = &intel_quirks[i];
16194
16195                 if (d->device == q->device &&
16196                     (d->subsystem_vendor == q->subsystem_vendor ||
16197                      q->subsystem_vendor == PCI_ANY_ID) &&
16198                     (d->subsystem_device == q->subsystem_device ||
16199                      q->subsystem_device == PCI_ANY_ID))
16200                         q->hook(dev);
16201         }
16202         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16203                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16204                         intel_dmi_quirks[i].hook(dev);
16205         }
16206 }
16207
16208 /* Disable the VGA plane that we never use */
16209 static void i915_disable_vga(struct drm_device *dev)
16210 {
16211         struct drm_i915_private *dev_priv = to_i915(dev);
16212         struct pci_dev *pdev = dev_priv->drm.pdev;
16213         u8 sr1;
16214         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16215
16216         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16217         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16218         outb(SR01, VGA_SR_INDEX);
16219         sr1 = inb(VGA_SR_DATA);
16220         outb(sr1 | 1<<5, VGA_SR_DATA);
16221         vga_put(pdev, VGA_RSRC_LEGACY_IO);
16222         udelay(300);
16223
16224         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16225         POSTING_READ(vga_reg);
16226 }
16227
16228 void intel_modeset_init_hw(struct drm_device *dev)
16229 {
16230         struct drm_i915_private *dev_priv = to_i915(dev);
16231
16232         intel_update_cdclk(dev);
16233
16234         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16235
16236         intel_init_clock_gating(dev);
16237 }
16238
16239 /*
16240  * Calculate what we think the watermarks should be for the state we've read
16241  * out of the hardware and then immediately program those watermarks so that
16242  * we ensure the hardware settings match our internal state.
16243  *
16244  * We can calculate what we think WM's should be by creating a duplicate of the
16245  * current state (which was constructed during hardware readout) and running it
16246  * through the atomic check code to calculate new watermark values in the
16247  * state object.
16248  */
16249 static void sanitize_watermarks(struct drm_device *dev)
16250 {
16251         struct drm_i915_private *dev_priv = to_i915(dev);
16252         struct drm_atomic_state *state;
16253         struct drm_crtc *crtc;
16254         struct drm_crtc_state *cstate;
16255         struct drm_modeset_acquire_ctx ctx;
16256         int ret;
16257         int i;
16258
16259         /* Only supported on platforms that use atomic watermark design */
16260         if (!dev_priv->display.optimize_watermarks)
16261                 return;
16262
16263         /*
16264          * We need to hold connection_mutex before calling duplicate_state so
16265          * that the connector loop is protected.
16266          */
16267         drm_modeset_acquire_init(&ctx, 0);
16268 retry:
16269         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16270         if (ret == -EDEADLK) {
16271                 drm_modeset_backoff(&ctx);
16272                 goto retry;
16273         } else if (WARN_ON(ret)) {
16274                 goto fail;
16275         }
16276
16277         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16278         if (WARN_ON(IS_ERR(state)))
16279                 goto fail;
16280
16281         /*
16282          * Hardware readout is the only time we don't want to calculate
16283          * intermediate watermarks (since we don't trust the current
16284          * watermarks).
16285          */
16286         to_intel_atomic_state(state)->skip_intermediate_wm = true;
16287
16288         ret = intel_atomic_check(dev, state);
16289         if (ret) {
16290                 /*
16291                  * If we fail here, it means that the hardware appears to be
16292                  * programmed in a way that shouldn't be possible, given our
16293                  * understanding of watermark requirements.  This might mean a
16294                  * mistake in the hardware readout code or a mistake in the
16295                  * watermark calculations for a given platform.  Raise a WARN
16296                  * so that this is noticeable.
16297                  *
16298                  * If this actually happens, we'll have to just leave the
16299                  * BIOS-programmed watermarks untouched and hope for the best.
16300                  */
16301                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16302                 goto put_state;
16303         }
16304
16305         /* Write calculated watermark values back */
16306         for_each_crtc_in_state(state, crtc, cstate, i) {
16307                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16308
16309                 cs->wm.need_postvbl_update = true;
16310                 dev_priv->display.optimize_watermarks(cs);
16311         }
16312
16313 put_state:
16314         drm_atomic_state_put(state);
16315 fail:
16316         drm_modeset_drop_locks(&ctx);
16317         drm_modeset_acquire_fini(&ctx);
16318 }
16319
16320 void intel_modeset_init(struct drm_device *dev)
16321 {
16322         struct drm_i915_private *dev_priv = to_i915(dev);
16323         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16324         int sprite, ret;
16325         enum pipe pipe;
16326         struct intel_crtc *crtc;
16327
16328         drm_mode_config_init(dev);
16329
16330         dev->mode_config.min_width = 0;
16331         dev->mode_config.min_height = 0;
16332
16333         dev->mode_config.preferred_depth = 24;
16334         dev->mode_config.prefer_shadow = 1;
16335
16336         dev->mode_config.allow_fb_modifiers = true;
16337
16338         dev->mode_config.funcs = &intel_mode_funcs;
16339
16340         intel_init_quirks(dev);
16341
16342         intel_init_pm(dev);
16343
16344         if (INTEL_INFO(dev)->num_pipes == 0)
16345                 return;
16346
16347         /*
16348          * There may be no VBT; and if the BIOS enabled SSC we can
16349          * just keep using it to avoid unnecessary flicker.  Whereas if the
16350          * BIOS isn't using it, don't assume it will work even if the VBT
16351          * indicates as much.
16352          */
16353         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
16354                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16355                                             DREF_SSC1_ENABLE);
16356
16357                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16358                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16359                                      bios_lvds_use_ssc ? "en" : "dis",
16360                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16361                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16362                 }
16363         }
16364
16365         if (IS_GEN2(dev)) {
16366                 dev->mode_config.max_width = 2048;
16367                 dev->mode_config.max_height = 2048;
16368         } else if (IS_GEN3(dev)) {
16369                 dev->mode_config.max_width = 4096;
16370                 dev->mode_config.max_height = 4096;
16371         } else {
16372                 dev->mode_config.max_width = 8192;
16373                 dev->mode_config.max_height = 8192;
16374         }
16375
16376         if (IS_845G(dev) || IS_I865G(dev)) {
16377                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
16378                 dev->mode_config.cursor_height = 1023;
16379         } else if (IS_GEN2(dev)) {
16380                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16381                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16382         } else {
16383                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16384                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16385         }
16386
16387         dev->mode_config.fb_base = ggtt->mappable_base;
16388
16389         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16390                       INTEL_INFO(dev)->num_pipes,
16391                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16392
16393         for_each_pipe(dev_priv, pipe) {
16394                 intel_crtc_init(dev, pipe);
16395                 for_each_sprite(dev_priv, pipe, sprite) {
16396                         ret = intel_plane_init(dev, pipe, sprite);
16397                         if (ret)
16398                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16399                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
16400                 }
16401         }
16402
16403         intel_update_czclk(dev_priv);
16404         intel_update_cdclk(dev);
16405
16406         intel_shared_dpll_init(dev);
16407
16408         if (dev_priv->max_cdclk_freq == 0)
16409                 intel_update_max_cdclk(dev);
16410
16411         /* Just disable it once at startup */
16412         i915_disable_vga(dev);
16413         intel_setup_outputs(dev);
16414
16415         drm_modeset_lock_all(dev);
16416         intel_modeset_setup_hw_state(dev);
16417         drm_modeset_unlock_all(dev);
16418
16419         for_each_intel_crtc(dev, crtc) {
16420                 struct intel_initial_plane_config plane_config = {};
16421
16422                 if (!crtc->active)
16423                         continue;
16424
16425                 /*
16426                  * Note that reserving the BIOS fb up front prevents us
16427                  * from stuffing other stolen allocations like the ring
16428                  * on top.  This prevents some ugliness at boot time, and
16429                  * can even allow for smooth boot transitions if the BIOS
16430                  * fb is large enough for the active pipe configuration.
16431                  */
16432                 dev_priv->display.get_initial_plane_config(crtc,
16433                                                            &plane_config);
16434
16435                 /*
16436                  * If the fb is shared between multiple heads, we'll
16437                  * just get the first one.
16438                  */
16439                 intel_find_initial_plane_obj(crtc, &plane_config);
16440         }
16441
16442         /*
16443          * Make sure hardware watermarks really match the state we read out.
16444          * Note that we need to do this after reconstructing the BIOS fb's
16445          * since the watermark calculation done here will use pstate->fb.
16446          */
16447         sanitize_watermarks(dev);
16448 }
16449
16450 static void intel_enable_pipe_a(struct drm_device *dev)
16451 {
16452         struct intel_connector *connector;
16453         struct drm_connector *crt = NULL;
16454         struct intel_load_detect_pipe load_detect_temp;
16455         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16456
16457         /* We can't just switch on the pipe A, we need to set things up with a
16458          * proper mode and output configuration. As a gross hack, enable pipe A
16459          * by enabling the load detect pipe once. */
16460         for_each_intel_connector(dev, connector) {
16461                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16462                         crt = &connector->base;
16463                         break;
16464                 }
16465         }
16466
16467         if (!crt)
16468                 return;
16469
16470         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16471                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16472 }
16473
16474 static bool
16475 intel_check_plane_mapping(struct intel_crtc *crtc)
16476 {
16477         struct drm_device *dev = crtc->base.dev;
16478         struct drm_i915_private *dev_priv = to_i915(dev);
16479         u32 val;
16480
16481         if (INTEL_INFO(dev)->num_pipes == 1)
16482                 return true;
16483
16484         val = I915_READ(DSPCNTR(!crtc->plane));
16485
16486         if ((val & DISPLAY_PLANE_ENABLE) &&
16487             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16488                 return false;
16489
16490         return true;
16491 }
16492
16493 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16494 {
16495         struct drm_device *dev = crtc->base.dev;
16496         struct intel_encoder *encoder;
16497
16498         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16499                 return true;
16500
16501         return false;
16502 }
16503
16504 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16505 {
16506         struct drm_device *dev = encoder->base.dev;
16507         struct intel_connector *connector;
16508
16509         for_each_connector_on_encoder(dev, &encoder->base, connector)
16510                 return connector;
16511
16512         return NULL;
16513 }
16514
16515 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16516                               enum transcoder pch_transcoder)
16517 {
16518         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16519                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16520 }
16521
16522 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16523 {
16524         struct drm_device *dev = crtc->base.dev;
16525         struct drm_i915_private *dev_priv = to_i915(dev);
16526         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16527
16528         /* Clear any frame start delays used for debugging left by the BIOS */
16529         if (!transcoder_is_dsi(cpu_transcoder)) {
16530                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16531
16532                 I915_WRITE(reg,
16533                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16534         }
16535
16536         /* restore vblank interrupts to correct state */
16537         drm_crtc_vblank_reset(&crtc->base);
16538         if (crtc->active) {
16539                 struct intel_plane *plane;
16540
16541                 drm_crtc_vblank_on(&crtc->base);
16542
16543                 /* Disable everything but the primary plane */
16544                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16545                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16546                                 continue;
16547
16548                         plane->disable_plane(&plane->base, &crtc->base);
16549                 }
16550         }
16551
16552         /* We need to sanitize the plane -> pipe mapping first because this will
16553          * disable the crtc (and hence change the state) if it is wrong. Note
16554          * that gen4+ has a fixed plane -> pipe mapping.  */
16555         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16556                 bool plane;
16557
16558                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16559                               crtc->base.base.id, crtc->base.name);
16560
16561                 /* Pipe has the wrong plane attached and the plane is active.
16562                  * Temporarily change the plane mapping and disable everything
16563                  * ...  */
16564                 plane = crtc->plane;
16565                 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16566                 crtc->plane = !plane;
16567                 intel_crtc_disable_noatomic(&crtc->base);
16568                 crtc->plane = plane;
16569         }
16570
16571         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16572             crtc->pipe == PIPE_A && !crtc->active) {
16573                 /* BIOS forgot to enable pipe A, this mostly happens after
16574                  * resume. Force-enable the pipe to fix this, the update_dpms
16575                  * call below we restore the pipe to the right state, but leave
16576                  * the required bits on. */
16577                 intel_enable_pipe_a(dev);
16578         }
16579
16580         /* Adjust the state of the output pipe according to whether we
16581          * have active connectors/encoders. */
16582         if (crtc->active && !intel_crtc_has_encoders(crtc))
16583                 intel_crtc_disable_noatomic(&crtc->base);
16584
16585         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
16586                 /*
16587                  * We start out with underrun reporting disabled to avoid races.
16588                  * For correct bookkeeping mark this on active crtcs.
16589                  *
16590                  * Also on gmch platforms we dont have any hardware bits to
16591                  * disable the underrun reporting. Which means we need to start
16592                  * out with underrun reporting disabled also on inactive pipes,
16593                  * since otherwise we'll complain about the garbage we read when
16594                  * e.g. coming up after runtime pm.
16595                  *
16596                  * No protection against concurrent access is required - at
16597                  * worst a fifo underrun happens which also sets this to false.
16598                  */
16599                 crtc->cpu_fifo_underrun_disabled = true;
16600                 /*
16601                  * We track the PCH trancoder underrun reporting state
16602                  * within the crtc. With crtc for pipe A housing the underrun
16603                  * reporting state for PCH transcoder A, crtc for pipe B housing
16604                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16605                  * and marking underrun reporting as disabled for the non-existing
16606                  * PCH transcoders B and C would prevent enabling the south
16607                  * error interrupt (see cpt_can_enable_serr_int()).
16608                  */
16609                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16610                         crtc->pch_fifo_underrun_disabled = true;
16611         }
16612 }
16613
16614 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16615 {
16616         struct intel_connector *connector;
16617
16618         /* We need to check both for a crtc link (meaning that the
16619          * encoder is active and trying to read from a pipe) and the
16620          * pipe itself being active. */
16621         bool has_active_crtc = encoder->base.crtc &&
16622                 to_intel_crtc(encoder->base.crtc)->active;
16623
16624         connector = intel_encoder_find_connector(encoder);
16625         if (connector && !has_active_crtc) {
16626                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16627                               encoder->base.base.id,
16628                               encoder->base.name);
16629
16630                 /* Connector is active, but has no active pipe. This is
16631                  * fallout from our resume register restoring. Disable
16632                  * the encoder manually again. */
16633                 if (encoder->base.crtc) {
16634                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16635
16636                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16637                                       encoder->base.base.id,
16638                                       encoder->base.name);
16639                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16640                         if (encoder->post_disable)
16641                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16642                 }
16643                 encoder->base.crtc = NULL;
16644
16645                 /* Inconsistent output/port/pipe state happens presumably due to
16646                  * a bug in one of the get_hw_state functions. Or someplace else
16647                  * in our code, like the register restore mess on resume. Clamp
16648                  * things to off as a safer default. */
16649
16650                 connector->base.dpms = DRM_MODE_DPMS_OFF;
16651                 connector->base.encoder = NULL;
16652         }
16653         /* Enabled encoders without active connectors will be fixed in
16654          * the crtc fixup. */
16655 }
16656
16657 void i915_redisable_vga_power_on(struct drm_device *dev)
16658 {
16659         struct drm_i915_private *dev_priv = to_i915(dev);
16660         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16661
16662         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16663                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16664                 i915_disable_vga(dev);
16665         }
16666 }
16667
16668 void i915_redisable_vga(struct drm_device *dev)
16669 {
16670         struct drm_i915_private *dev_priv = to_i915(dev);
16671
16672         /* This function can be called both from intel_modeset_setup_hw_state or
16673          * at a very early point in our resume sequence, where the power well
16674          * structures are not yet restored. Since this function is at a very
16675          * paranoid "someone might have enabled VGA while we were not looking"
16676          * level, just check if the power well is enabled instead of trying to
16677          * follow the "don't touch the power well if we don't need it" policy
16678          * the rest of the driver uses. */
16679         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16680                 return;
16681
16682         i915_redisable_vga_power_on(dev);
16683
16684         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16685 }
16686
16687 static bool primary_get_hw_state(struct intel_plane *plane)
16688 {
16689         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16690
16691         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16692 }
16693
16694 /* FIXME read out full plane state for all planes */
16695 static void readout_plane_state(struct intel_crtc *crtc)
16696 {
16697         struct drm_plane *primary = crtc->base.primary;
16698         struct intel_plane_state *plane_state =
16699                 to_intel_plane_state(primary->state);
16700
16701         plane_state->base.visible = crtc->active &&
16702                 primary_get_hw_state(to_intel_plane(primary));
16703
16704         if (plane_state->base.visible)
16705                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16706 }
16707
16708 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16709 {
16710         struct drm_i915_private *dev_priv = to_i915(dev);
16711         enum pipe pipe;
16712         struct intel_crtc *crtc;
16713         struct intel_encoder *encoder;
16714         struct intel_connector *connector;
16715         int i;
16716
16717         dev_priv->active_crtcs = 0;
16718
16719         for_each_intel_crtc(dev, crtc) {
16720                 struct intel_crtc_state *crtc_state = crtc->config;
16721                 int pixclk = 0;
16722
16723                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16724                 memset(crtc_state, 0, sizeof(*crtc_state));
16725                 crtc_state->base.crtc = &crtc->base;
16726
16727                 crtc_state->base.active = crtc_state->base.enable =
16728                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16729
16730                 crtc->base.enabled = crtc_state->base.enable;
16731                 crtc->active = crtc_state->base.active;
16732
16733                 if (crtc_state->base.active) {
16734                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16735
16736                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16737                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
16738                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16739                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16740                         else
16741                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16742
16743                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16744                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16745                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16746                 }
16747
16748                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16749
16750                 readout_plane_state(crtc);
16751
16752                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16753                               crtc->base.base.id, crtc->base.name,
16754                               crtc->active ? "enabled" : "disabled");
16755         }
16756
16757         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16758                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16759
16760                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16761                                                   &pll->config.hw_state);
16762                 pll->config.crtc_mask = 0;
16763                 for_each_intel_crtc(dev, crtc) {
16764                         if (crtc->active && crtc->config->shared_dpll == pll)
16765                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16766                 }
16767                 pll->active_mask = pll->config.crtc_mask;
16768
16769                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16770                               pll->name, pll->config.crtc_mask, pll->on);
16771         }
16772
16773         for_each_intel_encoder(dev, encoder) {
16774                 pipe = 0;
16775
16776                 if (encoder->get_hw_state(encoder, &pipe)) {
16777                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16778                         encoder->base.crtc = &crtc->base;
16779                         crtc->config->output_types |= 1 << encoder->type;
16780                         encoder->get_config(encoder, crtc->config);
16781                 } else {
16782                         encoder->base.crtc = NULL;
16783                 }
16784
16785                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16786                               encoder->base.base.id,
16787                               encoder->base.name,
16788                               encoder->base.crtc ? "enabled" : "disabled",
16789                               pipe_name(pipe));
16790         }
16791
16792         for_each_intel_connector(dev, connector) {
16793                 if (connector->get_hw_state(connector)) {
16794                         connector->base.dpms = DRM_MODE_DPMS_ON;
16795
16796                         encoder = connector->encoder;
16797                         connector->base.encoder = &encoder->base;
16798
16799                         if (encoder->base.crtc &&
16800                             encoder->base.crtc->state->active) {
16801                                 /*
16802                                  * This has to be done during hardware readout
16803                                  * because anything calling .crtc_disable may
16804                                  * rely on the connector_mask being accurate.
16805                                  */
16806                                 encoder->base.crtc->state->connector_mask |=
16807                                         1 << drm_connector_index(&connector->base);
16808                                 encoder->base.crtc->state->encoder_mask |=
16809                                         1 << drm_encoder_index(&encoder->base);
16810                         }
16811
16812                 } else {
16813                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16814                         connector->base.encoder = NULL;
16815                 }
16816                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16817                               connector->base.base.id,
16818                               connector->base.name,
16819                               connector->base.encoder ? "enabled" : "disabled");
16820         }
16821
16822         for_each_intel_crtc(dev, crtc) {
16823                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16824
16825                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16826                 if (crtc->base.state->active) {
16827                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16828                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16829                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16830
16831                         /*
16832                          * The initial mode needs to be set in order to keep
16833                          * the atomic core happy. It wants a valid mode if the
16834                          * crtc's enabled, so we do the above call.
16835                          *
16836                          * At this point some state updated by the connectors
16837                          * in their ->detect() callback has not run yet, so
16838                          * no recalculation can be done yet.
16839                          *
16840                          * Even if we could do a recalculation and modeset
16841                          * right now it would cause a double modeset if
16842                          * fbdev or userspace chooses a different initial mode.
16843                          *
16844                          * If that happens, someone indicated they wanted a
16845                          * mode change, which means it's safe to do a full
16846                          * recalculation.
16847                          */
16848                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16849
16850                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16851                         update_scanline_offset(crtc);
16852                 }
16853
16854                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16855         }
16856 }
16857
16858 /* Scan out the current hw modeset state,
16859  * and sanitizes it to the current state
16860  */
16861 static void
16862 intel_modeset_setup_hw_state(struct drm_device *dev)
16863 {
16864         struct drm_i915_private *dev_priv = to_i915(dev);
16865         enum pipe pipe;
16866         struct intel_crtc *crtc;
16867         struct intel_encoder *encoder;
16868         int i;
16869
16870         intel_modeset_readout_hw_state(dev);
16871
16872         /* HW state is read out, now we need to sanitize this mess. */
16873         for_each_intel_encoder(dev, encoder) {
16874                 intel_sanitize_encoder(encoder);
16875         }
16876
16877         for_each_pipe(dev_priv, pipe) {
16878                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16879                 intel_sanitize_crtc(crtc);
16880                 intel_dump_pipe_config(crtc, crtc->config,
16881                                        "[setup_hw_state]");
16882         }
16883
16884         intel_modeset_update_connector_atomic_state(dev);
16885
16886         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16887                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16888
16889                 if (!pll->on || pll->active_mask)
16890                         continue;
16891
16892                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16893
16894                 pll->funcs.disable(dev_priv, pll);
16895                 pll->on = false;
16896         }
16897
16898         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16899                 vlv_wm_get_hw_state(dev);
16900         else if (IS_GEN9(dev))
16901                 skl_wm_get_hw_state(dev);
16902         else if (HAS_PCH_SPLIT(dev))
16903                 ilk_wm_get_hw_state(dev);
16904
16905         for_each_intel_crtc(dev, crtc) {
16906                 unsigned long put_domains;
16907
16908                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16909                 if (WARN_ON(put_domains))
16910                         modeset_put_power_domains(dev_priv, put_domains);
16911         }
16912         intel_display_set_init_power(dev_priv, false);
16913
16914         intel_fbc_init_pipe_state(dev_priv);
16915 }
16916
16917 void intel_display_resume(struct drm_device *dev)
16918 {
16919         struct drm_i915_private *dev_priv = to_i915(dev);
16920         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16921         struct drm_modeset_acquire_ctx ctx;
16922         int ret;
16923
16924         dev_priv->modeset_restore_state = NULL;
16925         if (state)
16926                 state->acquire_ctx = &ctx;
16927
16928         /*
16929          * This is a cludge because with real atomic modeset mode_config.mutex
16930          * won't be taken. Unfortunately some probed state like
16931          * audio_codec_enable is still protected by mode_config.mutex, so lock
16932          * it here for now.
16933          */
16934         mutex_lock(&dev->mode_config.mutex);
16935         drm_modeset_acquire_init(&ctx, 0);
16936
16937         while (1) {
16938                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16939                 if (ret != -EDEADLK)
16940                         break;
16941
16942                 drm_modeset_backoff(&ctx);
16943         }
16944
16945         if (!ret)
16946                 ret = __intel_display_resume(dev, state);
16947
16948         drm_modeset_drop_locks(&ctx);
16949         drm_modeset_acquire_fini(&ctx);
16950         mutex_unlock(&dev->mode_config.mutex);
16951
16952         if (ret)
16953                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16954         drm_atomic_state_put(state);
16955 }
16956
16957 void intel_modeset_gem_init(struct drm_device *dev)
16958 {
16959         struct drm_i915_private *dev_priv = to_i915(dev);
16960         struct drm_crtc *c;
16961         struct drm_i915_gem_object *obj;
16962
16963         intel_init_gt_powersave(dev_priv);
16964
16965         intel_modeset_init_hw(dev);
16966
16967         intel_setup_overlay(dev_priv);
16968
16969         /*
16970          * Make sure any fbs we allocated at startup are properly
16971          * pinned & fenced.  When we do the allocation it's too early
16972          * for this.
16973          */
16974         for_each_crtc(dev, c) {
16975                 struct i915_vma *vma;
16976
16977                 obj = intel_fb_obj(c->primary->fb);
16978                 if (obj == NULL)
16979                         continue;
16980
16981                 mutex_lock(&dev->struct_mutex);
16982                 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
16983                                                  c->primary->state->rotation);
16984                 mutex_unlock(&dev->struct_mutex);
16985                 if (IS_ERR(vma)) {
16986                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16987                                   to_intel_crtc(c)->pipe);
16988                         drm_framebuffer_unreference(c->primary->fb);
16989                         c->primary->fb = NULL;
16990                         c->primary->crtc = c->primary->state->crtc = NULL;
16991                         update_state_fb(c->primary);
16992                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16993                 }
16994         }
16995 }
16996
16997 int intel_connector_register(struct drm_connector *connector)
16998 {
16999         struct intel_connector *intel_connector = to_intel_connector(connector);
17000         int ret;
17001
17002         ret = intel_backlight_device_register(intel_connector);
17003         if (ret)
17004                 goto err;
17005
17006         return 0;
17007
17008 err:
17009         return ret;
17010 }
17011
17012 void intel_connector_unregister(struct drm_connector *connector)
17013 {
17014         struct intel_connector *intel_connector = to_intel_connector(connector);
17015
17016         intel_backlight_device_unregister(intel_connector);
17017         intel_panel_destroy_backlight(connector);
17018 }
17019
17020 void intel_modeset_cleanup(struct drm_device *dev)
17021 {
17022         struct drm_i915_private *dev_priv = to_i915(dev);
17023
17024         intel_disable_gt_powersave(dev_priv);
17025
17026         /*
17027          * Interrupts and polling as the first thing to avoid creating havoc.
17028          * Too much stuff here (turning of connectors, ...) would
17029          * experience fancy races otherwise.
17030          */
17031         intel_irq_uninstall(dev_priv);
17032
17033         /*
17034          * Due to the hpd irq storm handling the hotplug work can re-arm the
17035          * poll handlers. Hence disable polling after hpd handling is shut down.
17036          */
17037         drm_kms_helper_poll_fini(dev);
17038
17039         intel_unregister_dsm_handler();
17040
17041         intel_fbc_global_disable(dev_priv);
17042
17043         /* flush any delayed tasks or pending work */
17044         flush_scheduled_work();
17045
17046         drm_mode_config_cleanup(dev);
17047
17048         intel_cleanup_overlay(dev_priv);
17049
17050         intel_cleanup_gt_powersave(dev_priv);
17051
17052         intel_teardown_gmbus(dev);
17053 }
17054
17055 void intel_connector_attach_encoder(struct intel_connector *connector,
17056                                     struct intel_encoder *encoder)
17057 {
17058         connector->encoder = encoder;
17059         drm_mode_connector_attach_encoder(&connector->base,
17060                                           &encoder->base);
17061 }
17062
17063 /*
17064  * set vga decode state - true == enable VGA decode
17065  */
17066 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
17067 {
17068         struct drm_i915_private *dev_priv = to_i915(dev);
17069         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17070         u16 gmch_ctrl;
17071
17072         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17073                 DRM_ERROR("failed to read control word\n");
17074                 return -EIO;
17075         }
17076
17077         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17078                 return 0;
17079
17080         if (state)
17081                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17082         else
17083                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17084
17085         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17086                 DRM_ERROR("failed to write control word\n");
17087                 return -EIO;
17088         }
17089
17090         return 0;
17091 }
17092
17093 struct intel_display_error_state {
17094
17095         u32 power_well_driver;
17096
17097         int num_transcoders;
17098
17099         struct intel_cursor_error_state {
17100                 u32 control;
17101                 u32 position;
17102                 u32 base;
17103                 u32 size;
17104         } cursor[I915_MAX_PIPES];
17105
17106         struct intel_pipe_error_state {
17107                 bool power_domain_on;
17108                 u32 source;
17109                 u32 stat;
17110         } pipe[I915_MAX_PIPES];
17111
17112         struct intel_plane_error_state {
17113                 u32 control;
17114                 u32 stride;
17115                 u32 size;
17116                 u32 pos;
17117                 u32 addr;
17118                 u32 surface;
17119                 u32 tile_offset;
17120         } plane[I915_MAX_PIPES];
17121
17122         struct intel_transcoder_error_state {
17123                 bool power_domain_on;
17124                 enum transcoder cpu_transcoder;
17125
17126                 u32 conf;
17127
17128                 u32 htotal;
17129                 u32 hblank;
17130                 u32 hsync;
17131                 u32 vtotal;
17132                 u32 vblank;
17133                 u32 vsync;
17134         } transcoder[4];
17135 };
17136
17137 struct intel_display_error_state *
17138 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17139 {
17140         struct intel_display_error_state *error;
17141         int transcoders[] = {
17142                 TRANSCODER_A,
17143                 TRANSCODER_B,
17144                 TRANSCODER_C,
17145                 TRANSCODER_EDP,
17146         };
17147         int i;
17148
17149         if (INTEL_INFO(dev_priv)->num_pipes == 0)
17150                 return NULL;
17151
17152         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17153         if (error == NULL)
17154                 return NULL;
17155
17156         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17157                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17158
17159         for_each_pipe(dev_priv, i) {
17160                 error->pipe[i].power_domain_on =
17161                         __intel_display_power_is_enabled(dev_priv,
17162                                                          POWER_DOMAIN_PIPE(i));
17163                 if (!error->pipe[i].power_domain_on)
17164                         continue;
17165
17166                 error->cursor[i].control = I915_READ(CURCNTR(i));
17167                 error->cursor[i].position = I915_READ(CURPOS(i));
17168                 error->cursor[i].base = I915_READ(CURBASE(i));
17169
17170                 error->plane[i].control = I915_READ(DSPCNTR(i));
17171                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17172                 if (INTEL_GEN(dev_priv) <= 3) {
17173                         error->plane[i].size = I915_READ(DSPSIZE(i));
17174                         error->plane[i].pos = I915_READ(DSPPOS(i));
17175                 }
17176                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17177                         error->plane[i].addr = I915_READ(DSPADDR(i));
17178                 if (INTEL_GEN(dev_priv) >= 4) {
17179                         error->plane[i].surface = I915_READ(DSPSURF(i));
17180                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17181                 }
17182
17183                 error->pipe[i].source = I915_READ(PIPESRC(i));
17184
17185                 if (HAS_GMCH_DISPLAY(dev_priv))
17186                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17187         }
17188
17189         /* Note: this does not include DSI transcoders. */
17190         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17191         if (HAS_DDI(dev_priv))
17192                 error->num_transcoders++; /* Account for eDP. */
17193
17194         for (i = 0; i < error->num_transcoders; i++) {
17195                 enum transcoder cpu_transcoder = transcoders[i];
17196
17197                 error->transcoder[i].power_domain_on =
17198                         __intel_display_power_is_enabled(dev_priv,
17199                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17200                 if (!error->transcoder[i].power_domain_on)
17201                         continue;
17202
17203                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17204
17205                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17206                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17207                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17208                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17209                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17210                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17211                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17212         }
17213
17214         return error;
17215 }
17216
17217 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17218
17219 void
17220 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17221                                 struct drm_device *dev,
17222                                 struct intel_display_error_state *error)
17223 {
17224         struct drm_i915_private *dev_priv = to_i915(dev);
17225         int i;
17226
17227         if (!error)
17228                 return;
17229
17230         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
17231         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
17232                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17233                            error->power_well_driver);
17234         for_each_pipe(dev_priv, i) {
17235                 err_printf(m, "Pipe [%d]:\n", i);
17236                 err_printf(m, "  Power: %s\n",
17237                            onoff(error->pipe[i].power_domain_on));
17238                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17239                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17240
17241                 err_printf(m, "Plane [%d]:\n", i);
17242                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17243                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17244                 if (INTEL_INFO(dev)->gen <= 3) {
17245                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17246                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17247                 }
17248                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
17249                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17250                 if (INTEL_INFO(dev)->gen >= 4) {
17251                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17252                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17253                 }
17254
17255                 err_printf(m, "Cursor [%d]:\n", i);
17256                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17257                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17258                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17259         }
17260
17261         for (i = 0; i < error->num_transcoders; i++) {
17262                 err_printf(m, "CPU transcoder: %s\n",
17263                            transcoder_name(error->transcoder[i].cpu_transcoder));
17264                 err_printf(m, "  Power: %s\n",
17265                            onoff(error->transcoder[i].power_domain_on));
17266                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17267                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17268                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17269                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17270                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17271                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17272                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17273         }
17274 }