drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_dmabuf.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct drm_device *dev,
 101                                   struct intel_framebuffer *ifb,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd,
 103                                   struct drm_i915_gem_object *obj);
 104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 108                                          struct intel_link_m_n *m_n,
 109                                          struct intel_link_m_n *m2_n2);
 110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 113 static void vlv_prepare_pll(struct intel_crtc *crtc,
 114                             const struct intel_crtc_state *pipe_config);
 115 static void chv_prepare_pll(struct intel_crtc *crtc,
 116                             const struct intel_crtc_state *pipe_config);
 117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 120         struct intel_crtc_state *crtc_state);
 121 static void skylake_pfit_enable(struct intel_crtc *crtc);
 122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 127 static int bxt_calc_cdclk(int max_pixclk);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                                   const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static int
 184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 185 {
 186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 187 }
 188
 189 static int
 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 191 {
 192         /* RAWCLK_FREQ_VLV register updated from power well code */
 193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 195 }
 196
 197 static int
 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 199 {
 200         uint32_t clkcfg;
 201
 202         /* hrawclock is 1/4 the FSB frequency */
 203         clkcfg = I915_READ(CLKCFG);
 204         switch (clkcfg & CLKCFG_FSB_MASK) {
 205         case CLKCFG_FSB_400:
 206                 return 100000;
 207         case CLKCFG_FSB_533:
 208                 return 133333;
 209         case CLKCFG_FSB_667:
 210                 return 166667;
 211         case CLKCFG_FSB_800:
 212                 return 200000;
 213         case CLKCFG_FSB_1067:
 214                 return 266667;
 215         case CLKCFG_FSB_1333:
 216                 return 333333;
 217         /* these two are just a guess; one of them might be right */
 218         case CLKCFG_FSB_1600:
 219         case CLKCFG_FSB_1600_ALT:
 220                 return 400000;
 221         default:
 222                 return 133333;
 223         }
 224 }
 225
 226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 227 {
 228         if (HAS_PCH_SPLIT(dev_priv))
 229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 234         else
 235                 return; /* no rawclk on other platforms, or no need to know it */
 236
 237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 238 }
 239
 240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 241 {
 242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 243                 return;
 244
 245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 246                                                       CCK_CZ_CLOCK_CONTROL);
 247
 248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 249 }
 250
 251 static inline u32 /* units of 100MHz */
 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 253                     const struct intel_crtc_state *pipe_config)
 254 {
 255         if (HAS_DDI(dev_priv))
 256                 return pipe_config->port_clock; /* SPLL */
 257         else if (IS_GEN5(dev_priv))
 258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 259         else
 260                 return 270000;
 261 }
 262
 263 static const struct intel_limit intel_limits_i8xx_dac = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 2 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_dvo = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 2, .max = 33 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 4, .p2_fast = 4 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i8xx_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 908000, .max = 1512000 },
 292         .n = { .min = 2, .max = 16 },
 293         .m = { .min = 96, .max = 140 },
 294         .m1 = { .min = 18, .max = 26 },
 295         .m2 = { .min = 6, .max = 16 },
 296         .p = { .min = 4, .max = 128 },
 297         .p1 = { .min = 1, .max = 6 },
 298         .p2 = { .dot_limit = 165000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_sdvo = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 200000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const struct intel_limit intel_limits_i9xx_lvds = {
 316         .dot = { .min = 20000, .max = 400000 },
 317         .vco = { .min = 1400000, .max = 2800000 },
 318         .n = { .min = 1, .max = 6 },
 319         .m = { .min = 70, .max = 120 },
 320         .m1 = { .min = 8, .max = 18 },
 321         .m2 = { .min = 3, .max = 7 },
 322         .p = { .min = 7, .max = 98 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 112000,
 325                 .p2_slow = 14, .p2_fast = 7 },
 326 };
 327
 328
 329 static const struct intel_limit intel_limits_g4x_sdvo = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 1750000, .max = 3500000},
 332         .n = { .min = 1, .max = 4 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 1, .max = 3},
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 10,
 340                 .p2_fast = 10
 341         },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_hdmi = {
 345         .dot = { .min = 22000, .max = 400000 },
 346         .vco = { .min = 1750000, .max = 3500000},
 347         .n = { .min = 1, .max = 4 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 16, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 5, .max = 80 },
 352         .p1 = { .min = 1, .max = 8},
 353         .p2 = { .dot_limit = 165000,
 354                 .p2_slow = 10, .p2_fast = 5 },
 355 };
 356
 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 358         .dot = { .min = 20000, .max = 115000 },
 359         .vco = { .min = 1750000, .max = 3500000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 104, .max = 138 },
 362         .m1 = { .min = 17, .max = 23 },
 363         .m2 = { .min = 5, .max = 11 },
 364         .p = { .min = 28, .max = 112 },
 365         .p1 = { .min = 2, .max = 8 },
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 14, .p2_fast = 14
 368         },
 369 };
 370
 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 372         .dot = { .min = 80000, .max = 224000 },
 373         .vco = { .min = 1750000, .max = 3500000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 104, .max = 138 },
 376         .m1 = { .min = 17, .max = 23 },
 377         .m2 = { .min = 5, .max = 11 },
 378         .p = { .min = 14, .max = 42 },
 379         .p1 = { .min = 2, .max = 6 },
 380         .p2 = { .dot_limit = 0,
 381                 .p2_slow = 7, .p2_fast = 7
 382         },
 383 };
 384
 385 static const struct intel_limit intel_limits_pineview_sdvo = {
 386         .dot = { .min = 20000, .max = 400000},
 387         .vco = { .min = 1700000, .max = 3500000 },
 388         /* Pineview's Ncounter is a ring counter */
 389         .n = { .min = 3, .max = 6 },
 390         .m = { .min = 2, .max = 256 },
 391         /* Pineview only has one combined m divider, which we treat as m2. */
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 5, .max = 80 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 200000,
 397                 .p2_slow = 10, .p2_fast = 5 },
 398 };
 399
 400 static const struct intel_limit intel_limits_pineview_lvds = {
 401         .dot = { .min = 20000, .max = 400000 },
 402         .vco = { .min = 1700000, .max = 3500000 },
 403         .n = { .min = 3, .max = 6 },
 404         .m = { .min = 2, .max = 256 },
 405         .m1 = { .min = 0, .max = 0 },
 406         .m2 = { .min = 0, .max = 254 },
 407         .p = { .min = 7, .max = 112 },
 408         .p1 = { .min = 1, .max = 8 },
 409         .p2 = { .dot_limit = 112000,
 410                 .p2_slow = 14, .p2_fast = 14 },
 411 };
 412
 413 /* Ironlake / Sandybridge
 414  *
 415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 416  * the range value for them is (actual_value - 2).
 417  */
 418 static const struct intel_limit intel_limits_ironlake_dac = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 5 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 5, .max = 80 },
 426         .p1 = { .min = 1, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 10, .p2_fast = 5 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 118 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 127 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 56 },
 452         .p1 = { .min = 2, .max = 8 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 /* LVDS 100mhz refclk limits. */
 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 2 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 28, .max = 112 },
 466         .p1 = { .min = 2, .max = 8 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 14, .p2_fast = 14 },
 469 };
 470
 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 472         .dot = { .min = 25000, .max = 350000 },
 473         .vco = { .min = 1760000, .max = 3510000 },
 474         .n = { .min = 1, .max = 3 },
 475         .m = { .min = 79, .max = 126 },
 476         .m1 = { .min = 12, .max = 22 },
 477         .m2 = { .min = 5, .max = 9 },
 478         .p = { .min = 14, .max = 42 },
 479         .p1 = { .min = 2, .max = 6 },
 480         .p2 = { .dot_limit = 225000,
 481                 .p2_slow = 7, .p2_fast = 7 },
 482 };
 483
 484 static const struct intel_limit intel_limits_vlv = {
 485          /*
 486           * These are the data rate limits (measured in fast clocks)
 487           * since those are the strictest limits we have. The fast
 488           * clock and actual rate limits are more relaxed, so checking
 489           * them would make no difference.
 490           */
 491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 492         .vco = { .min = 4000000, .max = 6000000 },
 493         .n = { .min = 1, .max = 7 },
 494         .m1 = { .min = 2, .max = 3 },
 495         .m2 = { .min = 11, .max = 156 },
 496         .p1 = { .min = 2, .max = 3 },
 497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 498 };
 499
 500 static const struct intel_limit intel_limits_chv = {
 501         /*
 502          * These are the data rate limits (measured in fast clocks)
 503          * since those are the strictest limits we have.  The fast
 504          * clock and actual rate limits are more relaxed, so checking
 505          * them would make no difference.
 506          */
 507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 508         .vco = { .min = 4800000, .max = 6480000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 514 };
 515
 516 static const struct intel_limit intel_limits_bxt = {
 517         /* FIXME: find real dot limits */
 518         .dot = { .min = 0, .max = INT_MAX },
 519         .vco = { .min = 4800000, .max = 6700000 },
 520         .n = { .min = 1, .max = 1 },
 521         .m1 = { .min = 2, .max = 2 },
 522         /* FIXME: find real m2 limits */
 523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 524         .p1 = { .min = 2, .max = 4 },
 525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 526 };
 527
 528 static bool
 529 needs_modeset(struct drm_crtc_state *state)
 530 {
 531         return drm_atomic_crtc_needs_modeset(state);
 532 }
 533
 534 /*
 535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 538  * The helpers' return value is the rate of the clock that is fed to the
 539  * display engine's pipe which can be the above fast dot clock rate or a
 540  * divided-down version of it.
 541  */
 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 544 {
 545         clock->m = clock->m2 + 2;
 546         clock->p = clock->p1 * clock->p2;
 547         if (WARN_ON(clock->n == 0 || clock->p == 0))
 548                 return 0;
 549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 551
 552         return clock->dot;
 553 }
 554
 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 556 {
 557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 558 }
 559
 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 561 {
 562         clock->m = i9xx_dpll_compute_m(clock);
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 565                 return 0;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568
 569         return clock->dot;
 570 }
 571
 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 573 {
 574         clock->m = clock->m1 * clock->m2;
 575         clock->p = clock->p1 * clock->p2;
 576         if (WARN_ON(clock->n == 0 || clock->p == 0))
 577                 return 0;
 578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 580
 581         return clock->dot / 5;
 582 }
 583
 584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 585 {
 586         clock->m = clock->m1 * clock->m2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 591                         clock->n << 22);
 592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 593
 594         return clock->dot / 5;
 595 }
 596
 597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 598 /**
 599  * Returns whether the given set of divisors are valid for a given refclk with
 600  * the given connectors.
 601  */
 602
 603 static bool intel_PLL_is_valid(struct drm_device *dev,
 604                                const struct intel_limit *limit,
 605                                const struct dpll *clock)
 606 {
 607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 608                 INTELPllInvalid("n out of range\n");
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 612                 INTELPllInvalid("m2 out of range\n");
 613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 614                 INTELPllInvalid("m1 out of range\n");
 615
 616         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 617             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 618                 if (clock->m1 <= clock->m2)
 619                         INTELPllInvalid("m1 <= m2\n");
 620
 621         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 622                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 623                         INTELPllInvalid("p out of range\n");
 624                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 625                         INTELPllInvalid("m out of range\n");
 626         }
 627
 628         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 629                 INTELPllInvalid("vco out of range\n");
 630         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 631          * connector, etc., rather than just a single range.
 632          */
 633         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 634                 INTELPllInvalid("dot out of range\n");
 635
 636         return true;
 637 }
 638
 639 static int
 640 i9xx_select_p2_div(const struct intel_limit *limit,
 641                    const struct intel_crtc_state *crtc_state,
 642                    int target)
 643 {
 644         struct drm_device *dev = crtc_state->base.crtc->dev;
 645
 646         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 647                 /*
 648                  * For LVDS just rely on its current settings for dual-channel.
 649                  * We haven't figured out how to reliably set up different
 650                  * single/dual channel state, if we even can.
 651                  */
 652                 if (intel_is_dual_link_lvds(dev))
 653                         return limit->p2.p2_fast;
 654                 else
 655                         return limit->p2.p2_slow;
 656         } else {
 657                 if (target < limit->p2.dot_limit)
 658                         return limit->p2.p2_slow;
 659                 else
 660                         return limit->p2.p2_fast;
 661         }
 662 }
 663
 664 /*
 665  * Returns a set of divisors for the desired target clock with the given
 666  * refclk, or FALSE.  The returned values represent the clock equation:
 667  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 668  *
 669  * Target and reference clocks are specified in kHz.
 670  *
 671  * If match_clock is provided, then best_clock P divider must match the P
 672  * divider from @match_clock used for LVDS downclocking.
 673  */
 674 static bool
 675 i9xx_find_best_dpll(const struct intel_limit *limit,
 676                     struct intel_crtc_state *crtc_state,
 677                     int target, int refclk, struct dpll *match_clock,
 678                     struct dpll *best_clock)
 679 {
 680         struct drm_device *dev = crtc_state->base.crtc->dev;
 681         struct dpll clock;
 682         int err = target;
 683
 684         memset(best_clock, 0, sizeof(*best_clock));
 685
 686         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 687
 688         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 689              clock.m1++) {
 690                 for (clock.m2 = limit->m2.min;
 691                      clock.m2 <= limit->m2.max; clock.m2++) {
 692                         if (clock.m2 >= clock.m1)
 693                                 break;
 694                         for (clock.n = limit->n.min;
 695                              clock.n <= limit->n.max; clock.n++) {
 696                                 for (clock.p1 = limit->p1.min;
 697                                         clock.p1 <= limit->p1.max; clock.p1++) {
 698                                         int this_err;
 699
 700                                         i9xx_calc_dpll_params(refclk, &clock);
 701                                         if (!intel_PLL_is_valid(dev, limit,
 702                                                                 &clock))
 703                                                 continue;
 704                                         if (match_clock &&
 705                                             clock.p != match_clock->p)
 706                                                 continue;
 707
 708                                         this_err = abs(clock.dot - target);
 709                                         if (this_err < err) {
 710                                                 *best_clock = clock;
 711                                                 err = this_err;
 712                                         }
 713                                 }
 714                         }
 715                 }
 716         }
 717
 718         return (err != target);
 719 }
 720
 721 /*
 722  * Returns a set of divisors for the desired target clock with the given
 723  * refclk, or FALSE.  The returned values represent the clock equation:
 724  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 725  *
 726  * Target and reference clocks are specified in kHz.
 727  *
 728  * If match_clock is provided, then best_clock P divider must match the P
 729  * divider from @match_clock used for LVDS downclocking.
 730  */
 731 static bool
 732 pnv_find_best_dpll(const struct intel_limit *limit,
 733                    struct intel_crtc_state *crtc_state,
 734                    int target, int refclk, struct dpll *match_clock,
 735                    struct dpll *best_clock)
 736 {
 737         struct drm_device *dev = crtc_state->base.crtc->dev;
 738         struct dpll clock;
 739         int err = target;
 740
 741         memset(best_clock, 0, sizeof(*best_clock));
 742
 743         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 744
 745         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 746              clock.m1++) {
 747                 for (clock.m2 = limit->m2.min;
 748                      clock.m2 <= limit->m2.max; clock.m2++) {
 749                         for (clock.n = limit->n.min;
 750                              clock.n <= limit->n.max; clock.n++) {
 751                                 for (clock.p1 = limit->p1.min;
 752                                         clock.p1 <= limit->p1.max; clock.p1++) {
 753                                         int this_err;
 754
 755                                         pnv_calc_dpll_params(refclk, &clock);
 756                                         if (!intel_PLL_is_valid(dev, limit,
 757                                                                 &clock))
 758                                                 continue;
 759                                         if (match_clock &&
 760                                             clock.p != match_clock->p)
 761                                                 continue;
 762
 763                                         this_err = abs(clock.dot - target);
 764                                         if (this_err < err) {
 765                                                 *best_clock = clock;
 766                                                 err = this_err;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772
 773         return (err != target);
 774 }
 775
 776 /*
 777  * Returns a set of divisors for the desired target clock with the given
 778  * refclk, or FALSE.  The returned values represent the clock equation:
 779  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 780  *
 781  * Target and reference clocks are specified in kHz.
 782  *
 783  * If match_clock is provided, then best_clock P divider must match the P
 784  * divider from @match_clock used for LVDS downclocking.
 785  */
 786 static bool
 787 g4x_find_best_dpll(const struct intel_limit *limit,
 788                    struct intel_crtc_state *crtc_state,
 789                    int target, int refclk, struct dpll *match_clock,
 790                    struct dpll *best_clock)
 791 {
 792         struct drm_device *dev = crtc_state->base.crtc->dev;
 793         struct dpll clock;
 794         int max_n;
 795         bool found = false;
 796         /* approximately equals target * 0.00585 */
 797         int err_most = (target >> 8) + (target >> 9);
 798
 799         memset(best_clock, 0, sizeof(*best_clock));
 800
 801         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 802
 803         max_n = limit->n.max;
 804         /* based on hardware requirement, prefer smaller n to precision */
 805         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 806                 /* based on hardware requirement, prefere larger m1,m2 */
 807                 for (clock.m1 = limit->m1.max;
 808                      clock.m1 >= limit->m1.min; clock.m1--) {
 809                         for (clock.m2 = limit->m2.max;
 810                              clock.m2 >= limit->m2.min; clock.m2--) {
 811                                 for (clock.p1 = limit->p1.max;
 812                                      clock.p1 >= limit->p1.min; clock.p1--) {
 813                                         int this_err;
 814
 815                                         i9xx_calc_dpll_params(refclk, &clock);
 816                                         if (!intel_PLL_is_valid(dev, limit,
 817                                                                 &clock))
 818                                                 continue;
 819
 820                                         this_err = abs(clock.dot - target);
 821                                         if (this_err < err_most) {
 822                                                 *best_clock = clock;
 823                                                 err_most = this_err;
 824                                                 max_n = clock.n;
 825                                                 found = true;
 826                                         }
 827                                 }
 828                         }
 829                 }
 830         }
 831         return found;
 832 }
 833
 834 /*
 835  * Check if the calculated PLL configuration is more optimal compared to the
 836  * best configuration and error found so far. Return the calculated error.
 837  */
 838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 839                                const struct dpll *calculated_clock,
 840                                const struct dpll *best_clock,
 841                                unsigned int best_error_ppm,
 842                                unsigned int *error_ppm)
 843 {
 844         /*
 845          * For CHV ignore the error and consider only the P value.
 846          * Prefer a bigger P value based on HW requirements.
 847          */
 848         if (IS_CHERRYVIEW(dev)) {
 849                 *error_ppm = 0;
 850
 851                 return calculated_clock->p > best_clock->p;
 852         }
 853
 854         if (WARN_ON_ONCE(!target_freq))
 855                 return false;
 856
 857         *error_ppm = div_u64(1000000ULL *
 858                                 abs(target_freq - calculated_clock->dot),
 859                              target_freq);
 860         /*
 861          * Prefer a better P value over a better (smaller) error if the error
 862          * is small. Ensure this preference for future configurations too by
 863          * setting the error to 0.
 864          */
 865         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 866                 *error_ppm = 0;
 867
 868                 return true;
 869         }
 870
 871         return *error_ppm + 10 < best_error_ppm;
 872 }
 873
 874 /*
 875  * Returns a set of divisors for the desired target clock with the given
 876  * refclk, or FALSE.  The returned values represent the clock equation:
 877  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 878  */
 879 static bool
 880 vlv_find_best_dpll(const struct intel_limit *limit,
 881                    struct intel_crtc_state *crtc_state,
 882                    int target, int refclk, struct dpll *match_clock,
 883                    struct dpll *best_clock)
 884 {
 885         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 886         struct drm_device *dev = crtc->base.dev;
 887         struct dpll clock;
 888         unsigned int bestppm = 1000000;
 889         /* min update 19.2 MHz */
 890         int max_n = min(limit->n.max, refclk / 19200);
 891         bool found = false;
 892
 893         target *= 5; /* fast clock */
 894
 895         memset(best_clock, 0, sizeof(*best_clock));
 896
 897         /* based on hardware requirement, prefer smaller n to precision */
 898         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 899                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 900                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 901                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 902                                 clock.p = clock.p1 * clock.p2;
 903                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 904                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 905                                         unsigned int ppm;
 906
 907                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 908                                                                      refclk * clock.m1);
 909
 910                                         vlv_calc_dpll_params(refclk, &clock);
 911
 912                                         if (!intel_PLL_is_valid(dev, limit,
 913                                                                 &clock))
 914                                                 continue;
 915
 916                                         if (!vlv_PLL_is_optimal(dev, target,
 917                                                                 &clock,
 918                                                                 best_clock,
 919                                                                 bestppm, &ppm))
 920                                                 continue;
 921
 922                                         *best_clock = clock;
 923                                         bestppm = ppm;
 924                                         found = true;
 925                                 }
 926                         }
 927                 }
 928         }
 929
 930         return found;
 931 }
 932
 933 /*
 934  * Returns a set of divisors for the desired target clock with the given
 935  * refclk, or FALSE.  The returned values represent the clock equation:
 936  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 937  */
 938 static bool
 939 chv_find_best_dpll(const struct intel_limit *limit,
 940                    struct intel_crtc_state *crtc_state,
 941                    int target, int refclk, struct dpll *match_clock,
 942                    struct dpll *best_clock)
 943 {
 944         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 945         struct drm_device *dev = crtc->base.dev;
 946         unsigned int best_error_ppm;
 947         struct dpll clock;
 948         uint64_t m2;
 949         int found = false;
 950
 951         memset(best_clock, 0, sizeof(*best_clock));
 952         best_error_ppm = 1000000;
 953
 954         /*
 955          * Based on hardware doc, the n always set to 1, and m1 always
 956          * set to 2.  If requires to support 200Mhz refclk, we need to
 957          * revisit this because n may not 1 anymore.
 958          */
 959         clock.n = 1, clock.m1 = 2;
 960         target *= 5;    /* fast clock */
 961
 962         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 963                 for (clock.p2 = limit->p2.p2_fast;
 964                                 clock.p2 >= limit->p2.p2_slow;
 965                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 966                         unsigned int error_ppm;
 967
 968                         clock.p = clock.p1 * clock.p2;
 969
 970                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 971                                         clock.n) << 22, refclk * clock.m1);
 972
 973                         if (m2 > INT_MAX/clock.m1)
 974                                 continue;
 975
 976                         clock.m2 = m2;
 977
 978                         chv_calc_dpll_params(refclk, &clock);
 979
 980                         if (!intel_PLL_is_valid(dev, limit, &clock))
 981                                 continue;
 982
 983                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 984                                                 best_error_ppm, &error_ppm))
 985                                 continue;
 986
 987                         *best_clock = clock;
 988                         best_error_ppm = error_ppm;
 989                         found = true;
 990                 }
 991         }
 992
 993         return found;
 994 }
 995
 996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 997                         struct dpll *best_clock)
 998 {
 999         int refclk = 100000;
1000         const struct intel_limit *limit = &intel_limits_bxt;
1001
1002         return chv_find_best_dpll(limit, crtc_state,
1003                                   target_clock, refclk, NULL, best_clock);
1004 }
1005
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1007 {
1008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
1010         /* Be paranoid as we can arrive here with only partial
1011          * state retrieved from the hardware during setup.
1012          *
1013          * We can ditch the adjusted_mode.crtc_clock check as soon
1014          * as Haswell has gained clock readout/fastboot support.
1015          *
1016          * We can ditch the crtc->primary->fb check as soon as we can
1017          * properly reconstruct framebuffers.
1018          *
1019          * FIXME: The intel_crtc->active here should be switched to
1020          * crtc->state->active once we have proper CRTC states wired up
1021          * for atomic.
1022          */
1023         return intel_crtc->active && crtc->primary->state->fb &&
1024                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1025 }
1026
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028                                              enum pipe pipe)
1029 {
1030         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1032
1033         return intel_crtc->config->cpu_transcoder;
1034 }
1035
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1037 {
1038         struct drm_i915_private *dev_priv = to_i915(dev);
1039         i915_reg_t reg = PIPEDSL(pipe);
1040         u32 line1, line2;
1041         u32 line_mask;
1042
1043         if (IS_GEN2(dev))
1044                 line_mask = DSL_LINEMASK_GEN2;
1045         else
1046                 line_mask = DSL_LINEMASK_GEN3;
1047
1048         line1 = I915_READ(reg) & line_mask;
1049         msleep(5);
1050         line2 = I915_READ(reg) & line_mask;
1051
1052         return line1 == line2;
1053 }
1054
1055 /*
1056  * intel_wait_for_pipe_off - wait for pipe to turn off
1057  * @crtc: crtc whose pipe to wait for
1058  *
1059  * After disabling a pipe, we can't wait for vblank in the usual way,
1060  * spinning on the vblank interrupt status bit, since we won't actually
1061  * see an interrupt when the pipe is disabled.
1062  *
1063  * On Gen4 and above:
1064  *   wait for the pipe register state bit to turn off
1065  *
1066  * Otherwise:
1067  *   wait for the display line value to settle (it usually
1068  *   ends up stopping at the start of the next frame).
1069  *
1070  */
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1072 {
1073         struct drm_device *dev = crtc->base.dev;
1074         struct drm_i915_private *dev_priv = to_i915(dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077
1078         if (INTEL_INFO(dev)->gen >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191                            enum pipe pipe)
1192 {
1193         struct drm_device *dev = &dev_priv->drm;
1194         i915_reg_t pp_reg;
1195         u32 val;
1196         enum pipe panel_pipe = PIPE_A;
1197         bool locked = true;
1198
1199         if (WARN_ON(HAS_DDI(dev)))
1200                 return;
1201
1202         if (HAS_PCH_SPLIT(dev)) {
1203                 u32 port_sel;
1204
1205                 pp_reg = PP_CONTROL(0);
1206                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1207
1208                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210                         panel_pipe = PIPE_B;
1211                 /* XXX: else fix for eDP */
1212         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213                 /* presumably write lock depends on pipe, not port select */
1214                 pp_reg = PP_CONTROL(pipe);
1215                 panel_pipe = pipe;
1216         } else {
1217                 pp_reg = PP_CONTROL(0);
1218                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219                         panel_pipe = PIPE_B;
1220         }
1221
1222         val = I915_READ(pp_reg);
1223         if (!(val & PANEL_POWER_ON) ||
1224             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1225                 locked = false;
1226
1227         I915_STATE_WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233                           enum pipe pipe, bool state)
1234 {
1235         struct drm_device *dev = &dev_priv->drm;
1236         bool cur_state;
1237
1238         if (IS_845G(dev) || IS_I865G(dev))
1239                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1240         else
1241                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1242
1243         I915_STATE_WARN(cur_state != state,
1244              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245                         pipe_name(pipe), onoff(state), onoff(cur_state));
1246 }
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251                  enum pipe pipe, bool state)
1252 {
1253         bool cur_state;
1254         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1255                                                                       pipe);
1256         enum intel_display_power_domain power_domain;
1257
1258         /* if we need the pipe quirk it must be always on */
1259         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1261                 state = true;
1262
1263         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266                 cur_state = !!(val & PIPECONF_ENABLE);
1267
1268                 intel_display_power_put(dev_priv, power_domain);
1269         } else {
1270                 cur_state = false;
1271         }
1272
1273         I915_STATE_WARN(cur_state != state,
1274              "pipe %c assertion failure (expected %s, current %s)\n",
1275                         pipe_name(pipe), onoff(state), onoff(cur_state));
1276 }
1277
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279                          enum plane plane, bool state)
1280 {
1281         u32 val;
1282         bool cur_state;
1283
1284         val = I915_READ(DSPCNTR(plane));
1285         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286         I915_STATE_WARN(cur_state != state,
1287              "plane %c assertion failure (expected %s, current %s)\n",
1288                         plane_name(plane), onoff(state), onoff(cur_state));
1289 }
1290
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1295                                    enum pipe pipe)
1296 {
1297         struct drm_device *dev = &dev_priv->drm;
1298         int i;
1299
1300         /* Primary planes are fixed to pipes on gen4+ */
1301         if (INTEL_INFO(dev)->gen >= 4) {
1302                 u32 val = I915_READ(DSPCNTR(pipe));
1303                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304                      "plane %c assertion failure, should be disabled but not\n",
1305                      plane_name(pipe));
1306                 return;
1307         }
1308
1309         /* Need to check both planes against the pipe */
1310         for_each_pipe(dev_priv, i) {
1311                 u32 val = I915_READ(DSPCNTR(i));
1312                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313                         DISPPLANE_SEL_PIPE_SHIFT;
1314                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316                      plane_name(i), pipe_name(pipe));
1317         }
1318 }
1319
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1321                                     enum pipe pipe)
1322 {
1323         struct drm_device *dev = &dev_priv->drm;
1324         int sprite;
1325
1326         if (INTEL_INFO(dev)->gen >= 9) {
1327                 for_each_sprite(dev_priv, pipe, sprite) {
1328                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331                              sprite, pipe_name(pipe));
1332                 }
1333         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334                 for_each_sprite(dev_priv, pipe, sprite) {
1335                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1336                         I915_STATE_WARN(val & SP_ENABLE,
1337                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338                              sprite_name(pipe, sprite), pipe_name(pipe));
1339                 }
1340         } else if (INTEL_INFO(dev)->gen >= 7) {
1341                 u32 val = I915_READ(SPRCTL(pipe));
1342                 I915_STATE_WARN(val & SPRITE_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         } else if (INTEL_INFO(dev)->gen >= 5) {
1346                 u32 val = I915_READ(DVSCNTR(pipe));
1347                 I915_STATE_WARN(val & DVS_ENABLE,
1348                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349                      plane_name(pipe), pipe_name(pipe));
1350         }
1351 }
1352
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1354 {
1355         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356                 drm_crtc_vblank_put(crtc);
1357 }
1358
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1360                                     enum pipe pipe)
1361 {
1362         u32 val;
1363         bool enabled;
1364
1365         val = I915_READ(PCH_TRANSCONF(pipe));
1366         enabled = !!(val & TRANS_ENABLE);
1367         I915_STATE_WARN(enabled,
1368              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369              pipe_name(pipe));
1370 }
1371
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373                             enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375         if ((val & DP_PORT_EN) == 0)
1376                 return false;
1377
1378         if (HAS_PCH_CPT(dev_priv)) {
1379                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381                         return false;
1382         } else if (IS_CHERRYVIEW(dev_priv)) {
1383                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384                         return false;
1385         } else {
1386                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387                         return false;
1388         }
1389         return true;
1390 }
1391
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393                               enum pipe pipe, u32 val)
1394 {
1395         if ((val & SDVO_ENABLE) == 0)
1396                 return false;
1397
1398         if (HAS_PCH_CPT(dev_priv)) {
1399                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1400                         return false;
1401         } else if (IS_CHERRYVIEW(dev_priv)) {
1402                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403                         return false;
1404         } else {
1405                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406                         return false;
1407         }
1408         return true;
1409 }
1410
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412                               enum pipe pipe, u32 val)
1413 {
1414         if ((val & LVDS_PORT_EN) == 0)
1415                 return false;
1416
1417         if (HAS_PCH_CPT(dev_priv)) {
1418                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419                         return false;
1420         } else {
1421                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422                         return false;
1423         }
1424         return true;
1425 }
1426
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428                               enum pipe pipe, u32 val)
1429 {
1430         if ((val & ADPA_DAC_ENABLE) == 0)
1431                 return false;
1432         if (HAS_PCH_CPT(dev_priv)) {
1433                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434                         return false;
1435         } else {
1436                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437                         return false;
1438         }
1439         return true;
1440 }
1441
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443                                    enum pipe pipe, i915_reg_t reg,
1444                                    u32 port_sel)
1445 {
1446         u32 val = I915_READ(reg);
1447         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449              i915_mmio_reg_offset(reg), pipe_name(pipe));
1450
1451         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452              && (val & DP_PIPEB_SELECT),
1453              "IBX PCH dp port still using transcoder B\n");
1454 }
1455
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457                                      enum pipe pipe, i915_reg_t reg)
1458 {
1459         u32 val = I915_READ(reg);
1460         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462              i915_mmio_reg_offset(reg), pipe_name(pipe));
1463
1464         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465              && (val & SDVO_PIPE_B_SELECT),
1466              "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470                                       enum pipe pipe)
1471 {
1472         u32 val;
1473
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478         val = I915_READ(PCH_ADPA);
1479         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480              "PCH VGA enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482
1483         val = I915_READ(PCH_LVDS);
1484         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486              pipe_name(pipe));
1487
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494                             const struct intel_crtc_state *pipe_config)
1495 {
1496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497         enum pipe pipe = crtc->pipe;
1498
1499         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500         POSTING_READ(DPLL(pipe));
1501         udelay(150);
1502
1503         if (intel_wait_for_register(dev_priv,
1504                                     DPLL(pipe),
1505                                     DPLL_LOCK_VLV,
1506                                     DPLL_LOCK_VLV,
1507                                     1))
1508                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1509 }
1510
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512                            const struct intel_crtc_state *pipe_config)
1513 {
1514         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515         enum pipe pipe = crtc->pipe;
1516
1517         assert_pipe_disabled(dev_priv, pipe);
1518
1519         /* PLL is protected by panel, make sure we can write it */
1520         assert_panel_unlocked(dev_priv, pipe);
1521
1522         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523                 _vlv_enable_pll(crtc, pipe_config);
1524
1525         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526         POSTING_READ(DPLL_MD(pipe));
1527 }
1528
1529
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531                             const struct intel_crtc_state *pipe_config)
1532 {
1533         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534         enum pipe pipe = crtc->pipe;
1535         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1536         u32 tmp;
1537
1538         mutex_lock(&dev_priv->sb_lock);
1539
1540         /* Enable back the 10bit clock to display controller */
1541         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542         tmp |= DPIO_DCLKP_EN;
1543         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1544
1545         mutex_unlock(&dev_priv->sb_lock);
1546
1547         /*
1548          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549          */
1550         udelay(1);
1551
1552         /* Enable PLL */
1553         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1554
1555         /* Check PLL is locked */
1556         if (intel_wait_for_register(dev_priv,
1557                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1558                                     1))
1559                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1560 }
1561
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563                            const struct intel_crtc_state *pipe_config)
1564 {
1565         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566         enum pipe pipe = crtc->pipe;
1567
1568         assert_pipe_disabled(dev_priv, pipe);
1569
1570         /* PLL is protected by panel, make sure we can write it */
1571         assert_panel_unlocked(dev_priv, pipe);
1572
1573         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574                 _chv_enable_pll(crtc, pipe_config);
1575
1576         if (pipe != PIPE_A) {
1577                 /*
1578                  * WaPixelRepeatModeFixForC0:chv
1579                  *
1580                  * DPLLCMD is AWOL. Use chicken bits to propagate
1581                  * the value from DPLLBMD to either pipe B or C.
1582                  */
1583                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585                 I915_WRITE(CBR4_VLV, 0);
1586                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1587
1588                 /*
1589                  * DPLLB VGA mode also seems to cause problems.
1590                  * We should always have it disabled.
1591                  */
1592                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1593         } else {
1594                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595                 POSTING_READ(DPLL_MD(pipe));
1596         }
1597 }
1598
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1600 {
1601         struct intel_crtc *crtc;
1602         int count = 0;
1603
1604         for_each_intel_crtc(dev, crtc) {
1605                 count += crtc->base.state->active &&
1606                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1607         }
1608
1609         return count;
1610 }
1611
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614         struct drm_device *dev = crtc->base.dev;
1615         struct drm_i915_private *dev_priv = to_i915(dev);
1616         i915_reg_t reg = DPLL(crtc->pipe);
1617         u32 dpll = crtc->config->dpll_hw_state.dpll;
1618
1619         assert_pipe_disabled(dev_priv, crtc->pipe);
1620
1621         /* PLL is protected by panel, make sure we can write it */
1622         if (IS_MOBILE(dev) && !IS_I830(dev))
1623                 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625         /* Enable DVO 2x clock on both PLLs if necessary */
1626         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1627                 /*
1628                  * It appears to be important that we don't enable this
1629                  * for the current pipe before otherwise configuring the
1630                  * PLL. No idea how this should be handled if multiple
1631                  * DVO outputs are enabled simultaneosly.
1632                  */
1633                 dpll |= DPLL_DVO_2X_MODE;
1634                 I915_WRITE(DPLL(!crtc->pipe),
1635                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1636         }
1637
1638         /*
1639          * Apparently we need to have VGA mode enabled prior to changing
1640          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641          * dividers, even though the register value does change.
1642          */
1643         I915_WRITE(reg, 0);
1644
1645         I915_WRITE(reg, dpll);
1646
1647         /* Wait for the clocks to stabilize. */
1648         POSTING_READ(reg);
1649         udelay(150);
1650
1651         if (INTEL_INFO(dev)->gen >= 4) {
1652                 I915_WRITE(DPLL_MD(crtc->pipe),
1653                            crtc->config->dpll_hw_state.dpll_md);
1654         } else {
1655                 /* The pixel multiplier can only be updated once the
1656                  * DPLL is enabled and the clocks are stable.
1657                  *
1658                  * So write it again.
1659                  */
1660                 I915_WRITE(reg, dpll);
1661         }
1662
1663         /* We do this three times for luck */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667         I915_WRITE(reg, dpll);
1668         POSTING_READ(reg);
1669         udelay(150); /* wait for warmup */
1670         I915_WRITE(reg, dpll);
1671         POSTING_READ(reg);
1672         udelay(150); /* wait for warmup */
1673 }
1674
1675 /**
1676  * i9xx_disable_pll - disable a PLL
1677  * @dev_priv: i915 private structure
1678  * @pipe: pipe PLL to disable
1679  *
1680  * Disable the PLL for @pipe, making sure the pipe is off first.
1681  *
1682  * Note!  This is for pre-ILK only.
1683  */
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1685 {
1686         struct drm_device *dev = crtc->base.dev;
1687         struct drm_i915_private *dev_priv = to_i915(dev);
1688         enum pipe pipe = crtc->pipe;
1689
1690         /* Disable DVO 2x clock on both PLLs if necessary */
1691         if (IS_I830(dev) &&
1692             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693             !intel_num_dvo_pipes(dev)) {
1694                 I915_WRITE(DPLL(PIPE_B),
1695                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696                 I915_WRITE(DPLL(PIPE_A),
1697                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1698         }
1699
1700         /* Don't disable pipe or pipe PLLs if needed */
1701         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1703                 return;
1704
1705         /* Make sure the pipe isn't still relying on us */
1706         assert_pipe_disabled(dev_priv, pipe);
1707
1708         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709         POSTING_READ(DPLL(pipe));
1710 }
1711
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         u32 val;
1715
1716         /* Make sure the pipe isn't still relying on us */
1717         assert_pipe_disabled(dev_priv, pipe);
1718
1719         val = DPLL_INTEGRATED_REF_CLK_VLV |
1720                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1721         if (pipe != PIPE_A)
1722                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1731         u32 val;
1732
1733         /* Make sure the pipe isn't still relying on us */
1734         assert_pipe_disabled(dev_priv, pipe);
1735
1736         val = DPLL_SSC_REF_CLK_CHV |
1737                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1738         if (pipe != PIPE_A)
1739                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1740
1741         I915_WRITE(DPLL(pipe), val);
1742         POSTING_READ(DPLL(pipe));
1743
1744         mutex_lock(&dev_priv->sb_lock);
1745
1746         /* Disable 10bit clock to display controller */
1747         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748         val &= ~DPIO_DCLKP_EN;
1749         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1750
1751         mutex_unlock(&dev_priv->sb_lock);
1752 }
1753
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755                          struct intel_digital_port *dport,
1756                          unsigned int expected_mask)
1757 {
1758         u32 port_mask;
1759         i915_reg_t dpll_reg;
1760
1761         switch (dport->port) {
1762         case PORT_B:
1763                 port_mask = DPLL_PORTB_READY_MASK;
1764                 dpll_reg = DPLL(0);
1765                 break;
1766         case PORT_C:
1767                 port_mask = DPLL_PORTC_READY_MASK;
1768                 dpll_reg = DPLL(0);
1769                 expected_mask <<= 4;
1770                 break;
1771         case PORT_D:
1772                 port_mask = DPLL_PORTD_READY_MASK;
1773                 dpll_reg = DPIO_PHY_STATUS;
1774                 break;
1775         default:
1776                 BUG();
1777         }
1778
1779         if (intel_wait_for_register(dev_priv,
1780                                     dpll_reg, port_mask, expected_mask,
1781                                     1000))
1782                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1784 }
1785
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1787                                            enum pipe pipe)
1788 {
1789         struct drm_device *dev = &dev_priv->drm;
1790         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792         i915_reg_t reg;
1793         uint32_t val, pipeconf_val;
1794
1795         /* Make sure PCH DPLL is enabled */
1796         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1797
1798         /* FDI must be feeding us bits for PCH ports */
1799         assert_fdi_tx_enabled(dev_priv, pipe);
1800         assert_fdi_rx_enabled(dev_priv, pipe);
1801
1802         if (HAS_PCH_CPT(dev)) {
1803                 /* Workaround: Set the timing override bit before enabling the
1804                  * pch transcoder. */
1805                 reg = TRANS_CHICKEN2(pipe);
1806                 val = I915_READ(reg);
1807                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808                 I915_WRITE(reg, val);
1809         }
1810
1811         reg = PCH_TRANSCONF(pipe);
1812         val = I915_READ(reg);
1813         pipeconf_val = I915_READ(PIPECONF(pipe));
1814
1815         if (HAS_PCH_IBX(dev_priv)) {
1816                 /*
1817                  * Make the BPC in transcoder be consistent with
1818                  * that in pipeconf reg. For HDMI we must use 8bpc
1819                  * here for both 8bpc and 12bpc.
1820                  */
1821                 val &= ~PIPECONF_BPC_MASK;
1822                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823                         val |= PIPECONF_8BPC;
1824                 else
1825                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1826         }
1827
1828         val &= ~TRANS_INTERLACE_MASK;
1829         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830                 if (HAS_PCH_IBX(dev_priv) &&
1831                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832                         val |= TRANS_LEGACY_INTERLACED_ILK;
1833                 else
1834                         val |= TRANS_INTERLACED;
1835         else
1836                 val |= TRANS_PROGRESSIVE;
1837
1838         I915_WRITE(reg, val | TRANS_ENABLE);
1839         if (intel_wait_for_register(dev_priv,
1840                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1841                                     100))
1842                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1843 }
1844
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846                                       enum transcoder cpu_transcoder)
1847 {
1848         u32 val, pipeconf_val;
1849
1850         /* FDI must be feeding us bits for PCH ports */
1851         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1853
1854         /* Workaround: set timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858
1859         val = TRANS_ENABLE;
1860         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1861
1862         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863             PIPECONF_INTERLACED_ILK)
1864                 val |= TRANS_INTERLACED;
1865         else
1866                 val |= TRANS_PROGRESSIVE;
1867
1868         I915_WRITE(LPT_TRANSCONF, val);
1869         if (intel_wait_for_register(dev_priv,
1870                                     LPT_TRANSCONF,
1871                                     TRANS_STATE_ENABLE,
1872                                     TRANS_STATE_ENABLE,
1873                                     100))
1874                 DRM_ERROR("Failed to enable PCH transcoder\n");
1875 }
1876
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1878                                             enum pipe pipe)
1879 {
1880         struct drm_device *dev = &dev_priv->drm;
1881         i915_reg_t reg;
1882         uint32_t val;
1883
1884         /* FDI relies on the transcoder */
1885         assert_fdi_tx_disabled(dev_priv, pipe);
1886         assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888         /* Ports must be off as well */
1889         assert_pch_ports_disabled(dev_priv, pipe);
1890
1891         reg = PCH_TRANSCONF(pipe);
1892         val = I915_READ(reg);
1893         val &= ~TRANS_ENABLE;
1894         I915_WRITE(reg, val);
1895         /* wait for PCH transcoder off, transcoder state */
1896         if (intel_wait_for_register(dev_priv,
1897                                     reg, TRANS_STATE_ENABLE, 0,
1898                                     50))
1899                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901         if (HAS_PCH_CPT(dev)) {
1902                 /* Workaround: Clear the timing override chicken bit again. */
1903                 reg = TRANS_CHICKEN2(pipe);
1904                 val = I915_READ(reg);
1905                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906                 I915_WRITE(reg, val);
1907         }
1908 }
1909
1910 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912         u32 val;
1913
1914         val = I915_READ(LPT_TRANSCONF);
1915         val &= ~TRANS_ENABLE;
1916         I915_WRITE(LPT_TRANSCONF, val);
1917         /* wait for PCH transcoder off, transcoder state */
1918         if (intel_wait_for_register(dev_priv,
1919                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920                                     50))
1921                 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923         /* Workaround: clear timing override bit. */
1924         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 /**
1930  * intel_enable_pipe - enable a pipe, asserting requirements
1931  * @crtc: crtc responsible for the pipe
1932  *
1933  * Enable @crtc's pipe, making sure that various hardware specific requirements
1934  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935  */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938         struct drm_device *dev = crtc->base.dev;
1939         struct drm_i915_private *dev_priv = to_i915(dev);
1940         enum pipe pipe = crtc->pipe;
1941         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942         enum pipe pch_transcoder;
1943         i915_reg_t reg;
1944         u32 val;
1945
1946         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
1948         assert_planes_disabled(dev_priv, pipe);
1949         assert_cursor_disabled(dev_priv, pipe);
1950         assert_sprites_disabled(dev_priv, pipe);
1951
1952         if (HAS_PCH_LPT(dev_priv))
1953                 pch_transcoder = TRANSCODER_A;
1954         else
1955                 pch_transcoder = pipe;
1956
1957         /*
1958          * A pipe without a PLL won't actually be able to drive bits from
1959          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1960          * need the check.
1961          */
1962         if (HAS_GMCH_DISPLAY(dev_priv)) {
1963                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964                         assert_dsi_pll_enabled(dev_priv);
1965                 else
1966                         assert_pll_enabled(dev_priv, pipe);
1967         } else {
1968                 if (crtc->config->has_pch_encoder) {
1969                         /* if driving the PCH, we need FDI enabled */
1970                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971                         assert_fdi_tx_pll_enabled(dev_priv,
1972                                                   (enum pipe) cpu_transcoder);
1973                 }
1974                 /* FIXME: assert CPU port conditions for SNB+ */
1975         }
1976
1977         reg = PIPECONF(cpu_transcoder);
1978         val = I915_READ(reg);
1979         if (val & PIPECONF_ENABLE) {
1980                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982                 return;
1983         }
1984
1985         I915_WRITE(reg, val | PIPECONF_ENABLE);
1986         POSTING_READ(reg);
1987
1988         /*
1989          * Until the pipe starts DSL will read as 0, which would cause
1990          * an apparent vblank timestamp jump, which messes up also the
1991          * frame count when it's derived from the timestamps. So let's
1992          * wait for the pipe to start properly before we call
1993          * drm_crtc_vblank_on()
1994          */
1995         if (dev->max_vblank_count == 0 &&
1996             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999
2000 /**
2001  * intel_disable_pipe - disable a pipe, asserting requirements
2002  * @crtc: crtc whose pipes is to be disabled
2003  *
2004  * Disable the pipe of @crtc, making sure that various hardware
2005  * specific requirements are met, if applicable, e.g. plane
2006  * disabled, panel fitter off, etc.
2007  *
2008  * Will wait until the pipe has shut down before returning.
2009  */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014         enum pipe pipe = crtc->pipe;
2015         i915_reg_t reg;
2016         u32 val;
2017
2018         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
2020         /*
2021          * Make sure planes won't keep trying to pump pixels to us,
2022          * or we might hang the display.
2023          */
2024         assert_planes_disabled(dev_priv, pipe);
2025         assert_cursor_disabled(dev_priv, pipe);
2026         assert_sprites_disabled(dev_priv, pipe);
2027
2028         reg = PIPECONF(cpu_transcoder);
2029         val = I915_READ(reg);
2030         if ((val & PIPECONF_ENABLE) == 0)
2031                 return;
2032
2033         /*
2034          * Double wide has implications for planes
2035          * so best keep it disabled when not needed.
2036          */
2037         if (crtc->config->double_wide)
2038                 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040         /* Don't disable pipe or pipe PLLs if needed */
2041         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043                 val &= ~PIPECONF_ENABLE;
2044
2045         I915_WRITE(reg, val);
2046         if ((val & PIPECONF_ENABLE) == 0)
2047                 intel_wait_for_pipe_off(crtc);
2048 }
2049
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052         return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056                                            uint64_t fb_modifier, unsigned int cpp)
2057 {
2058         switch (fb_modifier) {
2059         case DRM_FORMAT_MOD_NONE:
2060                 return cpp;
2061         case I915_FORMAT_MOD_X_TILED:
2062                 if (IS_GEN2(dev_priv))
2063                         return 128;
2064                 else
2065                         return 512;
2066         case I915_FORMAT_MOD_Y_TILED:
2067                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068                         return 128;
2069                 else
2070                         return 512;
2071         case I915_FORMAT_MOD_Yf_TILED:
2072                 switch (cpp) {
2073                 case 1:
2074                         return 64;
2075                 case 2:
2076                 case 4:
2077                         return 128;
2078                 case 8:
2079                 case 16:
2080                         return 256;
2081                 default:
2082                         MISSING_CASE(cpp);
2083                         return cpp;
2084                 }
2085                 break;
2086         default:
2087                 MISSING_CASE(fb_modifier);
2088                 return cpp;
2089         }
2090 }
2091
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093                                uint64_t fb_modifier, unsigned int cpp)
2094 {
2095         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096                 return 1;
2097         else
2098                 return intel_tile_size(dev_priv) /
2099                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104                             unsigned int *tile_width,
2105                             unsigned int *tile_height,
2106                             uint64_t fb_modifier,
2107                             unsigned int cpp)
2108 {
2109         unsigned int tile_width_bytes =
2110                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112         *tile_width = tile_width_bytes / cpp;
2113         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118                       uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123         return ALIGN(height, tile_height);
2124 }
2125
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128         unsigned int size = 0;
2129         int i;
2130
2131         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134         return size;
2135 }
2136
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139                         const struct drm_framebuffer *fb,
2140                         unsigned int rotation)
2141 {
2142         if (intel_rotation_90_or_270(rotation)) {
2143                 *view = i915_ggtt_view_rotated;
2144                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145         } else {
2146                 *view = i915_ggtt_view_normal;
2147         }
2148 }
2149
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152         if (INTEL_INFO(dev_priv)->gen >= 9)
2153                 return 256 * 1024;
2154         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156                 return 128 * 1024;
2157         else if (INTEL_INFO(dev_priv)->gen >= 4)
2158                 return 4 * 1024;
2159         else
2160                 return 0;
2161 }
2162
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164                                          uint64_t fb_modifier)
2165 {
2166         switch (fb_modifier) {
2167         case DRM_FORMAT_MOD_NONE:
2168                 return intel_linear_alignment(dev_priv);
2169         case I915_FORMAT_MOD_X_TILED:
2170                 if (INTEL_INFO(dev_priv)->gen >= 9)
2171                         return 256 * 1024;
2172                 return 0;
2173         case I915_FORMAT_MOD_Y_TILED:
2174         case I915_FORMAT_MOD_Yf_TILED:
2175                 return 1 * 1024 * 1024;
2176         default:
2177                 MISSING_CASE(fb_modifier);
2178                 return 0;
2179         }
2180 }
2181
2182 struct i915_vma *
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2184 {
2185         struct drm_device *dev = fb->dev;
2186         struct drm_i915_private *dev_priv = to_i915(dev);
2187         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2188         struct i915_ggtt_view view;
2189         struct i915_vma *vma;
2190         u32 alignment;
2191
2192         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2193
2194         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2195
2196         intel_fill_fb_ggtt_view(&view, fb, rotation);
2197
2198         /* Note that the w/a also requires 64 PTE of padding following the
2199          * bo. We currently fill all unused PTE with the shadow page and so
2200          * we should always have valid PTE following the scanout preventing
2201          * the VT-d warning.
2202          */
2203         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2204                 alignment = 256 * 1024;
2205
2206         /*
2207          * Global gtt pte registers are special registers which actually forward
2208          * writes to a chunk of system memory. Which means that there is no risk
2209          * that the register values disappear as soon as we call
2210          * intel_runtime_pm_put(), so it is correct to wrap only the
2211          * pin/unpin/fence and not more.
2212          */
2213         intel_runtime_pm_get(dev_priv);
2214
2215         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2216         if (IS_ERR(vma))
2217                 goto err;
2218
2219         if (i915_vma_is_map_and_fenceable(vma)) {
2220                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2221                  * fence, whereas 965+ only requires a fence if using
2222                  * framebuffer compression.  For simplicity, we always, when
2223                  * possible, install a fence as the cost is not that onerous.
2224                  *
2225                  * If we fail to fence the tiled scanout, then either the
2226                  * modeset will reject the change (which is highly unlikely as
2227                  * the affected systems, all but one, do not have unmappable
2228                  * space) or we will not be able to enable full powersaving
2229                  * techniques (also likely not to apply due to various limits
2230                  * FBC and the like impose on the size of the buffer, which
2231                  * presumably we violated anyway with this unmappable buffer).
2232                  * Anyway, it is presumably better to stumble onwards with
2233                  * something and try to run the system in a "less than optimal"
2234                  * mode that matches the user configuration.
2235                  */
2236                 if (i915_vma_get_fence(vma) == 0)
2237                         i915_vma_pin_fence(vma);
2238         }
2239
2240 err:
2241         intel_runtime_pm_put(dev_priv);
2242         return vma;
2243 }
2244
2245 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2246 {
2247         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248         struct i915_ggtt_view view;
2249         struct i915_vma *vma;
2250
2251         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2252
2253         intel_fill_fb_ggtt_view(&view, fb, rotation);
2254         vma = i915_gem_object_to_ggtt(obj, &view);
2255
2256         i915_vma_unpin_fence(vma);
2257         i915_gem_object_unpin_from_display_plane(vma);
2258 }
2259
2260 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2261                           unsigned int rotation)
2262 {
2263         if (intel_rotation_90_or_270(rotation))
2264                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2265         else
2266                 return fb->pitches[plane];
2267 }
2268
2269 /*
2270  * Convert the x/y offsets into a linear offset.
2271  * Only valid with 0/180 degree rotation, which is fine since linear
2272  * offset is only used with linear buffers on pre-hsw and tiled buffers
2273  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2274  */
2275 u32 intel_fb_xy_to_linear(int x, int y,
2276                           const struct intel_plane_state *state,
2277                           int plane)
2278 {
2279         const struct drm_framebuffer *fb = state->base.fb;
2280         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2281         unsigned int pitch = fb->pitches[plane];
2282
2283         return y * pitch + x * cpp;
2284 }
2285
2286 /*
2287  * Add the x/y offsets derived from fb->offsets[] to the user
2288  * specified plane src x/y offsets. The resulting x/y offsets
2289  * specify the start of scanout from the beginning of the gtt mapping.
2290  */
2291 void intel_add_fb_offsets(int *x, int *y,
2292                           const struct intel_plane_state *state,
2293                           int plane)
2294
2295 {
2296         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2297         unsigned int rotation = state->base.rotation;
2298
2299         if (intel_rotation_90_or_270(rotation)) {
2300                 *x += intel_fb->rotated[plane].x;
2301                 *y += intel_fb->rotated[plane].y;
2302         } else {
2303                 *x += intel_fb->normal[plane].x;
2304                 *y += intel_fb->normal[plane].y;
2305         }
2306 }
2307
2308 /*
2309  * Input tile dimensions and pitch must already be
2310  * rotated to match x and y, and in pixel units.
2311  */
2312 static u32 _intel_adjust_tile_offset(int *x, int *y,
2313                                      unsigned int tile_width,
2314                                      unsigned int tile_height,
2315                                      unsigned int tile_size,
2316                                      unsigned int pitch_tiles,
2317                                      u32 old_offset,
2318                                      u32 new_offset)
2319 {
2320         unsigned int pitch_pixels = pitch_tiles * tile_width;
2321         unsigned int tiles;
2322
2323         WARN_ON(old_offset & (tile_size - 1));
2324         WARN_ON(new_offset & (tile_size - 1));
2325         WARN_ON(new_offset > old_offset);
2326
2327         tiles = (old_offset - new_offset) / tile_size;
2328
2329         *y += tiles / pitch_tiles * tile_height;
2330         *x += tiles % pitch_tiles * tile_width;
2331
2332         /* minimize x in case it got needlessly big */
2333         *y += *x / pitch_pixels * tile_height;
2334         *x %= pitch_pixels;
2335
2336         return new_offset;
2337 }
2338
2339 /*
2340  * Adjust the tile offset by moving the difference into
2341  * the x/y offsets.
2342  */
2343 static u32 intel_adjust_tile_offset(int *x, int *y,
2344                                     const struct intel_plane_state *state, int plane,
2345                                     u32 old_offset, u32 new_offset)
2346 {
2347         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2348         const struct drm_framebuffer *fb = state->base.fb;
2349         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2350         unsigned int rotation = state->base.rotation;
2351         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2352
2353         WARN_ON(new_offset > old_offset);
2354
2355         if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2356                 unsigned int tile_size, tile_width, tile_height;
2357                 unsigned int pitch_tiles;
2358
2359                 tile_size = intel_tile_size(dev_priv);
2360                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2361                                 fb->modifier[plane], cpp);
2362
2363                 if (intel_rotation_90_or_270(rotation)) {
2364                         pitch_tiles = pitch / tile_height;
2365                         swap(tile_width, tile_height);
2366                 } else {
2367                         pitch_tiles = pitch / (tile_width * cpp);
2368                 }
2369
2370                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2371                                           tile_size, pitch_tiles,
2372                                           old_offset, new_offset);
2373         } else {
2374                 old_offset += *y * pitch + *x * cpp;
2375
2376                 *y = (old_offset - new_offset) / pitch;
2377                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2378         }
2379
2380         return new_offset;
2381 }
2382
2383 /*
2384  * Computes the linear offset to the base tile and adjusts
2385  * x, y. bytes per pixel is assumed to be a power-of-two.
2386  *
2387  * In the 90/270 rotated case, x and y are assumed
2388  * to be already rotated to match the rotated GTT view, and
2389  * pitch is the tile_height aligned framebuffer height.
2390  *
2391  * This function is used when computing the derived information
2392  * under intel_framebuffer, so using any of that information
2393  * here is not allowed. Anything under drm_framebuffer can be
2394  * used. This is why the user has to pass in the pitch since it
2395  * is specified in the rotated orientation.
2396  */
2397 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2398                                       int *x, int *y,
2399                                       const struct drm_framebuffer *fb, int plane,
2400                                       unsigned int pitch,
2401                                       unsigned int rotation,
2402                                       u32 alignment)
2403 {
2404         uint64_t fb_modifier = fb->modifier[plane];
2405         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2406         u32 offset, offset_aligned;
2407
2408         if (alignment)
2409                 alignment--;
2410
2411         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2412                 unsigned int tile_size, tile_width, tile_height;
2413                 unsigned int tile_rows, tiles, pitch_tiles;
2414
2415                 tile_size = intel_tile_size(dev_priv);
2416                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2417                                 fb_modifier, cpp);
2418
2419                 if (intel_rotation_90_or_270(rotation)) {
2420                         pitch_tiles = pitch / tile_height;
2421                         swap(tile_width, tile_height);
2422                 } else {
2423                         pitch_tiles = pitch / (tile_width * cpp);
2424                 }
2425
2426                 tile_rows = *y / tile_height;
2427                 *y %= tile_height;
2428
2429                 tiles = *x / tile_width;
2430                 *x %= tile_width;
2431
2432                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2433                 offset_aligned = offset & ~alignment;
2434
2435                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2436                                           tile_size, pitch_tiles,
2437                                           offset, offset_aligned);
2438         } else {
2439                 offset = *y * pitch + *x * cpp;
2440                 offset_aligned = offset & ~alignment;
2441
2442                 *y = (offset & alignment) / pitch;
2443                 *x = ((offset & alignment) - *y * pitch) / cpp;
2444         }
2445
2446         return offset_aligned;
2447 }
2448
2449 u32 intel_compute_tile_offset(int *x, int *y,
2450                               const struct intel_plane_state *state,
2451                               int plane)
2452 {
2453         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2454         const struct drm_framebuffer *fb = state->base.fb;
2455         unsigned int rotation = state->base.rotation;
2456         int pitch = intel_fb_pitch(fb, plane, rotation);
2457         u32 alignment;
2458
2459         /* AUX_DIST needs only 4K alignment */
2460         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2461                 alignment = 4096;
2462         else
2463                 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2464
2465         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2466                                           rotation, alignment);
2467 }
2468
2469 /* Convert the fb->offset[] linear offset into x/y offsets */
2470 static void intel_fb_offset_to_xy(int *x, int *y,
2471                                   const struct drm_framebuffer *fb, int plane)
2472 {
2473         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2474         unsigned int pitch = fb->pitches[plane];
2475         u32 linear_offset = fb->offsets[plane];
2476
2477         *y = linear_offset / pitch;
2478         *x = linear_offset % pitch / cpp;
2479 }
2480
2481 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2482 {
2483         switch (fb_modifier) {
2484         case I915_FORMAT_MOD_X_TILED:
2485                 return I915_TILING_X;
2486         case I915_FORMAT_MOD_Y_TILED:
2487                 return I915_TILING_Y;
2488         default:
2489                 return I915_TILING_NONE;
2490         }
2491 }
2492
2493 static int
2494 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2495                    struct drm_framebuffer *fb)
2496 {
2497         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2498         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2499         u32 gtt_offset_rotated = 0;
2500         unsigned int max_size = 0;
2501         uint32_t format = fb->pixel_format;
2502         int i, num_planes = drm_format_num_planes(format);
2503         unsigned int tile_size = intel_tile_size(dev_priv);
2504
2505         for (i = 0; i < num_planes; i++) {
2506                 unsigned int width, height;
2507                 unsigned int cpp, size;
2508                 u32 offset;
2509                 int x, y;
2510
2511                 cpp = drm_format_plane_cpp(format, i);
2512                 width = drm_format_plane_width(fb->width, format, i);
2513                 height = drm_format_plane_height(fb->height, format, i);
2514
2515                 intel_fb_offset_to_xy(&x, &y, fb, i);
2516
2517                 /*
2518                  * The fence (if used) is aligned to the start of the object
2519                  * so having the framebuffer wrap around across the edge of the
2520                  * fenced region doesn't really work. We have no API to configure
2521                  * the fence start offset within the object (nor could we probably
2522                  * on gen2/3). So it's just easier if we just require that the
2523                  * fb layout agrees with the fence layout. We already check that the
2524                  * fb stride matches the fence stride elsewhere.
2525                  */
2526                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2527                     (x + width) * cpp > fb->pitches[i]) {
2528                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2529                                   i, fb->offsets[i]);
2530                         return -EINVAL;
2531                 }
2532
2533                 /*
2534                  * First pixel of the framebuffer from
2535                  * the start of the normal gtt mapping.
2536                  */
2537                 intel_fb->normal[i].x = x;
2538                 intel_fb->normal[i].y = y;
2539
2540                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2541                                                     fb, 0, fb->pitches[i],
2542                                                     DRM_ROTATE_0, tile_size);
2543                 offset /= tile_size;
2544
2545                 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2546                         unsigned int tile_width, tile_height;
2547                         unsigned int pitch_tiles;
2548                         struct drm_rect r;
2549
2550                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2551                                         fb->modifier[i], cpp);
2552
2553                         rot_info->plane[i].offset = offset;
2554                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2555                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2556                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2557
2558                         intel_fb->rotated[i].pitch =
2559                                 rot_info->plane[i].height * tile_height;
2560
2561                         /* how many tiles does this plane need */
2562                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2563                         /*
2564                          * If the plane isn't horizontally tile aligned,
2565                          * we need one more tile.
2566                          */
2567                         if (x != 0)
2568                                 size++;
2569
2570                         /* rotate the x/y offsets to match the GTT view */
2571                         r.x1 = x;
2572                         r.y1 = y;
2573                         r.x2 = x + width;
2574                         r.y2 = y + height;
2575                         drm_rect_rotate(&r,
2576                                         rot_info->plane[i].width * tile_width,
2577                                         rot_info->plane[i].height * tile_height,
2578                                         DRM_ROTATE_270);
2579                         x = r.x1;
2580                         y = r.y1;
2581
2582                         /* rotate the tile dimensions to match the GTT view */
2583                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2584                         swap(tile_width, tile_height);
2585
2586                         /*
2587                          * We only keep the x/y offsets, so push all of the
2588                          * gtt offset into the x/y offsets.
2589                          */
2590                         _intel_adjust_tile_offset(&x, &y, tile_size,
2591                                                   tile_width, tile_height, pitch_tiles,
2592                                                   gtt_offset_rotated * tile_size, 0);
2593
2594                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2595
2596                         /*
2597                          * First pixel of the framebuffer from
2598                          * the start of the rotated gtt mapping.
2599                          */
2600                         intel_fb->rotated[i].x = x;
2601                         intel_fb->rotated[i].y = y;
2602                 } else {
2603                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2604                                             x * cpp, tile_size);
2605                 }
2606
2607                 /* how many tiles in total needed in the bo */
2608                 max_size = max(max_size, offset + size);
2609         }
2610
2611         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2612                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2613                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2614                 return -EINVAL;
2615         }
2616
2617         return 0;
2618 }
2619
2620 static int i9xx_format_to_fourcc(int format)
2621 {
2622         switch (format) {
2623         case DISPPLANE_8BPP:
2624                 return DRM_FORMAT_C8;
2625         case DISPPLANE_BGRX555:
2626                 return DRM_FORMAT_XRGB1555;
2627         case DISPPLANE_BGRX565:
2628                 return DRM_FORMAT_RGB565;
2629         default:
2630         case DISPPLANE_BGRX888:
2631                 return DRM_FORMAT_XRGB8888;
2632         case DISPPLANE_RGBX888:
2633                 return DRM_FORMAT_XBGR8888;
2634         case DISPPLANE_BGRX101010:
2635                 return DRM_FORMAT_XRGB2101010;
2636         case DISPPLANE_RGBX101010:
2637                 return DRM_FORMAT_XBGR2101010;
2638         }
2639 }
2640
2641 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2642 {
2643         switch (format) {
2644         case PLANE_CTL_FORMAT_RGB_565:
2645                 return DRM_FORMAT_RGB565;
2646         default:
2647         case PLANE_CTL_FORMAT_XRGB_8888:
2648                 if (rgb_order) {
2649                         if (alpha)
2650                                 return DRM_FORMAT_ABGR8888;
2651                         else
2652                                 return DRM_FORMAT_XBGR8888;
2653                 } else {
2654                         if (alpha)
2655                                 return DRM_FORMAT_ARGB8888;
2656                         else
2657                                 return DRM_FORMAT_XRGB8888;
2658                 }
2659         case PLANE_CTL_FORMAT_XRGB_2101010:
2660                 if (rgb_order)
2661                         return DRM_FORMAT_XBGR2101010;
2662                 else
2663                         return DRM_FORMAT_XRGB2101010;
2664         }
2665 }
2666
2667 static bool
2668 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2669                               struct intel_initial_plane_config *plane_config)
2670 {
2671         struct drm_device *dev = crtc->base.dev;
2672         struct drm_i915_private *dev_priv = to_i915(dev);
2673         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2674         struct drm_i915_gem_object *obj = NULL;
2675         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2676         struct drm_framebuffer *fb = &plane_config->fb->base;
2677         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2678         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2679                                     PAGE_SIZE);
2680
2681         size_aligned -= base_aligned;
2682
2683         if (plane_config->size == 0)
2684                 return false;
2685
2686         /* If the FB is too big, just don't use it since fbdev is not very
2687          * important and we should probably use that space with FBC or other
2688          * features. */
2689         if (size_aligned * 2 > ggtt->stolen_usable_size)
2690                 return false;
2691
2692         mutex_lock(&dev->struct_mutex);
2693
2694         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2695                                                              base_aligned,
2696                                                              base_aligned,
2697                                                              size_aligned);
2698         if (!obj) {
2699                 mutex_unlock(&dev->struct_mutex);
2700                 return false;
2701         }
2702
2703         if (plane_config->tiling == I915_TILING_X)
2704                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2705
2706         mode_cmd.pixel_format = fb->pixel_format;
2707         mode_cmd.width = fb->width;
2708         mode_cmd.height = fb->height;
2709         mode_cmd.pitches[0] = fb->pitches[0];
2710         mode_cmd.modifier[0] = fb->modifier[0];
2711         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2712
2713         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2714                                    &mode_cmd, obj)) {
2715                 DRM_DEBUG_KMS("intel fb init failed\n");
2716                 goto out_unref_obj;
2717         }
2718
2719         mutex_unlock(&dev->struct_mutex);
2720
2721         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2722         return true;
2723
2724 out_unref_obj:
2725         i915_gem_object_put(obj);
2726         mutex_unlock(&dev->struct_mutex);
2727         return false;
2728 }
2729
2730 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2731 static void
2732 update_state_fb(struct drm_plane *plane)
2733 {
2734         if (plane->fb == plane->state->fb)
2735                 return;
2736
2737         if (plane->state->fb)
2738                 drm_framebuffer_unreference(plane->state->fb);
2739         plane->state->fb = plane->fb;
2740         if (plane->state->fb)
2741                 drm_framebuffer_reference(plane->state->fb);
2742 }
2743
2744 static void
2745 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2746                              struct intel_initial_plane_config *plane_config)
2747 {
2748         struct drm_device *dev = intel_crtc->base.dev;
2749         struct drm_i915_private *dev_priv = to_i915(dev);
2750         struct drm_crtc *c;
2751         struct intel_crtc *i;
2752         struct drm_i915_gem_object *obj;
2753         struct drm_plane *primary = intel_crtc->base.primary;
2754         struct drm_plane_state *plane_state = primary->state;
2755         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2756         struct intel_plane *intel_plane = to_intel_plane(primary);
2757         struct intel_plane_state *intel_state =
2758                 to_intel_plane_state(plane_state);
2759         struct drm_framebuffer *fb;
2760
2761         if (!plane_config->fb)
2762                 return;
2763
2764         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2765                 fb = &plane_config->fb->base;
2766                 goto valid_fb;
2767         }
2768
2769         kfree(plane_config->fb);
2770
2771         /*
2772          * Failed to alloc the obj, check to see if we should share
2773          * an fb with another CRTC instead
2774          */
2775         for_each_crtc(dev, c) {
2776                 i = to_intel_crtc(c);
2777
2778                 if (c == &intel_crtc->base)
2779                         continue;
2780
2781                 if (!i->active)
2782                         continue;
2783
2784                 fb = c->primary->fb;
2785                 if (!fb)
2786                         continue;
2787
2788                 obj = intel_fb_obj(fb);
2789                 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2790                         drm_framebuffer_reference(fb);
2791                         goto valid_fb;
2792                 }
2793         }
2794
2795         /*
2796          * We've failed to reconstruct the BIOS FB.  Current display state
2797          * indicates that the primary plane is visible, but has a NULL FB,
2798          * which will lead to problems later if we don't fix it up.  The
2799          * simplest solution is to just disable the primary plane now and
2800          * pretend the BIOS never had it enabled.
2801          */
2802         to_intel_plane_state(plane_state)->base.visible = false;
2803         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2804         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2805         intel_plane->disable_plane(primary, &intel_crtc->base);
2806
2807         return;
2808
2809 valid_fb:
2810         plane_state->src_x = 0;
2811         plane_state->src_y = 0;
2812         plane_state->src_w = fb->width << 16;
2813         plane_state->src_h = fb->height << 16;
2814
2815         plane_state->crtc_x = 0;
2816         plane_state->crtc_y = 0;
2817         plane_state->crtc_w = fb->width;
2818         plane_state->crtc_h = fb->height;
2819
2820         intel_state->base.src.x1 = plane_state->src_x;
2821         intel_state->base.src.y1 = plane_state->src_y;
2822         intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2823         intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2824         intel_state->base.dst.x1 = plane_state->crtc_x;
2825         intel_state->base.dst.y1 = plane_state->crtc_y;
2826         intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2827         intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2828
2829         obj = intel_fb_obj(fb);
2830         if (i915_gem_object_is_tiled(obj))
2831                 dev_priv->preserve_bios_swizzle = true;
2832
2833         drm_framebuffer_reference(fb);
2834         primary->fb = primary->state->fb = fb;
2835         primary->crtc = primary->state->crtc = &intel_crtc->base;
2836         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2837         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2838                   &obj->frontbuffer_bits);
2839 }
2840
2841 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2842                                unsigned int rotation)
2843 {
2844         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2845
2846         switch (fb->modifier[plane]) {
2847         case DRM_FORMAT_MOD_NONE:
2848         case I915_FORMAT_MOD_X_TILED:
2849                 switch (cpp) {
2850                 case 8:
2851                         return 4096;
2852                 case 4:
2853                 case 2:
2854                 case 1:
2855                         return 8192;
2856                 default:
2857                         MISSING_CASE(cpp);
2858                         break;
2859                 }
2860                 break;
2861         case I915_FORMAT_MOD_Y_TILED:
2862         case I915_FORMAT_MOD_Yf_TILED:
2863                 switch (cpp) {
2864                 case 8:
2865                         return 2048;
2866                 case 4:
2867                         return 4096;
2868                 case 2:
2869                 case 1:
2870                         return 8192;
2871                 default:
2872                         MISSING_CASE(cpp);
2873                         break;
2874                 }
2875                 break;
2876         default:
2877                 MISSING_CASE(fb->modifier[plane]);
2878         }
2879
2880         return 2048;
2881 }
2882
2883 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2884 {
2885         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2886         const struct drm_framebuffer *fb = plane_state->base.fb;
2887         unsigned int rotation = plane_state->base.rotation;
2888         int x = plane_state->base.src.x1 >> 16;
2889         int y = plane_state->base.src.y1 >> 16;
2890         int w = drm_rect_width(&plane_state->base.src) >> 16;
2891         int h = drm_rect_height(&plane_state->base.src) >> 16;
2892         int max_width = skl_max_plane_width(fb, 0, rotation);
2893         int max_height = 4096;
2894         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2895
2896         if (w > max_width || h > max_height) {
2897                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2898                               w, h, max_width, max_height);
2899                 return -EINVAL;
2900         }
2901
2902         intel_add_fb_offsets(&x, &y, plane_state, 0);
2903         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2904
2905         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2906
2907         /*
2908          * AUX surface offset is specified as the distance from the
2909          * main surface offset, and it must be non-negative. Make
2910          * sure that is what we will get.
2911          */
2912         if (offset > aux_offset)
2913                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2914                                                   offset, aux_offset & ~(alignment - 1));
2915
2916         /*
2917          * When using an X-tiled surface, the plane blows up
2918          * if the x offset + width exceed the stride.
2919          *
2920          * TODO: linear and Y-tiled seem fine, Yf untested,
2921          */
2922         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2923                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2924
2925                 while ((x + w) * cpp > fb->pitches[0]) {
2926                         if (offset == 0) {
2927                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2928                                 return -EINVAL;
2929                         }
2930
2931                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2932                                                           offset, offset - alignment);
2933                 }
2934         }
2935
2936         plane_state->main.offset = offset;
2937         plane_state->main.x = x;
2938         plane_state->main.y = y;
2939
2940         return 0;
2941 }
2942
2943 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2944 {
2945         const struct drm_framebuffer *fb = plane_state->base.fb;
2946         unsigned int rotation = plane_state->base.rotation;
2947         int max_width = skl_max_plane_width(fb, 1, rotation);
2948         int max_height = 4096;
2949         int x = plane_state->base.src.x1 >> 17;
2950         int y = plane_state->base.src.y1 >> 17;
2951         int w = drm_rect_width(&plane_state->base.src) >> 17;
2952         int h = drm_rect_height(&plane_state->base.src) >> 17;
2953         u32 offset;
2954
2955         intel_add_fb_offsets(&x, &y, plane_state, 1);
2956         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2957
2958         /* FIXME not quite sure how/if these apply to the chroma plane */
2959         if (w > max_width || h > max_height) {
2960                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2961                               w, h, max_width, max_height);
2962                 return -EINVAL;
2963         }
2964
2965         plane_state->aux.offset = offset;
2966         plane_state->aux.x = x;
2967         plane_state->aux.y = y;
2968
2969         return 0;
2970 }
2971
2972 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2973 {
2974         const struct drm_framebuffer *fb = plane_state->base.fb;
2975         unsigned int rotation = plane_state->base.rotation;
2976         int ret;
2977
2978         /* Rotate src coordinates to match rotated GTT view */
2979         if (intel_rotation_90_or_270(rotation))
2980                 drm_rect_rotate(&plane_state->base.src,
2981                                 fb->width, fb->height, DRM_ROTATE_270);
2982
2983         /*
2984          * Handle the AUX surface first since
2985          * the main surface setup depends on it.
2986          */
2987         if (fb->pixel_format == DRM_FORMAT_NV12) {
2988                 ret = skl_check_nv12_aux_surface(plane_state);
2989                 if (ret)
2990                         return ret;
2991         } else {
2992                 plane_state->aux.offset = ~0xfff;
2993                 plane_state->aux.x = 0;
2994                 plane_state->aux.y = 0;
2995         }
2996
2997         ret = skl_check_main_surface(plane_state);
2998         if (ret)
2999                 return ret;
3000
3001         return 0;
3002 }
3003
3004 static void i9xx_update_primary_plane(struct drm_plane *primary,
3005                                       const struct intel_crtc_state *crtc_state,
3006                                       const struct intel_plane_state *plane_state)
3007 {
3008         struct drm_device *dev = primary->dev;
3009         struct drm_i915_private *dev_priv = to_i915(dev);
3010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3011         struct drm_framebuffer *fb = plane_state->base.fb;
3012         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3013         int plane = intel_crtc->plane;
3014         u32 linear_offset;
3015         u32 dspcntr;
3016         i915_reg_t reg = DSPCNTR(plane);
3017         unsigned int rotation = plane_state->base.rotation;
3018         int x = plane_state->base.src.x1 >> 16;
3019         int y = plane_state->base.src.y1 >> 16;
3020
3021         dspcntr = DISPPLANE_GAMMA_ENABLE;
3022
3023         dspcntr |= DISPLAY_PLANE_ENABLE;
3024
3025         if (INTEL_INFO(dev)->gen < 4) {
3026                 if (intel_crtc->pipe == PIPE_B)
3027                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3028
3029                 /* pipesrc and dspsize control the size that is scaled from,
3030                  * which should always be the user's requested size.
3031                  */
3032                 I915_WRITE(DSPSIZE(plane),
3033                            ((crtc_state->pipe_src_h - 1) << 16) |
3034                            (crtc_state->pipe_src_w - 1));
3035                 I915_WRITE(DSPPOS(plane), 0);
3036         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3037                 I915_WRITE(PRIMSIZE(plane),
3038                            ((crtc_state->pipe_src_h - 1) << 16) |
3039                            (crtc_state->pipe_src_w - 1));
3040                 I915_WRITE(PRIMPOS(plane), 0);
3041                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3042         }
3043
3044         switch (fb->pixel_format) {
3045         case DRM_FORMAT_C8:
3046                 dspcntr |= DISPPLANE_8BPP;
3047                 break;
3048         case DRM_FORMAT_XRGB1555:
3049                 dspcntr |= DISPPLANE_BGRX555;
3050                 break;
3051         case DRM_FORMAT_RGB565:
3052                 dspcntr |= DISPPLANE_BGRX565;
3053                 break;
3054         case DRM_FORMAT_XRGB8888:
3055                 dspcntr |= DISPPLANE_BGRX888;
3056                 break;
3057         case DRM_FORMAT_XBGR8888:
3058                 dspcntr |= DISPPLANE_RGBX888;
3059                 break;
3060         case DRM_FORMAT_XRGB2101010:
3061                 dspcntr |= DISPPLANE_BGRX101010;
3062                 break;
3063         case DRM_FORMAT_XBGR2101010:
3064                 dspcntr |= DISPPLANE_RGBX101010;
3065                 break;
3066         default:
3067                 BUG();
3068         }
3069
3070         if (INTEL_GEN(dev_priv) >= 4 &&
3071             fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3072                 dspcntr |= DISPPLANE_TILED;
3073
3074         if (IS_G4X(dev))
3075                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3076
3077         intel_add_fb_offsets(&x, &y, plane_state, 0);
3078
3079         if (INTEL_INFO(dev)->gen >= 4)
3080                 intel_crtc->dspaddr_offset =
3081                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3082
3083         if (rotation == DRM_ROTATE_180) {
3084                 dspcntr |= DISPPLANE_ROTATE_180;
3085
3086                 x += (crtc_state->pipe_src_w - 1);
3087                 y += (crtc_state->pipe_src_h - 1);
3088         }
3089
3090         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3091
3092         if (INTEL_INFO(dev)->gen < 4)
3093                 intel_crtc->dspaddr_offset = linear_offset;
3094
3095         intel_crtc->adjusted_x = x;
3096         intel_crtc->adjusted_y = y;
3097
3098         I915_WRITE(reg, dspcntr);
3099
3100         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3101         if (INTEL_INFO(dev)->gen >= 4) {
3102                 I915_WRITE(DSPSURF(plane),
3103                            intel_fb_gtt_offset(fb, rotation) +
3104                            intel_crtc->dspaddr_offset);
3105                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3106                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3107         } else
3108                 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
3109         POSTING_READ(reg);
3110 }
3111
3112 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3113                                        struct drm_crtc *crtc)
3114 {
3115         struct drm_device *dev = crtc->dev;
3116         struct drm_i915_private *dev_priv = to_i915(dev);
3117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3118         int plane = intel_crtc->plane;
3119
3120         I915_WRITE(DSPCNTR(plane), 0);
3121         if (INTEL_INFO(dev_priv)->gen >= 4)
3122                 I915_WRITE(DSPSURF(plane), 0);
3123         else
3124                 I915_WRITE(DSPADDR(plane), 0);
3125         POSTING_READ(DSPCNTR(plane));
3126 }
3127
3128 static void ironlake_update_primary_plane(struct drm_plane *primary,
3129                                           const struct intel_crtc_state *crtc_state,
3130                                           const struct intel_plane_state *plane_state)
3131 {
3132         struct drm_device *dev = primary->dev;
3133         struct drm_i915_private *dev_priv = to_i915(dev);
3134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3135         struct drm_framebuffer *fb = plane_state->base.fb;
3136         int plane = intel_crtc->plane;
3137         u32 linear_offset;
3138         u32 dspcntr;
3139         i915_reg_t reg = DSPCNTR(plane);
3140         unsigned int rotation = plane_state->base.rotation;
3141         int x = plane_state->base.src.x1 >> 16;
3142         int y = plane_state->base.src.y1 >> 16;
3143
3144         dspcntr = DISPPLANE_GAMMA_ENABLE;
3145         dspcntr |= DISPLAY_PLANE_ENABLE;
3146
3147         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3148                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3149
3150         switch (fb->pixel_format) {
3151         case DRM_FORMAT_C8:
3152                 dspcntr |= DISPPLANE_8BPP;
3153                 break;
3154         case DRM_FORMAT_RGB565:
3155                 dspcntr |= DISPPLANE_BGRX565;
3156                 break;
3157         case DRM_FORMAT_XRGB8888:
3158                 dspcntr |= DISPPLANE_BGRX888;
3159                 break;
3160         case DRM_FORMAT_XBGR8888:
3161                 dspcntr |= DISPPLANE_RGBX888;
3162                 break;
3163         case DRM_FORMAT_XRGB2101010:
3164                 dspcntr |= DISPPLANE_BGRX101010;
3165                 break;
3166         case DRM_FORMAT_XBGR2101010:
3167                 dspcntr |= DISPPLANE_RGBX101010;
3168                 break;
3169         default:
3170                 BUG();
3171         }
3172
3173         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3174                 dspcntr |= DISPPLANE_TILED;
3175
3176         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
3177                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3178
3179         intel_add_fb_offsets(&x, &y, plane_state, 0);
3180
3181         intel_crtc->dspaddr_offset =
3182                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3183
3184         if (rotation == DRM_ROTATE_180) {
3185                 dspcntr |= DISPPLANE_ROTATE_180;
3186
3187                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
3188                         x += (crtc_state->pipe_src_w - 1);
3189                         y += (crtc_state->pipe_src_h - 1);
3190                 }
3191         }
3192
3193         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3194
3195         intel_crtc->adjusted_x = x;
3196         intel_crtc->adjusted_y = y;
3197
3198         I915_WRITE(reg, dspcntr);
3199
3200         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3201         I915_WRITE(DSPSURF(plane),
3202                    intel_fb_gtt_offset(fb, rotation) +
3203                    intel_crtc->dspaddr_offset);
3204         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3205                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3206         } else {
3207                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3208                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3209         }
3210         POSTING_READ(reg);
3211 }
3212
3213 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3214                               uint64_t fb_modifier, uint32_t pixel_format)
3215 {
3216         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3217                 return 64;
3218         } else {
3219                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3220
3221                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3222         }
3223 }
3224
3225 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3226                         unsigned int rotation)
3227 {
3228         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3229         struct i915_ggtt_view view;
3230         struct i915_vma *vma;
3231
3232         intel_fill_fb_ggtt_view(&view, fb, rotation);
3233
3234         vma = i915_gem_object_to_ggtt(obj, &view);
3235         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3236                  view.type))
3237                 return -1;
3238
3239         return i915_ggtt_offset(vma);
3240 }
3241
3242 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3243 {
3244         struct drm_device *dev = intel_crtc->base.dev;
3245         struct drm_i915_private *dev_priv = to_i915(dev);
3246
3247         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3248         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3249         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3250 }
3251
3252 /*
3253  * This function detaches (aka. unbinds) unused scalers in hardware
3254  */
3255 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3256 {
3257         struct intel_crtc_scaler_state *scaler_state;
3258         int i;
3259
3260         scaler_state = &intel_crtc->config->scaler_state;
3261
3262         /* loop through and disable scalers that aren't in use */
3263         for (i = 0; i < intel_crtc->num_scalers; i++) {
3264                 if (!scaler_state->scalers[i].in_use)
3265                         skl_detach_scaler(intel_crtc, i);
3266         }
3267 }
3268
3269 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3270                      unsigned int rotation)
3271 {
3272         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3273         u32 stride = intel_fb_pitch(fb, plane, rotation);
3274
3275         /*
3276          * The stride is either expressed as a multiple of 64 bytes chunks for
3277          * linear buffers or in number of tiles for tiled buffers.
3278          */
3279         if (intel_rotation_90_or_270(rotation)) {
3280                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3281
3282                 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3283         } else {
3284                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3285                                                     fb->pixel_format);
3286         }
3287
3288         return stride;
3289 }
3290
3291 u32 skl_plane_ctl_format(uint32_t pixel_format)
3292 {
3293         switch (pixel_format) {
3294         case DRM_FORMAT_C8:
3295                 return PLANE_CTL_FORMAT_INDEXED;
3296         case DRM_FORMAT_RGB565:
3297                 return PLANE_CTL_FORMAT_RGB_565;
3298         case DRM_FORMAT_XBGR8888:
3299                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3300         case DRM_FORMAT_XRGB8888:
3301                 return PLANE_CTL_FORMAT_XRGB_8888;
3302         /*
3303          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3304          * to be already pre-multiplied. We need to add a knob (or a different
3305          * DRM_FORMAT) for user-space to configure that.
3306          */
3307         case DRM_FORMAT_ABGR8888:
3308                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3309                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3310         case DRM_FORMAT_ARGB8888:
3311                 return PLANE_CTL_FORMAT_XRGB_8888 |
3312                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3313         case DRM_FORMAT_XRGB2101010:
3314                 return PLANE_CTL_FORMAT_XRGB_2101010;
3315         case DRM_FORMAT_XBGR2101010:
3316                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3317         case DRM_FORMAT_YUYV:
3318                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3319         case DRM_FORMAT_YVYU:
3320                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3321         case DRM_FORMAT_UYVY:
3322                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3323         case DRM_FORMAT_VYUY:
3324                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3325         default:
3326                 MISSING_CASE(pixel_format);
3327         }
3328
3329         return 0;
3330 }
3331
3332 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3333 {
3334         switch (fb_modifier) {
3335         case DRM_FORMAT_MOD_NONE:
3336                 break;
3337         case I915_FORMAT_MOD_X_TILED:
3338                 return PLANE_CTL_TILED_X;
3339         case I915_FORMAT_MOD_Y_TILED:
3340                 return PLANE_CTL_TILED_Y;
3341         case I915_FORMAT_MOD_Yf_TILED:
3342                 return PLANE_CTL_TILED_YF;
3343         default:
3344                 MISSING_CASE(fb_modifier);
3345         }
3346
3347         return 0;
3348 }
3349
3350 u32 skl_plane_ctl_rotation(unsigned int rotation)
3351 {
3352         switch (rotation) {
3353         case DRM_ROTATE_0:
3354                 break;
3355         /*
3356          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3357          * while i915 HW rotation is clockwise, thats why this swapping.
3358          */
3359         case DRM_ROTATE_90:
3360                 return PLANE_CTL_ROTATE_270;
3361         case DRM_ROTATE_180:
3362                 return PLANE_CTL_ROTATE_180;
3363         case DRM_ROTATE_270:
3364                 return PLANE_CTL_ROTATE_90;
3365         default:
3366                 MISSING_CASE(rotation);
3367         }
3368
3369         return 0;
3370 }
3371
3372 static void skylake_update_primary_plane(struct drm_plane *plane,
3373                                          const struct intel_crtc_state *crtc_state,
3374                                          const struct intel_plane_state *plane_state)
3375 {
3376         struct drm_device *dev = plane->dev;
3377         struct drm_i915_private *dev_priv = to_i915(dev);
3378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3379         struct drm_framebuffer *fb = plane_state->base.fb;
3380         const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
3381         int pipe = intel_crtc->pipe;
3382         u32 plane_ctl;
3383         unsigned int rotation = plane_state->base.rotation;
3384         u32 stride = skl_plane_stride(fb, 0, rotation);
3385         u32 surf_addr = plane_state->main.offset;
3386         int scaler_id = plane_state->scaler_id;
3387         int src_x = plane_state->main.x;
3388         int src_y = plane_state->main.y;
3389         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3390         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3391         int dst_x = plane_state->base.dst.x1;
3392         int dst_y = plane_state->base.dst.y1;
3393         int dst_w = drm_rect_width(&plane_state->base.dst);
3394         int dst_h = drm_rect_height(&plane_state->base.dst);
3395
3396         plane_ctl = PLANE_CTL_ENABLE |
3397                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3398                     PLANE_CTL_PIPE_CSC_ENABLE;
3399
3400         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3401         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3402         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3403         plane_ctl |= skl_plane_ctl_rotation(rotation);
3404
3405         /* Sizes are 0 based */
3406         src_w--;
3407         src_h--;
3408         dst_w--;
3409         dst_h--;
3410
3411         intel_crtc->dspaddr_offset = surf_addr;
3412
3413         intel_crtc->adjusted_x = src_x;
3414         intel_crtc->adjusted_y = src_y;
3415
3416         if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
3417                 skl_write_plane_wm(intel_crtc, wm, 0);
3418
3419         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3420         I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3421         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3422         I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3423
3424         if (scaler_id >= 0) {
3425                 uint32_t ps_ctrl = 0;
3426
3427                 WARN_ON(!dst_w || !dst_h);
3428                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3429                         crtc_state->scaler_state.scalers[scaler_id].mode;
3430                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3431                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3432                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3433                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3434                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3435         } else {
3436                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3437         }
3438
3439         I915_WRITE(PLANE_SURF(pipe, 0),
3440                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
3441
3442         POSTING_READ(PLANE_SURF(pipe, 0));
3443 }
3444
3445 static void skylake_disable_primary_plane(struct drm_plane *primary,
3446                                           struct drm_crtc *crtc)
3447 {
3448         struct drm_device *dev = crtc->dev;
3449         struct drm_i915_private *dev_priv = to_i915(dev);
3450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3451         int pipe = intel_crtc->pipe;
3452
3453         /*
3454          * We only populate skl_results on watermark updates, and if the
3455          * plane's visiblity isn't actually changing neither is its watermarks.
3456          */
3457         if (!crtc->primary->state->visible)
3458                 skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0);
3459
3460         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3461         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3462         POSTING_READ(PLANE_SURF(pipe, 0));
3463 }
3464
3465 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3466 static int
3467 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3468                            int x, int y, enum mode_set_atomic state)
3469 {
3470         /* Support for kgdboc is disabled, this needs a major rework. */
3471         DRM_ERROR("legacy panic handler not supported any more.\n");
3472
3473         return -ENODEV;
3474 }
3475
3476 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3477 {
3478         struct intel_crtc *crtc;
3479
3480         for_each_intel_crtc(&dev_priv->drm, crtc)
3481                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3482 }
3483
3484 static void intel_update_primary_planes(struct drm_device *dev)
3485 {
3486         struct drm_crtc *crtc;
3487
3488         for_each_crtc(dev, crtc) {
3489                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3490                 struct intel_plane_state *plane_state =
3491                         to_intel_plane_state(plane->base.state);
3492
3493                 if (plane_state->base.visible)
3494                         plane->update_plane(&plane->base,
3495                                             to_intel_crtc_state(crtc->state),
3496                                             plane_state);
3497         }
3498 }
3499
3500 static int
3501 __intel_display_resume(struct drm_device *dev,
3502                        struct drm_atomic_state *state)
3503 {
3504         struct drm_crtc_state *crtc_state;
3505         struct drm_crtc *crtc;
3506         int i, ret;
3507
3508         intel_modeset_setup_hw_state(dev);
3509         i915_redisable_vga(dev);
3510
3511         if (!state)
3512                 return 0;
3513
3514         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3515                 /*
3516                  * Force recalculation even if we restore
3517                  * current state. With fast modeset this may not result
3518                  * in a modeset when the state is compatible.
3519                  */
3520                 crtc_state->mode_changed = true;
3521         }
3522
3523         /* ignore any reset values/BIOS leftovers in the WM registers */
3524         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3525
3526         ret = drm_atomic_commit(state);
3527
3528         WARN_ON(ret == -EDEADLK);
3529         return ret;
3530 }
3531
3532 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3533 {
3534         return intel_has_gpu_reset(dev_priv) &&
3535                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3536 }
3537
3538 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3539 {
3540         struct drm_device *dev = &dev_priv->drm;
3541         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3542         struct drm_atomic_state *state;
3543         int ret;
3544
3545         /*
3546          * Need mode_config.mutex so that we don't
3547          * trample ongoing ->detect() and whatnot.
3548          */
3549         mutex_lock(&dev->mode_config.mutex);
3550         drm_modeset_acquire_init(ctx, 0);
3551         while (1) {
3552                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3553                 if (ret != -EDEADLK)
3554                         break;
3555
3556                 drm_modeset_backoff(ctx);
3557         }
3558
3559         /* reset doesn't touch the display, but flips might get nuked anyway, */
3560         if (!i915.force_reset_modeset_test &&
3561             !gpu_reset_clobbers_display(dev_priv))
3562                 return;
3563
3564         /*
3565          * Disabling the crtcs gracefully seems nicer. Also the
3566          * g33 docs say we should at least disable all the planes.
3567          */
3568         state = drm_atomic_helper_duplicate_state(dev, ctx);
3569         if (IS_ERR(state)) {
3570                 ret = PTR_ERR(state);
3571                 state = NULL;
3572                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3573                 goto err;
3574         }
3575
3576         ret = drm_atomic_helper_disable_all(dev, ctx);
3577         if (ret) {
3578                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3579                 goto err;
3580         }
3581
3582         dev_priv->modeset_restore_state = state;
3583         state->acquire_ctx = ctx;
3584         return;
3585
3586 err:
3587         drm_atomic_state_free(state);
3588 }
3589
3590 void intel_finish_reset(struct drm_i915_private *dev_priv)
3591 {
3592         struct drm_device *dev = &dev_priv->drm;
3593         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3594         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3595         int ret;
3596
3597         /*
3598          * Flips in the rings will be nuked by the reset,
3599          * so complete all pending flips so that user space
3600          * will get its events and not get stuck.
3601          */
3602         intel_complete_page_flips(dev_priv);
3603
3604         dev_priv->modeset_restore_state = NULL;
3605
3606         dev_priv->modeset_restore_state = NULL;
3607
3608         /* reset doesn't touch the display */
3609         if (!gpu_reset_clobbers_display(dev_priv)) {
3610                 if (!state) {
3611                         /*
3612                          * Flips in the rings have been nuked by the reset,
3613                          * so update the base address of all primary
3614                          * planes to the the last fb to make sure we're
3615                          * showing the correct fb after a reset.
3616                          *
3617                          * FIXME: Atomic will make this obsolete since we won't schedule
3618                          * CS-based flips (which might get lost in gpu resets) any more.
3619                          */
3620                         intel_update_primary_planes(dev);
3621                 } else {
3622                         ret = __intel_display_resume(dev, state);
3623                         if (ret)
3624                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3625                 }
3626         } else {
3627                 /*
3628                  * The display has been reset as well,
3629                  * so need a full re-initialization.
3630                  */
3631                 intel_runtime_pm_disable_interrupts(dev_priv);
3632                 intel_runtime_pm_enable_interrupts(dev_priv);
3633
3634                 intel_pps_unlock_regs_wa(dev_priv);
3635                 intel_modeset_init_hw(dev);
3636
3637                 spin_lock_irq(&dev_priv->irq_lock);
3638                 if (dev_priv->display.hpd_irq_setup)
3639                         dev_priv->display.hpd_irq_setup(dev_priv);
3640                 spin_unlock_irq(&dev_priv->irq_lock);
3641
3642                 ret = __intel_display_resume(dev, state);
3643                 if (ret)
3644                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3645
3646                 intel_hpd_init(dev_priv);
3647         }
3648
3649         drm_modeset_drop_locks(ctx);
3650         drm_modeset_acquire_fini(ctx);
3651         mutex_unlock(&dev->mode_config.mutex);
3652 }
3653
3654 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3655 {
3656         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3657
3658         if (i915_reset_in_progress(error))
3659                 return true;
3660
3661         if (crtc->reset_count != i915_reset_count(error))
3662                 return true;
3663
3664         return false;
3665 }
3666
3667 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3668 {
3669         struct drm_device *dev = crtc->dev;
3670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3671         bool pending;
3672
3673         if (abort_flip_on_reset(intel_crtc))
3674                 return false;
3675
3676         spin_lock_irq(&dev->event_lock);
3677         pending = to_intel_crtc(crtc)->flip_work != NULL;
3678         spin_unlock_irq(&dev->event_lock);
3679
3680         return pending;
3681 }
3682
3683 static void intel_update_pipe_config(struct intel_crtc *crtc,
3684                                      struct intel_crtc_state *old_crtc_state)
3685 {
3686         struct drm_device *dev = crtc->base.dev;
3687         struct drm_i915_private *dev_priv = to_i915(dev);
3688         struct intel_crtc_state *pipe_config =
3689                 to_intel_crtc_state(crtc->base.state);
3690
3691         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3692         crtc->base.mode = crtc->base.state->mode;
3693
3694         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3695                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3696                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3697
3698         /*
3699          * Update pipe size and adjust fitter if needed: the reason for this is
3700          * that in compute_mode_changes we check the native mode (not the pfit
3701          * mode) to see if we can flip rather than do a full mode set. In the
3702          * fastboot case, we'll flip, but if we don't update the pipesrc and
3703          * pfit state, we'll end up with a big fb scanned out into the wrong
3704          * sized surface.
3705          */
3706
3707         I915_WRITE(PIPESRC(crtc->pipe),
3708                    ((pipe_config->pipe_src_w - 1) << 16) |
3709                    (pipe_config->pipe_src_h - 1));
3710
3711         /* on skylake this is done by detaching scalers */
3712         if (INTEL_INFO(dev)->gen >= 9) {
3713                 skl_detach_scalers(crtc);
3714
3715                 if (pipe_config->pch_pfit.enabled)
3716                         skylake_pfit_enable(crtc);
3717         } else if (HAS_PCH_SPLIT(dev)) {
3718                 if (pipe_config->pch_pfit.enabled)
3719                         ironlake_pfit_enable(crtc);
3720                 else if (old_crtc_state->pch_pfit.enabled)
3721                         ironlake_pfit_disable(crtc, true);
3722         }
3723 }
3724
3725 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3726 {
3727         struct drm_device *dev = crtc->dev;
3728         struct drm_i915_private *dev_priv = to_i915(dev);
3729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3730         int pipe = intel_crtc->pipe;
3731         i915_reg_t reg;
3732         u32 temp;
3733
3734         /* enable normal train */
3735         reg = FDI_TX_CTL(pipe);
3736         temp = I915_READ(reg);
3737         if (IS_IVYBRIDGE(dev)) {
3738                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3739                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3740         } else {
3741                 temp &= ~FDI_LINK_TRAIN_NONE;
3742                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3743         }
3744         I915_WRITE(reg, temp);
3745
3746         reg = FDI_RX_CTL(pipe);
3747         temp = I915_READ(reg);
3748         if (HAS_PCH_CPT(dev)) {
3749                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3750                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3751         } else {
3752                 temp &= ~FDI_LINK_TRAIN_NONE;
3753                 temp |= FDI_LINK_TRAIN_NONE;
3754         }
3755         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3756
3757         /* wait one idle pattern time */
3758         POSTING_READ(reg);
3759         udelay(1000);
3760
3761         /* IVB wants error correction enabled */
3762         if (IS_IVYBRIDGE(dev))
3763                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3764                            FDI_FE_ERRC_ENABLE);
3765 }
3766
3767 /* The FDI link training functions for ILK/Ibexpeak. */
3768 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3769 {
3770         struct drm_device *dev = crtc->dev;
3771         struct drm_i915_private *dev_priv = to_i915(dev);
3772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3773         int pipe = intel_crtc->pipe;
3774         i915_reg_t reg;
3775         u32 temp, tries;
3776
3777         /* FDI needs bits from pipe first */
3778         assert_pipe_enabled(dev_priv, pipe);
3779
3780         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3781            for train result */
3782         reg = FDI_RX_IMR(pipe);
3783         temp = I915_READ(reg);
3784         temp &= ~FDI_RX_SYMBOL_LOCK;
3785         temp &= ~FDI_RX_BIT_LOCK;
3786         I915_WRITE(reg, temp);
3787         I915_READ(reg);
3788         udelay(150);
3789
3790         /* enable CPU FDI TX and PCH FDI RX */
3791         reg = FDI_TX_CTL(pipe);
3792         temp = I915_READ(reg);
3793         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3794         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3795         temp &= ~FDI_LINK_TRAIN_NONE;
3796         temp |= FDI_LINK_TRAIN_PATTERN_1;
3797         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3798
3799         reg = FDI_RX_CTL(pipe);
3800         temp = I915_READ(reg);
3801         temp &= ~FDI_LINK_TRAIN_NONE;
3802         temp |= FDI_LINK_TRAIN_PATTERN_1;
3803         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3804
3805         POSTING_READ(reg);
3806         udelay(150);
3807
3808         /* Ironlake workaround, enable clock pointer after FDI enable*/
3809         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3810         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3811                    FDI_RX_PHASE_SYNC_POINTER_EN);
3812
3813         reg = FDI_RX_IIR(pipe);
3814         for (tries = 0; tries < 5; tries++) {
3815                 temp = I915_READ(reg);
3816                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3817
3818                 if ((temp & FDI_RX_BIT_LOCK)) {
3819                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3820                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3821                         break;
3822                 }
3823         }
3824         if (tries == 5)
3825                 DRM_ERROR("FDI train 1 fail!\n");
3826
3827         /* Train 2 */
3828         reg = FDI_TX_CTL(pipe);
3829         temp = I915_READ(reg);
3830         temp &= ~FDI_LINK_TRAIN_NONE;
3831         temp |= FDI_LINK_TRAIN_PATTERN_2;
3832         I915_WRITE(reg, temp);
3833
3834         reg = FDI_RX_CTL(pipe);
3835         temp = I915_READ(reg);
3836         temp &= ~FDI_LINK_TRAIN_NONE;
3837         temp |= FDI_LINK_TRAIN_PATTERN_2;
3838         I915_WRITE(reg, temp);
3839
3840         POSTING_READ(reg);
3841         udelay(150);
3842
3843         reg = FDI_RX_IIR(pipe);
3844         for (tries = 0; tries < 5; tries++) {
3845                 temp = I915_READ(reg);
3846                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3847
3848                 if (temp & FDI_RX_SYMBOL_LOCK) {
3849                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3850                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3851                         break;
3852                 }
3853         }
3854         if (tries == 5)
3855                 DRM_ERROR("FDI train 2 fail!\n");
3856
3857         DRM_DEBUG_KMS("FDI train done\n");
3858
3859 }
3860
3861 static const int snb_b_fdi_train_param[] = {
3862         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3863         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3864         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3865         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3866 };
3867
3868 /* The FDI link training functions for SNB/Cougarpoint. */
3869 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3870 {
3871         struct drm_device *dev = crtc->dev;
3872         struct drm_i915_private *dev_priv = to_i915(dev);
3873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3874         int pipe = intel_crtc->pipe;
3875         i915_reg_t reg;
3876         u32 temp, i, retry;
3877
3878         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3879            for train result */
3880         reg = FDI_RX_IMR(pipe);
3881         temp = I915_READ(reg);
3882         temp &= ~FDI_RX_SYMBOL_LOCK;
3883         temp &= ~FDI_RX_BIT_LOCK;
3884         I915_WRITE(reg, temp);
3885
3886         POSTING_READ(reg);
3887         udelay(150);
3888
3889         /* enable CPU FDI TX and PCH FDI RX */
3890         reg = FDI_TX_CTL(pipe);
3891         temp = I915_READ(reg);
3892         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3893         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3894         temp &= ~FDI_LINK_TRAIN_NONE;
3895         temp |= FDI_LINK_TRAIN_PATTERN_1;
3896         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3897         /* SNB-B */
3898         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3899         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3900
3901         I915_WRITE(FDI_RX_MISC(pipe),
3902                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3903
3904         reg = FDI_RX_CTL(pipe);
3905         temp = I915_READ(reg);
3906         if (HAS_PCH_CPT(dev)) {
3907                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3908                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3909         } else {
3910                 temp &= ~FDI_LINK_TRAIN_NONE;
3911                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3912         }
3913         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3914
3915         POSTING_READ(reg);
3916         udelay(150);
3917
3918         for (i = 0; i < 4; i++) {
3919                 reg = FDI_TX_CTL(pipe);
3920                 temp = I915_READ(reg);
3921                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3922                 temp |= snb_b_fdi_train_param[i];
3923                 I915_WRITE(reg, temp);
3924
3925                 POSTING_READ(reg);
3926                 udelay(500);
3927
3928                 for (retry = 0; retry < 5; retry++) {
3929                         reg = FDI_RX_IIR(pipe);
3930                         temp = I915_READ(reg);
3931                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3932                         if (temp & FDI_RX_BIT_LOCK) {
3933                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3934                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3935                                 break;
3936                         }
3937                         udelay(50);
3938                 }
3939                 if (retry < 5)
3940                         break;
3941         }
3942         if (i == 4)
3943                 DRM_ERROR("FDI train 1 fail!\n");
3944
3945         /* Train 2 */
3946         reg = FDI_TX_CTL(pipe);
3947         temp = I915_READ(reg);
3948         temp &= ~FDI_LINK_TRAIN_NONE;
3949         temp |= FDI_LINK_TRAIN_PATTERN_2;
3950         if (IS_GEN6(dev)) {
3951                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3952                 /* SNB-B */
3953                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3954         }
3955         I915_WRITE(reg, temp);
3956
3957         reg = FDI_RX_CTL(pipe);
3958         temp = I915_READ(reg);
3959         if (HAS_PCH_CPT(dev)) {
3960                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3961                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3962         } else {
3963                 temp &= ~FDI_LINK_TRAIN_NONE;
3964                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3965         }
3966         I915_WRITE(reg, temp);
3967
3968         POSTING_READ(reg);
3969         udelay(150);
3970
3971         for (i = 0; i < 4; i++) {
3972                 reg = FDI_TX_CTL(pipe);
3973                 temp = I915_READ(reg);
3974                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3975                 temp |= snb_b_fdi_train_param[i];
3976                 I915_WRITE(reg, temp);
3977
3978                 POSTING_READ(reg);
3979                 udelay(500);
3980
3981                 for (retry = 0; retry < 5; retry++) {
3982                         reg = FDI_RX_IIR(pipe);
3983                         temp = I915_READ(reg);
3984                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3985                         if (temp & FDI_RX_SYMBOL_LOCK) {
3986                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3987                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3988                                 break;
3989                         }
3990                         udelay(50);
3991                 }
3992                 if (retry < 5)
3993                         break;
3994         }
3995         if (i == 4)
3996                 DRM_ERROR("FDI train 2 fail!\n");
3997
3998         DRM_DEBUG_KMS("FDI train done.\n");
3999 }
4000
4001 /* Manual link training for Ivy Bridge A0 parts */
4002 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
4003 {
4004         struct drm_device *dev = crtc->dev;
4005         struct drm_i915_private *dev_priv = to_i915(dev);
4006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4007         int pipe = intel_crtc->pipe;
4008         i915_reg_t reg;
4009         u32 temp, i, j;
4010
4011         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4012            for train result */
4013         reg = FDI_RX_IMR(pipe);
4014         temp = I915_READ(reg);
4015         temp &= ~FDI_RX_SYMBOL_LOCK;
4016         temp &= ~FDI_RX_BIT_LOCK;
4017         I915_WRITE(reg, temp);
4018
4019         POSTING_READ(reg);
4020         udelay(150);
4021
4022         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4023                       I915_READ(FDI_RX_IIR(pipe)));
4024
4025         /* Try each vswing and preemphasis setting twice before moving on */
4026         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4027                 /* disable first in case we need to retry */
4028                 reg = FDI_TX_CTL(pipe);
4029                 temp = I915_READ(reg);
4030                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4031                 temp &= ~FDI_TX_ENABLE;
4032                 I915_WRITE(reg, temp);
4033
4034                 reg = FDI_RX_CTL(pipe);
4035                 temp = I915_READ(reg);
4036                 temp &= ~FDI_LINK_TRAIN_AUTO;
4037                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4038                 temp &= ~FDI_RX_ENABLE;
4039                 I915_WRITE(reg, temp);
4040
4041                 /* enable CPU FDI TX and PCH FDI RX */
4042                 reg = FDI_TX_CTL(pipe);
4043                 temp = I915_READ(reg);
4044                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4045                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4046                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4047                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4048                 temp |= snb_b_fdi_train_param[j/2];
4049                 temp |= FDI_COMPOSITE_SYNC;
4050                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4051
4052                 I915_WRITE(FDI_RX_MISC(pipe),
4053                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4054
4055                 reg = FDI_RX_CTL(pipe);
4056                 temp = I915_READ(reg);
4057                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4058                 temp |= FDI_COMPOSITE_SYNC;
4059                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4060
4061                 POSTING_READ(reg);
4062                 udelay(1); /* should be 0.5us */
4063
4064                 for (i = 0; i < 4; i++) {
4065                         reg = FDI_RX_IIR(pipe);
4066                         temp = I915_READ(reg);
4067                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4068
4069                         if (temp & FDI_RX_BIT_LOCK ||
4070                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4071                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4072                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4073                                               i);
4074                                 break;
4075                         }
4076                         udelay(1); /* should be 0.5us */
4077                 }
4078                 if (i == 4) {
4079                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4080                         continue;
4081                 }
4082
4083                 /* Train 2 */
4084                 reg = FDI_TX_CTL(pipe);
4085                 temp = I915_READ(reg);
4086                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4087                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4088                 I915_WRITE(reg, temp);
4089
4090                 reg = FDI_RX_CTL(pipe);
4091                 temp = I915_READ(reg);
4092                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4093                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4094                 I915_WRITE(reg, temp);
4095
4096                 POSTING_READ(reg);
4097                 udelay(2); /* should be 1.5us */
4098
4099                 for (i = 0; i < 4; i++) {
4100                         reg = FDI_RX_IIR(pipe);
4101                         temp = I915_READ(reg);
4102                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4103
4104                         if (temp & FDI_RX_SYMBOL_LOCK ||
4105                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4106                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4107                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4108                                               i);
4109                                 goto train_done;
4110                         }
4111                         udelay(2); /* should be 1.5us */
4112                 }
4113                 if (i == 4)
4114                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4115         }
4116
4117 train_done:
4118         DRM_DEBUG_KMS("FDI train done.\n");
4119 }
4120
4121 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4122 {
4123         struct drm_device *dev = intel_crtc->base.dev;
4124         struct drm_i915_private *dev_priv = to_i915(dev);
4125         int pipe = intel_crtc->pipe;
4126         i915_reg_t reg;
4127         u32 temp;
4128
4129         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4130         reg = FDI_RX_CTL(pipe);
4131         temp = I915_READ(reg);
4132         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4133         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4134         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4135         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4136
4137         POSTING_READ(reg);
4138         udelay(200);
4139
4140         /* Switch from Rawclk to PCDclk */
4141         temp = I915_READ(reg);
4142         I915_WRITE(reg, temp | FDI_PCDCLK);
4143
4144         POSTING_READ(reg);
4145         udelay(200);
4146
4147         /* Enable CPU FDI TX PLL, always on for Ironlake */
4148         reg = FDI_TX_CTL(pipe);
4149         temp = I915_READ(reg);
4150         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4151                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4152
4153                 POSTING_READ(reg);
4154                 udelay(100);
4155         }
4156 }
4157
4158 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4159 {
4160         struct drm_device *dev = intel_crtc->base.dev;
4161         struct drm_i915_private *dev_priv = to_i915(dev);
4162         int pipe = intel_crtc->pipe;
4163         i915_reg_t reg;
4164         u32 temp;
4165
4166         /* Switch from PCDclk to Rawclk */
4167         reg = FDI_RX_CTL(pipe);
4168         temp = I915_READ(reg);
4169         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4170
4171         /* Disable CPU FDI TX PLL */
4172         reg = FDI_TX_CTL(pipe);
4173         temp = I915_READ(reg);
4174         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4175
4176         POSTING_READ(reg);
4177         udelay(100);
4178
4179         reg = FDI_RX_CTL(pipe);
4180         temp = I915_READ(reg);
4181         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4182
4183         /* Wait for the clocks to turn off. */
4184         POSTING_READ(reg);
4185         udelay(100);
4186 }
4187
4188 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4189 {
4190         struct drm_device *dev = crtc->dev;
4191         struct drm_i915_private *dev_priv = to_i915(dev);
4192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4193         int pipe = intel_crtc->pipe;
4194         i915_reg_t reg;
4195         u32 temp;
4196
4197         /* disable CPU FDI tx and PCH FDI rx */
4198         reg = FDI_TX_CTL(pipe);
4199         temp = I915_READ(reg);
4200         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4201         POSTING_READ(reg);
4202
4203         reg = FDI_RX_CTL(pipe);
4204         temp = I915_READ(reg);
4205         temp &= ~(0x7 << 16);
4206         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4207         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4208
4209         POSTING_READ(reg);
4210         udelay(100);
4211
4212         /* Ironlake workaround, disable clock pointer after downing FDI */
4213         if (HAS_PCH_IBX(dev))
4214                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4215
4216         /* still set train pattern 1 */
4217         reg = FDI_TX_CTL(pipe);
4218         temp = I915_READ(reg);
4219         temp &= ~FDI_LINK_TRAIN_NONE;
4220         temp |= FDI_LINK_TRAIN_PATTERN_1;
4221         I915_WRITE(reg, temp);
4222
4223         reg = FDI_RX_CTL(pipe);
4224         temp = I915_READ(reg);
4225         if (HAS_PCH_CPT(dev)) {
4226                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4227                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4228         } else {
4229                 temp &= ~FDI_LINK_TRAIN_NONE;
4230                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4231         }
4232         /* BPC in FDI rx is consistent with that in PIPECONF */
4233         temp &= ~(0x07 << 16);
4234         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4235         I915_WRITE(reg, temp);
4236
4237         POSTING_READ(reg);
4238         udelay(100);
4239 }
4240
4241 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4242 {
4243         struct intel_crtc *crtc;
4244
4245         /* Note that we don't need to be called with mode_config.lock here
4246          * as our list of CRTC objects is static for the lifetime of the
4247          * device and so cannot disappear as we iterate. Similarly, we can
4248          * happily treat the predicates as racy, atomic checks as userspace
4249          * cannot claim and pin a new fb without at least acquring the
4250          * struct_mutex and so serialising with us.
4251          */
4252         for_each_intel_crtc(dev, crtc) {
4253                 if (atomic_read(&crtc->unpin_work_count) == 0)
4254                         continue;
4255
4256                 if (crtc->flip_work)
4257                         intel_wait_for_vblank(dev, crtc->pipe);
4258
4259                 return true;
4260         }
4261
4262         return false;
4263 }
4264
4265 static void page_flip_completed(struct intel_crtc *intel_crtc)
4266 {
4267         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4268         struct intel_flip_work *work = intel_crtc->flip_work;
4269
4270         intel_crtc->flip_work = NULL;
4271
4272         if (work->event)
4273                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4274
4275         drm_crtc_vblank_put(&intel_crtc->base);
4276
4277         wake_up_all(&dev_priv->pending_flip_queue);
4278         queue_work(dev_priv->wq, &work->unpin_work);
4279
4280         trace_i915_flip_complete(intel_crtc->plane,
4281                                  work->pending_flip_obj);
4282 }
4283
4284 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4285 {
4286         struct drm_device *dev = crtc->dev;
4287         struct drm_i915_private *dev_priv = to_i915(dev);
4288         long ret;
4289
4290         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4291
4292         ret = wait_event_interruptible_timeout(
4293                                         dev_priv->pending_flip_queue,
4294                                         !intel_crtc_has_pending_flip(crtc),
4295                                         60*HZ);
4296
4297         if (ret < 0)
4298                 return ret;
4299
4300         if (ret == 0) {
4301                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4302                 struct intel_flip_work *work;
4303
4304                 spin_lock_irq(&dev->event_lock);
4305                 work = intel_crtc->flip_work;
4306                 if (work && !is_mmio_work(work)) {
4307                         WARN_ONCE(1, "Removing stuck page flip\n");
4308                         page_flip_completed(intel_crtc);
4309                 }
4310                 spin_unlock_irq(&dev->event_lock);
4311         }
4312
4313         return 0;
4314 }
4315
4316 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4317 {
4318         u32 temp;
4319
4320         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4321
4322         mutex_lock(&dev_priv->sb_lock);
4323
4324         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4325         temp |= SBI_SSCCTL_DISABLE;
4326         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4327
4328         mutex_unlock(&dev_priv->sb_lock);
4329 }
4330
4331 /* Program iCLKIP clock to the desired frequency */
4332 static void lpt_program_iclkip(struct drm_crtc *crtc)
4333 {
4334         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4335         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4336         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4337         u32 temp;
4338
4339         lpt_disable_iclkip(dev_priv);
4340
4341         /* The iCLK virtual clock root frequency is in MHz,
4342          * but the adjusted_mode->crtc_clock in in KHz. To get the
4343          * divisors, it is necessary to divide one by another, so we
4344          * convert the virtual clock precision to KHz here for higher
4345          * precision.
4346          */
4347         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4348                 u32 iclk_virtual_root_freq = 172800 * 1000;
4349                 u32 iclk_pi_range = 64;
4350                 u32 desired_divisor;
4351
4352                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4353                                                     clock << auxdiv);
4354                 divsel = (desired_divisor / iclk_pi_range) - 2;
4355                 phaseinc = desired_divisor % iclk_pi_range;
4356
4357                 /*
4358                  * Near 20MHz is a corner case which is
4359                  * out of range for the 7-bit divisor
4360                  */
4361                 if (divsel <= 0x7f)
4362                         break;
4363         }
4364
4365         /* This should not happen with any sane values */
4366         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4367                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4368         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4369                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4370
4371         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4372                         clock,
4373                         auxdiv,
4374                         divsel,
4375                         phasedir,
4376                         phaseinc);
4377
4378         mutex_lock(&dev_priv->sb_lock);
4379
4380         /* Program SSCDIVINTPHASE6 */
4381         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4382         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4383         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4384         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4385         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4386         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4387         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4388         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4389
4390         /* Program SSCAUXDIV */
4391         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4392         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4393         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4394         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4395
4396         /* Enable modulator and associated divider */
4397         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4398         temp &= ~SBI_SSCCTL_DISABLE;
4399         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4400
4401         mutex_unlock(&dev_priv->sb_lock);
4402
4403         /* Wait for initialization time */
4404         udelay(24);
4405
4406         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4407 }
4408
4409 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4410 {
4411         u32 divsel, phaseinc, auxdiv;
4412         u32 iclk_virtual_root_freq = 172800 * 1000;
4413         u32 iclk_pi_range = 64;
4414         u32 desired_divisor;
4415         u32 temp;
4416
4417         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4418                 return 0;
4419
4420         mutex_lock(&dev_priv->sb_lock);
4421
4422         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4423         if (temp & SBI_SSCCTL_DISABLE) {
4424                 mutex_unlock(&dev_priv->sb_lock);
4425                 return 0;
4426         }
4427
4428         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4429         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4430                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4431         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4432                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4433
4434         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4435         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4436                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4437
4438         mutex_unlock(&dev_priv->sb_lock);
4439
4440         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4441
4442         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4443                                  desired_divisor << auxdiv);
4444 }
4445
4446 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4447                                                 enum pipe pch_transcoder)
4448 {
4449         struct drm_device *dev = crtc->base.dev;
4450         struct drm_i915_private *dev_priv = to_i915(dev);
4451         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4452
4453         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4454                    I915_READ(HTOTAL(cpu_transcoder)));
4455         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4456                    I915_READ(HBLANK(cpu_transcoder)));
4457         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4458                    I915_READ(HSYNC(cpu_transcoder)));
4459
4460         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4461                    I915_READ(VTOTAL(cpu_transcoder)));
4462         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4463                    I915_READ(VBLANK(cpu_transcoder)));
4464         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4465                    I915_READ(VSYNC(cpu_transcoder)));
4466         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4467                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4468 }
4469
4470 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4471 {
4472         struct drm_i915_private *dev_priv = to_i915(dev);
4473         uint32_t temp;
4474
4475         temp = I915_READ(SOUTH_CHICKEN1);
4476         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4477                 return;
4478
4479         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4480         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4481
4482         temp &= ~FDI_BC_BIFURCATION_SELECT;
4483         if (enable)
4484                 temp |= FDI_BC_BIFURCATION_SELECT;
4485
4486         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4487         I915_WRITE(SOUTH_CHICKEN1, temp);
4488         POSTING_READ(SOUTH_CHICKEN1);
4489 }
4490
4491 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4492 {
4493         struct drm_device *dev = intel_crtc->base.dev;
4494
4495         switch (intel_crtc->pipe) {
4496         case PIPE_A:
4497                 break;
4498         case PIPE_B:
4499                 if (intel_crtc->config->fdi_lanes > 2)
4500                         cpt_set_fdi_bc_bifurcation(dev, false);
4501                 else
4502                         cpt_set_fdi_bc_bifurcation(dev, true);
4503
4504                 break;
4505         case PIPE_C:
4506                 cpt_set_fdi_bc_bifurcation(dev, true);
4507
4508                 break;
4509         default:
4510                 BUG();
4511         }
4512 }
4513
4514 /* Return which DP Port should be selected for Transcoder DP control */
4515 static enum port
4516 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4517 {
4518         struct drm_device *dev = crtc->dev;
4519         struct intel_encoder *encoder;
4520
4521         for_each_encoder_on_crtc(dev, crtc, encoder) {
4522                 if (encoder->type == INTEL_OUTPUT_DP ||
4523                     encoder->type == INTEL_OUTPUT_EDP)
4524                         return enc_to_dig_port(&encoder->base)->port;
4525         }
4526
4527         return -1;
4528 }
4529
4530 /*
4531  * Enable PCH resources required for PCH ports:
4532  *   - PCH PLLs
4533  *   - FDI training & RX/TX
4534  *   - update transcoder timings
4535  *   - DP transcoding bits
4536  *   - transcoder
4537  */
4538 static void ironlake_pch_enable(struct drm_crtc *crtc)
4539 {
4540         struct drm_device *dev = crtc->dev;
4541         struct drm_i915_private *dev_priv = to_i915(dev);
4542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4543         int pipe = intel_crtc->pipe;
4544         u32 temp;
4545
4546         assert_pch_transcoder_disabled(dev_priv, pipe);
4547
4548         if (IS_IVYBRIDGE(dev))
4549                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4550
4551         /* Write the TU size bits before fdi link training, so that error
4552          * detection works. */
4553         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4554                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4555
4556         /* For PCH output, training FDI link */
4557         dev_priv->display.fdi_link_train(crtc);
4558
4559         /* We need to program the right clock selection before writing the pixel
4560          * mutliplier into the DPLL. */
4561         if (HAS_PCH_CPT(dev)) {
4562                 u32 sel;
4563
4564                 temp = I915_READ(PCH_DPLL_SEL);
4565                 temp |= TRANS_DPLL_ENABLE(pipe);
4566                 sel = TRANS_DPLLB_SEL(pipe);
4567                 if (intel_crtc->config->shared_dpll ==
4568                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4569                         temp |= sel;
4570                 else
4571                         temp &= ~sel;
4572                 I915_WRITE(PCH_DPLL_SEL, temp);
4573         }
4574
4575         /* XXX: pch pll's can be enabled any time before we enable the PCH
4576          * transcoder, and we actually should do this to not upset any PCH
4577          * transcoder that already use the clock when we share it.
4578          *
4579          * Note that enable_shared_dpll tries to do the right thing, but
4580          * get_shared_dpll unconditionally resets the pll - we need that to have
4581          * the right LVDS enable sequence. */
4582         intel_enable_shared_dpll(intel_crtc);
4583
4584         /* set transcoder timing, panel must allow it */
4585         assert_panel_unlocked(dev_priv, pipe);
4586         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4587
4588         intel_fdi_normal_train(crtc);
4589
4590         /* For PCH DP, enable TRANS_DP_CTL */
4591         if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4592                 const struct drm_display_mode *adjusted_mode =
4593                         &intel_crtc->config->base.adjusted_mode;
4594                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4595                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4596                 temp = I915_READ(reg);
4597                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4598                           TRANS_DP_SYNC_MASK |
4599                           TRANS_DP_BPC_MASK);
4600                 temp |= TRANS_DP_OUTPUT_ENABLE;
4601                 temp |= bpc << 9; /* same format but at 11:9 */
4602
4603                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4604                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4605                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4606                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4607
4608                 switch (intel_trans_dp_port_sel(crtc)) {
4609                 case PORT_B:
4610                         temp |= TRANS_DP_PORT_SEL_B;
4611                         break;
4612                 case PORT_C:
4613                         temp |= TRANS_DP_PORT_SEL_C;
4614                         break;
4615                 case PORT_D:
4616                         temp |= TRANS_DP_PORT_SEL_D;
4617                         break;
4618                 default:
4619                         BUG();
4620                 }
4621
4622                 I915_WRITE(reg, temp);
4623         }
4624
4625         ironlake_enable_pch_transcoder(dev_priv, pipe);
4626 }
4627
4628 static void lpt_pch_enable(struct drm_crtc *crtc)
4629 {
4630         struct drm_device *dev = crtc->dev;
4631         struct drm_i915_private *dev_priv = to_i915(dev);
4632         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4633         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4634
4635         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4636
4637         lpt_program_iclkip(crtc);
4638
4639         /* Set transcoder timing. */
4640         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4641
4642         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4643 }
4644
4645 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4646 {
4647         struct drm_i915_private *dev_priv = to_i915(dev);
4648         i915_reg_t dslreg = PIPEDSL(pipe);
4649         u32 temp;
4650
4651         temp = I915_READ(dslreg);
4652         udelay(500);
4653         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4654                 if (wait_for(I915_READ(dslreg) != temp, 5))
4655                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4656         }
4657 }
4658
4659 static int
4660 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4661                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4662                   int src_w, int src_h, int dst_w, int dst_h)
4663 {
4664         struct intel_crtc_scaler_state *scaler_state =
4665                 &crtc_state->scaler_state;
4666         struct intel_crtc *intel_crtc =
4667                 to_intel_crtc(crtc_state->base.crtc);
4668         int need_scaling;
4669
4670         need_scaling = intel_rotation_90_or_270(rotation) ?
4671                 (src_h != dst_w || src_w != dst_h):
4672                 (src_w != dst_w || src_h != dst_h);
4673
4674         /*
4675          * if plane is being disabled or scaler is no more required or force detach
4676          *  - free scaler binded to this plane/crtc
4677          *  - in order to do this, update crtc->scaler_usage
4678          *
4679          * Here scaler state in crtc_state is set free so that
4680          * scaler can be assigned to other user. Actual register
4681          * update to free the scaler is done in plane/panel-fit programming.
4682          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4683          */
4684         if (force_detach || !need_scaling) {
4685                 if (*scaler_id >= 0) {
4686                         scaler_state->scaler_users &= ~(1 << scaler_user);
4687                         scaler_state->scalers[*scaler_id].in_use = 0;
4688
4689                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4690                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4691                                 intel_crtc->pipe, scaler_user, *scaler_id,
4692                                 scaler_state->scaler_users);
4693                         *scaler_id = -1;
4694                 }
4695                 return 0;
4696         }
4697
4698         /* range checks */
4699         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4700                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4701
4702                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4703                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4704                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4705                         "size is out of scaler range\n",
4706                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4707                 return -EINVAL;
4708         }
4709
4710         /* mark this plane as a scaler user in crtc_state */
4711         scaler_state->scaler_users |= (1 << scaler_user);
4712         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4713                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4714                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4715                 scaler_state->scaler_users);
4716
4717         return 0;
4718 }
4719
4720 /**
4721  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4722  *
4723  * @state: crtc's scaler state
4724  *
4725  * Return
4726  *     0 - scaler_usage updated successfully
4727  *    error - requested scaling cannot be supported or other error condition
4728  */
4729 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4730 {
4731         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4732         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4733
4734         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4735                       intel_crtc->base.base.id, intel_crtc->base.name,
4736                       intel_crtc->pipe, SKL_CRTC_INDEX);
4737
4738         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4739                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4740                 state->pipe_src_w, state->pipe_src_h,
4741                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4742 }
4743
4744 /**
4745  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4746  *
4747  * @state: crtc's scaler state
4748  * @plane_state: atomic plane state to update
4749  *
4750  * Return
4751  *     0 - scaler_usage updated successfully
4752  *    error - requested scaling cannot be supported or other error condition
4753  */
4754 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4755                                    struct intel_plane_state *plane_state)
4756 {
4757
4758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4759         struct intel_plane *intel_plane =
4760                 to_intel_plane(plane_state->base.plane);
4761         struct drm_framebuffer *fb = plane_state->base.fb;
4762         int ret;
4763
4764         bool force_detach = !fb || !plane_state->base.visible;
4765
4766         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4767                       intel_plane->base.base.id, intel_plane->base.name,
4768                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4769
4770         ret = skl_update_scaler(crtc_state, force_detach,
4771                                 drm_plane_index(&intel_plane->base),
4772                                 &plane_state->scaler_id,
4773                                 plane_state->base.rotation,
4774                                 drm_rect_width(&plane_state->base.src) >> 16,
4775                                 drm_rect_height(&plane_state->base.src) >> 16,
4776                                 drm_rect_width(&plane_state->base.dst),
4777                                 drm_rect_height(&plane_state->base.dst));
4778
4779         if (ret || plane_state->scaler_id < 0)
4780                 return ret;
4781
4782         /* check colorkey */
4783         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4784                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4785                               intel_plane->base.base.id,
4786                               intel_plane->base.name);
4787                 return -EINVAL;
4788         }
4789
4790         /* Check src format */
4791         switch (fb->pixel_format) {
4792         case DRM_FORMAT_RGB565:
4793         case DRM_FORMAT_XBGR8888:
4794         case DRM_FORMAT_XRGB8888:
4795         case DRM_FORMAT_ABGR8888:
4796         case DRM_FORMAT_ARGB8888:
4797         case DRM_FORMAT_XRGB2101010:
4798         case DRM_FORMAT_XBGR2101010:
4799         case DRM_FORMAT_YUYV:
4800         case DRM_FORMAT_YVYU:
4801         case DRM_FORMAT_UYVY:
4802         case DRM_FORMAT_VYUY:
4803                 break;
4804         default:
4805                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4806                               intel_plane->base.base.id, intel_plane->base.name,
4807                               fb->base.id, fb->pixel_format);
4808                 return -EINVAL;
4809         }
4810
4811         return 0;
4812 }
4813
4814 static void skylake_scaler_disable(struct intel_crtc *crtc)
4815 {
4816         int i;
4817
4818         for (i = 0; i < crtc->num_scalers; i++)
4819                 skl_detach_scaler(crtc, i);
4820 }
4821
4822 static void skylake_pfit_enable(struct intel_crtc *crtc)
4823 {
4824         struct drm_device *dev = crtc->base.dev;
4825         struct drm_i915_private *dev_priv = to_i915(dev);
4826         int pipe = crtc->pipe;
4827         struct intel_crtc_scaler_state *scaler_state =
4828                 &crtc->config->scaler_state;
4829
4830         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4831
4832         if (crtc->config->pch_pfit.enabled) {
4833                 int id;
4834
4835                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4836                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4837                         return;
4838                 }
4839
4840                 id = scaler_state->scaler_id;
4841                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4842                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4843                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4844                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4845
4846                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4847         }
4848 }
4849
4850 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4851 {
4852         struct drm_device *dev = crtc->base.dev;
4853         struct drm_i915_private *dev_priv = to_i915(dev);
4854         int pipe = crtc->pipe;
4855
4856         if (crtc->config->pch_pfit.enabled) {
4857                 /* Force use of hard-coded filter coefficients
4858                  * as some pre-programmed values are broken,
4859                  * e.g. x201.
4860                  */
4861                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4862                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4863                                                  PF_PIPE_SEL_IVB(pipe));
4864                 else
4865                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4866                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4867                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4868         }
4869 }
4870
4871 void hsw_enable_ips(struct intel_crtc *crtc)
4872 {
4873         struct drm_device *dev = crtc->base.dev;
4874         struct drm_i915_private *dev_priv = to_i915(dev);
4875
4876         if (!crtc->config->ips_enabled)
4877                 return;
4878
4879         /*
4880          * We can only enable IPS after we enable a plane and wait for a vblank
4881          * This function is called from post_plane_update, which is run after
4882          * a vblank wait.
4883          */
4884
4885         assert_plane_enabled(dev_priv, crtc->plane);
4886         if (IS_BROADWELL(dev)) {
4887                 mutex_lock(&dev_priv->rps.hw_lock);
4888                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4889                 mutex_unlock(&dev_priv->rps.hw_lock);
4890                 /* Quoting Art Runyan: "its not safe to expect any particular
4891                  * value in IPS_CTL bit 31 after enabling IPS through the
4892                  * mailbox." Moreover, the mailbox may return a bogus state,
4893                  * so we need to just enable it and continue on.
4894                  */
4895         } else {
4896                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4897                 /* The bit only becomes 1 in the next vblank, so this wait here
4898                  * is essentially intel_wait_for_vblank. If we don't have this
4899                  * and don't wait for vblanks until the end of crtc_enable, then
4900                  * the HW state readout code will complain that the expected
4901                  * IPS_CTL value is not the one we read. */
4902                 if (intel_wait_for_register(dev_priv,
4903                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4904                                             50))
4905                         DRM_ERROR("Timed out waiting for IPS enable\n");
4906         }
4907 }
4908
4909 void hsw_disable_ips(struct intel_crtc *crtc)
4910 {
4911         struct drm_device *dev = crtc->base.dev;
4912         struct drm_i915_private *dev_priv = to_i915(dev);
4913
4914         if (!crtc->config->ips_enabled)
4915                 return;
4916
4917         assert_plane_enabled(dev_priv, crtc->plane);
4918         if (IS_BROADWELL(dev)) {
4919                 mutex_lock(&dev_priv->rps.hw_lock);
4920                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4921                 mutex_unlock(&dev_priv->rps.hw_lock);
4922                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4923                 if (intel_wait_for_register(dev_priv,
4924                                             IPS_CTL, IPS_ENABLE, 0,
4925                                             42))
4926                         DRM_ERROR("Timed out waiting for IPS disable\n");
4927         } else {
4928                 I915_WRITE(IPS_CTL, 0);
4929                 POSTING_READ(IPS_CTL);
4930         }
4931
4932         /* We need to wait for a vblank before we can disable the plane. */
4933         intel_wait_for_vblank(dev, crtc->pipe);
4934 }
4935
4936 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4937 {
4938         if (intel_crtc->overlay) {
4939                 struct drm_device *dev = intel_crtc->base.dev;
4940                 struct drm_i915_private *dev_priv = to_i915(dev);
4941
4942                 mutex_lock(&dev->struct_mutex);
4943                 dev_priv->mm.interruptible = false;
4944                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4945                 dev_priv->mm.interruptible = true;
4946                 mutex_unlock(&dev->struct_mutex);
4947         }
4948
4949         /* Let userspace switch the overlay on again. In most cases userspace
4950          * has to recompute where to put it anyway.
4951          */
4952 }
4953
4954 /**
4955  * intel_post_enable_primary - Perform operations after enabling primary plane
4956  * @crtc: the CRTC whose primary plane was just enabled
4957  *
4958  * Performs potentially sleeping operations that must be done after the primary
4959  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4960  * called due to an explicit primary plane update, or due to an implicit
4961  * re-enable that is caused when a sprite plane is updated to no longer
4962  * completely hide the primary plane.
4963  */
4964 static void
4965 intel_post_enable_primary(struct drm_crtc *crtc)
4966 {
4967         struct drm_device *dev = crtc->dev;
4968         struct drm_i915_private *dev_priv = to_i915(dev);
4969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4970         int pipe = intel_crtc->pipe;
4971
4972         /*
4973          * FIXME IPS should be fine as long as one plane is
4974          * enabled, but in practice it seems to have problems
4975          * when going from primary only to sprite only and vice
4976          * versa.
4977          */
4978         hsw_enable_ips(intel_crtc);
4979
4980         /*
4981          * Gen2 reports pipe underruns whenever all planes are disabled.
4982          * So don't enable underrun reporting before at least some planes
4983          * are enabled.
4984          * FIXME: Need to fix the logic to work when we turn off all planes
4985          * but leave the pipe running.
4986          */
4987         if (IS_GEN2(dev))
4988                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4989
4990         /* Underruns don't always raise interrupts, so check manually. */
4991         intel_check_cpu_fifo_underruns(dev_priv);
4992         intel_check_pch_fifo_underruns(dev_priv);
4993 }
4994
4995 /* FIXME move all this to pre_plane_update() with proper state tracking */
4996 static void
4997 intel_pre_disable_primary(struct drm_crtc *crtc)
4998 {
4999         struct drm_device *dev = crtc->dev;
5000         struct drm_i915_private *dev_priv = to_i915(dev);
5001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5002         int pipe = intel_crtc->pipe;
5003
5004         /*
5005          * Gen2 reports pipe underruns whenever all planes are disabled.
5006          * So diasble underrun reporting before all the planes get disabled.
5007          * FIXME: Need to fix the logic to work when we turn off all planes
5008          * but leave the pipe running.
5009          */
5010         if (IS_GEN2(dev))
5011                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5012
5013         /*
5014          * FIXME IPS should be fine as long as one plane is
5015          * enabled, but in practice it seems to have problems
5016          * when going from primary only to sprite only and vice
5017          * versa.
5018          */
5019         hsw_disable_ips(intel_crtc);
5020 }
5021
5022 /* FIXME get rid of this and use pre_plane_update */
5023 static void
5024 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5025 {
5026         struct drm_device *dev = crtc->dev;
5027         struct drm_i915_private *dev_priv = to_i915(dev);
5028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5029         int pipe = intel_crtc->pipe;
5030
5031         intel_pre_disable_primary(crtc);
5032
5033         /*
5034          * Vblank time updates from the shadow to live plane control register
5035          * are blocked if the memory self-refresh mode is active at that
5036          * moment. So to make sure the plane gets truly disabled, disable
5037          * first the self-refresh mode. The self-refresh enable bit in turn
5038          * will be checked/applied by the HW only at the next frame start
5039          * event which is after the vblank start event, so we need to have a
5040          * wait-for-vblank between disabling the plane and the pipe.
5041          */
5042         if (HAS_GMCH_DISPLAY(dev)) {
5043                 intel_set_memory_cxsr(dev_priv, false);
5044                 dev_priv->wm.vlv.cxsr = false;
5045                 intel_wait_for_vblank(dev, pipe);
5046         }
5047 }
5048
5049 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5050 {
5051         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5052         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5053         struct intel_crtc_state *pipe_config =
5054                 to_intel_crtc_state(crtc->base.state);
5055         struct drm_plane *primary = crtc->base.primary;
5056         struct drm_plane_state *old_pri_state =
5057                 drm_atomic_get_existing_plane_state(old_state, primary);
5058
5059         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5060
5061         crtc->wm.cxsr_allowed = true;
5062
5063         if (pipe_config->update_wm_post && pipe_config->base.active)
5064                 intel_update_watermarks(&crtc->base);
5065
5066         if (old_pri_state) {
5067                 struct intel_plane_state *primary_state =
5068                         to_intel_plane_state(primary->state);
5069                 struct intel_plane_state *old_primary_state =
5070                         to_intel_plane_state(old_pri_state);
5071
5072                 intel_fbc_post_update(crtc);
5073
5074                 if (primary_state->base.visible &&
5075                     (needs_modeset(&pipe_config->base) ||
5076                      !old_primary_state->base.visible))
5077                         intel_post_enable_primary(&crtc->base);
5078         }
5079 }
5080
5081 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5082 {
5083         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5084         struct drm_device *dev = crtc->base.dev;
5085         struct drm_i915_private *dev_priv = to_i915(dev);
5086         struct intel_crtc_state *pipe_config =
5087                 to_intel_crtc_state(crtc->base.state);
5088         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5089         struct drm_plane *primary = crtc->base.primary;
5090         struct drm_plane_state *old_pri_state =
5091                 drm_atomic_get_existing_plane_state(old_state, primary);
5092         bool modeset = needs_modeset(&pipe_config->base);
5093
5094         if (old_pri_state) {
5095                 struct intel_plane_state *primary_state =
5096                         to_intel_plane_state(primary->state);
5097                 struct intel_plane_state *old_primary_state =
5098                         to_intel_plane_state(old_pri_state);
5099
5100                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5101
5102                 if (old_primary_state->base.visible &&
5103                     (modeset || !primary_state->base.visible))
5104                         intel_pre_disable_primary(&crtc->base);
5105         }
5106
5107         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
5108                 crtc->wm.cxsr_allowed = false;
5109
5110                 /*
5111                  * Vblank time updates from the shadow to live plane control register
5112                  * are blocked if the memory self-refresh mode is active at that
5113                  * moment. So to make sure the plane gets truly disabled, disable
5114                  * first the self-refresh mode. The self-refresh enable bit in turn
5115                  * will be checked/applied by the HW only at the next frame start
5116                  * event which is after the vblank start event, so we need to have a
5117                  * wait-for-vblank between disabling the plane and the pipe.
5118                  */
5119                 if (old_crtc_state->base.active) {
5120                         intel_set_memory_cxsr(dev_priv, false);
5121                         dev_priv->wm.vlv.cxsr = false;
5122                         intel_wait_for_vblank(dev, crtc->pipe);
5123                 }
5124         }
5125
5126         /*
5127          * IVB workaround: must disable low power watermarks for at least
5128          * one frame before enabling scaling.  LP watermarks can be re-enabled
5129          * when scaling is disabled.
5130          *
5131          * WaCxSRDisabledForSpriteScaling:ivb
5132          */
5133         if (pipe_config->disable_lp_wm) {
5134                 ilk_disable_lp_wm(dev);
5135                 intel_wait_for_vblank(dev, crtc->pipe);
5136         }
5137
5138         /*
5139          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5140          * watermark programming here.
5141          */
5142         if (needs_modeset(&pipe_config->base))
5143                 return;
5144
5145         /*
5146          * For platforms that support atomic watermarks, program the
5147          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5148          * will be the intermediate values that are safe for both pre- and
5149          * post- vblank; when vblank happens, the 'active' values will be set
5150          * to the final 'target' values and we'll do this again to get the
5151          * optimal watermarks.  For gen9+ platforms, the values we program here
5152          * will be the final target values which will get automatically latched
5153          * at vblank time; no further programming will be necessary.
5154          *
5155          * If a platform hasn't been transitioned to atomic watermarks yet,
5156          * we'll continue to update watermarks the old way, if flags tell
5157          * us to.
5158          */
5159         if (dev_priv->display.initial_watermarks != NULL)
5160                 dev_priv->display.initial_watermarks(pipe_config);
5161         else if (pipe_config->update_wm_pre)
5162                 intel_update_watermarks(&crtc->base);
5163 }
5164
5165 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5166 {
5167         struct drm_device *dev = crtc->dev;
5168         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5169         struct drm_plane *p;
5170         int pipe = intel_crtc->pipe;
5171
5172         intel_crtc_dpms_overlay_disable(intel_crtc);
5173
5174         drm_for_each_plane_mask(p, dev, plane_mask)
5175                 to_intel_plane(p)->disable_plane(p, crtc);
5176
5177         /*
5178          * FIXME: Once we grow proper nuclear flip support out of this we need
5179          * to compute the mask of flip planes precisely. For the time being
5180          * consider this a flip to a NULL plane.
5181          */
5182         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5183 }
5184
5185 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5186                                           struct intel_crtc_state *crtc_state,
5187                                           struct drm_atomic_state *old_state)
5188 {
5189         struct drm_connector_state *old_conn_state;
5190         struct drm_connector *conn;
5191         int i;
5192
5193         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5194                 struct drm_connector_state *conn_state = conn->state;
5195                 struct intel_encoder *encoder =
5196                         to_intel_encoder(conn_state->best_encoder);
5197
5198                 if (conn_state->crtc != crtc)
5199                         continue;
5200
5201                 if (encoder->pre_pll_enable)
5202                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5203         }
5204 }
5205
5206 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5207                                       struct intel_crtc_state *crtc_state,
5208                                       struct drm_atomic_state *old_state)
5209 {
5210         struct drm_connector_state *old_conn_state;
5211         struct drm_connector *conn;
5212         int i;
5213
5214         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5215                 struct drm_connector_state *conn_state = conn->state;
5216                 struct intel_encoder *encoder =
5217                         to_intel_encoder(conn_state->best_encoder);
5218
5219                 if (conn_state->crtc != crtc)
5220                         continue;
5221
5222                 if (encoder->pre_enable)
5223                         encoder->pre_enable(encoder, crtc_state, conn_state);
5224         }
5225 }
5226
5227 static void intel_encoders_enable(struct drm_crtc *crtc,
5228                                   struct intel_crtc_state *crtc_state,
5229                                   struct drm_atomic_state *old_state)
5230 {
5231         struct drm_connector_state *old_conn_state;
5232         struct drm_connector *conn;
5233         int i;
5234
5235         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5236                 struct drm_connector_state *conn_state = conn->state;
5237                 struct intel_encoder *encoder =
5238                         to_intel_encoder(conn_state->best_encoder);
5239
5240                 if (conn_state->crtc != crtc)
5241                         continue;
5242
5243                 encoder->enable(encoder, crtc_state, conn_state);
5244                 intel_opregion_notify_encoder(encoder, true);
5245         }
5246 }
5247
5248 static void intel_encoders_disable(struct drm_crtc *crtc,
5249                                    struct intel_crtc_state *old_crtc_state,
5250                                    struct drm_atomic_state *old_state)
5251 {
5252         struct drm_connector_state *old_conn_state;
5253         struct drm_connector *conn;
5254         int i;
5255
5256         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5257                 struct intel_encoder *encoder =
5258                         to_intel_encoder(old_conn_state->best_encoder);
5259
5260                 if (old_conn_state->crtc != crtc)
5261                         continue;
5262
5263                 intel_opregion_notify_encoder(encoder, false);
5264                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5265         }
5266 }
5267
5268 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5269                                         struct intel_crtc_state *old_crtc_state,
5270                                         struct drm_atomic_state *old_state)
5271 {
5272         struct drm_connector_state *old_conn_state;
5273         struct drm_connector *conn;
5274         int i;
5275
5276         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5277                 struct intel_encoder *encoder =
5278                         to_intel_encoder(old_conn_state->best_encoder);
5279
5280                 if (old_conn_state->crtc != crtc)
5281                         continue;
5282
5283                 if (encoder->post_disable)
5284                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5285         }
5286 }
5287
5288 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5289                                             struct intel_crtc_state *old_crtc_state,
5290                                             struct drm_atomic_state *old_state)
5291 {
5292         struct drm_connector_state *old_conn_state;
5293         struct drm_connector *conn;
5294         int i;
5295
5296         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5297                 struct intel_encoder *encoder =
5298                         to_intel_encoder(old_conn_state->best_encoder);
5299
5300                 if (old_conn_state->crtc != crtc)
5301                         continue;
5302
5303                 if (encoder->post_pll_disable)
5304                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5305         }
5306 }
5307
5308 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5309                                  struct drm_atomic_state *old_state)
5310 {
5311         struct drm_crtc *crtc = pipe_config->base.crtc;
5312         struct drm_device *dev = crtc->dev;
5313         struct drm_i915_private *dev_priv = to_i915(dev);
5314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5315         int pipe = intel_crtc->pipe;
5316
5317         if (WARN_ON(intel_crtc->active))
5318                 return;
5319
5320         /*
5321          * Sometimes spurious CPU pipe underruns happen during FDI
5322          * training, at least with VGA+HDMI cloning. Suppress them.
5323          *
5324          * On ILK we get an occasional spurious CPU pipe underruns
5325          * between eDP port A enable and vdd enable. Also PCH port
5326          * enable seems to result in the occasional CPU pipe underrun.
5327          *
5328          * Spurious PCH underruns also occur during PCH enabling.
5329          */
5330         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5331                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5332         if (intel_crtc->config->has_pch_encoder)
5333                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5334
5335         if (intel_crtc->config->has_pch_encoder)
5336                 intel_prepare_shared_dpll(intel_crtc);
5337
5338         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5339                 intel_dp_set_m_n(intel_crtc, M1_N1);
5340
5341         intel_set_pipe_timings(intel_crtc);
5342         intel_set_pipe_src_size(intel_crtc);
5343
5344         if (intel_crtc->config->has_pch_encoder) {
5345                 intel_cpu_transcoder_set_m_n(intel_crtc,
5346                                      &intel_crtc->config->fdi_m_n, NULL);
5347         }
5348
5349         ironlake_set_pipeconf(crtc);
5350
5351         intel_crtc->active = true;
5352
5353         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5354
5355         if (intel_crtc->config->has_pch_encoder) {
5356                 /* Note: FDI PLL enabling _must_ be done before we enable the
5357                  * cpu pipes, hence this is separate from all the other fdi/pch
5358                  * enabling. */
5359                 ironlake_fdi_pll_enable(intel_crtc);
5360         } else {
5361                 assert_fdi_tx_disabled(dev_priv, pipe);
5362                 assert_fdi_rx_disabled(dev_priv, pipe);
5363         }
5364
5365         ironlake_pfit_enable(intel_crtc);
5366
5367         /*
5368          * On ILK+ LUT must be loaded before the pipe is running but with
5369          * clocks enabled
5370          */
5371         intel_color_load_luts(&pipe_config->base);
5372
5373         if (dev_priv->display.initial_watermarks != NULL)
5374                 dev_priv->display.initial_watermarks(intel_crtc->config);
5375         intel_enable_pipe(intel_crtc);
5376
5377         if (intel_crtc->config->has_pch_encoder)
5378                 ironlake_pch_enable(crtc);
5379
5380         assert_vblank_disabled(crtc);
5381         drm_crtc_vblank_on(crtc);
5382
5383         intel_encoders_enable(crtc, pipe_config, old_state);
5384
5385         if (HAS_PCH_CPT(dev))
5386                 cpt_verify_modeset(dev, intel_crtc->pipe);
5387
5388         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5389         if (intel_crtc->config->has_pch_encoder)
5390                 intel_wait_for_vblank(dev, pipe);
5391         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5392         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5393 }
5394
5395 /* IPS only exists on ULT machines and is tied to pipe A. */
5396 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5397 {
5398         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5399 }
5400
5401 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5402                                 struct drm_atomic_state *old_state)
5403 {
5404         struct drm_crtc *crtc = pipe_config->base.crtc;
5405         struct drm_device *dev = crtc->dev;
5406         struct drm_i915_private *dev_priv = to_i915(dev);
5407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5408         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5409         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5410
5411         if (WARN_ON(intel_crtc->active))
5412                 return;
5413
5414         if (intel_crtc->config->has_pch_encoder)
5415                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5416                                                       false);
5417
5418         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5419
5420         if (intel_crtc->config->shared_dpll)
5421                 intel_enable_shared_dpll(intel_crtc);
5422
5423         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5424                 intel_dp_set_m_n(intel_crtc, M1_N1);
5425
5426         if (!transcoder_is_dsi(cpu_transcoder))
5427                 intel_set_pipe_timings(intel_crtc);
5428
5429         intel_set_pipe_src_size(intel_crtc);
5430
5431         if (cpu_transcoder != TRANSCODER_EDP &&
5432             !transcoder_is_dsi(cpu_transcoder)) {
5433                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5434                            intel_crtc->config->pixel_multiplier - 1);
5435         }
5436
5437         if (intel_crtc->config->has_pch_encoder) {
5438                 intel_cpu_transcoder_set_m_n(intel_crtc,
5439                                      &intel_crtc->config->fdi_m_n, NULL);
5440         }
5441
5442         if (!transcoder_is_dsi(cpu_transcoder))
5443                 haswell_set_pipeconf(crtc);
5444
5445         haswell_set_pipemisc(crtc);
5446
5447         intel_color_set_csc(&pipe_config->base);
5448
5449         intel_crtc->active = true;
5450
5451         if (intel_crtc->config->has_pch_encoder)
5452                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5453         else
5454                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5455
5456         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5457
5458         if (intel_crtc->config->has_pch_encoder)
5459                 dev_priv->display.fdi_link_train(crtc);
5460
5461         if (!transcoder_is_dsi(cpu_transcoder))
5462                 intel_ddi_enable_pipe_clock(intel_crtc);
5463
5464         if (INTEL_INFO(dev)->gen >= 9)
5465                 skylake_pfit_enable(intel_crtc);
5466         else
5467                 ironlake_pfit_enable(intel_crtc);
5468
5469         /*
5470          * On ILK+ LUT must be loaded before the pipe is running but with
5471          * clocks enabled
5472          */
5473         intel_color_load_luts(&pipe_config->base);
5474
5475         intel_ddi_set_pipe_settings(crtc);
5476         if (!transcoder_is_dsi(cpu_transcoder))
5477                 intel_ddi_enable_transcoder_func(crtc);
5478
5479         if (dev_priv->display.initial_watermarks != NULL)
5480                 dev_priv->display.initial_watermarks(pipe_config);
5481         else
5482                 intel_update_watermarks(crtc);
5483
5484         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5485         if (!transcoder_is_dsi(cpu_transcoder))
5486                 intel_enable_pipe(intel_crtc);
5487
5488         if (intel_crtc->config->has_pch_encoder)
5489                 lpt_pch_enable(crtc);
5490
5491         if (intel_crtc->config->dp_encoder_is_mst)
5492                 intel_ddi_set_vc_payload_alloc(crtc, true);
5493
5494         assert_vblank_disabled(crtc);
5495         drm_crtc_vblank_on(crtc);
5496
5497         intel_encoders_enable(crtc, pipe_config, old_state);
5498
5499         if (intel_crtc->config->has_pch_encoder) {
5500                 intel_wait_for_vblank(dev, pipe);
5501                 intel_wait_for_vblank(dev, pipe);
5502                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5503                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5504                                                       true);
5505         }
5506
5507         /* If we change the relative order between pipe/planes enabling, we need
5508          * to change the workaround. */
5509         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5510         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5511                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5512                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5513         }
5514 }
5515
5516 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5517 {
5518         struct drm_device *dev = crtc->base.dev;
5519         struct drm_i915_private *dev_priv = to_i915(dev);
5520         int pipe = crtc->pipe;
5521
5522         /* To avoid upsetting the power well on haswell only disable the pfit if
5523          * it's in use. The hw state code will make sure we get this right. */
5524         if (force || crtc->config->pch_pfit.enabled) {
5525                 I915_WRITE(PF_CTL(pipe), 0);
5526                 I915_WRITE(PF_WIN_POS(pipe), 0);
5527                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5528         }
5529 }
5530
5531 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5532                                   struct drm_atomic_state *old_state)
5533 {
5534         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5535         struct drm_device *dev = crtc->dev;
5536         struct drm_i915_private *dev_priv = to_i915(dev);
5537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5538         int pipe = intel_crtc->pipe;
5539
5540         /*
5541          * Sometimes spurious CPU pipe underruns happen when the
5542          * pipe is already disabled, but FDI RX/TX is still enabled.
5543          * Happens at least with VGA+HDMI cloning. Suppress them.
5544          */
5545         if (intel_crtc->config->has_pch_encoder) {
5546                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5547                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5548         }
5549
5550         intel_encoders_disable(crtc, old_crtc_state, old_state);
5551
5552         drm_crtc_vblank_off(crtc);
5553         assert_vblank_disabled(crtc);
5554
5555         intel_disable_pipe(intel_crtc);
5556
5557         ironlake_pfit_disable(intel_crtc, false);
5558
5559         if (intel_crtc->config->has_pch_encoder)
5560                 ironlake_fdi_disable(crtc);
5561
5562         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5563
5564         if (intel_crtc->config->has_pch_encoder) {
5565                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5566
5567                 if (HAS_PCH_CPT(dev)) {
5568                         i915_reg_t reg;
5569                         u32 temp;
5570
5571                         /* disable TRANS_DP_CTL */
5572                         reg = TRANS_DP_CTL(pipe);
5573                         temp = I915_READ(reg);
5574                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5575                                   TRANS_DP_PORT_SEL_MASK);
5576                         temp |= TRANS_DP_PORT_SEL_NONE;
5577                         I915_WRITE(reg, temp);
5578
5579                         /* disable DPLL_SEL */
5580                         temp = I915_READ(PCH_DPLL_SEL);
5581                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5582                         I915_WRITE(PCH_DPLL_SEL, temp);
5583                 }
5584
5585                 ironlake_fdi_pll_disable(intel_crtc);
5586         }
5587
5588         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5589         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5590 }
5591
5592 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5593                                  struct drm_atomic_state *old_state)
5594 {
5595         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5596         struct drm_device *dev = crtc->dev;
5597         struct drm_i915_private *dev_priv = to_i915(dev);
5598         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5599         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5600
5601         if (intel_crtc->config->has_pch_encoder)
5602                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5603                                                       false);
5604
5605         intel_encoders_disable(crtc, old_crtc_state, old_state);
5606
5607         drm_crtc_vblank_off(crtc);
5608         assert_vblank_disabled(crtc);
5609
5610         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5611         if (!transcoder_is_dsi(cpu_transcoder))
5612                 intel_disable_pipe(intel_crtc);
5613
5614         if (intel_crtc->config->dp_encoder_is_mst)
5615                 intel_ddi_set_vc_payload_alloc(crtc, false);
5616
5617         if (!transcoder_is_dsi(cpu_transcoder))
5618                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5619
5620         if (INTEL_INFO(dev)->gen >= 9)
5621                 skylake_scaler_disable(intel_crtc);
5622         else
5623                 ironlake_pfit_disable(intel_crtc, false);
5624
5625         if (!transcoder_is_dsi(cpu_transcoder))
5626                 intel_ddi_disable_pipe_clock(intel_crtc);
5627
5628         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5629
5630         if (old_crtc_state->has_pch_encoder)
5631                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5632                                                       true);
5633 }
5634
5635 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5636 {
5637         struct drm_device *dev = crtc->base.dev;
5638         struct drm_i915_private *dev_priv = to_i915(dev);
5639         struct intel_crtc_state *pipe_config = crtc->config;
5640
5641         if (!pipe_config->gmch_pfit.control)
5642                 return;
5643
5644         /*
5645          * The panel fitter should only be adjusted whilst the pipe is disabled,
5646          * according to register description and PRM.
5647          */
5648         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5649         assert_pipe_disabled(dev_priv, crtc->pipe);
5650
5651         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5652         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5653
5654         /* Border color in case we don't scale up to the full screen. Black by
5655          * default, change to something else for debugging. */
5656         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5657 }
5658
5659 static enum intel_display_power_domain port_to_power_domain(enum port port)
5660 {
5661         switch (port) {
5662         case PORT_A:
5663                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5664         case PORT_B:
5665                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5666         case PORT_C:
5667                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5668         case PORT_D:
5669                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5670         case PORT_E:
5671                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5672         default:
5673                 MISSING_CASE(port);
5674                 return POWER_DOMAIN_PORT_OTHER;
5675         }
5676 }
5677
5678 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5679 {
5680         switch (port) {
5681         case PORT_A:
5682                 return POWER_DOMAIN_AUX_A;
5683         case PORT_B:
5684                 return POWER_DOMAIN_AUX_B;
5685         case PORT_C:
5686                 return POWER_DOMAIN_AUX_C;
5687         case PORT_D:
5688                 return POWER_DOMAIN_AUX_D;
5689         case PORT_E:
5690                 /* FIXME: Check VBT for actual wiring of PORT E */
5691                 return POWER_DOMAIN_AUX_D;
5692         default:
5693                 MISSING_CASE(port);
5694                 return POWER_DOMAIN_AUX_A;
5695         }
5696 }
5697
5698 enum intel_display_power_domain
5699 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5700 {
5701         struct drm_device *dev = intel_encoder->base.dev;
5702         struct intel_digital_port *intel_dig_port;
5703
5704         switch (intel_encoder->type) {
5705         case INTEL_OUTPUT_UNKNOWN:
5706                 /* Only DDI platforms should ever use this output type */
5707                 WARN_ON_ONCE(!HAS_DDI(dev));
5708         case INTEL_OUTPUT_DP:
5709         case INTEL_OUTPUT_HDMI:
5710         case INTEL_OUTPUT_EDP:
5711                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5712                 return port_to_power_domain(intel_dig_port->port);
5713         case INTEL_OUTPUT_DP_MST:
5714                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5715                 return port_to_power_domain(intel_dig_port->port);
5716         case INTEL_OUTPUT_ANALOG:
5717                 return POWER_DOMAIN_PORT_CRT;
5718         case INTEL_OUTPUT_DSI:
5719                 return POWER_DOMAIN_PORT_DSI;
5720         default:
5721                 return POWER_DOMAIN_PORT_OTHER;
5722         }
5723 }
5724
5725 enum intel_display_power_domain
5726 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5727 {
5728         struct drm_device *dev = intel_encoder->base.dev;
5729         struct intel_digital_port *intel_dig_port;
5730
5731         switch (intel_encoder->type) {
5732         case INTEL_OUTPUT_UNKNOWN:
5733         case INTEL_OUTPUT_HDMI:
5734                 /*
5735                  * Only DDI platforms should ever use these output types.
5736                  * We can get here after the HDMI detect code has already set
5737                  * the type of the shared encoder. Since we can't be sure
5738                  * what's the status of the given connectors, play safe and
5739                  * run the DP detection too.
5740                  */
5741                 WARN_ON_ONCE(!HAS_DDI(dev));
5742         case INTEL_OUTPUT_DP:
5743         case INTEL_OUTPUT_EDP:
5744                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5745                 return port_to_aux_power_domain(intel_dig_port->port);
5746         case INTEL_OUTPUT_DP_MST:
5747                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5748                 return port_to_aux_power_domain(intel_dig_port->port);
5749         default:
5750                 MISSING_CASE(intel_encoder->type);
5751                 return POWER_DOMAIN_AUX_A;
5752         }
5753 }
5754
5755 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5756                                             struct intel_crtc_state *crtc_state)
5757 {
5758         struct drm_device *dev = crtc->dev;
5759         struct drm_encoder *encoder;
5760         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5761         enum pipe pipe = intel_crtc->pipe;
5762         unsigned long mask;
5763         enum transcoder transcoder = crtc_state->cpu_transcoder;
5764
5765         if (!crtc_state->base.active)
5766                 return 0;
5767
5768         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5769         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5770         if (crtc_state->pch_pfit.enabled ||
5771             crtc_state->pch_pfit.force_thru)
5772                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5773
5774         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5775                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5776
5777                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5778         }
5779
5780         if (crtc_state->shared_dpll)
5781                 mask |= BIT(POWER_DOMAIN_PLLS);
5782
5783         return mask;
5784 }
5785
5786 static unsigned long
5787 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5788                                struct intel_crtc_state *crtc_state)
5789 {
5790         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5792         enum intel_display_power_domain domain;
5793         unsigned long domains, new_domains, old_domains;
5794
5795         old_domains = intel_crtc->enabled_power_domains;
5796         intel_crtc->enabled_power_domains = new_domains =
5797                 get_crtc_power_domains(crtc, crtc_state);
5798
5799         domains = new_domains & ~old_domains;
5800
5801         for_each_power_domain(domain, domains)
5802                 intel_display_power_get(dev_priv, domain);
5803
5804         return old_domains & ~new_domains;
5805 }
5806
5807 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5808                                       unsigned long domains)
5809 {
5810         enum intel_display_power_domain domain;
5811
5812         for_each_power_domain(domain, domains)
5813                 intel_display_power_put(dev_priv, domain);
5814 }
5815
5816 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5817 {
5818         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5819
5820         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5821             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5822                 return max_cdclk_freq;
5823         else if (IS_CHERRYVIEW(dev_priv))
5824                 return max_cdclk_freq*95/100;
5825         else if (INTEL_INFO(dev_priv)->gen < 4)
5826                 return 2*max_cdclk_freq*90/100;
5827         else
5828                 return max_cdclk_freq*90/100;
5829 }
5830
5831 static int skl_calc_cdclk(int max_pixclk, int vco);
5832
5833 static void intel_update_max_cdclk(struct drm_device *dev)
5834 {
5835         struct drm_i915_private *dev_priv = to_i915(dev);
5836
5837         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5838                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5839                 int max_cdclk, vco;
5840
5841                 vco = dev_priv->skl_preferred_vco_freq;
5842                 WARN_ON(vco != 8100000 && vco != 8640000);
5843
5844                 /*
5845                  * Use the lower (vco 8640) cdclk values as a
5846                  * first guess. skl_calc_cdclk() will correct it
5847                  * if the preferred vco is 8100 instead.
5848                  */
5849                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5850                         max_cdclk = 617143;
5851                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5852                         max_cdclk = 540000;
5853                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5854                         max_cdclk = 432000;
5855                 else
5856                         max_cdclk = 308571;
5857
5858                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5859         } else if (IS_BROXTON(dev)) {
5860                 dev_priv->max_cdclk_freq = 624000;
5861         } else if (IS_BROADWELL(dev))  {
5862                 /*
5863                  * FIXME with extra cooling we can allow
5864                  * 540 MHz for ULX and 675 Mhz for ULT.
5865                  * How can we know if extra cooling is
5866                  * available? PCI ID, VTB, something else?
5867                  */
5868                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5869                         dev_priv->max_cdclk_freq = 450000;
5870                 else if (IS_BDW_ULX(dev))
5871                         dev_priv->max_cdclk_freq = 450000;
5872                 else if (IS_BDW_ULT(dev))
5873                         dev_priv->max_cdclk_freq = 540000;
5874                 else
5875                         dev_priv->max_cdclk_freq = 675000;
5876         } else if (IS_CHERRYVIEW(dev)) {
5877                 dev_priv->max_cdclk_freq = 320000;
5878         } else if (IS_VALLEYVIEW(dev)) {
5879                 dev_priv->max_cdclk_freq = 400000;
5880         } else {
5881                 /* otherwise assume cdclk is fixed */
5882                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5883         }
5884
5885         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5886
5887         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5888                          dev_priv->max_cdclk_freq);
5889
5890         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5891                          dev_priv->max_dotclk_freq);
5892 }
5893
5894 static void intel_update_cdclk(struct drm_device *dev)
5895 {
5896         struct drm_i915_private *dev_priv = to_i915(dev);
5897
5898         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5899
5900         if (INTEL_GEN(dev_priv) >= 9)
5901                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5902                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5903                                  dev_priv->cdclk_pll.ref);
5904         else
5905                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5906                                  dev_priv->cdclk_freq);
5907
5908         /*
5909          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5910          * Programmng [sic] note: bit[9:2] should be programmed to the number
5911          * of cdclk that generates 4MHz reference clock freq which is used to
5912          * generate GMBus clock. This will vary with the cdclk freq.
5913          */
5914         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5915                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5916 }
5917
5918 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5919 static int skl_cdclk_decimal(int cdclk)
5920 {
5921         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5922 }
5923
5924 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5925 {
5926         int ratio;
5927
5928         if (cdclk == dev_priv->cdclk_pll.ref)
5929                 return 0;
5930
5931         switch (cdclk) {
5932         default:
5933                 MISSING_CASE(cdclk);
5934         case 144000:
5935         case 288000:
5936         case 384000:
5937         case 576000:
5938                 ratio = 60;
5939                 break;
5940         case 624000:
5941                 ratio = 65;
5942                 break;
5943         }
5944
5945         return dev_priv->cdclk_pll.ref * ratio;
5946 }
5947
5948 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5949 {
5950         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5951
5952         /* Timeout 200us */
5953         if (intel_wait_for_register(dev_priv,
5954                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5955                                     1))
5956                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5957
5958         dev_priv->cdclk_pll.vco = 0;
5959 }
5960
5961 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5962 {
5963         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5964         u32 val;
5965
5966         val = I915_READ(BXT_DE_PLL_CTL);
5967         val &= ~BXT_DE_PLL_RATIO_MASK;
5968         val |= BXT_DE_PLL_RATIO(ratio);
5969         I915_WRITE(BXT_DE_PLL_CTL, val);
5970
5971         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5972
5973         /* Timeout 200us */
5974         if (intel_wait_for_register(dev_priv,
5975                                     BXT_DE_PLL_ENABLE,
5976                                     BXT_DE_PLL_LOCK,
5977                                     BXT_DE_PLL_LOCK,
5978                                     1))
5979                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5980
5981         dev_priv->cdclk_pll.vco = vco;
5982 }
5983
5984 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5985 {
5986         u32 val, divider;
5987         int vco, ret;
5988
5989         vco = bxt_de_pll_vco(dev_priv, cdclk);
5990
5991         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5992
5993         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5994         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5995         case 8:
5996                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5997                 break;
5998         case 4:
5999                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
6000                 break;
6001         case 3:
6002                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
6003                 break;
6004         case 2:
6005                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6006                 break;
6007         default:
6008                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6009                 WARN_ON(vco != 0);
6010
6011                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6012                 break;
6013         }
6014
6015         /* Inform power controller of upcoming frequency change */
6016         mutex_lock(&dev_priv->rps.hw_lock);
6017         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6018                                       0x80000000);
6019         mutex_unlock(&dev_priv->rps.hw_lock);
6020
6021         if (ret) {
6022                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6023                           ret, cdclk);
6024                 return;
6025         }
6026
6027         if (dev_priv->cdclk_pll.vco != 0 &&
6028             dev_priv->cdclk_pll.vco != vco)
6029                 bxt_de_pll_disable(dev_priv);
6030
6031         if (dev_priv->cdclk_pll.vco != vco)
6032                 bxt_de_pll_enable(dev_priv, vco);
6033
6034         val = divider | skl_cdclk_decimal(cdclk);
6035         /*
6036          * FIXME if only the cd2x divider needs changing, it could be done
6037          * without shutting off the pipe (if only one pipe is active).
6038          */
6039         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6040         /*
6041          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6042          * enable otherwise.
6043          */
6044         if (cdclk >= 500000)
6045                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6046         I915_WRITE(CDCLK_CTL, val);
6047
6048         mutex_lock(&dev_priv->rps.hw_lock);
6049         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6050                                       DIV_ROUND_UP(cdclk, 25000));
6051         mutex_unlock(&dev_priv->rps.hw_lock);
6052
6053         if (ret) {
6054                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6055                           ret, cdclk);
6056                 return;
6057         }
6058
6059         intel_update_cdclk(&dev_priv->drm);
6060 }
6061
6062 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6063 {
6064         u32 cdctl, expected;
6065
6066         intel_update_cdclk(&dev_priv->drm);
6067
6068         if (dev_priv->cdclk_pll.vco == 0 ||
6069             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6070                 goto sanitize;
6071
6072         /* DPLL okay; verify the cdclock
6073          *
6074          * Some BIOS versions leave an incorrect decimal frequency value and
6075          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6076          * so sanitize this register.
6077          */
6078         cdctl = I915_READ(CDCLK_CTL);
6079         /*
6080          * Let's ignore the pipe field, since BIOS could have configured the
6081          * dividers both synching to an active pipe, or asynchronously
6082          * (PIPE_NONE).
6083          */
6084         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6085
6086         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6087                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6088         /*
6089          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6090          * enable otherwise.
6091          */
6092         if (dev_priv->cdclk_freq >= 500000)
6093                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6094
6095         if (cdctl == expected)
6096                 /* All well; nothing to sanitize */
6097                 return;
6098
6099 sanitize:
6100         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6101
6102         /* force cdclk programming */
6103         dev_priv->cdclk_freq = 0;
6104
6105         /* force full PLL disable + enable */
6106         dev_priv->cdclk_pll.vco = -1;
6107 }
6108
6109 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6110 {
6111         bxt_sanitize_cdclk(dev_priv);
6112
6113         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6114                 return;
6115
6116         /*
6117          * FIXME:
6118          * - The initial CDCLK needs to be read from VBT.
6119          *   Need to make this change after VBT has changes for BXT.
6120          */
6121         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6122 }
6123
6124 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6125 {
6126         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6127 }
6128
6129 static int skl_calc_cdclk(int max_pixclk, int vco)
6130 {
6131         if (vco == 8640000) {
6132                 if (max_pixclk > 540000)
6133                         return 617143;
6134                 else if (max_pixclk > 432000)
6135                         return 540000;
6136                 else if (max_pixclk > 308571)
6137                         return 432000;
6138                 else
6139                         return 308571;
6140         } else {
6141                 if (max_pixclk > 540000)
6142                         return 675000;
6143                 else if (max_pixclk > 450000)
6144                         return 540000;
6145                 else if (max_pixclk > 337500)
6146                         return 450000;
6147                 else
6148                         return 337500;
6149         }
6150 }
6151
6152 static void
6153 skl_dpll0_update(struct drm_i915_private *dev_priv)
6154 {
6155         u32 val;
6156
6157         dev_priv->cdclk_pll.ref = 24000;
6158         dev_priv->cdclk_pll.vco = 0;
6159
6160         val = I915_READ(LCPLL1_CTL);
6161         if ((val & LCPLL_PLL_ENABLE) == 0)
6162                 return;
6163
6164         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6165                 return;
6166
6167         val = I915_READ(DPLL_CTRL1);
6168
6169         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6170                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6171                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6172                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6173                 return;
6174
6175         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6176         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6177         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6178         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6179         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6180                 dev_priv->cdclk_pll.vco = 8100000;
6181                 break;
6182         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6183         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6184                 dev_priv->cdclk_pll.vco = 8640000;
6185                 break;
6186         default:
6187                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6188                 break;
6189         }
6190 }
6191
6192 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6193 {
6194         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6195
6196         dev_priv->skl_preferred_vco_freq = vco;
6197
6198         if (changed)
6199                 intel_update_max_cdclk(&dev_priv->drm);
6200 }
6201
6202 static void
6203 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6204 {
6205         int min_cdclk = skl_calc_cdclk(0, vco);
6206         u32 val;
6207
6208         WARN_ON(vco != 8100000 && vco != 8640000);
6209
6210         /* select the minimum CDCLK before enabling DPLL 0 */
6211         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6212         I915_WRITE(CDCLK_CTL, val);
6213         POSTING_READ(CDCLK_CTL);
6214
6215         /*
6216          * We always enable DPLL0 with the lowest link rate possible, but still
6217          * taking into account the VCO required to operate the eDP panel at the
6218          * desired frequency. The usual DP link rates operate with a VCO of
6219          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6220          * The modeset code is responsible for the selection of the exact link
6221          * rate later on, with the constraint of choosing a frequency that
6222          * works with vco.
6223          */
6224         val = I915_READ(DPLL_CTRL1);
6225
6226         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6227                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6228         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6229         if (vco == 8640000)
6230                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6231                                             SKL_DPLL0);
6232         else
6233                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6234                                             SKL_DPLL0);
6235
6236         I915_WRITE(DPLL_CTRL1, val);
6237         POSTING_READ(DPLL_CTRL1);
6238
6239         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6240
6241         if (intel_wait_for_register(dev_priv,
6242                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6243                                     5))
6244                 DRM_ERROR("DPLL0 not locked\n");
6245
6246         dev_priv->cdclk_pll.vco = vco;
6247
6248         /* We'll want to keep using the current vco from now on. */
6249         skl_set_preferred_cdclk_vco(dev_priv, vco);
6250 }
6251
6252 static void
6253 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6254 {
6255         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6256         if (intel_wait_for_register(dev_priv,
6257                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6258                                    1))
6259                 DRM_ERROR("Couldn't disable DPLL0\n");
6260
6261         dev_priv->cdclk_pll.vco = 0;
6262 }
6263
6264 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6265 {
6266         int ret;
6267         u32 val;
6268
6269         /* inform PCU we want to change CDCLK */
6270         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6271         mutex_lock(&dev_priv->rps.hw_lock);
6272         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6273         mutex_unlock(&dev_priv->rps.hw_lock);
6274
6275         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6276 }
6277
6278 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6279 {
6280         return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6281 }
6282
6283 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6284 {
6285         struct drm_device *dev = &dev_priv->drm;
6286         u32 freq_select, pcu_ack;
6287
6288         WARN_ON((cdclk == 24000) != (vco == 0));
6289
6290         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6291
6292         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6293                 DRM_ERROR("failed to inform PCU about cdclk change\n");
6294                 return;
6295         }
6296
6297         /* set CDCLK_CTL */
6298         switch (cdclk) {
6299         case 450000:
6300         case 432000:
6301                 freq_select = CDCLK_FREQ_450_432;
6302                 pcu_ack = 1;
6303                 break;
6304         case 540000:
6305                 freq_select = CDCLK_FREQ_540;
6306                 pcu_ack = 2;
6307                 break;
6308         case 308571:
6309         case 337500:
6310         default:
6311                 freq_select = CDCLK_FREQ_337_308;
6312                 pcu_ack = 0;
6313                 break;
6314         case 617143:
6315         case 675000:
6316                 freq_select = CDCLK_FREQ_675_617;
6317                 pcu_ack = 3;
6318                 break;
6319         }
6320
6321         if (dev_priv->cdclk_pll.vco != 0 &&
6322             dev_priv->cdclk_pll.vco != vco)
6323                 skl_dpll0_disable(dev_priv);
6324
6325         if (dev_priv->cdclk_pll.vco != vco)
6326                 skl_dpll0_enable(dev_priv, vco);
6327
6328         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6329         POSTING_READ(CDCLK_CTL);
6330
6331         /* inform PCU of the change */
6332         mutex_lock(&dev_priv->rps.hw_lock);
6333         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6334         mutex_unlock(&dev_priv->rps.hw_lock);
6335
6336         intel_update_cdclk(dev);
6337 }
6338
6339 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6340
6341 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6342 {
6343         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6344 }
6345
6346 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6347 {
6348         int cdclk, vco;
6349
6350         skl_sanitize_cdclk(dev_priv);
6351
6352         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6353                 /*
6354                  * Use the current vco as our initial
6355                  * guess as to what the preferred vco is.
6356                  */
6357                 if (dev_priv->skl_preferred_vco_freq == 0)
6358                         skl_set_preferred_cdclk_vco(dev_priv,
6359                                                     dev_priv->cdclk_pll.vco);
6360                 return;
6361         }
6362
6363         vco = dev_priv->skl_preferred_vco_freq;
6364         if (vco == 0)
6365                 vco = 8100000;
6366         cdclk = skl_calc_cdclk(0, vco);
6367
6368         skl_set_cdclk(dev_priv, cdclk, vco);
6369 }
6370
6371 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6372 {
6373         uint32_t cdctl, expected;
6374
6375         /*
6376          * check if the pre-os intialized the display
6377          * There is SWF18 scratchpad register defined which is set by the
6378          * pre-os which can be used by the OS drivers to check the status
6379          */
6380         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6381                 goto sanitize;
6382
6383         intel_update_cdclk(&dev_priv->drm);
6384         /* Is PLL enabled and locked ? */
6385         if (dev_priv->cdclk_pll.vco == 0 ||
6386             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6387                 goto sanitize;
6388
6389         /* DPLL okay; verify the cdclock
6390          *
6391          * Noticed in some instances that the freq selection is correct but
6392          * decimal part is programmed wrong from BIOS where pre-os does not
6393          * enable display. Verify the same as well.
6394          */
6395         cdctl = I915_READ(CDCLK_CTL);
6396         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6397                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6398         if (cdctl == expected)
6399                 /* All well; nothing to sanitize */
6400                 return;
6401
6402 sanitize:
6403         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6404
6405         /* force cdclk programming */
6406         dev_priv->cdclk_freq = 0;
6407         /* force full PLL disable + enable */
6408         dev_priv->cdclk_pll.vco = -1;
6409 }
6410
6411 /* Adjust CDclk dividers to allow high res or save power if possible */
6412 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6413 {
6414         struct drm_i915_private *dev_priv = to_i915(dev);
6415         u32 val, cmd;
6416
6417         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6418                                         != dev_priv->cdclk_freq);
6419
6420         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6421                 cmd = 2;
6422         else if (cdclk == 266667)
6423                 cmd = 1;
6424         else
6425                 cmd = 0;
6426
6427         mutex_lock(&dev_priv->rps.hw_lock);
6428         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6429         val &= ~DSPFREQGUAR_MASK;
6430         val |= (cmd << DSPFREQGUAR_SHIFT);
6431         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6432         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6433                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6434                      50)) {
6435                 DRM_ERROR("timed out waiting for CDclk change\n");
6436         }
6437         mutex_unlock(&dev_priv->rps.hw_lock);
6438
6439         mutex_lock(&dev_priv->sb_lock);
6440
6441         if (cdclk == 400000) {
6442                 u32 divider;
6443
6444                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6445
6446                 /* adjust cdclk divider */
6447                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6448                 val &= ~CCK_FREQUENCY_VALUES;
6449                 val |= divider;
6450                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6451
6452                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6453                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6454                              50))
6455                         DRM_ERROR("timed out waiting for CDclk change\n");
6456         }
6457
6458         /* adjust self-refresh exit latency value */
6459         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6460         val &= ~0x7f;
6461
6462         /*
6463          * For high bandwidth configs, we set a higher latency in the bunit
6464          * so that the core display fetch happens in time to avoid underruns.
6465          */
6466         if (cdclk == 400000)
6467                 val |= 4500 / 250; /* 4.5 usec */
6468         else
6469                 val |= 3000 / 250; /* 3.0 usec */
6470         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6471
6472         mutex_unlock(&dev_priv->sb_lock);
6473
6474         intel_update_cdclk(dev);
6475 }
6476
6477 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6478 {
6479         struct drm_i915_private *dev_priv = to_i915(dev);
6480         u32 val, cmd;
6481
6482         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6483                                                 != dev_priv->cdclk_freq);
6484
6485         switch (cdclk) {
6486         case 333333:
6487         case 320000:
6488         case 266667:
6489         case 200000:
6490                 break;
6491         default:
6492                 MISSING_CASE(cdclk);
6493                 return;
6494         }
6495
6496         /*
6497          * Specs are full of misinformation, but testing on actual
6498          * hardware has shown that we just need to write the desired
6499          * CCK divider into the Punit register.
6500          */
6501         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6502
6503         mutex_lock(&dev_priv->rps.hw_lock);
6504         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6505         val &= ~DSPFREQGUAR_MASK_CHV;
6506         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6507         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6508         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6509                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6510                      50)) {
6511                 DRM_ERROR("timed out waiting for CDclk change\n");
6512         }
6513         mutex_unlock(&dev_priv->rps.hw_lock);
6514
6515         intel_update_cdclk(dev);
6516 }
6517
6518 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6519                                  int max_pixclk)
6520 {
6521         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6522         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6523
6524         /*
6525          * Really only a few cases to deal with, as only 4 CDclks are supported:
6526          *   200MHz
6527          *   267MHz
6528          *   320/333MHz (depends on HPLL freq)
6529          *   400MHz (VLV only)
6530          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6531          * of the lower bin and adjust if needed.
6532          *
6533          * We seem to get an unstable or solid color picture at 200MHz.
6534          * Not sure what's wrong. For now use 200MHz only when all pipes
6535          * are off.
6536          */
6537         if (!IS_CHERRYVIEW(dev_priv) &&
6538             max_pixclk > freq_320*limit/100)
6539                 return 400000;
6540         else if (max_pixclk > 266667*limit/100)
6541                 return freq_320;
6542         else if (max_pixclk > 0)
6543                 return 266667;
6544         else
6545                 return 200000;
6546 }
6547
6548 static int bxt_calc_cdclk(int max_pixclk)
6549 {
6550         if (max_pixclk > 576000)
6551                 return 624000;
6552         else if (max_pixclk > 384000)
6553                 return 576000;
6554         else if (max_pixclk > 288000)
6555                 return 384000;
6556         else if (max_pixclk > 144000)
6557                 return 288000;
6558         else
6559                 return 144000;
6560 }
6561
6562 /* Compute the max pixel clock for new configuration. */
6563 static int intel_mode_max_pixclk(struct drm_device *dev,
6564                                  struct drm_atomic_state *state)
6565 {
6566         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6567         struct drm_i915_private *dev_priv = to_i915(dev);
6568         struct drm_crtc *crtc;
6569         struct drm_crtc_state *crtc_state;
6570         unsigned max_pixclk = 0, i;
6571         enum pipe pipe;
6572
6573         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6574                sizeof(intel_state->min_pixclk));
6575
6576         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6577                 int pixclk = 0;
6578
6579                 if (crtc_state->enable)
6580                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6581
6582                 intel_state->min_pixclk[i] = pixclk;
6583         }
6584
6585         for_each_pipe(dev_priv, pipe)
6586                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6587
6588         return max_pixclk;
6589 }
6590
6591 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6592 {
6593         struct drm_device *dev = state->dev;
6594         struct drm_i915_private *dev_priv = to_i915(dev);
6595         int max_pixclk = intel_mode_max_pixclk(dev, state);
6596         struct intel_atomic_state *intel_state =
6597                 to_intel_atomic_state(state);
6598
6599         intel_state->cdclk = intel_state->dev_cdclk =
6600                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6601
6602         if (!intel_state->active_crtcs)
6603                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6604
6605         return 0;
6606 }
6607
6608 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6609 {
6610         int max_pixclk = ilk_max_pixel_rate(state);
6611         struct intel_atomic_state *intel_state =
6612                 to_intel_atomic_state(state);
6613
6614         intel_state->cdclk = intel_state->dev_cdclk =
6615                 bxt_calc_cdclk(max_pixclk);
6616
6617         if (!intel_state->active_crtcs)
6618                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6619
6620         return 0;
6621 }
6622
6623 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6624 {
6625         unsigned int credits, default_credits;
6626
6627         if (IS_CHERRYVIEW(dev_priv))
6628                 default_credits = PFI_CREDIT(12);
6629         else
6630                 default_credits = PFI_CREDIT(8);
6631
6632         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6633                 /* CHV suggested value is 31 or 63 */
6634                 if (IS_CHERRYVIEW(dev_priv))
6635                         credits = PFI_CREDIT_63;
6636                 else
6637                         credits = PFI_CREDIT(15);
6638         } else {
6639                 credits = default_credits;
6640         }
6641
6642         /*
6643          * WA - write default credits before re-programming
6644          * FIXME: should we also set the resend bit here?
6645          */
6646         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6647                    default_credits);
6648
6649         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6650                    credits | PFI_CREDIT_RESEND);
6651
6652         /*
6653          * FIXME is this guaranteed to clear
6654          * immediately or should we poll for it?
6655          */
6656         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6657 }
6658
6659 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6660 {
6661         struct drm_device *dev = old_state->dev;
6662         struct drm_i915_private *dev_priv = to_i915(dev);
6663         struct intel_atomic_state *old_intel_state =
6664                 to_intel_atomic_state(old_state);
6665         unsigned req_cdclk = old_intel_state->dev_cdclk;
6666
6667         /*
6668          * FIXME: We can end up here with all power domains off, yet
6669          * with a CDCLK frequency other than the minimum. To account
6670          * for this take the PIPE-A power domain, which covers the HW
6671          * blocks needed for the following programming. This can be
6672          * removed once it's guaranteed that we get here either with
6673          * the minimum CDCLK set, or the required power domains
6674          * enabled.
6675          */
6676         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6677
6678         if (IS_CHERRYVIEW(dev))
6679                 cherryview_set_cdclk(dev, req_cdclk);
6680         else
6681                 valleyview_set_cdclk(dev, req_cdclk);
6682
6683         vlv_program_pfi_credits(dev_priv);
6684
6685         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6686 }
6687
6688 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6689                                    struct drm_atomic_state *old_state)
6690 {
6691         struct drm_crtc *crtc = pipe_config->base.crtc;
6692         struct drm_device *dev = crtc->dev;
6693         struct drm_i915_private *dev_priv = to_i915(dev);
6694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6695         int pipe = intel_crtc->pipe;
6696
6697         if (WARN_ON(intel_crtc->active))
6698                 return;
6699
6700         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6701                 intel_dp_set_m_n(intel_crtc, M1_N1);
6702
6703         intel_set_pipe_timings(intel_crtc);
6704         intel_set_pipe_src_size(intel_crtc);
6705
6706         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6707                 struct drm_i915_private *dev_priv = to_i915(dev);
6708
6709                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6710                 I915_WRITE(CHV_CANVAS(pipe), 0);
6711         }
6712
6713         i9xx_set_pipeconf(intel_crtc);
6714
6715         intel_crtc->active = true;
6716
6717         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6718
6719         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6720
6721         if (IS_CHERRYVIEW(dev)) {
6722                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6723                 chv_enable_pll(intel_crtc, intel_crtc->config);
6724         } else {
6725                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6726                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6727         }
6728
6729         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6730
6731         i9xx_pfit_enable(intel_crtc);
6732
6733         intel_color_load_luts(&pipe_config->base);
6734
6735         intel_update_watermarks(crtc);
6736         intel_enable_pipe(intel_crtc);
6737
6738         assert_vblank_disabled(crtc);
6739         drm_crtc_vblank_on(crtc);
6740
6741         intel_encoders_enable(crtc, pipe_config, old_state);
6742 }
6743
6744 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6745 {
6746         struct drm_device *dev = crtc->base.dev;
6747         struct drm_i915_private *dev_priv = to_i915(dev);
6748
6749         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6750         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6751 }
6752
6753 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6754                              struct drm_atomic_state *old_state)
6755 {
6756         struct drm_crtc *crtc = pipe_config->base.crtc;
6757         struct drm_device *dev = crtc->dev;
6758         struct drm_i915_private *dev_priv = to_i915(dev);
6759         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6760         enum pipe pipe = intel_crtc->pipe;
6761
6762         if (WARN_ON(intel_crtc->active))
6763                 return;
6764
6765         i9xx_set_pll_dividers(intel_crtc);
6766
6767         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6768                 intel_dp_set_m_n(intel_crtc, M1_N1);
6769
6770         intel_set_pipe_timings(intel_crtc);
6771         intel_set_pipe_src_size(intel_crtc);
6772
6773         i9xx_set_pipeconf(intel_crtc);
6774
6775         intel_crtc->active = true;
6776
6777         if (!IS_GEN2(dev))
6778                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6779
6780         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6781
6782         i9xx_enable_pll(intel_crtc);
6783
6784         i9xx_pfit_enable(intel_crtc);
6785
6786         intel_color_load_luts(&pipe_config->base);
6787
6788         intel_update_watermarks(crtc);
6789         intel_enable_pipe(intel_crtc);
6790
6791         assert_vblank_disabled(crtc);
6792         drm_crtc_vblank_on(crtc);
6793
6794         intel_encoders_enable(crtc, pipe_config, old_state);
6795 }
6796
6797 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6798 {
6799         struct drm_device *dev = crtc->base.dev;
6800         struct drm_i915_private *dev_priv = to_i915(dev);
6801
6802         if (!crtc->config->gmch_pfit.control)
6803                 return;
6804
6805         assert_pipe_disabled(dev_priv, crtc->pipe);
6806
6807         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6808                          I915_READ(PFIT_CONTROL));
6809         I915_WRITE(PFIT_CONTROL, 0);
6810 }
6811
6812 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6813                               struct drm_atomic_state *old_state)
6814 {
6815         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6816         struct drm_device *dev = crtc->dev;
6817         struct drm_i915_private *dev_priv = to_i915(dev);
6818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6819         int pipe = intel_crtc->pipe;
6820
6821         /*
6822          * On gen2 planes are double buffered but the pipe isn't, so we must
6823          * wait for planes to fully turn off before disabling the pipe.
6824          */
6825         if (IS_GEN2(dev))
6826                 intel_wait_for_vblank(dev, pipe);
6827
6828         intel_encoders_disable(crtc, old_crtc_state, old_state);
6829
6830         drm_crtc_vblank_off(crtc);
6831         assert_vblank_disabled(crtc);
6832
6833         intel_disable_pipe(intel_crtc);
6834
6835         i9xx_pfit_disable(intel_crtc);
6836
6837         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6838
6839         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6840                 if (IS_CHERRYVIEW(dev))
6841                         chv_disable_pll(dev_priv, pipe);
6842                 else if (IS_VALLEYVIEW(dev))
6843                         vlv_disable_pll(dev_priv, pipe);
6844                 else
6845                         i9xx_disable_pll(intel_crtc);
6846         }
6847
6848         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6849
6850         if (!IS_GEN2(dev))
6851                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6852 }
6853
6854 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6855 {
6856         struct intel_encoder *encoder;
6857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6858         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6859         enum intel_display_power_domain domain;
6860         unsigned long domains;
6861         struct drm_atomic_state *state;
6862         struct intel_crtc_state *crtc_state;
6863         int ret;
6864
6865         if (!intel_crtc->active)
6866                 return;
6867
6868         if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6869                 WARN_ON(intel_crtc->flip_work);
6870
6871                 intel_pre_disable_primary_noatomic(crtc);
6872
6873                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6874                 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6875         }
6876
6877         state = drm_atomic_state_alloc(crtc->dev);
6878         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6879
6880         /* Everything's already locked, -EDEADLK can't happen. */
6881         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6882         ret = drm_atomic_add_affected_connectors(state, crtc);
6883
6884         WARN_ON(IS_ERR(crtc_state) || ret);
6885
6886         dev_priv->display.crtc_disable(crtc_state, state);
6887
6888         drm_atomic_state_free(state);
6889
6890         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6891                       crtc->base.id, crtc->name);
6892
6893         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6894         crtc->state->active = false;
6895         intel_crtc->active = false;
6896         crtc->enabled = false;
6897         crtc->state->connector_mask = 0;
6898         crtc->state->encoder_mask = 0;
6899
6900         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6901                 encoder->base.crtc = NULL;
6902
6903         intel_fbc_disable(intel_crtc);
6904         intel_update_watermarks(crtc);
6905         intel_disable_shared_dpll(intel_crtc);
6906
6907         domains = intel_crtc->enabled_power_domains;
6908         for_each_power_domain(domain, domains)
6909                 intel_display_power_put(dev_priv, domain);
6910         intel_crtc->enabled_power_domains = 0;
6911
6912         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6913         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6914 }
6915
6916 /*
6917  * turn all crtc's off, but do not adjust state
6918  * This has to be paired with a call to intel_modeset_setup_hw_state.
6919  */
6920 int intel_display_suspend(struct drm_device *dev)
6921 {
6922         struct drm_i915_private *dev_priv = to_i915(dev);
6923         struct drm_atomic_state *state;
6924         int ret;
6925
6926         state = drm_atomic_helper_suspend(dev);
6927         ret = PTR_ERR_OR_ZERO(state);
6928         if (ret)
6929                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6930         else
6931                 dev_priv->modeset_restore_state = state;
6932         return ret;
6933 }
6934
6935 void intel_encoder_destroy(struct drm_encoder *encoder)
6936 {
6937         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6938
6939         drm_encoder_cleanup(encoder);
6940         kfree(intel_encoder);
6941 }
6942
6943 /* Cross check the actual hw state with our own modeset state tracking (and it's
6944  * internal consistency). */
6945 static void intel_connector_verify_state(struct intel_connector *connector)
6946 {
6947         struct drm_crtc *crtc = connector->base.state->crtc;
6948
6949         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6950                       connector->base.base.id,
6951                       connector->base.name);
6952
6953         if (connector->get_hw_state(connector)) {
6954                 struct intel_encoder *encoder = connector->encoder;
6955                 struct drm_connector_state *conn_state = connector->base.state;
6956
6957                 I915_STATE_WARN(!crtc,
6958                          "connector enabled without attached crtc\n");
6959
6960                 if (!crtc)
6961                         return;
6962
6963                 I915_STATE_WARN(!crtc->state->active,
6964                       "connector is active, but attached crtc isn't\n");
6965
6966                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6967                         return;
6968
6969                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6970                         "atomic encoder doesn't match attached encoder\n");
6971
6972                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6973                         "attached encoder crtc differs from connector crtc\n");
6974         } else {
6975                 I915_STATE_WARN(crtc && crtc->state->active,
6976                         "attached crtc is active, but connector isn't\n");
6977                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6978                         "best encoder set without crtc!\n");
6979         }
6980 }
6981
6982 int intel_connector_init(struct intel_connector *connector)
6983 {
6984         drm_atomic_helper_connector_reset(&connector->base);
6985
6986         if (!connector->base.state)
6987                 return -ENOMEM;
6988
6989         return 0;
6990 }
6991
6992 struct intel_connector *intel_connector_alloc(void)
6993 {
6994         struct intel_connector *connector;
6995
6996         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6997         if (!connector)
6998                 return NULL;
6999
7000         if (intel_connector_init(connector) < 0) {
7001                 kfree(connector);
7002                 return NULL;
7003         }
7004
7005         return connector;
7006 }
7007
7008 /* Simple connector->get_hw_state implementation for encoders that support only
7009  * one connector and no cloning and hence the encoder state determines the state
7010  * of the connector. */
7011 bool intel_connector_get_hw_state(struct intel_connector *connector)
7012 {
7013         enum pipe pipe = 0;
7014         struct intel_encoder *encoder = connector->encoder;
7015
7016         return encoder->get_hw_state(encoder, &pipe);
7017 }
7018
7019 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7020 {
7021         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7022                 return crtc_state->fdi_lanes;
7023
7024         return 0;
7025 }
7026
7027 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7028                                      struct intel_crtc_state *pipe_config)
7029 {
7030         struct drm_atomic_state *state = pipe_config->base.state;
7031         struct intel_crtc *other_crtc;
7032         struct intel_crtc_state *other_crtc_state;
7033
7034         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7035                       pipe_name(pipe), pipe_config->fdi_lanes);
7036         if (pipe_config->fdi_lanes > 4) {
7037                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7038                               pipe_name(pipe), pipe_config->fdi_lanes);
7039                 return -EINVAL;
7040         }
7041
7042         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7043                 if (pipe_config->fdi_lanes > 2) {
7044                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7045                                       pipe_config->fdi_lanes);
7046                         return -EINVAL;
7047                 } else {
7048                         return 0;
7049                 }
7050         }
7051
7052         if (INTEL_INFO(dev)->num_pipes == 2)
7053                 return 0;
7054
7055         /* Ivybridge 3 pipe is really complicated */
7056         switch (pipe) {
7057         case PIPE_A:
7058                 return 0;
7059         case PIPE_B:
7060                 if (pipe_config->fdi_lanes <= 2)
7061                         return 0;
7062
7063                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
7064                 other_crtc_state =
7065                         intel_atomic_get_crtc_state(state, other_crtc);
7066                 if (IS_ERR(other_crtc_state))
7067                         return PTR_ERR(other_crtc_state);
7068
7069                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7070                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7071                                       pipe_name(pipe), pipe_config->fdi_lanes);
7072                         return -EINVAL;
7073                 }
7074                 return 0;
7075         case PIPE_C:
7076                 if (pipe_config->fdi_lanes > 2) {
7077                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7078                                       pipe_name(pipe), pipe_config->fdi_lanes);
7079                         return -EINVAL;
7080                 }
7081
7082                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
7083                 other_crtc_state =
7084                         intel_atomic_get_crtc_state(state, other_crtc);
7085                 if (IS_ERR(other_crtc_state))
7086                         return PTR_ERR(other_crtc_state);
7087
7088                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7089                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7090                         return -EINVAL;
7091                 }
7092                 return 0;
7093         default:
7094                 BUG();
7095         }
7096 }
7097
7098 #define RETRY 1
7099 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7100                                        struct intel_crtc_state *pipe_config)
7101 {
7102         struct drm_device *dev = intel_crtc->base.dev;
7103         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7104         int lane, link_bw, fdi_dotclock, ret;
7105         bool needs_recompute = false;
7106
7107 retry:
7108         /* FDI is a binary signal running at ~2.7GHz, encoding
7109          * each output octet as 10 bits. The actual frequency
7110          * is stored as a divider into a 100MHz clock, and the
7111          * mode pixel clock is stored in units of 1KHz.
7112          * Hence the bw of each lane in terms of the mode signal
7113          * is:
7114          */
7115         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7116
7117         fdi_dotclock = adjusted_mode->crtc_clock;
7118
7119         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7120                                            pipe_config->pipe_bpp);
7121
7122         pipe_config->fdi_lanes = lane;
7123
7124         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7125                                link_bw, &pipe_config->fdi_m_n);
7126
7127         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7128         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7129                 pipe_config->pipe_bpp -= 2*3;
7130                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7131                               pipe_config->pipe_bpp);
7132                 needs_recompute = true;
7133                 pipe_config->bw_constrained = true;
7134
7135                 goto retry;
7136         }
7137
7138         if (needs_recompute)
7139                 return RETRY;
7140
7141         return ret;
7142 }
7143
7144 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7145                                      struct intel_crtc_state *pipe_config)
7146 {
7147         if (pipe_config->pipe_bpp > 24)
7148                 return false;
7149
7150         /* HSW can handle pixel rate up to cdclk? */
7151         if (IS_HASWELL(dev_priv))
7152                 return true;
7153
7154         /*
7155          * We compare against max which means we must take
7156          * the increased cdclk requirement into account when
7157          * calculating the new cdclk.
7158          *
7159          * Should measure whether using a lower cdclk w/o IPS
7160          */
7161         return ilk_pipe_pixel_rate(pipe_config) <=
7162                 dev_priv->max_cdclk_freq * 95 / 100;
7163 }
7164
7165 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7166                                    struct intel_crtc_state *pipe_config)
7167 {
7168         struct drm_device *dev = crtc->base.dev;
7169         struct drm_i915_private *dev_priv = to_i915(dev);
7170
7171         pipe_config->ips_enabled = i915.enable_ips &&
7172                 hsw_crtc_supports_ips(crtc) &&
7173                 pipe_config_supports_ips(dev_priv, pipe_config);
7174 }
7175
7176 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7177 {
7178         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7179
7180         /* GDG double wide on either pipe, otherwise pipe A only */
7181         return INTEL_INFO(dev_priv)->gen < 4 &&
7182                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7183 }
7184
7185 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7186                                      struct intel_crtc_state *pipe_config)
7187 {
7188         struct drm_device *dev = crtc->base.dev;
7189         struct drm_i915_private *dev_priv = to_i915(dev);
7190         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7191         int clock_limit = dev_priv->max_dotclk_freq;
7192
7193         if (INTEL_INFO(dev)->gen < 4) {
7194                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7195
7196                 /*
7197                  * Enable double wide mode when the dot clock
7198                  * is > 90% of the (display) core speed.
7199                  */
7200                 if (intel_crtc_supports_double_wide(crtc) &&
7201                     adjusted_mode->crtc_clock > clock_limit) {
7202                         clock_limit = dev_priv->max_dotclk_freq;
7203                         pipe_config->double_wide = true;
7204                 }
7205         }
7206
7207         if (adjusted_mode->crtc_clock > clock_limit) {
7208                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7209                               adjusted_mode->crtc_clock, clock_limit,
7210                               yesno(pipe_config->double_wide));
7211                 return -EINVAL;
7212         }
7213
7214         /*
7215          * Pipe horizontal size must be even in:
7216          * - DVO ganged mode
7217          * - LVDS dual channel mode
7218          * - Double wide pipe
7219          */
7220         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7221              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7222                 pipe_config->pipe_src_w &= ~1;
7223
7224         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7225          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7226          */
7227         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
7228                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7229                 return -EINVAL;
7230
7231         if (HAS_IPS(dev))
7232                 hsw_compute_ips_config(crtc, pipe_config);
7233
7234         if (pipe_config->has_pch_encoder)
7235                 return ironlake_fdi_compute_config(crtc, pipe_config);
7236
7237         return 0;
7238 }
7239
7240 static int skylake_get_display_clock_speed(struct drm_device *dev)
7241 {
7242         struct drm_i915_private *dev_priv = to_i915(dev);
7243         uint32_t cdctl;
7244
7245         skl_dpll0_update(dev_priv);
7246
7247         if (dev_priv->cdclk_pll.vco == 0)
7248                 return dev_priv->cdclk_pll.ref;
7249
7250         cdctl = I915_READ(CDCLK_CTL);
7251
7252         if (dev_priv->cdclk_pll.vco == 8640000) {
7253                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7254                 case CDCLK_FREQ_450_432:
7255                         return 432000;
7256                 case CDCLK_FREQ_337_308:
7257                         return 308571;
7258                 case CDCLK_FREQ_540:
7259                         return 540000;
7260                 case CDCLK_FREQ_675_617:
7261                         return 617143;
7262                 default:
7263                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7264                 }
7265         } else {
7266                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7267                 case CDCLK_FREQ_450_432:
7268                         return 450000;
7269                 case CDCLK_FREQ_337_308:
7270                         return 337500;
7271                 case CDCLK_FREQ_540:
7272                         return 540000;
7273                 case CDCLK_FREQ_675_617:
7274                         return 675000;
7275                 default:
7276                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7277                 }
7278         }
7279
7280         return dev_priv->cdclk_pll.ref;
7281 }
7282
7283 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7284 {
7285         u32 val;
7286
7287         dev_priv->cdclk_pll.ref = 19200;
7288         dev_priv->cdclk_pll.vco = 0;
7289
7290         val = I915_READ(BXT_DE_PLL_ENABLE);
7291         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7292                 return;
7293
7294         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7295                 return;
7296
7297         val = I915_READ(BXT_DE_PLL_CTL);
7298         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7299                 dev_priv->cdclk_pll.ref;
7300 }
7301
7302 static int broxton_get_display_clock_speed(struct drm_device *dev)
7303 {
7304         struct drm_i915_private *dev_priv = to_i915(dev);
7305         u32 divider;
7306         int div, vco;
7307
7308         bxt_de_pll_update(dev_priv);
7309
7310         vco = dev_priv->cdclk_pll.vco;
7311         if (vco == 0)
7312                 return dev_priv->cdclk_pll.ref;
7313
7314         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7315
7316         switch (divider) {
7317         case BXT_CDCLK_CD2X_DIV_SEL_1:
7318                 div = 2;
7319                 break;
7320         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7321                 div = 3;
7322                 break;
7323         case BXT_CDCLK_CD2X_DIV_SEL_2:
7324                 div = 4;
7325                 break;
7326         case BXT_CDCLK_CD2X_DIV_SEL_4:
7327                 div = 8;
7328                 break;
7329         default:
7330                 MISSING_CASE(divider);
7331                 return dev_priv->cdclk_pll.ref;
7332         }
7333
7334         return DIV_ROUND_CLOSEST(vco, div);
7335 }
7336
7337 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7338 {
7339         struct drm_i915_private *dev_priv = to_i915(dev);
7340         uint32_t lcpll = I915_READ(LCPLL_CTL);
7341         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7342
7343         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7344                 return 800000;
7345         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7346                 return 450000;
7347         else if (freq == LCPLL_CLK_FREQ_450)
7348                 return 450000;
7349         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7350                 return 540000;
7351         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7352                 return 337500;
7353         else
7354                 return 675000;
7355 }
7356
7357 static int haswell_get_display_clock_speed(struct drm_device *dev)
7358 {
7359         struct drm_i915_private *dev_priv = to_i915(dev);
7360         uint32_t lcpll = I915_READ(LCPLL_CTL);
7361         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7362
7363         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7364                 return 800000;
7365         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7366                 return 450000;
7367         else if (freq == LCPLL_CLK_FREQ_450)
7368                 return 450000;
7369         else if (IS_HSW_ULT(dev))
7370                 return 337500;
7371         else
7372                 return 540000;
7373 }
7374
7375 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7376 {
7377         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7378                                       CCK_DISPLAY_CLOCK_CONTROL);
7379 }
7380
7381 static int ilk_get_display_clock_speed(struct drm_device *dev)
7382 {
7383         return 450000;
7384 }
7385
7386 static int i945_get_display_clock_speed(struct drm_device *dev)
7387 {
7388         return 400000;
7389 }
7390
7391 static int i915_get_display_clock_speed(struct drm_device *dev)
7392 {
7393         return 333333;
7394 }
7395
7396 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7397 {
7398         return 200000;
7399 }
7400
7401 static int pnv_get_display_clock_speed(struct drm_device *dev)
7402 {
7403         struct pci_dev *pdev = dev->pdev;
7404         u16 gcfgc = 0;
7405
7406         pci_read_config_word(pdev, GCFGC, &gcfgc);
7407
7408         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7409         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7410                 return 266667;
7411         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7412                 return 333333;
7413         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7414                 return 444444;
7415         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7416                 return 200000;
7417         default:
7418                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7419         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7420                 return 133333;
7421         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7422                 return 166667;
7423         }
7424 }
7425
7426 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7427 {
7428         struct pci_dev *pdev = dev->pdev;
7429         u16 gcfgc = 0;
7430
7431         pci_read_config_word(pdev, GCFGC, &gcfgc);
7432
7433         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7434                 return 133333;
7435         else {
7436                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7437                 case GC_DISPLAY_CLOCK_333_MHZ:
7438                         return 333333;
7439                 default:
7440                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7441                         return 190000;
7442                 }
7443         }
7444 }
7445
7446 static int i865_get_display_clock_speed(struct drm_device *dev)
7447 {
7448         return 266667;
7449 }
7450
7451 static int i85x_get_display_clock_speed(struct drm_device *dev)
7452 {
7453         struct pci_dev *pdev = dev->pdev;
7454         u16 hpllcc = 0;
7455
7456         /*
7457          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7458          * encoding is different :(
7459          * FIXME is this the right way to detect 852GM/852GMV?
7460          */
7461         if (pdev->revision == 0x1)
7462                 return 133333;
7463
7464         pci_bus_read_config_word(pdev->bus,
7465                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7466
7467         /* Assume that the hardware is in the high speed state.  This
7468          * should be the default.
7469          */
7470         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7471         case GC_CLOCK_133_200:
7472         case GC_CLOCK_133_200_2:
7473         case GC_CLOCK_100_200:
7474                 return 200000;
7475         case GC_CLOCK_166_250:
7476                 return 250000;
7477         case GC_CLOCK_100_133:
7478                 return 133333;
7479         case GC_CLOCK_133_266:
7480         case GC_CLOCK_133_266_2:
7481         case GC_CLOCK_166_266:
7482                 return 266667;
7483         }
7484
7485         /* Shouldn't happen */
7486         return 0;
7487 }
7488
7489 static int i830_get_display_clock_speed(struct drm_device *dev)
7490 {
7491         return 133333;
7492 }
7493
7494 static unsigned int intel_hpll_vco(struct drm_device *dev)
7495 {
7496         struct drm_i915_private *dev_priv = to_i915(dev);
7497         static const unsigned int blb_vco[8] = {
7498                 [0] = 3200000,
7499                 [1] = 4000000,
7500                 [2] = 5333333,
7501                 [3] = 4800000,
7502                 [4] = 6400000,
7503         };
7504         static const unsigned int pnv_vco[8] = {
7505                 [0] = 3200000,
7506                 [1] = 4000000,
7507                 [2] = 5333333,
7508                 [3] = 4800000,
7509                 [4] = 2666667,
7510         };
7511         static const unsigned int cl_vco[8] = {
7512                 [0] = 3200000,
7513                 [1] = 4000000,
7514                 [2] = 5333333,
7515                 [3] = 6400000,
7516                 [4] = 3333333,
7517                 [5] = 3566667,
7518                 [6] = 4266667,
7519         };
7520         static const unsigned int elk_vco[8] = {
7521                 [0] = 3200000,
7522                 [1] = 4000000,
7523                 [2] = 5333333,
7524                 [3] = 4800000,
7525         };
7526         static const unsigned int ctg_vco[8] = {
7527                 [0] = 3200000,
7528                 [1] = 4000000,
7529                 [2] = 5333333,
7530                 [3] = 6400000,
7531                 [4] = 2666667,
7532                 [5] = 4266667,
7533         };
7534         const unsigned int *vco_table;
7535         unsigned int vco;
7536         uint8_t tmp = 0;
7537
7538         /* FIXME other chipsets? */
7539         if (IS_GM45(dev))
7540                 vco_table = ctg_vco;
7541         else if (IS_G4X(dev))
7542                 vco_table = elk_vco;
7543         else if (IS_CRESTLINE(dev))
7544                 vco_table = cl_vco;
7545         else if (IS_PINEVIEW(dev))
7546                 vco_table = pnv_vco;
7547         else if (IS_G33(dev))
7548                 vco_table = blb_vco;
7549         else
7550                 return 0;
7551
7552         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7553
7554         vco = vco_table[tmp & 0x7];
7555         if (vco == 0)
7556                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7557         else
7558                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7559
7560         return vco;
7561 }
7562
7563 static int gm45_get_display_clock_speed(struct drm_device *dev)
7564 {
7565         struct pci_dev *pdev = dev->pdev;
7566         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7567         uint16_t tmp = 0;
7568
7569         pci_read_config_word(pdev, GCFGC, &tmp);
7570
7571         cdclk_sel = (tmp >> 12) & 0x1;
7572
7573         switch (vco) {
7574         case 2666667:
7575         case 4000000:
7576         case 5333333:
7577                 return cdclk_sel ? 333333 : 222222;
7578         case 3200000:
7579                 return cdclk_sel ? 320000 : 228571;
7580         default:
7581                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7582                 return 222222;
7583         }
7584 }
7585
7586 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7587 {
7588         struct pci_dev *pdev = dev->pdev;
7589         static const uint8_t div_3200[] = { 16, 10,  8 };
7590         static const uint8_t div_4000[] = { 20, 12, 10 };
7591         static const uint8_t div_5333[] = { 24, 16, 14 };
7592         const uint8_t *div_table;
7593         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7594         uint16_t tmp = 0;
7595
7596         pci_read_config_word(pdev, GCFGC, &tmp);
7597
7598         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7599
7600         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7601                 goto fail;
7602
7603         switch (vco) {
7604         case 3200000:
7605                 div_table = div_3200;
7606                 break;
7607         case 4000000:
7608                 div_table = div_4000;
7609                 break;
7610         case 5333333:
7611                 div_table = div_5333;
7612                 break;
7613         default:
7614                 goto fail;
7615         }
7616
7617         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7618
7619 fail:
7620         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7621         return 200000;
7622 }
7623
7624 static int g33_get_display_clock_speed(struct drm_device *dev)
7625 {
7626         struct pci_dev *pdev = dev->pdev;
7627         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7628         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7629         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7630         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7631         const uint8_t *div_table;
7632         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7633         uint16_t tmp = 0;
7634
7635         pci_read_config_word(pdev, GCFGC, &tmp);
7636
7637         cdclk_sel = (tmp >> 4) & 0x7;
7638
7639         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7640                 goto fail;
7641
7642         switch (vco) {
7643         case 3200000:
7644                 div_table = div_3200;
7645                 break;
7646         case 4000000:
7647                 div_table = div_4000;
7648                 break;
7649         case 4800000:
7650                 div_table = div_4800;
7651                 break;
7652         case 5333333:
7653                 div_table = div_5333;
7654                 break;
7655         default:
7656                 goto fail;
7657         }
7658
7659         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7660
7661 fail:
7662         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7663         return 190476;
7664 }
7665
7666 static void
7667 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7668 {
7669         while (*num > DATA_LINK_M_N_MASK ||
7670                *den > DATA_LINK_M_N_MASK) {
7671                 *num >>= 1;
7672                 *den >>= 1;
7673         }
7674 }
7675
7676 static void compute_m_n(unsigned int m, unsigned int n,
7677                         uint32_t *ret_m, uint32_t *ret_n)
7678 {
7679         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7680         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7681         intel_reduce_m_n_ratio(ret_m, ret_n);
7682 }
7683
7684 void
7685 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7686                        int pixel_clock, int link_clock,
7687                        struct intel_link_m_n *m_n)
7688 {
7689         m_n->tu = 64;
7690
7691         compute_m_n(bits_per_pixel * pixel_clock,
7692                     link_clock * nlanes * 8,
7693                     &m_n->gmch_m, &m_n->gmch_n);
7694
7695         compute_m_n(pixel_clock, link_clock,
7696                     &m_n->link_m, &m_n->link_n);
7697 }
7698
7699 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7700 {
7701         if (i915.panel_use_ssc >= 0)
7702                 return i915.panel_use_ssc != 0;
7703         return dev_priv->vbt.lvds_use_ssc
7704                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7705 }
7706
7707 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7708 {
7709         return (1 << dpll->n) << 16 | dpll->m2;
7710 }
7711
7712 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7713 {
7714         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7715 }
7716
7717 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7718                                      struct intel_crtc_state *crtc_state,
7719                                      struct dpll *reduced_clock)
7720 {
7721         struct drm_device *dev = crtc->base.dev;
7722         u32 fp, fp2 = 0;
7723
7724         if (IS_PINEVIEW(dev)) {
7725                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7726                 if (reduced_clock)
7727                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7728         } else {
7729                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7730                 if (reduced_clock)
7731                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7732         }
7733
7734         crtc_state->dpll_hw_state.fp0 = fp;
7735
7736         crtc->lowfreq_avail = false;
7737         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7738             reduced_clock) {
7739                 crtc_state->dpll_hw_state.fp1 = fp2;
7740                 crtc->lowfreq_avail = true;
7741         } else {
7742                 crtc_state->dpll_hw_state.fp1 = fp;
7743         }
7744 }
7745
7746 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7747                 pipe)
7748 {
7749         u32 reg_val;
7750
7751         /*
7752          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7753          * and set it to a reasonable value instead.
7754          */
7755         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7756         reg_val &= 0xffffff00;
7757         reg_val |= 0x00000030;
7758         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7759
7760         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7761         reg_val &= 0x8cffffff;
7762         reg_val = 0x8c000000;
7763         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7764
7765         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7766         reg_val &= 0xffffff00;
7767         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7768
7769         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7770         reg_val &= 0x00ffffff;
7771         reg_val |= 0xb0000000;
7772         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7773 }
7774
7775 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7776                                          struct intel_link_m_n *m_n)
7777 {
7778         struct drm_device *dev = crtc->base.dev;
7779         struct drm_i915_private *dev_priv = to_i915(dev);
7780         int pipe = crtc->pipe;
7781
7782         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7783         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7784         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7785         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7786 }
7787
7788 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7789                                          struct intel_link_m_n *m_n,
7790                                          struct intel_link_m_n *m2_n2)
7791 {
7792         struct drm_device *dev = crtc->base.dev;
7793         struct drm_i915_private *dev_priv = to_i915(dev);
7794         int pipe = crtc->pipe;
7795         enum transcoder transcoder = crtc->config->cpu_transcoder;
7796
7797         if (INTEL_INFO(dev)->gen >= 5) {
7798                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7799                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7800                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7801                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7802                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7803                  * for gen < 8) and if DRRS is supported (to make sure the
7804                  * registers are not unnecessarily accessed).
7805                  */
7806                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7807                         crtc->config->has_drrs) {
7808                         I915_WRITE(PIPE_DATA_M2(transcoder),
7809                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7810                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7811                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7812                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7813                 }
7814         } else {
7815                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7816                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7817                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7818                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7819         }
7820 }
7821
7822 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7823 {
7824         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7825
7826         if (m_n == M1_N1) {
7827                 dp_m_n = &crtc->config->dp_m_n;
7828                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7829         } else if (m_n == M2_N2) {
7830
7831                 /*
7832                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7833                  * needs to be programmed into M1_N1.
7834                  */
7835                 dp_m_n = &crtc->config->dp_m2_n2;
7836         } else {
7837                 DRM_ERROR("Unsupported divider value\n");
7838                 return;
7839         }
7840
7841         if (crtc->config->has_pch_encoder)
7842                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7843         else
7844                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7845 }
7846
7847 static void vlv_compute_dpll(struct intel_crtc *crtc,
7848                              struct intel_crtc_state *pipe_config)
7849 {
7850         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7851                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7852         if (crtc->pipe != PIPE_A)
7853                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7854
7855         /* DPLL not used with DSI, but still need the rest set up */
7856         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7857                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7858                         DPLL_EXT_BUFFER_ENABLE_VLV;
7859
7860         pipe_config->dpll_hw_state.dpll_md =
7861                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7862 }
7863
7864 static void chv_compute_dpll(struct intel_crtc *crtc,
7865                              struct intel_crtc_state *pipe_config)
7866 {
7867         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7868                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7869         if (crtc->pipe != PIPE_A)
7870                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7871
7872         /* DPLL not used with DSI, but still need the rest set up */
7873         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7874                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7875
7876         pipe_config->dpll_hw_state.dpll_md =
7877                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7878 }
7879
7880 static void vlv_prepare_pll(struct intel_crtc *crtc,
7881                             const struct intel_crtc_state *pipe_config)
7882 {
7883         struct drm_device *dev = crtc->base.dev;
7884         struct drm_i915_private *dev_priv = to_i915(dev);
7885         enum pipe pipe = crtc->pipe;
7886         u32 mdiv;
7887         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7888         u32 coreclk, reg_val;
7889
7890         /* Enable Refclk */
7891         I915_WRITE(DPLL(pipe),
7892                    pipe_config->dpll_hw_state.dpll &
7893                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7894
7895         /* No need to actually set up the DPLL with DSI */
7896         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7897                 return;
7898
7899         mutex_lock(&dev_priv->sb_lock);
7900
7901         bestn = pipe_config->dpll.n;
7902         bestm1 = pipe_config->dpll.m1;
7903         bestm2 = pipe_config->dpll.m2;
7904         bestp1 = pipe_config->dpll.p1;
7905         bestp2 = pipe_config->dpll.p2;
7906
7907         /* See eDP HDMI DPIO driver vbios notes doc */
7908
7909         /* PLL B needs special handling */
7910         if (pipe == PIPE_B)
7911                 vlv_pllb_recal_opamp(dev_priv, pipe);
7912
7913         /* Set up Tx target for periodic Rcomp update */
7914         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7915
7916         /* Disable target IRef on PLL */
7917         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7918         reg_val &= 0x00ffffff;
7919         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7920
7921         /* Disable fast lock */
7922         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7923
7924         /* Set idtafcrecal before PLL is enabled */
7925         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7926         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7927         mdiv |= ((bestn << DPIO_N_SHIFT));
7928         mdiv |= (1 << DPIO_K_SHIFT);
7929
7930         /*
7931          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7932          * but we don't support that).
7933          * Note: don't use the DAC post divider as it seems unstable.
7934          */
7935         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7936         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7937
7938         mdiv |= DPIO_ENABLE_CALIBRATION;
7939         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7940
7941         /* Set HBR and RBR LPF coefficients */
7942         if (pipe_config->port_clock == 162000 ||
7943             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7944             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7945                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7946                                  0x009f0003);
7947         else
7948                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7949                                  0x00d0000f);
7950
7951         if (intel_crtc_has_dp_encoder(pipe_config)) {
7952                 /* Use SSC source */
7953                 if (pipe == PIPE_A)
7954                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7955                                          0x0df40000);
7956                 else
7957                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7958                                          0x0df70000);
7959         } else { /* HDMI or VGA */
7960                 /* Use bend source */
7961                 if (pipe == PIPE_A)
7962                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7963                                          0x0df70000);
7964                 else
7965                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7966                                          0x0df40000);
7967         }
7968
7969         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7970         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7971         if (intel_crtc_has_dp_encoder(crtc->config))
7972                 coreclk |= 0x01000000;
7973         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7974
7975         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7976         mutex_unlock(&dev_priv->sb_lock);
7977 }
7978
7979 static void chv_prepare_pll(struct intel_crtc *crtc,
7980                             const struct intel_crtc_state *pipe_config)
7981 {
7982         struct drm_device *dev = crtc->base.dev;
7983         struct drm_i915_private *dev_priv = to_i915(dev);
7984         enum pipe pipe = crtc->pipe;
7985         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7986         u32 loopfilter, tribuf_calcntr;
7987         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7988         u32 dpio_val;
7989         int vco;
7990
7991         /* Enable Refclk and SSC */
7992         I915_WRITE(DPLL(pipe),
7993                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7994
7995         /* No need to actually set up the DPLL with DSI */
7996         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7997                 return;
7998
7999         bestn = pipe_config->dpll.n;
8000         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8001         bestm1 = pipe_config->dpll.m1;
8002         bestm2 = pipe_config->dpll.m2 >> 22;
8003         bestp1 = pipe_config->dpll.p1;
8004         bestp2 = pipe_config->dpll.p2;
8005         vco = pipe_config->dpll.vco;
8006         dpio_val = 0;
8007         loopfilter = 0;
8008
8009         mutex_lock(&dev_priv->sb_lock);
8010
8011         /* p1 and p2 divider */
8012         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8013                         5 << DPIO_CHV_S1_DIV_SHIFT |
8014                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8015                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8016                         1 << DPIO_CHV_K_DIV_SHIFT);
8017
8018         /* Feedback post-divider - m2 */
8019         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8020
8021         /* Feedback refclk divider - n and m1 */
8022         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8023                         DPIO_CHV_M1_DIV_BY_2 |
8024                         1 << DPIO_CHV_N_DIV_SHIFT);
8025
8026         /* M2 fraction division */
8027         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8028
8029         /* M2 fraction division enable */
8030         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8031         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8032         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8033         if (bestm2_frac)
8034                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8035         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8036
8037         /* Program digital lock detect threshold */
8038         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8039         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8040                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8041         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8042         if (!bestm2_frac)
8043                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8044         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8045
8046         /* Loop filter */
8047         if (vco == 5400000) {
8048                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8049                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8050                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8051                 tribuf_calcntr = 0x9;
8052         } else if (vco <= 6200000) {
8053                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8054                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8055                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8056                 tribuf_calcntr = 0x9;
8057         } else if (vco <= 6480000) {
8058                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8059                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8060                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8061                 tribuf_calcntr = 0x8;
8062         } else {
8063                 /* Not supported. Apply the same limits as in the max case */
8064                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8065                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8066                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8067                 tribuf_calcntr = 0;
8068         }
8069         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8070
8071         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8072         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8073         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8074         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8075
8076         /* AFC Recal */
8077         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8078                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8079                         DPIO_AFC_RECAL);
8080
8081         mutex_unlock(&dev_priv->sb_lock);
8082 }
8083
8084 /**
8085  * vlv_force_pll_on - forcibly enable just the PLL
8086  * @dev_priv: i915 private structure
8087  * @pipe: pipe PLL to enable
8088  * @dpll: PLL configuration
8089  *
8090  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8091  * in cases where we need the PLL enabled even when @pipe is not going to
8092  * be enabled.
8093  */
8094 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
8095                      const struct dpll *dpll)
8096 {
8097         struct intel_crtc *crtc =
8098                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
8099         struct intel_crtc_state *pipe_config;
8100
8101         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8102         if (!pipe_config)
8103                 return -ENOMEM;
8104
8105         pipe_config->base.crtc = &crtc->base;
8106         pipe_config->pixel_multiplier = 1;
8107         pipe_config->dpll = *dpll;
8108
8109         if (IS_CHERRYVIEW(dev)) {
8110                 chv_compute_dpll(crtc, pipe_config);
8111                 chv_prepare_pll(crtc, pipe_config);
8112                 chv_enable_pll(crtc, pipe_config);
8113         } else {
8114                 vlv_compute_dpll(crtc, pipe_config);
8115                 vlv_prepare_pll(crtc, pipe_config);
8116                 vlv_enable_pll(crtc, pipe_config);
8117         }
8118
8119         kfree(pipe_config);
8120
8121         return 0;
8122 }
8123
8124 /**
8125  * vlv_force_pll_off - forcibly disable just the PLL
8126  * @dev_priv: i915 private structure
8127  * @pipe: pipe PLL to disable
8128  *
8129  * Disable the PLL for @pipe. To be used in cases where we need
8130  * the PLL enabled even when @pipe is not going to be enabled.
8131  */
8132 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8133 {
8134         if (IS_CHERRYVIEW(dev))
8135                 chv_disable_pll(to_i915(dev), pipe);
8136         else
8137                 vlv_disable_pll(to_i915(dev), pipe);
8138 }
8139
8140 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8141                               struct intel_crtc_state *crtc_state,
8142                               struct dpll *reduced_clock)
8143 {
8144         struct drm_device *dev = crtc->base.dev;
8145         struct drm_i915_private *dev_priv = to_i915(dev);
8146         u32 dpll;
8147         struct dpll *clock = &crtc_state->dpll;
8148
8149         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8150
8151         dpll = DPLL_VGA_MODE_DIS;
8152
8153         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8154                 dpll |= DPLLB_MODE_LVDS;
8155         else
8156                 dpll |= DPLLB_MODE_DAC_SERIAL;
8157
8158         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8159                 dpll |= (crtc_state->pixel_multiplier - 1)
8160                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8161         }
8162
8163         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8164             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8165                 dpll |= DPLL_SDVO_HIGH_SPEED;
8166
8167         if (intel_crtc_has_dp_encoder(crtc_state))
8168                 dpll |= DPLL_SDVO_HIGH_SPEED;
8169
8170         /* compute bitmask from p1 value */
8171         if (IS_PINEVIEW(dev))
8172                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8173         else {
8174                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8175                 if (IS_G4X(dev) && reduced_clock)
8176                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8177         }
8178         switch (clock->p2) {
8179         case 5:
8180                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8181                 break;
8182         case 7:
8183                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8184                 break;
8185         case 10:
8186                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8187                 break;
8188         case 14:
8189                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8190                 break;
8191         }
8192         if (INTEL_INFO(dev)->gen >= 4)
8193                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8194
8195         if (crtc_state->sdvo_tv_clock)
8196                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8197         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8198                  intel_panel_use_ssc(dev_priv))
8199                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8200         else
8201                 dpll |= PLL_REF_INPUT_DREFCLK;
8202
8203         dpll |= DPLL_VCO_ENABLE;
8204         crtc_state->dpll_hw_state.dpll = dpll;
8205
8206         if (INTEL_INFO(dev)->gen >= 4) {
8207                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8208                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8209                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8210         }
8211 }
8212
8213 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8214                               struct intel_crtc_state *crtc_state,
8215                               struct dpll *reduced_clock)
8216 {
8217         struct drm_device *dev = crtc->base.dev;
8218         struct drm_i915_private *dev_priv = to_i915(dev);
8219         u32 dpll;
8220         struct dpll *clock = &crtc_state->dpll;
8221
8222         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8223
8224         dpll = DPLL_VGA_MODE_DIS;
8225
8226         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8227                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8228         } else {
8229                 if (clock->p1 == 2)
8230                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8231                 else
8232                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8233                 if (clock->p2 == 4)
8234                         dpll |= PLL_P2_DIVIDE_BY_4;
8235         }
8236
8237         if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8238                 dpll |= DPLL_DVO_2X_MODE;
8239
8240         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8241             intel_panel_use_ssc(dev_priv))
8242                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8243         else
8244                 dpll |= PLL_REF_INPUT_DREFCLK;
8245
8246         dpll |= DPLL_VCO_ENABLE;
8247         crtc_state->dpll_hw_state.dpll = dpll;
8248 }
8249
8250 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8251 {
8252         struct drm_device *dev = intel_crtc->base.dev;
8253         struct drm_i915_private *dev_priv = to_i915(dev);
8254         enum pipe pipe = intel_crtc->pipe;
8255         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8256         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8257         uint32_t crtc_vtotal, crtc_vblank_end;
8258         int vsyncshift = 0;
8259
8260         /* We need to be careful not to changed the adjusted mode, for otherwise
8261          * the hw state checker will get angry at the mismatch. */
8262         crtc_vtotal = adjusted_mode->crtc_vtotal;
8263         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8264
8265         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8266                 /* the chip adds 2 halflines automatically */
8267                 crtc_vtotal -= 1;
8268                 crtc_vblank_end -= 1;
8269
8270                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8271                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8272                 else
8273                         vsyncshift = adjusted_mode->crtc_hsync_start -
8274                                 adjusted_mode->crtc_htotal / 2;
8275                 if (vsyncshift < 0)
8276                         vsyncshift += adjusted_mode->crtc_htotal;
8277         }
8278
8279         if (INTEL_INFO(dev)->gen > 3)
8280                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8281
8282         I915_WRITE(HTOTAL(cpu_transcoder),
8283                    (adjusted_mode->crtc_hdisplay - 1) |
8284                    ((adjusted_mode->crtc_htotal - 1) << 16));
8285         I915_WRITE(HBLANK(cpu_transcoder),
8286                    (adjusted_mode->crtc_hblank_start - 1) |
8287                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8288         I915_WRITE(HSYNC(cpu_transcoder),
8289                    (adjusted_mode->crtc_hsync_start - 1) |
8290                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8291
8292         I915_WRITE(VTOTAL(cpu_transcoder),
8293                    (adjusted_mode->crtc_vdisplay - 1) |
8294                    ((crtc_vtotal - 1) << 16));
8295         I915_WRITE(VBLANK(cpu_transcoder),
8296                    (adjusted_mode->crtc_vblank_start - 1) |
8297                    ((crtc_vblank_end - 1) << 16));
8298         I915_WRITE(VSYNC(cpu_transcoder),
8299                    (adjusted_mode->crtc_vsync_start - 1) |
8300                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8301
8302         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8303          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8304          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8305          * bits. */
8306         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
8307             (pipe == PIPE_B || pipe == PIPE_C))
8308                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8309
8310 }
8311
8312 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8313 {
8314         struct drm_device *dev = intel_crtc->base.dev;
8315         struct drm_i915_private *dev_priv = to_i915(dev);
8316         enum pipe pipe = intel_crtc->pipe;
8317
8318         /* pipesrc controls the size that is scaled from, which should
8319          * always be the user's requested size.
8320          */
8321         I915_WRITE(PIPESRC(pipe),
8322                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8323                    (intel_crtc->config->pipe_src_h - 1));
8324 }
8325
8326 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8327                                    struct intel_crtc_state *pipe_config)
8328 {
8329         struct drm_device *dev = crtc->base.dev;
8330         struct drm_i915_private *dev_priv = to_i915(dev);
8331         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8332         uint32_t tmp;
8333
8334         tmp = I915_READ(HTOTAL(cpu_transcoder));
8335         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8336         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8337         tmp = I915_READ(HBLANK(cpu_transcoder));
8338         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8339         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8340         tmp = I915_READ(HSYNC(cpu_transcoder));
8341         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8342         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8343
8344         tmp = I915_READ(VTOTAL(cpu_transcoder));
8345         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8346         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8347         tmp = I915_READ(VBLANK(cpu_transcoder));
8348         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8349         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8350         tmp = I915_READ(VSYNC(cpu_transcoder));
8351         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8352         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8353
8354         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8355                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8356                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8357                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8358         }
8359 }
8360
8361 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8362                                     struct intel_crtc_state *pipe_config)
8363 {
8364         struct drm_device *dev = crtc->base.dev;
8365         struct drm_i915_private *dev_priv = to_i915(dev);
8366         u32 tmp;
8367
8368         tmp = I915_READ(PIPESRC(crtc->pipe));
8369         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8370         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8371
8372         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8373         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8374 }
8375
8376 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8377                                  struct intel_crtc_state *pipe_config)
8378 {
8379         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8380         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8381         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8382         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8383
8384         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8385         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8386         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8387         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8388
8389         mode->flags = pipe_config->base.adjusted_mode.flags;
8390         mode->type = DRM_MODE_TYPE_DRIVER;
8391
8392         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8393         mode->flags |= pipe_config->base.adjusted_mode.flags;
8394
8395         mode->hsync = drm_mode_hsync(mode);
8396         mode->vrefresh = drm_mode_vrefresh(mode);
8397         drm_mode_set_name(mode);
8398 }
8399
8400 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8401 {
8402         struct drm_device *dev = intel_crtc->base.dev;
8403         struct drm_i915_private *dev_priv = to_i915(dev);
8404         uint32_t pipeconf;
8405
8406         pipeconf = 0;
8407
8408         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8409             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8410                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8411
8412         if (intel_crtc->config->double_wide)
8413                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8414
8415         /* only g4x and later have fancy bpc/dither controls */
8416         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8417                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8418                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8419                         pipeconf |= PIPECONF_DITHER_EN |
8420                                     PIPECONF_DITHER_TYPE_SP;
8421
8422                 switch (intel_crtc->config->pipe_bpp) {
8423                 case 18:
8424                         pipeconf |= PIPECONF_6BPC;
8425                         break;
8426                 case 24:
8427                         pipeconf |= PIPECONF_8BPC;
8428                         break;
8429                 case 30:
8430                         pipeconf |= PIPECONF_10BPC;
8431                         break;
8432                 default:
8433                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8434                         BUG();
8435                 }
8436         }
8437
8438         if (HAS_PIPE_CXSR(dev)) {
8439                 if (intel_crtc->lowfreq_avail) {
8440                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8441                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8442                 } else {
8443                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8444                 }
8445         }
8446
8447         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8448                 if (INTEL_INFO(dev)->gen < 4 ||
8449                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8450                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8451                 else
8452                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8453         } else
8454                 pipeconf |= PIPECONF_PROGRESSIVE;
8455
8456         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8457              intel_crtc->config->limited_color_range)
8458                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8459
8460         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8461         POSTING_READ(PIPECONF(intel_crtc->pipe));
8462 }
8463
8464 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8465                                    struct intel_crtc_state *crtc_state)
8466 {
8467         struct drm_device *dev = crtc->base.dev;
8468         struct drm_i915_private *dev_priv = to_i915(dev);
8469         const struct intel_limit *limit;
8470         int refclk = 48000;
8471
8472         memset(&crtc_state->dpll_hw_state, 0,
8473                sizeof(crtc_state->dpll_hw_state));
8474
8475         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8476                 if (intel_panel_use_ssc(dev_priv)) {
8477                         refclk = dev_priv->vbt.lvds_ssc_freq;
8478                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8479                 }
8480
8481                 limit = &intel_limits_i8xx_lvds;
8482         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8483                 limit = &intel_limits_i8xx_dvo;
8484         } else {
8485                 limit = &intel_limits_i8xx_dac;
8486         }
8487
8488         if (!crtc_state->clock_set &&
8489             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8490                                  refclk, NULL, &crtc_state->dpll)) {
8491                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8492                 return -EINVAL;
8493         }
8494
8495         i8xx_compute_dpll(crtc, crtc_state, NULL);
8496
8497         return 0;
8498 }
8499
8500 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8501                                   struct intel_crtc_state *crtc_state)
8502 {
8503         struct drm_device *dev = crtc->base.dev;
8504         struct drm_i915_private *dev_priv = to_i915(dev);
8505         const struct intel_limit *limit;
8506         int refclk = 96000;
8507
8508         memset(&crtc_state->dpll_hw_state, 0,
8509                sizeof(crtc_state->dpll_hw_state));
8510
8511         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8512                 if (intel_panel_use_ssc(dev_priv)) {
8513                         refclk = dev_priv->vbt.lvds_ssc_freq;
8514                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8515                 }
8516
8517                 if (intel_is_dual_link_lvds(dev))
8518                         limit = &intel_limits_g4x_dual_channel_lvds;
8519                 else
8520                         limit = &intel_limits_g4x_single_channel_lvds;
8521         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8522                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8523                 limit = &intel_limits_g4x_hdmi;
8524         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8525                 limit = &intel_limits_g4x_sdvo;
8526         } else {
8527                 /* The option is for other outputs */
8528                 limit = &intel_limits_i9xx_sdvo;
8529         }
8530
8531         if (!crtc_state->clock_set &&
8532             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8533                                 refclk, NULL, &crtc_state->dpll)) {
8534                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8535                 return -EINVAL;
8536         }
8537
8538         i9xx_compute_dpll(crtc, crtc_state, NULL);
8539
8540         return 0;
8541 }
8542
8543 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8544                                   struct intel_crtc_state *crtc_state)
8545 {
8546         struct drm_device *dev = crtc->base.dev;
8547         struct drm_i915_private *dev_priv = to_i915(dev);
8548         const struct intel_limit *limit;
8549         int refclk = 96000;
8550
8551         memset(&crtc_state->dpll_hw_state, 0,
8552                sizeof(crtc_state->dpll_hw_state));
8553
8554         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8555                 if (intel_panel_use_ssc(dev_priv)) {
8556                         refclk = dev_priv->vbt.lvds_ssc_freq;
8557                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8558                 }
8559
8560                 limit = &intel_limits_pineview_lvds;
8561         } else {
8562                 limit = &intel_limits_pineview_sdvo;
8563         }
8564
8565         if (!crtc_state->clock_set &&
8566             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8567                                 refclk, NULL, &crtc_state->dpll)) {
8568                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8569                 return -EINVAL;
8570         }
8571
8572         i9xx_compute_dpll(crtc, crtc_state, NULL);
8573
8574         return 0;
8575 }
8576
8577 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8578                                    struct intel_crtc_state *crtc_state)
8579 {
8580         struct drm_device *dev = crtc->base.dev;
8581         struct drm_i915_private *dev_priv = to_i915(dev);
8582         const struct intel_limit *limit;
8583         int refclk = 96000;
8584
8585         memset(&crtc_state->dpll_hw_state, 0,
8586                sizeof(crtc_state->dpll_hw_state));
8587
8588         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8589                 if (intel_panel_use_ssc(dev_priv)) {
8590                         refclk = dev_priv->vbt.lvds_ssc_freq;
8591                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8592                 }
8593
8594                 limit = &intel_limits_i9xx_lvds;
8595         } else {
8596                 limit = &intel_limits_i9xx_sdvo;
8597         }
8598
8599         if (!crtc_state->clock_set &&
8600             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8601                                  refclk, NULL, &crtc_state->dpll)) {
8602                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8603                 return -EINVAL;
8604         }
8605
8606         i9xx_compute_dpll(crtc, crtc_state, NULL);
8607
8608         return 0;
8609 }
8610
8611 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8612                                   struct intel_crtc_state *crtc_state)
8613 {
8614         int refclk = 100000;
8615         const struct intel_limit *limit = &intel_limits_chv;
8616
8617         memset(&crtc_state->dpll_hw_state, 0,
8618                sizeof(crtc_state->dpll_hw_state));
8619
8620         if (!crtc_state->clock_set &&
8621             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8622                                 refclk, NULL, &crtc_state->dpll)) {
8623                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8624                 return -EINVAL;
8625         }
8626
8627         chv_compute_dpll(crtc, crtc_state);
8628
8629         return 0;
8630 }
8631
8632 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8633                                   struct intel_crtc_state *crtc_state)
8634 {
8635         int refclk = 100000;
8636         const struct intel_limit *limit = &intel_limits_vlv;
8637
8638         memset(&crtc_state->dpll_hw_state, 0,
8639                sizeof(crtc_state->dpll_hw_state));
8640
8641         if (!crtc_state->clock_set &&
8642             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8643                                 refclk, NULL, &crtc_state->dpll)) {
8644                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8645                 return -EINVAL;
8646         }
8647
8648         vlv_compute_dpll(crtc, crtc_state);
8649
8650         return 0;
8651 }
8652
8653 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8654                                  struct intel_crtc_state *pipe_config)
8655 {
8656         struct drm_device *dev = crtc->base.dev;
8657         struct drm_i915_private *dev_priv = to_i915(dev);
8658         uint32_t tmp;
8659
8660         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8661                 return;
8662
8663         tmp = I915_READ(PFIT_CONTROL);
8664         if (!(tmp & PFIT_ENABLE))
8665                 return;
8666
8667         /* Check whether the pfit is attached to our pipe. */
8668         if (INTEL_INFO(dev)->gen < 4) {
8669                 if (crtc->pipe != PIPE_B)
8670                         return;
8671         } else {
8672                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8673                         return;
8674         }
8675
8676         pipe_config->gmch_pfit.control = tmp;
8677         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8678 }
8679
8680 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8681                                struct intel_crtc_state *pipe_config)
8682 {
8683         struct drm_device *dev = crtc->base.dev;
8684         struct drm_i915_private *dev_priv = to_i915(dev);
8685         int pipe = pipe_config->cpu_transcoder;
8686         struct dpll clock;
8687         u32 mdiv;
8688         int refclk = 100000;
8689
8690         /* In case of DSI, DPLL will not be used */
8691         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8692                 return;
8693
8694         mutex_lock(&dev_priv->sb_lock);
8695         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8696         mutex_unlock(&dev_priv->sb_lock);
8697
8698         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8699         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8700         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8701         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8702         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8703
8704         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8705 }
8706
8707 static void
8708 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8709                               struct intel_initial_plane_config *plane_config)
8710 {
8711         struct drm_device *dev = crtc->base.dev;
8712         struct drm_i915_private *dev_priv = to_i915(dev);
8713         u32 val, base, offset;
8714         int pipe = crtc->pipe, plane = crtc->plane;
8715         int fourcc, pixel_format;
8716         unsigned int aligned_height;
8717         struct drm_framebuffer *fb;
8718         struct intel_framebuffer *intel_fb;
8719
8720         val = I915_READ(DSPCNTR(plane));
8721         if (!(val & DISPLAY_PLANE_ENABLE))
8722                 return;
8723
8724         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8725         if (!intel_fb) {
8726                 DRM_DEBUG_KMS("failed to alloc fb\n");
8727                 return;
8728         }
8729
8730         fb = &intel_fb->base;
8731
8732         if (INTEL_INFO(dev)->gen >= 4) {
8733                 if (val & DISPPLANE_TILED) {
8734                         plane_config->tiling = I915_TILING_X;
8735                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8736                 }
8737         }
8738
8739         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8740         fourcc = i9xx_format_to_fourcc(pixel_format);
8741         fb->pixel_format = fourcc;
8742         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8743
8744         if (INTEL_INFO(dev)->gen >= 4) {
8745                 if (plane_config->tiling)
8746                         offset = I915_READ(DSPTILEOFF(plane));
8747                 else
8748                         offset = I915_READ(DSPLINOFF(plane));
8749                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8750         } else {
8751                 base = I915_READ(DSPADDR(plane));
8752         }
8753         plane_config->base = base;
8754
8755         val = I915_READ(PIPESRC(pipe));
8756         fb->width = ((val >> 16) & 0xfff) + 1;
8757         fb->height = ((val >> 0) & 0xfff) + 1;
8758
8759         val = I915_READ(DSPSTRIDE(pipe));
8760         fb->pitches[0] = val & 0xffffffc0;
8761
8762         aligned_height = intel_fb_align_height(dev, fb->height,
8763                                                fb->pixel_format,
8764                                                fb->modifier[0]);
8765
8766         plane_config->size = fb->pitches[0] * aligned_height;
8767
8768         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8769                       pipe_name(pipe), plane, fb->width, fb->height,
8770                       fb->bits_per_pixel, base, fb->pitches[0],
8771                       plane_config->size);
8772
8773         plane_config->fb = intel_fb;
8774 }
8775
8776 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8777                                struct intel_crtc_state *pipe_config)
8778 {
8779         struct drm_device *dev = crtc->base.dev;
8780         struct drm_i915_private *dev_priv = to_i915(dev);
8781         int pipe = pipe_config->cpu_transcoder;
8782         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8783         struct dpll clock;
8784         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8785         int refclk = 100000;
8786
8787         /* In case of DSI, DPLL will not be used */
8788         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8789                 return;
8790
8791         mutex_lock(&dev_priv->sb_lock);
8792         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8793         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8794         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8795         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8796         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8797         mutex_unlock(&dev_priv->sb_lock);
8798
8799         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8800         clock.m2 = (pll_dw0 & 0xff) << 22;
8801         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8802                 clock.m2 |= pll_dw2 & 0x3fffff;
8803         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8804         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8805         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8806
8807         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8808 }
8809
8810 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8811                                  struct intel_crtc_state *pipe_config)
8812 {
8813         struct drm_device *dev = crtc->base.dev;
8814         struct drm_i915_private *dev_priv = to_i915(dev);
8815         enum intel_display_power_domain power_domain;
8816         uint32_t tmp;
8817         bool ret;
8818
8819         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8820         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8821                 return false;
8822
8823         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8824         pipe_config->shared_dpll = NULL;
8825
8826         ret = false;
8827
8828         tmp = I915_READ(PIPECONF(crtc->pipe));
8829         if (!(tmp & PIPECONF_ENABLE))
8830                 goto out;
8831
8832         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8833                 switch (tmp & PIPECONF_BPC_MASK) {
8834                 case PIPECONF_6BPC:
8835                         pipe_config->pipe_bpp = 18;
8836                         break;
8837                 case PIPECONF_8BPC:
8838                         pipe_config->pipe_bpp = 24;
8839                         break;
8840                 case PIPECONF_10BPC:
8841                         pipe_config->pipe_bpp = 30;
8842                         break;
8843                 default:
8844                         break;
8845                 }
8846         }
8847
8848         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8849             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8850                 pipe_config->limited_color_range = true;
8851
8852         if (INTEL_INFO(dev)->gen < 4)
8853                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8854
8855         intel_get_pipe_timings(crtc, pipe_config);
8856         intel_get_pipe_src_size(crtc, pipe_config);
8857
8858         i9xx_get_pfit_config(crtc, pipe_config);
8859
8860         if (INTEL_INFO(dev)->gen >= 4) {
8861                 /* No way to read it out on pipes B and C */
8862                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8863                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8864                 else
8865                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8866                 pipe_config->pixel_multiplier =
8867                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8868                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8869                 pipe_config->dpll_hw_state.dpll_md = tmp;
8870         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8871                 tmp = I915_READ(DPLL(crtc->pipe));
8872                 pipe_config->pixel_multiplier =
8873                         ((tmp & SDVO_MULTIPLIER_MASK)
8874                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8875         } else {
8876                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8877                  * port and will be fixed up in the encoder->get_config
8878                  * function. */
8879                 pipe_config->pixel_multiplier = 1;
8880         }
8881         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8882         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8883                 /*
8884                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8885                  * on 830. Filter it out here so that we don't
8886                  * report errors due to that.
8887                  */
8888                 if (IS_I830(dev))
8889                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8890
8891                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8892                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8893         } else {
8894                 /* Mask out read-only status bits. */
8895                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8896                                                      DPLL_PORTC_READY_MASK |
8897                                                      DPLL_PORTB_READY_MASK);
8898         }
8899
8900         if (IS_CHERRYVIEW(dev))
8901                 chv_crtc_clock_get(crtc, pipe_config);
8902         else if (IS_VALLEYVIEW(dev))
8903                 vlv_crtc_clock_get(crtc, pipe_config);
8904         else
8905                 i9xx_crtc_clock_get(crtc, pipe_config);
8906
8907         /*
8908          * Normally the dotclock is filled in by the encoder .get_config()
8909          * but in case the pipe is enabled w/o any ports we need a sane
8910          * default.
8911          */
8912         pipe_config->base.adjusted_mode.crtc_clock =
8913                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8914
8915         ret = true;
8916
8917 out:
8918         intel_display_power_put(dev_priv, power_domain);
8919
8920         return ret;
8921 }
8922
8923 static void ironlake_init_pch_refclk(struct drm_device *dev)
8924 {
8925         struct drm_i915_private *dev_priv = to_i915(dev);
8926         struct intel_encoder *encoder;
8927         int i;
8928         u32 val, final;
8929         bool has_lvds = false;
8930         bool has_cpu_edp = false;
8931         bool has_panel = false;
8932         bool has_ck505 = false;
8933         bool can_ssc = false;
8934         bool using_ssc_source = false;
8935
8936         /* We need to take the global config into account */
8937         for_each_intel_encoder(dev, encoder) {
8938                 switch (encoder->type) {
8939                 case INTEL_OUTPUT_LVDS:
8940                         has_panel = true;
8941                         has_lvds = true;
8942                         break;
8943                 case INTEL_OUTPUT_EDP:
8944                         has_panel = true;
8945                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8946                                 has_cpu_edp = true;
8947                         break;
8948                 default:
8949                         break;
8950                 }
8951         }
8952
8953         if (HAS_PCH_IBX(dev)) {
8954                 has_ck505 = dev_priv->vbt.display_clock_mode;
8955                 can_ssc = has_ck505;
8956         } else {
8957                 has_ck505 = false;
8958                 can_ssc = true;
8959         }
8960
8961         /* Check if any DPLLs are using the SSC source */
8962         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8963                 u32 temp = I915_READ(PCH_DPLL(i));
8964
8965                 if (!(temp & DPLL_VCO_ENABLE))
8966                         continue;
8967
8968                 if ((temp & PLL_REF_INPUT_MASK) ==
8969                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8970                         using_ssc_source = true;
8971                         break;
8972                 }
8973         }
8974
8975         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8976                       has_panel, has_lvds, has_ck505, using_ssc_source);
8977
8978         /* Ironlake: try to setup display ref clock before DPLL
8979          * enabling. This is only under driver's control after
8980          * PCH B stepping, previous chipset stepping should be
8981          * ignoring this setting.
8982          */
8983         val = I915_READ(PCH_DREF_CONTROL);
8984
8985         /* As we must carefully and slowly disable/enable each source in turn,
8986          * compute the final state we want first and check if we need to
8987          * make any changes at all.
8988          */
8989         final = val;
8990         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8991         if (has_ck505)
8992                 final |= DREF_NONSPREAD_CK505_ENABLE;
8993         else
8994                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8995
8996         final &= ~DREF_SSC_SOURCE_MASK;
8997         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8998         final &= ~DREF_SSC1_ENABLE;
8999
9000         if (has_panel) {
9001                 final |= DREF_SSC_SOURCE_ENABLE;
9002
9003                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9004                         final |= DREF_SSC1_ENABLE;
9005
9006                 if (has_cpu_edp) {
9007                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9008                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9009                         else
9010                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9011                 } else
9012                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9013         } else if (using_ssc_source) {
9014                 final |= DREF_SSC_SOURCE_ENABLE;
9015                 final |= DREF_SSC1_ENABLE;
9016         }
9017
9018         if (final == val)
9019                 return;
9020
9021         /* Always enable nonspread source */
9022         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9023
9024         if (has_ck505)
9025                 val |= DREF_NONSPREAD_CK505_ENABLE;
9026         else
9027                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9028
9029         if (has_panel) {
9030                 val &= ~DREF_SSC_SOURCE_MASK;
9031                 val |= DREF_SSC_SOURCE_ENABLE;
9032
9033                 /* SSC must be turned on before enabling the CPU output  */
9034                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9035                         DRM_DEBUG_KMS("Using SSC on panel\n");
9036                         val |= DREF_SSC1_ENABLE;
9037                 } else
9038                         val &= ~DREF_SSC1_ENABLE;
9039
9040                 /* Get SSC going before enabling the outputs */
9041                 I915_WRITE(PCH_DREF_CONTROL, val);
9042                 POSTING_READ(PCH_DREF_CONTROL);
9043                 udelay(200);
9044
9045                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9046
9047                 /* Enable CPU source on CPU attached eDP */
9048                 if (has_cpu_edp) {
9049                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9050                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9051                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9052                         } else
9053                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9054                 } else
9055                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9056
9057                 I915_WRITE(PCH_DREF_CONTROL, val);
9058                 POSTING_READ(PCH_DREF_CONTROL);
9059                 udelay(200);
9060         } else {
9061                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9062
9063                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9064
9065                 /* Turn off CPU output */
9066                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9067
9068                 I915_WRITE(PCH_DREF_CONTROL, val);
9069                 POSTING_READ(PCH_DREF_CONTROL);
9070                 udelay(200);
9071
9072                 if (!using_ssc_source) {
9073                         DRM_DEBUG_KMS("Disabling SSC source\n");
9074
9075                         /* Turn off the SSC source */
9076                         val &= ~DREF_SSC_SOURCE_MASK;
9077                         val |= DREF_SSC_SOURCE_DISABLE;
9078
9079                         /* Turn off SSC1 */
9080                         val &= ~DREF_SSC1_ENABLE;
9081
9082                         I915_WRITE(PCH_DREF_CONTROL, val);
9083                         POSTING_READ(PCH_DREF_CONTROL);
9084                         udelay(200);
9085                 }
9086         }
9087
9088         BUG_ON(val != final);
9089 }
9090
9091 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9092 {
9093         uint32_t tmp;
9094
9095         tmp = I915_READ(SOUTH_CHICKEN2);
9096         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9097         I915_WRITE(SOUTH_CHICKEN2, tmp);
9098
9099         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9100                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9101                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9102
9103         tmp = I915_READ(SOUTH_CHICKEN2);
9104         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9105         I915_WRITE(SOUTH_CHICKEN2, tmp);
9106
9107         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9108                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9109                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9110 }
9111
9112 /* WaMPhyProgramming:hsw */
9113 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9114 {
9115         uint32_t tmp;
9116
9117         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9118         tmp &= ~(0xFF << 24);
9119         tmp |= (0x12 << 24);
9120         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9121
9122         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9123         tmp |= (1 << 11);
9124         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9125
9126         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9127         tmp |= (1 << 11);
9128         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9129
9130         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9131         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9132         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9133
9134         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9135         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9136         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9137
9138         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9139         tmp &= ~(7 << 13);
9140         tmp |= (5 << 13);
9141         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9142
9143         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9144         tmp &= ~(7 << 13);
9145         tmp |= (5 << 13);
9146         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9147
9148         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9149         tmp &= ~0xFF;
9150         tmp |= 0x1C;
9151         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9152
9153         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9154         tmp &= ~0xFF;
9155         tmp |= 0x1C;
9156         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9157
9158         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9159         tmp &= ~(0xFF << 16);
9160         tmp |= (0x1C << 16);
9161         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9162
9163         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9164         tmp &= ~(0xFF << 16);
9165         tmp |= (0x1C << 16);
9166         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9167
9168         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9169         tmp |= (1 << 27);
9170         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9171
9172         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9173         tmp |= (1 << 27);
9174         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9175
9176         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9177         tmp &= ~(0xF << 28);
9178         tmp |= (4 << 28);
9179         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9180
9181         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9182         tmp &= ~(0xF << 28);
9183         tmp |= (4 << 28);
9184         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9185 }
9186
9187 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9188  * Programming" based on the parameters passed:
9189  * - Sequence to enable CLKOUT_DP
9190  * - Sequence to enable CLKOUT_DP without spread
9191  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9192  */
9193 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9194                                  bool with_fdi)
9195 {
9196         struct drm_i915_private *dev_priv = to_i915(dev);
9197         uint32_t reg, tmp;
9198
9199         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9200                 with_spread = true;
9201         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
9202                 with_fdi = false;
9203
9204         mutex_lock(&dev_priv->sb_lock);
9205
9206         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9207         tmp &= ~SBI_SSCCTL_DISABLE;
9208         tmp |= SBI_SSCCTL_PATHALT;
9209         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9210
9211         udelay(24);
9212
9213         if (with_spread) {
9214                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9215                 tmp &= ~SBI_SSCCTL_PATHALT;
9216                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9217
9218                 if (with_fdi) {
9219                         lpt_reset_fdi_mphy(dev_priv);
9220                         lpt_program_fdi_mphy(dev_priv);
9221                 }
9222         }
9223
9224         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9225         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9226         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9227         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9228
9229         mutex_unlock(&dev_priv->sb_lock);
9230 }
9231
9232 /* Sequence to disable CLKOUT_DP */
9233 static void lpt_disable_clkout_dp(struct drm_device *dev)
9234 {
9235         struct drm_i915_private *dev_priv = to_i915(dev);
9236         uint32_t reg, tmp;
9237
9238         mutex_lock(&dev_priv->sb_lock);
9239
9240         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9241         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9242         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9243         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9244
9245         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9246         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9247                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9248                         tmp |= SBI_SSCCTL_PATHALT;
9249                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9250                         udelay(32);
9251                 }
9252                 tmp |= SBI_SSCCTL_DISABLE;
9253                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9254         }
9255
9256         mutex_unlock(&dev_priv->sb_lock);
9257 }
9258
9259 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9260
9261 static const uint16_t sscdivintphase[] = {
9262         [BEND_IDX( 50)] = 0x3B23,
9263         [BEND_IDX( 45)] = 0x3B23,
9264         [BEND_IDX( 40)] = 0x3C23,
9265         [BEND_IDX( 35)] = 0x3C23,
9266         [BEND_IDX( 30)] = 0x3D23,
9267         [BEND_IDX( 25)] = 0x3D23,
9268         [BEND_IDX( 20)] = 0x3E23,
9269         [BEND_IDX( 15)] = 0x3E23,
9270         [BEND_IDX( 10)] = 0x3F23,
9271         [BEND_IDX(  5)] = 0x3F23,
9272         [BEND_IDX(  0)] = 0x0025,
9273         [BEND_IDX( -5)] = 0x0025,
9274         [BEND_IDX(-10)] = 0x0125,
9275         [BEND_IDX(-15)] = 0x0125,
9276         [BEND_IDX(-20)] = 0x0225,
9277         [BEND_IDX(-25)] = 0x0225,
9278         [BEND_IDX(-30)] = 0x0325,
9279         [BEND_IDX(-35)] = 0x0325,
9280         [BEND_IDX(-40)] = 0x0425,
9281         [BEND_IDX(-45)] = 0x0425,
9282         [BEND_IDX(-50)] = 0x0525,
9283 };
9284
9285 /*
9286  * Bend CLKOUT_DP
9287  * steps -50 to 50 inclusive, in steps of 5
9288  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9289  * change in clock period = -(steps / 10) * 5.787 ps
9290  */
9291 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9292 {
9293         uint32_t tmp;
9294         int idx = BEND_IDX(steps);
9295
9296         if (WARN_ON(steps % 5 != 0))
9297                 return;
9298
9299         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9300                 return;
9301
9302         mutex_lock(&dev_priv->sb_lock);
9303
9304         if (steps % 10 != 0)
9305                 tmp = 0xAAAAAAAB;
9306         else
9307                 tmp = 0x00000000;
9308         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9309
9310         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9311         tmp &= 0xffff0000;
9312         tmp |= sscdivintphase[idx];
9313         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9314
9315         mutex_unlock(&dev_priv->sb_lock);
9316 }
9317
9318 #undef BEND_IDX
9319
9320 static void lpt_init_pch_refclk(struct drm_device *dev)
9321 {
9322         struct intel_encoder *encoder;
9323         bool has_vga = false;
9324
9325         for_each_intel_encoder(dev, encoder) {
9326                 switch (encoder->type) {
9327                 case INTEL_OUTPUT_ANALOG:
9328                         has_vga = true;
9329                         break;
9330                 default:
9331                         break;
9332                 }
9333         }
9334
9335         if (has_vga) {
9336                 lpt_bend_clkout_dp(to_i915(dev), 0);
9337                 lpt_enable_clkout_dp(dev, true, true);
9338         } else {
9339                 lpt_disable_clkout_dp(dev);
9340         }
9341 }
9342
9343 /*
9344  * Initialize reference clocks when the driver loads
9345  */
9346 void intel_init_pch_refclk(struct drm_device *dev)
9347 {
9348         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9349                 ironlake_init_pch_refclk(dev);
9350         else if (HAS_PCH_LPT(dev))
9351                 lpt_init_pch_refclk(dev);
9352 }
9353
9354 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9355 {
9356         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9358         int pipe = intel_crtc->pipe;
9359         uint32_t val;
9360
9361         val = 0;
9362
9363         switch (intel_crtc->config->pipe_bpp) {
9364         case 18:
9365                 val |= PIPECONF_6BPC;
9366                 break;
9367         case 24:
9368                 val |= PIPECONF_8BPC;
9369                 break;
9370         case 30:
9371                 val |= PIPECONF_10BPC;
9372                 break;
9373         case 36:
9374                 val |= PIPECONF_12BPC;
9375                 break;
9376         default:
9377                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9378                 BUG();
9379         }
9380
9381         if (intel_crtc->config->dither)
9382                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9383
9384         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9385                 val |= PIPECONF_INTERLACED_ILK;
9386         else
9387                 val |= PIPECONF_PROGRESSIVE;
9388
9389         if (intel_crtc->config->limited_color_range)
9390                 val |= PIPECONF_COLOR_RANGE_SELECT;
9391
9392         I915_WRITE(PIPECONF(pipe), val);
9393         POSTING_READ(PIPECONF(pipe));
9394 }
9395
9396 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9397 {
9398         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9400         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9401         u32 val = 0;
9402
9403         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9404                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9405
9406         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9407                 val |= PIPECONF_INTERLACED_ILK;
9408         else
9409                 val |= PIPECONF_PROGRESSIVE;
9410
9411         I915_WRITE(PIPECONF(cpu_transcoder), val);
9412         POSTING_READ(PIPECONF(cpu_transcoder));
9413 }
9414
9415 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9416 {
9417         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9419
9420         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9421                 u32 val = 0;
9422
9423                 switch (intel_crtc->config->pipe_bpp) {
9424                 case 18:
9425                         val |= PIPEMISC_DITHER_6_BPC;
9426                         break;
9427                 case 24:
9428                         val |= PIPEMISC_DITHER_8_BPC;
9429                         break;
9430                 case 30:
9431                         val |= PIPEMISC_DITHER_10_BPC;
9432                         break;
9433                 case 36:
9434                         val |= PIPEMISC_DITHER_12_BPC;
9435                         break;
9436                 default:
9437                         /* Case prevented by pipe_config_set_bpp. */
9438                         BUG();
9439                 }
9440
9441                 if (intel_crtc->config->dither)
9442                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9443
9444                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9445         }
9446 }
9447
9448 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9449 {
9450         /*
9451          * Account for spread spectrum to avoid
9452          * oversubscribing the link. Max center spread
9453          * is 2.5%; use 5% for safety's sake.
9454          */
9455         u32 bps = target_clock * bpp * 21 / 20;
9456         return DIV_ROUND_UP(bps, link_bw * 8);
9457 }
9458
9459 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9460 {
9461         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9462 }
9463
9464 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9465                                   struct intel_crtc_state *crtc_state,
9466                                   struct dpll *reduced_clock)
9467 {
9468         struct drm_crtc *crtc = &intel_crtc->base;
9469         struct drm_device *dev = crtc->dev;
9470         struct drm_i915_private *dev_priv = to_i915(dev);
9471         u32 dpll, fp, fp2;
9472         int factor;
9473
9474         /* Enable autotuning of the PLL clock (if permissible) */
9475         factor = 21;
9476         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9477                 if ((intel_panel_use_ssc(dev_priv) &&
9478                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9479                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9480                         factor = 25;
9481         } else if (crtc_state->sdvo_tv_clock)
9482                 factor = 20;
9483
9484         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9485
9486         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9487                 fp |= FP_CB_TUNE;
9488
9489         if (reduced_clock) {
9490                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9491
9492                 if (reduced_clock->m < factor * reduced_clock->n)
9493                         fp2 |= FP_CB_TUNE;
9494         } else {
9495                 fp2 = fp;
9496         }
9497
9498         dpll = 0;
9499
9500         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9501                 dpll |= DPLLB_MODE_LVDS;
9502         else
9503                 dpll |= DPLLB_MODE_DAC_SERIAL;
9504
9505         dpll |= (crtc_state->pixel_multiplier - 1)
9506                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9507
9508         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9509             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9510                 dpll |= DPLL_SDVO_HIGH_SPEED;
9511
9512         if (intel_crtc_has_dp_encoder(crtc_state))
9513                 dpll |= DPLL_SDVO_HIGH_SPEED;
9514
9515         /* compute bitmask from p1 value */
9516         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9517         /* also FPA1 */
9518         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9519
9520         switch (crtc_state->dpll.p2) {
9521         case 5:
9522                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9523                 break;
9524         case 7:
9525                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9526                 break;
9527         case 10:
9528                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9529                 break;
9530         case 14:
9531                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9532                 break;
9533         }
9534
9535         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9536             intel_panel_use_ssc(dev_priv))
9537                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9538         else
9539                 dpll |= PLL_REF_INPUT_DREFCLK;
9540
9541         dpll |= DPLL_VCO_ENABLE;
9542
9543         crtc_state->dpll_hw_state.dpll = dpll;
9544         crtc_state->dpll_hw_state.fp0 = fp;
9545         crtc_state->dpll_hw_state.fp1 = fp2;
9546 }
9547
9548 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9549                                        struct intel_crtc_state *crtc_state)
9550 {
9551         struct drm_device *dev = crtc->base.dev;
9552         struct drm_i915_private *dev_priv = to_i915(dev);
9553         struct dpll reduced_clock;
9554         bool has_reduced_clock = false;
9555         struct intel_shared_dpll *pll;
9556         const struct intel_limit *limit;
9557         int refclk = 120000;
9558
9559         memset(&crtc_state->dpll_hw_state, 0,
9560                sizeof(crtc_state->dpll_hw_state));
9561
9562         crtc->lowfreq_avail = false;
9563
9564         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9565         if (!crtc_state->has_pch_encoder)
9566                 return 0;
9567
9568         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9569                 if (intel_panel_use_ssc(dev_priv)) {
9570                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9571                                       dev_priv->vbt.lvds_ssc_freq);
9572                         refclk = dev_priv->vbt.lvds_ssc_freq;
9573                 }
9574
9575                 if (intel_is_dual_link_lvds(dev)) {
9576                         if (refclk == 100000)
9577                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9578                         else
9579                                 limit = &intel_limits_ironlake_dual_lvds;
9580                 } else {
9581                         if (refclk == 100000)
9582                                 limit = &intel_limits_ironlake_single_lvds_100m;
9583                         else
9584                                 limit = &intel_limits_ironlake_single_lvds;
9585                 }
9586         } else {
9587                 limit = &intel_limits_ironlake_dac;
9588         }
9589
9590         if (!crtc_state->clock_set &&
9591             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9592                                 refclk, NULL, &crtc_state->dpll)) {
9593                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9594                 return -EINVAL;
9595         }
9596
9597         ironlake_compute_dpll(crtc, crtc_state,
9598                               has_reduced_clock ? &reduced_clock : NULL);
9599
9600         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9601         if (pll == NULL) {
9602                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9603                                  pipe_name(crtc->pipe));
9604                 return -EINVAL;
9605         }
9606
9607         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9608             has_reduced_clock)
9609                 crtc->lowfreq_avail = true;
9610
9611         return 0;
9612 }
9613
9614 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9615                                          struct intel_link_m_n *m_n)
9616 {
9617         struct drm_device *dev = crtc->base.dev;
9618         struct drm_i915_private *dev_priv = to_i915(dev);
9619         enum pipe pipe = crtc->pipe;
9620
9621         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9622         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9623         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9624                 & ~TU_SIZE_MASK;
9625         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9626         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9627                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9628 }
9629
9630 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9631                                          enum transcoder transcoder,
9632                                          struct intel_link_m_n *m_n,
9633                                          struct intel_link_m_n *m2_n2)
9634 {
9635         struct drm_device *dev = crtc->base.dev;
9636         struct drm_i915_private *dev_priv = to_i915(dev);
9637         enum pipe pipe = crtc->pipe;
9638
9639         if (INTEL_INFO(dev)->gen >= 5) {
9640                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9641                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9642                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9643                         & ~TU_SIZE_MASK;
9644                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9645                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9646                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9647                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9648                  * gen < 8) and if DRRS is supported (to make sure the
9649                  * registers are not unnecessarily read).
9650                  */
9651                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9652                         crtc->config->has_drrs) {
9653                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9654                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9655                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9656                                         & ~TU_SIZE_MASK;
9657                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9658                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9659                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9660                 }
9661         } else {
9662                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9663                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9664                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9665                         & ~TU_SIZE_MASK;
9666                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9667                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9668                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9669         }
9670 }
9671
9672 void intel_dp_get_m_n(struct intel_crtc *crtc,
9673                       struct intel_crtc_state *pipe_config)
9674 {
9675         if (pipe_config->has_pch_encoder)
9676                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9677         else
9678                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9679                                              &pipe_config->dp_m_n,
9680                                              &pipe_config->dp_m2_n2);
9681 }
9682
9683 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9684                                         struct intel_crtc_state *pipe_config)
9685 {
9686         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9687                                      &pipe_config->fdi_m_n, NULL);
9688 }
9689
9690 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9691                                     struct intel_crtc_state *pipe_config)
9692 {
9693         struct drm_device *dev = crtc->base.dev;
9694         struct drm_i915_private *dev_priv = to_i915(dev);
9695         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9696         uint32_t ps_ctrl = 0;
9697         int id = -1;
9698         int i;
9699
9700         /* find scaler attached to this pipe */
9701         for (i = 0; i < crtc->num_scalers; i++) {
9702                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9703                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9704                         id = i;
9705                         pipe_config->pch_pfit.enabled = true;
9706                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9707                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9708                         break;
9709                 }
9710         }
9711
9712         scaler_state->scaler_id = id;
9713         if (id >= 0) {
9714                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9715         } else {
9716                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9717         }
9718 }
9719
9720 static void
9721 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9722                                  struct intel_initial_plane_config *plane_config)
9723 {
9724         struct drm_device *dev = crtc->base.dev;
9725         struct drm_i915_private *dev_priv = to_i915(dev);
9726         u32 val, base, offset, stride_mult, tiling;
9727         int pipe = crtc->pipe;
9728         int fourcc, pixel_format;
9729         unsigned int aligned_height;
9730         struct drm_framebuffer *fb;
9731         struct intel_framebuffer *intel_fb;
9732
9733         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9734         if (!intel_fb) {
9735                 DRM_DEBUG_KMS("failed to alloc fb\n");
9736                 return;
9737         }
9738
9739         fb = &intel_fb->base;
9740
9741         val = I915_READ(PLANE_CTL(pipe, 0));
9742         if (!(val & PLANE_CTL_ENABLE))
9743                 goto error;
9744
9745         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9746         fourcc = skl_format_to_fourcc(pixel_format,
9747                                       val & PLANE_CTL_ORDER_RGBX,
9748                                       val & PLANE_CTL_ALPHA_MASK);
9749         fb->pixel_format = fourcc;
9750         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9751
9752         tiling = val & PLANE_CTL_TILED_MASK;
9753         switch (tiling) {
9754         case PLANE_CTL_TILED_LINEAR:
9755                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9756                 break;
9757         case PLANE_CTL_TILED_X:
9758                 plane_config->tiling = I915_TILING_X;
9759                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9760                 break;
9761         case PLANE_CTL_TILED_Y:
9762                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9763                 break;
9764         case PLANE_CTL_TILED_YF:
9765                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9766                 break;
9767         default:
9768                 MISSING_CASE(tiling);
9769                 goto error;
9770         }
9771
9772         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9773         plane_config->base = base;
9774
9775         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9776
9777         val = I915_READ(PLANE_SIZE(pipe, 0));
9778         fb->height = ((val >> 16) & 0xfff) + 1;
9779         fb->width = ((val >> 0) & 0x1fff) + 1;
9780
9781         val = I915_READ(PLANE_STRIDE(pipe, 0));
9782         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9783                                                 fb->pixel_format);
9784         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9785
9786         aligned_height = intel_fb_align_height(dev, fb->height,
9787                                                fb->pixel_format,
9788                                                fb->modifier[0]);
9789
9790         plane_config->size = fb->pitches[0] * aligned_height;
9791
9792         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9793                       pipe_name(pipe), fb->width, fb->height,
9794                       fb->bits_per_pixel, base, fb->pitches[0],
9795                       plane_config->size);
9796
9797         plane_config->fb = intel_fb;
9798         return;
9799
9800 error:
9801         kfree(intel_fb);
9802 }
9803
9804 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9805                                      struct intel_crtc_state *pipe_config)
9806 {
9807         struct drm_device *dev = crtc->base.dev;
9808         struct drm_i915_private *dev_priv = to_i915(dev);
9809         uint32_t tmp;
9810
9811         tmp = I915_READ(PF_CTL(crtc->pipe));
9812
9813         if (tmp & PF_ENABLE) {
9814                 pipe_config->pch_pfit.enabled = true;
9815                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9816                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9817
9818                 /* We currently do not free assignements of panel fitters on
9819                  * ivb/hsw (since we don't use the higher upscaling modes which
9820                  * differentiates them) so just WARN about this case for now. */
9821                 if (IS_GEN7(dev)) {
9822                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9823                                 PF_PIPE_SEL_IVB(crtc->pipe));
9824                 }
9825         }
9826 }
9827
9828 static void
9829 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9830                                   struct intel_initial_plane_config *plane_config)
9831 {
9832         struct drm_device *dev = crtc->base.dev;
9833         struct drm_i915_private *dev_priv = to_i915(dev);
9834         u32 val, base, offset;
9835         int pipe = crtc->pipe;
9836         int fourcc, pixel_format;
9837         unsigned int aligned_height;
9838         struct drm_framebuffer *fb;
9839         struct intel_framebuffer *intel_fb;
9840
9841         val = I915_READ(DSPCNTR(pipe));
9842         if (!(val & DISPLAY_PLANE_ENABLE))
9843                 return;
9844
9845         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9846         if (!intel_fb) {
9847                 DRM_DEBUG_KMS("failed to alloc fb\n");
9848                 return;
9849         }
9850
9851         fb = &intel_fb->base;
9852
9853         if (INTEL_INFO(dev)->gen >= 4) {
9854                 if (val & DISPPLANE_TILED) {
9855                         plane_config->tiling = I915_TILING_X;
9856                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9857                 }
9858         }
9859
9860         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9861         fourcc = i9xx_format_to_fourcc(pixel_format);
9862         fb->pixel_format = fourcc;
9863         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9864
9865         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9866         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9867                 offset = I915_READ(DSPOFFSET(pipe));
9868         } else {
9869                 if (plane_config->tiling)
9870                         offset = I915_READ(DSPTILEOFF(pipe));
9871                 else
9872                         offset = I915_READ(DSPLINOFF(pipe));
9873         }
9874         plane_config->base = base;
9875
9876         val = I915_READ(PIPESRC(pipe));
9877         fb->width = ((val >> 16) & 0xfff) + 1;
9878         fb->height = ((val >> 0) & 0xfff) + 1;
9879
9880         val = I915_READ(DSPSTRIDE(pipe));
9881         fb->pitches[0] = val & 0xffffffc0;
9882
9883         aligned_height = intel_fb_align_height(dev, fb->height,
9884                                                fb->pixel_format,
9885                                                fb->modifier[0]);
9886
9887         plane_config->size = fb->pitches[0] * aligned_height;
9888
9889         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9890                       pipe_name(pipe), fb->width, fb->height,
9891                       fb->bits_per_pixel, base, fb->pitches[0],
9892                       plane_config->size);
9893
9894         plane_config->fb = intel_fb;
9895 }
9896
9897 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9898                                      struct intel_crtc_state *pipe_config)
9899 {
9900         struct drm_device *dev = crtc->base.dev;
9901         struct drm_i915_private *dev_priv = to_i915(dev);
9902         enum intel_display_power_domain power_domain;
9903         uint32_t tmp;
9904         bool ret;
9905
9906         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9907         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9908                 return false;
9909
9910         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9911         pipe_config->shared_dpll = NULL;
9912
9913         ret = false;
9914         tmp = I915_READ(PIPECONF(crtc->pipe));
9915         if (!(tmp & PIPECONF_ENABLE))
9916                 goto out;
9917
9918         switch (tmp & PIPECONF_BPC_MASK) {
9919         case PIPECONF_6BPC:
9920                 pipe_config->pipe_bpp = 18;
9921                 break;
9922         case PIPECONF_8BPC:
9923                 pipe_config->pipe_bpp = 24;
9924                 break;
9925         case PIPECONF_10BPC:
9926                 pipe_config->pipe_bpp = 30;
9927                 break;
9928         case PIPECONF_12BPC:
9929                 pipe_config->pipe_bpp = 36;
9930                 break;
9931         default:
9932                 break;
9933         }
9934
9935         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9936                 pipe_config->limited_color_range = true;
9937
9938         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9939                 struct intel_shared_dpll *pll;
9940                 enum intel_dpll_id pll_id;
9941
9942                 pipe_config->has_pch_encoder = true;
9943
9944                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9945                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9946                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9947
9948                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9949
9950                 if (HAS_PCH_IBX(dev_priv)) {
9951                         /*
9952                          * The pipe->pch transcoder and pch transcoder->pll
9953                          * mapping is fixed.
9954                          */
9955                         pll_id = (enum intel_dpll_id) crtc->pipe;
9956                 } else {
9957                         tmp = I915_READ(PCH_DPLL_SEL);
9958                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9959                                 pll_id = DPLL_ID_PCH_PLL_B;
9960                         else
9961                                 pll_id= DPLL_ID_PCH_PLL_A;
9962                 }
9963
9964                 pipe_config->shared_dpll =
9965                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9966                 pll = pipe_config->shared_dpll;
9967
9968                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9969                                                  &pipe_config->dpll_hw_state));
9970
9971                 tmp = pipe_config->dpll_hw_state.dpll;
9972                 pipe_config->pixel_multiplier =
9973                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9974                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9975
9976                 ironlake_pch_clock_get(crtc, pipe_config);
9977         } else {
9978                 pipe_config->pixel_multiplier = 1;
9979         }
9980
9981         intel_get_pipe_timings(crtc, pipe_config);
9982         intel_get_pipe_src_size(crtc, pipe_config);
9983
9984         ironlake_get_pfit_config(crtc, pipe_config);
9985
9986         ret = true;
9987
9988 out:
9989         intel_display_power_put(dev_priv, power_domain);
9990
9991         return ret;
9992 }
9993
9994 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9995 {
9996         struct drm_device *dev = &dev_priv->drm;
9997         struct intel_crtc *crtc;
9998
9999         for_each_intel_crtc(dev, crtc)
10000                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
10001                      pipe_name(crtc->pipe));
10002
10003         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10004         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10005         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10006         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10007         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10008         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10009              "CPU PWM1 enabled\n");
10010         if (IS_HASWELL(dev))
10011                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10012                      "CPU PWM2 enabled\n");
10013         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10014              "PCH PWM1 enabled\n");
10015         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10016              "Utility pin enabled\n");
10017         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10018
10019         /*
10020          * In theory we can still leave IRQs enabled, as long as only the HPD
10021          * interrupts remain enabled. We used to check for that, but since it's
10022          * gen-specific and since we only disable LCPLL after we fully disable
10023          * the interrupts, the check below should be enough.
10024          */
10025         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10026 }
10027
10028 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10029 {
10030         struct drm_device *dev = &dev_priv->drm;
10031
10032         if (IS_HASWELL(dev))
10033                 return I915_READ(D_COMP_HSW);
10034         else
10035                 return I915_READ(D_COMP_BDW);
10036 }
10037
10038 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10039 {
10040         struct drm_device *dev = &dev_priv->drm;
10041
10042         if (IS_HASWELL(dev)) {
10043                 mutex_lock(&dev_priv->rps.hw_lock);
10044                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10045                                             val))
10046                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10047                 mutex_unlock(&dev_priv->rps.hw_lock);
10048         } else {
10049                 I915_WRITE(D_COMP_BDW, val);
10050                 POSTING_READ(D_COMP_BDW);
10051         }
10052 }
10053
10054 /*
10055  * This function implements pieces of two sequences from BSpec:
10056  * - Sequence for display software to disable LCPLL
10057  * - Sequence for display software to allow package C8+
10058  * The steps implemented here are just the steps that actually touch the LCPLL
10059  * register. Callers should take care of disabling all the display engine
10060  * functions, doing the mode unset, fixing interrupts, etc.
10061  */
10062 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10063                               bool switch_to_fclk, bool allow_power_down)
10064 {
10065         uint32_t val;
10066
10067         assert_can_disable_lcpll(dev_priv);
10068
10069         val = I915_READ(LCPLL_CTL);
10070
10071         if (switch_to_fclk) {
10072                 val |= LCPLL_CD_SOURCE_FCLK;
10073                 I915_WRITE(LCPLL_CTL, val);
10074
10075                 if (wait_for_us(I915_READ(LCPLL_CTL) &
10076                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10077                         DRM_ERROR("Switching to FCLK failed\n");
10078
10079                 val = I915_READ(LCPLL_CTL);
10080         }
10081
10082         val |= LCPLL_PLL_DISABLE;
10083         I915_WRITE(LCPLL_CTL, val);
10084         POSTING_READ(LCPLL_CTL);
10085
10086         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10087                 DRM_ERROR("LCPLL still locked\n");
10088
10089         val = hsw_read_dcomp(dev_priv);
10090         val |= D_COMP_COMP_DISABLE;
10091         hsw_write_dcomp(dev_priv, val);
10092         ndelay(100);
10093
10094         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10095                      1))
10096                 DRM_ERROR("D_COMP RCOMP still in progress\n");
10097
10098         if (allow_power_down) {
10099                 val = I915_READ(LCPLL_CTL);
10100                 val |= LCPLL_POWER_DOWN_ALLOW;
10101                 I915_WRITE(LCPLL_CTL, val);
10102                 POSTING_READ(LCPLL_CTL);
10103         }
10104 }
10105
10106 /*
10107  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10108  * source.
10109  */
10110 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10111 {
10112         uint32_t val;
10113
10114         val = I915_READ(LCPLL_CTL);
10115
10116         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10117                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10118                 return;
10119
10120         /*
10121          * Make sure we're not on PC8 state before disabling PC8, otherwise
10122          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10123          */
10124         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10125
10126         if (val & LCPLL_POWER_DOWN_ALLOW) {
10127                 val &= ~LCPLL_POWER_DOWN_ALLOW;
10128                 I915_WRITE(LCPLL_CTL, val);
10129                 POSTING_READ(LCPLL_CTL);
10130         }
10131
10132         val = hsw_read_dcomp(dev_priv);
10133         val |= D_COMP_COMP_FORCE;
10134         val &= ~D_COMP_COMP_DISABLE;
10135         hsw_write_dcomp(dev_priv, val);
10136
10137         val = I915_READ(LCPLL_CTL);
10138         val &= ~LCPLL_PLL_DISABLE;
10139         I915_WRITE(LCPLL_CTL, val);
10140
10141         if (intel_wait_for_register(dev_priv,
10142                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10143                                     5))
10144                 DRM_ERROR("LCPLL not locked yet\n");
10145
10146         if (val & LCPLL_CD_SOURCE_FCLK) {
10147                 val = I915_READ(LCPLL_CTL);
10148                 val &= ~LCPLL_CD_SOURCE_FCLK;
10149                 I915_WRITE(LCPLL_CTL, val);
10150
10151                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10152                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10153                         DRM_ERROR("Switching back to LCPLL failed\n");
10154         }
10155
10156         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10157         intel_update_cdclk(&dev_priv->drm);
10158 }
10159
10160 /*
10161  * Package states C8 and deeper are really deep PC states that can only be
10162  * reached when all the devices on the system allow it, so even if the graphics
10163  * device allows PC8+, it doesn't mean the system will actually get to these
10164  * states. Our driver only allows PC8+ when going into runtime PM.
10165  *
10166  * The requirements for PC8+ are that all the outputs are disabled, the power
10167  * well is disabled and most interrupts are disabled, and these are also
10168  * requirements for runtime PM. When these conditions are met, we manually do
10169  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10170  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10171  * hang the machine.
10172  *
10173  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10174  * the state of some registers, so when we come back from PC8+ we need to
10175  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10176  * need to take care of the registers kept by RC6. Notice that this happens even
10177  * if we don't put the device in PCI D3 state (which is what currently happens
10178  * because of the runtime PM support).
10179  *
10180  * For more, read "Display Sequences for Package C8" on the hardware
10181  * documentation.
10182  */
10183 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10184 {
10185         struct drm_device *dev = &dev_priv->drm;
10186         uint32_t val;
10187
10188         DRM_DEBUG_KMS("Enabling package C8+\n");
10189
10190         if (HAS_PCH_LPT_LP(dev)) {
10191                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10192                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10193                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10194         }
10195
10196         lpt_disable_clkout_dp(dev);
10197         hsw_disable_lcpll(dev_priv, true, true);
10198 }
10199
10200 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10201 {
10202         struct drm_device *dev = &dev_priv->drm;
10203         uint32_t val;
10204
10205         DRM_DEBUG_KMS("Disabling package C8+\n");
10206
10207         hsw_restore_lcpll(dev_priv);
10208         lpt_init_pch_refclk(dev);
10209
10210         if (HAS_PCH_LPT_LP(dev)) {
10211                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10212                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10213                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10214         }
10215 }
10216
10217 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10218 {
10219         struct drm_device *dev = old_state->dev;
10220         struct intel_atomic_state *old_intel_state =
10221                 to_intel_atomic_state(old_state);
10222         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10223
10224         bxt_set_cdclk(to_i915(dev), req_cdclk);
10225 }
10226
10227 /* compute the max rate for new configuration */
10228 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10229 {
10230         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10231         struct drm_i915_private *dev_priv = to_i915(state->dev);
10232         struct drm_crtc *crtc;
10233         struct drm_crtc_state *cstate;
10234         struct intel_crtc_state *crtc_state;
10235         unsigned max_pixel_rate = 0, i;
10236         enum pipe pipe;
10237
10238         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10239                sizeof(intel_state->min_pixclk));
10240
10241         for_each_crtc_in_state(state, crtc, cstate, i) {
10242                 int pixel_rate;
10243
10244                 crtc_state = to_intel_crtc_state(cstate);
10245                 if (!crtc_state->base.enable) {
10246                         intel_state->min_pixclk[i] = 0;
10247                         continue;
10248                 }
10249
10250                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10251
10252                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10253                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10254                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10255
10256                 intel_state->min_pixclk[i] = pixel_rate;
10257         }
10258
10259         for_each_pipe(dev_priv, pipe)
10260                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10261
10262         return max_pixel_rate;
10263 }
10264
10265 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10266 {
10267         struct drm_i915_private *dev_priv = to_i915(dev);
10268         uint32_t val, data;
10269         int ret;
10270
10271         if (WARN((I915_READ(LCPLL_CTL) &
10272                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10273                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10274                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10275                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10276                  "trying to change cdclk frequency with cdclk not enabled\n"))
10277                 return;
10278
10279         mutex_lock(&dev_priv->rps.hw_lock);
10280         ret = sandybridge_pcode_write(dev_priv,
10281                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10282         mutex_unlock(&dev_priv->rps.hw_lock);
10283         if (ret) {
10284                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10285                 return;
10286         }
10287
10288         val = I915_READ(LCPLL_CTL);
10289         val |= LCPLL_CD_SOURCE_FCLK;
10290         I915_WRITE(LCPLL_CTL, val);
10291
10292         if (wait_for_us(I915_READ(LCPLL_CTL) &
10293                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10294                 DRM_ERROR("Switching to FCLK failed\n");
10295
10296         val = I915_READ(LCPLL_CTL);
10297         val &= ~LCPLL_CLK_FREQ_MASK;
10298
10299         switch (cdclk) {
10300         case 450000:
10301                 val |= LCPLL_CLK_FREQ_450;
10302                 data = 0;
10303                 break;
10304         case 540000:
10305                 val |= LCPLL_CLK_FREQ_54O_BDW;
10306                 data = 1;
10307                 break;
10308         case 337500:
10309                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10310                 data = 2;
10311                 break;
10312         case 675000:
10313                 val |= LCPLL_CLK_FREQ_675_BDW;
10314                 data = 3;
10315                 break;
10316         default:
10317                 WARN(1, "invalid cdclk frequency\n");
10318                 return;
10319         }
10320
10321         I915_WRITE(LCPLL_CTL, val);
10322
10323         val = I915_READ(LCPLL_CTL);
10324         val &= ~LCPLL_CD_SOURCE_FCLK;
10325         I915_WRITE(LCPLL_CTL, val);
10326
10327         if (wait_for_us((I915_READ(LCPLL_CTL) &
10328                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10329                 DRM_ERROR("Switching back to LCPLL failed\n");
10330
10331         mutex_lock(&dev_priv->rps.hw_lock);
10332         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10333         mutex_unlock(&dev_priv->rps.hw_lock);
10334
10335         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10336
10337         intel_update_cdclk(dev);
10338
10339         WARN(cdclk != dev_priv->cdclk_freq,
10340              "cdclk requested %d kHz but got %d kHz\n",
10341              cdclk, dev_priv->cdclk_freq);
10342 }
10343
10344 static int broadwell_calc_cdclk(int max_pixclk)
10345 {
10346         if (max_pixclk > 540000)
10347                 return 675000;
10348         else if (max_pixclk > 450000)
10349                 return 540000;
10350         else if (max_pixclk > 337500)
10351                 return 450000;
10352         else
10353                 return 337500;
10354 }
10355
10356 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10357 {
10358         struct drm_i915_private *dev_priv = to_i915(state->dev);
10359         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10360         int max_pixclk = ilk_max_pixel_rate(state);
10361         int cdclk;
10362
10363         /*
10364          * FIXME should also account for plane ratio
10365          * once 64bpp pixel formats are supported.
10366          */
10367         cdclk = broadwell_calc_cdclk(max_pixclk);
10368
10369         if (cdclk > dev_priv->max_cdclk_freq) {
10370                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10371                               cdclk, dev_priv->max_cdclk_freq);
10372                 return -EINVAL;
10373         }
10374
10375         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10376         if (!intel_state->active_crtcs)
10377                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10378
10379         return 0;
10380 }
10381
10382 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10383 {
10384         struct drm_device *dev = old_state->dev;
10385         struct intel_atomic_state *old_intel_state =
10386                 to_intel_atomic_state(old_state);
10387         unsigned req_cdclk = old_intel_state->dev_cdclk;
10388
10389         broadwell_set_cdclk(dev, req_cdclk);
10390 }
10391
10392 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10393 {
10394         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10395         struct drm_i915_private *dev_priv = to_i915(state->dev);
10396         const int max_pixclk = ilk_max_pixel_rate(state);
10397         int vco = intel_state->cdclk_pll_vco;
10398         int cdclk;
10399
10400         /*
10401          * FIXME should also account for plane ratio
10402          * once 64bpp pixel formats are supported.
10403          */
10404         cdclk = skl_calc_cdclk(max_pixclk, vco);
10405
10406         /*
10407          * FIXME move the cdclk caclulation to
10408          * compute_config() so we can fail gracegully.
10409          */
10410         if (cdclk > dev_priv->max_cdclk_freq) {
10411                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10412                           cdclk, dev_priv->max_cdclk_freq);
10413                 cdclk = dev_priv->max_cdclk_freq;
10414         }
10415
10416         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10417         if (!intel_state->active_crtcs)
10418                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10419
10420         return 0;
10421 }
10422
10423 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10424 {
10425         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10426         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10427         unsigned int req_cdclk = intel_state->dev_cdclk;
10428         unsigned int req_vco = intel_state->cdclk_pll_vco;
10429
10430         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10431 }
10432
10433 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10434                                       struct intel_crtc_state *crtc_state)
10435 {
10436         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10437                 if (!intel_ddi_pll_select(crtc, crtc_state))
10438                         return -EINVAL;
10439         }
10440
10441         crtc->lowfreq_avail = false;
10442
10443         return 0;
10444 }
10445
10446 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10447                                 enum port port,
10448                                 struct intel_crtc_state *pipe_config)
10449 {
10450         enum intel_dpll_id id;
10451
10452         switch (port) {
10453         case PORT_A:
10454                 id = DPLL_ID_SKL_DPLL0;
10455                 break;
10456         case PORT_B:
10457                 id = DPLL_ID_SKL_DPLL1;
10458                 break;
10459         case PORT_C:
10460                 id = DPLL_ID_SKL_DPLL2;
10461                 break;
10462         default:
10463                 DRM_ERROR("Incorrect port type\n");
10464                 return;
10465         }
10466
10467         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10468 }
10469
10470 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10471                                 enum port port,
10472                                 struct intel_crtc_state *pipe_config)
10473 {
10474         enum intel_dpll_id id;
10475         u32 temp;
10476
10477         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10478         id = temp >> (port * 3 + 1);
10479
10480         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10481                 return;
10482
10483         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10484 }
10485
10486 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10487                                 enum port port,
10488                                 struct intel_crtc_state *pipe_config)
10489 {
10490         enum intel_dpll_id id;
10491         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10492
10493         switch (ddi_pll_sel) {
10494         case PORT_CLK_SEL_WRPLL1:
10495                 id = DPLL_ID_WRPLL1;
10496                 break;
10497         case PORT_CLK_SEL_WRPLL2:
10498                 id = DPLL_ID_WRPLL2;
10499                 break;
10500         case PORT_CLK_SEL_SPLL:
10501                 id = DPLL_ID_SPLL;
10502                 break;
10503         case PORT_CLK_SEL_LCPLL_810:
10504                 id = DPLL_ID_LCPLL_810;
10505                 break;
10506         case PORT_CLK_SEL_LCPLL_1350:
10507                 id = DPLL_ID_LCPLL_1350;
10508                 break;
10509         case PORT_CLK_SEL_LCPLL_2700:
10510                 id = DPLL_ID_LCPLL_2700;
10511                 break;
10512         default:
10513                 MISSING_CASE(ddi_pll_sel);
10514                 /* fall through */
10515         case PORT_CLK_SEL_NONE:
10516                 return;
10517         }
10518
10519         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10520 }
10521
10522 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10523                                      struct intel_crtc_state *pipe_config,
10524                                      unsigned long *power_domain_mask)
10525 {
10526         struct drm_device *dev = crtc->base.dev;
10527         struct drm_i915_private *dev_priv = to_i915(dev);
10528         enum intel_display_power_domain power_domain;
10529         u32 tmp;
10530
10531         /*
10532          * The pipe->transcoder mapping is fixed with the exception of the eDP
10533          * transcoder handled below.
10534          */
10535         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10536
10537         /*
10538          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10539          * consistency and less surprising code; it's in always on power).
10540          */
10541         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10542         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10543                 enum pipe trans_edp_pipe;
10544                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10545                 default:
10546                         WARN(1, "unknown pipe linked to edp transcoder\n");
10547                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10548                 case TRANS_DDI_EDP_INPUT_A_ON:
10549                         trans_edp_pipe = PIPE_A;
10550                         break;
10551                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10552                         trans_edp_pipe = PIPE_B;
10553                         break;
10554                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10555                         trans_edp_pipe = PIPE_C;
10556                         break;
10557                 }
10558
10559                 if (trans_edp_pipe == crtc->pipe)
10560                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10561         }
10562
10563         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10564         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10565                 return false;
10566         *power_domain_mask |= BIT(power_domain);
10567
10568         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10569
10570         return tmp & PIPECONF_ENABLE;
10571 }
10572
10573 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10574                                          struct intel_crtc_state *pipe_config,
10575                                          unsigned long *power_domain_mask)
10576 {
10577         struct drm_device *dev = crtc->base.dev;
10578         struct drm_i915_private *dev_priv = to_i915(dev);
10579         enum intel_display_power_domain power_domain;
10580         enum port port;
10581         enum transcoder cpu_transcoder;
10582         u32 tmp;
10583
10584         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10585                 if (port == PORT_A)
10586                         cpu_transcoder = TRANSCODER_DSI_A;
10587                 else
10588                         cpu_transcoder = TRANSCODER_DSI_C;
10589
10590                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10591                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10592                         continue;
10593                 *power_domain_mask |= BIT(power_domain);
10594
10595                 /*
10596                  * The PLL needs to be enabled with a valid divider
10597                  * configuration, otherwise accessing DSI registers will hang
10598                  * the machine. See BSpec North Display Engine
10599                  * registers/MIPI[BXT]. We can break out here early, since we
10600                  * need the same DSI PLL to be enabled for both DSI ports.
10601                  */
10602                 if (!intel_dsi_pll_is_enabled(dev_priv))
10603                         break;
10604
10605                 /* XXX: this works for video mode only */
10606                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10607                 if (!(tmp & DPI_ENABLE))
10608                         continue;
10609
10610                 tmp = I915_READ(MIPI_CTRL(port));
10611                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10612                         continue;
10613
10614                 pipe_config->cpu_transcoder = cpu_transcoder;
10615                 break;
10616         }
10617
10618         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10619 }
10620
10621 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10622                                        struct intel_crtc_state *pipe_config)
10623 {
10624         struct drm_device *dev = crtc->base.dev;
10625         struct drm_i915_private *dev_priv = to_i915(dev);
10626         struct intel_shared_dpll *pll;
10627         enum port port;
10628         uint32_t tmp;
10629
10630         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10631
10632         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10633
10634         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10635                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10636         else if (IS_BROXTON(dev))
10637                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10638         else
10639                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10640
10641         pll = pipe_config->shared_dpll;
10642         if (pll) {
10643                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10644                                                  &pipe_config->dpll_hw_state));
10645         }
10646
10647         /*
10648          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10649          * DDI E. So just check whether this pipe is wired to DDI E and whether
10650          * the PCH transcoder is on.
10651          */
10652         if (INTEL_INFO(dev)->gen < 9 &&
10653             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10654                 pipe_config->has_pch_encoder = true;
10655
10656                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10657                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10658                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10659
10660                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10661         }
10662 }
10663
10664 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10665                                     struct intel_crtc_state *pipe_config)
10666 {
10667         struct drm_device *dev = crtc->base.dev;
10668         struct drm_i915_private *dev_priv = to_i915(dev);
10669         enum intel_display_power_domain power_domain;
10670         unsigned long power_domain_mask;
10671         bool active;
10672
10673         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10674         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10675                 return false;
10676         power_domain_mask = BIT(power_domain);
10677
10678         pipe_config->shared_dpll = NULL;
10679
10680         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10681
10682         if (IS_BROXTON(dev_priv) &&
10683             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10684                 WARN_ON(active);
10685                 active = true;
10686         }
10687
10688         if (!active)
10689                 goto out;
10690
10691         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10692                 haswell_get_ddi_port_state(crtc, pipe_config);
10693                 intel_get_pipe_timings(crtc, pipe_config);
10694         }
10695
10696         intel_get_pipe_src_size(crtc, pipe_config);
10697
10698         pipe_config->gamma_mode =
10699                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10700
10701         if (INTEL_INFO(dev)->gen >= 9) {
10702                 skl_init_scalers(dev, crtc, pipe_config);
10703         }
10704
10705         if (INTEL_INFO(dev)->gen >= 9) {
10706                 pipe_config->scaler_state.scaler_id = -1;
10707                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10708         }
10709
10710         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10711         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10712                 power_domain_mask |= BIT(power_domain);
10713                 if (INTEL_INFO(dev)->gen >= 9)
10714                         skylake_get_pfit_config(crtc, pipe_config);
10715                 else
10716                         ironlake_get_pfit_config(crtc, pipe_config);
10717         }
10718
10719         if (IS_HASWELL(dev))
10720                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10721                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10722
10723         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10724             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10725                 pipe_config->pixel_multiplier =
10726                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10727         } else {
10728                 pipe_config->pixel_multiplier = 1;
10729         }
10730
10731 out:
10732         for_each_power_domain(power_domain, power_domain_mask)
10733                 intel_display_power_put(dev_priv, power_domain);
10734
10735         return active;
10736 }
10737
10738 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10739                                const struct intel_plane_state *plane_state)
10740 {
10741         struct drm_device *dev = crtc->dev;
10742         struct drm_i915_private *dev_priv = to_i915(dev);
10743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10744         uint32_t cntl = 0, size = 0;
10745
10746         if (plane_state && plane_state->base.visible) {
10747                 unsigned int width = plane_state->base.crtc_w;
10748                 unsigned int height = plane_state->base.crtc_h;
10749                 unsigned int stride = roundup_pow_of_two(width) * 4;
10750
10751                 switch (stride) {
10752                 default:
10753                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10754                                   width, stride);
10755                         stride = 256;
10756                         /* fallthrough */
10757                 case 256:
10758                 case 512:
10759                 case 1024:
10760                 case 2048:
10761                         break;
10762                 }
10763
10764                 cntl |= CURSOR_ENABLE |
10765                         CURSOR_GAMMA_ENABLE |
10766                         CURSOR_FORMAT_ARGB |
10767                         CURSOR_STRIDE(stride);
10768
10769                 size = (height << 12) | width;
10770         }
10771
10772         if (intel_crtc->cursor_cntl != 0 &&
10773             (intel_crtc->cursor_base != base ||
10774              intel_crtc->cursor_size != size ||
10775              intel_crtc->cursor_cntl != cntl)) {
10776                 /* On these chipsets we can only modify the base/size/stride
10777                  * whilst the cursor is disabled.
10778                  */
10779                 I915_WRITE(CURCNTR(PIPE_A), 0);
10780                 POSTING_READ(CURCNTR(PIPE_A));
10781                 intel_crtc->cursor_cntl = 0;
10782         }
10783
10784         if (intel_crtc->cursor_base != base) {
10785                 I915_WRITE(CURBASE(PIPE_A), base);
10786                 intel_crtc->cursor_base = base;
10787         }
10788
10789         if (intel_crtc->cursor_size != size) {
10790                 I915_WRITE(CURSIZE, size);
10791                 intel_crtc->cursor_size = size;
10792         }
10793
10794         if (intel_crtc->cursor_cntl != cntl) {
10795                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10796                 POSTING_READ(CURCNTR(PIPE_A));
10797                 intel_crtc->cursor_cntl = cntl;
10798         }
10799 }
10800
10801 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10802                                const struct intel_plane_state *plane_state)
10803 {
10804         struct drm_device *dev = crtc->dev;
10805         struct drm_i915_private *dev_priv = to_i915(dev);
10806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10807         const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
10808         int pipe = intel_crtc->pipe;
10809         uint32_t cntl = 0;
10810
10811         if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
10812                 skl_write_cursor_wm(intel_crtc, wm);
10813
10814         if (plane_state && plane_state->base.visible) {
10815                 cntl = MCURSOR_GAMMA_ENABLE;
10816                 switch (plane_state->base.crtc_w) {
10817                         case 64:
10818                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10819                                 break;
10820                         case 128:
10821                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10822                                 break;
10823                         case 256:
10824                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10825                                 break;
10826                         default:
10827                                 MISSING_CASE(plane_state->base.crtc_w);
10828                                 return;
10829                 }
10830                 cntl |= pipe << 28; /* Connect to correct pipe */
10831
10832                 if (HAS_DDI(dev))
10833                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10834
10835                 if (plane_state->base.rotation == DRM_ROTATE_180)
10836                         cntl |= CURSOR_ROTATE_180;
10837         }
10838
10839         if (intel_crtc->cursor_cntl != cntl) {
10840                 I915_WRITE(CURCNTR(pipe), cntl);
10841                 POSTING_READ(CURCNTR(pipe));
10842                 intel_crtc->cursor_cntl = cntl;
10843         }
10844
10845         /* and commit changes on next vblank */
10846         I915_WRITE(CURBASE(pipe), base);
10847         POSTING_READ(CURBASE(pipe));
10848
10849         intel_crtc->cursor_base = base;
10850 }
10851
10852 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10853 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10854                                      const struct intel_plane_state *plane_state)
10855 {
10856         struct drm_device *dev = crtc->dev;
10857         struct drm_i915_private *dev_priv = to_i915(dev);
10858         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10859         int pipe = intel_crtc->pipe;
10860         u32 base = intel_crtc->cursor_addr;
10861         u32 pos = 0;
10862
10863         if (plane_state) {
10864                 int x = plane_state->base.crtc_x;
10865                 int y = plane_state->base.crtc_y;
10866
10867                 if (x < 0) {
10868                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10869                         x = -x;
10870                 }
10871                 pos |= x << CURSOR_X_SHIFT;
10872
10873                 if (y < 0) {
10874                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10875                         y = -y;
10876                 }
10877                 pos |= y << CURSOR_Y_SHIFT;
10878
10879                 /* ILK+ do this automagically */
10880                 if (HAS_GMCH_DISPLAY(dev) &&
10881                     plane_state->base.rotation == DRM_ROTATE_180) {
10882                         base += (plane_state->base.crtc_h *
10883                                  plane_state->base.crtc_w - 1) * 4;
10884                 }
10885         }
10886
10887         I915_WRITE(CURPOS(pipe), pos);
10888
10889         if (IS_845G(dev) || IS_I865G(dev))
10890                 i845_update_cursor(crtc, base, plane_state);
10891         else
10892                 i9xx_update_cursor(crtc, base, plane_state);
10893 }
10894
10895 static bool cursor_size_ok(struct drm_device *dev,
10896                            uint32_t width, uint32_t height)
10897 {
10898         if (width == 0 || height == 0)
10899                 return false;
10900
10901         /*
10902          * 845g/865g are special in that they are only limited by
10903          * the width of their cursors, the height is arbitrary up to
10904          * the precision of the register. Everything else requires
10905          * square cursors, limited to a few power-of-two sizes.
10906          */
10907         if (IS_845G(dev) || IS_I865G(dev)) {
10908                 if ((width & 63) != 0)
10909                         return false;
10910
10911                 if (width > (IS_845G(dev) ? 64 : 512))
10912                         return false;
10913
10914                 if (height > 1023)
10915                         return false;
10916         } else {
10917                 switch (width | height) {
10918                 case 256:
10919                 case 128:
10920                         if (IS_GEN2(dev))
10921                                 return false;
10922                 case 64:
10923                         break;
10924                 default:
10925                         return false;
10926                 }
10927         }
10928
10929         return true;
10930 }
10931
10932 /* VESA 640x480x72Hz mode to set on the pipe */
10933 static struct drm_display_mode load_detect_mode = {
10934         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10935                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10936 };
10937
10938 struct drm_framebuffer *
10939 __intel_framebuffer_create(struct drm_device *dev,
10940                            struct drm_mode_fb_cmd2 *mode_cmd,
10941                            struct drm_i915_gem_object *obj)
10942 {
10943         struct intel_framebuffer *intel_fb;
10944         int ret;
10945
10946         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10947         if (!intel_fb)
10948                 return ERR_PTR(-ENOMEM);
10949
10950         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10951         if (ret)
10952                 goto err;
10953
10954         return &intel_fb->base;
10955
10956 err:
10957         kfree(intel_fb);
10958         return ERR_PTR(ret);
10959 }
10960
10961 static struct drm_framebuffer *
10962 intel_framebuffer_create(struct drm_device *dev,
10963                          struct drm_mode_fb_cmd2 *mode_cmd,
10964                          struct drm_i915_gem_object *obj)
10965 {
10966         struct drm_framebuffer *fb;
10967         int ret;
10968
10969         ret = i915_mutex_lock_interruptible(dev);
10970         if (ret)
10971                 return ERR_PTR(ret);
10972         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10973         mutex_unlock(&dev->struct_mutex);
10974
10975         return fb;
10976 }
10977
10978 static u32
10979 intel_framebuffer_pitch_for_width(int width, int bpp)
10980 {
10981         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10982         return ALIGN(pitch, 64);
10983 }
10984
10985 static u32
10986 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10987 {
10988         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10989         return PAGE_ALIGN(pitch * mode->vdisplay);
10990 }
10991
10992 static struct drm_framebuffer *
10993 intel_framebuffer_create_for_mode(struct drm_device *dev,
10994                                   struct drm_display_mode *mode,
10995                                   int depth, int bpp)
10996 {
10997         struct drm_framebuffer *fb;
10998         struct drm_i915_gem_object *obj;
10999         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11000
11001         obj = i915_gem_object_create(dev,
11002                                     intel_framebuffer_size_for_mode(mode, bpp));
11003         if (IS_ERR(obj))
11004                 return ERR_CAST(obj);
11005
11006         mode_cmd.width = mode->hdisplay;
11007         mode_cmd.height = mode->vdisplay;
11008         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11009                                                                 bpp);
11010         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11011
11012         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11013         if (IS_ERR(fb))
11014                 i915_gem_object_put_unlocked(obj);
11015
11016         return fb;
11017 }
11018
11019 static struct drm_framebuffer *
11020 mode_fits_in_fbdev(struct drm_device *dev,
11021                    struct drm_display_mode *mode)
11022 {
11023 #ifdef CONFIG_DRM_FBDEV_EMULATION
11024         struct drm_i915_private *dev_priv = to_i915(dev);
11025         struct drm_i915_gem_object *obj;
11026         struct drm_framebuffer *fb;
11027
11028         if (!dev_priv->fbdev)
11029                 return NULL;
11030
11031         if (!dev_priv->fbdev->fb)
11032                 return NULL;
11033
11034         obj = dev_priv->fbdev->fb->obj;
11035         BUG_ON(!obj);
11036
11037         fb = &dev_priv->fbdev->fb->base;
11038         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11039                                                                fb->bits_per_pixel))
11040                 return NULL;
11041
11042         if (obj->base.size < mode->vdisplay * fb->pitches[0])
11043                 return NULL;
11044
11045         drm_framebuffer_reference(fb);
11046         return fb;
11047 #else
11048         return NULL;
11049 #endif
11050 }
11051
11052 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11053                                            struct drm_crtc *crtc,
11054                                            struct drm_display_mode *mode,
11055                                            struct drm_framebuffer *fb,
11056                                            int x, int y)
11057 {
11058         struct drm_plane_state *plane_state;
11059         int hdisplay, vdisplay;
11060         int ret;
11061
11062         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11063         if (IS_ERR(plane_state))
11064                 return PTR_ERR(plane_state);
11065
11066         if (mode)
11067                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11068         else
11069                 hdisplay = vdisplay = 0;
11070
11071         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11072         if (ret)
11073                 return ret;
11074         drm_atomic_set_fb_for_plane(plane_state, fb);
11075         plane_state->crtc_x = 0;
11076         plane_state->crtc_y = 0;
11077         plane_state->crtc_w = hdisplay;
11078         plane_state->crtc_h = vdisplay;
11079         plane_state->src_x = x << 16;
11080         plane_state->src_y = y << 16;
11081         plane_state->src_w = hdisplay << 16;
11082         plane_state->src_h = vdisplay << 16;
11083
11084         return 0;
11085 }
11086
11087 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11088                                 struct drm_display_mode *mode,
11089                                 struct intel_load_detect_pipe *old,
11090                                 struct drm_modeset_acquire_ctx *ctx)
11091 {
11092         struct intel_crtc *intel_crtc;
11093         struct intel_encoder *intel_encoder =
11094                 intel_attached_encoder(connector);
11095         struct drm_crtc *possible_crtc;
11096         struct drm_encoder *encoder = &intel_encoder->base;
11097         struct drm_crtc *crtc = NULL;
11098         struct drm_device *dev = encoder->dev;
11099         struct drm_framebuffer *fb;
11100         struct drm_mode_config *config = &dev->mode_config;
11101         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11102         struct drm_connector_state *connector_state;
11103         struct intel_crtc_state *crtc_state;
11104         int ret, i = -1;
11105
11106         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11107                       connector->base.id, connector->name,
11108                       encoder->base.id, encoder->name);
11109
11110         old->restore_state = NULL;
11111
11112 retry:
11113         ret = drm_modeset_lock(&config->connection_mutex, ctx);
11114         if (ret)
11115                 goto fail;
11116
11117         /*
11118          * Algorithm gets a little messy:
11119          *
11120          *   - if the connector already has an assigned crtc, use it (but make
11121          *     sure it's on first)
11122          *
11123          *   - try to find the first unused crtc that can drive this connector,
11124          *     and use that if we find one
11125          */
11126
11127         /* See if we already have a CRTC for this connector */
11128         if (connector->state->crtc) {
11129                 crtc = connector->state->crtc;
11130
11131                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11132                 if (ret)
11133                         goto fail;
11134
11135                 /* Make sure the crtc and connector are running */
11136                 goto found;
11137         }
11138
11139         /* Find an unused one (if possible) */
11140         for_each_crtc(dev, possible_crtc) {
11141                 i++;
11142                 if (!(encoder->possible_crtcs & (1 << i)))
11143                         continue;
11144
11145                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11146                 if (ret)
11147                         goto fail;
11148
11149                 if (possible_crtc->state->enable) {
11150                         drm_modeset_unlock(&possible_crtc->mutex);
11151                         continue;
11152                 }
11153
11154                 crtc = possible_crtc;
11155                 break;
11156         }
11157
11158         /*
11159          * If we didn't find an unused CRTC, don't use any.
11160          */
11161         if (!crtc) {
11162                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11163                 goto fail;
11164         }
11165
11166 found:
11167         intel_crtc = to_intel_crtc(crtc);
11168
11169         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11170         if (ret)
11171                 goto fail;
11172
11173         state = drm_atomic_state_alloc(dev);
11174         restore_state = drm_atomic_state_alloc(dev);
11175         if (!state || !restore_state) {
11176                 ret = -ENOMEM;
11177                 goto fail;
11178         }
11179
11180         state->acquire_ctx = ctx;
11181         restore_state->acquire_ctx = ctx;
11182
11183         connector_state = drm_atomic_get_connector_state(state, connector);
11184         if (IS_ERR(connector_state)) {
11185                 ret = PTR_ERR(connector_state);
11186                 goto fail;
11187         }
11188
11189         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11190         if (ret)
11191                 goto fail;
11192
11193         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11194         if (IS_ERR(crtc_state)) {
11195                 ret = PTR_ERR(crtc_state);
11196                 goto fail;
11197         }
11198
11199         crtc_state->base.active = crtc_state->base.enable = true;
11200
11201         if (!mode)
11202                 mode = &load_detect_mode;
11203
11204         /* We need a framebuffer large enough to accommodate all accesses
11205          * that the plane may generate whilst we perform load detection.
11206          * We can not rely on the fbcon either being present (we get called
11207          * during its initialisation to detect all boot displays, or it may
11208          * not even exist) or that it is large enough to satisfy the
11209          * requested mode.
11210          */
11211         fb = mode_fits_in_fbdev(dev, mode);
11212         if (fb == NULL) {
11213                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11214                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11215         } else
11216                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11217         if (IS_ERR(fb)) {
11218                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11219                 goto fail;
11220         }
11221
11222         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11223         if (ret)
11224                 goto fail;
11225
11226         drm_framebuffer_unreference(fb);
11227
11228         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11229         if (ret)
11230                 goto fail;
11231
11232         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11233         if (!ret)
11234                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11235         if (!ret)
11236                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11237         if (ret) {
11238                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11239                 goto fail;
11240         }
11241
11242         ret = drm_atomic_commit(state);
11243         if (ret) {
11244                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11245                 goto fail;
11246         }
11247
11248         old->restore_state = restore_state;
11249
11250         /* let the connector get through one full cycle before testing */
11251         intel_wait_for_vblank(dev, intel_crtc->pipe);
11252         return true;
11253
11254 fail:
11255         drm_atomic_state_free(state);
11256         drm_atomic_state_free(restore_state);
11257         restore_state = state = NULL;
11258
11259         if (ret == -EDEADLK) {
11260                 drm_modeset_backoff(ctx);
11261                 goto retry;
11262         }
11263
11264         return false;
11265 }
11266
11267 void intel_release_load_detect_pipe(struct drm_connector *connector,
11268                                     struct intel_load_detect_pipe *old,
11269                                     struct drm_modeset_acquire_ctx *ctx)
11270 {
11271         struct intel_encoder *intel_encoder =
11272                 intel_attached_encoder(connector);
11273         struct drm_encoder *encoder = &intel_encoder->base;
11274         struct drm_atomic_state *state = old->restore_state;
11275         int ret;
11276
11277         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11278                       connector->base.id, connector->name,
11279                       encoder->base.id, encoder->name);
11280
11281         if (!state)
11282                 return;
11283
11284         ret = drm_atomic_commit(state);
11285         if (ret) {
11286                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11287                 drm_atomic_state_free(state);
11288         }
11289 }
11290
11291 static int i9xx_pll_refclk(struct drm_device *dev,
11292                            const struct intel_crtc_state *pipe_config)
11293 {
11294         struct drm_i915_private *dev_priv = to_i915(dev);
11295         u32 dpll = pipe_config->dpll_hw_state.dpll;
11296
11297         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11298                 return dev_priv->vbt.lvds_ssc_freq;
11299         else if (HAS_PCH_SPLIT(dev))
11300                 return 120000;
11301         else if (!IS_GEN2(dev))
11302                 return 96000;
11303         else
11304                 return 48000;
11305 }
11306
11307 /* Returns the clock of the currently programmed mode of the given pipe. */
11308 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11309                                 struct intel_crtc_state *pipe_config)
11310 {
11311         struct drm_device *dev = crtc->base.dev;
11312         struct drm_i915_private *dev_priv = to_i915(dev);
11313         int pipe = pipe_config->cpu_transcoder;
11314         u32 dpll = pipe_config->dpll_hw_state.dpll;
11315         u32 fp;
11316         struct dpll clock;
11317         int port_clock;
11318         int refclk = i9xx_pll_refclk(dev, pipe_config);
11319
11320         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11321                 fp = pipe_config->dpll_hw_state.fp0;
11322         else
11323                 fp = pipe_config->dpll_hw_state.fp1;
11324
11325         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11326         if (IS_PINEVIEW(dev)) {
11327                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11328                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11329         } else {
11330                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11331                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11332         }
11333
11334         if (!IS_GEN2(dev)) {
11335                 if (IS_PINEVIEW(dev))
11336                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11337                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11338                 else
11339                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11340                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11341
11342                 switch (dpll & DPLL_MODE_MASK) {
11343                 case DPLLB_MODE_DAC_SERIAL:
11344                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11345                                 5 : 10;
11346                         break;
11347                 case DPLLB_MODE_LVDS:
11348                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11349                                 7 : 14;
11350                         break;
11351                 default:
11352                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11353                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11354                         return;
11355                 }
11356
11357                 if (IS_PINEVIEW(dev))
11358                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11359                 else
11360                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11361         } else {
11362                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
11363                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11364
11365                 if (is_lvds) {
11366                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11367                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11368
11369                         if (lvds & LVDS_CLKB_POWER_UP)
11370                                 clock.p2 = 7;
11371                         else
11372                                 clock.p2 = 14;
11373                 } else {
11374                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11375                                 clock.p1 = 2;
11376                         else {
11377                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11378                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11379                         }
11380                         if (dpll & PLL_P2_DIVIDE_BY_4)
11381                                 clock.p2 = 4;
11382                         else
11383                                 clock.p2 = 2;
11384                 }
11385
11386                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11387         }
11388
11389         /*
11390          * This value includes pixel_multiplier. We will use
11391          * port_clock to compute adjusted_mode.crtc_clock in the
11392          * encoder's get_config() function.
11393          */
11394         pipe_config->port_clock = port_clock;
11395 }
11396
11397 int intel_dotclock_calculate(int link_freq,
11398                              const struct intel_link_m_n *m_n)
11399 {
11400         /*
11401          * The calculation for the data clock is:
11402          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11403          * But we want to avoid losing precison if possible, so:
11404          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11405          *
11406          * and the link clock is simpler:
11407          * link_clock = (m * link_clock) / n
11408          */
11409
11410         if (!m_n->link_n)
11411                 return 0;
11412
11413         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11414 }
11415
11416 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11417                                    struct intel_crtc_state *pipe_config)
11418 {
11419         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11420
11421         /* read out port_clock from the DPLL */
11422         i9xx_crtc_clock_get(crtc, pipe_config);
11423
11424         /*
11425          * In case there is an active pipe without active ports,
11426          * we may need some idea for the dotclock anyway.
11427          * Calculate one based on the FDI configuration.
11428          */
11429         pipe_config->base.adjusted_mode.crtc_clock =
11430                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11431                                          &pipe_config->fdi_m_n);
11432 }
11433
11434 /** Returns the currently programmed mode of the given pipe. */
11435 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11436                                              struct drm_crtc *crtc)
11437 {
11438         struct drm_i915_private *dev_priv = to_i915(dev);
11439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11440         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11441         struct drm_display_mode *mode;
11442         struct intel_crtc_state *pipe_config;
11443         int htot = I915_READ(HTOTAL(cpu_transcoder));
11444         int hsync = I915_READ(HSYNC(cpu_transcoder));
11445         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11446         int vsync = I915_READ(VSYNC(cpu_transcoder));
11447         enum pipe pipe = intel_crtc->pipe;
11448
11449         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11450         if (!mode)
11451                 return NULL;
11452
11453         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11454         if (!pipe_config) {
11455                 kfree(mode);
11456                 return NULL;
11457         }
11458
11459         /*
11460          * Construct a pipe_config sufficient for getting the clock info
11461          * back out of crtc_clock_get.
11462          *
11463          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11464          * to use a real value here instead.
11465          */
11466         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11467         pipe_config->pixel_multiplier = 1;
11468         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11469         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11470         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11471         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11472
11473         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11474         mode->hdisplay = (htot & 0xffff) + 1;
11475         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11476         mode->hsync_start = (hsync & 0xffff) + 1;
11477         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11478         mode->vdisplay = (vtot & 0xffff) + 1;
11479         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11480         mode->vsync_start = (vsync & 0xffff) + 1;
11481         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11482
11483         drm_mode_set_name(mode);
11484
11485         kfree(pipe_config);
11486
11487         return mode;
11488 }
11489
11490 static void intel_crtc_destroy(struct drm_crtc *crtc)
11491 {
11492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11493         struct drm_device *dev = crtc->dev;
11494         struct intel_flip_work *work;
11495
11496         spin_lock_irq(&dev->event_lock);
11497         work = intel_crtc->flip_work;
11498         intel_crtc->flip_work = NULL;
11499         spin_unlock_irq(&dev->event_lock);
11500
11501         if (work) {
11502                 cancel_work_sync(&work->mmio_work);
11503                 cancel_work_sync(&work->unpin_work);
11504                 kfree(work);
11505         }
11506
11507         drm_crtc_cleanup(crtc);
11508
11509         kfree(intel_crtc);
11510 }
11511
11512 static void intel_unpin_work_fn(struct work_struct *__work)
11513 {
11514         struct intel_flip_work *work =
11515                 container_of(__work, struct intel_flip_work, unpin_work);
11516         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11517         struct drm_device *dev = crtc->base.dev;
11518         struct drm_plane *primary = crtc->base.primary;
11519
11520         if (is_mmio_work(work))
11521                 flush_work(&work->mmio_work);
11522
11523         mutex_lock(&dev->struct_mutex);
11524         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11525         i915_gem_object_put(work->pending_flip_obj);
11526         mutex_unlock(&dev->struct_mutex);
11527
11528         i915_gem_request_put(work->flip_queued_req);
11529
11530         intel_frontbuffer_flip_complete(to_i915(dev),
11531                                         to_intel_plane(primary)->frontbuffer_bit);
11532         intel_fbc_post_update(crtc);
11533         drm_framebuffer_unreference(work->old_fb);
11534
11535         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11536         atomic_dec(&crtc->unpin_work_count);
11537
11538         kfree(work);
11539 }
11540
11541 /* Is 'a' after or equal to 'b'? */
11542 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11543 {
11544         return !((a - b) & 0x80000000);
11545 }
11546
11547 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11548                                    struct intel_flip_work *work)
11549 {
11550         struct drm_device *dev = crtc->base.dev;
11551         struct drm_i915_private *dev_priv = to_i915(dev);
11552
11553         if (abort_flip_on_reset(crtc))
11554                 return true;
11555
11556         /*
11557          * The relevant registers doen't exist on pre-ctg.
11558          * As the flip done interrupt doesn't trigger for mmio
11559          * flips on gmch platforms, a flip count check isn't
11560          * really needed there. But since ctg has the registers,
11561          * include it in the check anyway.
11562          */
11563         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11564                 return true;
11565
11566         /*
11567          * BDW signals flip done immediately if the plane
11568          * is disabled, even if the plane enable is already
11569          * armed to occur at the next vblank :(
11570          */
11571
11572         /*
11573          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11574          * used the same base address. In that case the mmio flip might
11575          * have completed, but the CS hasn't even executed the flip yet.
11576          *
11577          * A flip count check isn't enough as the CS might have updated
11578          * the base address just after start of vblank, but before we
11579          * managed to process the interrupt. This means we'd complete the
11580          * CS flip too soon.
11581          *
11582          * Combining both checks should get us a good enough result. It may
11583          * still happen that the CS flip has been executed, but has not
11584          * yet actually completed. But in case the base address is the same
11585          * anyway, we don't really care.
11586          */
11587         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11588                 crtc->flip_work->gtt_offset &&
11589                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11590                                     crtc->flip_work->flip_count);
11591 }
11592
11593 static bool
11594 __pageflip_finished_mmio(struct intel_crtc *crtc,
11595                                struct intel_flip_work *work)
11596 {
11597         /*
11598          * MMIO work completes when vblank is different from
11599          * flip_queued_vblank.
11600          *
11601          * Reset counter value doesn't matter, this is handled by
11602          * i915_wait_request finishing early, so no need to handle
11603          * reset here.
11604          */
11605         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11606 }
11607
11608
11609 static bool pageflip_finished(struct intel_crtc *crtc,
11610                               struct intel_flip_work *work)
11611 {
11612         if (!atomic_read(&work->pending))
11613                 return false;
11614
11615         smp_rmb();
11616
11617         if (is_mmio_work(work))
11618                 return __pageflip_finished_mmio(crtc, work);
11619         else
11620                 return __pageflip_finished_cs(crtc, work);
11621 }
11622
11623 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11624 {
11625         struct drm_device *dev = &dev_priv->drm;
11626         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11628         struct intel_flip_work *work;
11629         unsigned long flags;
11630
11631         /* Ignore early vblank irqs */
11632         if (!crtc)
11633                 return;
11634
11635         /*
11636          * This is called both by irq handlers and the reset code (to complete
11637          * lost pageflips) so needs the full irqsave spinlocks.
11638          */
11639         spin_lock_irqsave(&dev->event_lock, flags);
11640         work = intel_crtc->flip_work;
11641
11642         if (work != NULL &&
11643             !is_mmio_work(work) &&
11644             pageflip_finished(intel_crtc, work))
11645                 page_flip_completed(intel_crtc);
11646
11647         spin_unlock_irqrestore(&dev->event_lock, flags);
11648 }
11649
11650 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11651 {
11652         struct drm_device *dev = &dev_priv->drm;
11653         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11655         struct intel_flip_work *work;
11656         unsigned long flags;
11657
11658         /* Ignore early vblank irqs */
11659         if (!crtc)
11660                 return;
11661
11662         /*
11663          * This is called both by irq handlers and the reset code (to complete
11664          * lost pageflips) so needs the full irqsave spinlocks.
11665          */
11666         spin_lock_irqsave(&dev->event_lock, flags);
11667         work = intel_crtc->flip_work;
11668
11669         if (work != NULL &&
11670             is_mmio_work(work) &&
11671             pageflip_finished(intel_crtc, work))
11672                 page_flip_completed(intel_crtc);
11673
11674         spin_unlock_irqrestore(&dev->event_lock, flags);
11675 }
11676
11677 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11678                                                struct intel_flip_work *work)
11679 {
11680         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11681
11682         /* Ensure that the work item is consistent when activating it ... */
11683         smp_mb__before_atomic();
11684         atomic_set(&work->pending, 1);
11685 }
11686
11687 static int intel_gen2_queue_flip(struct drm_device *dev,
11688                                  struct drm_crtc *crtc,
11689                                  struct drm_framebuffer *fb,
11690                                  struct drm_i915_gem_object *obj,
11691                                  struct drm_i915_gem_request *req,
11692                                  uint32_t flags)
11693 {
11694         struct intel_ring *ring = req->ring;
11695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11696         u32 flip_mask;
11697         int ret;
11698
11699         ret = intel_ring_begin(req, 6);
11700         if (ret)
11701                 return ret;
11702
11703         /* Can't queue multiple flips, so wait for the previous
11704          * one to finish before executing the next.
11705          */
11706         if (intel_crtc->plane)
11707                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11708         else
11709                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11710         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11711         intel_ring_emit(ring, MI_NOOP);
11712         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11713                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11714         intel_ring_emit(ring, fb->pitches[0]);
11715         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11716         intel_ring_emit(ring, 0); /* aux display base address, unused */
11717
11718         return 0;
11719 }
11720
11721 static int intel_gen3_queue_flip(struct drm_device *dev,
11722                                  struct drm_crtc *crtc,
11723                                  struct drm_framebuffer *fb,
11724                                  struct drm_i915_gem_object *obj,
11725                                  struct drm_i915_gem_request *req,
11726                                  uint32_t flags)
11727 {
11728         struct intel_ring *ring = req->ring;
11729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11730         u32 flip_mask;
11731         int ret;
11732
11733         ret = intel_ring_begin(req, 6);
11734         if (ret)
11735                 return ret;
11736
11737         if (intel_crtc->plane)
11738                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11739         else
11740                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11741         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11742         intel_ring_emit(ring, MI_NOOP);
11743         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11744                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11745         intel_ring_emit(ring, fb->pitches[0]);
11746         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11747         intel_ring_emit(ring, MI_NOOP);
11748
11749         return 0;
11750 }
11751
11752 static int intel_gen4_queue_flip(struct drm_device *dev,
11753                                  struct drm_crtc *crtc,
11754                                  struct drm_framebuffer *fb,
11755                                  struct drm_i915_gem_object *obj,
11756                                  struct drm_i915_gem_request *req,
11757                                  uint32_t flags)
11758 {
11759         struct intel_ring *ring = req->ring;
11760         struct drm_i915_private *dev_priv = to_i915(dev);
11761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11762         uint32_t pf, pipesrc;
11763         int ret;
11764
11765         ret = intel_ring_begin(req, 4);
11766         if (ret)
11767                 return ret;
11768
11769         /* i965+ uses the linear or tiled offsets from the
11770          * Display Registers (which do not change across a page-flip)
11771          * so we need only reprogram the base address.
11772          */
11773         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11774                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11775         intel_ring_emit(ring, fb->pitches[0]);
11776         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11777                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11778
11779         /* XXX Enabling the panel-fitter across page-flip is so far
11780          * untested on non-native modes, so ignore it for now.
11781          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11782          */
11783         pf = 0;
11784         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11785         intel_ring_emit(ring, pf | pipesrc);
11786
11787         return 0;
11788 }
11789
11790 static int intel_gen6_queue_flip(struct drm_device *dev,
11791                                  struct drm_crtc *crtc,
11792                                  struct drm_framebuffer *fb,
11793                                  struct drm_i915_gem_object *obj,
11794                                  struct drm_i915_gem_request *req,
11795                                  uint32_t flags)
11796 {
11797         struct intel_ring *ring = req->ring;
11798         struct drm_i915_private *dev_priv = to_i915(dev);
11799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11800         uint32_t pf, pipesrc;
11801         int ret;
11802
11803         ret = intel_ring_begin(req, 4);
11804         if (ret)
11805                 return ret;
11806
11807         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11808                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11809         intel_ring_emit(ring, fb->pitches[0] |
11810                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11811         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11812
11813         /* Contrary to the suggestions in the documentation,
11814          * "Enable Panel Fitter" does not seem to be required when page
11815          * flipping with a non-native mode, and worse causes a normal
11816          * modeset to fail.
11817          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11818          */
11819         pf = 0;
11820         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11821         intel_ring_emit(ring, pf | pipesrc);
11822
11823         return 0;
11824 }
11825
11826 static int intel_gen7_queue_flip(struct drm_device *dev,
11827                                  struct drm_crtc *crtc,
11828                                  struct drm_framebuffer *fb,
11829                                  struct drm_i915_gem_object *obj,
11830                                  struct drm_i915_gem_request *req,
11831                                  uint32_t flags)
11832 {
11833         struct intel_ring *ring = req->ring;
11834         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11835         uint32_t plane_bit = 0;
11836         int len, ret;
11837
11838         switch (intel_crtc->plane) {
11839         case PLANE_A:
11840                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11841                 break;
11842         case PLANE_B:
11843                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11844                 break;
11845         case PLANE_C:
11846                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11847                 break;
11848         default:
11849                 WARN_ONCE(1, "unknown plane in flip command\n");
11850                 return -ENODEV;
11851         }
11852
11853         len = 4;
11854         if (req->engine->id == RCS) {
11855                 len += 6;
11856                 /*
11857                  * On Gen 8, SRM is now taking an extra dword to accommodate
11858                  * 48bits addresses, and we need a NOOP for the batch size to
11859                  * stay even.
11860                  */
11861                 if (IS_GEN8(dev))
11862                         len += 2;
11863         }
11864
11865         /*
11866          * BSpec MI_DISPLAY_FLIP for IVB:
11867          * "The full packet must be contained within the same cache line."
11868          *
11869          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11870          * cacheline, if we ever start emitting more commands before
11871          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11872          * then do the cacheline alignment, and finally emit the
11873          * MI_DISPLAY_FLIP.
11874          */
11875         ret = intel_ring_cacheline_align(req);
11876         if (ret)
11877                 return ret;
11878
11879         ret = intel_ring_begin(req, len);
11880         if (ret)
11881                 return ret;
11882
11883         /* Unmask the flip-done completion message. Note that the bspec says that
11884          * we should do this for both the BCS and RCS, and that we must not unmask
11885          * more than one flip event at any time (or ensure that one flip message
11886          * can be sent by waiting for flip-done prior to queueing new flips).
11887          * Experimentation says that BCS works despite DERRMR masking all
11888          * flip-done completion events and that unmasking all planes at once
11889          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11890          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11891          */
11892         if (req->engine->id == RCS) {
11893                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11894                 intel_ring_emit_reg(ring, DERRMR);
11895                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11896                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11897                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11898                 if (IS_GEN8(dev))
11899                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11900                                               MI_SRM_LRM_GLOBAL_GTT);
11901                 else
11902                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11903                                               MI_SRM_LRM_GLOBAL_GTT);
11904                 intel_ring_emit_reg(ring, DERRMR);
11905                 intel_ring_emit(ring,
11906                                 i915_ggtt_offset(req->engine->scratch) + 256);
11907                 if (IS_GEN8(dev)) {
11908                         intel_ring_emit(ring, 0);
11909                         intel_ring_emit(ring, MI_NOOP);
11910                 }
11911         }
11912
11913         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11914         intel_ring_emit(ring, fb->pitches[0] |
11915                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11916         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11917         intel_ring_emit(ring, (MI_NOOP));
11918
11919         return 0;
11920 }
11921
11922 static bool use_mmio_flip(struct intel_engine_cs *engine,
11923                           struct drm_i915_gem_object *obj)
11924 {
11925         struct reservation_object *resv;
11926
11927         /*
11928          * This is not being used for older platforms, because
11929          * non-availability of flip done interrupt forces us to use
11930          * CS flips. Older platforms derive flip done using some clever
11931          * tricks involving the flip_pending status bits and vblank irqs.
11932          * So using MMIO flips there would disrupt this mechanism.
11933          */
11934
11935         if (engine == NULL)
11936                 return true;
11937
11938         if (INTEL_GEN(engine->i915) < 5)
11939                 return false;
11940
11941         if (i915.use_mmio_flip < 0)
11942                 return false;
11943         else if (i915.use_mmio_flip > 0)
11944                 return true;
11945         else if (i915.enable_execlists)
11946                 return true;
11947
11948         resv = i915_gem_object_get_dmabuf_resv(obj);
11949         if (resv && !reservation_object_test_signaled_rcu(resv, false))
11950                 return true;
11951
11952         return engine != i915_gem_active_get_engine(&obj->last_write,
11953                                                     &obj->base.dev->struct_mutex);
11954 }
11955
11956 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11957                              unsigned int rotation,
11958                              struct intel_flip_work *work)
11959 {
11960         struct drm_device *dev = intel_crtc->base.dev;
11961         struct drm_i915_private *dev_priv = to_i915(dev);
11962         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11963         const enum pipe pipe = intel_crtc->pipe;
11964         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11965
11966         ctl = I915_READ(PLANE_CTL(pipe, 0));
11967         ctl &= ~PLANE_CTL_TILED_MASK;
11968         switch (fb->modifier[0]) {
11969         case DRM_FORMAT_MOD_NONE:
11970                 break;
11971         case I915_FORMAT_MOD_X_TILED:
11972                 ctl |= PLANE_CTL_TILED_X;
11973                 break;
11974         case I915_FORMAT_MOD_Y_TILED:
11975                 ctl |= PLANE_CTL_TILED_Y;
11976                 break;
11977         case I915_FORMAT_MOD_Yf_TILED:
11978                 ctl |= PLANE_CTL_TILED_YF;
11979                 break;
11980         default:
11981                 MISSING_CASE(fb->modifier[0]);
11982         }
11983
11984         /*
11985          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11986          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11987          */
11988         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11989         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11990
11991         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11992         POSTING_READ(PLANE_SURF(pipe, 0));
11993 }
11994
11995 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11996                              struct intel_flip_work *work)
11997 {
11998         struct drm_device *dev = intel_crtc->base.dev;
11999         struct drm_i915_private *dev_priv = to_i915(dev);
12000         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12001         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12002         u32 dspcntr;
12003
12004         dspcntr = I915_READ(reg);
12005
12006         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
12007                 dspcntr |= DISPPLANE_TILED;
12008         else
12009                 dspcntr &= ~DISPPLANE_TILED;
12010
12011         I915_WRITE(reg, dspcntr);
12012
12013         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12014         POSTING_READ(DSPSURF(intel_crtc->plane));
12015 }
12016
12017 static void intel_mmio_flip_work_func(struct work_struct *w)
12018 {
12019         struct intel_flip_work *work =
12020                 container_of(w, struct intel_flip_work, mmio_work);
12021         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12022         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12023         struct intel_framebuffer *intel_fb =
12024                 to_intel_framebuffer(crtc->base.primary->fb);
12025         struct drm_i915_gem_object *obj = intel_fb->obj;
12026         struct reservation_object *resv;
12027
12028         if (work->flip_queued_req)
12029                 WARN_ON(i915_wait_request(work->flip_queued_req,
12030                                           0, NULL, NO_WAITBOOST));
12031
12032         /* For framebuffer backed by dmabuf, wait for fence */
12033         resv = i915_gem_object_get_dmabuf_resv(obj);
12034         if (resv)
12035                 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
12036                                                             MAX_SCHEDULE_TIMEOUT) < 0);
12037
12038         intel_pipe_update_start(crtc);
12039
12040         if (INTEL_GEN(dev_priv) >= 9)
12041                 skl_do_mmio_flip(crtc, work->rotation, work);
12042         else
12043                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12044                 ilk_do_mmio_flip(crtc, work);
12045
12046         intel_pipe_update_end(crtc, work);
12047 }
12048
12049 static int intel_default_queue_flip(struct drm_device *dev,
12050                                     struct drm_crtc *crtc,
12051                                     struct drm_framebuffer *fb,
12052                                     struct drm_i915_gem_object *obj,
12053                                     struct drm_i915_gem_request *req,
12054                                     uint32_t flags)
12055 {
12056         return -ENODEV;
12057 }
12058
12059 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12060                                       struct intel_crtc *intel_crtc,
12061                                       struct intel_flip_work *work)
12062 {
12063         u32 addr, vblank;
12064
12065         if (!atomic_read(&work->pending))
12066                 return false;
12067
12068         smp_rmb();
12069
12070         vblank = intel_crtc_get_vblank_counter(intel_crtc);
12071         if (work->flip_ready_vblank == 0) {
12072                 if (work->flip_queued_req &&
12073                     !i915_gem_request_completed(work->flip_queued_req))
12074                         return false;
12075
12076                 work->flip_ready_vblank = vblank;
12077         }
12078
12079         if (vblank - work->flip_ready_vblank < 3)
12080                 return false;
12081
12082         /* Potential stall - if we see that the flip has happened,
12083          * assume a missed interrupt. */
12084         if (INTEL_GEN(dev_priv) >= 4)
12085                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12086         else
12087                 addr = I915_READ(DSPADDR(intel_crtc->plane));
12088
12089         /* There is a potential issue here with a false positive after a flip
12090          * to the same address. We could address this by checking for a
12091          * non-incrementing frame counter.
12092          */
12093         return addr == work->gtt_offset;
12094 }
12095
12096 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12097 {
12098         struct drm_device *dev = &dev_priv->drm;
12099         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
12100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12101         struct intel_flip_work *work;
12102
12103         WARN_ON(!in_interrupt());
12104
12105         if (crtc == NULL)
12106                 return;
12107
12108         spin_lock(&dev->event_lock);
12109         work = intel_crtc->flip_work;
12110
12111         if (work != NULL && !is_mmio_work(work) &&
12112             __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12113                 WARN_ONCE(1,
12114                           "Kicking stuck page flip: queued at %d, now %d\n",
12115                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12116                 page_flip_completed(intel_crtc);
12117                 work = NULL;
12118         }
12119
12120         if (work != NULL && !is_mmio_work(work) &&
12121             intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12122                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12123         spin_unlock(&dev->event_lock);
12124 }
12125
12126 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12127                                 struct drm_framebuffer *fb,
12128                                 struct drm_pending_vblank_event *event,
12129                                 uint32_t page_flip_flags)
12130 {
12131         struct drm_device *dev = crtc->dev;
12132         struct drm_i915_private *dev_priv = to_i915(dev);
12133         struct drm_framebuffer *old_fb = crtc->primary->fb;
12134         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12136         struct drm_plane *primary = crtc->primary;
12137         enum pipe pipe = intel_crtc->pipe;
12138         struct intel_flip_work *work;
12139         struct intel_engine_cs *engine;
12140         bool mmio_flip;
12141         struct drm_i915_gem_request *request;
12142         struct i915_vma *vma;
12143         int ret;
12144
12145         /*
12146          * drm_mode_page_flip_ioctl() should already catch this, but double
12147          * check to be safe.  In the future we may enable pageflipping from
12148          * a disabled primary plane.
12149          */
12150         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12151                 return -EBUSY;
12152
12153         /* Can't change pixel format via MI display flips. */
12154         if (fb->pixel_format != crtc->primary->fb->pixel_format)
12155                 return -EINVAL;
12156
12157         /*
12158          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12159          * Note that pitch changes could also affect these register.
12160          */
12161         if (INTEL_INFO(dev)->gen > 3 &&
12162             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12163              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12164                 return -EINVAL;
12165
12166         if (i915_terminally_wedged(&dev_priv->gpu_error))
12167                 goto out_hang;
12168
12169         work = kzalloc(sizeof(*work), GFP_KERNEL);
12170         if (work == NULL)
12171                 return -ENOMEM;
12172
12173         work->event = event;
12174         work->crtc = crtc;
12175         work->old_fb = old_fb;
12176         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12177
12178         ret = drm_crtc_vblank_get(crtc);
12179         if (ret)
12180                 goto free_work;
12181
12182         /* We borrow the event spin lock for protecting flip_work */
12183         spin_lock_irq(&dev->event_lock);
12184         if (intel_crtc->flip_work) {
12185                 /* Before declaring the flip queue wedged, check if
12186                  * the hardware completed the operation behind our backs.
12187                  */
12188                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12189                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12190                         page_flip_completed(intel_crtc);
12191                 } else {
12192                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12193                         spin_unlock_irq(&dev->event_lock);
12194
12195                         drm_crtc_vblank_put(crtc);
12196                         kfree(work);
12197                         return -EBUSY;
12198                 }
12199         }
12200         intel_crtc->flip_work = work;
12201         spin_unlock_irq(&dev->event_lock);
12202
12203         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12204                 flush_workqueue(dev_priv->wq);
12205
12206         /* Reference the objects for the scheduled work. */
12207         drm_framebuffer_reference(work->old_fb);
12208
12209         crtc->primary->fb = fb;
12210         update_state_fb(crtc->primary);
12211
12212         work->pending_flip_obj = i915_gem_object_get(obj);
12213
12214         ret = i915_mutex_lock_interruptible(dev);
12215         if (ret)
12216                 goto cleanup;
12217
12218         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12219         if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12220                 ret = -EIO;
12221                 goto cleanup;
12222         }
12223
12224         atomic_inc(&intel_crtc->unpin_work_count);
12225
12226         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12227                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12228
12229         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12230                 engine = &dev_priv->engine[BCS];
12231                 if (fb->modifier[0] != old_fb->modifier[0])
12232                         /* vlv: DISPLAY_FLIP fails to change tiling */
12233                         engine = NULL;
12234         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
12235                 engine = &dev_priv->engine[BCS];
12236         } else if (INTEL_INFO(dev)->gen >= 7) {
12237                 engine = i915_gem_active_get_engine(&obj->last_write,
12238                                                     &obj->base.dev->struct_mutex);
12239                 if (engine == NULL || engine->id != RCS)
12240                         engine = &dev_priv->engine[BCS];
12241         } else {
12242                 engine = &dev_priv->engine[RCS];
12243         }
12244
12245         mmio_flip = use_mmio_flip(engine, obj);
12246
12247         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12248         if (IS_ERR(vma)) {
12249                 ret = PTR_ERR(vma);
12250                 goto cleanup_pending;
12251         }
12252
12253         work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12254         work->gtt_offset += intel_crtc->dspaddr_offset;
12255         work->rotation = crtc->primary->state->rotation;
12256
12257         /*
12258          * There's the potential that the next frame will not be compatible with
12259          * FBC, so we want to call pre_update() before the actual page flip.
12260          * The problem is that pre_update() caches some information about the fb
12261          * object, so we want to do this only after the object is pinned. Let's
12262          * be on the safe side and do this immediately before scheduling the
12263          * flip.
12264          */
12265         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12266                              to_intel_plane_state(primary->state));
12267
12268         if (mmio_flip) {
12269                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12270
12271                 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12272                                                             &obj->base.dev->struct_mutex);
12273                 schedule_work(&work->mmio_work);
12274         } else {
12275                 request = i915_gem_request_alloc(engine, engine->last_context);
12276                 if (IS_ERR(request)) {
12277                         ret = PTR_ERR(request);
12278                         goto cleanup_unpin;
12279                 }
12280
12281                 ret = i915_gem_request_await_object(request, obj, false);
12282                 if (ret)
12283                         goto cleanup_request;
12284
12285                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12286                                                    page_flip_flags);
12287                 if (ret)
12288                         goto cleanup_request;
12289
12290                 intel_mark_page_flip_active(intel_crtc, work);
12291
12292                 work->flip_queued_req = i915_gem_request_get(request);
12293                 i915_add_request_no_flush(request);
12294         }
12295
12296         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12297                           to_intel_plane(primary)->frontbuffer_bit);
12298         mutex_unlock(&dev->struct_mutex);
12299
12300         intel_frontbuffer_flip_prepare(to_i915(dev),
12301                                        to_intel_plane(primary)->frontbuffer_bit);
12302
12303         trace_i915_flip_request(intel_crtc->plane, obj);
12304
12305         return 0;
12306
12307 cleanup_request:
12308         i915_add_request_no_flush(request);
12309 cleanup_unpin:
12310         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12311 cleanup_pending:
12312         atomic_dec(&intel_crtc->unpin_work_count);
12313         mutex_unlock(&dev->struct_mutex);
12314 cleanup:
12315         crtc->primary->fb = old_fb;
12316         update_state_fb(crtc->primary);
12317
12318         i915_gem_object_put_unlocked(obj);
12319         drm_framebuffer_unreference(work->old_fb);
12320
12321         spin_lock_irq(&dev->event_lock);
12322         intel_crtc->flip_work = NULL;
12323         spin_unlock_irq(&dev->event_lock);
12324
12325         drm_crtc_vblank_put(crtc);
12326 free_work:
12327         kfree(work);
12328
12329         if (ret == -EIO) {
12330                 struct drm_atomic_state *state;
12331                 struct drm_plane_state *plane_state;
12332
12333 out_hang:
12334                 state = drm_atomic_state_alloc(dev);
12335                 if (!state)
12336                         return -ENOMEM;
12337                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12338
12339 retry:
12340                 plane_state = drm_atomic_get_plane_state(state, primary);
12341                 ret = PTR_ERR_OR_ZERO(plane_state);
12342                 if (!ret) {
12343                         drm_atomic_set_fb_for_plane(plane_state, fb);
12344
12345                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12346                         if (!ret)
12347                                 ret = drm_atomic_commit(state);
12348                 }
12349
12350                 if (ret == -EDEADLK) {
12351                         drm_modeset_backoff(state->acquire_ctx);
12352                         drm_atomic_state_clear(state);
12353                         goto retry;
12354                 }
12355
12356                 if (ret)
12357                         drm_atomic_state_free(state);
12358
12359                 if (ret == 0 && event) {
12360                         spin_lock_irq(&dev->event_lock);
12361                         drm_crtc_send_vblank_event(crtc, event);
12362                         spin_unlock_irq(&dev->event_lock);
12363                 }
12364         }
12365         return ret;
12366 }
12367
12368
12369 /**
12370  * intel_wm_need_update - Check whether watermarks need updating
12371  * @plane: drm plane
12372  * @state: new plane state
12373  *
12374  * Check current plane state versus the new one to determine whether
12375  * watermarks need to be recalculated.
12376  *
12377  * Returns true or false.
12378  */
12379 static bool intel_wm_need_update(struct drm_plane *plane,
12380                                  struct drm_plane_state *state)
12381 {
12382         struct intel_plane_state *new = to_intel_plane_state(state);
12383         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12384
12385         /* Update watermarks on tiling or size changes. */
12386         if (new->base.visible != cur->base.visible)
12387                 return true;
12388
12389         if (!cur->base.fb || !new->base.fb)
12390                 return false;
12391
12392         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12393             cur->base.rotation != new->base.rotation ||
12394             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12395             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12396             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12397             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12398                 return true;
12399
12400         return false;
12401 }
12402
12403 static bool needs_scaling(struct intel_plane_state *state)
12404 {
12405         int src_w = drm_rect_width(&state->base.src) >> 16;
12406         int src_h = drm_rect_height(&state->base.src) >> 16;
12407         int dst_w = drm_rect_width(&state->base.dst);
12408         int dst_h = drm_rect_height(&state->base.dst);
12409
12410         return (src_w != dst_w || src_h != dst_h);
12411 }
12412
12413 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12414                                     struct drm_plane_state *plane_state)
12415 {
12416         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12417         struct drm_crtc *crtc = crtc_state->crtc;
12418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12419         struct drm_plane *plane = plane_state->plane;
12420         struct drm_device *dev = crtc->dev;
12421         struct drm_i915_private *dev_priv = to_i915(dev);
12422         struct intel_plane_state *old_plane_state =
12423                 to_intel_plane_state(plane->state);
12424         bool mode_changed = needs_modeset(crtc_state);
12425         bool was_crtc_enabled = crtc->state->active;
12426         bool is_crtc_enabled = crtc_state->active;
12427         bool turn_off, turn_on, visible, was_visible;
12428         struct drm_framebuffer *fb = plane_state->fb;
12429         int ret;
12430
12431         if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12432                 ret = skl_update_scaler_plane(
12433                         to_intel_crtc_state(crtc_state),
12434                         to_intel_plane_state(plane_state));
12435                 if (ret)
12436                         return ret;
12437         }
12438
12439         was_visible = old_plane_state->base.visible;
12440         visible = to_intel_plane_state(plane_state)->base.visible;
12441
12442         if (!was_crtc_enabled && WARN_ON(was_visible))
12443                 was_visible = false;
12444
12445         /*
12446          * Visibility is calculated as if the crtc was on, but
12447          * after scaler setup everything depends on it being off
12448          * when the crtc isn't active.
12449          *
12450          * FIXME this is wrong for watermarks. Watermarks should also
12451          * be computed as if the pipe would be active. Perhaps move
12452          * per-plane wm computation to the .check_plane() hook, and
12453          * only combine the results from all planes in the current place?
12454          */
12455         if (!is_crtc_enabled)
12456                 to_intel_plane_state(plane_state)->base.visible = visible = false;
12457
12458         if (!was_visible && !visible)
12459                 return 0;
12460
12461         if (fb != old_plane_state->base.fb)
12462                 pipe_config->fb_changed = true;
12463
12464         turn_off = was_visible && (!visible || mode_changed);
12465         turn_on = visible && (!was_visible || mode_changed);
12466
12467         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12468                          intel_crtc->base.base.id,
12469                          intel_crtc->base.name,
12470                          plane->base.id, plane->name,
12471                          fb ? fb->base.id : -1);
12472
12473         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12474                          plane->base.id, plane->name,
12475                          was_visible, visible,
12476                          turn_off, turn_on, mode_changed);
12477
12478         if (turn_on) {
12479                 pipe_config->update_wm_pre = true;
12480
12481                 /* must disable cxsr around plane enable/disable */
12482                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12483                         pipe_config->disable_cxsr = true;
12484         } else if (turn_off) {
12485                 pipe_config->update_wm_post = true;
12486
12487                 /* must disable cxsr around plane enable/disable */
12488                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12489                         pipe_config->disable_cxsr = true;
12490         } else if (intel_wm_need_update(plane, plane_state)) {
12491                 /* FIXME bollocks */
12492                 pipe_config->update_wm_pre = true;
12493                 pipe_config->update_wm_post = true;
12494         }
12495
12496         /* Pre-gen9 platforms need two-step watermark updates */
12497         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12498             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12499                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12500
12501         if (visible || was_visible)
12502                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12503
12504         /*
12505          * WaCxSRDisabledForSpriteScaling:ivb
12506          *
12507          * cstate->update_wm was already set above, so this flag will
12508          * take effect when we commit and program watermarks.
12509          */
12510         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12511             needs_scaling(to_intel_plane_state(plane_state)) &&
12512             !needs_scaling(old_plane_state))
12513                 pipe_config->disable_lp_wm = true;
12514
12515         return 0;
12516 }
12517
12518 static bool encoders_cloneable(const struct intel_encoder *a,
12519                                const struct intel_encoder *b)
12520 {
12521         /* masks could be asymmetric, so check both ways */
12522         return a == b || (a->cloneable & (1 << b->type) &&
12523                           b->cloneable & (1 << a->type));
12524 }
12525
12526 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12527                                          struct intel_crtc *crtc,
12528                                          struct intel_encoder *encoder)
12529 {
12530         struct intel_encoder *source_encoder;
12531         struct drm_connector *connector;
12532         struct drm_connector_state *connector_state;
12533         int i;
12534
12535         for_each_connector_in_state(state, connector, connector_state, i) {
12536                 if (connector_state->crtc != &crtc->base)
12537                         continue;
12538
12539                 source_encoder =
12540                         to_intel_encoder(connector_state->best_encoder);
12541                 if (!encoders_cloneable(encoder, source_encoder))
12542                         return false;
12543         }
12544
12545         return true;
12546 }
12547
12548 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12549                                    struct drm_crtc_state *crtc_state)
12550 {
12551         struct drm_device *dev = crtc->dev;
12552         struct drm_i915_private *dev_priv = to_i915(dev);
12553         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12554         struct intel_crtc_state *pipe_config =
12555                 to_intel_crtc_state(crtc_state);
12556         struct drm_atomic_state *state = crtc_state->state;
12557         int ret;
12558         bool mode_changed = needs_modeset(crtc_state);
12559
12560         if (mode_changed && !crtc_state->active)
12561                 pipe_config->update_wm_post = true;
12562
12563         if (mode_changed && crtc_state->enable &&
12564             dev_priv->display.crtc_compute_clock &&
12565             !WARN_ON(pipe_config->shared_dpll)) {
12566                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12567                                                            pipe_config);
12568                 if (ret)
12569                         return ret;
12570         }
12571
12572         if (crtc_state->color_mgmt_changed) {
12573                 ret = intel_color_check(crtc, crtc_state);
12574                 if (ret)
12575                         return ret;
12576
12577                 /*
12578                  * Changing color management on Intel hardware is
12579                  * handled as part of planes update.
12580                  */
12581                 crtc_state->planes_changed = true;
12582         }
12583
12584         ret = 0;
12585         if (dev_priv->display.compute_pipe_wm) {
12586                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12587                 if (ret) {
12588                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12589                         return ret;
12590                 }
12591         }
12592
12593         if (dev_priv->display.compute_intermediate_wm &&
12594             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12595                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12596                         return 0;
12597
12598                 /*
12599                  * Calculate 'intermediate' watermarks that satisfy both the
12600                  * old state and the new state.  We can program these
12601                  * immediately.
12602                  */
12603                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12604                                                                 intel_crtc,
12605                                                                 pipe_config);
12606                 if (ret) {
12607                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12608                         return ret;
12609                 }
12610         } else if (dev_priv->display.compute_intermediate_wm) {
12611                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12612                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12613         }
12614
12615         if (INTEL_INFO(dev)->gen >= 9) {
12616                 if (mode_changed)
12617                         ret = skl_update_scaler_crtc(pipe_config);
12618
12619                 if (!ret)
12620                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12621                                                          pipe_config);
12622         }
12623
12624         return ret;
12625 }
12626
12627 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12628         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12629         .atomic_begin = intel_begin_crtc_commit,
12630         .atomic_flush = intel_finish_crtc_commit,
12631         .atomic_check = intel_crtc_atomic_check,
12632 };
12633
12634 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12635 {
12636         struct intel_connector *connector;
12637
12638         for_each_intel_connector(dev, connector) {
12639                 if (connector->base.state->crtc)
12640                         drm_connector_unreference(&connector->base);
12641
12642                 if (connector->base.encoder) {
12643                         connector->base.state->best_encoder =
12644                                 connector->base.encoder;
12645                         connector->base.state->crtc =
12646                                 connector->base.encoder->crtc;
12647
12648                         drm_connector_reference(&connector->base);
12649                 } else {
12650                         connector->base.state->best_encoder = NULL;
12651                         connector->base.state->crtc = NULL;
12652                 }
12653         }
12654 }
12655
12656 static void
12657 connected_sink_compute_bpp(struct intel_connector *connector,
12658                            struct intel_crtc_state *pipe_config)
12659 {
12660         const struct drm_display_info *info = &connector->base.display_info;
12661         int bpp = pipe_config->pipe_bpp;
12662
12663         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12664                       connector->base.base.id,
12665                       connector->base.name);
12666
12667         /* Don't use an invalid EDID bpc value */
12668         if (info->bpc != 0 && info->bpc * 3 < bpp) {
12669                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12670                               bpp, info->bpc * 3);
12671                 pipe_config->pipe_bpp = info->bpc * 3;
12672         }
12673
12674         /* Clamp bpp to 8 on screens without EDID 1.4 */
12675         if (info->bpc == 0 && bpp > 24) {
12676                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12677                               bpp);
12678                 pipe_config->pipe_bpp = 24;
12679         }
12680 }
12681
12682 static int
12683 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12684                           struct intel_crtc_state *pipe_config)
12685 {
12686         struct drm_device *dev = crtc->base.dev;
12687         struct drm_atomic_state *state;
12688         struct drm_connector *connector;
12689         struct drm_connector_state *connector_state;
12690         int bpp, i;
12691
12692         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12693                 bpp = 10*3;
12694         else if (INTEL_INFO(dev)->gen >= 5)
12695                 bpp = 12*3;
12696         else
12697                 bpp = 8*3;
12698
12699
12700         pipe_config->pipe_bpp = bpp;
12701
12702         state = pipe_config->base.state;
12703
12704         /* Clamp display bpp to EDID value */
12705         for_each_connector_in_state(state, connector, connector_state, i) {
12706                 if (connector_state->crtc != &crtc->base)
12707                         continue;
12708
12709                 connected_sink_compute_bpp(to_intel_connector(connector),
12710                                            pipe_config);
12711         }
12712
12713         return bpp;
12714 }
12715
12716 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12717 {
12718         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12719                         "type: 0x%x flags: 0x%x\n",
12720                 mode->crtc_clock,
12721                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12722                 mode->crtc_hsync_end, mode->crtc_htotal,
12723                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12724                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12725 }
12726
12727 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12728                                    struct intel_crtc_state *pipe_config,
12729                                    const char *context)
12730 {
12731         struct drm_device *dev = crtc->base.dev;
12732         struct drm_plane *plane;
12733         struct intel_plane *intel_plane;
12734         struct intel_plane_state *state;
12735         struct drm_framebuffer *fb;
12736
12737         DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12738                       crtc->base.base.id, crtc->base.name,
12739                       context, pipe_config, pipe_name(crtc->pipe));
12740
12741         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12742         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12743                       pipe_config->pipe_bpp, pipe_config->dither);
12744         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12745                       pipe_config->has_pch_encoder,
12746                       pipe_config->fdi_lanes,
12747                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12748                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12749                       pipe_config->fdi_m_n.tu);
12750         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12751                       intel_crtc_has_dp_encoder(pipe_config),
12752                       pipe_config->lane_count,
12753                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12754                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12755                       pipe_config->dp_m_n.tu);
12756
12757         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12758                       intel_crtc_has_dp_encoder(pipe_config),
12759                       pipe_config->lane_count,
12760                       pipe_config->dp_m2_n2.gmch_m,
12761                       pipe_config->dp_m2_n2.gmch_n,
12762                       pipe_config->dp_m2_n2.link_m,
12763                       pipe_config->dp_m2_n2.link_n,
12764                       pipe_config->dp_m2_n2.tu);
12765
12766         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12767                       pipe_config->has_audio,
12768                       pipe_config->has_infoframe);
12769
12770         DRM_DEBUG_KMS("requested mode:\n");
12771         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12772         DRM_DEBUG_KMS("adjusted mode:\n");
12773         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12774         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12775         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12776         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12777                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12778         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12779                       crtc->num_scalers,
12780                       pipe_config->scaler_state.scaler_users,
12781                       pipe_config->scaler_state.scaler_id);
12782         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12783                       pipe_config->gmch_pfit.control,
12784                       pipe_config->gmch_pfit.pgm_ratios,
12785                       pipe_config->gmch_pfit.lvds_border_bits);
12786         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12787                       pipe_config->pch_pfit.pos,
12788                       pipe_config->pch_pfit.size,
12789                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12790         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12791         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12792
12793         if (IS_BROXTON(dev)) {
12794                 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12795                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12796                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12797                               pipe_config->dpll_hw_state.ebb0,
12798                               pipe_config->dpll_hw_state.ebb4,
12799                               pipe_config->dpll_hw_state.pll0,
12800                               pipe_config->dpll_hw_state.pll1,
12801                               pipe_config->dpll_hw_state.pll2,
12802                               pipe_config->dpll_hw_state.pll3,
12803                               pipe_config->dpll_hw_state.pll6,
12804                               pipe_config->dpll_hw_state.pll8,
12805                               pipe_config->dpll_hw_state.pll9,
12806                               pipe_config->dpll_hw_state.pll10,
12807                               pipe_config->dpll_hw_state.pcsdw12);
12808         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12809                 DRM_DEBUG_KMS("dpll_hw_state: "
12810                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12811                               pipe_config->dpll_hw_state.ctrl1,
12812                               pipe_config->dpll_hw_state.cfgcr1,
12813                               pipe_config->dpll_hw_state.cfgcr2);
12814         } else if (HAS_DDI(dev)) {
12815                 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12816                               pipe_config->dpll_hw_state.wrpll,
12817                               pipe_config->dpll_hw_state.spll);
12818         } else {
12819                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12820                               "fp0: 0x%x, fp1: 0x%x\n",
12821                               pipe_config->dpll_hw_state.dpll,
12822                               pipe_config->dpll_hw_state.dpll_md,
12823                               pipe_config->dpll_hw_state.fp0,
12824                               pipe_config->dpll_hw_state.fp1);
12825         }
12826
12827         DRM_DEBUG_KMS("planes on this crtc\n");
12828         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12829                 char *format_name;
12830                 intel_plane = to_intel_plane(plane);
12831                 if (intel_plane->pipe != crtc->pipe)
12832                         continue;
12833
12834                 state = to_intel_plane_state(plane->state);
12835                 fb = state->base.fb;
12836                 if (!fb) {
12837                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12838                                       plane->base.id, plane->name, state->scaler_id);
12839                         continue;
12840                 }
12841
12842                 format_name = drm_get_format_name(fb->pixel_format);
12843
12844                 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12845                               plane->base.id, plane->name);
12846                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12847                               fb->base.id, fb->width, fb->height, format_name);
12848                 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12849                               state->scaler_id,
12850                               state->base.src.x1 >> 16,
12851                               state->base.src.y1 >> 16,
12852                               drm_rect_width(&state->base.src) >> 16,
12853                               drm_rect_height(&state->base.src) >> 16,
12854                               state->base.dst.x1, state->base.dst.y1,
12855                               drm_rect_width(&state->base.dst),
12856                               drm_rect_height(&state->base.dst));
12857
12858                 kfree(format_name);
12859         }
12860 }
12861
12862 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12863 {
12864         struct drm_device *dev = state->dev;
12865         struct drm_connector *connector;
12866         unsigned int used_ports = 0;
12867         unsigned int used_mst_ports = 0;
12868
12869         /*
12870          * Walk the connector list instead of the encoder
12871          * list to detect the problem on ddi platforms
12872          * where there's just one encoder per digital port.
12873          */
12874         drm_for_each_connector(connector, dev) {
12875                 struct drm_connector_state *connector_state;
12876                 struct intel_encoder *encoder;
12877
12878                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12879                 if (!connector_state)
12880                         connector_state = connector->state;
12881
12882                 if (!connector_state->best_encoder)
12883                         continue;
12884
12885                 encoder = to_intel_encoder(connector_state->best_encoder);
12886
12887                 WARN_ON(!connector_state->crtc);
12888
12889                 switch (encoder->type) {
12890                         unsigned int port_mask;
12891                 case INTEL_OUTPUT_UNKNOWN:
12892                         if (WARN_ON(!HAS_DDI(dev)))
12893                                 break;
12894                 case INTEL_OUTPUT_DP:
12895                 case INTEL_OUTPUT_HDMI:
12896                 case INTEL_OUTPUT_EDP:
12897                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12898
12899                         /* the same port mustn't appear more than once */
12900                         if (used_ports & port_mask)
12901                                 return false;
12902
12903                         used_ports |= port_mask;
12904                         break;
12905                 case INTEL_OUTPUT_DP_MST:
12906                         used_mst_ports |=
12907                                 1 << enc_to_mst(&encoder->base)->primary->port;
12908                         break;
12909                 default:
12910                         break;
12911                 }
12912         }
12913
12914         /* can't mix MST and SST/HDMI on the same port */
12915         if (used_ports & used_mst_ports)
12916                 return false;
12917
12918         return true;
12919 }
12920
12921 static void
12922 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12923 {
12924         struct drm_crtc_state tmp_state;
12925         struct intel_crtc_scaler_state scaler_state;
12926         struct intel_dpll_hw_state dpll_hw_state;
12927         struct intel_shared_dpll *shared_dpll;
12928         bool force_thru;
12929
12930         /* FIXME: before the switch to atomic started, a new pipe_config was
12931          * kzalloc'd. Code that depends on any field being zero should be
12932          * fixed, so that the crtc_state can be safely duplicated. For now,
12933          * only fields that are know to not cause problems are preserved. */
12934
12935         tmp_state = crtc_state->base;
12936         scaler_state = crtc_state->scaler_state;
12937         shared_dpll = crtc_state->shared_dpll;
12938         dpll_hw_state = crtc_state->dpll_hw_state;
12939         force_thru = crtc_state->pch_pfit.force_thru;
12940
12941         memset(crtc_state, 0, sizeof *crtc_state);
12942
12943         crtc_state->base = tmp_state;
12944         crtc_state->scaler_state = scaler_state;
12945         crtc_state->shared_dpll = shared_dpll;
12946         crtc_state->dpll_hw_state = dpll_hw_state;
12947         crtc_state->pch_pfit.force_thru = force_thru;
12948 }
12949
12950 static int
12951 intel_modeset_pipe_config(struct drm_crtc *crtc,
12952                           struct intel_crtc_state *pipe_config)
12953 {
12954         struct drm_atomic_state *state = pipe_config->base.state;
12955         struct intel_encoder *encoder;
12956         struct drm_connector *connector;
12957         struct drm_connector_state *connector_state;
12958         int base_bpp, ret = -EINVAL;
12959         int i;
12960         bool retry = true;
12961
12962         clear_intel_crtc_state(pipe_config);
12963
12964         pipe_config->cpu_transcoder =
12965                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12966
12967         /*
12968          * Sanitize sync polarity flags based on requested ones. If neither
12969          * positive or negative polarity is requested, treat this as meaning
12970          * negative polarity.
12971          */
12972         if (!(pipe_config->base.adjusted_mode.flags &
12973               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12974                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12975
12976         if (!(pipe_config->base.adjusted_mode.flags &
12977               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12978                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12979
12980         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12981                                              pipe_config);
12982         if (base_bpp < 0)
12983                 goto fail;
12984
12985         /*
12986          * Determine the real pipe dimensions. Note that stereo modes can
12987          * increase the actual pipe size due to the frame doubling and
12988          * insertion of additional space for blanks between the frame. This
12989          * is stored in the crtc timings. We use the requested mode to do this
12990          * computation to clearly distinguish it from the adjusted mode, which
12991          * can be changed by the connectors in the below retry loop.
12992          */
12993         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12994                                &pipe_config->pipe_src_w,
12995                                &pipe_config->pipe_src_h);
12996
12997         for_each_connector_in_state(state, connector, connector_state, i) {
12998                 if (connector_state->crtc != crtc)
12999                         continue;
13000
13001                 encoder = to_intel_encoder(connector_state->best_encoder);
13002
13003                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13004                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13005                         goto fail;
13006                 }
13007
13008                 /*
13009                  * Determine output_types before calling the .compute_config()
13010                  * hooks so that the hooks can use this information safely.
13011                  */
13012                 pipe_config->output_types |= 1 << encoder->type;
13013         }
13014
13015 encoder_retry:
13016         /* Ensure the port clock defaults are reset when retrying. */
13017         pipe_config->port_clock = 0;
13018         pipe_config->pixel_multiplier = 1;
13019
13020         /* Fill in default crtc timings, allow encoders to overwrite them. */
13021         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13022                               CRTC_STEREO_DOUBLE);
13023
13024         /* Pass our mode to the connectors and the CRTC to give them a chance to
13025          * adjust it according to limitations or connector properties, and also
13026          * a chance to reject the mode entirely.
13027          */
13028         for_each_connector_in_state(state, connector, connector_state, i) {
13029                 if (connector_state->crtc != crtc)
13030                         continue;
13031
13032                 encoder = to_intel_encoder(connector_state->best_encoder);
13033
13034                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13035                         DRM_DEBUG_KMS("Encoder config failure\n");
13036                         goto fail;
13037                 }
13038         }
13039
13040         /* Set default port clock if not overwritten by the encoder. Needs to be
13041          * done afterwards in case the encoder adjusts the mode. */
13042         if (!pipe_config->port_clock)
13043                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13044                         * pipe_config->pixel_multiplier;
13045
13046         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13047         if (ret < 0) {
13048                 DRM_DEBUG_KMS("CRTC fixup failed\n");
13049                 goto fail;
13050         }
13051
13052         if (ret == RETRY) {
13053                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13054                         ret = -EINVAL;
13055                         goto fail;
13056                 }
13057
13058                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13059                 retry = false;
13060                 goto encoder_retry;
13061         }
13062
13063         /* Dithering seems to not pass-through bits correctly when it should, so
13064          * only enable it on 6bpc panels. */
13065         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13066         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13067                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13068
13069 fail:
13070         return ret;
13071 }
13072
13073 static void
13074 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13075 {
13076         struct drm_crtc *crtc;
13077         struct drm_crtc_state *crtc_state;
13078         int i;
13079
13080         /* Double check state. */
13081         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13082                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13083
13084                 /* Update hwmode for vblank functions */
13085                 if (crtc->state->active)
13086                         crtc->hwmode = crtc->state->adjusted_mode;
13087                 else
13088                         crtc->hwmode.crtc_clock = 0;
13089
13090                 /*
13091                  * Update legacy state to satisfy fbc code. This can
13092                  * be removed when fbc uses the atomic state.
13093                  */
13094                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13095                         struct drm_plane_state *plane_state = crtc->primary->state;
13096
13097                         crtc->primary->fb = plane_state->fb;
13098                         crtc->x = plane_state->src_x >> 16;
13099                         crtc->y = plane_state->src_y >> 16;
13100                 }
13101         }
13102 }
13103
13104 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13105 {
13106         int diff;
13107
13108         if (clock1 == clock2)
13109                 return true;
13110
13111         if (!clock1 || !clock2)
13112                 return false;
13113
13114         diff = abs(clock1 - clock2);
13115
13116         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13117                 return true;
13118
13119         return false;
13120 }
13121
13122 static bool
13123 intel_compare_m_n(unsigned int m, unsigned int n,
13124                   unsigned int m2, unsigned int n2,
13125                   bool exact)
13126 {
13127         if (m == m2 && n == n2)
13128                 return true;
13129
13130         if (exact || !m || !n || !m2 || !n2)
13131                 return false;
13132
13133         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13134
13135         if (n > n2) {
13136                 while (n > n2) {
13137                         m2 <<= 1;
13138                         n2 <<= 1;
13139                 }
13140         } else if (n < n2) {
13141                 while (n < n2) {
13142                         m <<= 1;
13143                         n <<= 1;
13144                 }
13145         }
13146
13147         if (n != n2)
13148                 return false;
13149
13150         return intel_fuzzy_clock_check(m, m2);
13151 }
13152
13153 static bool
13154 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13155                        struct intel_link_m_n *m2_n2,
13156                        bool adjust)
13157 {
13158         if (m_n->tu == m2_n2->tu &&
13159             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13160                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13161             intel_compare_m_n(m_n->link_m, m_n->link_n,
13162                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13163                 if (adjust)
13164                         *m2_n2 = *m_n;
13165
13166                 return true;
13167         }
13168
13169         return false;
13170 }
13171
13172 static bool
13173 intel_pipe_config_compare(struct drm_device *dev,
13174                           struct intel_crtc_state *current_config,
13175                           struct intel_crtc_state *pipe_config,
13176                           bool adjust)
13177 {
13178         bool ret = true;
13179
13180 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13181         do { \
13182                 if (!adjust) \
13183                         DRM_ERROR(fmt, ##__VA_ARGS__); \
13184                 else \
13185                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13186         } while (0)
13187
13188 #define PIPE_CONF_CHECK_X(name) \
13189         if (current_config->name != pipe_config->name) { \
13190                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13191                           "(expected 0x%08x, found 0x%08x)\n", \
13192                           current_config->name, \
13193                           pipe_config->name); \
13194                 ret = false; \
13195         }
13196
13197 #define PIPE_CONF_CHECK_I(name) \
13198         if (current_config->name != pipe_config->name) { \
13199                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13200                           "(expected %i, found %i)\n", \
13201                           current_config->name, \
13202                           pipe_config->name); \
13203                 ret = false; \
13204         }
13205
13206 #define PIPE_CONF_CHECK_P(name) \
13207         if (current_config->name != pipe_config->name) { \
13208                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13209                           "(expected %p, found %p)\n", \
13210                           current_config->name, \
13211                           pipe_config->name); \
13212                 ret = false; \
13213         }
13214
13215 #define PIPE_CONF_CHECK_M_N(name) \
13216         if (!intel_compare_link_m_n(&current_config->name, \
13217                                     &pipe_config->name,\
13218                                     adjust)) { \
13219                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13220                           "(expected tu %i gmch %i/%i link %i/%i, " \
13221                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13222                           current_config->name.tu, \
13223                           current_config->name.gmch_m, \
13224                           current_config->name.gmch_n, \
13225                           current_config->name.link_m, \
13226                           current_config->name.link_n, \
13227                           pipe_config->name.tu, \
13228                           pipe_config->name.gmch_m, \
13229                           pipe_config->name.gmch_n, \
13230                           pipe_config->name.link_m, \
13231                           pipe_config->name.link_n); \
13232                 ret = false; \
13233         }
13234
13235 /* This is required for BDW+ where there is only one set of registers for
13236  * switching between high and low RR.
13237  * This macro can be used whenever a comparison has to be made between one
13238  * hw state and multiple sw state variables.
13239  */
13240 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13241         if (!intel_compare_link_m_n(&current_config->name, \
13242                                     &pipe_config->name, adjust) && \
13243             !intel_compare_link_m_n(&current_config->alt_name, \
13244                                     &pipe_config->name, adjust)) { \
13245                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13246                           "(expected tu %i gmch %i/%i link %i/%i, " \
13247                           "or tu %i gmch %i/%i link %i/%i, " \
13248                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13249                           current_config->name.tu, \
13250                           current_config->name.gmch_m, \
13251                           current_config->name.gmch_n, \
13252                           current_config->name.link_m, \
13253                           current_config->name.link_n, \
13254                           current_config->alt_name.tu, \
13255                           current_config->alt_name.gmch_m, \
13256                           current_config->alt_name.gmch_n, \
13257                           current_config->alt_name.link_m, \
13258                           current_config->alt_name.link_n, \
13259                           pipe_config->name.tu, \
13260                           pipe_config->name.gmch_m, \
13261                           pipe_config->name.gmch_n, \
13262                           pipe_config->name.link_m, \
13263                           pipe_config->name.link_n); \
13264                 ret = false; \
13265         }
13266
13267 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13268         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13269                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13270                           "(expected %i, found %i)\n", \
13271                           current_config->name & (mask), \
13272                           pipe_config->name & (mask)); \
13273                 ret = false; \
13274         }
13275
13276 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13277         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13278                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13279                           "(expected %i, found %i)\n", \
13280                           current_config->name, \
13281                           pipe_config->name); \
13282                 ret = false; \
13283         }
13284
13285 #define PIPE_CONF_QUIRK(quirk)  \
13286         ((current_config->quirks | pipe_config->quirks) & (quirk))
13287
13288         PIPE_CONF_CHECK_I(cpu_transcoder);
13289
13290         PIPE_CONF_CHECK_I(has_pch_encoder);
13291         PIPE_CONF_CHECK_I(fdi_lanes);
13292         PIPE_CONF_CHECK_M_N(fdi_m_n);
13293
13294         PIPE_CONF_CHECK_I(lane_count);
13295         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13296
13297         if (INTEL_INFO(dev)->gen < 8) {
13298                 PIPE_CONF_CHECK_M_N(dp_m_n);
13299
13300                 if (current_config->has_drrs)
13301                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13302         } else
13303                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13304
13305         PIPE_CONF_CHECK_X(output_types);
13306
13307         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13308         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13309         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13310         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13311         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13312         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13313
13314         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13315         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13316         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13317         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13318         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13319         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13320
13321         PIPE_CONF_CHECK_I(pixel_multiplier);
13322         PIPE_CONF_CHECK_I(has_hdmi_sink);
13323         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
13324             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
13325                 PIPE_CONF_CHECK_I(limited_color_range);
13326         PIPE_CONF_CHECK_I(has_infoframe);
13327
13328         PIPE_CONF_CHECK_I(has_audio);
13329
13330         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13331                               DRM_MODE_FLAG_INTERLACE);
13332
13333         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13334                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13335                                       DRM_MODE_FLAG_PHSYNC);
13336                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13337                                       DRM_MODE_FLAG_NHSYNC);
13338                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13339                                       DRM_MODE_FLAG_PVSYNC);
13340                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13341                                       DRM_MODE_FLAG_NVSYNC);
13342         }
13343
13344         PIPE_CONF_CHECK_X(gmch_pfit.control);
13345         /* pfit ratios are autocomputed by the hw on gen4+ */
13346         if (INTEL_INFO(dev)->gen < 4)
13347                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13348         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13349
13350         if (!adjust) {
13351                 PIPE_CONF_CHECK_I(pipe_src_w);
13352                 PIPE_CONF_CHECK_I(pipe_src_h);
13353
13354                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13355                 if (current_config->pch_pfit.enabled) {
13356                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13357                         PIPE_CONF_CHECK_X(pch_pfit.size);
13358                 }
13359
13360                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13361         }
13362
13363         /* BDW+ don't expose a synchronous way to read the state */
13364         if (IS_HASWELL(dev))
13365                 PIPE_CONF_CHECK_I(ips_enabled);
13366
13367         PIPE_CONF_CHECK_I(double_wide);
13368
13369         PIPE_CONF_CHECK_P(shared_dpll);
13370         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13371         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13372         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13373         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13374         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13375         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13376         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13377         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13378         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13379
13380         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13381         PIPE_CONF_CHECK_X(dsi_pll.div);
13382
13383         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13384                 PIPE_CONF_CHECK_I(pipe_bpp);
13385
13386         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13387         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13388
13389 #undef PIPE_CONF_CHECK_X
13390 #undef PIPE_CONF_CHECK_I
13391 #undef PIPE_CONF_CHECK_P
13392 #undef PIPE_CONF_CHECK_FLAGS
13393 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13394 #undef PIPE_CONF_QUIRK
13395 #undef INTEL_ERR_OR_DBG_KMS
13396
13397         return ret;
13398 }
13399
13400 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13401                                            const struct intel_crtc_state *pipe_config)
13402 {
13403         if (pipe_config->has_pch_encoder) {
13404                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13405                                                             &pipe_config->fdi_m_n);
13406                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13407
13408                 /*
13409                  * FDI already provided one idea for the dotclock.
13410                  * Yell if the encoder disagrees.
13411                  */
13412                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13413                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13414                      fdi_dotclock, dotclock);
13415         }
13416 }
13417
13418 static void verify_wm_state(struct drm_crtc *crtc,
13419                             struct drm_crtc_state *new_state)
13420 {
13421         struct drm_device *dev = crtc->dev;
13422         struct drm_i915_private *dev_priv = to_i915(dev);
13423         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13424         struct skl_ddb_entry *hw_entry, *sw_entry;
13425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13426         const enum pipe pipe = intel_crtc->pipe;
13427         int plane;
13428
13429         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13430                 return;
13431
13432         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13433         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13434
13435         /* planes */
13436         for_each_plane(dev_priv, pipe, plane) {
13437                 hw_entry = &hw_ddb.plane[pipe][plane];
13438                 sw_entry = &sw_ddb->plane[pipe][plane];
13439
13440                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13441                         continue;
13442
13443                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13444                           "(expected (%u,%u), found (%u,%u))\n",
13445                           pipe_name(pipe), plane + 1,
13446                           sw_entry->start, sw_entry->end,
13447                           hw_entry->start, hw_entry->end);
13448         }
13449
13450         /*
13451          * cursor
13452          * If the cursor plane isn't active, we may not have updated it's ddb
13453          * allocation. In that case since the ddb allocation will be updated
13454          * once the plane becomes visible, we can skip this check
13455          */
13456         if (intel_crtc->cursor_addr) {
13457                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13458                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13459
13460                 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13461                         DRM_ERROR("mismatch in DDB state pipe %c cursor "
13462                                   "(expected (%u,%u), found (%u,%u))\n",
13463                                   pipe_name(pipe),
13464                                   sw_entry->start, sw_entry->end,
13465                                   hw_entry->start, hw_entry->end);
13466                 }
13467         }
13468 }
13469
13470 static void
13471 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13472 {
13473         struct drm_connector *connector;
13474
13475         drm_for_each_connector(connector, dev) {
13476                 struct drm_encoder *encoder = connector->encoder;
13477                 struct drm_connector_state *state = connector->state;
13478
13479                 if (state->crtc != crtc)
13480                         continue;
13481
13482                 intel_connector_verify_state(to_intel_connector(connector));
13483
13484                 I915_STATE_WARN(state->best_encoder != encoder,
13485                      "connector's atomic encoder doesn't match legacy encoder\n");
13486         }
13487 }
13488
13489 static void
13490 verify_encoder_state(struct drm_device *dev)
13491 {
13492         struct intel_encoder *encoder;
13493         struct intel_connector *connector;
13494
13495         for_each_intel_encoder(dev, encoder) {
13496                 bool enabled = false;
13497                 enum pipe pipe;
13498
13499                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13500                               encoder->base.base.id,
13501                               encoder->base.name);
13502
13503                 for_each_intel_connector(dev, connector) {
13504                         if (connector->base.state->best_encoder != &encoder->base)
13505                                 continue;
13506                         enabled = true;
13507
13508                         I915_STATE_WARN(connector->base.state->crtc !=
13509                                         encoder->base.crtc,
13510                              "connector's crtc doesn't match encoder crtc\n");
13511                 }
13512
13513                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13514                      "encoder's enabled state mismatch "
13515                      "(expected %i, found %i)\n",
13516                      !!encoder->base.crtc, enabled);
13517
13518                 if (!encoder->base.crtc) {
13519                         bool active;
13520
13521                         active = encoder->get_hw_state(encoder, &pipe);
13522                         I915_STATE_WARN(active,
13523                              "encoder detached but still enabled on pipe %c.\n",
13524                              pipe_name(pipe));
13525                 }
13526         }
13527 }
13528
13529 static void
13530 verify_crtc_state(struct drm_crtc *crtc,
13531                   struct drm_crtc_state *old_crtc_state,
13532                   struct drm_crtc_state *new_crtc_state)
13533 {
13534         struct drm_device *dev = crtc->dev;
13535         struct drm_i915_private *dev_priv = to_i915(dev);
13536         struct intel_encoder *encoder;
13537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13538         struct intel_crtc_state *pipe_config, *sw_config;
13539         struct drm_atomic_state *old_state;
13540         bool active;
13541
13542         old_state = old_crtc_state->state;
13543         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13544         pipe_config = to_intel_crtc_state(old_crtc_state);
13545         memset(pipe_config, 0, sizeof(*pipe_config));
13546         pipe_config->base.crtc = crtc;
13547         pipe_config->base.state = old_state;
13548
13549         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13550
13551         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13552
13553         /* hw state is inconsistent with the pipe quirk */
13554         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13555             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13556                 active = new_crtc_state->active;
13557
13558         I915_STATE_WARN(new_crtc_state->active != active,
13559              "crtc active state doesn't match with hw state "
13560              "(expected %i, found %i)\n", new_crtc_state->active, active);
13561
13562         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13563              "transitional active state does not match atomic hw state "
13564              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13565
13566         for_each_encoder_on_crtc(dev, crtc, encoder) {
13567                 enum pipe pipe;
13568
13569                 active = encoder->get_hw_state(encoder, &pipe);
13570                 I915_STATE_WARN(active != new_crtc_state->active,
13571                         "[ENCODER:%i] active %i with crtc active %i\n",
13572                         encoder->base.base.id, active, new_crtc_state->active);
13573
13574                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13575                                 "Encoder connected to wrong pipe %c\n",
13576                                 pipe_name(pipe));
13577
13578                 if (active) {
13579                         pipe_config->output_types |= 1 << encoder->type;
13580                         encoder->get_config(encoder, pipe_config);
13581                 }
13582         }
13583
13584         if (!new_crtc_state->active)
13585                 return;
13586
13587         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13588
13589         sw_config = to_intel_crtc_state(crtc->state);
13590         if (!intel_pipe_config_compare(dev, sw_config,
13591                                        pipe_config, false)) {
13592                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13593                 intel_dump_pipe_config(intel_crtc, pipe_config,
13594                                        "[hw state]");
13595                 intel_dump_pipe_config(intel_crtc, sw_config,
13596                                        "[sw state]");
13597         }
13598 }
13599
13600 static void
13601 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13602                          struct intel_shared_dpll *pll,
13603                          struct drm_crtc *crtc,
13604                          struct drm_crtc_state *new_state)
13605 {
13606         struct intel_dpll_hw_state dpll_hw_state;
13607         unsigned crtc_mask;
13608         bool active;
13609
13610         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13611
13612         DRM_DEBUG_KMS("%s\n", pll->name);
13613
13614         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13615
13616         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13617                 I915_STATE_WARN(!pll->on && pll->active_mask,
13618                      "pll in active use but not on in sw tracking\n");
13619                 I915_STATE_WARN(pll->on && !pll->active_mask,
13620                      "pll is on but not used by any active crtc\n");
13621                 I915_STATE_WARN(pll->on != active,
13622                      "pll on state mismatch (expected %i, found %i)\n",
13623                      pll->on, active);
13624         }
13625
13626         if (!crtc) {
13627                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13628                                 "more active pll users than references: %x vs %x\n",
13629                                 pll->active_mask, pll->config.crtc_mask);
13630
13631                 return;
13632         }
13633
13634         crtc_mask = 1 << drm_crtc_index(crtc);
13635
13636         if (new_state->active)
13637                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13638                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13639                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13640         else
13641                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13642                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13643                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13644
13645         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13646                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13647                         crtc_mask, pll->config.crtc_mask);
13648
13649         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13650                                           &dpll_hw_state,
13651                                           sizeof(dpll_hw_state)),
13652                         "pll hw state mismatch\n");
13653 }
13654
13655 static void
13656 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13657                          struct drm_crtc_state *old_crtc_state,
13658                          struct drm_crtc_state *new_crtc_state)
13659 {
13660         struct drm_i915_private *dev_priv = to_i915(dev);
13661         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13662         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13663
13664         if (new_state->shared_dpll)
13665                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13666
13667         if (old_state->shared_dpll &&
13668             old_state->shared_dpll != new_state->shared_dpll) {
13669                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13670                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13671
13672                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13673                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13674                                 pipe_name(drm_crtc_index(crtc)));
13675                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13676                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13677                                 pipe_name(drm_crtc_index(crtc)));
13678         }
13679 }
13680
13681 static void
13682 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13683                          struct drm_crtc_state *old_state,
13684                          struct drm_crtc_state *new_state)
13685 {
13686         if (!needs_modeset(new_state) &&
13687             !to_intel_crtc_state(new_state)->update_pipe)
13688                 return;
13689
13690         verify_wm_state(crtc, new_state);
13691         verify_connector_state(crtc->dev, crtc);
13692         verify_crtc_state(crtc, old_state, new_state);
13693         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13694 }
13695
13696 static void
13697 verify_disabled_dpll_state(struct drm_device *dev)
13698 {
13699         struct drm_i915_private *dev_priv = to_i915(dev);
13700         int i;
13701
13702         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13703                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13704 }
13705
13706 static void
13707 intel_modeset_verify_disabled(struct drm_device *dev)
13708 {
13709         verify_encoder_state(dev);
13710         verify_connector_state(dev, NULL);
13711         verify_disabled_dpll_state(dev);
13712 }
13713
13714 static void update_scanline_offset(struct intel_crtc *crtc)
13715 {
13716         struct drm_device *dev = crtc->base.dev;
13717
13718         /*
13719          * The scanline counter increments at the leading edge of hsync.
13720          *
13721          * On most platforms it starts counting from vtotal-1 on the
13722          * first active line. That means the scanline counter value is
13723          * always one less than what we would expect. Ie. just after
13724          * start of vblank, which also occurs at start of hsync (on the
13725          * last active line), the scanline counter will read vblank_start-1.
13726          *
13727          * On gen2 the scanline counter starts counting from 1 instead
13728          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13729          * to keep the value positive), instead of adding one.
13730          *
13731          * On HSW+ the behaviour of the scanline counter depends on the output
13732          * type. For DP ports it behaves like most other platforms, but on HDMI
13733          * there's an extra 1 line difference. So we need to add two instead of
13734          * one to the value.
13735          */
13736         if (IS_GEN2(dev)) {
13737                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13738                 int vtotal;
13739
13740                 vtotal = adjusted_mode->crtc_vtotal;
13741                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13742                         vtotal /= 2;
13743
13744                 crtc->scanline_offset = vtotal - 1;
13745         } else if (HAS_DDI(dev) &&
13746                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13747                 crtc->scanline_offset = 2;
13748         } else
13749                 crtc->scanline_offset = 1;
13750 }
13751
13752 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13753 {
13754         struct drm_device *dev = state->dev;
13755         struct drm_i915_private *dev_priv = to_i915(dev);
13756         struct intel_shared_dpll_config *shared_dpll = NULL;
13757         struct drm_crtc *crtc;
13758         struct drm_crtc_state *crtc_state;
13759         int i;
13760
13761         if (!dev_priv->display.crtc_compute_clock)
13762                 return;
13763
13764         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13765                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13766                 struct intel_shared_dpll *old_dpll =
13767                         to_intel_crtc_state(crtc->state)->shared_dpll;
13768
13769                 if (!needs_modeset(crtc_state))
13770                         continue;
13771
13772                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13773
13774                 if (!old_dpll)
13775                         continue;
13776
13777                 if (!shared_dpll)
13778                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13779
13780                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13781         }
13782 }
13783
13784 /*
13785  * This implements the workaround described in the "notes" section of the mode
13786  * set sequence documentation. When going from no pipes or single pipe to
13787  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13788  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13789  */
13790 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13791 {
13792         struct drm_crtc_state *crtc_state;
13793         struct intel_crtc *intel_crtc;
13794         struct drm_crtc *crtc;
13795         struct intel_crtc_state *first_crtc_state = NULL;
13796         struct intel_crtc_state *other_crtc_state = NULL;
13797         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13798         int i;
13799
13800         /* look at all crtc's that are going to be enabled in during modeset */
13801         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13802                 intel_crtc = to_intel_crtc(crtc);
13803
13804                 if (!crtc_state->active || !needs_modeset(crtc_state))
13805                         continue;
13806
13807                 if (first_crtc_state) {
13808                         other_crtc_state = to_intel_crtc_state(crtc_state);
13809                         break;
13810                 } else {
13811                         first_crtc_state = to_intel_crtc_state(crtc_state);
13812                         first_pipe = intel_crtc->pipe;
13813                 }
13814         }
13815
13816         /* No workaround needed? */
13817         if (!first_crtc_state)
13818                 return 0;
13819
13820         /* w/a possibly needed, check how many crtc's are already enabled. */
13821         for_each_intel_crtc(state->dev, intel_crtc) {
13822                 struct intel_crtc_state *pipe_config;
13823
13824                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13825                 if (IS_ERR(pipe_config))
13826                         return PTR_ERR(pipe_config);
13827
13828                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13829
13830                 if (!pipe_config->base.active ||
13831                     needs_modeset(&pipe_config->base))
13832                         continue;
13833
13834                 /* 2 or more enabled crtcs means no need for w/a */
13835                 if (enabled_pipe != INVALID_PIPE)
13836                         return 0;
13837
13838                 enabled_pipe = intel_crtc->pipe;
13839         }
13840
13841         if (enabled_pipe != INVALID_PIPE)
13842                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13843         else if (other_crtc_state)
13844                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13845
13846         return 0;
13847 }
13848
13849 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13850 {
13851         struct drm_crtc *crtc;
13852         struct drm_crtc_state *crtc_state;
13853         int ret = 0;
13854
13855         /* add all active pipes to the state */
13856         for_each_crtc(state->dev, crtc) {
13857                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13858                 if (IS_ERR(crtc_state))
13859                         return PTR_ERR(crtc_state);
13860
13861                 if (!crtc_state->active || needs_modeset(crtc_state))
13862                         continue;
13863
13864                 crtc_state->mode_changed = true;
13865
13866                 ret = drm_atomic_add_affected_connectors(state, crtc);
13867                 if (ret)
13868                         break;
13869
13870                 ret = drm_atomic_add_affected_planes(state, crtc);
13871                 if (ret)
13872                         break;
13873         }
13874
13875         return ret;
13876 }
13877
13878 static int intel_modeset_checks(struct drm_atomic_state *state)
13879 {
13880         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13881         struct drm_i915_private *dev_priv = to_i915(state->dev);
13882         struct drm_crtc *crtc;
13883         struct drm_crtc_state *crtc_state;
13884         int ret = 0, i;
13885
13886         if (!check_digital_port_conflicts(state)) {
13887                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13888                 return -EINVAL;
13889         }
13890
13891         intel_state->modeset = true;
13892         intel_state->active_crtcs = dev_priv->active_crtcs;
13893
13894         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13895                 if (crtc_state->active)
13896                         intel_state->active_crtcs |= 1 << i;
13897                 else
13898                         intel_state->active_crtcs &= ~(1 << i);
13899
13900                 if (crtc_state->active != crtc->state->active)
13901                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13902         }
13903
13904         /*
13905          * See if the config requires any additional preparation, e.g.
13906          * to adjust global state with pipes off.  We need to do this
13907          * here so we can get the modeset_pipe updated config for the new
13908          * mode set on this crtc.  For other crtcs we need to use the
13909          * adjusted_mode bits in the crtc directly.
13910          */
13911         if (dev_priv->display.modeset_calc_cdclk) {
13912                 if (!intel_state->cdclk_pll_vco)
13913                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13914                 if (!intel_state->cdclk_pll_vco)
13915                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13916
13917                 ret = dev_priv->display.modeset_calc_cdclk(state);
13918                 if (ret < 0)
13919                         return ret;
13920
13921                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13922                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13923                         ret = intel_modeset_all_pipes(state);
13924
13925                 if (ret < 0)
13926                         return ret;
13927
13928                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13929                               intel_state->cdclk, intel_state->dev_cdclk);
13930         } else
13931                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13932
13933         intel_modeset_clear_plls(state);
13934
13935         if (IS_HASWELL(dev_priv))
13936                 return haswell_mode_set_planes_workaround(state);
13937
13938         return 0;
13939 }
13940
13941 /*
13942  * Handle calculation of various watermark data at the end of the atomic check
13943  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13944  * handlers to ensure that all derived state has been updated.
13945  */
13946 static int calc_watermark_data(struct drm_atomic_state *state)
13947 {
13948         struct drm_device *dev = state->dev;
13949         struct drm_i915_private *dev_priv = to_i915(dev);
13950
13951         /* Is there platform-specific watermark information to calculate? */
13952         if (dev_priv->display.compute_global_watermarks)
13953                 return dev_priv->display.compute_global_watermarks(state);
13954
13955         return 0;
13956 }
13957
13958 /**
13959  * intel_atomic_check - validate state object
13960  * @dev: drm device
13961  * @state: state to validate
13962  */
13963 static int intel_atomic_check(struct drm_device *dev,
13964                               struct drm_atomic_state *state)
13965 {
13966         struct drm_i915_private *dev_priv = to_i915(dev);
13967         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13968         struct drm_crtc *crtc;
13969         struct drm_crtc_state *crtc_state;
13970         int ret, i;
13971         bool any_ms = false;
13972
13973         ret = drm_atomic_helper_check_modeset(dev, state);
13974         if (ret)
13975                 return ret;
13976
13977         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13978                 struct intel_crtc_state *pipe_config =
13979                         to_intel_crtc_state(crtc_state);
13980
13981                 /* Catch I915_MODE_FLAG_INHERITED */
13982                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13983                         crtc_state->mode_changed = true;
13984
13985                 if (!needs_modeset(crtc_state))
13986                         continue;
13987
13988                 if (!crtc_state->enable) {
13989                         any_ms = true;
13990                         continue;
13991                 }
13992
13993                 /* FIXME: For only active_changed we shouldn't need to do any
13994                  * state recomputation at all. */
13995
13996                 ret = drm_atomic_add_affected_connectors(state, crtc);
13997                 if (ret)
13998                         return ret;
13999
14000                 ret = intel_modeset_pipe_config(crtc, pipe_config);
14001                 if (ret) {
14002                         intel_dump_pipe_config(to_intel_crtc(crtc),
14003                                                pipe_config, "[failed]");
14004                         return ret;
14005                 }
14006
14007                 if (i915.fastboot &&
14008                     intel_pipe_config_compare(dev,
14009                                         to_intel_crtc_state(crtc->state),
14010                                         pipe_config, true)) {
14011                         crtc_state->mode_changed = false;
14012                         to_intel_crtc_state(crtc_state)->update_pipe = true;
14013                 }
14014
14015                 if (needs_modeset(crtc_state))
14016                         any_ms = true;
14017
14018                 ret = drm_atomic_add_affected_planes(state, crtc);
14019                 if (ret)
14020                         return ret;
14021
14022                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14023                                        needs_modeset(crtc_state) ?
14024                                        "[modeset]" : "[fastset]");
14025         }
14026
14027         if (any_ms) {
14028                 ret = intel_modeset_checks(state);
14029
14030                 if (ret)
14031                         return ret;
14032         } else
14033                 intel_state->cdclk = dev_priv->cdclk_freq;
14034
14035         ret = drm_atomic_helper_check_planes(dev, state);
14036         if (ret)
14037                 return ret;
14038
14039         intel_fbc_choose_crtc(dev_priv, state);
14040         return calc_watermark_data(state);
14041 }
14042
14043 static int intel_atomic_prepare_commit(struct drm_device *dev,
14044                                        struct drm_atomic_state *state,
14045                                        bool nonblock)
14046 {
14047         struct drm_i915_private *dev_priv = to_i915(dev);
14048         struct drm_plane_state *plane_state;
14049         struct drm_crtc_state *crtc_state;
14050         struct drm_plane *plane;
14051         struct drm_crtc *crtc;
14052         int i, ret;
14053
14054         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14055                 if (state->legacy_cursor_update)
14056                         continue;
14057
14058                 ret = intel_crtc_wait_for_pending_flips(crtc);
14059                 if (ret)
14060                         return ret;
14061
14062                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14063                         flush_workqueue(dev_priv->wq);
14064         }
14065
14066         ret = mutex_lock_interruptible(&dev->struct_mutex);
14067         if (ret)
14068                 return ret;
14069
14070         ret = drm_atomic_helper_prepare_planes(dev, state);
14071         mutex_unlock(&dev->struct_mutex);
14072
14073         if (!ret && !nonblock) {
14074                 for_each_plane_in_state(state, plane, plane_state, i) {
14075                         struct intel_plane_state *intel_plane_state =
14076                                 to_intel_plane_state(plane_state);
14077
14078                         if (!intel_plane_state->wait_req)
14079                                 continue;
14080
14081                         ret = i915_wait_request(intel_plane_state->wait_req,
14082                                                 I915_WAIT_INTERRUPTIBLE,
14083                                                 NULL, NULL);
14084                         if (ret) {
14085                                 /* Any hang should be swallowed by the wait */
14086                                 WARN_ON(ret == -EIO);
14087                                 mutex_lock(&dev->struct_mutex);
14088                                 drm_atomic_helper_cleanup_planes(dev, state);
14089                                 mutex_unlock(&dev->struct_mutex);
14090                                 break;
14091                         }
14092                 }
14093         }
14094
14095         return ret;
14096 }
14097
14098 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14099 {
14100         struct drm_device *dev = crtc->base.dev;
14101
14102         if (!dev->max_vblank_count)
14103                 return drm_accurate_vblank_count(&crtc->base);
14104
14105         return dev->driver->get_vblank_counter(dev, crtc->pipe);
14106 }
14107
14108 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14109                                           struct drm_i915_private *dev_priv,
14110                                           unsigned crtc_mask)
14111 {
14112         unsigned last_vblank_count[I915_MAX_PIPES];
14113         enum pipe pipe;
14114         int ret;
14115
14116         if (!crtc_mask)
14117                 return;
14118
14119         for_each_pipe(dev_priv, pipe) {
14120                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14121
14122                 if (!((1 << pipe) & crtc_mask))
14123                         continue;
14124
14125                 ret = drm_crtc_vblank_get(crtc);
14126                 if (WARN_ON(ret != 0)) {
14127                         crtc_mask &= ~(1 << pipe);
14128                         continue;
14129                 }
14130
14131                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14132         }
14133
14134         for_each_pipe(dev_priv, pipe) {
14135                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14136                 long lret;
14137
14138                 if (!((1 << pipe) & crtc_mask))
14139                         continue;
14140
14141                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14142                                 last_vblank_count[pipe] !=
14143                                         drm_crtc_vblank_count(crtc),
14144                                 msecs_to_jiffies(50));
14145
14146                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14147
14148                 drm_crtc_vblank_put(crtc);
14149         }
14150 }
14151
14152 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14153 {
14154         /* fb updated, need to unpin old fb */
14155         if (crtc_state->fb_changed)
14156                 return true;
14157
14158         /* wm changes, need vblank before final wm's */
14159         if (crtc_state->update_wm_post)
14160                 return true;
14161
14162         /*
14163          * cxsr is re-enabled after vblank.
14164          * This is already handled by crtc_state->update_wm_post,
14165          * but added for clarity.
14166          */
14167         if (crtc_state->disable_cxsr)
14168                 return true;
14169
14170         return false;
14171 }
14172
14173 static void intel_update_crtc(struct drm_crtc *crtc,
14174                               struct drm_atomic_state *state,
14175                               struct drm_crtc_state *old_crtc_state,
14176                               unsigned int *crtc_vblank_mask)
14177 {
14178         struct drm_device *dev = crtc->dev;
14179         struct drm_i915_private *dev_priv = to_i915(dev);
14180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14181         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14182         bool modeset = needs_modeset(crtc->state);
14183
14184         if (modeset) {
14185                 update_scanline_offset(intel_crtc);
14186                 dev_priv->display.crtc_enable(pipe_config, state);
14187         } else {
14188                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14189         }
14190
14191         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14192                 intel_fbc_enable(
14193                     intel_crtc, pipe_config,
14194                     to_intel_plane_state(crtc->primary->state));
14195         }
14196
14197         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14198
14199         if (needs_vblank_wait(pipe_config))
14200                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14201 }
14202
14203 static void intel_update_crtcs(struct drm_atomic_state *state,
14204                                unsigned int *crtc_vblank_mask)
14205 {
14206         struct drm_crtc *crtc;
14207         struct drm_crtc_state *old_crtc_state;
14208         int i;
14209
14210         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14211                 if (!crtc->state->active)
14212                         continue;
14213
14214                 intel_update_crtc(crtc, state, old_crtc_state,
14215                                   crtc_vblank_mask);
14216         }
14217 }
14218
14219 static void skl_update_crtcs(struct drm_atomic_state *state,
14220                              unsigned int *crtc_vblank_mask)
14221 {
14222         struct drm_device *dev = state->dev;
14223         struct drm_i915_private *dev_priv = to_i915(dev);
14224         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14225         struct drm_crtc *crtc;
14226         struct drm_crtc_state *old_crtc_state;
14227         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
14228         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
14229         unsigned int updated = 0;
14230         bool progress;
14231         enum pipe pipe;
14232
14233         /*
14234          * Whenever the number of active pipes changes, we need to make sure we
14235          * update the pipes in the right order so that their ddb allocations
14236          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14237          * cause pipe underruns and other bad stuff.
14238          */
14239         do {
14240                 int i;
14241                 progress = false;
14242
14243                 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14244                         bool vbl_wait = false;
14245                         unsigned int cmask = drm_crtc_mask(crtc);
14246                         pipe = to_intel_crtc(crtc)->pipe;
14247
14248                         if (updated & cmask || !crtc->state->active)
14249                                 continue;
14250                         if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb,
14251                                                         pipe))
14252                                 continue;
14253
14254                         updated |= cmask;
14255
14256                         /*
14257                          * If this is an already active pipe, it's DDB changed,
14258                          * and this isn't the last pipe that needs updating
14259                          * then we need to wait for a vblank to pass for the
14260                          * new ddb allocation to take effect.
14261                          */
14262                         if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) &&
14263                             !crtc->state->active_changed &&
14264                             intel_state->wm_results.dirty_pipes != updated)
14265                                 vbl_wait = true;
14266
14267                         intel_update_crtc(crtc, state, old_crtc_state,
14268                                           crtc_vblank_mask);
14269
14270                         if (vbl_wait)
14271                                 intel_wait_for_vblank(dev, pipe);
14272
14273                         progress = true;
14274                 }
14275         } while (progress);
14276 }
14277
14278 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14279 {
14280         struct drm_device *dev = state->dev;
14281         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14282         struct drm_i915_private *dev_priv = to_i915(dev);
14283         struct drm_crtc_state *old_crtc_state;
14284         struct drm_crtc *crtc;
14285         struct intel_crtc_state *intel_cstate;
14286         struct drm_plane *plane;
14287         struct drm_plane_state *plane_state;
14288         bool hw_check = intel_state->modeset;
14289         unsigned long put_domains[I915_MAX_PIPES] = {};
14290         unsigned crtc_vblank_mask = 0;
14291         int i, ret;
14292
14293         for_each_plane_in_state(state, plane, plane_state, i) {
14294                 struct intel_plane_state *intel_plane_state =
14295                         to_intel_plane_state(plane_state);
14296
14297                 if (!intel_plane_state->wait_req)
14298                         continue;
14299
14300                 ret = i915_wait_request(intel_plane_state->wait_req,
14301                                         0, NULL, NULL);
14302                 /* EIO should be eaten, and we can't get interrupted in the
14303                  * worker, and blocking commits have waited already. */
14304                 WARN_ON(ret);
14305         }
14306
14307         drm_atomic_helper_wait_for_dependencies(state);
14308
14309         if (intel_state->modeset) {
14310                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14311                        sizeof(intel_state->min_pixclk));
14312                 dev_priv->active_crtcs = intel_state->active_crtcs;
14313                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14314
14315                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14316         }
14317
14318         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14319                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14320
14321                 if (needs_modeset(crtc->state) ||
14322                     to_intel_crtc_state(crtc->state)->update_pipe) {
14323                         hw_check = true;
14324
14325                         put_domains[to_intel_crtc(crtc)->pipe] =
14326                                 modeset_get_crtc_power_domains(crtc,
14327                                         to_intel_crtc_state(crtc->state));
14328                 }
14329
14330                 if (!needs_modeset(crtc->state))
14331                         continue;
14332
14333                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14334
14335                 if (old_crtc_state->active) {
14336                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14337                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14338                         intel_crtc->active = false;
14339                         intel_fbc_disable(intel_crtc);
14340                         intel_disable_shared_dpll(intel_crtc);
14341
14342                         /*
14343                          * Underruns don't always raise
14344                          * interrupts, so check manually.
14345                          */
14346                         intel_check_cpu_fifo_underruns(dev_priv);
14347                         intel_check_pch_fifo_underruns(dev_priv);
14348
14349                         if (!crtc->state->active)
14350                                 intel_update_watermarks(crtc);
14351                 }
14352         }
14353
14354         /* Only after disabling all output pipelines that will be changed can we
14355          * update the the output configuration. */
14356         intel_modeset_update_crtc_state(state);
14357
14358         if (intel_state->modeset) {
14359                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14360
14361                 if (dev_priv->display.modeset_commit_cdclk &&
14362                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14363                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14364                         dev_priv->display.modeset_commit_cdclk(state);
14365
14366                 /*
14367                  * SKL workaround: bspec recommends we disable the SAGV when we
14368                  * have more then one pipe enabled
14369                  */
14370                 if (IS_SKYLAKE(dev_priv) && !skl_can_enable_sagv(state))
14371                         skl_disable_sagv(dev_priv);
14372
14373                 intel_modeset_verify_disabled(dev);
14374         }
14375
14376         /* Complete the events for pipes that have now been disabled */
14377         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14378                 bool modeset = needs_modeset(crtc->state);
14379
14380                 /* Complete events for now disable pipes here. */
14381                 if (modeset && !crtc->state->active && crtc->state->event) {
14382                         spin_lock_irq(&dev->event_lock);
14383                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14384                         spin_unlock_irq(&dev->event_lock);
14385
14386                         crtc->state->event = NULL;
14387                 }
14388         }
14389
14390         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14391         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14392
14393         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14394          * already, but still need the state for the delayed optimization. To
14395          * fix this:
14396          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14397          * - schedule that vblank worker _before_ calling hw_done
14398          * - at the start of commit_tail, cancel it _synchrously
14399          * - switch over to the vblank wait helper in the core after that since
14400          *   we don't need out special handling any more.
14401          */
14402         if (!state->legacy_cursor_update)
14403                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14404
14405         /*
14406          * Now that the vblank has passed, we can go ahead and program the
14407          * optimal watermarks on platforms that need two-step watermark
14408          * programming.
14409          *
14410          * TODO: Move this (and other cleanup) to an async worker eventually.
14411          */
14412         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14413                 intel_cstate = to_intel_crtc_state(crtc->state);
14414
14415                 if (dev_priv->display.optimize_watermarks)
14416                         dev_priv->display.optimize_watermarks(intel_cstate);
14417         }
14418
14419         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14420                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14421
14422                 if (put_domains[i])
14423                         modeset_put_power_domains(dev_priv, put_domains[i]);
14424
14425                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14426         }
14427
14428         if (IS_SKYLAKE(dev_priv) && intel_state->modeset &&
14429             skl_can_enable_sagv(state))
14430                 skl_enable_sagv(dev_priv);
14431
14432         drm_atomic_helper_commit_hw_done(state);
14433
14434         if (intel_state->modeset)
14435                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14436
14437         mutex_lock(&dev->struct_mutex);
14438         drm_atomic_helper_cleanup_planes(dev, state);
14439         mutex_unlock(&dev->struct_mutex);
14440
14441         drm_atomic_helper_commit_cleanup_done(state);
14442
14443         drm_atomic_state_free(state);
14444
14445         /* As one of the primary mmio accessors, KMS has a high likelihood
14446          * of triggering bugs in unclaimed access. After we finish
14447          * modesetting, see if an error has been flagged, and if so
14448          * enable debugging for the next modeset - and hope we catch
14449          * the culprit.
14450          *
14451          * XXX note that we assume display power is on at this point.
14452          * This might hold true now but we need to add pm helper to check
14453          * unclaimed only when the hardware is on, as atomic commits
14454          * can happen also when the device is completely off.
14455          */
14456         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14457 }
14458
14459 static void intel_atomic_commit_work(struct work_struct *work)
14460 {
14461         struct drm_atomic_state *state = container_of(work,
14462                                                       struct drm_atomic_state,
14463                                                       commit_work);
14464         intel_atomic_commit_tail(state);
14465 }
14466
14467 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14468 {
14469         struct drm_plane_state *old_plane_state;
14470         struct drm_plane *plane;
14471         int i;
14472
14473         for_each_plane_in_state(state, plane, old_plane_state, i)
14474                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14475                                   intel_fb_obj(plane->state->fb),
14476                                   to_intel_plane(plane)->frontbuffer_bit);
14477 }
14478
14479 /**
14480  * intel_atomic_commit - commit validated state object
14481  * @dev: DRM device
14482  * @state: the top-level driver state object
14483  * @nonblock: nonblocking commit
14484  *
14485  * This function commits a top-level state object that has been validated
14486  * with drm_atomic_helper_check().
14487  *
14488  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
14489  * nonblocking commits are only safe for pure plane updates. Everything else
14490  * should work though.
14491  *
14492  * RETURNS
14493  * Zero for success or -errno.
14494  */
14495 static int intel_atomic_commit(struct drm_device *dev,
14496                                struct drm_atomic_state *state,
14497                                bool nonblock)
14498 {
14499         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14500         struct drm_i915_private *dev_priv = to_i915(dev);
14501         int ret = 0;
14502
14503         if (intel_state->modeset && nonblock) {
14504                 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14505                 return -EINVAL;
14506         }
14507
14508         ret = drm_atomic_helper_setup_commit(state, nonblock);
14509         if (ret)
14510                 return ret;
14511
14512         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14513
14514         ret = intel_atomic_prepare_commit(dev, state, nonblock);
14515         if (ret) {
14516                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14517                 return ret;
14518         }
14519
14520         drm_atomic_helper_swap_state(state, true);
14521         dev_priv->wm.distrust_bios_wm = false;
14522         dev_priv->wm.skl_results = intel_state->wm_results;
14523         intel_shared_dpll_commit(state);
14524         intel_atomic_track_fbs(state);
14525
14526         if (nonblock)
14527                 queue_work(system_unbound_wq, &state->commit_work);
14528         else
14529                 intel_atomic_commit_tail(state);
14530
14531         return 0;
14532 }
14533
14534 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14535 {
14536         struct drm_device *dev = crtc->dev;
14537         struct drm_atomic_state *state;
14538         struct drm_crtc_state *crtc_state;
14539         int ret;
14540
14541         state = drm_atomic_state_alloc(dev);
14542         if (!state) {
14543                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14544                               crtc->base.id, crtc->name);
14545                 return;
14546         }
14547
14548         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14549
14550 retry:
14551         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14552         ret = PTR_ERR_OR_ZERO(crtc_state);
14553         if (!ret) {
14554                 if (!crtc_state->active)
14555                         goto out;
14556
14557                 crtc_state->mode_changed = true;
14558                 ret = drm_atomic_commit(state);
14559         }
14560
14561         if (ret == -EDEADLK) {
14562                 drm_atomic_state_clear(state);
14563                 drm_modeset_backoff(state->acquire_ctx);
14564                 goto retry;
14565         }
14566
14567         if (ret)
14568 out:
14569                 drm_atomic_state_free(state);
14570 }
14571
14572 /*
14573  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14574  *        drm_atomic_helper_legacy_gamma_set() directly.
14575  */
14576 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14577                                          u16 *red, u16 *green, u16 *blue,
14578                                          uint32_t size)
14579 {
14580         struct drm_device *dev = crtc->dev;
14581         struct drm_mode_config *config = &dev->mode_config;
14582         struct drm_crtc_state *state;
14583         int ret;
14584
14585         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14586         if (ret)
14587                 return ret;
14588
14589         /*
14590          * Make sure we update the legacy properties so this works when
14591          * atomic is not enabled.
14592          */
14593
14594         state = crtc->state;
14595
14596         drm_object_property_set_value(&crtc->base,
14597                                       config->degamma_lut_property,
14598                                       (state->degamma_lut) ?
14599                                       state->degamma_lut->base.id : 0);
14600
14601         drm_object_property_set_value(&crtc->base,
14602                                       config->ctm_property,
14603                                       (state->ctm) ?
14604                                       state->ctm->base.id : 0);
14605
14606         drm_object_property_set_value(&crtc->base,
14607                                       config->gamma_lut_property,
14608                                       (state->gamma_lut) ?
14609                                       state->gamma_lut->base.id : 0);
14610
14611         return 0;
14612 }
14613
14614 static const struct drm_crtc_funcs intel_crtc_funcs = {
14615         .gamma_set = intel_atomic_legacy_gamma_set,
14616         .set_config = drm_atomic_helper_set_config,
14617         .set_property = drm_atomic_helper_crtc_set_property,
14618         .destroy = intel_crtc_destroy,
14619         .page_flip = intel_crtc_page_flip,
14620         .atomic_duplicate_state = intel_crtc_duplicate_state,
14621         .atomic_destroy_state = intel_crtc_destroy_state,
14622 };
14623
14624 /**
14625  * intel_prepare_plane_fb - Prepare fb for usage on plane
14626  * @plane: drm plane to prepare for
14627  * @fb: framebuffer to prepare for presentation
14628  *
14629  * Prepares a framebuffer for usage on a display plane.  Generally this
14630  * involves pinning the underlying object and updating the frontbuffer tracking
14631  * bits.  Some older platforms need special physical address handling for
14632  * cursor planes.
14633  *
14634  * Must be called with struct_mutex held.
14635  *
14636  * Returns 0 on success, negative error code on failure.
14637  */
14638 int
14639 intel_prepare_plane_fb(struct drm_plane *plane,
14640                        struct drm_plane_state *new_state)
14641 {
14642         struct drm_device *dev = plane->dev;
14643         struct drm_framebuffer *fb = new_state->fb;
14644         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14645         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14646         struct reservation_object *resv;
14647         int ret = 0;
14648
14649         if (!obj && !old_obj)
14650                 return 0;
14651
14652         if (old_obj) {
14653                 struct drm_crtc_state *crtc_state =
14654                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14655
14656                 /* Big Hammer, we also need to ensure that any pending
14657                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14658                  * current scanout is retired before unpinning the old
14659                  * framebuffer. Note that we rely on userspace rendering
14660                  * into the buffer attached to the pipe they are waiting
14661                  * on. If not, userspace generates a GPU hang with IPEHR
14662                  * point to the MI_WAIT_FOR_EVENT.
14663                  *
14664                  * This should only fail upon a hung GPU, in which case we
14665                  * can safely continue.
14666                  */
14667                 if (needs_modeset(crtc_state))
14668                         ret = i915_gem_object_wait_rendering(old_obj, true);
14669                 if (ret) {
14670                         /* GPU hangs should have been swallowed by the wait */
14671                         WARN_ON(ret == -EIO);
14672                         return ret;
14673                 }
14674         }
14675
14676         if (!obj)
14677                 return 0;
14678
14679         /* For framebuffer backed by dmabuf, wait for fence */
14680         resv = i915_gem_object_get_dmabuf_resv(obj);
14681         if (resv) {
14682                 long lret;
14683
14684                 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14685                                                            MAX_SCHEDULE_TIMEOUT);
14686                 if (lret == -ERESTARTSYS)
14687                         return lret;
14688
14689                 WARN(lret < 0, "waiting returns %li\n", lret);
14690         }
14691
14692         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14693             INTEL_INFO(dev)->cursor_needs_physical) {
14694                 int align = IS_I830(dev) ? 16 * 1024 : 256;
14695                 ret = i915_gem_object_attach_phys(obj, align);
14696                 if (ret)
14697                         DRM_DEBUG_KMS("failed to attach phys object\n");
14698         } else {
14699                 struct i915_vma *vma;
14700
14701                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14702                 if (IS_ERR(vma))
14703                         ret = PTR_ERR(vma);
14704         }
14705
14706         if (ret == 0) {
14707                 to_intel_plane_state(new_state)->wait_req =
14708                         i915_gem_active_get(&obj->last_write,
14709                                             &obj->base.dev->struct_mutex);
14710         }
14711
14712         return ret;
14713 }
14714
14715 /**
14716  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14717  * @plane: drm plane to clean up for
14718  * @fb: old framebuffer that was on plane
14719  *
14720  * Cleans up a framebuffer that has just been removed from a plane.
14721  *
14722  * Must be called with struct_mutex held.
14723  */
14724 void
14725 intel_cleanup_plane_fb(struct drm_plane *plane,
14726                        struct drm_plane_state *old_state)
14727 {
14728         struct drm_device *dev = plane->dev;
14729         struct intel_plane_state *old_intel_state;
14730         struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14731         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14732         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14733
14734         old_intel_state = to_intel_plane_state(old_state);
14735
14736         if (!obj && !old_obj)
14737                 return;
14738
14739         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14740             !INTEL_INFO(dev)->cursor_needs_physical))
14741                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14742
14743         i915_gem_request_assign(&intel_state->wait_req, NULL);
14744         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14745 }
14746
14747 int
14748 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14749 {
14750         int max_scale;
14751         int crtc_clock, cdclk;
14752
14753         if (!intel_crtc || !crtc_state->base.enable)
14754                 return DRM_PLANE_HELPER_NO_SCALING;
14755
14756         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14757         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14758
14759         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14760                 return DRM_PLANE_HELPER_NO_SCALING;
14761
14762         /*
14763          * skl max scale is lower of:
14764          *    close to 3 but not 3, -1 is for that purpose
14765          *            or
14766          *    cdclk/crtc_clock
14767          */
14768         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14769
14770         return max_scale;
14771 }
14772
14773 static int
14774 intel_check_primary_plane(struct drm_plane *plane,
14775                           struct intel_crtc_state *crtc_state,
14776                           struct intel_plane_state *state)
14777 {
14778         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14779         struct drm_crtc *crtc = state->base.crtc;
14780         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14781         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14782         bool can_position = false;
14783         int ret;
14784
14785         if (INTEL_GEN(dev_priv) >= 9) {
14786                 /* use scaler when colorkey is not required */
14787                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14788                         min_scale = 1;
14789                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14790                 }
14791                 can_position = true;
14792         }
14793
14794         ret = drm_plane_helper_check_state(&state->base,
14795                                            &state->clip,
14796                                            min_scale, max_scale,
14797                                            can_position, true);
14798         if (ret)
14799                 return ret;
14800
14801         if (!state->base.fb)
14802                 return 0;
14803
14804         if (INTEL_GEN(dev_priv) >= 9) {
14805                 ret = skl_check_plane_surface(state);
14806                 if (ret)
14807                         return ret;
14808         }
14809
14810         return 0;
14811 }
14812
14813 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14814                                     struct drm_crtc_state *old_crtc_state)
14815 {
14816         struct drm_device *dev = crtc->dev;
14817         struct drm_i915_private *dev_priv = to_i915(dev);
14818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14819         struct intel_crtc_state *old_intel_state =
14820                 to_intel_crtc_state(old_crtc_state);
14821         bool modeset = needs_modeset(crtc->state);
14822         enum pipe pipe = intel_crtc->pipe;
14823
14824         /* Perform vblank evasion around commit operation */
14825         intel_pipe_update_start(intel_crtc);
14826
14827         if (modeset)
14828                 return;
14829
14830         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14831                 intel_color_set_csc(crtc->state);
14832                 intel_color_load_luts(crtc->state);
14833         }
14834
14835         if (to_intel_crtc_state(crtc->state)->update_pipe)
14836                 intel_update_pipe_config(intel_crtc, old_intel_state);
14837         else if (INTEL_GEN(dev_priv) >= 9) {
14838                 skl_detach_scalers(intel_crtc);
14839
14840                 I915_WRITE(PIPE_WM_LINETIME(pipe),
14841                            dev_priv->wm.skl_hw.wm_linetime[pipe]);
14842         }
14843 }
14844
14845 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14846                                      struct drm_crtc_state *old_crtc_state)
14847 {
14848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14849
14850         intel_pipe_update_end(intel_crtc, NULL);
14851 }
14852
14853 /**
14854  * intel_plane_destroy - destroy a plane
14855  * @plane: plane to destroy
14856  *
14857  * Common destruction function for all types of planes (primary, cursor,
14858  * sprite).
14859  */
14860 void intel_plane_destroy(struct drm_plane *plane)
14861 {
14862         if (!plane)
14863                 return;
14864
14865         drm_plane_cleanup(plane);
14866         kfree(to_intel_plane(plane));
14867 }
14868
14869 const struct drm_plane_funcs intel_plane_funcs = {
14870         .update_plane = drm_atomic_helper_update_plane,
14871         .disable_plane = drm_atomic_helper_disable_plane,
14872         .destroy = intel_plane_destroy,
14873         .set_property = drm_atomic_helper_plane_set_property,
14874         .atomic_get_property = intel_plane_atomic_get_property,
14875         .atomic_set_property = intel_plane_atomic_set_property,
14876         .atomic_duplicate_state = intel_plane_duplicate_state,
14877         .atomic_destroy_state = intel_plane_destroy_state,
14878
14879 };
14880
14881 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14882                                                     int pipe)
14883 {
14884         struct intel_plane *primary = NULL;
14885         struct intel_plane_state *state = NULL;
14886         const uint32_t *intel_primary_formats;
14887         unsigned int num_formats;
14888         int ret;
14889
14890         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14891         if (!primary)
14892                 goto fail;
14893
14894         state = intel_create_plane_state(&primary->base);
14895         if (!state)
14896                 goto fail;
14897         primary->base.state = &state->base;
14898
14899         primary->can_scale = false;
14900         primary->max_downscale = 1;
14901         if (INTEL_INFO(dev)->gen >= 9) {
14902                 primary->can_scale = true;
14903                 state->scaler_id = -1;
14904         }
14905         primary->pipe = pipe;
14906         primary->plane = pipe;
14907         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14908         primary->check_plane = intel_check_primary_plane;
14909         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14910                 primary->plane = !pipe;
14911
14912         if (INTEL_INFO(dev)->gen >= 9) {
14913                 intel_primary_formats = skl_primary_formats;
14914                 num_formats = ARRAY_SIZE(skl_primary_formats);
14915
14916                 primary->update_plane = skylake_update_primary_plane;
14917                 primary->disable_plane = skylake_disable_primary_plane;
14918         } else if (HAS_PCH_SPLIT(dev)) {
14919                 intel_primary_formats = i965_primary_formats;
14920                 num_formats = ARRAY_SIZE(i965_primary_formats);
14921
14922                 primary->update_plane = ironlake_update_primary_plane;
14923                 primary->disable_plane = i9xx_disable_primary_plane;
14924         } else if (INTEL_INFO(dev)->gen >= 4) {
14925                 intel_primary_formats = i965_primary_formats;
14926                 num_formats = ARRAY_SIZE(i965_primary_formats);
14927
14928                 primary->update_plane = i9xx_update_primary_plane;
14929                 primary->disable_plane = i9xx_disable_primary_plane;
14930         } else {
14931                 intel_primary_formats = i8xx_primary_formats;
14932                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14933
14934                 primary->update_plane = i9xx_update_primary_plane;
14935                 primary->disable_plane = i9xx_disable_primary_plane;
14936         }
14937
14938         if (INTEL_INFO(dev)->gen >= 9)
14939                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14940                                                &intel_plane_funcs,
14941                                                intel_primary_formats, num_formats,
14942                                                DRM_PLANE_TYPE_PRIMARY,
14943                                                "plane 1%c", pipe_name(pipe));
14944         else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14945                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14946                                                &intel_plane_funcs,
14947                                                intel_primary_formats, num_formats,
14948                                                DRM_PLANE_TYPE_PRIMARY,
14949                                                "primary %c", pipe_name(pipe));
14950         else
14951                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14952                                                &intel_plane_funcs,
14953                                                intel_primary_formats, num_formats,
14954                                                DRM_PLANE_TYPE_PRIMARY,
14955                                                "plane %c", plane_name(primary->plane));
14956         if (ret)
14957                 goto fail;
14958
14959         if (INTEL_INFO(dev)->gen >= 4)
14960                 intel_create_rotation_property(dev, primary);
14961
14962         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14963
14964         return &primary->base;
14965
14966 fail:
14967         kfree(state);
14968         kfree(primary);
14969
14970         return NULL;
14971 }
14972
14973 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14974 {
14975         if (!dev->mode_config.rotation_property) {
14976                 unsigned long flags = DRM_ROTATE_0 |
14977                         DRM_ROTATE_180;
14978
14979                 if (INTEL_INFO(dev)->gen >= 9)
14980                         flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
14981
14982                 dev->mode_config.rotation_property =
14983                         drm_mode_create_rotation_property(dev, flags);
14984         }
14985         if (dev->mode_config.rotation_property)
14986                 drm_object_attach_property(&plane->base.base,
14987                                 dev->mode_config.rotation_property,
14988                                 plane->base.state->rotation);
14989 }
14990
14991 static int
14992 intel_check_cursor_plane(struct drm_plane *plane,
14993                          struct intel_crtc_state *crtc_state,
14994                          struct intel_plane_state *state)
14995 {
14996         struct drm_framebuffer *fb = state->base.fb;
14997         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14998         enum pipe pipe = to_intel_plane(plane)->pipe;
14999         unsigned stride;
15000         int ret;
15001
15002         ret = drm_plane_helper_check_state(&state->base,
15003                                            &state->clip,
15004                                            DRM_PLANE_HELPER_NO_SCALING,
15005                                            DRM_PLANE_HELPER_NO_SCALING,
15006                                            true, true);
15007         if (ret)
15008                 return ret;
15009
15010         /* if we want to turn off the cursor ignore width and height */
15011         if (!obj)
15012                 return 0;
15013
15014         /* Check for which cursor types we support */
15015         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
15016                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15017                           state->base.crtc_w, state->base.crtc_h);
15018                 return -EINVAL;
15019         }
15020
15021         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15022         if (obj->base.size < stride * state->base.crtc_h) {
15023                 DRM_DEBUG_KMS("buffer is too small\n");
15024                 return -ENOMEM;
15025         }
15026
15027         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
15028                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15029                 return -EINVAL;
15030         }
15031
15032         /*
15033          * There's something wrong with the cursor on CHV pipe C.
15034          * If it straddles the left edge of the screen then
15035          * moving it away from the edge or disabling it often
15036          * results in a pipe underrun, and often that can lead to
15037          * dead pipe (constant underrun reported, and it scans
15038          * out just a solid color). To recover from that, the
15039          * display power well must be turned off and on again.
15040          * Refuse the put the cursor into that compromised position.
15041          */
15042         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
15043             state->base.visible && state->base.crtc_x < 0) {
15044                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15045                 return -EINVAL;
15046         }
15047
15048         return 0;
15049 }
15050
15051 static void
15052 intel_disable_cursor_plane(struct drm_plane *plane,
15053                            struct drm_crtc *crtc)
15054 {
15055         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15056
15057         intel_crtc->cursor_addr = 0;
15058         intel_crtc_update_cursor(crtc, NULL);
15059 }
15060
15061 static void
15062 intel_update_cursor_plane(struct drm_plane *plane,
15063                           const struct intel_crtc_state *crtc_state,
15064                           const struct intel_plane_state *state)
15065 {
15066         struct drm_crtc *crtc = crtc_state->base.crtc;
15067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15068         struct drm_device *dev = plane->dev;
15069         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15070         uint32_t addr;
15071
15072         if (!obj)
15073                 addr = 0;
15074         else if (!INTEL_INFO(dev)->cursor_needs_physical)
15075                 addr = i915_gem_object_ggtt_offset(obj, NULL);
15076         else
15077                 addr = obj->phys_handle->busaddr;
15078
15079         intel_crtc->cursor_addr = addr;
15080         intel_crtc_update_cursor(crtc, state);
15081 }
15082
15083 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
15084                                                    int pipe)
15085 {
15086         struct intel_plane *cursor = NULL;
15087         struct intel_plane_state *state = NULL;
15088         int ret;
15089
15090         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15091         if (!cursor)
15092                 goto fail;
15093
15094         state = intel_create_plane_state(&cursor->base);
15095         if (!state)
15096                 goto fail;
15097         cursor->base.state = &state->base;
15098
15099         cursor->can_scale = false;
15100         cursor->max_downscale = 1;
15101         cursor->pipe = pipe;
15102         cursor->plane = pipe;
15103         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15104         cursor->check_plane = intel_check_cursor_plane;
15105         cursor->update_plane = intel_update_cursor_plane;
15106         cursor->disable_plane = intel_disable_cursor_plane;
15107
15108         ret = drm_universal_plane_init(dev, &cursor->base, 0,
15109                                        &intel_plane_funcs,
15110                                        intel_cursor_formats,
15111                                        ARRAY_SIZE(intel_cursor_formats),
15112                                        DRM_PLANE_TYPE_CURSOR,
15113                                        "cursor %c", pipe_name(pipe));
15114         if (ret)
15115                 goto fail;
15116
15117         if (INTEL_INFO(dev)->gen >= 4) {
15118                 if (!dev->mode_config.rotation_property)
15119                         dev->mode_config.rotation_property =
15120                                 drm_mode_create_rotation_property(dev,
15121                                                         DRM_ROTATE_0 |
15122                                                         DRM_ROTATE_180);
15123                 if (dev->mode_config.rotation_property)
15124                         drm_object_attach_property(&cursor->base.base,
15125                                 dev->mode_config.rotation_property,
15126                                 state->base.rotation);
15127         }
15128
15129         if (INTEL_INFO(dev)->gen >=9)
15130                 state->scaler_id = -1;
15131
15132         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15133
15134         return &cursor->base;
15135
15136 fail:
15137         kfree(state);
15138         kfree(cursor);
15139
15140         return NULL;
15141 }
15142
15143 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
15144         struct intel_crtc_state *crtc_state)
15145 {
15146         int i;
15147         struct intel_scaler *intel_scaler;
15148         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
15149
15150         for (i = 0; i < intel_crtc->num_scalers; i++) {
15151                 intel_scaler = &scaler_state->scalers[i];
15152                 intel_scaler->in_use = 0;
15153                 intel_scaler->mode = PS_SCALER_MODE_DYN;
15154         }
15155
15156         scaler_state->scaler_id = -1;
15157 }
15158
15159 static void intel_crtc_init(struct drm_device *dev, int pipe)
15160 {
15161         struct drm_i915_private *dev_priv = to_i915(dev);
15162         struct intel_crtc *intel_crtc;
15163         struct intel_crtc_state *crtc_state = NULL;
15164         struct drm_plane *primary = NULL;
15165         struct drm_plane *cursor = NULL;
15166         int ret;
15167
15168         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15169         if (intel_crtc == NULL)
15170                 return;
15171
15172         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15173         if (!crtc_state)
15174                 goto fail;
15175         intel_crtc->config = crtc_state;
15176         intel_crtc->base.state = &crtc_state->base;
15177         crtc_state->base.crtc = &intel_crtc->base;
15178
15179         /* initialize shared scalers */
15180         if (INTEL_INFO(dev)->gen >= 9) {
15181                 if (pipe == PIPE_C)
15182                         intel_crtc->num_scalers = 1;
15183                 else
15184                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
15185
15186                 skl_init_scalers(dev, intel_crtc, crtc_state);
15187         }
15188
15189         primary = intel_primary_plane_create(dev, pipe);
15190         if (!primary)
15191                 goto fail;
15192
15193         cursor = intel_cursor_plane_create(dev, pipe);
15194         if (!cursor)
15195                 goto fail;
15196
15197         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
15198                                         cursor, &intel_crtc_funcs,
15199                                         "pipe %c", pipe_name(pipe));
15200         if (ret)
15201                 goto fail;
15202
15203         /*
15204          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
15205          * is hooked to pipe B. Hence we want plane A feeding pipe B.
15206          */
15207         intel_crtc->pipe = pipe;
15208         intel_crtc->plane = pipe;
15209         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
15210                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
15211                 intel_crtc->plane = !pipe;
15212         }
15213
15214         intel_crtc->cursor_base = ~0;
15215         intel_crtc->cursor_cntl = ~0;
15216         intel_crtc->cursor_size = ~0;
15217
15218         intel_crtc->wm.cxsr_allowed = true;
15219
15220         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15221                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15222         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15223         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15224
15225         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15226
15227         intel_color_init(&intel_crtc->base);
15228
15229         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15230         return;
15231
15232 fail:
15233         intel_plane_destroy(primary);
15234         intel_plane_destroy(cursor);
15235         kfree(crtc_state);
15236         kfree(intel_crtc);
15237 }
15238
15239 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15240 {
15241         struct drm_encoder *encoder = connector->base.encoder;
15242         struct drm_device *dev = connector->base.dev;
15243
15244         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15245
15246         if (!encoder || WARN_ON(!encoder->crtc))
15247                 return INVALID_PIPE;
15248
15249         return to_intel_crtc(encoder->crtc)->pipe;
15250 }
15251
15252 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15253                                 struct drm_file *file)
15254 {
15255         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15256         struct drm_crtc *drmmode_crtc;
15257         struct intel_crtc *crtc;
15258
15259         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15260         if (!drmmode_crtc)
15261                 return -ENOENT;
15262
15263         crtc = to_intel_crtc(drmmode_crtc);
15264         pipe_from_crtc_id->pipe = crtc->pipe;
15265
15266         return 0;
15267 }
15268
15269 static int intel_encoder_clones(struct intel_encoder *encoder)
15270 {
15271         struct drm_device *dev = encoder->base.dev;
15272         struct intel_encoder *source_encoder;
15273         int index_mask = 0;
15274         int entry = 0;
15275
15276         for_each_intel_encoder(dev, source_encoder) {
15277                 if (encoders_cloneable(encoder, source_encoder))
15278                         index_mask |= (1 << entry);
15279
15280                 entry++;
15281         }
15282
15283         return index_mask;
15284 }
15285
15286 static bool has_edp_a(struct drm_device *dev)
15287 {
15288         struct drm_i915_private *dev_priv = to_i915(dev);
15289
15290         if (!IS_MOBILE(dev))
15291                 return false;
15292
15293         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15294                 return false;
15295
15296         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15297                 return false;
15298
15299         return true;
15300 }
15301
15302 static bool intel_crt_present(struct drm_device *dev)
15303 {
15304         struct drm_i915_private *dev_priv = to_i915(dev);
15305
15306         if (INTEL_INFO(dev)->gen >= 9)
15307                 return false;
15308
15309         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
15310                 return false;
15311
15312         if (IS_CHERRYVIEW(dev))
15313                 return false;
15314
15315         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15316                 return false;
15317
15318         /* DDI E can't be used if DDI A requires 4 lanes */
15319         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15320                 return false;
15321
15322         if (!dev_priv->vbt.int_crt_support)
15323                 return false;
15324
15325         return true;
15326 }
15327
15328 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15329 {
15330         int pps_num;
15331         int pps_idx;
15332
15333         if (HAS_DDI(dev_priv))
15334                 return;
15335         /*
15336          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15337          * everywhere where registers can be write protected.
15338          */
15339         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15340                 pps_num = 2;
15341         else
15342                 pps_num = 1;
15343
15344         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15345                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15346
15347                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15348                 I915_WRITE(PP_CONTROL(pps_idx), val);
15349         }
15350 }
15351
15352 static void intel_pps_init(struct drm_i915_private *dev_priv)
15353 {
15354         if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15355                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15356         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15357                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15358         else
15359                 dev_priv->pps_mmio_base = PPS_BASE;
15360
15361         intel_pps_unlock_regs_wa(dev_priv);
15362 }
15363
15364 static void intel_setup_outputs(struct drm_device *dev)
15365 {
15366         struct drm_i915_private *dev_priv = to_i915(dev);
15367         struct intel_encoder *encoder;
15368         bool dpd_is_edp = false;
15369
15370         intel_pps_init(dev_priv);
15371
15372         /*
15373          * intel_edp_init_connector() depends on this completing first, to
15374          * prevent the registeration of both eDP and LVDS and the incorrect
15375          * sharing of the PPS.
15376          */
15377         intel_lvds_init(dev);
15378
15379         if (intel_crt_present(dev))
15380                 intel_crt_init(dev);
15381
15382         if (IS_BROXTON(dev)) {
15383                 /*
15384                  * FIXME: Broxton doesn't support port detection via the
15385                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15386                  * detect the ports.
15387                  */
15388                 intel_ddi_init(dev, PORT_A);
15389                 intel_ddi_init(dev, PORT_B);
15390                 intel_ddi_init(dev, PORT_C);
15391
15392                 intel_dsi_init(dev);
15393         } else if (HAS_DDI(dev)) {
15394                 int found;
15395
15396                 /*
15397                  * Haswell uses DDI functions to detect digital outputs.
15398                  * On SKL pre-D0 the strap isn't connected, so we assume
15399                  * it's there.
15400                  */
15401                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15402                 /* WaIgnoreDDIAStrap: skl */
15403                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15404                         intel_ddi_init(dev, PORT_A);
15405
15406                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15407                  * register */
15408                 found = I915_READ(SFUSE_STRAP);
15409
15410                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15411                         intel_ddi_init(dev, PORT_B);
15412                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15413                         intel_ddi_init(dev, PORT_C);
15414                 if (found & SFUSE_STRAP_DDID_DETECTED)
15415                         intel_ddi_init(dev, PORT_D);
15416                 /*
15417                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15418                  */
15419                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
15420                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15421                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15422                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15423                         intel_ddi_init(dev, PORT_E);
15424
15425         } else if (HAS_PCH_SPLIT(dev)) {
15426                 int found;
15427                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15428
15429                 if (has_edp_a(dev))
15430                         intel_dp_init(dev, DP_A, PORT_A);
15431
15432                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15433                         /* PCH SDVOB multiplex with HDMIB */
15434                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15435                         if (!found)
15436                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15437                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15438                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
15439                 }
15440
15441                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15442                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15443
15444                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15445                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15446
15447                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15448                         intel_dp_init(dev, PCH_DP_C, PORT_C);
15449
15450                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15451                         intel_dp_init(dev, PCH_DP_D, PORT_D);
15452         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15453                 bool has_edp, has_port;
15454
15455                 /*
15456                  * The DP_DETECTED bit is the latched state of the DDC
15457                  * SDA pin at boot. However since eDP doesn't require DDC
15458                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15459                  * eDP ports may have been muxed to an alternate function.
15460                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15461                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15462                  * detect eDP ports.
15463                  *
15464                  * Sadly the straps seem to be missing sometimes even for HDMI
15465                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15466                  * and VBT for the presence of the port. Additionally we can't
15467                  * trust the port type the VBT declares as we've seen at least
15468                  * HDMI ports that the VBT claim are DP or eDP.
15469                  */
15470                 has_edp = intel_dp_is_edp(dev, PORT_B);
15471                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15472                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15473                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15474                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15475                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15476
15477                 has_edp = intel_dp_is_edp(dev, PORT_C);
15478                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15479                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15480                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15481                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15482                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15483
15484                 if (IS_CHERRYVIEW(dev)) {
15485                         /*
15486                          * eDP not supported on port D,
15487                          * so no need to worry about it
15488                          */
15489                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15490                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15491                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
15492                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15493                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15494                 }
15495
15496                 intel_dsi_init(dev);
15497         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15498                 bool found = false;
15499
15500                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15501                         DRM_DEBUG_KMS("probing SDVOB\n");
15502                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15503                         if (!found && IS_G4X(dev)) {
15504                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15505                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15506                         }
15507
15508                         if (!found && IS_G4X(dev))
15509                                 intel_dp_init(dev, DP_B, PORT_B);
15510                 }
15511
15512                 /* Before G4X SDVOC doesn't have its own detect register */
15513
15514                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15515                         DRM_DEBUG_KMS("probing SDVOC\n");
15516                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15517                 }
15518
15519                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15520
15521                         if (IS_G4X(dev)) {
15522                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15523                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15524                         }
15525                         if (IS_G4X(dev))
15526                                 intel_dp_init(dev, DP_C, PORT_C);
15527                 }
15528
15529                 if (IS_G4X(dev) &&
15530                     (I915_READ(DP_D) & DP_DETECTED))
15531                         intel_dp_init(dev, DP_D, PORT_D);
15532         } else if (IS_GEN2(dev))
15533                 intel_dvo_init(dev);
15534
15535         if (SUPPORTS_TV(dev))
15536                 intel_tv_init(dev);
15537
15538         intel_psr_init(dev);
15539
15540         for_each_intel_encoder(dev, encoder) {
15541                 encoder->base.possible_crtcs = encoder->crtc_mask;
15542                 encoder->base.possible_clones =
15543                         intel_encoder_clones(encoder);
15544         }
15545
15546         intel_init_pch_refclk(dev);
15547
15548         drm_helper_move_panel_connectors_to_head(dev);
15549 }
15550
15551 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15552 {
15553         struct drm_device *dev = fb->dev;
15554         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15555
15556         drm_framebuffer_cleanup(fb);
15557         mutex_lock(&dev->struct_mutex);
15558         WARN_ON(!intel_fb->obj->framebuffer_references--);
15559         i915_gem_object_put(intel_fb->obj);
15560         mutex_unlock(&dev->struct_mutex);
15561         kfree(intel_fb);
15562 }
15563
15564 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15565                                                 struct drm_file *file,
15566                                                 unsigned int *handle)
15567 {
15568         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15569         struct drm_i915_gem_object *obj = intel_fb->obj;
15570
15571         if (obj->userptr.mm) {
15572                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15573                 return -EINVAL;
15574         }
15575
15576         return drm_gem_handle_create(file, &obj->base, handle);
15577 }
15578
15579 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15580                                         struct drm_file *file,
15581                                         unsigned flags, unsigned color,
15582                                         struct drm_clip_rect *clips,
15583                                         unsigned num_clips)
15584 {
15585         struct drm_device *dev = fb->dev;
15586         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15587         struct drm_i915_gem_object *obj = intel_fb->obj;
15588
15589         mutex_lock(&dev->struct_mutex);
15590         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15591         mutex_unlock(&dev->struct_mutex);
15592
15593         return 0;
15594 }
15595
15596 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15597         .destroy = intel_user_framebuffer_destroy,
15598         .create_handle = intel_user_framebuffer_create_handle,
15599         .dirty = intel_user_framebuffer_dirty,
15600 };
15601
15602 static
15603 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15604                          uint32_t pixel_format)
15605 {
15606         u32 gen = INTEL_INFO(dev)->gen;
15607
15608         if (gen >= 9) {
15609                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15610
15611                 /* "The stride in bytes must not exceed the of the size of 8K
15612                  *  pixels and 32K bytes."
15613                  */
15614                 return min(8192 * cpp, 32768);
15615         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15616                 return 32*1024;
15617         } else if (gen >= 4) {
15618                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15619                         return 16*1024;
15620                 else
15621                         return 32*1024;
15622         } else if (gen >= 3) {
15623                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15624                         return 8*1024;
15625                 else
15626                         return 16*1024;
15627         } else {
15628                 /* XXX DSPC is limited to 4k tiled */
15629                 return 8*1024;
15630         }
15631 }
15632
15633 static int intel_framebuffer_init(struct drm_device *dev,
15634                                   struct intel_framebuffer *intel_fb,
15635                                   struct drm_mode_fb_cmd2 *mode_cmd,
15636                                   struct drm_i915_gem_object *obj)
15637 {
15638         struct drm_i915_private *dev_priv = to_i915(dev);
15639         unsigned int tiling = i915_gem_object_get_tiling(obj);
15640         int ret;
15641         u32 pitch_limit, stride_alignment;
15642         char *format_name;
15643
15644         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15645
15646         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15647                 /*
15648                  * If there's a fence, enforce that
15649                  * the fb modifier and tiling mode match.
15650                  */
15651                 if (tiling != I915_TILING_NONE &&
15652                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15653                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15654                         return -EINVAL;
15655                 }
15656         } else {
15657                 if (tiling == I915_TILING_X) {
15658                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15659                 } else if (tiling == I915_TILING_Y) {
15660                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15661                         return -EINVAL;
15662                 }
15663         }
15664
15665         /* Passed in modifier sanity checking. */
15666         switch (mode_cmd->modifier[0]) {
15667         case I915_FORMAT_MOD_Y_TILED:
15668         case I915_FORMAT_MOD_Yf_TILED:
15669                 if (INTEL_INFO(dev)->gen < 9) {
15670                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15671                                   mode_cmd->modifier[0]);
15672                         return -EINVAL;
15673                 }
15674         case DRM_FORMAT_MOD_NONE:
15675         case I915_FORMAT_MOD_X_TILED:
15676                 break;
15677         default:
15678                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15679                           mode_cmd->modifier[0]);
15680                 return -EINVAL;
15681         }
15682
15683         /*
15684          * gen2/3 display engine uses the fence if present,
15685          * so the tiling mode must match the fb modifier exactly.
15686          */
15687         if (INTEL_INFO(dev_priv)->gen < 4 &&
15688             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15689                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15690                 return -EINVAL;
15691         }
15692
15693         stride_alignment = intel_fb_stride_alignment(dev_priv,
15694                                                      mode_cmd->modifier[0],
15695                                                      mode_cmd->pixel_format);
15696         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15697                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15698                           mode_cmd->pitches[0], stride_alignment);
15699                 return -EINVAL;
15700         }
15701
15702         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15703                                            mode_cmd->pixel_format);
15704         if (mode_cmd->pitches[0] > pitch_limit) {
15705                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15706                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15707                           "tiled" : "linear",
15708                           mode_cmd->pitches[0], pitch_limit);
15709                 return -EINVAL;
15710         }
15711
15712         /*
15713          * If there's a fence, enforce that
15714          * the fb pitch and fence stride match.
15715          */
15716         if (tiling != I915_TILING_NONE &&
15717             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15718                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15719                           mode_cmd->pitches[0],
15720                           i915_gem_object_get_stride(obj));
15721                 return -EINVAL;
15722         }
15723
15724         /* Reject formats not supported by any plane early. */
15725         switch (mode_cmd->pixel_format) {
15726         case DRM_FORMAT_C8:
15727         case DRM_FORMAT_RGB565:
15728         case DRM_FORMAT_XRGB8888:
15729         case DRM_FORMAT_ARGB8888:
15730                 break;
15731         case DRM_FORMAT_XRGB1555:
15732                 if (INTEL_INFO(dev)->gen > 3) {
15733                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15734                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15735                         kfree(format_name);
15736                         return -EINVAL;
15737                 }
15738                 break;
15739         case DRM_FORMAT_ABGR8888:
15740                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15741                     INTEL_INFO(dev)->gen < 9) {
15742                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15743                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15744                         kfree(format_name);
15745                         return -EINVAL;
15746                 }
15747                 break;
15748         case DRM_FORMAT_XBGR8888:
15749         case DRM_FORMAT_XRGB2101010:
15750         case DRM_FORMAT_XBGR2101010:
15751                 if (INTEL_INFO(dev)->gen < 4) {
15752                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15753                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15754                         kfree(format_name);
15755                         return -EINVAL;
15756                 }
15757                 break;
15758         case DRM_FORMAT_ABGR2101010:
15759                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15760                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15761                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15762                         kfree(format_name);
15763                         return -EINVAL;
15764                 }
15765                 break;
15766         case DRM_FORMAT_YUYV:
15767         case DRM_FORMAT_UYVY:
15768         case DRM_FORMAT_YVYU:
15769         case DRM_FORMAT_VYUY:
15770                 if (INTEL_INFO(dev)->gen < 5) {
15771                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15772                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15773                         kfree(format_name);
15774                         return -EINVAL;
15775                 }
15776                 break;
15777         default:
15778                 format_name = drm_get_format_name(mode_cmd->pixel_format);
15779                 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15780                 kfree(format_name);
15781                 return -EINVAL;
15782         }
15783
15784         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15785         if (mode_cmd->offsets[0] != 0)
15786                 return -EINVAL;
15787
15788         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15789         intel_fb->obj = obj;
15790
15791         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15792         if (ret)
15793                 return ret;
15794
15795         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15796         if (ret) {
15797                 DRM_ERROR("framebuffer init failed %d\n", ret);
15798                 return ret;
15799         }
15800
15801         intel_fb->obj->framebuffer_references++;
15802
15803         return 0;
15804 }
15805
15806 static struct drm_framebuffer *
15807 intel_user_framebuffer_create(struct drm_device *dev,
15808                               struct drm_file *filp,
15809                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15810 {
15811         struct drm_framebuffer *fb;
15812         struct drm_i915_gem_object *obj;
15813         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15814
15815         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15816         if (!obj)
15817                 return ERR_PTR(-ENOENT);
15818
15819         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15820         if (IS_ERR(fb))
15821                 i915_gem_object_put_unlocked(obj);
15822
15823         return fb;
15824 }
15825
15826 #ifndef CONFIG_DRM_FBDEV_EMULATION
15827 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15828 {
15829 }
15830 #endif
15831
15832 static const struct drm_mode_config_funcs intel_mode_funcs = {
15833         .fb_create = intel_user_framebuffer_create,
15834         .output_poll_changed = intel_fbdev_output_poll_changed,
15835         .atomic_check = intel_atomic_check,
15836         .atomic_commit = intel_atomic_commit,
15837         .atomic_state_alloc = intel_atomic_state_alloc,
15838         .atomic_state_clear = intel_atomic_state_clear,
15839 };
15840
15841 /**
15842  * intel_init_display_hooks - initialize the display modesetting hooks
15843  * @dev_priv: device private
15844  */
15845 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15846 {
15847         if (INTEL_INFO(dev_priv)->gen >= 9) {
15848                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15849                 dev_priv->display.get_initial_plane_config =
15850                         skylake_get_initial_plane_config;
15851                 dev_priv->display.crtc_compute_clock =
15852                         haswell_crtc_compute_clock;
15853                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15854                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15855         } else if (HAS_DDI(dev_priv)) {
15856                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15857                 dev_priv->display.get_initial_plane_config =
15858                         ironlake_get_initial_plane_config;
15859                 dev_priv->display.crtc_compute_clock =
15860                         haswell_crtc_compute_clock;
15861                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15862                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15863         } else if (HAS_PCH_SPLIT(dev_priv)) {
15864                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15865                 dev_priv->display.get_initial_plane_config =
15866                         ironlake_get_initial_plane_config;
15867                 dev_priv->display.crtc_compute_clock =
15868                         ironlake_crtc_compute_clock;
15869                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15870                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15871         } else if (IS_CHERRYVIEW(dev_priv)) {
15872                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15873                 dev_priv->display.get_initial_plane_config =
15874                         i9xx_get_initial_plane_config;
15875                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15876                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15877                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15878         } else if (IS_VALLEYVIEW(dev_priv)) {
15879                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15880                 dev_priv->display.get_initial_plane_config =
15881                         i9xx_get_initial_plane_config;
15882                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15883                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15884                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15885         } else if (IS_G4X(dev_priv)) {
15886                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15887                 dev_priv->display.get_initial_plane_config =
15888                         i9xx_get_initial_plane_config;
15889                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15890                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15891                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15892         } else if (IS_PINEVIEW(dev_priv)) {
15893                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15894                 dev_priv->display.get_initial_plane_config =
15895                         i9xx_get_initial_plane_config;
15896                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15897                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15898                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15899         } else if (!IS_GEN2(dev_priv)) {
15900                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15901                 dev_priv->display.get_initial_plane_config =
15902                         i9xx_get_initial_plane_config;
15903                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15904                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15905                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15906         } else {
15907                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15908                 dev_priv->display.get_initial_plane_config =
15909                         i9xx_get_initial_plane_config;
15910                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15911                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15912                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15913         }
15914
15915         /* Returns the core display clock speed */
15916         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15917                 dev_priv->display.get_display_clock_speed =
15918                         skylake_get_display_clock_speed;
15919         else if (IS_BROXTON(dev_priv))
15920                 dev_priv->display.get_display_clock_speed =
15921                         broxton_get_display_clock_speed;
15922         else if (IS_BROADWELL(dev_priv))
15923                 dev_priv->display.get_display_clock_speed =
15924                         broadwell_get_display_clock_speed;
15925         else if (IS_HASWELL(dev_priv))
15926                 dev_priv->display.get_display_clock_speed =
15927                         haswell_get_display_clock_speed;
15928         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15929                 dev_priv->display.get_display_clock_speed =
15930                         valleyview_get_display_clock_speed;
15931         else if (IS_GEN5(dev_priv))
15932                 dev_priv->display.get_display_clock_speed =
15933                         ilk_get_display_clock_speed;
15934         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15935                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15936                 dev_priv->display.get_display_clock_speed =
15937                         i945_get_display_clock_speed;
15938         else if (IS_GM45(dev_priv))
15939                 dev_priv->display.get_display_clock_speed =
15940                         gm45_get_display_clock_speed;
15941         else if (IS_CRESTLINE(dev_priv))
15942                 dev_priv->display.get_display_clock_speed =
15943                         i965gm_get_display_clock_speed;
15944         else if (IS_PINEVIEW(dev_priv))
15945                 dev_priv->display.get_display_clock_speed =
15946                         pnv_get_display_clock_speed;
15947         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15948                 dev_priv->display.get_display_clock_speed =
15949                         g33_get_display_clock_speed;
15950         else if (IS_I915G(dev_priv))
15951                 dev_priv->display.get_display_clock_speed =
15952                         i915_get_display_clock_speed;
15953         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15954                 dev_priv->display.get_display_clock_speed =
15955                         i9xx_misc_get_display_clock_speed;
15956         else if (IS_I915GM(dev_priv))
15957                 dev_priv->display.get_display_clock_speed =
15958                         i915gm_get_display_clock_speed;
15959         else if (IS_I865G(dev_priv))
15960                 dev_priv->display.get_display_clock_speed =
15961                         i865_get_display_clock_speed;
15962         else if (IS_I85X(dev_priv))
15963                 dev_priv->display.get_display_clock_speed =
15964                         i85x_get_display_clock_speed;
15965         else { /* 830 */
15966                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15967                 dev_priv->display.get_display_clock_speed =
15968                         i830_get_display_clock_speed;
15969         }
15970
15971         if (IS_GEN5(dev_priv)) {
15972                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15973         } else if (IS_GEN6(dev_priv)) {
15974                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15975         } else if (IS_IVYBRIDGE(dev_priv)) {
15976                 /* FIXME: detect B0+ stepping and use auto training */
15977                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15978         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15979                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15980         }
15981
15982         if (IS_BROADWELL(dev_priv)) {
15983                 dev_priv->display.modeset_commit_cdclk =
15984                         broadwell_modeset_commit_cdclk;
15985                 dev_priv->display.modeset_calc_cdclk =
15986                         broadwell_modeset_calc_cdclk;
15987         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15988                 dev_priv->display.modeset_commit_cdclk =
15989                         valleyview_modeset_commit_cdclk;
15990                 dev_priv->display.modeset_calc_cdclk =
15991                         valleyview_modeset_calc_cdclk;
15992         } else if (IS_BROXTON(dev_priv)) {
15993                 dev_priv->display.modeset_commit_cdclk =
15994                         bxt_modeset_commit_cdclk;
15995                 dev_priv->display.modeset_calc_cdclk =
15996                         bxt_modeset_calc_cdclk;
15997         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15998                 dev_priv->display.modeset_commit_cdclk =
15999                         skl_modeset_commit_cdclk;
16000                 dev_priv->display.modeset_calc_cdclk =
16001                         skl_modeset_calc_cdclk;
16002         }
16003
16004         if (dev_priv->info.gen >= 9)
16005                 dev_priv->display.update_crtcs = skl_update_crtcs;
16006         else
16007                 dev_priv->display.update_crtcs = intel_update_crtcs;
16008
16009         switch (INTEL_INFO(dev_priv)->gen) {
16010         case 2:
16011                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16012                 break;
16013
16014         case 3:
16015                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16016                 break;
16017
16018         case 4:
16019         case 5:
16020                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16021                 break;
16022
16023         case 6:
16024                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16025                 break;
16026         case 7:
16027         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16028                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16029                 break;
16030         case 9:
16031                 /* Drop through - unsupported since execlist only. */
16032         default:
16033                 /* Default just returns -ENODEV to indicate unsupported */
16034                 dev_priv->display.queue_flip = intel_default_queue_flip;
16035         }
16036 }
16037
16038 /*
16039  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16040  * resume, or other times.  This quirk makes sure that's the case for
16041  * affected systems.
16042  */
16043 static void quirk_pipea_force(struct drm_device *dev)
16044 {
16045         struct drm_i915_private *dev_priv = to_i915(dev);
16046
16047         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16048         DRM_INFO("applying pipe a force quirk\n");
16049 }
16050
16051 static void quirk_pipeb_force(struct drm_device *dev)
16052 {
16053         struct drm_i915_private *dev_priv = to_i915(dev);
16054
16055         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16056         DRM_INFO("applying pipe b force quirk\n");
16057 }
16058
16059 /*
16060  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16061  */
16062 static void quirk_ssc_force_disable(struct drm_device *dev)
16063 {
16064         struct drm_i915_private *dev_priv = to_i915(dev);
16065         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16066         DRM_INFO("applying lvds SSC disable quirk\n");
16067 }
16068
16069 /*
16070  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16071  * brightness value
16072  */
16073 static void quirk_invert_brightness(struct drm_device *dev)
16074 {
16075         struct drm_i915_private *dev_priv = to_i915(dev);
16076         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16077         DRM_INFO("applying inverted panel brightness quirk\n");
16078 }
16079
16080 /* Some VBT's incorrectly indicate no backlight is present */
16081 static void quirk_backlight_present(struct drm_device *dev)
16082 {
16083         struct drm_i915_private *dev_priv = to_i915(dev);
16084         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16085         DRM_INFO("applying backlight present quirk\n");
16086 }
16087
16088 struct intel_quirk {
16089         int device;
16090         int subsystem_vendor;
16091         int subsystem_device;
16092         void (*hook)(struct drm_device *dev);
16093 };
16094
16095 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16096 struct intel_dmi_quirk {
16097         void (*hook)(struct drm_device *dev);
16098         const struct dmi_system_id (*dmi_id_list)[];
16099 };
16100
16101 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16102 {
16103         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16104         return 1;
16105 }
16106
16107 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16108         {
16109                 .dmi_id_list = &(const struct dmi_system_id[]) {
16110                         {
16111                                 .callback = intel_dmi_reverse_brightness,
16112                                 .ident = "NCR Corporation",
16113                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16114                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
16115                                 },
16116                         },
16117                         { }  /* terminating entry */
16118                 },
16119                 .hook = quirk_invert_brightness,
16120         },
16121 };
16122
16123 static struct intel_quirk intel_quirks[] = {
16124         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16125         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16126
16127         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16128         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16129
16130         /* 830 needs to leave pipe A & dpll A up */
16131         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16132
16133         /* 830 needs to leave pipe B & dpll B up */
16134         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16135
16136         /* Lenovo U160 cannot use SSC on LVDS */
16137         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16138
16139         /* Sony Vaio Y cannot use SSC on LVDS */
16140         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16141
16142         /* Acer Aspire 5734Z must invert backlight brightness */
16143         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16144
16145         /* Acer/eMachines G725 */
16146         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16147
16148         /* Acer/eMachines e725 */
16149         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16150
16151         /* Acer/Packard Bell NCL20 */
16152         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16153
16154         /* Acer Aspire 4736Z */
16155         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16156
16157         /* Acer Aspire 5336 */
16158         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16159
16160         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16161         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16162
16163         /* Acer C720 Chromebook (Core i3 4005U) */
16164         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16165
16166         /* Apple Macbook 2,1 (Core 2 T7400) */
16167         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16168
16169         /* Apple Macbook 4,1 */
16170         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16171
16172         /* Toshiba CB35 Chromebook (Celeron 2955U) */
16173         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16174
16175         /* HP Chromebook 14 (Celeron 2955U) */
16176         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16177
16178         /* Dell Chromebook 11 */
16179         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16180
16181         /* Dell Chromebook 11 (2015 version) */
16182         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16183 };
16184
16185 static void intel_init_quirks(struct drm_device *dev)
16186 {
16187         struct pci_dev *d = dev->pdev;
16188         int i;
16189
16190         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16191                 struct intel_quirk *q = &intel_quirks[i];
16192
16193                 if (d->device == q->device &&
16194                     (d->subsystem_vendor == q->subsystem_vendor ||
16195                      q->subsystem_vendor == PCI_ANY_ID) &&
16196                     (d->subsystem_device == q->subsystem_device ||
16197                      q->subsystem_device == PCI_ANY_ID))
16198                         q->hook(dev);
16199         }
16200         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16201                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16202                         intel_dmi_quirks[i].hook(dev);
16203         }
16204 }
16205
16206 /* Disable the VGA plane that we never use */
16207 static void i915_disable_vga(struct drm_device *dev)
16208 {
16209         struct drm_i915_private *dev_priv = to_i915(dev);
16210         struct pci_dev *pdev = dev_priv->drm.pdev;
16211         u8 sr1;
16212         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16213
16214         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16215         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16216         outb(SR01, VGA_SR_INDEX);
16217         sr1 = inb(VGA_SR_DATA);
16218         outb(sr1 | 1<<5, VGA_SR_DATA);
16219         vga_put(pdev, VGA_RSRC_LEGACY_IO);
16220         udelay(300);
16221
16222         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16223         POSTING_READ(vga_reg);
16224 }
16225
16226 void intel_modeset_init_hw(struct drm_device *dev)
16227 {
16228         struct drm_i915_private *dev_priv = to_i915(dev);
16229
16230         intel_update_cdclk(dev);
16231
16232         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16233
16234         intel_init_clock_gating(dev);
16235 }
16236
16237 /*
16238  * Calculate what we think the watermarks should be for the state we've read
16239  * out of the hardware and then immediately program those watermarks so that
16240  * we ensure the hardware settings match our internal state.
16241  *
16242  * We can calculate what we think WM's should be by creating a duplicate of the
16243  * current state (which was constructed during hardware readout) and running it
16244  * through the atomic check code to calculate new watermark values in the
16245  * state object.
16246  */
16247 static void sanitize_watermarks(struct drm_device *dev)
16248 {
16249         struct drm_i915_private *dev_priv = to_i915(dev);
16250         struct drm_atomic_state *state;
16251         struct drm_crtc *crtc;
16252         struct drm_crtc_state *cstate;
16253         struct drm_modeset_acquire_ctx ctx;
16254         int ret;
16255         int i;
16256
16257         /* Only supported on platforms that use atomic watermark design */
16258         if (!dev_priv->display.optimize_watermarks)
16259                 return;
16260
16261         /*
16262          * We need to hold connection_mutex before calling duplicate_state so
16263          * that the connector loop is protected.
16264          */
16265         drm_modeset_acquire_init(&ctx, 0);
16266 retry:
16267         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16268         if (ret == -EDEADLK) {
16269                 drm_modeset_backoff(&ctx);
16270                 goto retry;
16271         } else if (WARN_ON(ret)) {
16272                 goto fail;
16273         }
16274
16275         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16276         if (WARN_ON(IS_ERR(state)))
16277                 goto fail;
16278
16279         /*
16280          * Hardware readout is the only time we don't want to calculate
16281          * intermediate watermarks (since we don't trust the current
16282          * watermarks).
16283          */
16284         to_intel_atomic_state(state)->skip_intermediate_wm = true;
16285
16286         ret = intel_atomic_check(dev, state);
16287         if (ret) {
16288                 /*
16289                  * If we fail here, it means that the hardware appears to be
16290                  * programmed in a way that shouldn't be possible, given our
16291                  * understanding of watermark requirements.  This might mean a
16292                  * mistake in the hardware readout code or a mistake in the
16293                  * watermark calculations for a given platform.  Raise a WARN
16294                  * so that this is noticeable.
16295                  *
16296                  * If this actually happens, we'll have to just leave the
16297                  * BIOS-programmed watermarks untouched and hope for the best.
16298                  */
16299                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16300                 goto fail;
16301         }
16302
16303         /* Write calculated watermark values back */
16304         for_each_crtc_in_state(state, crtc, cstate, i) {
16305                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16306
16307                 cs->wm.need_postvbl_update = true;
16308                 dev_priv->display.optimize_watermarks(cs);
16309         }
16310
16311         drm_atomic_state_free(state);
16312 fail:
16313         drm_modeset_drop_locks(&ctx);
16314         drm_modeset_acquire_fini(&ctx);
16315 }
16316
16317 void intel_modeset_init(struct drm_device *dev)
16318 {
16319         struct drm_i915_private *dev_priv = to_i915(dev);
16320         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16321         int sprite, ret;
16322         enum pipe pipe;
16323         struct intel_crtc *crtc;
16324
16325         drm_mode_config_init(dev);
16326
16327         dev->mode_config.min_width = 0;
16328         dev->mode_config.min_height = 0;
16329
16330         dev->mode_config.preferred_depth = 24;
16331         dev->mode_config.prefer_shadow = 1;
16332
16333         dev->mode_config.allow_fb_modifiers = true;
16334
16335         dev->mode_config.funcs = &intel_mode_funcs;
16336
16337         intel_init_quirks(dev);
16338
16339         intel_init_pm(dev);
16340
16341         if (INTEL_INFO(dev)->num_pipes == 0)
16342                 return;
16343
16344         /*
16345          * There may be no VBT; and if the BIOS enabled SSC we can
16346          * just keep using it to avoid unnecessary flicker.  Whereas if the
16347          * BIOS isn't using it, don't assume it will work even if the VBT
16348          * indicates as much.
16349          */
16350         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
16351                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16352                                             DREF_SSC1_ENABLE);
16353
16354                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16355                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16356                                      bios_lvds_use_ssc ? "en" : "dis",
16357                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16358                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16359                 }
16360         }
16361
16362         if (IS_GEN2(dev)) {
16363                 dev->mode_config.max_width = 2048;
16364                 dev->mode_config.max_height = 2048;
16365         } else if (IS_GEN3(dev)) {
16366                 dev->mode_config.max_width = 4096;
16367                 dev->mode_config.max_height = 4096;
16368         } else {
16369                 dev->mode_config.max_width = 8192;
16370                 dev->mode_config.max_height = 8192;
16371         }
16372
16373         if (IS_845G(dev) || IS_I865G(dev)) {
16374                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
16375                 dev->mode_config.cursor_height = 1023;
16376         } else if (IS_GEN2(dev)) {
16377                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16378                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16379         } else {
16380                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16381                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16382         }
16383
16384         dev->mode_config.fb_base = ggtt->mappable_base;
16385
16386         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16387                       INTEL_INFO(dev)->num_pipes,
16388                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16389
16390         for_each_pipe(dev_priv, pipe) {
16391                 intel_crtc_init(dev, pipe);
16392                 for_each_sprite(dev_priv, pipe, sprite) {
16393                         ret = intel_plane_init(dev, pipe, sprite);
16394                         if (ret)
16395                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16396                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
16397                 }
16398         }
16399
16400         intel_update_czclk(dev_priv);
16401         intel_update_cdclk(dev);
16402
16403         intel_shared_dpll_init(dev);
16404
16405         if (dev_priv->max_cdclk_freq == 0)
16406                 intel_update_max_cdclk(dev);
16407
16408         /* Just disable it once at startup */
16409         i915_disable_vga(dev);
16410         intel_setup_outputs(dev);
16411
16412         drm_modeset_lock_all(dev);
16413         intel_modeset_setup_hw_state(dev);
16414         drm_modeset_unlock_all(dev);
16415
16416         for_each_intel_crtc(dev, crtc) {
16417                 struct intel_initial_plane_config plane_config = {};
16418
16419                 if (!crtc->active)
16420                         continue;
16421
16422                 /*
16423                  * Note that reserving the BIOS fb up front prevents us
16424                  * from stuffing other stolen allocations like the ring
16425                  * on top.  This prevents some ugliness at boot time, and
16426                  * can even allow for smooth boot transitions if the BIOS
16427                  * fb is large enough for the active pipe configuration.
16428                  */
16429                 dev_priv->display.get_initial_plane_config(crtc,
16430                                                            &plane_config);
16431
16432                 /*
16433                  * If the fb is shared between multiple heads, we'll
16434                  * just get the first one.
16435                  */
16436                 intel_find_initial_plane_obj(crtc, &plane_config);
16437         }
16438
16439         /*
16440          * Make sure hardware watermarks really match the state we read out.
16441          * Note that we need to do this after reconstructing the BIOS fb's
16442          * since the watermark calculation done here will use pstate->fb.
16443          */
16444         sanitize_watermarks(dev);
16445 }
16446
16447 static void intel_enable_pipe_a(struct drm_device *dev)
16448 {
16449         struct intel_connector *connector;
16450         struct drm_connector *crt = NULL;
16451         struct intel_load_detect_pipe load_detect_temp;
16452         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16453
16454         /* We can't just switch on the pipe A, we need to set things up with a
16455          * proper mode and output configuration. As a gross hack, enable pipe A
16456          * by enabling the load detect pipe once. */
16457         for_each_intel_connector(dev, connector) {
16458                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16459                         crt = &connector->base;
16460                         break;
16461                 }
16462         }
16463
16464         if (!crt)
16465                 return;
16466
16467         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16468                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16469 }
16470
16471 static bool
16472 intel_check_plane_mapping(struct intel_crtc *crtc)
16473 {
16474         struct drm_device *dev = crtc->base.dev;
16475         struct drm_i915_private *dev_priv = to_i915(dev);
16476         u32 val;
16477
16478         if (INTEL_INFO(dev)->num_pipes == 1)
16479                 return true;
16480
16481         val = I915_READ(DSPCNTR(!crtc->plane));
16482
16483         if ((val & DISPLAY_PLANE_ENABLE) &&
16484             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16485                 return false;
16486
16487         return true;
16488 }
16489
16490 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16491 {
16492         struct drm_device *dev = crtc->base.dev;
16493         struct intel_encoder *encoder;
16494
16495         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16496                 return true;
16497
16498         return false;
16499 }
16500
16501 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16502 {
16503         struct drm_device *dev = encoder->base.dev;
16504         struct intel_connector *connector;
16505
16506         for_each_connector_on_encoder(dev, &encoder->base, connector)
16507                 return connector;
16508
16509         return NULL;
16510 }
16511
16512 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16513                               enum transcoder pch_transcoder)
16514 {
16515         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16516                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16517 }
16518
16519 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16520 {
16521         struct drm_device *dev = crtc->base.dev;
16522         struct drm_i915_private *dev_priv = to_i915(dev);
16523         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16524
16525         /* Clear any frame start delays used for debugging left by the BIOS */
16526         if (!transcoder_is_dsi(cpu_transcoder)) {
16527                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16528
16529                 I915_WRITE(reg,
16530                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16531         }
16532
16533         /* restore vblank interrupts to correct state */
16534         drm_crtc_vblank_reset(&crtc->base);
16535         if (crtc->active) {
16536                 struct intel_plane *plane;
16537
16538                 drm_crtc_vblank_on(&crtc->base);
16539
16540                 /* Disable everything but the primary plane */
16541                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16542                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16543                                 continue;
16544
16545                         plane->disable_plane(&plane->base, &crtc->base);
16546                 }
16547         }
16548
16549         /* We need to sanitize the plane -> pipe mapping first because this will
16550          * disable the crtc (and hence change the state) if it is wrong. Note
16551          * that gen4+ has a fixed plane -> pipe mapping.  */
16552         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16553                 bool plane;
16554
16555                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16556                               crtc->base.base.id, crtc->base.name);
16557
16558                 /* Pipe has the wrong plane attached and the plane is active.
16559                  * Temporarily change the plane mapping and disable everything
16560                  * ...  */
16561                 plane = crtc->plane;
16562                 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16563                 crtc->plane = !plane;
16564                 intel_crtc_disable_noatomic(&crtc->base);
16565                 crtc->plane = plane;
16566         }
16567
16568         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16569             crtc->pipe == PIPE_A && !crtc->active) {
16570                 /* BIOS forgot to enable pipe A, this mostly happens after
16571                  * resume. Force-enable the pipe to fix this, the update_dpms
16572                  * call below we restore the pipe to the right state, but leave
16573                  * the required bits on. */
16574                 intel_enable_pipe_a(dev);
16575         }
16576
16577         /* Adjust the state of the output pipe according to whether we
16578          * have active connectors/encoders. */
16579         if (crtc->active && !intel_crtc_has_encoders(crtc))
16580                 intel_crtc_disable_noatomic(&crtc->base);
16581
16582         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
16583                 /*
16584                  * We start out with underrun reporting disabled to avoid races.
16585                  * For correct bookkeeping mark this on active crtcs.
16586                  *
16587                  * Also on gmch platforms we dont have any hardware bits to
16588                  * disable the underrun reporting. Which means we need to start
16589                  * out with underrun reporting disabled also on inactive pipes,
16590                  * since otherwise we'll complain about the garbage we read when
16591                  * e.g. coming up after runtime pm.
16592                  *
16593                  * No protection against concurrent access is required - at
16594                  * worst a fifo underrun happens which also sets this to false.
16595                  */
16596                 crtc->cpu_fifo_underrun_disabled = true;
16597                 /*
16598                  * We track the PCH trancoder underrun reporting state
16599                  * within the crtc. With crtc for pipe A housing the underrun
16600                  * reporting state for PCH transcoder A, crtc for pipe B housing
16601                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16602                  * and marking underrun reporting as disabled for the non-existing
16603                  * PCH transcoders B and C would prevent enabling the south
16604                  * error interrupt (see cpt_can_enable_serr_int()).
16605                  */
16606                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16607                         crtc->pch_fifo_underrun_disabled = true;
16608         }
16609 }
16610
16611 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16612 {
16613         struct intel_connector *connector;
16614
16615         /* We need to check both for a crtc link (meaning that the
16616          * encoder is active and trying to read from a pipe) and the
16617          * pipe itself being active. */
16618         bool has_active_crtc = encoder->base.crtc &&
16619                 to_intel_crtc(encoder->base.crtc)->active;
16620
16621         connector = intel_encoder_find_connector(encoder);
16622         if (connector && !has_active_crtc) {
16623                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16624                               encoder->base.base.id,
16625                               encoder->base.name);
16626
16627                 /* Connector is active, but has no active pipe. This is
16628                  * fallout from our resume register restoring. Disable
16629                  * the encoder manually again. */
16630                 if (encoder->base.crtc) {
16631                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16632
16633                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16634                                       encoder->base.base.id,
16635                                       encoder->base.name);
16636                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16637                         if (encoder->post_disable)
16638                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16639                 }
16640                 encoder->base.crtc = NULL;
16641
16642                 /* Inconsistent output/port/pipe state happens presumably due to
16643                  * a bug in one of the get_hw_state functions. Or someplace else
16644                  * in our code, like the register restore mess on resume. Clamp
16645                  * things to off as a safer default. */
16646
16647                 connector->base.dpms = DRM_MODE_DPMS_OFF;
16648                 connector->base.encoder = NULL;
16649         }
16650         /* Enabled encoders without active connectors will be fixed in
16651          * the crtc fixup. */
16652 }
16653
16654 void i915_redisable_vga_power_on(struct drm_device *dev)
16655 {
16656         struct drm_i915_private *dev_priv = to_i915(dev);
16657         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16658
16659         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16660                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16661                 i915_disable_vga(dev);
16662         }
16663 }
16664
16665 void i915_redisable_vga(struct drm_device *dev)
16666 {
16667         struct drm_i915_private *dev_priv = to_i915(dev);
16668
16669         /* This function can be called both from intel_modeset_setup_hw_state or
16670          * at a very early point in our resume sequence, where the power well
16671          * structures are not yet restored. Since this function is at a very
16672          * paranoid "someone might have enabled VGA while we were not looking"
16673          * level, just check if the power well is enabled instead of trying to
16674          * follow the "don't touch the power well if we don't need it" policy
16675          * the rest of the driver uses. */
16676         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16677                 return;
16678
16679         i915_redisable_vga_power_on(dev);
16680
16681         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16682 }
16683
16684 static bool primary_get_hw_state(struct intel_plane *plane)
16685 {
16686         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16687
16688         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16689 }
16690
16691 /* FIXME read out full plane state for all planes */
16692 static void readout_plane_state(struct intel_crtc *crtc)
16693 {
16694         struct drm_plane *primary = crtc->base.primary;
16695         struct intel_plane_state *plane_state =
16696                 to_intel_plane_state(primary->state);
16697
16698         plane_state->base.visible = crtc->active &&
16699                 primary_get_hw_state(to_intel_plane(primary));
16700
16701         if (plane_state->base.visible)
16702                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16703 }
16704
16705 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16706 {
16707         struct drm_i915_private *dev_priv = to_i915(dev);
16708         enum pipe pipe;
16709         struct intel_crtc *crtc;
16710         struct intel_encoder *encoder;
16711         struct intel_connector *connector;
16712         int i;
16713
16714         dev_priv->active_crtcs = 0;
16715
16716         for_each_intel_crtc(dev, crtc) {
16717                 struct intel_crtc_state *crtc_state = crtc->config;
16718                 int pixclk = 0;
16719
16720                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16721                 memset(crtc_state, 0, sizeof(*crtc_state));
16722                 crtc_state->base.crtc = &crtc->base;
16723
16724                 crtc_state->base.active = crtc_state->base.enable =
16725                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16726
16727                 crtc->base.enabled = crtc_state->base.enable;
16728                 crtc->active = crtc_state->base.active;
16729
16730                 if (crtc_state->base.active) {
16731                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16732
16733                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16734                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
16735                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16736                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16737                         else
16738                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16739
16740                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16741                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16742                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16743                 }
16744
16745                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16746
16747                 readout_plane_state(crtc);
16748
16749                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16750                               crtc->base.base.id, crtc->base.name,
16751                               crtc->active ? "enabled" : "disabled");
16752         }
16753
16754         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16755                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16756
16757                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16758                                                   &pll->config.hw_state);
16759                 pll->config.crtc_mask = 0;
16760                 for_each_intel_crtc(dev, crtc) {
16761                         if (crtc->active && crtc->config->shared_dpll == pll)
16762                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16763                 }
16764                 pll->active_mask = pll->config.crtc_mask;
16765
16766                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16767                               pll->name, pll->config.crtc_mask, pll->on);
16768         }
16769
16770         for_each_intel_encoder(dev, encoder) {
16771                 pipe = 0;
16772
16773                 if (encoder->get_hw_state(encoder, &pipe)) {
16774                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16775                         encoder->base.crtc = &crtc->base;
16776                         crtc->config->output_types |= 1 << encoder->type;
16777                         encoder->get_config(encoder, crtc->config);
16778                 } else {
16779                         encoder->base.crtc = NULL;
16780                 }
16781
16782                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16783                               encoder->base.base.id,
16784                               encoder->base.name,
16785                               encoder->base.crtc ? "enabled" : "disabled",
16786                               pipe_name(pipe));
16787         }
16788
16789         for_each_intel_connector(dev, connector) {
16790                 if (connector->get_hw_state(connector)) {
16791                         connector->base.dpms = DRM_MODE_DPMS_ON;
16792
16793                         encoder = connector->encoder;
16794                         connector->base.encoder = &encoder->base;
16795
16796                         if (encoder->base.crtc &&
16797                             encoder->base.crtc->state->active) {
16798                                 /*
16799                                  * This has to be done during hardware readout
16800                                  * because anything calling .crtc_disable may
16801                                  * rely on the connector_mask being accurate.
16802                                  */
16803                                 encoder->base.crtc->state->connector_mask |=
16804                                         1 << drm_connector_index(&connector->base);
16805                                 encoder->base.crtc->state->encoder_mask |=
16806                                         1 << drm_encoder_index(&encoder->base);
16807                         }
16808
16809                 } else {
16810                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16811                         connector->base.encoder = NULL;
16812                 }
16813                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16814                               connector->base.base.id,
16815                               connector->base.name,
16816                               connector->base.encoder ? "enabled" : "disabled");
16817         }
16818
16819         for_each_intel_crtc(dev, crtc) {
16820                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16821
16822                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16823                 if (crtc->base.state->active) {
16824                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16825                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16826                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16827
16828                         /*
16829                          * The initial mode needs to be set in order to keep
16830                          * the atomic core happy. It wants a valid mode if the
16831                          * crtc's enabled, so we do the above call.
16832                          *
16833                          * At this point some state updated by the connectors
16834                          * in their ->detect() callback has not run yet, so
16835                          * no recalculation can be done yet.
16836                          *
16837                          * Even if we could do a recalculation and modeset
16838                          * right now it would cause a double modeset if
16839                          * fbdev or userspace chooses a different initial mode.
16840                          *
16841                          * If that happens, someone indicated they wanted a
16842                          * mode change, which means it's safe to do a full
16843                          * recalculation.
16844                          */
16845                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16846
16847                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16848                         update_scanline_offset(crtc);
16849                 }
16850
16851                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16852         }
16853 }
16854
16855 /* Scan out the current hw modeset state,
16856  * and sanitizes it to the current state
16857  */
16858 static void
16859 intel_modeset_setup_hw_state(struct drm_device *dev)
16860 {
16861         struct drm_i915_private *dev_priv = to_i915(dev);
16862         enum pipe pipe;
16863         struct intel_crtc *crtc;
16864         struct intel_encoder *encoder;
16865         int i;
16866
16867         intel_modeset_readout_hw_state(dev);
16868
16869         /* HW state is read out, now we need to sanitize this mess. */
16870         for_each_intel_encoder(dev, encoder) {
16871                 intel_sanitize_encoder(encoder);
16872         }
16873
16874         for_each_pipe(dev_priv, pipe) {
16875                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16876                 intel_sanitize_crtc(crtc);
16877                 intel_dump_pipe_config(crtc, crtc->config,
16878                                        "[setup_hw_state]");
16879         }
16880
16881         intel_modeset_update_connector_atomic_state(dev);
16882
16883         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16884                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16885
16886                 if (!pll->on || pll->active_mask)
16887                         continue;
16888
16889                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16890
16891                 pll->funcs.disable(dev_priv, pll);
16892                 pll->on = false;
16893         }
16894
16895         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16896                 vlv_wm_get_hw_state(dev);
16897         else if (IS_GEN9(dev))
16898                 skl_wm_get_hw_state(dev);
16899         else if (HAS_PCH_SPLIT(dev))
16900                 ilk_wm_get_hw_state(dev);
16901
16902         for_each_intel_crtc(dev, crtc) {
16903                 unsigned long put_domains;
16904
16905                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16906                 if (WARN_ON(put_domains))
16907                         modeset_put_power_domains(dev_priv, put_domains);
16908         }
16909         intel_display_set_init_power(dev_priv, false);
16910
16911         intel_fbc_init_pipe_state(dev_priv);
16912 }
16913
16914 void intel_display_resume(struct drm_device *dev)
16915 {
16916         struct drm_i915_private *dev_priv = to_i915(dev);
16917         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16918         struct drm_modeset_acquire_ctx ctx;
16919         int ret;
16920
16921         dev_priv->modeset_restore_state = NULL;
16922         if (state)
16923                 state->acquire_ctx = &ctx;
16924
16925         /*
16926          * This is a cludge because with real atomic modeset mode_config.mutex
16927          * won't be taken. Unfortunately some probed state like
16928          * audio_codec_enable is still protected by mode_config.mutex, so lock
16929          * it here for now.
16930          */
16931         mutex_lock(&dev->mode_config.mutex);
16932         drm_modeset_acquire_init(&ctx, 0);
16933
16934         while (1) {
16935                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16936                 if (ret != -EDEADLK)
16937                         break;
16938
16939                 drm_modeset_backoff(&ctx);
16940         }
16941
16942         if (!ret)
16943                 ret = __intel_display_resume(dev, state);
16944
16945         drm_modeset_drop_locks(&ctx);
16946         drm_modeset_acquire_fini(&ctx);
16947         mutex_unlock(&dev->mode_config.mutex);
16948
16949         if (ret) {
16950                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16951                 drm_atomic_state_free(state);
16952         }
16953 }
16954
16955 void intel_modeset_gem_init(struct drm_device *dev)
16956 {
16957         struct drm_i915_private *dev_priv = to_i915(dev);
16958         struct drm_crtc *c;
16959         struct drm_i915_gem_object *obj;
16960
16961         intel_init_gt_powersave(dev_priv);
16962
16963         intel_modeset_init_hw(dev);
16964
16965         intel_setup_overlay(dev_priv);
16966
16967         /*
16968          * Make sure any fbs we allocated at startup are properly
16969          * pinned & fenced.  When we do the allocation it's too early
16970          * for this.
16971          */
16972         for_each_crtc(dev, c) {
16973                 struct i915_vma *vma;
16974
16975                 obj = intel_fb_obj(c->primary->fb);
16976                 if (obj == NULL)
16977                         continue;
16978
16979                 mutex_lock(&dev->struct_mutex);
16980                 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
16981                                                  c->primary->state->rotation);
16982                 mutex_unlock(&dev->struct_mutex);
16983                 if (IS_ERR(vma)) {
16984                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16985                                   to_intel_crtc(c)->pipe);
16986                         drm_framebuffer_unreference(c->primary->fb);
16987                         c->primary->fb = NULL;
16988                         c->primary->crtc = c->primary->state->crtc = NULL;
16989                         update_state_fb(c->primary);
16990                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16991                 }
16992         }
16993 }
16994
16995 int intel_connector_register(struct drm_connector *connector)
16996 {
16997         struct intel_connector *intel_connector = to_intel_connector(connector);
16998         int ret;
16999
17000         ret = intel_backlight_device_register(intel_connector);
17001         if (ret)
17002                 goto err;
17003
17004         return 0;
17005
17006 err:
17007         return ret;
17008 }
17009
17010 void intel_connector_unregister(struct drm_connector *connector)
17011 {
17012         struct intel_connector *intel_connector = to_intel_connector(connector);
17013
17014         intel_backlight_device_unregister(intel_connector);
17015         intel_panel_destroy_backlight(connector);
17016 }
17017
17018 void intel_modeset_cleanup(struct drm_device *dev)
17019 {
17020         struct drm_i915_private *dev_priv = to_i915(dev);
17021
17022         intel_disable_gt_powersave(dev_priv);
17023
17024         /*
17025          * Interrupts and polling as the first thing to avoid creating havoc.
17026          * Too much stuff here (turning of connectors, ...) would
17027          * experience fancy races otherwise.
17028          */
17029         intel_irq_uninstall(dev_priv);
17030
17031         /*
17032          * Due to the hpd irq storm handling the hotplug work can re-arm the
17033          * poll handlers. Hence disable polling after hpd handling is shut down.
17034          */
17035         drm_kms_helper_poll_fini(dev);
17036
17037         intel_unregister_dsm_handler();
17038
17039         intel_fbc_global_disable(dev_priv);
17040
17041         /* flush any delayed tasks or pending work */
17042         flush_scheduled_work();
17043
17044         drm_mode_config_cleanup(dev);
17045
17046         intel_cleanup_overlay(dev_priv);
17047
17048         intel_cleanup_gt_powersave(dev_priv);
17049
17050         intel_teardown_gmbus(dev);
17051 }
17052
17053 void intel_connector_attach_encoder(struct intel_connector *connector,
17054                                     struct intel_encoder *encoder)
17055 {
17056         connector->encoder = encoder;
17057         drm_mode_connector_attach_encoder(&connector->base,
17058                                           &encoder->base);
17059 }
17060
17061 /*
17062  * set vga decode state - true == enable VGA decode
17063  */
17064 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
17065 {
17066         struct drm_i915_private *dev_priv = to_i915(dev);
17067         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17068         u16 gmch_ctrl;
17069
17070         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17071                 DRM_ERROR("failed to read control word\n");
17072                 return -EIO;
17073         }
17074
17075         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17076                 return 0;
17077
17078         if (state)
17079                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17080         else
17081                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17082
17083         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17084                 DRM_ERROR("failed to write control word\n");
17085                 return -EIO;
17086         }
17087
17088         return 0;
17089 }
17090
17091 struct intel_display_error_state {
17092
17093         u32 power_well_driver;
17094
17095         int num_transcoders;
17096
17097         struct intel_cursor_error_state {
17098                 u32 control;
17099                 u32 position;
17100                 u32 base;
17101                 u32 size;
17102         } cursor[I915_MAX_PIPES];
17103
17104         struct intel_pipe_error_state {
17105                 bool power_domain_on;
17106                 u32 source;
17107                 u32 stat;
17108         } pipe[I915_MAX_PIPES];
17109
17110         struct intel_plane_error_state {
17111                 u32 control;
17112                 u32 stride;
17113                 u32 size;
17114                 u32 pos;
17115                 u32 addr;
17116                 u32 surface;
17117                 u32 tile_offset;
17118         } plane[I915_MAX_PIPES];
17119
17120         struct intel_transcoder_error_state {
17121                 bool power_domain_on;
17122                 enum transcoder cpu_transcoder;
17123
17124                 u32 conf;
17125
17126                 u32 htotal;
17127                 u32 hblank;
17128                 u32 hsync;
17129                 u32 vtotal;
17130                 u32 vblank;
17131                 u32 vsync;
17132         } transcoder[4];
17133 };
17134
17135 struct intel_display_error_state *
17136 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17137 {
17138         struct intel_display_error_state *error;
17139         int transcoders[] = {
17140                 TRANSCODER_A,
17141                 TRANSCODER_B,
17142                 TRANSCODER_C,
17143                 TRANSCODER_EDP,
17144         };
17145         int i;
17146
17147         if (INTEL_INFO(dev_priv)->num_pipes == 0)
17148                 return NULL;
17149
17150         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17151         if (error == NULL)
17152                 return NULL;
17153
17154         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17155                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17156
17157         for_each_pipe(dev_priv, i) {
17158                 error->pipe[i].power_domain_on =
17159                         __intel_display_power_is_enabled(dev_priv,
17160                                                          POWER_DOMAIN_PIPE(i));
17161                 if (!error->pipe[i].power_domain_on)
17162                         continue;
17163
17164                 error->cursor[i].control = I915_READ(CURCNTR(i));
17165                 error->cursor[i].position = I915_READ(CURPOS(i));
17166                 error->cursor[i].base = I915_READ(CURBASE(i));
17167
17168                 error->plane[i].control = I915_READ(DSPCNTR(i));
17169                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17170                 if (INTEL_GEN(dev_priv) <= 3) {
17171                         error->plane[i].size = I915_READ(DSPSIZE(i));
17172                         error->plane[i].pos = I915_READ(DSPPOS(i));
17173                 }
17174                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17175                         error->plane[i].addr = I915_READ(DSPADDR(i));
17176                 if (INTEL_GEN(dev_priv) >= 4) {
17177                         error->plane[i].surface = I915_READ(DSPSURF(i));
17178                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17179                 }
17180
17181                 error->pipe[i].source = I915_READ(PIPESRC(i));
17182
17183                 if (HAS_GMCH_DISPLAY(dev_priv))
17184                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17185         }
17186
17187         /* Note: this does not include DSI transcoders. */
17188         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17189         if (HAS_DDI(dev_priv))
17190                 error->num_transcoders++; /* Account for eDP. */
17191
17192         for (i = 0; i < error->num_transcoders; i++) {
17193                 enum transcoder cpu_transcoder = transcoders[i];
17194
17195                 error->transcoder[i].power_domain_on =
17196                         __intel_display_power_is_enabled(dev_priv,
17197                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17198                 if (!error->transcoder[i].power_domain_on)
17199                         continue;
17200
17201                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17202
17203                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17204                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17205                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17206                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17207                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17208                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17209                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17210         }
17211
17212         return error;
17213 }
17214
17215 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17216
17217 void
17218 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17219                                 struct drm_device *dev,
17220                                 struct intel_display_error_state *error)
17221 {
17222         struct drm_i915_private *dev_priv = to_i915(dev);
17223         int i;
17224
17225         if (!error)
17226                 return;
17227
17228         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
17229         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
17230                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17231                            error->power_well_driver);
17232         for_each_pipe(dev_priv, i) {
17233                 err_printf(m, "Pipe [%d]:\n", i);
17234                 err_printf(m, "  Power: %s\n",
17235                            onoff(error->pipe[i].power_domain_on));
17236                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17237                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17238
17239                 err_printf(m, "Plane [%d]:\n", i);
17240                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17241                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17242                 if (INTEL_INFO(dev)->gen <= 3) {
17243                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17244                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17245                 }
17246                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
17247                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17248                 if (INTEL_INFO(dev)->gen >= 4) {
17249                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17250                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17251                 }
17252
17253                 err_printf(m, "Cursor [%d]:\n", i);
17254                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17255                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17256                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17257         }
17258
17259         for (i = 0; i < error->num_transcoders; i++) {
17260                 err_printf(m, "CPU transcoder: %s\n",
17261                            transcoder_name(error->transcoder[i].cpu_transcoder));
17262                 err_printf(m, "  Power: %s\n",
17263                            onoff(error->transcoder[i].power_domain_on));
17264                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17265                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17266                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17267                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17268                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17269                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17270                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17271         }
17272 }