Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
45         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
46
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
51                                 struct intel_crtc_config *pipe_config);
52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
53                                    struct intel_crtc_config *pipe_config);
54
55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
56                           int x, int y, struct drm_framebuffer *old_fb);
57 static int intel_framebuffer_init(struct drm_device *dev,
58                                   struct intel_framebuffer *ifb,
59                                   struct drm_mode_fb_cmd2 *mode_cmd,
60                                   struct drm_i915_gem_object *obj);
61 static void intel_dp_set_m_n(struct intel_crtc *crtc);
62 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
63 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
64 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
65                                          struct intel_link_m_n *m_n);
66 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
67 static void haswell_set_pipeconf(struct drm_crtc *crtc);
68 static void intel_set_pipe_csc(struct drm_crtc *crtc);
69 static void vlv_prepare_pll(struct intel_crtc *crtc);
70
71 typedef struct {
72         int     min, max;
73 } intel_range_t;
74
75 typedef struct {
76         int     dot_limit;
77         int     p2_slow, p2_fast;
78 } intel_p2_t;
79
80 typedef struct intel_limit intel_limit_t;
81 struct intel_limit {
82         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
83         intel_p2_t          p2;
84 };
85
86 int
87 intel_pch_rawclk(struct drm_device *dev)
88 {
89         struct drm_i915_private *dev_priv = dev->dev_private;
90
91         WARN_ON(!HAS_PCH_SPLIT(dev));
92
93         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
94 }
95
96 static inline u32 /* units of 100MHz */
97 intel_fdi_link_freq(struct drm_device *dev)
98 {
99         if (IS_GEN5(dev)) {
100                 struct drm_i915_private *dev_priv = dev->dev_private;
101                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102         } else
103                 return 27;
104 }
105
106 static const intel_limit_t intel_limits_i8xx_dac = {
107         .dot = { .min = 25000, .max = 350000 },
108         .vco = { .min = 908000, .max = 1512000 },
109         .n = { .min = 2, .max = 16 },
110         .m = { .min = 96, .max = 140 },
111         .m1 = { .min = 18, .max = 26 },
112         .m2 = { .min = 6, .max = 16 },
113         .p = { .min = 4, .max = 128 },
114         .p1 = { .min = 2, .max = 33 },
115         .p2 = { .dot_limit = 165000,
116                 .p2_slow = 4, .p2_fast = 2 },
117 };
118
119 static const intel_limit_t intel_limits_i8xx_dvo = {
120         .dot = { .min = 25000, .max = 350000 },
121         .vco = { .min = 908000, .max = 1512000 },
122         .n = { .min = 2, .max = 16 },
123         .m = { .min = 96, .max = 140 },
124         .m1 = { .min = 18, .max = 26 },
125         .m2 = { .min = 6, .max = 16 },
126         .p = { .min = 4, .max = 128 },
127         .p1 = { .min = 2, .max = 33 },
128         .p2 = { .dot_limit = 165000,
129                 .p2_slow = 4, .p2_fast = 4 },
130 };
131
132 static const intel_limit_t intel_limits_i8xx_lvds = {
133         .dot = { .min = 25000, .max = 350000 },
134         .vco = { .min = 908000, .max = 1512000 },
135         .n = { .min = 2, .max = 16 },
136         .m = { .min = 96, .max = 140 },
137         .m1 = { .min = 18, .max = 26 },
138         .m2 = { .min = 6, .max = 16 },
139         .p = { .min = 4, .max = 128 },
140         .p1 = { .min = 1, .max = 6 },
141         .p2 = { .dot_limit = 165000,
142                 .p2_slow = 14, .p2_fast = 7 },
143 };
144
145 static const intel_limit_t intel_limits_i9xx_sdvo = {
146         .dot = { .min = 20000, .max = 400000 },
147         .vco = { .min = 1400000, .max = 2800000 },
148         .n = { .min = 1, .max = 6 },
149         .m = { .min = 70, .max = 120 },
150         .m1 = { .min = 8, .max = 18 },
151         .m2 = { .min = 3, .max = 7 },
152         .p = { .min = 5, .max = 80 },
153         .p1 = { .min = 1, .max = 8 },
154         .p2 = { .dot_limit = 200000,
155                 .p2_slow = 10, .p2_fast = 5 },
156 };
157
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159         .dot = { .min = 20000, .max = 400000 },
160         .vco = { .min = 1400000, .max = 2800000 },
161         .n = { .min = 1, .max = 6 },
162         .m = { .min = 70, .max = 120 },
163         .m1 = { .min = 8, .max = 18 },
164         .m2 = { .min = 3, .max = 7 },
165         .p = { .min = 7, .max = 98 },
166         .p1 = { .min = 1, .max = 8 },
167         .p2 = { .dot_limit = 112000,
168                 .p2_slow = 14, .p2_fast = 7 },
169 };
170
171
172 static const intel_limit_t intel_limits_g4x_sdvo = {
173         .dot = { .min = 25000, .max = 270000 },
174         .vco = { .min = 1750000, .max = 3500000},
175         .n = { .min = 1, .max = 4 },
176         .m = { .min = 104, .max = 138 },
177         .m1 = { .min = 17, .max = 23 },
178         .m2 = { .min = 5, .max = 11 },
179         .p = { .min = 10, .max = 30 },
180         .p1 = { .min = 1, .max = 3},
181         .p2 = { .dot_limit = 270000,
182                 .p2_slow = 10,
183                 .p2_fast = 10
184         },
185 };
186
187 static const intel_limit_t intel_limits_g4x_hdmi = {
188         .dot = { .min = 22000, .max = 400000 },
189         .vco = { .min = 1750000, .max = 3500000},
190         .n = { .min = 1, .max = 4 },
191         .m = { .min = 104, .max = 138 },
192         .m1 = { .min = 16, .max = 23 },
193         .m2 = { .min = 5, .max = 11 },
194         .p = { .min = 5, .max = 80 },
195         .p1 = { .min = 1, .max = 8},
196         .p2 = { .dot_limit = 165000,
197                 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
201         .dot = { .min = 20000, .max = 115000 },
202         .vco = { .min = 1750000, .max = 3500000 },
203         .n = { .min = 1, .max = 3 },
204         .m = { .min = 104, .max = 138 },
205         .m1 = { .min = 17, .max = 23 },
206         .m2 = { .min = 5, .max = 11 },
207         .p = { .min = 28, .max = 112 },
208         .p1 = { .min = 2, .max = 8 },
209         .p2 = { .dot_limit = 0,
210                 .p2_slow = 14, .p2_fast = 14
211         },
212 };
213
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
215         .dot = { .min = 80000, .max = 224000 },
216         .vco = { .min = 1750000, .max = 3500000 },
217         .n = { .min = 1, .max = 3 },
218         .m = { .min = 104, .max = 138 },
219         .m1 = { .min = 17, .max = 23 },
220         .m2 = { .min = 5, .max = 11 },
221         .p = { .min = 14, .max = 42 },
222         .p1 = { .min = 2, .max = 6 },
223         .p2 = { .dot_limit = 0,
224                 .p2_slow = 7, .p2_fast = 7
225         },
226 };
227
228 static const intel_limit_t intel_limits_pineview_sdvo = {
229         .dot = { .min = 20000, .max = 400000},
230         .vco = { .min = 1700000, .max = 3500000 },
231         /* Pineview's Ncounter is a ring counter */
232         .n = { .min = 3, .max = 6 },
233         .m = { .min = 2, .max = 256 },
234         /* Pineview only has one combined m divider, which we treat as m2. */
235         .m1 = { .min = 0, .max = 0 },
236         .m2 = { .min = 0, .max = 254 },
237         .p = { .min = 5, .max = 80 },
238         .p1 = { .min = 1, .max = 8 },
239         .p2 = { .dot_limit = 200000,
240                 .p2_slow = 10, .p2_fast = 5 },
241 };
242
243 static const intel_limit_t intel_limits_pineview_lvds = {
244         .dot = { .min = 20000, .max = 400000 },
245         .vco = { .min = 1700000, .max = 3500000 },
246         .n = { .min = 3, .max = 6 },
247         .m = { .min = 2, .max = 256 },
248         .m1 = { .min = 0, .max = 0 },
249         .m2 = { .min = 0, .max = 254 },
250         .p = { .min = 7, .max = 112 },
251         .p1 = { .min = 1, .max = 8 },
252         .p2 = { .dot_limit = 112000,
253                 .p2_slow = 14, .p2_fast = 14 },
254 };
255
256 /* Ironlake / Sandybridge
257  *
258  * We calculate clock using (register_value + 2) for N/M1/M2, so here
259  * the range value for them is (actual_value - 2).
260  */
261 static const intel_limit_t intel_limits_ironlake_dac = {
262         .dot = { .min = 25000, .max = 350000 },
263         .vco = { .min = 1760000, .max = 3510000 },
264         .n = { .min = 1, .max = 5 },
265         .m = { .min = 79, .max = 127 },
266         .m1 = { .min = 12, .max = 22 },
267         .m2 = { .min = 5, .max = 9 },
268         .p = { .min = 5, .max = 80 },
269         .p1 = { .min = 1, .max = 8 },
270         .p2 = { .dot_limit = 225000,
271                 .p2_slow = 10, .p2_fast = 5 },
272 };
273
274 static const intel_limit_t intel_limits_ironlake_single_lvds = {
275         .dot = { .min = 25000, .max = 350000 },
276         .vco = { .min = 1760000, .max = 3510000 },
277         .n = { .min = 1, .max = 3 },
278         .m = { .min = 79, .max = 118 },
279         .m1 = { .min = 12, .max = 22 },
280         .m2 = { .min = 5, .max = 9 },
281         .p = { .min = 28, .max = 112 },
282         .p1 = { .min = 2, .max = 8 },
283         .p2 = { .dot_limit = 225000,
284                 .p2_slow = 14, .p2_fast = 14 },
285 };
286
287 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
288         .dot = { .min = 25000, .max = 350000 },
289         .vco = { .min = 1760000, .max = 3510000 },
290         .n = { .min = 1, .max = 3 },
291         .m = { .min = 79, .max = 127 },
292         .m1 = { .min = 12, .max = 22 },
293         .m2 = { .min = 5, .max = 9 },
294         .p = { .min = 14, .max = 56 },
295         .p1 = { .min = 2, .max = 8 },
296         .p2 = { .dot_limit = 225000,
297                 .p2_slow = 7, .p2_fast = 7 },
298 };
299
300 /* LVDS 100mhz refclk limits. */
301 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
302         .dot = { .min = 25000, .max = 350000 },
303         .vco = { .min = 1760000, .max = 3510000 },
304         .n = { .min = 1, .max = 2 },
305         .m = { .min = 79, .max = 126 },
306         .m1 = { .min = 12, .max = 22 },
307         .m2 = { .min = 5, .max = 9 },
308         .p = { .min = 28, .max = 112 },
309         .p1 = { .min = 2, .max = 8 },
310         .p2 = { .dot_limit = 225000,
311                 .p2_slow = 14, .p2_fast = 14 },
312 };
313
314 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
315         .dot = { .min = 25000, .max = 350000 },
316         .vco = { .min = 1760000, .max = 3510000 },
317         .n = { .min = 1, .max = 3 },
318         .m = { .min = 79, .max = 126 },
319         .m1 = { .min = 12, .max = 22 },
320         .m2 = { .min = 5, .max = 9 },
321         .p = { .min = 14, .max = 42 },
322         .p1 = { .min = 2, .max = 6 },
323         .p2 = { .dot_limit = 225000,
324                 .p2_slow = 7, .p2_fast = 7 },
325 };
326
327 static const intel_limit_t intel_limits_vlv = {
328          /*
329           * These are the data rate limits (measured in fast clocks)
330           * since those are the strictest limits we have. The fast
331           * clock and actual rate limits are more relaxed, so checking
332           * them would make no difference.
333           */
334         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
335         .vco = { .min = 4000000, .max = 6000000 },
336         .n = { .min = 1, .max = 7 },
337         .m1 = { .min = 2, .max = 3 },
338         .m2 = { .min = 11, .max = 156 },
339         .p1 = { .min = 2, .max = 3 },
340         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
341 };
342
343 static const intel_limit_t intel_limits_chv = {
344         /*
345          * These are the data rate limits (measured in fast clocks)
346          * since those are the strictest limits we have.  The fast
347          * clock and actual rate limits are more relaxed, so checking
348          * them would make no difference.
349          */
350         .dot = { .min = 25000 * 5, .max = 540000 * 5},
351         .vco = { .min = 4860000, .max = 6700000 },
352         .n = { .min = 1, .max = 1 },
353         .m1 = { .min = 2, .max = 2 },
354         .m2 = { .min = 24 << 22, .max = 175 << 22 },
355         .p1 = { .min = 2, .max = 4 },
356         .p2 = { .p2_slow = 1, .p2_fast = 14 },
357 };
358
359 static void vlv_clock(int refclk, intel_clock_t *clock)
360 {
361         clock->m = clock->m1 * clock->m2;
362         clock->p = clock->p1 * clock->p2;
363         if (WARN_ON(clock->n == 0 || clock->p == 0))
364                 return;
365         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
366         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
367 }
368
369 /**
370  * Returns whether any output on the specified pipe is of the specified type
371  */
372 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
373 {
374         struct drm_device *dev = crtc->dev;
375         struct intel_encoder *encoder;
376
377         for_each_encoder_on_crtc(dev, crtc, encoder)
378                 if (encoder->type == type)
379                         return true;
380
381         return false;
382 }
383
384 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
385                                                 int refclk)
386 {
387         struct drm_device *dev = crtc->dev;
388         const intel_limit_t *limit;
389
390         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
391                 if (intel_is_dual_link_lvds(dev)) {
392                         if (refclk == 100000)
393                                 limit = &intel_limits_ironlake_dual_lvds_100m;
394                         else
395                                 limit = &intel_limits_ironlake_dual_lvds;
396                 } else {
397                         if (refclk == 100000)
398                                 limit = &intel_limits_ironlake_single_lvds_100m;
399                         else
400                                 limit = &intel_limits_ironlake_single_lvds;
401                 }
402         } else
403                 limit = &intel_limits_ironlake_dac;
404
405         return limit;
406 }
407
408 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
409 {
410         struct drm_device *dev = crtc->dev;
411         const intel_limit_t *limit;
412
413         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
414                 if (intel_is_dual_link_lvds(dev))
415                         limit = &intel_limits_g4x_dual_channel_lvds;
416                 else
417                         limit = &intel_limits_g4x_single_channel_lvds;
418         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
419                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
420                 limit = &intel_limits_g4x_hdmi;
421         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
422                 limit = &intel_limits_g4x_sdvo;
423         } else /* The option is for other outputs */
424                 limit = &intel_limits_i9xx_sdvo;
425
426         return limit;
427 }
428
429 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
430 {
431         struct drm_device *dev = crtc->dev;
432         const intel_limit_t *limit;
433
434         if (HAS_PCH_SPLIT(dev))
435                 limit = intel_ironlake_limit(crtc, refclk);
436         else if (IS_G4X(dev)) {
437                 limit = intel_g4x_limit(crtc);
438         } else if (IS_PINEVIEW(dev)) {
439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
440                         limit = &intel_limits_pineview_lvds;
441                 else
442                         limit = &intel_limits_pineview_sdvo;
443         } else if (IS_CHERRYVIEW(dev)) {
444                 limit = &intel_limits_chv;
445         } else if (IS_VALLEYVIEW(dev)) {
446                 limit = &intel_limits_vlv;
447         } else if (!IS_GEN2(dev)) {
448                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
449                         limit = &intel_limits_i9xx_lvds;
450                 else
451                         limit = &intel_limits_i9xx_sdvo;
452         } else {
453                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
454                         limit = &intel_limits_i8xx_lvds;
455                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
456                         limit = &intel_limits_i8xx_dvo;
457                 else
458                         limit = &intel_limits_i8xx_dac;
459         }
460         return limit;
461 }
462
463 /* m1 is reserved as 0 in Pineview, n is a ring counter */
464 static void pineview_clock(int refclk, intel_clock_t *clock)
465 {
466         clock->m = clock->m2 + 2;
467         clock->p = clock->p1 * clock->p2;
468         if (WARN_ON(clock->n == 0 || clock->p == 0))
469                 return;
470         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
471         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
472 }
473
474 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
475 {
476         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
477 }
478
479 static void i9xx_clock(int refclk, intel_clock_t *clock)
480 {
481         clock->m = i9xx_dpll_compute_m(clock);
482         clock->p = clock->p1 * clock->p2;
483         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
484                 return;
485         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
486         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
487 }
488
489 static void chv_clock(int refclk, intel_clock_t *clock)
490 {
491         clock->m = clock->m1 * clock->m2;
492         clock->p = clock->p1 * clock->p2;
493         if (WARN_ON(clock->n == 0 || clock->p == 0))
494                 return;
495         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
496                         clock->n << 22);
497         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
498 }
499
500 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
501 /**
502  * Returns whether the given set of divisors are valid for a given refclk with
503  * the given connectors.
504  */
505
506 static bool intel_PLL_is_valid(struct drm_device *dev,
507                                const intel_limit_t *limit,
508                                const intel_clock_t *clock)
509 {
510         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
511                 INTELPllInvalid("n out of range\n");
512         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
513                 INTELPllInvalid("p1 out of range\n");
514         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
515                 INTELPllInvalid("m2 out of range\n");
516         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
517                 INTELPllInvalid("m1 out of range\n");
518
519         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
520                 if (clock->m1 <= clock->m2)
521                         INTELPllInvalid("m1 <= m2\n");
522
523         if (!IS_VALLEYVIEW(dev)) {
524                 if (clock->p < limit->p.min || limit->p.max < clock->p)
525                         INTELPllInvalid("p out of range\n");
526                 if (clock->m < limit->m.min || limit->m.max < clock->m)
527                         INTELPllInvalid("m out of range\n");
528         }
529
530         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
531                 INTELPllInvalid("vco out of range\n");
532         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
533          * connector, etc., rather than just a single range.
534          */
535         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
536                 INTELPllInvalid("dot out of range\n");
537
538         return true;
539 }
540
541 static bool
542 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
543                     int target, int refclk, intel_clock_t *match_clock,
544                     intel_clock_t *best_clock)
545 {
546         struct drm_device *dev = crtc->dev;
547         intel_clock_t clock;
548         int err = target;
549
550         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
551                 /*
552                  * For LVDS just rely on its current settings for dual-channel.
553                  * We haven't figured out how to reliably set up different
554                  * single/dual channel state, if we even can.
555                  */
556                 if (intel_is_dual_link_lvds(dev))
557                         clock.p2 = limit->p2.p2_fast;
558                 else
559                         clock.p2 = limit->p2.p2_slow;
560         } else {
561                 if (target < limit->p2.dot_limit)
562                         clock.p2 = limit->p2.p2_slow;
563                 else
564                         clock.p2 = limit->p2.p2_fast;
565         }
566
567         memset(best_clock, 0, sizeof(*best_clock));
568
569         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
570              clock.m1++) {
571                 for (clock.m2 = limit->m2.min;
572                      clock.m2 <= limit->m2.max; clock.m2++) {
573                         if (clock.m2 >= clock.m1)
574                                 break;
575                         for (clock.n = limit->n.min;
576                              clock.n <= limit->n.max; clock.n++) {
577                                 for (clock.p1 = limit->p1.min;
578                                         clock.p1 <= limit->p1.max; clock.p1++) {
579                                         int this_err;
580
581                                         i9xx_clock(refclk, &clock);
582                                         if (!intel_PLL_is_valid(dev, limit,
583                                                                 &clock))
584                                                 continue;
585                                         if (match_clock &&
586                                             clock.p != match_clock->p)
587                                                 continue;
588
589                                         this_err = abs(clock.dot - target);
590                                         if (this_err < err) {
591                                                 *best_clock = clock;
592                                                 err = this_err;
593                                         }
594                                 }
595                         }
596                 }
597         }
598
599         return (err != target);
600 }
601
602 static bool
603 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
604                    int target, int refclk, intel_clock_t *match_clock,
605                    intel_clock_t *best_clock)
606 {
607         struct drm_device *dev = crtc->dev;
608         intel_clock_t clock;
609         int err = target;
610
611         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
612                 /*
613                  * For LVDS just rely on its current settings for dual-channel.
614                  * We haven't figured out how to reliably set up different
615                  * single/dual channel state, if we even can.
616                  */
617                 if (intel_is_dual_link_lvds(dev))
618                         clock.p2 = limit->p2.p2_fast;
619                 else
620                         clock.p2 = limit->p2.p2_slow;
621         } else {
622                 if (target < limit->p2.dot_limit)
623                         clock.p2 = limit->p2.p2_slow;
624                 else
625                         clock.p2 = limit->p2.p2_fast;
626         }
627
628         memset(best_clock, 0, sizeof(*best_clock));
629
630         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631              clock.m1++) {
632                 for (clock.m2 = limit->m2.min;
633                      clock.m2 <= limit->m2.max; clock.m2++) {
634                         for (clock.n = limit->n.min;
635                              clock.n <= limit->n.max; clock.n++) {
636                                 for (clock.p1 = limit->p1.min;
637                                         clock.p1 <= limit->p1.max; clock.p1++) {
638                                         int this_err;
639
640                                         pineview_clock(refclk, &clock);
641                                         if (!intel_PLL_is_valid(dev, limit,
642                                                                 &clock))
643                                                 continue;
644                                         if (match_clock &&
645                                             clock.p != match_clock->p)
646                                                 continue;
647
648                                         this_err = abs(clock.dot - target);
649                                         if (this_err < err) {
650                                                 *best_clock = clock;
651                                                 err = this_err;
652                                         }
653                                 }
654                         }
655                 }
656         }
657
658         return (err != target);
659 }
660
661 static bool
662 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
663                    int target, int refclk, intel_clock_t *match_clock,
664                    intel_clock_t *best_clock)
665 {
666         struct drm_device *dev = crtc->dev;
667         intel_clock_t clock;
668         int max_n;
669         bool found;
670         /* approximately equals target * 0.00585 */
671         int err_most = (target >> 8) + (target >> 9);
672         found = false;
673
674         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
675                 if (intel_is_dual_link_lvds(dev))
676                         clock.p2 = limit->p2.p2_fast;
677                 else
678                         clock.p2 = limit->p2.p2_slow;
679         } else {
680                 if (target < limit->p2.dot_limit)
681                         clock.p2 = limit->p2.p2_slow;
682                 else
683                         clock.p2 = limit->p2.p2_fast;
684         }
685
686         memset(best_clock, 0, sizeof(*best_clock));
687         max_n = limit->n.max;
688         /* based on hardware requirement, prefer smaller n to precision */
689         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
690                 /* based on hardware requirement, prefere larger m1,m2 */
691                 for (clock.m1 = limit->m1.max;
692                      clock.m1 >= limit->m1.min; clock.m1--) {
693                         for (clock.m2 = limit->m2.max;
694                              clock.m2 >= limit->m2.min; clock.m2--) {
695                                 for (clock.p1 = limit->p1.max;
696                                      clock.p1 >= limit->p1.min; clock.p1--) {
697                                         int this_err;
698
699                                         i9xx_clock(refclk, &clock);
700                                         if (!intel_PLL_is_valid(dev, limit,
701                                                                 &clock))
702                                                 continue;
703
704                                         this_err = abs(clock.dot - target);
705                                         if (this_err < err_most) {
706                                                 *best_clock = clock;
707                                                 err_most = this_err;
708                                                 max_n = clock.n;
709                                                 found = true;
710                                         }
711                                 }
712                         }
713                 }
714         }
715         return found;
716 }
717
718 static bool
719 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
720                    int target, int refclk, intel_clock_t *match_clock,
721                    intel_clock_t *best_clock)
722 {
723         struct drm_device *dev = crtc->dev;
724         intel_clock_t clock;
725         unsigned int bestppm = 1000000;
726         /* min update 19.2 MHz */
727         int max_n = min(limit->n.max, refclk / 19200);
728         bool found = false;
729
730         target *= 5; /* fast clock */
731
732         memset(best_clock, 0, sizeof(*best_clock));
733
734         /* based on hardware requirement, prefer smaller n to precision */
735         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
736                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
737                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
738                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
739                                 clock.p = clock.p1 * clock.p2;
740                                 /* based on hardware requirement, prefer bigger m1,m2 values */
741                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
742                                         unsigned int ppm, diff;
743
744                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
745                                                                      refclk * clock.m1);
746
747                                         vlv_clock(refclk, &clock);
748
749                                         if (!intel_PLL_is_valid(dev, limit,
750                                                                 &clock))
751                                                 continue;
752
753                                         diff = abs(clock.dot - target);
754                                         ppm = div_u64(1000000ULL * diff, target);
755
756                                         if (ppm < 100 && clock.p > best_clock->p) {
757                                                 bestppm = 0;
758                                                 *best_clock = clock;
759                                                 found = true;
760                                         }
761
762                                         if (bestppm >= 10 && ppm < bestppm - 10) {
763                                                 bestppm = ppm;
764                                                 *best_clock = clock;
765                                                 found = true;
766                                         }
767                                 }
768                         }
769                 }
770         }
771
772         return found;
773 }
774
775 static bool
776 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
777                    int target, int refclk, intel_clock_t *match_clock,
778                    intel_clock_t *best_clock)
779 {
780         struct drm_device *dev = crtc->dev;
781         intel_clock_t clock;
782         uint64_t m2;
783         int found = false;
784
785         memset(best_clock, 0, sizeof(*best_clock));
786
787         /*
788          * Based on hardware doc, the n always set to 1, and m1 always
789          * set to 2.  If requires to support 200Mhz refclk, we need to
790          * revisit this because n may not 1 anymore.
791          */
792         clock.n = 1, clock.m1 = 2;
793         target *= 5;    /* fast clock */
794
795         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
796                 for (clock.p2 = limit->p2.p2_fast;
797                                 clock.p2 >= limit->p2.p2_slow;
798                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799
800                         clock.p = clock.p1 * clock.p2;
801
802                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
803                                         clock.n) << 22, refclk * clock.m1);
804
805                         if (m2 > INT_MAX/clock.m1)
806                                 continue;
807
808                         clock.m2 = m2;
809
810                         chv_clock(refclk, &clock);
811
812                         if (!intel_PLL_is_valid(dev, limit, &clock))
813                                 continue;
814
815                         /* based on hardware requirement, prefer bigger p
816                          */
817                         if (clock.p > best_clock->p) {
818                                 *best_clock = clock;
819                                 found = true;
820                         }
821                 }
822         }
823
824         return found;
825 }
826
827 bool intel_crtc_active(struct drm_crtc *crtc)
828 {
829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
830
831         /* Be paranoid as we can arrive here with only partial
832          * state retrieved from the hardware during setup.
833          *
834          * We can ditch the adjusted_mode.crtc_clock check as soon
835          * as Haswell has gained clock readout/fastboot support.
836          *
837          * We can ditch the crtc->primary->fb check as soon as we can
838          * properly reconstruct framebuffers.
839          */
840         return intel_crtc->active && crtc->primary->fb &&
841                 intel_crtc->config.adjusted_mode.crtc_clock;
842 }
843
844 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
845                                              enum pipe pipe)
846 {
847         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
849
850         return intel_crtc->config.cpu_transcoder;
851 }
852
853 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
854 {
855         struct drm_i915_private *dev_priv = dev->dev_private;
856         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
857
858         frame = I915_READ(frame_reg);
859
860         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
861                 WARN(1, "vblank wait timed out\n");
862 }
863
864 /**
865  * intel_wait_for_vblank - wait for vblank on a given pipe
866  * @dev: drm device
867  * @pipe: pipe to wait for
868  *
869  * Wait for vblank to occur on a given pipe.  Needed for various bits of
870  * mode setting code.
871  */
872 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
873 {
874         struct drm_i915_private *dev_priv = dev->dev_private;
875         int pipestat_reg = PIPESTAT(pipe);
876
877         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
878                 g4x_wait_for_vblank(dev, pipe);
879                 return;
880         }
881
882         /* Clear existing vblank status. Note this will clear any other
883          * sticky status fields as well.
884          *
885          * This races with i915_driver_irq_handler() with the result
886          * that either function could miss a vblank event.  Here it is not
887          * fatal, as we will either wait upon the next vblank interrupt or
888          * timeout.  Generally speaking intel_wait_for_vblank() is only
889          * called during modeset at which time the GPU should be idle and
890          * should *not* be performing page flips and thus not waiting on
891          * vblanks...
892          * Currently, the result of us stealing a vblank from the irq
893          * handler is that a single frame will be skipped during swapbuffers.
894          */
895         I915_WRITE(pipestat_reg,
896                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
897
898         /* Wait for vblank interrupt bit to set */
899         if (wait_for(I915_READ(pipestat_reg) &
900                      PIPE_VBLANK_INTERRUPT_STATUS,
901                      50))
902                 DRM_DEBUG_KMS("vblank wait timed out\n");
903 }
904
905 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
906 {
907         struct drm_i915_private *dev_priv = dev->dev_private;
908         u32 reg = PIPEDSL(pipe);
909         u32 line1, line2;
910         u32 line_mask;
911
912         if (IS_GEN2(dev))
913                 line_mask = DSL_LINEMASK_GEN2;
914         else
915                 line_mask = DSL_LINEMASK_GEN3;
916
917         line1 = I915_READ(reg) & line_mask;
918         mdelay(5);
919         line2 = I915_READ(reg) & line_mask;
920
921         return line1 == line2;
922 }
923
924 /*
925  * intel_wait_for_pipe_off - wait for pipe to turn off
926  * @dev: drm device
927  * @pipe: pipe to wait for
928  *
929  * After disabling a pipe, we can't wait for vblank in the usual way,
930  * spinning on the vblank interrupt status bit, since we won't actually
931  * see an interrupt when the pipe is disabled.
932  *
933  * On Gen4 and above:
934  *   wait for the pipe register state bit to turn off
935  *
936  * Otherwise:
937  *   wait for the display line value to settle (it usually
938  *   ends up stopping at the start of the next frame).
939  *
940  */
941 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
942 {
943         struct drm_i915_private *dev_priv = dev->dev_private;
944         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
945                                                                       pipe);
946
947         if (INTEL_INFO(dev)->gen >= 4) {
948                 int reg = PIPECONF(cpu_transcoder);
949
950                 /* Wait for the Pipe State to go off */
951                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
952                              100))
953                         WARN(1, "pipe_off wait timed out\n");
954         } else {
955                 /* Wait for the display line to settle */
956                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
957                         WARN(1, "pipe_off wait timed out\n");
958         }
959 }
960
961 /*
962  * ibx_digital_port_connected - is the specified port connected?
963  * @dev_priv: i915 private structure
964  * @port: the port to test
965  *
966  * Returns true if @port is connected, false otherwise.
967  */
968 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
969                                 struct intel_digital_port *port)
970 {
971         u32 bit;
972
973         if (HAS_PCH_IBX(dev_priv->dev)) {
974                 switch (port->port) {
975                 case PORT_B:
976                         bit = SDE_PORTB_HOTPLUG;
977                         break;
978                 case PORT_C:
979                         bit = SDE_PORTC_HOTPLUG;
980                         break;
981                 case PORT_D:
982                         bit = SDE_PORTD_HOTPLUG;
983                         break;
984                 default:
985                         return true;
986                 }
987         } else {
988                 switch (port->port) {
989                 case PORT_B:
990                         bit = SDE_PORTB_HOTPLUG_CPT;
991                         break;
992                 case PORT_C:
993                         bit = SDE_PORTC_HOTPLUG_CPT;
994                         break;
995                 case PORT_D:
996                         bit = SDE_PORTD_HOTPLUG_CPT;
997                         break;
998                 default:
999                         return true;
1000                 }
1001         }
1002
1003         return I915_READ(SDEISR) & bit;
1004 }
1005
1006 static const char *state_string(bool enabled)
1007 {
1008         return enabled ? "on" : "off";
1009 }
1010
1011 /* Only for pre-ILK configs */
1012 void assert_pll(struct drm_i915_private *dev_priv,
1013                 enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = DPLL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & DPLL_VCO_ENABLE);
1022         WARN(cur_state != state,
1023              "PLL state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026
1027 /* XXX: the dsi pll is shared between MIPI DSI ports */
1028 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1029 {
1030         u32 val;
1031         bool cur_state;
1032
1033         mutex_lock(&dev_priv->dpio_lock);
1034         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1035         mutex_unlock(&dev_priv->dpio_lock);
1036
1037         cur_state = val & DSI_PLL_VCO_EN;
1038         WARN(cur_state != state,
1039              "DSI PLL state assertion failure (expected %s, current %s)\n",
1040              state_string(state), state_string(cur_state));
1041 }
1042 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1043 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1044
1045 struct intel_shared_dpll *
1046 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1047 {
1048         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1049
1050         if (crtc->config.shared_dpll < 0)
1051                 return NULL;
1052
1053         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1054 }
1055
1056 /* For ILK+ */
1057 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1058                         struct intel_shared_dpll *pll,
1059                         bool state)
1060 {
1061         bool cur_state;
1062         struct intel_dpll_hw_state hw_state;
1063
1064         if (HAS_PCH_LPT(dev_priv->dev)) {
1065                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1066                 return;
1067         }
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                                   enum pipe pipe)
1158 {
1159         int pp_reg, lvds_reg;
1160         u32 val;
1161         enum pipe panel_pipe = PIPE_A;
1162         bool locked = true;
1163
1164         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1165                 pp_reg = PCH_PP_CONTROL;
1166                 lvds_reg = PCH_LVDS;
1167         } else {
1168                 pp_reg = PP_CONTROL;
1169                 lvds_reg = LVDS;
1170         }
1171
1172         val = I915_READ(pp_reg);
1173         if (!(val & PANEL_POWER_ON) ||
1174             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1175                 locked = false;
1176
1177         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1178                 panel_pipe = PIPE_B;
1179
1180         WARN(panel_pipe == pipe && locked,
1181              "panel assertion failure, pipe %c regs locked\n",
1182              pipe_name(pipe));
1183 }
1184
1185 static void assert_cursor(struct drm_i915_private *dev_priv,
1186                           enum pipe pipe, bool state)
1187 {
1188         struct drm_device *dev = dev_priv->dev;
1189         bool cur_state;
1190
1191         if (IS_845G(dev) || IS_I865G(dev))
1192                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1193         else
1194                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1195
1196         WARN(cur_state != state,
1197              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1198              pipe_name(pipe), state_string(state), state_string(cur_state));
1199 }
1200 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1201 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1202
1203 void assert_pipe(struct drm_i915_private *dev_priv,
1204                  enum pipe pipe, bool state)
1205 {
1206         int reg;
1207         u32 val;
1208         bool cur_state;
1209         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1210                                                                       pipe);
1211
1212         /* if we need the pipe A quirk it must be always on */
1213         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1214                 state = true;
1215
1216         if (!intel_display_power_enabled(dev_priv,
1217                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1218                 cur_state = false;
1219         } else {
1220                 reg = PIPECONF(cpu_transcoder);
1221                 val = I915_READ(reg);
1222                 cur_state = !!(val & PIPECONF_ENABLE);
1223         }
1224
1225         WARN(cur_state != state,
1226              "pipe %c assertion failure (expected %s, current %s)\n",
1227              pipe_name(pipe), state_string(state), state_string(cur_state));
1228 }
1229
1230 static void assert_plane(struct drm_i915_private *dev_priv,
1231                          enum plane plane, bool state)
1232 {
1233         int reg;
1234         u32 val;
1235         bool cur_state;
1236
1237         reg = DSPCNTR(plane);
1238         val = I915_READ(reg);
1239         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1240         WARN(cur_state != state,
1241              "plane %c assertion failure (expected %s, current %s)\n",
1242              plane_name(plane), state_string(state), state_string(cur_state));
1243 }
1244
1245 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1246 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1247
1248 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1249                                    enum pipe pipe)
1250 {
1251         struct drm_device *dev = dev_priv->dev;
1252         int reg, i;
1253         u32 val;
1254         int cur_pipe;
1255
1256         /* Primary planes are fixed to pipes on gen4+ */
1257         if (INTEL_INFO(dev)->gen >= 4) {
1258                 reg = DSPCNTR(pipe);
1259                 val = I915_READ(reg);
1260                 WARN(val & DISPLAY_PLANE_ENABLE,
1261                      "plane %c assertion failure, should be disabled but not\n",
1262                      plane_name(pipe));
1263                 return;
1264         }
1265
1266         /* Need to check both planes against the pipe */
1267         for_each_pipe(i) {
1268                 reg = DSPCNTR(i);
1269                 val = I915_READ(reg);
1270                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271                         DISPPLANE_SEL_PIPE_SHIFT;
1272                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274                      plane_name(i), pipe_name(pipe));
1275         }
1276 }
1277
1278 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279                                     enum pipe pipe)
1280 {
1281         struct drm_device *dev = dev_priv->dev;
1282         int reg, sprite;
1283         u32 val;
1284
1285         if (IS_VALLEYVIEW(dev)) {
1286                 for_each_sprite(pipe, sprite) {
1287                         reg = SPCNTR(pipe, sprite);
1288                         val = I915_READ(reg);
1289                         WARN(val & SP_ENABLE,
1290                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291                              sprite_name(pipe, sprite), pipe_name(pipe));
1292                 }
1293         } else if (INTEL_INFO(dev)->gen >= 7) {
1294                 reg = SPRCTL(pipe);
1295                 val = I915_READ(reg);
1296                 WARN(val & SPRITE_ENABLE,
1297                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1298                      plane_name(pipe), pipe_name(pipe));
1299         } else if (INTEL_INFO(dev)->gen >= 5) {
1300                 reg = DVSCNTR(pipe);
1301                 val = I915_READ(reg);
1302                 WARN(val & DVS_ENABLE,
1303                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1304                      plane_name(pipe), pipe_name(pipe));
1305         }
1306 }
1307
1308 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1309 {
1310         u32 val;
1311         bool enabled;
1312
1313         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1314
1315         val = I915_READ(PCH_DREF_CONTROL);
1316         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1317                             DREF_SUPERSPREAD_SOURCE_MASK));
1318         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1319 }
1320
1321 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322                                            enum pipe pipe)
1323 {
1324         int reg;
1325         u32 val;
1326         bool enabled;
1327
1328         reg = PCH_TRANSCONF(pipe);
1329         val = I915_READ(reg);
1330         enabled = !!(val & TRANS_ENABLE);
1331         WARN(enabled,
1332              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1333              pipe_name(pipe));
1334 }
1335
1336 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1337                             enum pipe pipe, u32 port_sel, u32 val)
1338 {
1339         if ((val & DP_PORT_EN) == 0)
1340                 return false;
1341
1342         if (HAS_PCH_CPT(dev_priv->dev)) {
1343                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1344                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1345                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1346                         return false;
1347         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1348                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1349                         return false;
1350         } else {
1351                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1352                         return false;
1353         }
1354         return true;
1355 }
1356
1357 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1358                               enum pipe pipe, u32 val)
1359 {
1360         if ((val & SDVO_ENABLE) == 0)
1361                 return false;
1362
1363         if (HAS_PCH_CPT(dev_priv->dev)) {
1364                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1365                         return false;
1366         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1367                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1368                         return false;
1369         } else {
1370                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1371                         return false;
1372         }
1373         return true;
1374 }
1375
1376 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1377                               enum pipe pipe, u32 val)
1378 {
1379         if ((val & LVDS_PORT_EN) == 0)
1380                 return false;
1381
1382         if (HAS_PCH_CPT(dev_priv->dev)) {
1383                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1384                         return false;
1385         } else {
1386                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1387                         return false;
1388         }
1389         return true;
1390 }
1391
1392 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1393                               enum pipe pipe, u32 val)
1394 {
1395         if ((val & ADPA_DAC_ENABLE) == 0)
1396                 return false;
1397         if (HAS_PCH_CPT(dev_priv->dev)) {
1398                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1399                         return false;
1400         } else {
1401                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1402                         return false;
1403         }
1404         return true;
1405 }
1406
1407 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1408                                    enum pipe pipe, int reg, u32 port_sel)
1409 {
1410         u32 val = I915_READ(reg);
1411         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1412              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1413              reg, pipe_name(pipe));
1414
1415         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1416              && (val & DP_PIPEB_SELECT),
1417              "IBX PCH dp port still using transcoder B\n");
1418 }
1419
1420 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1421                                      enum pipe pipe, int reg)
1422 {
1423         u32 val = I915_READ(reg);
1424         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1425              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1426              reg, pipe_name(pipe));
1427
1428         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1429              && (val & SDVO_PIPE_B_SELECT),
1430              "IBX PCH hdmi port still using transcoder B\n");
1431 }
1432
1433 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1434                                       enum pipe pipe)
1435 {
1436         int reg;
1437         u32 val;
1438
1439         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1440         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1441         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1442
1443         reg = PCH_ADPA;
1444         val = I915_READ(reg);
1445         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1446              "PCH VGA enabled on transcoder %c, should be disabled\n",
1447              pipe_name(pipe));
1448
1449         reg = PCH_LVDS;
1450         val = I915_READ(reg);
1451         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1452              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1453              pipe_name(pipe));
1454
1455         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1456         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1457         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1458 }
1459
1460 static void intel_init_dpio(struct drm_device *dev)
1461 {
1462         struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464         if (!IS_VALLEYVIEW(dev))
1465                 return;
1466
1467         /*
1468          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1469          * CHV x1 PHY (DP/HDMI D)
1470          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1471          */
1472         if (IS_CHERRYVIEW(dev)) {
1473                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1474                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1475         } else {
1476                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1477         }
1478 }
1479
1480 static void intel_reset_dpio(struct drm_device *dev)
1481 {
1482         struct drm_i915_private *dev_priv = dev->dev_private;
1483
1484         if (!IS_VALLEYVIEW(dev))
1485                 return;
1486
1487         if (IS_CHERRYVIEW(dev)) {
1488                 enum dpio_phy phy;
1489                 u32 val;
1490
1491                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1492                         /* Poll for phypwrgood signal */
1493                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1494                                                 PHY_POWERGOOD(phy), 1))
1495                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1496
1497                         /*
1498                          * Deassert common lane reset for PHY.
1499                          *
1500                          * This should only be done on init and resume from S3
1501                          * with both PLLs disabled, or we risk losing DPIO and
1502                          * PLL synchronization.
1503                          */
1504                         val = I915_READ(DISPLAY_PHY_CONTROL);
1505                         I915_WRITE(DISPLAY_PHY_CONTROL,
1506                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1507                 }
1508
1509         } else {
1510                 /*
1511                  * If DPIO has already been reset, e.g. by BIOS, just skip all
1512                  * this.
1513                  */
1514                 if (I915_READ(DPIO_CTL) & DPIO_CMNRST)
1515                         return;
1516
1517                 /*
1518                  * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1519                  * Need to assert and de-assert PHY SB reset by gating the
1520                  * common lane power, then un-gating it.
1521                  * Simply ungating isn't enough to reset the PHY enough to get
1522                  * ports and lanes running.
1523                  */
1524                 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1525                                      false);
1526                 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1527                                      true);
1528         }
1529 }
1530
1531 static void vlv_enable_pll(struct intel_crtc *crtc)
1532 {
1533         struct drm_device *dev = crtc->base.dev;
1534         struct drm_i915_private *dev_priv = dev->dev_private;
1535         int reg = DPLL(crtc->pipe);
1536         u32 dpll = crtc->config.dpll_hw_state.dpll;
1537
1538         assert_pipe_disabled(dev_priv, crtc->pipe);
1539
1540         /* No really, not for ILK+ */
1541         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1542
1543         /* PLL is protected by panel, make sure we can write it */
1544         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1545                 assert_panel_unlocked(dev_priv, crtc->pipe);
1546
1547         I915_WRITE(reg, dpll);
1548         POSTING_READ(reg);
1549         udelay(150);
1550
1551         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1552                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1553
1554         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1555         POSTING_READ(DPLL_MD(crtc->pipe));
1556
1557         /* We do this three times for luck */
1558         I915_WRITE(reg, dpll);
1559         POSTING_READ(reg);
1560         udelay(150); /* wait for warmup */
1561         I915_WRITE(reg, dpll);
1562         POSTING_READ(reg);
1563         udelay(150); /* wait for warmup */
1564         I915_WRITE(reg, dpll);
1565         POSTING_READ(reg);
1566         udelay(150); /* wait for warmup */
1567 }
1568
1569 static void chv_enable_pll(struct intel_crtc *crtc)
1570 {
1571         struct drm_device *dev = crtc->base.dev;
1572         struct drm_i915_private *dev_priv = dev->dev_private;
1573         int pipe = crtc->pipe;
1574         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1575         u32 tmp;
1576
1577         assert_pipe_disabled(dev_priv, crtc->pipe);
1578
1579         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1580
1581         mutex_lock(&dev_priv->dpio_lock);
1582
1583         /* Enable back the 10bit clock to display controller */
1584         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1585         tmp |= DPIO_DCLKP_EN;
1586         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1587
1588         /*
1589          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1590          */
1591         udelay(1);
1592
1593         /* Enable PLL */
1594         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1595
1596         /* Check PLL is locked */
1597         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1598                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1599
1600         /* not sure when this should be written */
1601         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1602         POSTING_READ(DPLL_MD(pipe));
1603
1604         mutex_unlock(&dev_priv->dpio_lock);
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_device *dev = crtc->base.dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         int reg = DPLL(crtc->pipe);
1612         u32 dpll = crtc->config.dpll_hw_state.dpll;
1613
1614         assert_pipe_disabled(dev_priv, crtc->pipe);
1615
1616         /* No really, not for ILK+ */
1617         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1618
1619         /* PLL is protected by panel, make sure we can write it */
1620         if (IS_MOBILE(dev) && !IS_I830(dev))
1621                 assert_panel_unlocked(dev_priv, crtc->pipe);
1622
1623         I915_WRITE(reg, dpll);
1624
1625         /* Wait for the clocks to stabilize. */
1626         POSTING_READ(reg);
1627         udelay(150);
1628
1629         if (INTEL_INFO(dev)->gen >= 4) {
1630                 I915_WRITE(DPLL_MD(crtc->pipe),
1631                            crtc->config.dpll_hw_state.dpll_md);
1632         } else {
1633                 /* The pixel multiplier can only be updated once the
1634                  * DPLL is enabled and the clocks are stable.
1635                  *
1636                  * So write it again.
1637                  */
1638                 I915_WRITE(reg, dpll);
1639         }
1640
1641         /* We do this three times for luck */
1642         I915_WRITE(reg, dpll);
1643         POSTING_READ(reg);
1644         udelay(150); /* wait for warmup */
1645         I915_WRITE(reg, dpll);
1646         POSTING_READ(reg);
1647         udelay(150); /* wait for warmup */
1648         I915_WRITE(reg, dpll);
1649         POSTING_READ(reg);
1650         udelay(150); /* wait for warmup */
1651 }
1652
1653 /**
1654  * i9xx_disable_pll - disable a PLL
1655  * @dev_priv: i915 private structure
1656  * @pipe: pipe PLL to disable
1657  *
1658  * Disable the PLL for @pipe, making sure the pipe is off first.
1659  *
1660  * Note!  This is for pre-ILK only.
1661  */
1662 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1663 {
1664         /* Don't disable pipe A or pipe A PLLs if needed */
1665         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1666                 return;
1667
1668         /* Make sure the pipe isn't still relying on us */
1669         assert_pipe_disabled(dev_priv, pipe);
1670
1671         I915_WRITE(DPLL(pipe), 0);
1672         POSTING_READ(DPLL(pipe));
1673 }
1674
1675 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676 {
1677         u32 val = 0;
1678
1679         /* Make sure the pipe isn't still relying on us */
1680         assert_pipe_disabled(dev_priv, pipe);
1681
1682         /*
1683          * Leave integrated clock source and reference clock enabled for pipe B.
1684          * The latter is needed for VGA hotplug / manual detection.
1685          */
1686         if (pipe == PIPE_B)
1687                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1688         I915_WRITE(DPLL(pipe), val);
1689         POSTING_READ(DPLL(pipe));
1690
1691 }
1692
1693 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694 {
1695         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1696         u32 val;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         /* Set PLL en = 0 */
1702         val = DPLL_SSC_REF_CLOCK_CHV;
1703         if (pipe != PIPE_A)
1704                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1705         I915_WRITE(DPLL(pipe), val);
1706         POSTING_READ(DPLL(pipe));
1707
1708         mutex_lock(&dev_priv->dpio_lock);
1709
1710         /* Disable 10bit clock to display controller */
1711         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1712         val &= ~DPIO_DCLKP_EN;
1713         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1714
1715         mutex_unlock(&dev_priv->dpio_lock);
1716 }
1717
1718 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1719                 struct intel_digital_port *dport)
1720 {
1721         u32 port_mask;
1722         int dpll_reg;
1723
1724         switch (dport->port) {
1725         case PORT_B:
1726                 port_mask = DPLL_PORTB_READY_MASK;
1727                 dpll_reg = DPLL(0);
1728                 break;
1729         case PORT_C:
1730                 port_mask = DPLL_PORTC_READY_MASK;
1731                 dpll_reg = DPLL(0);
1732                 break;
1733         case PORT_D:
1734                 port_mask = DPLL_PORTD_READY_MASK;
1735                 dpll_reg = DPIO_PHY_STATUS;
1736                 break;
1737         default:
1738                 BUG();
1739         }
1740
1741         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1742                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1743                      port_name(dport->port), I915_READ(dpll_reg));
1744 }
1745
1746 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1747 {
1748         struct drm_device *dev = crtc->base.dev;
1749         struct drm_i915_private *dev_priv = dev->dev_private;
1750         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1751
1752         WARN_ON(!pll->refcount);
1753         if (pll->active == 0) {
1754                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1755                 WARN_ON(pll->on);
1756                 assert_shared_dpll_disabled(dev_priv, pll);
1757
1758                 pll->mode_set(dev_priv, pll);
1759         }
1760 }
1761
1762 /**
1763  * intel_enable_shared_dpll - enable PCH PLL
1764  * @dev_priv: i915 private structure
1765  * @pipe: pipe PLL to enable
1766  *
1767  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1768  * drives the transcoder clock.
1769  */
1770 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1771 {
1772         struct drm_device *dev = crtc->base.dev;
1773         struct drm_i915_private *dev_priv = dev->dev_private;
1774         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1775
1776         if (WARN_ON(pll == NULL))
1777                 return;
1778
1779         if (WARN_ON(pll->refcount == 0))
1780                 return;
1781
1782         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1783                       pll->name, pll->active, pll->on,
1784                       crtc->base.base.id);
1785
1786         if (pll->active++) {
1787                 WARN_ON(!pll->on);
1788                 assert_shared_dpll_enabled(dev_priv, pll);
1789                 return;
1790         }
1791         WARN_ON(pll->on);
1792
1793         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1794         pll->enable(dev_priv, pll);
1795         pll->on = true;
1796 }
1797
1798 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1799 {
1800         struct drm_device *dev = crtc->base.dev;
1801         struct drm_i915_private *dev_priv = dev->dev_private;
1802         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1803
1804         /* PCH only available on ILK+ */
1805         BUG_ON(INTEL_INFO(dev)->gen < 5);
1806         if (WARN_ON(pll == NULL))
1807                return;
1808
1809         if (WARN_ON(pll->refcount == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (WARN_ON(pll->active == 0)) {
1817                 assert_shared_dpll_disabled(dev_priv, pll);
1818                 return;
1819         }
1820
1821         assert_shared_dpll_enabled(dev_priv, pll);
1822         WARN_ON(!pll->on);
1823         if (--pll->active)
1824                 return;
1825
1826         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1827         pll->disable(dev_priv, pll);
1828         pll->on = false;
1829 }
1830
1831 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1832                                            enum pipe pipe)
1833 {
1834         struct drm_device *dev = dev_priv->dev;
1835         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1836         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1837         uint32_t reg, val, pipeconf_val;
1838
1839         /* PCH only available on ILK+ */
1840         BUG_ON(INTEL_INFO(dev)->gen < 5);
1841
1842         /* Make sure PCH DPLL is enabled */
1843         assert_shared_dpll_enabled(dev_priv,
1844                                    intel_crtc_to_shared_dpll(intel_crtc));
1845
1846         /* FDI must be feeding us bits for PCH ports */
1847         assert_fdi_tx_enabled(dev_priv, pipe);
1848         assert_fdi_rx_enabled(dev_priv, pipe);
1849
1850         if (HAS_PCH_CPT(dev)) {
1851                 /* Workaround: Set the timing override bit before enabling the
1852                  * pch transcoder. */
1853                 reg = TRANS_CHICKEN2(pipe);
1854                 val = I915_READ(reg);
1855                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1856                 I915_WRITE(reg, val);
1857         }
1858
1859         reg = PCH_TRANSCONF(pipe);
1860         val = I915_READ(reg);
1861         pipeconf_val = I915_READ(PIPECONF(pipe));
1862
1863         if (HAS_PCH_IBX(dev_priv->dev)) {
1864                 /*
1865                  * make the BPC in transcoder be consistent with
1866                  * that in pipeconf reg.
1867                  */
1868                 val &= ~PIPECONF_BPC_MASK;
1869                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1870         }
1871
1872         val &= ~TRANS_INTERLACE_MASK;
1873         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1874                 if (HAS_PCH_IBX(dev_priv->dev) &&
1875                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1876                         val |= TRANS_LEGACY_INTERLACED_ILK;
1877                 else
1878                         val |= TRANS_INTERLACED;
1879         else
1880                 val |= TRANS_PROGRESSIVE;
1881
1882         I915_WRITE(reg, val | TRANS_ENABLE);
1883         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1884                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1885 }
1886
1887 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1888                                       enum transcoder cpu_transcoder)
1889 {
1890         u32 val, pipeconf_val;
1891
1892         /* PCH only available on ILK+ */
1893         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1894
1895         /* FDI must be feeding us bits for PCH ports */
1896         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1897         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1898
1899         /* Workaround: set timing override bit. */
1900         val = I915_READ(_TRANSA_CHICKEN2);
1901         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1902         I915_WRITE(_TRANSA_CHICKEN2, val);
1903
1904         val = TRANS_ENABLE;
1905         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1906
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1908             PIPECONF_INTERLACED_ILK)
1909                 val |= TRANS_INTERLACED;
1910         else
1911                 val |= TRANS_PROGRESSIVE;
1912
1913         I915_WRITE(LPT_TRANSCONF, val);
1914         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1915                 DRM_ERROR("Failed to enable PCH transcoder\n");
1916 }
1917
1918 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1919                                             enum pipe pipe)
1920 {
1921         struct drm_device *dev = dev_priv->dev;
1922         uint32_t reg, val;
1923
1924         /* FDI relies on the transcoder */
1925         assert_fdi_tx_disabled(dev_priv, pipe);
1926         assert_fdi_rx_disabled(dev_priv, pipe);
1927
1928         /* Ports must be off as well */
1929         assert_pch_ports_disabled(dev_priv, pipe);
1930
1931         reg = PCH_TRANSCONF(pipe);
1932         val = I915_READ(reg);
1933         val &= ~TRANS_ENABLE;
1934         I915_WRITE(reg, val);
1935         /* wait for PCH transcoder off, transcoder state */
1936         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1937                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1938
1939         if (!HAS_PCH_IBX(dev)) {
1940                 /* Workaround: Clear the timing override chicken bit again. */
1941                 reg = TRANS_CHICKEN2(pipe);
1942                 val = I915_READ(reg);
1943                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1944                 I915_WRITE(reg, val);
1945         }
1946 }
1947
1948 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1949 {
1950         u32 val;
1951
1952         val = I915_READ(LPT_TRANSCONF);
1953         val &= ~TRANS_ENABLE;
1954         I915_WRITE(LPT_TRANSCONF, val);
1955         /* wait for PCH transcoder off, transcoder state */
1956         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1957                 DRM_ERROR("Failed to disable PCH transcoder\n");
1958
1959         /* Workaround: clear timing override bit. */
1960         val = I915_READ(_TRANSA_CHICKEN2);
1961         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1962         I915_WRITE(_TRANSA_CHICKEN2, val);
1963 }
1964
1965 /**
1966  * intel_enable_pipe - enable a pipe, asserting requirements
1967  * @crtc: crtc responsible for the pipe
1968  *
1969  * Enable @crtc's pipe, making sure that various hardware specific requirements
1970  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1971  */
1972 static void intel_enable_pipe(struct intel_crtc *crtc)
1973 {
1974         struct drm_device *dev = crtc->base.dev;
1975         struct drm_i915_private *dev_priv = dev->dev_private;
1976         enum pipe pipe = crtc->pipe;
1977         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1978                                                                       pipe);
1979         enum pipe pch_transcoder;
1980         int reg;
1981         u32 val;
1982
1983         assert_planes_disabled(dev_priv, pipe);
1984         assert_cursor_disabled(dev_priv, pipe);
1985         assert_sprites_disabled(dev_priv, pipe);
1986
1987         if (HAS_PCH_LPT(dev_priv->dev))
1988                 pch_transcoder = TRANSCODER_A;
1989         else
1990                 pch_transcoder = pipe;
1991
1992         /*
1993          * A pipe without a PLL won't actually be able to drive bits from
1994          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1995          * need the check.
1996          */
1997         if (!HAS_PCH_SPLIT(dev_priv->dev))
1998                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1999                         assert_dsi_pll_enabled(dev_priv);
2000                 else
2001                         assert_pll_enabled(dev_priv, pipe);
2002         else {
2003                 if (crtc->config.has_pch_encoder) {
2004                         /* if driving the PCH, we need FDI enabled */
2005                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2006                         assert_fdi_tx_pll_enabled(dev_priv,
2007                                                   (enum pipe) cpu_transcoder);
2008                 }
2009                 /* FIXME: assert CPU port conditions for SNB+ */
2010         }
2011
2012         reg = PIPECONF(cpu_transcoder);
2013         val = I915_READ(reg);
2014         if (val & PIPECONF_ENABLE) {
2015                 WARN_ON(!(pipe == PIPE_A &&
2016                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
2017                 return;
2018         }
2019
2020         I915_WRITE(reg, val | PIPECONF_ENABLE);
2021         POSTING_READ(reg);
2022 }
2023
2024 /**
2025  * intel_disable_pipe - disable a pipe, asserting requirements
2026  * @dev_priv: i915 private structure
2027  * @pipe: pipe to disable
2028  *
2029  * Disable @pipe, making sure that various hardware specific requirements
2030  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2031  *
2032  * @pipe should be %PIPE_A or %PIPE_B.
2033  *
2034  * Will wait until the pipe has shut down before returning.
2035  */
2036 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2037                                enum pipe pipe)
2038 {
2039         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2040                                                                       pipe);
2041         int reg;
2042         u32 val;
2043
2044         /*
2045          * Make sure planes won't keep trying to pump pixels to us,
2046          * or we might hang the display.
2047          */
2048         assert_planes_disabled(dev_priv, pipe);
2049         assert_cursor_disabled(dev_priv, pipe);
2050         assert_sprites_disabled(dev_priv, pipe);
2051
2052         /* Don't disable pipe A or pipe A PLLs if needed */
2053         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2054                 return;
2055
2056         reg = PIPECONF(cpu_transcoder);
2057         val = I915_READ(reg);
2058         if ((val & PIPECONF_ENABLE) == 0)
2059                 return;
2060
2061         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2062         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2063 }
2064
2065 /*
2066  * Plane regs are double buffered, going from enabled->disabled needs a
2067  * trigger in order to latch.  The display address reg provides this.
2068  */
2069 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2070                                enum plane plane)
2071 {
2072         struct drm_device *dev = dev_priv->dev;
2073         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2074
2075         I915_WRITE(reg, I915_READ(reg));
2076         POSTING_READ(reg);
2077 }
2078
2079 /**
2080  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2081  * @dev_priv: i915 private structure
2082  * @plane: plane to enable
2083  * @pipe: pipe being fed
2084  *
2085  * Enable @plane on @pipe, making sure that @pipe is running first.
2086  */
2087 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2088                                           enum plane plane, enum pipe pipe)
2089 {
2090         struct intel_crtc *intel_crtc =
2091                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2092         int reg;
2093         u32 val;
2094
2095         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2096         assert_pipe_enabled(dev_priv, pipe);
2097
2098         if (intel_crtc->primary_enabled)
2099                 return;
2100
2101         intel_crtc->primary_enabled = true;
2102
2103         reg = DSPCNTR(plane);
2104         val = I915_READ(reg);
2105         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2106
2107         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2108         intel_flush_primary_plane(dev_priv, plane);
2109 }
2110
2111 /**
2112  * intel_disable_primary_hw_plane - disable the primary hardware plane
2113  * @dev_priv: i915 private structure
2114  * @plane: plane to disable
2115  * @pipe: pipe consuming the data
2116  *
2117  * Disable @plane; should be an independent operation.
2118  */
2119 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2120                                            enum plane plane, enum pipe pipe)
2121 {
2122         struct intel_crtc *intel_crtc =
2123                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2124         int reg;
2125         u32 val;
2126
2127         if (!intel_crtc->primary_enabled)
2128                 return;
2129
2130         intel_crtc->primary_enabled = false;
2131
2132         reg = DSPCNTR(plane);
2133         val = I915_READ(reg);
2134         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2135
2136         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2137         intel_flush_primary_plane(dev_priv, plane);
2138 }
2139
2140 static bool need_vtd_wa(struct drm_device *dev)
2141 {
2142 #ifdef CONFIG_INTEL_IOMMU
2143         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2144                 return true;
2145 #endif
2146         return false;
2147 }
2148
2149 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2150 {
2151         int tile_height;
2152
2153         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2154         return ALIGN(height, tile_height);
2155 }
2156
2157 int
2158 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2159                            struct drm_i915_gem_object *obj,
2160                            struct intel_engine_cs *pipelined)
2161 {
2162         struct drm_i915_private *dev_priv = dev->dev_private;
2163         u32 alignment;
2164         int ret;
2165
2166         switch (obj->tiling_mode) {
2167         case I915_TILING_NONE:
2168                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2169                         alignment = 128 * 1024;
2170                 else if (INTEL_INFO(dev)->gen >= 4)
2171                         alignment = 4 * 1024;
2172                 else
2173                         alignment = 64 * 1024;
2174                 break;
2175         case I915_TILING_X:
2176                 /* pin() will align the object as required by fence */
2177                 alignment = 0;
2178                 break;
2179         case I915_TILING_Y:
2180                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2181                 return -EINVAL;
2182         default:
2183                 BUG();
2184         }
2185
2186         /* Note that the w/a also requires 64 PTE of padding following the
2187          * bo. We currently fill all unused PTE with the shadow page and so
2188          * we should always have valid PTE following the scanout preventing
2189          * the VT-d warning.
2190          */
2191         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2192                 alignment = 256 * 1024;
2193
2194         dev_priv->mm.interruptible = false;
2195         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2196         if (ret)
2197                 goto err_interruptible;
2198
2199         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2200          * fence, whereas 965+ only requires a fence if using
2201          * framebuffer compression.  For simplicity, we always install
2202          * a fence as the cost is not that onerous.
2203          */
2204         ret = i915_gem_object_get_fence(obj);
2205         if (ret)
2206                 goto err_unpin;
2207
2208         i915_gem_object_pin_fence(obj);
2209
2210         dev_priv->mm.interruptible = true;
2211         return 0;
2212
2213 err_unpin:
2214         i915_gem_object_unpin_from_display_plane(obj);
2215 err_interruptible:
2216         dev_priv->mm.interruptible = true;
2217         return ret;
2218 }
2219
2220 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2221 {
2222         i915_gem_object_unpin_fence(obj);
2223         i915_gem_object_unpin_from_display_plane(obj);
2224 }
2225
2226 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2227  * is assumed to be a power-of-two. */
2228 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2229                                              unsigned int tiling_mode,
2230                                              unsigned int cpp,
2231                                              unsigned int pitch)
2232 {
2233         if (tiling_mode != I915_TILING_NONE) {
2234                 unsigned int tile_rows, tiles;
2235
2236                 tile_rows = *y / 8;
2237                 *y %= 8;
2238
2239                 tiles = *x / (512/cpp);
2240                 *x %= 512/cpp;
2241
2242                 return tile_rows * pitch * 8 + tiles * 4096;
2243         } else {
2244                 unsigned int offset;
2245
2246                 offset = *y * pitch + *x * cpp;
2247                 *y = 0;
2248                 *x = (offset & 4095) / cpp;
2249                 return offset & -4096;
2250         }
2251 }
2252
2253 int intel_format_to_fourcc(int format)
2254 {
2255         switch (format) {
2256         case DISPPLANE_8BPP:
2257                 return DRM_FORMAT_C8;
2258         case DISPPLANE_BGRX555:
2259                 return DRM_FORMAT_XRGB1555;
2260         case DISPPLANE_BGRX565:
2261                 return DRM_FORMAT_RGB565;
2262         default:
2263         case DISPPLANE_BGRX888:
2264                 return DRM_FORMAT_XRGB8888;
2265         case DISPPLANE_RGBX888:
2266                 return DRM_FORMAT_XBGR8888;
2267         case DISPPLANE_BGRX101010:
2268                 return DRM_FORMAT_XRGB2101010;
2269         case DISPPLANE_RGBX101010:
2270                 return DRM_FORMAT_XBGR2101010;
2271         }
2272 }
2273
2274 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2275                                   struct intel_plane_config *plane_config)
2276 {
2277         struct drm_device *dev = crtc->base.dev;
2278         struct drm_i915_gem_object *obj = NULL;
2279         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2280         u32 base = plane_config->base;
2281
2282         if (plane_config->size == 0)
2283                 return false;
2284
2285         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2286                                                              plane_config->size);
2287         if (!obj)
2288                 return false;
2289
2290         if (plane_config->tiled) {
2291                 obj->tiling_mode = I915_TILING_X;
2292                 obj->stride = crtc->base.primary->fb->pitches[0];
2293         }
2294
2295         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2296         mode_cmd.width = crtc->base.primary->fb->width;
2297         mode_cmd.height = crtc->base.primary->fb->height;
2298         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2299
2300         mutex_lock(&dev->struct_mutex);
2301
2302         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2303                                    &mode_cmd, obj)) {
2304                 DRM_DEBUG_KMS("intel fb init failed\n");
2305                 goto out_unref_obj;
2306         }
2307
2308         mutex_unlock(&dev->struct_mutex);
2309
2310         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2311         return true;
2312
2313 out_unref_obj:
2314         drm_gem_object_unreference(&obj->base);
2315         mutex_unlock(&dev->struct_mutex);
2316         return false;
2317 }
2318
2319 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2320                                  struct intel_plane_config *plane_config)
2321 {
2322         struct drm_device *dev = intel_crtc->base.dev;
2323         struct drm_crtc *c;
2324         struct intel_crtc *i;
2325         struct intel_framebuffer *fb;
2326
2327         if (!intel_crtc->base.primary->fb)
2328                 return;
2329
2330         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2331                 return;
2332
2333         kfree(intel_crtc->base.primary->fb);
2334         intel_crtc->base.primary->fb = NULL;
2335
2336         /*
2337          * Failed to alloc the obj, check to see if we should share
2338          * an fb with another CRTC instead
2339          */
2340         for_each_crtc(dev, c) {
2341                 i = to_intel_crtc(c);
2342
2343                 if (c == &intel_crtc->base)
2344                         continue;
2345
2346                 if (!i->active || !c->primary->fb)
2347                         continue;
2348
2349                 fb = to_intel_framebuffer(c->primary->fb);
2350                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2351                         drm_framebuffer_reference(c->primary->fb);
2352                         intel_crtc->base.primary->fb = c->primary->fb;
2353                         break;
2354                 }
2355         }
2356 }
2357
2358 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2359                                       struct drm_framebuffer *fb,
2360                                       int x, int y)
2361 {
2362         struct drm_device *dev = crtc->dev;
2363         struct drm_i915_private *dev_priv = dev->dev_private;
2364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2365         struct intel_framebuffer *intel_fb;
2366         struct drm_i915_gem_object *obj;
2367         int plane = intel_crtc->plane;
2368         unsigned long linear_offset;
2369         u32 dspcntr;
2370         u32 reg;
2371
2372         intel_fb = to_intel_framebuffer(fb);
2373         obj = intel_fb->obj;
2374
2375         reg = DSPCNTR(plane);
2376         dspcntr = I915_READ(reg);
2377         /* Mask out pixel format bits in case we change it */
2378         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2379         switch (fb->pixel_format) {
2380         case DRM_FORMAT_C8:
2381                 dspcntr |= DISPPLANE_8BPP;
2382                 break;
2383         case DRM_FORMAT_XRGB1555:
2384         case DRM_FORMAT_ARGB1555:
2385                 dspcntr |= DISPPLANE_BGRX555;
2386                 break;
2387         case DRM_FORMAT_RGB565:
2388                 dspcntr |= DISPPLANE_BGRX565;
2389                 break;
2390         case DRM_FORMAT_XRGB8888:
2391         case DRM_FORMAT_ARGB8888:
2392                 dspcntr |= DISPPLANE_BGRX888;
2393                 break;
2394         case DRM_FORMAT_XBGR8888:
2395         case DRM_FORMAT_ABGR8888:
2396                 dspcntr |= DISPPLANE_RGBX888;
2397                 break;
2398         case DRM_FORMAT_XRGB2101010:
2399         case DRM_FORMAT_ARGB2101010:
2400                 dspcntr |= DISPPLANE_BGRX101010;
2401                 break;
2402         case DRM_FORMAT_XBGR2101010:
2403         case DRM_FORMAT_ABGR2101010:
2404                 dspcntr |= DISPPLANE_RGBX101010;
2405                 break;
2406         default:
2407                 BUG();
2408         }
2409
2410         if (INTEL_INFO(dev)->gen >= 4) {
2411                 if (obj->tiling_mode != I915_TILING_NONE)
2412                         dspcntr |= DISPPLANE_TILED;
2413                 else
2414                         dspcntr &= ~DISPPLANE_TILED;
2415         }
2416
2417         if (IS_G4X(dev))
2418                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2419
2420         I915_WRITE(reg, dspcntr);
2421
2422         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2423
2424         if (INTEL_INFO(dev)->gen >= 4) {
2425                 intel_crtc->dspaddr_offset =
2426                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2427                                                        fb->bits_per_pixel / 8,
2428                                                        fb->pitches[0]);
2429                 linear_offset -= intel_crtc->dspaddr_offset;
2430         } else {
2431                 intel_crtc->dspaddr_offset = linear_offset;
2432         }
2433
2434         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2435                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2436                       fb->pitches[0]);
2437         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2438         if (INTEL_INFO(dev)->gen >= 4) {
2439                 I915_WRITE(DSPSURF(plane),
2440                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2441                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2442                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2443         } else
2444                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2445         POSTING_READ(reg);
2446 }
2447
2448 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2449                                           struct drm_framebuffer *fb,
2450                                           int x, int y)
2451 {
2452         struct drm_device *dev = crtc->dev;
2453         struct drm_i915_private *dev_priv = dev->dev_private;
2454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2455         struct intel_framebuffer *intel_fb;
2456         struct drm_i915_gem_object *obj;
2457         int plane = intel_crtc->plane;
2458         unsigned long linear_offset;
2459         u32 dspcntr;
2460         u32 reg;
2461
2462         intel_fb = to_intel_framebuffer(fb);
2463         obj = intel_fb->obj;
2464
2465         reg = DSPCNTR(plane);
2466         dspcntr = I915_READ(reg);
2467         /* Mask out pixel format bits in case we change it */
2468         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2469         switch (fb->pixel_format) {
2470         case DRM_FORMAT_C8:
2471                 dspcntr |= DISPPLANE_8BPP;
2472                 break;
2473         case DRM_FORMAT_RGB565:
2474                 dspcntr |= DISPPLANE_BGRX565;
2475                 break;
2476         case DRM_FORMAT_XRGB8888:
2477         case DRM_FORMAT_ARGB8888:
2478                 dspcntr |= DISPPLANE_BGRX888;
2479                 break;
2480         case DRM_FORMAT_XBGR8888:
2481         case DRM_FORMAT_ABGR8888:
2482                 dspcntr |= DISPPLANE_RGBX888;
2483                 break;
2484         case DRM_FORMAT_XRGB2101010:
2485         case DRM_FORMAT_ARGB2101010:
2486                 dspcntr |= DISPPLANE_BGRX101010;
2487                 break;
2488         case DRM_FORMAT_XBGR2101010:
2489         case DRM_FORMAT_ABGR2101010:
2490                 dspcntr |= DISPPLANE_RGBX101010;
2491                 break;
2492         default:
2493                 BUG();
2494         }
2495
2496         if (obj->tiling_mode != I915_TILING_NONE)
2497                 dspcntr |= DISPPLANE_TILED;
2498         else
2499                 dspcntr &= ~DISPPLANE_TILED;
2500
2501         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2502                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2503         else
2504                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2505
2506         I915_WRITE(reg, dspcntr);
2507
2508         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2509         intel_crtc->dspaddr_offset =
2510                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2511                                                fb->bits_per_pixel / 8,
2512                                                fb->pitches[0]);
2513         linear_offset -= intel_crtc->dspaddr_offset;
2514
2515         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2516                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2517                       fb->pitches[0]);
2518         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2519         I915_WRITE(DSPSURF(plane),
2520                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2521         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2522                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2523         } else {
2524                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2525                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2526         }
2527         POSTING_READ(reg);
2528 }
2529
2530 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2531 static int
2532 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2533                            int x, int y, enum mode_set_atomic state)
2534 {
2535         struct drm_device *dev = crtc->dev;
2536         struct drm_i915_private *dev_priv = dev->dev_private;
2537
2538         if (dev_priv->display.disable_fbc)
2539                 dev_priv->display.disable_fbc(dev);
2540         intel_increase_pllclock(crtc);
2541
2542         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2543
2544         return 0;
2545 }
2546
2547 void intel_display_handle_reset(struct drm_device *dev)
2548 {
2549         struct drm_i915_private *dev_priv = dev->dev_private;
2550         struct drm_crtc *crtc;
2551
2552         /*
2553          * Flips in the rings have been nuked by the reset,
2554          * so complete all pending flips so that user space
2555          * will get its events and not get stuck.
2556          *
2557          * Also update the base address of all primary
2558          * planes to the the last fb to make sure we're
2559          * showing the correct fb after a reset.
2560          *
2561          * Need to make two loops over the crtcs so that we
2562          * don't try to grab a crtc mutex before the
2563          * pending_flip_queue really got woken up.
2564          */
2565
2566         for_each_crtc(dev, crtc) {
2567                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568                 enum plane plane = intel_crtc->plane;
2569
2570                 intel_prepare_page_flip(dev, plane);
2571                 intel_finish_page_flip_plane(dev, plane);
2572         }
2573
2574         for_each_crtc(dev, crtc) {
2575                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2576
2577                 drm_modeset_lock(&crtc->mutex, NULL);
2578                 /*
2579                  * FIXME: Once we have proper support for primary planes (and
2580                  * disabling them without disabling the entire crtc) allow again
2581                  * a NULL crtc->primary->fb.
2582                  */
2583                 if (intel_crtc->active && crtc->primary->fb)
2584                         dev_priv->display.update_primary_plane(crtc,
2585                                                                crtc->primary->fb,
2586                                                                crtc->x,
2587                                                                crtc->y);
2588                 drm_modeset_unlock(&crtc->mutex);
2589         }
2590 }
2591
2592 static int
2593 intel_finish_fb(struct drm_framebuffer *old_fb)
2594 {
2595         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2596         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2597         bool was_interruptible = dev_priv->mm.interruptible;
2598         int ret;
2599
2600         /* Big Hammer, we also need to ensure that any pending
2601          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2602          * current scanout is retired before unpinning the old
2603          * framebuffer.
2604          *
2605          * This should only fail upon a hung GPU, in which case we
2606          * can safely continue.
2607          */
2608         dev_priv->mm.interruptible = false;
2609         ret = i915_gem_object_finish_gpu(obj);
2610         dev_priv->mm.interruptible = was_interruptible;
2611
2612         return ret;
2613 }
2614
2615 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2616 {
2617         struct drm_device *dev = crtc->dev;
2618         struct drm_i915_private *dev_priv = dev->dev_private;
2619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2620         unsigned long flags;
2621         bool pending;
2622
2623         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2624             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2625                 return false;
2626
2627         spin_lock_irqsave(&dev->event_lock, flags);
2628         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2629         spin_unlock_irqrestore(&dev->event_lock, flags);
2630
2631         return pending;
2632 }
2633
2634 static int
2635 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2636                     struct drm_framebuffer *fb)
2637 {
2638         struct drm_device *dev = crtc->dev;
2639         struct drm_i915_private *dev_priv = dev->dev_private;
2640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2641         struct drm_framebuffer *old_fb;
2642         int ret;
2643
2644         if (intel_crtc_has_pending_flip(crtc)) {
2645                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2646                 return -EBUSY;
2647         }
2648
2649         /* no fb bound */
2650         if (!fb) {
2651                 DRM_ERROR("No FB bound\n");
2652                 return 0;
2653         }
2654
2655         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2656                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2657                           plane_name(intel_crtc->plane),
2658                           INTEL_INFO(dev)->num_pipes);
2659                 return -EINVAL;
2660         }
2661
2662         mutex_lock(&dev->struct_mutex);
2663         ret = intel_pin_and_fence_fb_obj(dev,
2664                                          to_intel_framebuffer(fb)->obj,
2665                                          NULL);
2666         mutex_unlock(&dev->struct_mutex);
2667         if (ret != 0) {
2668                 DRM_ERROR("pin & fence failed\n");
2669                 return ret;
2670         }
2671
2672         /*
2673          * Update pipe size and adjust fitter if needed: the reason for this is
2674          * that in compute_mode_changes we check the native mode (not the pfit
2675          * mode) to see if we can flip rather than do a full mode set. In the
2676          * fastboot case, we'll flip, but if we don't update the pipesrc and
2677          * pfit state, we'll end up with a big fb scanned out into the wrong
2678          * sized surface.
2679          *
2680          * To fix this properly, we need to hoist the checks up into
2681          * compute_mode_changes (or above), check the actual pfit state and
2682          * whether the platform allows pfit disable with pipe active, and only
2683          * then update the pipesrc and pfit state, even on the flip path.
2684          */
2685         if (i915.fastboot) {
2686                 const struct drm_display_mode *adjusted_mode =
2687                         &intel_crtc->config.adjusted_mode;
2688
2689                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2690                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2691                            (adjusted_mode->crtc_vdisplay - 1));
2692                 if (!intel_crtc->config.pch_pfit.enabled &&
2693                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2694                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2695                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2696                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2697                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2698                 }
2699                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2700                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2701         }
2702
2703         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2704
2705         old_fb = crtc->primary->fb;
2706         crtc->primary->fb = fb;
2707         crtc->x = x;
2708         crtc->y = y;
2709
2710         if (old_fb) {
2711                 if (intel_crtc->active && old_fb != fb)
2712                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2713                 mutex_lock(&dev->struct_mutex);
2714                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2715                 mutex_unlock(&dev->struct_mutex);
2716         }
2717
2718         mutex_lock(&dev->struct_mutex);
2719         intel_update_fbc(dev);
2720         intel_edp_psr_update(dev);
2721         mutex_unlock(&dev->struct_mutex);
2722
2723         return 0;
2724 }
2725
2726 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2727 {
2728         struct drm_device *dev = crtc->dev;
2729         struct drm_i915_private *dev_priv = dev->dev_private;
2730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731         int pipe = intel_crtc->pipe;
2732         u32 reg, temp;
2733
2734         /* enable normal train */
2735         reg = FDI_TX_CTL(pipe);
2736         temp = I915_READ(reg);
2737         if (IS_IVYBRIDGE(dev)) {
2738                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2739                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2740         } else {
2741                 temp &= ~FDI_LINK_TRAIN_NONE;
2742                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2743         }
2744         I915_WRITE(reg, temp);
2745
2746         reg = FDI_RX_CTL(pipe);
2747         temp = I915_READ(reg);
2748         if (HAS_PCH_CPT(dev)) {
2749                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2750                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2751         } else {
2752                 temp &= ~FDI_LINK_TRAIN_NONE;
2753                 temp |= FDI_LINK_TRAIN_NONE;
2754         }
2755         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2756
2757         /* wait one idle pattern time */
2758         POSTING_READ(reg);
2759         udelay(1000);
2760
2761         /* IVB wants error correction enabled */
2762         if (IS_IVYBRIDGE(dev))
2763                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2764                            FDI_FE_ERRC_ENABLE);
2765 }
2766
2767 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2768 {
2769         return crtc->base.enabled && crtc->active &&
2770                 crtc->config.has_pch_encoder;
2771 }
2772
2773 static void ivb_modeset_global_resources(struct drm_device *dev)
2774 {
2775         struct drm_i915_private *dev_priv = dev->dev_private;
2776         struct intel_crtc *pipe_B_crtc =
2777                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2778         struct intel_crtc *pipe_C_crtc =
2779                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2780         uint32_t temp;
2781
2782         /*
2783          * When everything is off disable fdi C so that we could enable fdi B
2784          * with all lanes. Note that we don't care about enabled pipes without
2785          * an enabled pch encoder.
2786          */
2787         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2788             !pipe_has_enabled_pch(pipe_C_crtc)) {
2789                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2790                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2791
2792                 temp = I915_READ(SOUTH_CHICKEN1);
2793                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2794                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2795                 I915_WRITE(SOUTH_CHICKEN1, temp);
2796         }
2797 }
2798
2799 /* The FDI link training functions for ILK/Ibexpeak. */
2800 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2801 {
2802         struct drm_device *dev = crtc->dev;
2803         struct drm_i915_private *dev_priv = dev->dev_private;
2804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805         int pipe = intel_crtc->pipe;
2806         u32 reg, temp, tries;
2807
2808         /* FDI needs bits from pipe first */
2809         assert_pipe_enabled(dev_priv, pipe);
2810
2811         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2812            for train result */
2813         reg = FDI_RX_IMR(pipe);
2814         temp = I915_READ(reg);
2815         temp &= ~FDI_RX_SYMBOL_LOCK;
2816         temp &= ~FDI_RX_BIT_LOCK;
2817         I915_WRITE(reg, temp);
2818         I915_READ(reg);
2819         udelay(150);
2820
2821         /* enable CPU FDI TX and PCH FDI RX */
2822         reg = FDI_TX_CTL(pipe);
2823         temp = I915_READ(reg);
2824         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2825         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2826         temp &= ~FDI_LINK_TRAIN_NONE;
2827         temp |= FDI_LINK_TRAIN_PATTERN_1;
2828         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2829
2830         reg = FDI_RX_CTL(pipe);
2831         temp = I915_READ(reg);
2832         temp &= ~FDI_LINK_TRAIN_NONE;
2833         temp |= FDI_LINK_TRAIN_PATTERN_1;
2834         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2835
2836         POSTING_READ(reg);
2837         udelay(150);
2838
2839         /* Ironlake workaround, enable clock pointer after FDI enable*/
2840         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2841         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2842                    FDI_RX_PHASE_SYNC_POINTER_EN);
2843
2844         reg = FDI_RX_IIR(pipe);
2845         for (tries = 0; tries < 5; tries++) {
2846                 temp = I915_READ(reg);
2847                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2848
2849                 if ((temp & FDI_RX_BIT_LOCK)) {
2850                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2851                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2852                         break;
2853                 }
2854         }
2855         if (tries == 5)
2856                 DRM_ERROR("FDI train 1 fail!\n");
2857
2858         /* Train 2 */
2859         reg = FDI_TX_CTL(pipe);
2860         temp = I915_READ(reg);
2861         temp &= ~FDI_LINK_TRAIN_NONE;
2862         temp |= FDI_LINK_TRAIN_PATTERN_2;
2863         I915_WRITE(reg, temp);
2864
2865         reg = FDI_RX_CTL(pipe);
2866         temp = I915_READ(reg);
2867         temp &= ~FDI_LINK_TRAIN_NONE;
2868         temp |= FDI_LINK_TRAIN_PATTERN_2;
2869         I915_WRITE(reg, temp);
2870
2871         POSTING_READ(reg);
2872         udelay(150);
2873
2874         reg = FDI_RX_IIR(pipe);
2875         for (tries = 0; tries < 5; tries++) {
2876                 temp = I915_READ(reg);
2877                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2878
2879                 if (temp & FDI_RX_SYMBOL_LOCK) {
2880                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2881                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2882                         break;
2883                 }
2884         }
2885         if (tries == 5)
2886                 DRM_ERROR("FDI train 2 fail!\n");
2887
2888         DRM_DEBUG_KMS("FDI train done\n");
2889
2890 }
2891
2892 static const int snb_b_fdi_train_param[] = {
2893         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2894         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2895         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2896         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2897 };
2898
2899 /* The FDI link training functions for SNB/Cougarpoint. */
2900 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2901 {
2902         struct drm_device *dev = crtc->dev;
2903         struct drm_i915_private *dev_priv = dev->dev_private;
2904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2905         int pipe = intel_crtc->pipe;
2906         u32 reg, temp, i, retry;
2907
2908         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2909            for train result */
2910         reg = FDI_RX_IMR(pipe);
2911         temp = I915_READ(reg);
2912         temp &= ~FDI_RX_SYMBOL_LOCK;
2913         temp &= ~FDI_RX_BIT_LOCK;
2914         I915_WRITE(reg, temp);
2915
2916         POSTING_READ(reg);
2917         udelay(150);
2918
2919         /* enable CPU FDI TX and PCH FDI RX */
2920         reg = FDI_TX_CTL(pipe);
2921         temp = I915_READ(reg);
2922         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2923         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2924         temp &= ~FDI_LINK_TRAIN_NONE;
2925         temp |= FDI_LINK_TRAIN_PATTERN_1;
2926         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2927         /* SNB-B */
2928         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2929         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2930
2931         I915_WRITE(FDI_RX_MISC(pipe),
2932                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2933
2934         reg = FDI_RX_CTL(pipe);
2935         temp = I915_READ(reg);
2936         if (HAS_PCH_CPT(dev)) {
2937                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2938                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2939         } else {
2940                 temp &= ~FDI_LINK_TRAIN_NONE;
2941                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2942         }
2943         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2944
2945         POSTING_READ(reg);
2946         udelay(150);
2947
2948         for (i = 0; i < 4; i++) {
2949                 reg = FDI_TX_CTL(pipe);
2950                 temp = I915_READ(reg);
2951                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2952                 temp |= snb_b_fdi_train_param[i];
2953                 I915_WRITE(reg, temp);
2954
2955                 POSTING_READ(reg);
2956                 udelay(500);
2957
2958                 for (retry = 0; retry < 5; retry++) {
2959                         reg = FDI_RX_IIR(pipe);
2960                         temp = I915_READ(reg);
2961                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2962                         if (temp & FDI_RX_BIT_LOCK) {
2963                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2964                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2965                                 break;
2966                         }
2967                         udelay(50);
2968                 }
2969                 if (retry < 5)
2970                         break;
2971         }
2972         if (i == 4)
2973                 DRM_ERROR("FDI train 1 fail!\n");
2974
2975         /* Train 2 */
2976         reg = FDI_TX_CTL(pipe);
2977         temp = I915_READ(reg);
2978         temp &= ~FDI_LINK_TRAIN_NONE;
2979         temp |= FDI_LINK_TRAIN_PATTERN_2;
2980         if (IS_GEN6(dev)) {
2981                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2982                 /* SNB-B */
2983                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2984         }
2985         I915_WRITE(reg, temp);
2986
2987         reg = FDI_RX_CTL(pipe);
2988         temp = I915_READ(reg);
2989         if (HAS_PCH_CPT(dev)) {
2990                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2991                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2992         } else {
2993                 temp &= ~FDI_LINK_TRAIN_NONE;
2994                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2995         }
2996         I915_WRITE(reg, temp);
2997
2998         POSTING_READ(reg);
2999         udelay(150);
3000
3001         for (i = 0; i < 4; i++) {
3002                 reg = FDI_TX_CTL(pipe);
3003                 temp = I915_READ(reg);
3004                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3005                 temp |= snb_b_fdi_train_param[i];
3006                 I915_WRITE(reg, temp);
3007
3008                 POSTING_READ(reg);
3009                 udelay(500);
3010
3011                 for (retry = 0; retry < 5; retry++) {
3012                         reg = FDI_RX_IIR(pipe);
3013                         temp = I915_READ(reg);
3014                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3015                         if (temp & FDI_RX_SYMBOL_LOCK) {
3016                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3017                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3018                                 break;
3019                         }
3020                         udelay(50);
3021                 }
3022                 if (retry < 5)
3023                         break;
3024         }
3025         if (i == 4)
3026                 DRM_ERROR("FDI train 2 fail!\n");
3027
3028         DRM_DEBUG_KMS("FDI train done.\n");
3029 }
3030
3031 /* Manual link training for Ivy Bridge A0 parts */
3032 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3033 {
3034         struct drm_device *dev = crtc->dev;
3035         struct drm_i915_private *dev_priv = dev->dev_private;
3036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037         int pipe = intel_crtc->pipe;
3038         u32 reg, temp, i, j;
3039
3040         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3041            for train result */
3042         reg = FDI_RX_IMR(pipe);
3043         temp = I915_READ(reg);
3044         temp &= ~FDI_RX_SYMBOL_LOCK;
3045         temp &= ~FDI_RX_BIT_LOCK;
3046         I915_WRITE(reg, temp);
3047
3048         POSTING_READ(reg);
3049         udelay(150);
3050
3051         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3052                       I915_READ(FDI_RX_IIR(pipe)));
3053
3054         /* Try each vswing and preemphasis setting twice before moving on */
3055         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3056                 /* disable first in case we need to retry */
3057                 reg = FDI_TX_CTL(pipe);
3058                 temp = I915_READ(reg);
3059                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3060                 temp &= ~FDI_TX_ENABLE;
3061                 I915_WRITE(reg, temp);
3062
3063                 reg = FDI_RX_CTL(pipe);
3064                 temp = I915_READ(reg);
3065                 temp &= ~FDI_LINK_TRAIN_AUTO;
3066                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3067                 temp &= ~FDI_RX_ENABLE;
3068                 I915_WRITE(reg, temp);
3069
3070                 /* enable CPU FDI TX and PCH FDI RX */
3071                 reg = FDI_TX_CTL(pipe);
3072                 temp = I915_READ(reg);
3073                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3074                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3075                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3076                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3077                 temp |= snb_b_fdi_train_param[j/2];
3078                 temp |= FDI_COMPOSITE_SYNC;
3079                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3080
3081                 I915_WRITE(FDI_RX_MISC(pipe),
3082                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3083
3084                 reg = FDI_RX_CTL(pipe);
3085                 temp = I915_READ(reg);
3086                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3087                 temp |= FDI_COMPOSITE_SYNC;
3088                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3089
3090                 POSTING_READ(reg);
3091                 udelay(1); /* should be 0.5us */
3092
3093                 for (i = 0; i < 4; i++) {
3094                         reg = FDI_RX_IIR(pipe);
3095                         temp = I915_READ(reg);
3096                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3097
3098                         if (temp & FDI_RX_BIT_LOCK ||
3099                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3100                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3101                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3102                                               i);
3103                                 break;
3104                         }
3105                         udelay(1); /* should be 0.5us */
3106                 }
3107                 if (i == 4) {
3108                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3109                         continue;
3110                 }
3111
3112                 /* Train 2 */
3113                 reg = FDI_TX_CTL(pipe);
3114                 temp = I915_READ(reg);
3115                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3116                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3117                 I915_WRITE(reg, temp);
3118
3119                 reg = FDI_RX_CTL(pipe);
3120                 temp = I915_READ(reg);
3121                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3122                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3123                 I915_WRITE(reg, temp);
3124
3125                 POSTING_READ(reg);
3126                 udelay(2); /* should be 1.5us */
3127
3128                 for (i = 0; i < 4; i++) {
3129                         reg = FDI_RX_IIR(pipe);
3130                         temp = I915_READ(reg);
3131                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3132
3133                         if (temp & FDI_RX_SYMBOL_LOCK ||
3134                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3135                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3136                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3137                                               i);
3138                                 goto train_done;
3139                         }
3140                         udelay(2); /* should be 1.5us */
3141                 }
3142                 if (i == 4)
3143                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3144         }
3145
3146 train_done:
3147         DRM_DEBUG_KMS("FDI train done.\n");
3148 }
3149
3150 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3151 {
3152         struct drm_device *dev = intel_crtc->base.dev;
3153         struct drm_i915_private *dev_priv = dev->dev_private;
3154         int pipe = intel_crtc->pipe;
3155         u32 reg, temp;
3156
3157
3158         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3159         reg = FDI_RX_CTL(pipe);
3160         temp = I915_READ(reg);
3161         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3162         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3163         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3164         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3165
3166         POSTING_READ(reg);
3167         udelay(200);
3168
3169         /* Switch from Rawclk to PCDclk */
3170         temp = I915_READ(reg);
3171         I915_WRITE(reg, temp | FDI_PCDCLK);
3172
3173         POSTING_READ(reg);
3174         udelay(200);
3175
3176         /* Enable CPU FDI TX PLL, always on for Ironlake */
3177         reg = FDI_TX_CTL(pipe);
3178         temp = I915_READ(reg);
3179         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3180                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3181
3182                 POSTING_READ(reg);
3183                 udelay(100);
3184         }
3185 }
3186
3187 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3188 {
3189         struct drm_device *dev = intel_crtc->base.dev;
3190         struct drm_i915_private *dev_priv = dev->dev_private;
3191         int pipe = intel_crtc->pipe;
3192         u32 reg, temp;
3193
3194         /* Switch from PCDclk to Rawclk */
3195         reg = FDI_RX_CTL(pipe);
3196         temp = I915_READ(reg);
3197         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3198
3199         /* Disable CPU FDI TX PLL */
3200         reg = FDI_TX_CTL(pipe);
3201         temp = I915_READ(reg);
3202         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3203
3204         POSTING_READ(reg);
3205         udelay(100);
3206
3207         reg = FDI_RX_CTL(pipe);
3208         temp = I915_READ(reg);
3209         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3210
3211         /* Wait for the clocks to turn off. */
3212         POSTING_READ(reg);
3213         udelay(100);
3214 }
3215
3216 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3217 {
3218         struct drm_device *dev = crtc->dev;
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3221         int pipe = intel_crtc->pipe;
3222         u32 reg, temp;
3223
3224         /* disable CPU FDI tx and PCH FDI rx */
3225         reg = FDI_TX_CTL(pipe);
3226         temp = I915_READ(reg);
3227         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3228         POSTING_READ(reg);
3229
3230         reg = FDI_RX_CTL(pipe);
3231         temp = I915_READ(reg);
3232         temp &= ~(0x7 << 16);
3233         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3234         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3235
3236         POSTING_READ(reg);
3237         udelay(100);
3238
3239         /* Ironlake workaround, disable clock pointer after downing FDI */
3240         if (HAS_PCH_IBX(dev))
3241                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3242
3243         /* still set train pattern 1 */
3244         reg = FDI_TX_CTL(pipe);
3245         temp = I915_READ(reg);
3246         temp &= ~FDI_LINK_TRAIN_NONE;
3247         temp |= FDI_LINK_TRAIN_PATTERN_1;
3248         I915_WRITE(reg, temp);
3249
3250         reg = FDI_RX_CTL(pipe);
3251         temp = I915_READ(reg);
3252         if (HAS_PCH_CPT(dev)) {
3253                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3254                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3255         } else {
3256                 temp &= ~FDI_LINK_TRAIN_NONE;
3257                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3258         }
3259         /* BPC in FDI rx is consistent with that in PIPECONF */
3260         temp &= ~(0x07 << 16);
3261         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3262         I915_WRITE(reg, temp);
3263
3264         POSTING_READ(reg);
3265         udelay(100);
3266 }
3267
3268 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3269 {
3270         struct intel_crtc *crtc;
3271
3272         /* Note that we don't need to be called with mode_config.lock here
3273          * as our list of CRTC objects is static for the lifetime of the
3274          * device and so cannot disappear as we iterate. Similarly, we can
3275          * happily treat the predicates as racy, atomic checks as userspace
3276          * cannot claim and pin a new fb without at least acquring the
3277          * struct_mutex and so serialising with us.
3278          */
3279         for_each_intel_crtc(dev, crtc) {
3280                 if (atomic_read(&crtc->unpin_work_count) == 0)
3281                         continue;
3282
3283                 if (crtc->unpin_work)
3284                         intel_wait_for_vblank(dev, crtc->pipe);
3285
3286                 return true;
3287         }
3288
3289         return false;
3290 }
3291
3292 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3293 {
3294         struct drm_device *dev = crtc->dev;
3295         struct drm_i915_private *dev_priv = dev->dev_private;
3296
3297         if (crtc->primary->fb == NULL)
3298                 return;
3299
3300         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3301
3302         WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3303                                    !intel_crtc_has_pending_flip(crtc),
3304                                    60*HZ) == 0);
3305
3306         mutex_lock(&dev->struct_mutex);
3307         intel_finish_fb(crtc->primary->fb);
3308         mutex_unlock(&dev->struct_mutex);
3309 }
3310
3311 /* Program iCLKIP clock to the desired frequency */
3312 static void lpt_program_iclkip(struct drm_crtc *crtc)
3313 {
3314         struct drm_device *dev = crtc->dev;
3315         struct drm_i915_private *dev_priv = dev->dev_private;
3316         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3317         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3318         u32 temp;
3319
3320         mutex_lock(&dev_priv->dpio_lock);
3321
3322         /* It is necessary to ungate the pixclk gate prior to programming
3323          * the divisors, and gate it back when it is done.
3324          */
3325         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3326
3327         /* Disable SSCCTL */
3328         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3329                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3330                                 SBI_SSCCTL_DISABLE,
3331                         SBI_ICLK);
3332
3333         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3334         if (clock == 20000) {
3335                 auxdiv = 1;
3336                 divsel = 0x41;
3337                 phaseinc = 0x20;
3338         } else {
3339                 /* The iCLK virtual clock root frequency is in MHz,
3340                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3341                  * divisors, it is necessary to divide one by another, so we
3342                  * convert the virtual clock precision to KHz here for higher
3343                  * precision.
3344                  */
3345                 u32 iclk_virtual_root_freq = 172800 * 1000;
3346                 u32 iclk_pi_range = 64;
3347                 u32 desired_divisor, msb_divisor_value, pi_value;
3348
3349                 desired_divisor = (iclk_virtual_root_freq / clock);
3350                 msb_divisor_value = desired_divisor / iclk_pi_range;
3351                 pi_value = desired_divisor % iclk_pi_range;
3352
3353                 auxdiv = 0;
3354                 divsel = msb_divisor_value - 2;
3355                 phaseinc = pi_value;
3356         }
3357
3358         /* This should not happen with any sane values */
3359         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3360                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3361         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3362                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3363
3364         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3365                         clock,
3366                         auxdiv,
3367                         divsel,
3368                         phasedir,
3369                         phaseinc);
3370
3371         /* Program SSCDIVINTPHASE6 */
3372         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3373         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3374         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3375         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3376         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3377         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3378         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3379         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3380
3381         /* Program SSCAUXDIV */
3382         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3383         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3384         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3385         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3386
3387         /* Enable modulator and associated divider */
3388         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3389         temp &= ~SBI_SSCCTL_DISABLE;
3390         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3391
3392         /* Wait for initialization time */
3393         udelay(24);
3394
3395         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3396
3397         mutex_unlock(&dev_priv->dpio_lock);
3398 }
3399
3400 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3401                                                 enum pipe pch_transcoder)
3402 {
3403         struct drm_device *dev = crtc->base.dev;
3404         struct drm_i915_private *dev_priv = dev->dev_private;
3405         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3406
3407         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3408                    I915_READ(HTOTAL(cpu_transcoder)));
3409         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3410                    I915_READ(HBLANK(cpu_transcoder)));
3411         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3412                    I915_READ(HSYNC(cpu_transcoder)));
3413
3414         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3415                    I915_READ(VTOTAL(cpu_transcoder)));
3416         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3417                    I915_READ(VBLANK(cpu_transcoder)));
3418         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3419                    I915_READ(VSYNC(cpu_transcoder)));
3420         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3421                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3422 }
3423
3424 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3425 {
3426         struct drm_i915_private *dev_priv = dev->dev_private;
3427         uint32_t temp;
3428
3429         temp = I915_READ(SOUTH_CHICKEN1);
3430         if (temp & FDI_BC_BIFURCATION_SELECT)
3431                 return;
3432
3433         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3434         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3435
3436         temp |= FDI_BC_BIFURCATION_SELECT;
3437         DRM_DEBUG_KMS("enabling fdi C rx\n");
3438         I915_WRITE(SOUTH_CHICKEN1, temp);
3439         POSTING_READ(SOUTH_CHICKEN1);
3440 }
3441
3442 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3443 {
3444         struct drm_device *dev = intel_crtc->base.dev;
3445         struct drm_i915_private *dev_priv = dev->dev_private;
3446
3447         switch (intel_crtc->pipe) {
3448         case PIPE_A:
3449                 break;
3450         case PIPE_B:
3451                 if (intel_crtc->config.fdi_lanes > 2)
3452                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3453                 else
3454                         cpt_enable_fdi_bc_bifurcation(dev);
3455
3456                 break;
3457         case PIPE_C:
3458                 cpt_enable_fdi_bc_bifurcation(dev);
3459
3460                 break;
3461         default:
3462                 BUG();
3463         }
3464 }
3465
3466 /*
3467  * Enable PCH resources required for PCH ports:
3468  *   - PCH PLLs
3469  *   - FDI training & RX/TX
3470  *   - update transcoder timings
3471  *   - DP transcoding bits
3472  *   - transcoder
3473  */
3474 static void ironlake_pch_enable(struct drm_crtc *crtc)
3475 {
3476         struct drm_device *dev = crtc->dev;
3477         struct drm_i915_private *dev_priv = dev->dev_private;
3478         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3479         int pipe = intel_crtc->pipe;
3480         u32 reg, temp;
3481
3482         assert_pch_transcoder_disabled(dev_priv, pipe);
3483
3484         if (IS_IVYBRIDGE(dev))
3485                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3486
3487         /* Write the TU size bits before fdi link training, so that error
3488          * detection works. */
3489         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3490                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3491
3492         /* For PCH output, training FDI link */
3493         dev_priv->display.fdi_link_train(crtc);
3494
3495         /* We need to program the right clock selection before writing the pixel
3496          * mutliplier into the DPLL. */
3497         if (HAS_PCH_CPT(dev)) {
3498                 u32 sel;
3499
3500                 temp = I915_READ(PCH_DPLL_SEL);
3501                 temp |= TRANS_DPLL_ENABLE(pipe);
3502                 sel = TRANS_DPLLB_SEL(pipe);
3503                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3504                         temp |= sel;
3505                 else
3506                         temp &= ~sel;
3507                 I915_WRITE(PCH_DPLL_SEL, temp);
3508         }
3509
3510         /* XXX: pch pll's can be enabled any time before we enable the PCH
3511          * transcoder, and we actually should do this to not upset any PCH
3512          * transcoder that already use the clock when we share it.
3513          *
3514          * Note that enable_shared_dpll tries to do the right thing, but
3515          * get_shared_dpll unconditionally resets the pll - we need that to have
3516          * the right LVDS enable sequence. */
3517         intel_enable_shared_dpll(intel_crtc);
3518
3519         /* set transcoder timing, panel must allow