2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/reservation.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
45 #include <drm/i915_drm.h>
48 #include "i915_gem_clflush.h"
49 #include "i915_trace.h"
50 #include "intel_acpi.h"
51 #include "intel_atomic.h"
52 #include "intel_atomic_plane.h"
53 #include "intel_color.h"
54 #include "intel_cdclk.h"
55 #include "intel_crt.h"
56 #include "intel_ddi.h"
58 #include "intel_drv.h"
59 #include "intel_dsi.h"
60 #include "intel_dvo.h"
61 #include "intel_fbc.h"
62 #include "intel_fbdev.h"
63 #include "intel_fifo_underrun.h"
64 #include "intel_frontbuffer.h"
65 #include "intel_gmbus.h"
66 #include "intel_hdcp.h"
67 #include "intel_hdmi.h"
68 #include "intel_hotplug.h"
69 #include "intel_lvds.h"
70 #include "intel_overlay.h"
71 #include "intel_pipe_crc.h"
73 #include "intel_psr.h"
74 #include "intel_quirks.h"
75 #include "intel_sdvo.h"
76 #include "intel_sideband.h"
77 #include "intel_sprite.h"
79 #include "intel_vdsc.h"
81 /* Primary plane formats for gen <= 3 */
82 static const u32 i8xx_primary_formats[] = {
89 /* Primary plane formats for gen >= 4 */
90 static const u32 i965_primary_formats[] = {
95 DRM_FORMAT_XRGB2101010,
96 DRM_FORMAT_XBGR2101010,
99 static const u64 i9xx_format_modifiers[] = {
100 I915_FORMAT_MOD_X_TILED,
101 DRM_FORMAT_MOD_LINEAR,
102 DRM_FORMAT_MOD_INVALID
106 static const u32 intel_cursor_formats[] = {
110 static const u64 cursor_format_modifiers[] = {
111 DRM_FORMAT_MOD_LINEAR,
112 DRM_FORMAT_MOD_INVALID
115 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
116 struct intel_crtc_state *pipe_config);
117 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
118 struct intel_crtc_state *pipe_config);
120 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
121 struct drm_i915_gem_object *obj,
122 struct drm_mode_fb_cmd2 *mode_cmd);
123 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
124 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
125 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
126 const struct intel_link_m_n *m_n,
127 const struct intel_link_m_n *m2_n2);
128 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
129 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
130 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
131 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
132 static void vlv_prepare_pll(struct intel_crtc *crtc,
133 const struct intel_crtc_state *pipe_config);
134 static void chv_prepare_pll(struct intel_crtc *crtc,
135 const struct intel_crtc_state *pipe_config);
136 static void intel_begin_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
137 static void intel_finish_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
138 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
139 struct intel_crtc_state *crtc_state);
140 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
141 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
142 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
143 static void intel_modeset_setup_hw_state(struct drm_device *dev,
144 struct drm_modeset_acquire_ctx *ctx);
145 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
150 } dot, vco, n, m, m1, m2, p, p1;
154 int p2_slow, p2_fast;
158 /* returns HPLL frequency in kHz */
159 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
161 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
163 /* Obtain SKU information */
164 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
165 CCK_FUSE_HPLL_FREQ_MASK;
167 return vco_freq[hpll_freq] * 1000;
170 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
171 const char *name, u32 reg, int ref_freq)
176 val = vlv_cck_read(dev_priv, reg);
177 divider = val & CCK_FREQUENCY_VALUES;
179 WARN((val & CCK_FREQUENCY_STATUS) !=
180 (divider << CCK_FREQUENCY_STATUS_SHIFT),
181 "%s change in progress\n", name);
183 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
186 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
187 const char *name, u32 reg)
191 vlv_cck_get(dev_priv);
193 if (dev_priv->hpll_freq == 0)
194 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
196 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
198 vlv_cck_put(dev_priv);
203 static void intel_update_czclk(struct drm_i915_private *dev_priv)
205 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
208 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
209 CCK_CZ_CLOCK_CONTROL);
211 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
214 static inline u32 /* units of 100MHz */
215 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
216 const struct intel_crtc_state *pipe_config)
218 if (HAS_DDI(dev_priv))
219 return pipe_config->port_clock; /* SPLL */
221 return dev_priv->fdi_pll_freq;
224 static const struct intel_limit intel_limits_i8xx_dac = {
225 .dot = { .min = 25000, .max = 350000 },
226 .vco = { .min = 908000, .max = 1512000 },
227 .n = { .min = 2, .max = 16 },
228 .m = { .min = 96, .max = 140 },
229 .m1 = { .min = 18, .max = 26 },
230 .m2 = { .min = 6, .max = 16 },
231 .p = { .min = 4, .max = 128 },
232 .p1 = { .min = 2, .max = 33 },
233 .p2 = { .dot_limit = 165000,
234 .p2_slow = 4, .p2_fast = 2 },
237 static const struct intel_limit intel_limits_i8xx_dvo = {
238 .dot = { .min = 25000, .max = 350000 },
239 .vco = { .min = 908000, .max = 1512000 },
240 .n = { .min = 2, .max = 16 },
241 .m = { .min = 96, .max = 140 },
242 .m1 = { .min = 18, .max = 26 },
243 .m2 = { .min = 6, .max = 16 },
244 .p = { .min = 4, .max = 128 },
245 .p1 = { .min = 2, .max = 33 },
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 4, .p2_fast = 4 },
250 static const struct intel_limit intel_limits_i8xx_lvds = {
251 .dot = { .min = 25000, .max = 350000 },
252 .vco = { .min = 908000, .max = 1512000 },
253 .n = { .min = 2, .max = 16 },
254 .m = { .min = 96, .max = 140 },
255 .m1 = { .min = 18, .max = 26 },
256 .m2 = { .min = 6, .max = 16 },
257 .p = { .min = 4, .max = 128 },
258 .p1 = { .min = 1, .max = 6 },
259 .p2 = { .dot_limit = 165000,
260 .p2_slow = 14, .p2_fast = 7 },
263 static const struct intel_limit intel_limits_i9xx_sdvo = {
264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1400000, .max = 2800000 },
266 .n = { .min = 1, .max = 6 },
267 .m = { .min = 70, .max = 120 },
268 .m1 = { .min = 8, .max = 18 },
269 .m2 = { .min = 3, .max = 7 },
270 .p = { .min = 5, .max = 80 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 200000,
273 .p2_slow = 10, .p2_fast = 5 },
276 static const struct intel_limit intel_limits_i9xx_lvds = {
277 .dot = { .min = 20000, .max = 400000 },
278 .vco = { .min = 1400000, .max = 2800000 },
279 .n = { .min = 1, .max = 6 },
280 .m = { .min = 70, .max = 120 },
281 .m1 = { .min = 8, .max = 18 },
282 .m2 = { .min = 3, .max = 7 },
283 .p = { .min = 7, .max = 98 },
284 .p1 = { .min = 1, .max = 8 },
285 .p2 = { .dot_limit = 112000,
286 .p2_slow = 14, .p2_fast = 7 },
290 static const struct intel_limit intel_limits_g4x_sdvo = {
291 .dot = { .min = 25000, .max = 270000 },
292 .vco = { .min = 1750000, .max = 3500000},
293 .n = { .min = 1, .max = 4 },
294 .m = { .min = 104, .max = 138 },
295 .m1 = { .min = 17, .max = 23 },
296 .m2 = { .min = 5, .max = 11 },
297 .p = { .min = 10, .max = 30 },
298 .p1 = { .min = 1, .max = 3},
299 .p2 = { .dot_limit = 270000,
305 static const struct intel_limit intel_limits_g4x_hdmi = {
306 .dot = { .min = 22000, .max = 400000 },
307 .vco = { .min = 1750000, .max = 3500000},
308 .n = { .min = 1, .max = 4 },
309 .m = { .min = 104, .max = 138 },
310 .m1 = { .min = 16, .max = 23 },
311 .m2 = { .min = 5, .max = 11 },
312 .p = { .min = 5, .max = 80 },
313 .p1 = { .min = 1, .max = 8},
314 .p2 = { .dot_limit = 165000,
315 .p2_slow = 10, .p2_fast = 5 },
318 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
319 .dot = { .min = 20000, .max = 115000 },
320 .vco = { .min = 1750000, .max = 3500000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 104, .max = 138 },
323 .m1 = { .min = 17, .max = 23 },
324 .m2 = { .min = 5, .max = 11 },
325 .p = { .min = 28, .max = 112 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 0,
328 .p2_slow = 14, .p2_fast = 14
332 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
333 .dot = { .min = 80000, .max = 224000 },
334 .vco = { .min = 1750000, .max = 3500000 },
335 .n = { .min = 1, .max = 3 },
336 .m = { .min = 104, .max = 138 },
337 .m1 = { .min = 17, .max = 23 },
338 .m2 = { .min = 5, .max = 11 },
339 .p = { .min = 14, .max = 42 },
340 .p1 = { .min = 2, .max = 6 },
341 .p2 = { .dot_limit = 0,
342 .p2_slow = 7, .p2_fast = 7
346 static const struct intel_limit intel_limits_pineview_sdvo = {
347 .dot = { .min = 20000, .max = 400000},
348 .vco = { .min = 1700000, .max = 3500000 },
349 /* Pineview's Ncounter is a ring counter */
350 .n = { .min = 3, .max = 6 },
351 .m = { .min = 2, .max = 256 },
352 /* Pineview only has one combined m divider, which we treat as m2. */
353 .m1 = { .min = 0, .max = 0 },
354 .m2 = { .min = 0, .max = 254 },
355 .p = { .min = 5, .max = 80 },
356 .p1 = { .min = 1, .max = 8 },
357 .p2 = { .dot_limit = 200000,
358 .p2_slow = 10, .p2_fast = 5 },
361 static const struct intel_limit intel_limits_pineview_lvds = {
362 .dot = { .min = 20000, .max = 400000 },
363 .vco = { .min = 1700000, .max = 3500000 },
364 .n = { .min = 3, .max = 6 },
365 .m = { .min = 2, .max = 256 },
366 .m1 = { .min = 0, .max = 0 },
367 .m2 = { .min = 0, .max = 254 },
368 .p = { .min = 7, .max = 112 },
369 .p1 = { .min = 1, .max = 8 },
370 .p2 = { .dot_limit = 112000,
371 .p2_slow = 14, .p2_fast = 14 },
374 /* Ironlake / Sandybridge
376 * We calculate clock using (register_value + 2) for N/M1/M2, so here
377 * the range value for them is (actual_value - 2).
379 static const struct intel_limit intel_limits_ironlake_dac = {
380 .dot = { .min = 25000, .max = 350000 },
381 .vco = { .min = 1760000, .max = 3510000 },
382 .n = { .min = 1, .max = 5 },
383 .m = { .min = 79, .max = 127 },
384 .m1 = { .min = 12, .max = 22 },
385 .m2 = { .min = 5, .max = 9 },
386 .p = { .min = 5, .max = 80 },
387 .p1 = { .min = 1, .max = 8 },
388 .p2 = { .dot_limit = 225000,
389 .p2_slow = 10, .p2_fast = 5 },
392 static const struct intel_limit intel_limits_ironlake_single_lvds = {
393 .dot = { .min = 25000, .max = 350000 },
394 .vco = { .min = 1760000, .max = 3510000 },
395 .n = { .min = 1, .max = 3 },
396 .m = { .min = 79, .max = 118 },
397 .m1 = { .min = 12, .max = 22 },
398 .m2 = { .min = 5, .max = 9 },
399 .p = { .min = 28, .max = 112 },
400 .p1 = { .min = 2, .max = 8 },
401 .p2 = { .dot_limit = 225000,
402 .p2_slow = 14, .p2_fast = 14 },
405 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
406 .dot = { .min = 25000, .max = 350000 },
407 .vco = { .min = 1760000, .max = 3510000 },
408 .n = { .min = 1, .max = 3 },
409 .m = { .min = 79, .max = 127 },
410 .m1 = { .min = 12, .max = 22 },
411 .m2 = { .min = 5, .max = 9 },
412 .p = { .min = 14, .max = 56 },
413 .p1 = { .min = 2, .max = 8 },
414 .p2 = { .dot_limit = 225000,
415 .p2_slow = 7, .p2_fast = 7 },
418 /* LVDS 100mhz refclk limits. */
419 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
420 .dot = { .min = 25000, .max = 350000 },
421 .vco = { .min = 1760000, .max = 3510000 },
422 .n = { .min = 1, .max = 2 },
423 .m = { .min = 79, .max = 126 },
424 .m1 = { .min = 12, .max = 22 },
425 .m2 = { .min = 5, .max = 9 },
426 .p = { .min = 28, .max = 112 },
427 .p1 = { .min = 2, .max = 8 },
428 .p2 = { .dot_limit = 225000,
429 .p2_slow = 14, .p2_fast = 14 },
432 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
433 .dot = { .min = 25000, .max = 350000 },
434 .vco = { .min = 1760000, .max = 3510000 },
435 .n = { .min = 1, .max = 3 },
436 .m = { .min = 79, .max = 126 },
437 .m1 = { .min = 12, .max = 22 },
438 .m2 = { .min = 5, .max = 9 },
439 .p = { .min = 14, .max = 42 },
440 .p1 = { .min = 2, .max = 6 },
441 .p2 = { .dot_limit = 225000,
442 .p2_slow = 7, .p2_fast = 7 },
445 static const struct intel_limit intel_limits_vlv = {
447 * These are the data rate limits (measured in fast clocks)
448 * since those are the strictest limits we have. The fast
449 * clock and actual rate limits are more relaxed, so checking
450 * them would make no difference.
452 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
453 .vco = { .min = 4000000, .max = 6000000 },
454 .n = { .min = 1, .max = 7 },
455 .m1 = { .min = 2, .max = 3 },
456 .m2 = { .min = 11, .max = 156 },
457 .p1 = { .min = 2, .max = 3 },
458 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
461 static const struct intel_limit intel_limits_chv = {
463 * These are the data rate limits (measured in fast clocks)
464 * since those are the strictest limits we have. The fast
465 * clock and actual rate limits are more relaxed, so checking
466 * them would make no difference.
468 .dot = { .min = 25000 * 5, .max = 540000 * 5},
469 .vco = { .min = 4800000, .max = 6480000 },
470 .n = { .min = 1, .max = 1 },
471 .m1 = { .min = 2, .max = 2 },
472 .m2 = { .min = 24 << 22, .max = 175 << 22 },
473 .p1 = { .min = 2, .max = 4 },
474 .p2 = { .p2_slow = 1, .p2_fast = 14 },
477 static const struct intel_limit intel_limits_bxt = {
478 /* FIXME: find real dot limits */
479 .dot = { .min = 0, .max = INT_MAX },
480 .vco = { .min = 4800000, .max = 6700000 },
481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 /* FIXME: find real m2 limits */
484 .m2 = { .min = 2 << 22, .max = 255 << 22 },
485 .p1 = { .min = 2, .max = 4 },
486 .p2 = { .p2_slow = 1, .p2_fast = 20 },
489 /* WA Display #0827: Gen9:all */
491 skl_wa_827(struct drm_i915_private *dev_priv, int pipe, bool enable)
494 I915_WRITE(CLKGATE_DIS_PSL(pipe),
495 I915_READ(CLKGATE_DIS_PSL(pipe)) |
496 DUPS1_GATING_DIS | DUPS2_GATING_DIS);
498 I915_WRITE(CLKGATE_DIS_PSL(pipe),
499 I915_READ(CLKGATE_DIS_PSL(pipe)) &
500 ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
503 /* Wa_2006604312:icl */
505 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
509 I915_WRITE(CLKGATE_DIS_PSL(pipe),
510 I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
512 I915_WRITE(CLKGATE_DIS_PSL(pipe),
513 I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
517 needs_modeset(const struct drm_crtc_state *state)
519 return drm_atomic_crtc_needs_modeset(state);
523 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
524 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
525 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
526 * The helpers' return value is the rate of the clock that is fed to the
527 * display engine's pipe which can be the above fast dot clock rate or a
528 * divided-down version of it.
530 /* m1 is reserved as 0 in Pineview, n is a ring counter */
531 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
533 clock->m = clock->m2 + 2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
537 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
538 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
543 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
545 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
548 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
550 clock->m = i9xx_dpll_compute_m(clock);
551 clock->p = clock->p1 * clock->p2;
552 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
554 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
555 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
560 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
562 clock->m = clock->m1 * clock->m2;
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n == 0 || clock->p == 0))
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
569 return clock->dot / 5;
572 int chv_calc_dpll_params(int refclk, struct dpll *clock)
574 clock->m = clock->m1 * clock->m2;
575 clock->p = clock->p1 * clock->p2;
576 if (WARN_ON(clock->n == 0 || clock->p == 0))
578 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
580 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
582 return clock->dot / 5;
585 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
588 * Returns whether the given set of divisors are valid for a given refclk with
589 * the given connectors.
591 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
592 const struct intel_limit *limit,
593 const struct dpll *clock)
595 if (clock->n < limit->n.min || limit->n.max < clock->n)
596 INTELPllInvalid("n out of range\n");
597 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
598 INTELPllInvalid("p1 out of range\n");
599 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
600 INTELPllInvalid("m2 out of range\n");
601 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
602 INTELPllInvalid("m1 out of range\n");
604 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
605 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
606 if (clock->m1 <= clock->m2)
607 INTELPllInvalid("m1 <= m2\n");
609 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
610 !IS_GEN9_LP(dev_priv)) {
611 if (clock->p < limit->p.min || limit->p.max < clock->p)
612 INTELPllInvalid("p out of range\n");
613 if (clock->m < limit->m.min || limit->m.max < clock->m)
614 INTELPllInvalid("m out of range\n");
617 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
618 INTELPllInvalid("vco out of range\n");
619 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
620 * connector, etc., rather than just a single range.
622 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
623 INTELPllInvalid("dot out of range\n");
629 i9xx_select_p2_div(const struct intel_limit *limit,
630 const struct intel_crtc_state *crtc_state,
633 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
635 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
641 if (intel_is_dual_link_lvds(dev_priv))
642 return limit->p2.p2_fast;
644 return limit->p2.p2_slow;
646 if (target < limit->p2.dot_limit)
647 return limit->p2.p2_slow;
649 return limit->p2.p2_fast;
654 * Returns a set of divisors for the desired target clock with the given
655 * refclk, or FALSE. The returned values represent the clock equation:
656 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
658 * Target and reference clocks are specified in kHz.
660 * If match_clock is provided, then best_clock P divider must match the P
661 * divider from @match_clock used for LVDS downclocking.
664 i9xx_find_best_dpll(const struct intel_limit *limit,
665 struct intel_crtc_state *crtc_state,
666 int target, int refclk, struct dpll *match_clock,
667 struct dpll *best_clock)
669 struct drm_device *dev = crtc_state->base.crtc->dev;
673 memset(best_clock, 0, sizeof(*best_clock));
675 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
677 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
679 for (clock.m2 = limit->m2.min;
680 clock.m2 <= limit->m2.max; clock.m2++) {
681 if (clock.m2 >= clock.m1)
683 for (clock.n = limit->n.min;
684 clock.n <= limit->n.max; clock.n++) {
685 for (clock.p1 = limit->p1.min;
686 clock.p1 <= limit->p1.max; clock.p1++) {
689 i9xx_calc_dpll_params(refclk, &clock);
690 if (!intel_PLL_is_valid(to_i915(dev),
695 clock.p != match_clock->p)
698 this_err = abs(clock.dot - target);
699 if (this_err < err) {
708 return (err != target);
712 * Returns a set of divisors for the desired target clock with the given
713 * refclk, or FALSE. The returned values represent the clock equation:
714 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
716 * Target and reference clocks are specified in kHz.
718 * If match_clock is provided, then best_clock P divider must match the P
719 * divider from @match_clock used for LVDS downclocking.
722 pnv_find_best_dpll(const struct intel_limit *limit,
723 struct intel_crtc_state *crtc_state,
724 int target, int refclk, struct dpll *match_clock,
725 struct dpll *best_clock)
727 struct drm_device *dev = crtc_state->base.crtc->dev;
731 memset(best_clock, 0, sizeof(*best_clock));
733 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
735 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
737 for (clock.m2 = limit->m2.min;
738 clock.m2 <= limit->m2.max; clock.m2++) {
739 for (clock.n = limit->n.min;
740 clock.n <= limit->n.max; clock.n++) {
741 for (clock.p1 = limit->p1.min;
742 clock.p1 <= limit->p1.max; clock.p1++) {
745 pnv_calc_dpll_params(refclk, &clock);
746 if (!intel_PLL_is_valid(to_i915(dev),
751 clock.p != match_clock->p)
754 this_err = abs(clock.dot - target);
755 if (this_err < err) {
764 return (err != target);
768 * Returns a set of divisors for the desired target clock with the given
769 * refclk, or FALSE. The returned values represent the clock equation:
770 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
772 * Target and reference clocks are specified in kHz.
774 * If match_clock is provided, then best_clock P divider must match the P
775 * divider from @match_clock used for LVDS downclocking.
778 g4x_find_best_dpll(const struct intel_limit *limit,
779 struct intel_crtc_state *crtc_state,
780 int target, int refclk, struct dpll *match_clock,
781 struct dpll *best_clock)
783 struct drm_device *dev = crtc_state->base.crtc->dev;
787 /* approximately equals target * 0.00585 */
788 int err_most = (target >> 8) + (target >> 9);
790 memset(best_clock, 0, sizeof(*best_clock));
792 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
794 max_n = limit->n.max;
795 /* based on hardware requirement, prefer smaller n to precision */
796 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
797 /* based on hardware requirement, prefere larger m1,m2 */
798 for (clock.m1 = limit->m1.max;
799 clock.m1 >= limit->m1.min; clock.m1--) {
800 for (clock.m2 = limit->m2.max;
801 clock.m2 >= limit->m2.min; clock.m2--) {
802 for (clock.p1 = limit->p1.max;
803 clock.p1 >= limit->p1.min; clock.p1--) {
806 i9xx_calc_dpll_params(refclk, &clock);
807 if (!intel_PLL_is_valid(to_i915(dev),
812 this_err = abs(clock.dot - target);
813 if (this_err < err_most) {
827 * Check if the calculated PLL configuration is more optimal compared to the
828 * best configuration and error found so far. Return the calculated error.
830 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
831 const struct dpll *calculated_clock,
832 const struct dpll *best_clock,
833 unsigned int best_error_ppm,
834 unsigned int *error_ppm)
837 * For CHV ignore the error and consider only the P value.
838 * Prefer a bigger P value based on HW requirements.
840 if (IS_CHERRYVIEW(to_i915(dev))) {
843 return calculated_clock->p > best_clock->p;
846 if (WARN_ON_ONCE(!target_freq))
849 *error_ppm = div_u64(1000000ULL *
850 abs(target_freq - calculated_clock->dot),
853 * Prefer a better P value over a better (smaller) error if the error
854 * is small. Ensure this preference for future configurations too by
855 * setting the error to 0.
857 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
863 return *error_ppm + 10 < best_error_ppm;
867 * Returns a set of divisors for the desired target clock with the given
868 * refclk, or FALSE. The returned values represent the clock equation:
869 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
872 vlv_find_best_dpll(const struct intel_limit *limit,
873 struct intel_crtc_state *crtc_state,
874 int target, int refclk, struct dpll *match_clock,
875 struct dpll *best_clock)
877 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
878 struct drm_device *dev = crtc->base.dev;
880 unsigned int bestppm = 1000000;
881 /* min update 19.2 MHz */
882 int max_n = min(limit->n.max, refclk / 19200);
885 target *= 5; /* fast clock */
887 memset(best_clock, 0, sizeof(*best_clock));
889 /* based on hardware requirement, prefer smaller n to precision */
890 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
891 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
892 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
893 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
894 clock.p = clock.p1 * clock.p2;
895 /* based on hardware requirement, prefer bigger m1,m2 values */
896 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
899 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
902 vlv_calc_dpll_params(refclk, &clock);
904 if (!intel_PLL_is_valid(to_i915(dev),
909 if (!vlv_PLL_is_optimal(dev, target,
927 * Returns a set of divisors for the desired target clock with the given
928 * refclk, or FALSE. The returned values represent the clock equation:
929 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
932 chv_find_best_dpll(const struct intel_limit *limit,
933 struct intel_crtc_state *crtc_state,
934 int target, int refclk, struct dpll *match_clock,
935 struct dpll *best_clock)
937 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
938 struct drm_device *dev = crtc->base.dev;
939 unsigned int best_error_ppm;
944 memset(best_clock, 0, sizeof(*best_clock));
945 best_error_ppm = 1000000;
948 * Based on hardware doc, the n always set to 1, and m1 always
949 * set to 2. If requires to support 200Mhz refclk, we need to
950 * revisit this because n may not 1 anymore.
952 clock.n = 1, clock.m1 = 2;
953 target *= 5; /* fast clock */
955 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
956 for (clock.p2 = limit->p2.p2_fast;
957 clock.p2 >= limit->p2.p2_slow;
958 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
959 unsigned int error_ppm;
961 clock.p = clock.p1 * clock.p2;
963 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
966 if (m2 > INT_MAX/clock.m1)
971 chv_calc_dpll_params(refclk, &clock);
973 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
976 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
977 best_error_ppm, &error_ppm))
981 best_error_ppm = error_ppm;
989 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
990 struct dpll *best_clock)
993 const struct intel_limit *limit = &intel_limits_bxt;
995 return chv_find_best_dpll(limit, crtc_state,
996 crtc_state->port_clock, refclk,
1000 bool intel_crtc_active(struct intel_crtc *crtc)
1002 /* Be paranoid as we can arrive here with only partial
1003 * state retrieved from the hardware during setup.
1005 * We can ditch the adjusted_mode.crtc_clock check as soon
1006 * as Haswell has gained clock readout/fastboot support.
1008 * We can ditch the crtc->primary->state->fb check as soon as we can
1009 * properly reconstruct framebuffers.
1011 * FIXME: The intel_crtc->active here should be switched to
1012 * crtc->state->active once we have proper CRTC states wired up
1015 return crtc->active && crtc->base.primary->state->fb &&
1016 crtc->config->base.adjusted_mode.crtc_clock;
1019 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1022 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1024 return crtc->config->cpu_transcoder;
1027 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1030 i915_reg_t reg = PIPEDSL(pipe);
1034 if (IS_GEN(dev_priv, 2))
1035 line_mask = DSL_LINEMASK_GEN2;
1037 line_mask = DSL_LINEMASK_GEN3;
1039 line1 = I915_READ(reg) & line_mask;
1041 line2 = I915_READ(reg) & line_mask;
1043 return line1 != line2;
1046 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1048 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1049 enum pipe pipe = crtc->pipe;
1051 /* Wait for the display line to settle/start moving */
1052 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1053 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1054 pipe_name(pipe), onoff(state));
1057 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1059 wait_for_pipe_scanline_moving(crtc, false);
1062 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1064 wait_for_pipe_scanline_moving(crtc, true);
1068 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1070 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1071 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1073 if (INTEL_GEN(dev_priv) >= 4) {
1074 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1075 i915_reg_t reg = PIPECONF(cpu_transcoder);
1077 /* Wait for the Pipe State to go off */
1078 if (intel_wait_for_register(&dev_priv->uncore,
1079 reg, I965_PIPECONF_ACTIVE, 0,
1081 WARN(1, "pipe_off wait timed out\n");
1083 intel_wait_for_pipe_scanline_stopped(crtc);
1087 /* Only for pre-ILK configs */
1088 void assert_pll(struct drm_i915_private *dev_priv,
1089 enum pipe pipe, bool state)
1094 val = I915_READ(DPLL(pipe));
1095 cur_state = !!(val & DPLL_VCO_ENABLE);
1096 I915_STATE_WARN(cur_state != state,
1097 "PLL state assertion failure (expected %s, current %s)\n",
1098 onoff(state), onoff(cur_state));
1101 /* XXX: the dsi pll is shared between MIPI DSI ports */
1102 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1107 vlv_cck_get(dev_priv);
1108 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1109 vlv_cck_put(dev_priv);
1111 cur_state = val & DSI_PLL_VCO_EN;
1112 I915_STATE_WARN(cur_state != state,
1113 "DSI PLL state assertion failure (expected %s, current %s)\n",
1114 onoff(state), onoff(cur_state));
1117 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1118 enum pipe pipe, bool state)
1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1124 if (HAS_DDI(dev_priv)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1127 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129 u32 val = I915_READ(FDI_TX_CTL(pipe));
1130 cur_state = !!(val & FDI_TX_ENABLE);
1132 I915_STATE_WARN(cur_state != state,
1133 "FDI TX state assertion failure (expected %s, current %s)\n",
1134 onoff(state), onoff(cur_state));
1136 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1137 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1139 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1140 enum pipe pipe, bool state)
1145 val = I915_READ(FDI_RX_CTL(pipe));
1146 cur_state = !!(val & FDI_RX_ENABLE);
1147 I915_STATE_WARN(cur_state != state,
1148 "FDI RX state assertion failure (expected %s, current %s)\n",
1149 onoff(state), onoff(cur_state));
1151 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1152 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1154 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 /* ILK FDI PLL is always enabled */
1160 if (IS_GEN(dev_priv, 5))
1163 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1164 if (HAS_DDI(dev_priv))
1167 val = I915_READ(FDI_TX_CTL(pipe));
1168 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1171 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1172 enum pipe pipe, bool state)
1177 val = I915_READ(FDI_RX_CTL(pipe));
1178 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1179 I915_STATE_WARN(cur_state != state,
1180 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1181 onoff(state), onoff(cur_state));
1184 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1188 enum pipe panel_pipe = INVALID_PIPE;
1191 if (WARN_ON(HAS_DDI(dev_priv)))
1194 if (HAS_PCH_SPLIT(dev_priv)) {
1197 pp_reg = PP_CONTROL(0);
1198 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1201 case PANEL_PORT_SELECT_LVDS:
1202 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1204 case PANEL_PORT_SELECT_DPA:
1205 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1207 case PANEL_PORT_SELECT_DPC:
1208 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1210 case PANEL_PORT_SELECT_DPD:
1211 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1214 MISSING_CASE(port_sel);
1217 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg = PP_CONTROL(pipe);
1224 pp_reg = PP_CONTROL(0);
1225 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1227 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1228 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1231 val = I915_READ(pp_reg);
1232 if (!(val & PANEL_POWER_ON) ||
1233 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1236 I915_STATE_WARN(panel_pipe == pipe && locked,
1237 "panel assertion failure, pipe %c regs locked\n",
1241 void assert_pipe(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, bool state)
1245 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1247 enum intel_display_power_domain power_domain;
1248 intel_wakeref_t wakeref;
1250 /* we keep both pipes enabled on 830 */
1251 if (IS_I830(dev_priv))
1254 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1255 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1257 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1258 cur_state = !!(val & PIPECONF_ENABLE);
1260 intel_display_power_put(dev_priv, power_domain, wakeref);
1265 I915_STATE_WARN(cur_state != state,
1266 "pipe %c assertion failure (expected %s, current %s)\n",
1267 pipe_name(pipe), onoff(state), onoff(cur_state));
1270 static void assert_plane(struct intel_plane *plane, bool state)
1275 cur_state = plane->get_hw_state(plane, &pipe);
1277 I915_STATE_WARN(cur_state != state,
1278 "%s assertion failure (expected %s, current %s)\n",
1279 plane->base.name, onoff(state), onoff(cur_state));
1282 #define assert_plane_enabled(p) assert_plane(p, true)
1283 #define assert_plane_disabled(p) assert_plane(p, false)
1285 static void assert_planes_disabled(struct intel_crtc *crtc)
1287 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1288 struct intel_plane *plane;
1290 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1291 assert_plane_disabled(plane);
1294 static void assert_vblank_disabled(struct drm_crtc *crtc)
1296 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1297 drm_crtc_vblank_put(crtc);
1300 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1306 val = I915_READ(PCH_TRANSCONF(pipe));
1307 enabled = !!(val & TRANS_ENABLE);
1308 I915_STATE_WARN(enabled,
1309 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1313 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1314 enum pipe pipe, enum port port,
1317 enum pipe port_pipe;
1320 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1322 I915_STATE_WARN(state && port_pipe == pipe,
1323 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1324 port_name(port), pipe_name(pipe));
1326 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1327 "IBX PCH DP %c still using transcoder B\n",
1331 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, enum port port,
1333 i915_reg_t hdmi_reg)
1335 enum pipe port_pipe;
1338 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1340 I915_STATE_WARN(state && port_pipe == pipe,
1341 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1342 port_name(port), pipe_name(pipe));
1344 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1345 "IBX PCH HDMI %c still using transcoder B\n",
1349 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1352 enum pipe port_pipe;
1354 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1355 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1356 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1358 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1360 "PCH VGA enabled on transcoder %c, should be disabled\n",
1363 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1365 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1368 /* PCH SDVOB multiplex with HDMIB */
1369 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1370 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1371 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1374 static void _vlv_enable_pll(struct intel_crtc *crtc,
1375 const struct intel_crtc_state *pipe_config)
1377 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1378 enum pipe pipe = crtc->pipe;
1380 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1381 POSTING_READ(DPLL(pipe));
1384 if (intel_wait_for_register(&dev_priv->uncore,
1389 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1392 static void vlv_enable_pll(struct intel_crtc *crtc,
1393 const struct intel_crtc_state *pipe_config)
1395 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1396 enum pipe pipe = crtc->pipe;
1398 assert_pipe_disabled(dev_priv, pipe);
1400 /* PLL is protected by panel, make sure we can write it */
1401 assert_panel_unlocked(dev_priv, pipe);
1403 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1404 _vlv_enable_pll(crtc, pipe_config);
1406 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1407 POSTING_READ(DPLL_MD(pipe));
1411 static void _chv_enable_pll(struct intel_crtc *crtc,
1412 const struct intel_crtc_state *pipe_config)
1414 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1415 enum pipe pipe = crtc->pipe;
1416 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1419 vlv_dpio_get(dev_priv);
1421 /* Enable back the 10bit clock to display controller */
1422 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1423 tmp |= DPIO_DCLKP_EN;
1424 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1426 vlv_dpio_put(dev_priv);
1429 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1434 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1436 /* Check PLL is locked */
1437 if (intel_wait_for_register(&dev_priv->uncore,
1438 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1440 DRM_ERROR("PLL %d failed to lock\n", pipe);
1443 static void chv_enable_pll(struct intel_crtc *crtc,
1444 const struct intel_crtc_state *pipe_config)
1446 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1447 enum pipe pipe = crtc->pipe;
1449 assert_pipe_disabled(dev_priv, pipe);
1451 /* PLL is protected by panel, make sure we can write it */
1452 assert_panel_unlocked(dev_priv, pipe);
1454 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1455 _chv_enable_pll(crtc, pipe_config);
1457 if (pipe != PIPE_A) {
1459 * WaPixelRepeatModeFixForC0:chv
1461 * DPLLCMD is AWOL. Use chicken bits to propagate
1462 * the value from DPLLBMD to either pipe B or C.
1464 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1465 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1466 I915_WRITE(CBR4_VLV, 0);
1467 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1470 * DPLLB VGA mode also seems to cause problems.
1471 * We should always have it disabled.
1473 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1475 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1476 POSTING_READ(DPLL_MD(pipe));
1480 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1482 if (IS_I830(dev_priv))
1485 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1488 static void i9xx_enable_pll(struct intel_crtc *crtc,
1489 const struct intel_crtc_state *crtc_state)
1491 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1492 i915_reg_t reg = DPLL(crtc->pipe);
1493 u32 dpll = crtc_state->dpll_hw_state.dpll;
1496 assert_pipe_disabled(dev_priv, crtc->pipe);
1498 /* PLL is protected by panel, make sure we can write it */
1499 if (i9xx_has_pps(dev_priv))
1500 assert_panel_unlocked(dev_priv, crtc->pipe);
1503 * Apparently we need to have VGA mode enabled prior to changing
1504 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1505 * dividers, even though the register value does change.
1507 I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1508 I915_WRITE(reg, dpll);
1510 /* Wait for the clocks to stabilize. */
1514 if (INTEL_GEN(dev_priv) >= 4) {
1515 I915_WRITE(DPLL_MD(crtc->pipe),
1516 crtc_state->dpll_hw_state.dpll_md);
1518 /* The pixel multiplier can only be updated once the
1519 * DPLL is enabled and the clocks are stable.
1521 * So write it again.
1523 I915_WRITE(reg, dpll);
1526 /* We do this three times for luck */
1527 for (i = 0; i < 3; i++) {
1528 I915_WRITE(reg, dpll);
1530 udelay(150); /* wait for warmup */
1534 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1536 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1537 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1538 enum pipe pipe = crtc->pipe;
1540 /* Don't disable pipe or pipe PLLs if needed */
1541 if (IS_I830(dev_priv))
1544 /* Make sure the pipe isn't still relying on us */
1545 assert_pipe_disabled(dev_priv, pipe);
1547 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1548 POSTING_READ(DPLL(pipe));
1551 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1555 /* Make sure the pipe isn't still relying on us */
1556 assert_pipe_disabled(dev_priv, pipe);
1558 val = DPLL_INTEGRATED_REF_CLK_VLV |
1559 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1561 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1563 I915_WRITE(DPLL(pipe), val);
1564 POSTING_READ(DPLL(pipe));
1567 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1569 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1572 /* Make sure the pipe isn't still relying on us */
1573 assert_pipe_disabled(dev_priv, pipe);
1575 val = DPLL_SSC_REF_CLK_CHV |
1576 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1578 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1580 I915_WRITE(DPLL(pipe), val);
1581 POSTING_READ(DPLL(pipe));
1583 vlv_dpio_get(dev_priv);
1585 /* Disable 10bit clock to display controller */
1586 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1587 val &= ~DPIO_DCLKP_EN;
1588 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1590 vlv_dpio_put(dev_priv);
1593 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1594 struct intel_digital_port *dport,
1595 unsigned int expected_mask)
1598 i915_reg_t dpll_reg;
1600 switch (dport->base.port) {
1602 port_mask = DPLL_PORTB_READY_MASK;
1606 port_mask = DPLL_PORTC_READY_MASK;
1608 expected_mask <<= 4;
1611 port_mask = DPLL_PORTD_READY_MASK;
1612 dpll_reg = DPIO_PHY_STATUS;
1618 if (intel_wait_for_register(&dev_priv->uncore,
1619 dpll_reg, port_mask, expected_mask,
1621 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1622 port_name(dport->base.port),
1623 I915_READ(dpll_reg) & port_mask, expected_mask);
1626 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1628 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1629 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1630 enum pipe pipe = crtc->pipe;
1632 u32 val, pipeconf_val;
1634 /* Make sure PCH DPLL is enabled */
1635 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1637 /* FDI must be feeding us bits for PCH ports */
1638 assert_fdi_tx_enabled(dev_priv, pipe);
1639 assert_fdi_rx_enabled(dev_priv, pipe);
1641 if (HAS_PCH_CPT(dev_priv)) {
1642 /* Workaround: Set the timing override bit before enabling the
1643 * pch transcoder. */
1644 reg = TRANS_CHICKEN2(pipe);
1645 val = I915_READ(reg);
1646 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1647 I915_WRITE(reg, val);
1650 reg = PCH_TRANSCONF(pipe);
1651 val = I915_READ(reg);
1652 pipeconf_val = I915_READ(PIPECONF(pipe));
1654 if (HAS_PCH_IBX(dev_priv)) {
1656 * Make the BPC in transcoder be consistent with
1657 * that in pipeconf reg. For HDMI we must use 8bpc
1658 * here for both 8bpc and 12bpc.
1660 val &= ~PIPECONF_BPC_MASK;
1661 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1662 val |= PIPECONF_8BPC;
1664 val |= pipeconf_val & PIPECONF_BPC_MASK;
1667 val &= ~TRANS_INTERLACE_MASK;
1668 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1669 if (HAS_PCH_IBX(dev_priv) &&
1670 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1671 val |= TRANS_LEGACY_INTERLACED_ILK;
1673 val |= TRANS_INTERLACED;
1675 val |= TRANS_PROGRESSIVE;
1678 I915_WRITE(reg, val | TRANS_ENABLE);
1679 if (intel_wait_for_register(&dev_priv->uncore,
1680 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1682 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1685 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1686 enum transcoder cpu_transcoder)
1688 u32 val, pipeconf_val;
1690 /* FDI must be feeding us bits for PCH ports */
1691 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1692 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1694 /* Workaround: set timing override bit. */
1695 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1696 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1697 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1700 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1702 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1703 PIPECONF_INTERLACED_ILK)
1704 val |= TRANS_INTERLACED;
1706 val |= TRANS_PROGRESSIVE;
1708 I915_WRITE(LPT_TRANSCONF, val);
1709 if (intel_wait_for_register(&dev_priv->uncore,
1714 DRM_ERROR("Failed to enable PCH transcoder\n");
1717 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1723 /* FDI relies on the transcoder */
1724 assert_fdi_tx_disabled(dev_priv, pipe);
1725 assert_fdi_rx_disabled(dev_priv, pipe);
1727 /* Ports must be off as well */
1728 assert_pch_ports_disabled(dev_priv, pipe);
1730 reg = PCH_TRANSCONF(pipe);
1731 val = I915_READ(reg);
1732 val &= ~TRANS_ENABLE;
1733 I915_WRITE(reg, val);
1734 /* wait for PCH transcoder off, transcoder state */
1735 if (intel_wait_for_register(&dev_priv->uncore,
1736 reg, TRANS_STATE_ENABLE, 0,
1738 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1740 if (HAS_PCH_CPT(dev_priv)) {
1741 /* Workaround: Clear the timing override chicken bit again. */
1742 reg = TRANS_CHICKEN2(pipe);
1743 val = I915_READ(reg);
1744 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1745 I915_WRITE(reg, val);
1749 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1753 val = I915_READ(LPT_TRANSCONF);
1754 val &= ~TRANS_ENABLE;
1755 I915_WRITE(LPT_TRANSCONF, val);
1756 /* wait for PCH transcoder off, transcoder state */
1757 if (intel_wait_for_register(&dev_priv->uncore,
1758 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1760 DRM_ERROR("Failed to disable PCH transcoder\n");
1762 /* Workaround: clear timing override bit. */
1763 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1764 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1765 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1768 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1770 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1772 if (HAS_PCH_LPT(dev_priv))
1778 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1780 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1783 * On i965gm the hardware frame counter reads
1784 * zero when the TV encoder is enabled :(
1786 if (IS_I965GM(dev_priv) &&
1787 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1790 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1791 return 0xffffffff; /* full 32 bit counter */
1792 else if (INTEL_GEN(dev_priv) >= 3)
1793 return 0xffffff; /* only 24 bits of frame count */
1795 return 0; /* Gen2 doesn't have a hardware frame counter */
1798 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1800 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1802 drm_crtc_set_max_vblank_count(&crtc->base,
1803 intel_crtc_max_vblank_count(crtc_state));
1804 drm_crtc_vblank_on(&crtc->base);
1807 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1809 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1810 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1811 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1812 enum pipe pipe = crtc->pipe;
1816 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1818 assert_planes_disabled(crtc);
1821 * A pipe without a PLL won't actually be able to drive bits from
1822 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1825 if (HAS_GMCH(dev_priv)) {
1826 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1827 assert_dsi_pll_enabled(dev_priv);
1829 assert_pll_enabled(dev_priv, pipe);
1831 if (new_crtc_state->has_pch_encoder) {
1832 /* if driving the PCH, we need FDI enabled */
1833 assert_fdi_rx_pll_enabled(dev_priv,
1834 intel_crtc_pch_transcoder(crtc));
1835 assert_fdi_tx_pll_enabled(dev_priv,
1836 (enum pipe) cpu_transcoder);
1838 /* FIXME: assert CPU port conditions for SNB+ */
1841 trace_intel_pipe_enable(dev_priv, pipe);
1843 reg = PIPECONF(cpu_transcoder);
1844 val = I915_READ(reg);
1845 if (val & PIPECONF_ENABLE) {
1846 /* we keep both pipes enabled on 830 */
1847 WARN_ON(!IS_I830(dev_priv));
1851 I915_WRITE(reg, val | PIPECONF_ENABLE);
1855 * Until the pipe starts PIPEDSL reads will return a stale value,
1856 * which causes an apparent vblank timestamp jump when PIPEDSL
1857 * resets to its proper value. That also messes up the frame count
1858 * when it's derived from the timestamps. So let's wait for the
1859 * pipe to start properly before we call drm_crtc_vblank_on()
1861 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1862 intel_wait_for_pipe_scanline_moving(crtc);
1865 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1867 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1868 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1869 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1870 enum pipe pipe = crtc->pipe;
1874 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1877 * Make sure planes won't keep trying to pump pixels to us,
1878 * or we might hang the display.
1880 assert_planes_disabled(crtc);
1882 trace_intel_pipe_disable(dev_priv, pipe);
1884 reg = PIPECONF(cpu_transcoder);
1885 val = I915_READ(reg);
1886 if ((val & PIPECONF_ENABLE) == 0)
1890 * Double wide has implications for planes
1891 * so best keep it disabled when not needed.
1893 if (old_crtc_state->double_wide)
1894 val &= ~PIPECONF_DOUBLE_WIDE;
1896 /* Don't disable pipe or pipe PLLs if needed */
1897 if (!IS_I830(dev_priv))
1898 val &= ~PIPECONF_ENABLE;
1900 I915_WRITE(reg, val);
1901 if ((val & PIPECONF_ENABLE) == 0)
1902 intel_wait_for_pipe_off(old_crtc_state);
1905 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1907 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1911 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1913 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1914 unsigned int cpp = fb->format->cpp[color_plane];
1916 switch (fb->modifier) {
1917 case DRM_FORMAT_MOD_LINEAR:
1919 case I915_FORMAT_MOD_X_TILED:
1920 if (IS_GEN(dev_priv, 2))
1924 case I915_FORMAT_MOD_Y_TILED_CCS:
1925 if (color_plane == 1)
1928 case I915_FORMAT_MOD_Y_TILED:
1929 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1933 case I915_FORMAT_MOD_Yf_TILED_CCS:
1934 if (color_plane == 1)
1937 case I915_FORMAT_MOD_Yf_TILED:
1953 MISSING_CASE(fb->modifier);
1959 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
1961 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1964 return intel_tile_size(to_i915(fb->dev)) /
1965 intel_tile_width_bytes(fb, color_plane);
1968 /* Return the tile dimensions in pixel units */
1969 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
1970 unsigned int *tile_width,
1971 unsigned int *tile_height)
1973 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
1974 unsigned int cpp = fb->format->cpp[color_plane];
1976 *tile_width = tile_width_bytes / cpp;
1977 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1981 intel_fb_align_height(const struct drm_framebuffer *fb,
1982 int color_plane, unsigned int height)
1984 unsigned int tile_height = intel_tile_height(fb, color_plane);
1986 return ALIGN(height, tile_height);
1989 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1991 unsigned int size = 0;
1994 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
1995 size += rot_info->plane[i].width * rot_info->plane[i].height;
2001 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2002 const struct drm_framebuffer *fb,
2003 unsigned int rotation)
2005 view->type = I915_GGTT_VIEW_NORMAL;
2006 if (drm_rotation_90_or_270(rotation)) {
2007 view->type = I915_GGTT_VIEW_ROTATED;
2008 view->rotated = to_intel_framebuffer(fb)->rot_info;
2012 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2014 if (IS_I830(dev_priv))
2016 else if (IS_I85X(dev_priv))
2018 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2024 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2026 if (INTEL_GEN(dev_priv) >= 9)
2028 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2029 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2031 else if (INTEL_GEN(dev_priv) >= 4)
2037 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2040 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2042 /* AUX_DIST needs only 4K alignment */
2043 if (color_plane == 1)
2046 switch (fb->modifier) {
2047 case DRM_FORMAT_MOD_LINEAR:
2048 return intel_linear_alignment(dev_priv);
2049 case I915_FORMAT_MOD_X_TILED:
2050 if (INTEL_GEN(dev_priv) >= 9)
2053 case I915_FORMAT_MOD_Y_TILED_CCS:
2054 case I915_FORMAT_MOD_Yf_TILED_CCS:
2055 case I915_FORMAT_MOD_Y_TILED:
2056 case I915_FORMAT_MOD_Yf_TILED:
2057 return 1 * 1024 * 1024;
2059 MISSING_CASE(fb->modifier);
2064 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2066 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2067 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2069 return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2073 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2074 const struct i915_ggtt_view *view,
2076 unsigned long *out_flags)
2078 struct drm_device *dev = fb->dev;
2079 struct drm_i915_private *dev_priv = to_i915(dev);
2080 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2081 intel_wakeref_t wakeref;
2082 struct i915_vma *vma;
2083 unsigned int pinctl;
2086 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2088 alignment = intel_surf_alignment(fb, 0);
2090 /* Note that the w/a also requires 64 PTE of padding following the
2091 * bo. We currently fill all unused PTE with the shadow page and so
2092 * we should always have valid PTE following the scanout preventing
2095 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2096 alignment = 256 * 1024;
2099 * Global gtt pte registers are special registers which actually forward
2100 * writes to a chunk of system memory. Which means that there is no risk
2101 * that the register values disappear as soon as we call
2102 * intel_runtime_pm_put(), so it is correct to wrap only the
2103 * pin/unpin/fence and not more.
2105 wakeref = intel_runtime_pm_get(dev_priv);
2107 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2111 /* Valleyview is definitely limited to scanning out the first
2112 * 512MiB. Lets presume this behaviour was inherited from the
2113 * g4x display engine and that all earlier gen are similarly
2114 * limited. Testing suggests that it is a little more
2115 * complicated than this. For example, Cherryview appears quite
2116 * happy to scanout from anywhere within its global aperture.
2118 if (HAS_GMCH(dev_priv))
2119 pinctl |= PIN_MAPPABLE;
2121 vma = i915_gem_object_pin_to_display_plane(obj,
2122 alignment, view, pinctl);
2126 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2129 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2130 * fence, whereas 965+ only requires a fence if using
2131 * framebuffer compression. For simplicity, we always, when
2132 * possible, install a fence as the cost is not that onerous.
2134 * If we fail to fence the tiled scanout, then either the
2135 * modeset will reject the change (which is highly unlikely as
2136 * the affected systems, all but one, do not have unmappable
2137 * space) or we will not be able to enable full powersaving
2138 * techniques (also likely not to apply due to various limits
2139 * FBC and the like impose on the size of the buffer, which
2140 * presumably we violated anyway with this unmappable buffer).
2141 * Anyway, it is presumably better to stumble onwards with
2142 * something and try to run the system in a "less than optimal"
2143 * mode that matches the user configuration.
2145 ret = i915_vma_pin_fence(vma);
2146 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2147 i915_gem_object_unpin_from_display_plane(vma);
2152 if (ret == 0 && vma->fence)
2153 *out_flags |= PLANE_HAS_FENCE;
2158 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2160 intel_runtime_pm_put(dev_priv, wakeref);
2164 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2166 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2168 if (flags & PLANE_HAS_FENCE)
2169 i915_vma_unpin_fence(vma);
2170 i915_gem_object_unpin_from_display_plane(vma);
2174 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2175 unsigned int rotation)
2177 if (drm_rotation_90_or_270(rotation))
2178 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2180 return fb->pitches[color_plane];
2184 * Convert the x/y offsets into a linear offset.
2185 * Only valid with 0/180 degree rotation, which is fine since linear
2186 * offset is only used with linear buffers on pre-hsw and tiled buffers
2187 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2189 u32 intel_fb_xy_to_linear(int x, int y,
2190 const struct intel_plane_state *state,
2193 const struct drm_framebuffer *fb = state->base.fb;
2194 unsigned int cpp = fb->format->cpp[color_plane];
2195 unsigned int pitch = state->color_plane[color_plane].stride;
2197 return y * pitch + x * cpp;
2201 * Add the x/y offsets derived from fb->offsets[] to the user
2202 * specified plane src x/y offsets. The resulting x/y offsets
2203 * specify the start of scanout from the beginning of the gtt mapping.
2205 void intel_add_fb_offsets(int *x, int *y,
2206 const struct intel_plane_state *state,
2210 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2211 unsigned int rotation = state->base.rotation;
2213 if (drm_rotation_90_or_270(rotation)) {
2214 *x += intel_fb->rotated[color_plane].x;
2215 *y += intel_fb->rotated[color_plane].y;
2217 *x += intel_fb->normal[color_plane].x;
2218 *y += intel_fb->normal[color_plane].y;
2222 static u32 intel_adjust_tile_offset(int *x, int *y,
2223 unsigned int tile_width,
2224 unsigned int tile_height,
2225 unsigned int tile_size,
2226 unsigned int pitch_tiles,
2230 unsigned int pitch_pixels = pitch_tiles * tile_width;
2233 WARN_ON(old_offset & (tile_size - 1));
2234 WARN_ON(new_offset & (tile_size - 1));
2235 WARN_ON(new_offset > old_offset);
2237 tiles = (old_offset - new_offset) / tile_size;
2239 *y += tiles / pitch_tiles * tile_height;
2240 *x += tiles % pitch_tiles * tile_width;
2242 /* minimize x in case it got needlessly big */
2243 *y += *x / pitch_pixels * tile_height;
2249 static bool is_surface_linear(u64 modifier, int color_plane)
2251 return modifier == DRM_FORMAT_MOD_LINEAR;
2254 static u32 intel_adjust_aligned_offset(int *x, int *y,
2255 const struct drm_framebuffer *fb,
2257 unsigned int rotation,
2259 u32 old_offset, u32 new_offset)
2261 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2262 unsigned int cpp = fb->format->cpp[color_plane];
2264 WARN_ON(new_offset > old_offset);
2266 if (!is_surface_linear(fb->modifier, color_plane)) {
2267 unsigned int tile_size, tile_width, tile_height;
2268 unsigned int pitch_tiles;
2270 tile_size = intel_tile_size(dev_priv);
2271 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2273 if (drm_rotation_90_or_270(rotation)) {
2274 pitch_tiles = pitch / tile_height;
2275 swap(tile_width, tile_height);
2277 pitch_tiles = pitch / (tile_width * cpp);
2280 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2281 tile_size, pitch_tiles,
2282 old_offset, new_offset);
2284 old_offset += *y * pitch + *x * cpp;
2286 *y = (old_offset - new_offset) / pitch;
2287 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2294 * Adjust the tile offset by moving the difference into
2297 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2298 const struct intel_plane_state *state,
2300 u32 old_offset, u32 new_offset)
2302 return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
2303 state->base.rotation,
2304 state->color_plane[color_plane].stride,
2305 old_offset, new_offset);
2309 * Computes the aligned offset to the base tile and adjusts
2310 * x, y. bytes per pixel is assumed to be a power-of-two.
2312 * In the 90/270 rotated case, x and y are assumed
2313 * to be already rotated to match the rotated GTT view, and
2314 * pitch is the tile_height aligned framebuffer height.
2316 * This function is used when computing the derived information
2317 * under intel_framebuffer, so using any of that information
2318 * here is not allowed. Anything under drm_framebuffer can be
2319 * used. This is why the user has to pass in the pitch since it
2320 * is specified in the rotated orientation.
2322 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2324 const struct drm_framebuffer *fb,
2327 unsigned int rotation,
2330 unsigned int cpp = fb->format->cpp[color_plane];
2331 u32 offset, offset_aligned;
2336 if (!is_surface_linear(fb->modifier, color_plane)) {
2337 unsigned int tile_size, tile_width, tile_height;
2338 unsigned int tile_rows, tiles, pitch_tiles;
2340 tile_size = intel_tile_size(dev_priv);
2341 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2343 if (drm_rotation_90_or_270(rotation)) {
2344 pitch_tiles = pitch / tile_height;
2345 swap(tile_width, tile_height);
2347 pitch_tiles = pitch / (tile_width * cpp);
2350 tile_rows = *y / tile_height;
2353 tiles = *x / tile_width;
2356 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2357 offset_aligned = offset & ~alignment;
2359 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2360 tile_size, pitch_tiles,
2361 offset, offset_aligned);
2363 offset = *y * pitch + *x * cpp;
2364 offset_aligned = offset & ~alignment;
2366 *y = (offset & alignment) / pitch;
2367 *x = ((offset & alignment) - *y * pitch) / cpp;
2370 return offset_aligned;
2373 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2374 const struct intel_plane_state *state,
2377 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2378 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2379 const struct drm_framebuffer *fb = state->base.fb;
2380 unsigned int rotation = state->base.rotation;
2381 int pitch = state->color_plane[color_plane].stride;
2384 if (intel_plane->id == PLANE_CURSOR)
2385 alignment = intel_cursor_alignment(dev_priv);
2387 alignment = intel_surf_alignment(fb, color_plane);
2389 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2390 pitch, rotation, alignment);
2393 /* Convert the fb->offset[] into x/y offsets */
2394 static int intel_fb_offset_to_xy(int *x, int *y,
2395 const struct drm_framebuffer *fb,
2398 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2399 unsigned int height;
2401 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2402 fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2403 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2404 fb->offsets[color_plane], color_plane);
2408 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2409 height = ALIGN(height, intel_tile_height(fb, color_plane));
2411 /* Catch potential overflows early */
2412 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2413 fb->offsets[color_plane])) {
2414 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2415 fb->offsets[color_plane], fb->pitches[color_plane],
2423 intel_adjust_aligned_offset(x, y,
2424 fb, color_plane, DRM_MODE_ROTATE_0,
2425 fb->pitches[color_plane],
2426 fb->offsets[color_plane], 0);
2431 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2433 switch (fb_modifier) {
2434 case I915_FORMAT_MOD_X_TILED:
2435 return I915_TILING_X;
2436 case I915_FORMAT_MOD_Y_TILED:
2437 case I915_FORMAT_MOD_Y_TILED_CCS:
2438 return I915_TILING_Y;
2440 return I915_TILING_NONE;
2445 * From the Sky Lake PRM:
2446 * "The Color Control Surface (CCS) contains the compression status of
2447 * the cache-line pairs. The compression state of the cache-line pair
2448 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2449 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2450 * cache-line-pairs. CCS is always Y tiled."
2452 * Since cache line pairs refers to horizontally adjacent cache lines,
2453 * each cache line in the CCS corresponds to an area of 32x16 cache
2454 * lines on the main surface. Since each pixel is 4 bytes, this gives
2455 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2458 static const struct drm_format_info ccs_formats[] = {
2459 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2460 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2461 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2462 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2465 static const struct drm_format_info *
2466 lookup_format_info(const struct drm_format_info formats[],
2467 int num_formats, u32 format)
2471 for (i = 0; i < num_formats; i++) {
2472 if (formats[i].format == format)
2479 static const struct drm_format_info *
2480 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2482 switch (cmd->modifier[0]) {
2483 case I915_FORMAT_MOD_Y_TILED_CCS:
2484 case I915_FORMAT_MOD_Yf_TILED_CCS:
2485 return lookup_format_info(ccs_formats,
2486 ARRAY_SIZE(ccs_formats),
2493 bool is_ccs_modifier(u64 modifier)
2495 return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2496 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2500 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2501 struct drm_framebuffer *fb)
2503 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2504 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2505 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2506 u32 gtt_offset_rotated = 0;
2507 unsigned int max_size = 0;
2508 int i, num_planes = fb->format->num_planes;
2509 unsigned int tile_size = intel_tile_size(dev_priv);
2511 for (i = 0; i < num_planes; i++) {
2512 unsigned int width, height;
2513 unsigned int cpp, size;
2518 cpp = fb->format->cpp[i];
2519 width = drm_framebuffer_plane_width(fb->width, fb, i);
2520 height = drm_framebuffer_plane_height(fb->height, fb, i);
2522 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2524 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2529 if (is_ccs_modifier(fb->modifier) && i == 1) {
2530 int hsub = fb->format->hsub;
2531 int vsub = fb->format->vsub;
2532 int tile_width, tile_height;
2536 intel_tile_dims(fb, i, &tile_width, &tile_height);
2538 tile_height *= vsub;
2540 ccs_x = (x * hsub) % tile_width;
2541 ccs_y = (y * vsub) % tile_height;
2542 main_x = intel_fb->normal[0].x % tile_width;
2543 main_y = intel_fb->normal[0].y % tile_height;
2546 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2547 * x/y offsets must match between CCS and the main surface.
2549 if (main_x != ccs_x || main_y != ccs_y) {
2550 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2553 intel_fb->normal[0].x,
2554 intel_fb->normal[0].y,
2561 * The fence (if used) is aligned to the start of the object
2562 * so having the framebuffer wrap around across the edge of the
2563 * fenced region doesn't really work. We have no API to configure
2564 * the fence start offset within the object (nor could we probably
2565 * on gen2/3). So it's just easier if we just require that the
2566 * fb layout agrees with the fence layout. We already check that the
2567 * fb stride matches the fence stride elsewhere.
2569 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2570 (x + width) * cpp > fb->pitches[i]) {
2571 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2577 * First pixel of the framebuffer from
2578 * the start of the normal gtt mapping.
2580 intel_fb->normal[i].x = x;
2581 intel_fb->normal[i].y = y;
2583 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2587 offset /= tile_size;
2589 if (!is_surface_linear(fb->modifier, i)) {
2590 unsigned int tile_width, tile_height;
2591 unsigned int pitch_tiles;
2594 intel_tile_dims(fb, i, &tile_width, &tile_height);
2596 rot_info->plane[i].offset = offset;
2597 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2598 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2599 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2601 intel_fb->rotated[i].pitch =
2602 rot_info->plane[i].height * tile_height;
2604 /* how many tiles does this plane need */
2605 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2607 * If the plane isn't horizontally tile aligned,
2608 * we need one more tile.
2613 /* rotate the x/y offsets to match the GTT view */
2619 rot_info->plane[i].width * tile_width,
2620 rot_info->plane[i].height * tile_height,
2621 DRM_MODE_ROTATE_270);
2625 /* rotate the tile dimensions to match the GTT view */
2626 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2627 swap(tile_width, tile_height);
2630 * We only keep the x/y offsets, so push all of the
2631 * gtt offset into the x/y offsets.
2633 intel_adjust_tile_offset(&x, &y,
2634 tile_width, tile_height,
2635 tile_size, pitch_tiles,
2636 gtt_offset_rotated * tile_size, 0);
2638 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2641 * First pixel of the framebuffer from
2642 * the start of the rotated gtt mapping.
2644 intel_fb->rotated[i].x = x;
2645 intel_fb->rotated[i].y = y;
2647 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2648 x * cpp, tile_size);
2651 /* how many tiles in total needed in the bo */
2652 max_size = max(max_size, offset + size);
2655 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2656 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2657 mul_u32_u32(max_size, tile_size), obj->base.size);
2664 static int i9xx_format_to_fourcc(int format)
2667 case DISPPLANE_8BPP:
2668 return DRM_FORMAT_C8;
2669 case DISPPLANE_BGRX555:
2670 return DRM_FORMAT_XRGB1555;
2671 case DISPPLANE_BGRX565:
2672 return DRM_FORMAT_RGB565;
2674 case DISPPLANE_BGRX888:
2675 return DRM_FORMAT_XRGB8888;
2676 case DISPPLANE_RGBX888:
2677 return DRM_FORMAT_XBGR8888;
2678 case DISPPLANE_BGRX101010:
2679 return DRM_FORMAT_XRGB2101010;
2680 case DISPPLANE_RGBX101010:
2681 return DRM_FORMAT_XBGR2101010;
2685 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2688 case PLANE_CTL_FORMAT_RGB_565:
2689 return DRM_FORMAT_RGB565;
2690 case PLANE_CTL_FORMAT_NV12:
2691 return DRM_FORMAT_NV12;
2692 case PLANE_CTL_FORMAT_P010:
2693 return DRM_FORMAT_P010;
2694 case PLANE_CTL_FORMAT_P012:
2695 return DRM_FORMAT_P012;
2696 case PLANE_CTL_FORMAT_P016:
2697 return DRM_FORMAT_P016;
2698 case PLANE_CTL_FORMAT_Y210:
2699 return DRM_FORMAT_Y210;
2700 case PLANE_CTL_FORMAT_Y212:
2701 return DRM_FORMAT_Y212;
2702 case PLANE_CTL_FORMAT_Y216:
2703 return DRM_FORMAT_Y216;
2704 case PLANE_CTL_FORMAT_Y410:
2705 return DRM_FORMAT_XVYU2101010;
2706 case PLANE_CTL_FORMAT_Y412:
2707 return DRM_FORMAT_XVYU12_16161616;
2708 case PLANE_CTL_FORMAT_Y416:
2709 return DRM_FORMAT_XVYU16161616;
2711 case PLANE_CTL_FORMAT_XRGB_8888:
2714 return DRM_FORMAT_ABGR8888;
2716 return DRM_FORMAT_XBGR8888;
2719 return DRM_FORMAT_ARGB8888;
2721 return DRM_FORMAT_XRGB8888;
2723 case PLANE_CTL_FORMAT_XRGB_2101010:
2725 return DRM_FORMAT_XBGR2101010;
2727 return DRM_FORMAT_XRGB2101010;
2728 case PLANE_CTL_FORMAT_XRGB_16161616F:
2731 return DRM_FORMAT_ABGR16161616F;
2733 return DRM_FORMAT_XBGR16161616F;
2736 return DRM_FORMAT_ARGB16161616F;
2738 return DRM_FORMAT_XRGB16161616F;
2744 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2745 struct intel_initial_plane_config *plane_config)
2747 struct drm_device *dev = crtc->base.dev;
2748 struct drm_i915_private *dev_priv = to_i915(dev);
2749 struct drm_i915_gem_object *obj = NULL;
2750 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2751 struct drm_framebuffer *fb = &plane_config->fb->base;
2752 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2753 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2756 size_aligned -= base_aligned;
2758 if (plane_config->size == 0)
2761 /* If the FB is too big, just don't use it since fbdev is not very
2762 * important and we should probably use that space with FBC or other
2764 if (size_aligned * 2 > dev_priv->stolen_usable_size)
2767 switch (fb->modifier) {
2768 case DRM_FORMAT_MOD_LINEAR:
2769 case I915_FORMAT_MOD_X_TILED:
2770 case I915_FORMAT_MOD_Y_TILED:
2773 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
2778 mutex_lock(&dev->struct_mutex);
2779 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2783 mutex_unlock(&dev->struct_mutex);
2787 switch (plane_config->tiling) {
2788 case I915_TILING_NONE:
2792 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
2795 MISSING_CASE(plane_config->tiling);
2799 mode_cmd.pixel_format = fb->format->format;
2800 mode_cmd.width = fb->width;
2801 mode_cmd.height = fb->height;
2802 mode_cmd.pitches[0] = fb->pitches[0];
2803 mode_cmd.modifier[0] = fb->modifier;
2804 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2806 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2807 DRM_DEBUG_KMS("intel fb init failed\n");
2812 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2816 i915_gem_object_put(obj);
2821 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2822 struct intel_plane_state *plane_state,
2825 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2827 plane_state->base.visible = visible;
2830 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2832 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2835 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
2837 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2838 struct drm_plane *plane;
2841 * Active_planes aliases if multiple "primary" or cursor planes
2842 * have been used on the same (or wrong) pipe. plane_mask uses
2843 * unique ids, hence we can use that to reconstruct active_planes.
2845 crtc_state->active_planes = 0;
2847 drm_for_each_plane_mask(plane, &dev_priv->drm,
2848 crtc_state->base.plane_mask)
2849 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
2852 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2853 struct intel_plane *plane)
2855 struct intel_crtc_state *crtc_state =
2856 to_intel_crtc_state(crtc->base.state);
2857 struct intel_plane_state *plane_state =
2858 to_intel_plane_state(plane->base.state);
2860 DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
2861 plane->base.base.id, plane->base.name,
2862 crtc->base.base.id, crtc->base.name);
2864 intel_set_plane_visible(crtc_state, plane_state, false);
2865 fixup_active_planes(crtc_state);
2867 if (plane->id == PLANE_PRIMARY)
2868 intel_pre_disable_primary_noatomic(&crtc->base);
2870 intel_disable_plane(plane, crtc_state);
2874 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2875 struct intel_initial_plane_config *plane_config)
2877 struct drm_device *dev = intel_crtc->base.dev;
2878 struct drm_i915_private *dev_priv = to_i915(dev);
2880 struct drm_i915_gem_object *obj;
2881 struct drm_plane *primary = intel_crtc->base.primary;
2882 struct drm_plane_state *plane_state = primary->state;
2883 struct intel_plane *intel_plane = to_intel_plane(primary);
2884 struct intel_plane_state *intel_state =
2885 to_intel_plane_state(plane_state);
2886 struct drm_framebuffer *fb;
2888 if (!plane_config->fb)
2891 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2892 fb = &plane_config->fb->base;
2896 kfree(plane_config->fb);
2899 * Failed to alloc the obj, check to see if we should share
2900 * an fb with another CRTC instead
2902 for_each_crtc(dev, c) {
2903 struct intel_plane_state *state;
2905 if (c == &intel_crtc->base)
2908 if (!to_intel_crtc(c)->active)
2911 state = to_intel_plane_state(c->primary->state);
2915 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2916 fb = state->base.fb;
2917 drm_framebuffer_get(fb);
2923 * We've failed to reconstruct the BIOS FB. Current display state
2924 * indicates that the primary plane is visible, but has a NULL FB,
2925 * which will lead to problems later if we don't fix it up. The
2926 * simplest solution is to just disable the primary plane now and
2927 * pretend the BIOS never had it enabled.
2929 intel_plane_disable_noatomic(intel_crtc, intel_plane);
2934 intel_state->base.rotation = plane_config->rotation;
2935 intel_fill_fb_ggtt_view(&intel_state->view, fb,
2936 intel_state->base.rotation);
2937 intel_state->color_plane[0].stride =
2938 intel_fb_pitch(fb, 0, intel_state->base.rotation);
2940 mutex_lock(&dev->struct_mutex);
2942 intel_pin_and_fence_fb_obj(fb,
2944 intel_plane_uses_fence(intel_state),
2945 &intel_state->flags);
2946 mutex_unlock(&dev->struct_mutex);
2947 if (IS_ERR(intel_state->vma)) {
2948 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2949 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2951 intel_state->vma = NULL;
2952 drm_framebuffer_put(fb);
2956 obj = intel_fb_obj(fb);
2957 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2959 plane_state->src_x = 0;
2960 plane_state->src_y = 0;
2961 plane_state->src_w = fb->width << 16;
2962 plane_state->src_h = fb->height << 16;
2964 plane_state->crtc_x = 0;
2965 plane_state->crtc_y = 0;
2966 plane_state->crtc_w = fb->width;
2967 plane_state->crtc_h = fb->height;
2969 intel_state->base.src = drm_plane_state_src(plane_state);
2970 intel_state->base.dst = drm_plane_state_dest(plane_state);
2972 if (i915_gem_object_is_tiled(obj))
2973 dev_priv->preserve_bios_swizzle = true;
2975 plane_state->fb = fb;
2976 plane_state->crtc = &intel_crtc->base;
2978 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2979 &obj->frontbuffer_bits);
2982 static int skl_max_plane_width(const struct drm_framebuffer *fb,
2984 unsigned int rotation)
2986 int cpp = fb->format->cpp[color_plane];
2988 switch (fb->modifier) {
2989 case DRM_FORMAT_MOD_LINEAR:
2990 case I915_FORMAT_MOD_X_TILED:
2992 case I915_FORMAT_MOD_Y_TILED_CCS:
2993 case I915_FORMAT_MOD_Yf_TILED_CCS:
2994 /* FIXME AUX plane? */
2995 case I915_FORMAT_MOD_Y_TILED:
2996 case I915_FORMAT_MOD_Yf_TILED:
3002 MISSING_CASE(fb->modifier);
3007 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3009 unsigned int rotation)
3011 int cpp = fb->format->cpp[color_plane];
3013 switch (fb->modifier) {
3014 case DRM_FORMAT_MOD_LINEAR:
3015 case I915_FORMAT_MOD_X_TILED:
3020 case I915_FORMAT_MOD_Y_TILED_CCS:
3021 case I915_FORMAT_MOD_Yf_TILED_CCS:
3022 /* FIXME AUX plane? */
3023 case I915_FORMAT_MOD_Y_TILED:
3024 case I915_FORMAT_MOD_Yf_TILED:
3030 MISSING_CASE(fb->modifier);
3035 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3037 unsigned int rotation)
3042 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3043 int main_x, int main_y, u32 main_offset)
3045 const struct drm_framebuffer *fb = plane_state->base.fb;
3046 int hsub = fb->format->hsub;
3047 int vsub = fb->format->vsub;
3048 int aux_x = plane_state->color_plane[1].x;
3049 int aux_y = plane_state->color_plane[1].y;
3050 u32 aux_offset = plane_state->color_plane[1].offset;
3051 u32 alignment = intel_surf_alignment(fb, 1);
3053 while (aux_offset >= main_offset && aux_y <= main_y) {
3056 if (aux_x == main_x && aux_y == main_y)
3059 if (aux_offset == 0)
3064 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3065 aux_offset, aux_offset - alignment);
3066 aux_x = x * hsub + aux_x % hsub;
3067 aux_y = y * vsub + aux_y % vsub;
3070 if (aux_x != main_x || aux_y != main_y)
3073 plane_state->color_plane[1].offset = aux_offset;
3074 plane_state->color_plane[1].x = aux_x;
3075 plane_state->color_plane[1].y = aux_y;
3080 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3082 struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
3083 const struct drm_framebuffer *fb = plane_state->base.fb;
3084 unsigned int rotation = plane_state->base.rotation;
3085 int x = plane_state->base.src.x1 >> 16;
3086 int y = plane_state->base.src.y1 >> 16;
3087 int w = drm_rect_width(&plane_state->base.src) >> 16;
3088 int h = drm_rect_height(&plane_state->base.src) >> 16;
3090 int max_height = 4096;
3091 u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3093 if (INTEL_GEN(dev_priv) >= 11)
3094 max_width = icl_max_plane_width(fb, 0, rotation);
3095 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3096 max_width = glk_max_plane_width(fb, 0, rotation);
3098 max_width = skl_max_plane_width(fb, 0, rotation);
3100 if (w > max_width || h > max_height) {
3101 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3102 w, h, max_width, max_height);
3106 intel_add_fb_offsets(&x, &y, plane_state, 0);
3107 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3108 alignment = intel_surf_alignment(fb, 0);
3111 * AUX surface offset is specified as the distance from the
3112 * main surface offset, and it must be non-negative. Make
3113 * sure that is what we will get.
3115 if (offset > aux_offset)
3116 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3117 offset, aux_offset & ~(alignment - 1));
3120 * When using an X-tiled surface, the plane blows up
3121 * if the x offset + width exceed the stride.
3123 * TODO: linear and Y-tiled seem fine, Yf untested,
3125 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3126 int cpp = fb->format->cpp[0];
3128 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3130 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3134 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3135 offset, offset - alignment);
3140 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3141 * they match with the main surface x/y offsets.
3143 if (is_ccs_modifier(fb->modifier)) {
3144 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3148 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3149 offset, offset - alignment);
3152 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3153 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3158 plane_state->color_plane[0].offset = offset;
3159 plane_state->color_plane[0].x = x;
3160 plane_state->color_plane[0].y = y;
3165 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3167 const struct drm_framebuffer *fb = plane_state->base.fb;
3168 unsigned int rotation = plane_state->base.rotation;
3169 int max_width = skl_max_plane_width(fb, 1, rotation);
3170 int max_height = 4096;
3171 int x = plane_state->base.src.x1 >> 17;
3172 int y = plane_state->base.src.y1 >> 17;
3173 int w = drm_rect_width(&plane_state->base.src) >> 17;
3174 int h = drm_rect_height(&plane_state->base.src) >> 17;
3177 intel_add_fb_offsets(&x, &y, plane_state, 1);
3178 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3180 /* FIXME not quite sure how/if these apply to the chroma plane */
3181 if (w > max_width || h > max_height) {
3182 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3183 w, h, max_width, max_height);
3187 plane_state->color_plane[1].offset = offset;
3188 plane_state->color_plane[1].x = x;
3189 plane_state->color_plane[1].y = y;
3194 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3196 const struct drm_framebuffer *fb = plane_state->base.fb;
3197 int src_x = plane_state->base.src.x1 >> 16;
3198 int src_y = plane_state->base.src.y1 >> 16;
3199 int hsub = fb->format->hsub;
3200 int vsub = fb->format->vsub;
3201 int x = src_x / hsub;
3202 int y = src_y / vsub;
3205 intel_add_fb_offsets(&x, &y, plane_state, 1);
3206 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3208 plane_state->color_plane[1].offset = offset;
3209 plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3210 plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3215 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3217 const struct drm_framebuffer *fb = plane_state->base.fb;
3218 unsigned int rotation = plane_state->base.rotation;
3221 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
3222 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
3223 plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
3225 ret = intel_plane_check_stride(plane_state);
3229 if (!plane_state->base.visible)
3232 /* Rotate src coordinates to match rotated GTT view */
3233 if (drm_rotation_90_or_270(rotation))
3234 drm_rect_rotate(&plane_state->base.src,
3235 fb->width << 16, fb->height << 16,
3236 DRM_MODE_ROTATE_270);
3239 * Handle the AUX surface first since
3240 * the main surface setup depends on it.
3242 if (is_planar_yuv_format(fb->format->format)) {
3243 ret = skl_check_nv12_aux_surface(plane_state);
3246 } else if (is_ccs_modifier(fb->modifier)) {
3247 ret = skl_check_ccs_aux_surface(plane_state);
3251 plane_state->color_plane[1].offset = ~0xfff;
3252 plane_state->color_plane[1].x = 0;
3253 plane_state->color_plane[1].y = 0;
3256 ret = skl_check_main_surface(plane_state);
3264 i9xx_plane_max_stride(struct intel_plane *plane,
3265 u32 pixel_format, u64 modifier,
3266 unsigned int rotation)
3268 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3270 if (!HAS_GMCH(dev_priv)) {
3272 } else if (INTEL_GEN(dev_priv) >= 4) {
3273 if (modifier == I915_FORMAT_MOD_X_TILED)
3277 } else if (INTEL_GEN(dev_priv) >= 3) {
3278 if (modifier == I915_FORMAT_MOD_X_TILED)
3283 if (plane->i9xx_plane == PLANE_C)
3290 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3292 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3293 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3296 if (crtc_state->gamma_enable)
3297 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3299 if (crtc_state->csc_enable)
3300 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3302 if (INTEL_GEN(dev_priv) < 5)
3303 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3308 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3309 const struct intel_plane_state *plane_state)
3311 struct drm_i915_private *dev_priv =
3312 to_i915(plane_state->base.plane->dev);
3313 const struct drm_framebuffer *fb = plane_state->base.fb;
3314 unsigned int rotation = plane_state->base.rotation;
3317 dspcntr = DISPLAY_PLANE_ENABLE;
3319 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3320 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3321 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3323 switch (fb->format->format) {
3325 dspcntr |= DISPPLANE_8BPP;
3327 case DRM_FORMAT_XRGB1555:
3328 dspcntr |= DISPPLANE_BGRX555;
3330 case DRM_FORMAT_RGB565:
3331 dspcntr |= DISPPLANE_BGRX565;
3333 case DRM_FORMAT_XRGB8888:
3334 dspcntr |= DISPPLANE_BGRX888;
3336 case DRM_FORMAT_XBGR8888:
3337 dspcntr |= DISPPLANE_RGBX888;
3339 case DRM_FORMAT_XRGB2101010:
3340 dspcntr |= DISPPLANE_BGRX101010;
3342 case DRM_FORMAT_XBGR2101010:
3343 dspcntr |= DISPPLANE_RGBX101010;
3346 MISSING_CASE(fb->format->format);
3350 if (INTEL_GEN(dev_priv) >= 4 &&
3351 fb->modifier == I915_FORMAT_MOD_X_TILED)
3352 dspcntr |= DISPPLANE_TILED;
3354 if (rotation & DRM_MODE_ROTATE_180)
3355 dspcntr |= DISPPLANE_ROTATE_180;
3357 if (rotation & DRM_MODE_REFLECT_X)
3358 dspcntr |= DISPPLANE_MIRROR;
3363 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3365 struct drm_i915_private *dev_priv =
3366 to_i915(plane_state->base.plane->dev);
3367 const struct drm_framebuffer *fb = plane_state->base.fb;
3368 unsigned int rotation = plane_state->base.rotation;
3369 int src_x = plane_state->base.src.x1 >> 16;
3370 int src_y = plane_state->base.src.y1 >> 16;
3374 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
3375 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
3377 ret = intel_plane_check_stride(plane_state);
3381 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3383 if (INTEL_GEN(dev_priv) >= 4)
3384 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3389 /* HSW/BDW do this automagically in hardware */
3390 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3391 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3392 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3394 if (rotation & DRM_MODE_ROTATE_180) {
3397 } else if (rotation & DRM_MODE_REFLECT_X) {
3402 plane_state->color_plane[0].offset = offset;
3403 plane_state->color_plane[0].x = src_x;
3404 plane_state->color_plane[0].y = src_y;
3410 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3411 struct intel_plane_state *plane_state)
3415 ret = chv_plane_check_rotation(plane_state);
3419 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
3421 DRM_PLANE_HELPER_NO_SCALING,
3422 DRM_PLANE_HELPER_NO_SCALING,
3427 if (!plane_state->base.visible)
3430 ret = intel_plane_check_src_coordinates(plane_state);
3434 ret = i9xx_check_plane_surface(plane_state);
3438 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3443 static void i9xx_update_plane(struct intel_plane *plane,
3444 const struct intel_crtc_state *crtc_state,
3445 const struct intel_plane_state *plane_state)
3447 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3448 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3450 int x = plane_state->color_plane[0].x;
3451 int y = plane_state->color_plane[0].y;
3452 unsigned long irqflags;
3456 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3458 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3460 if (INTEL_GEN(dev_priv) >= 4)
3461 dspaddr_offset = plane_state->color_plane[0].offset;
3463 dspaddr_offset = linear_offset;
3465 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3467 I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3469 if (INTEL_GEN(dev_priv) < 4) {
3470 /* pipesrc and dspsize control the size that is scaled from,
3471 * which should always be the user's requested size.
3473 I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
3474 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3475 ((crtc_state->pipe_src_h - 1) << 16) |
3476 (crtc_state->pipe_src_w - 1));
3477 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3478 I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
3479 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3480 ((crtc_state->pipe_src_h - 1) << 16) |
3481 (crtc_state->pipe_src_w - 1));
3482 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3485 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3486 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3487 } else if (INTEL_GEN(dev_priv) >= 4) {
3488 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3489 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3493 * The control register self-arms if the plane was previously
3494 * disabled. Try to make the plane enable atomic by writing
3495 * the control register just before the surface register.
3497 I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3498 if (INTEL_GEN(dev_priv) >= 4)
3499 I915_WRITE_FW(DSPSURF(i9xx_plane),
3500 intel_plane_ggtt_offset(plane_state) +
3503 I915_WRITE_FW(DSPADDR(i9xx_plane),
3504 intel_plane_ggtt_offset(plane_state) +
3507 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3510 static void i9xx_disable_plane(struct intel_plane *plane,
3511 const struct intel_crtc_state *crtc_state)
3513 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3514 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3515 unsigned long irqflags;
3519 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
3520 * enable on ilk+ affect the pipe bottom color as
3521 * well, so we must configure them even if the plane
3524 * On pre-g4x there is no way to gamma correct the
3525 * pipe bottom color but we'll keep on doing this
3526 * anyway so that the crtc state readout works correctly.
3528 dspcntr = i9xx_plane_ctl_crtc(crtc_state);
3530 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3532 I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3533 if (INTEL_GEN(dev_priv) >= 4)
3534 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3536 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3538 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3541 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
3544 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3545 enum intel_display_power_domain power_domain;
3546 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3547 intel_wakeref_t wakeref;
3552 * Not 100% correct for planes that can move between pipes,
3553 * but that's only the case for gen2-4 which don't have any
3554 * display power wells.
3556 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
3557 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3561 val = I915_READ(DSPCNTR(i9xx_plane));
3563 ret = val & DISPLAY_PLANE_ENABLE;
3565 if (INTEL_GEN(dev_priv) >= 5)
3566 *pipe = plane->pipe;
3568 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
3569 DISPPLANE_SEL_PIPE_SHIFT;
3571 intel_display_power_put(dev_priv, power_domain, wakeref);
3577 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
3579 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3582 return intel_tile_width_bytes(fb, color_plane);
3585 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3587 struct drm_device *dev = intel_crtc->base.dev;
3588 struct drm_i915_private *dev_priv = to_i915(dev);
3590 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3591 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3592 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3596 * This function detaches (aka. unbinds) unused scalers in hardware
3598 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
3600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3601 const struct intel_crtc_scaler_state *scaler_state =
3602 &crtc_state->scaler_state;
3605 /* loop through and disable scalers that aren't in use */
3606 for (i = 0; i < intel_crtc->num_scalers; i++) {
3607 if (!scaler_state->scalers[i].in_use)
3608 skl_detach_scaler(intel_crtc, i);
3612 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
3613 int color_plane, unsigned int rotation)
3616 * The stride is either expressed as a multiple of 64 bytes chunks for
3617 * linear buffers or in number of tiles for tiled buffers.
3619 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3621 else if (drm_rotation_90_or_270(rotation))
3622 return intel_tile_height(fb, color_plane);
3624 return intel_tile_width_bytes(fb, color_plane);
3627 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
3630 const struct drm_framebuffer *fb = plane_state->base.fb;
3631 unsigned int rotation = plane_state->base.rotation;
3632 u32 stride = plane_state->color_plane[color_plane].stride;
3634 if (color_plane >= fb->format->num_planes)
3637 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
3640 static u32 skl_plane_ctl_format(u32 pixel_format)
3642 switch (pixel_format) {
3644 return PLANE_CTL_FORMAT_INDEXED;
3645 case DRM_FORMAT_RGB565:
3646 return PLANE_CTL_FORMAT_RGB_565;
3647 case DRM_FORMAT_XBGR8888:
3648 case DRM_FORMAT_ABGR8888:
3649 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3650 case DRM_FORMAT_XRGB8888:
3651 case DRM_FORMAT_ARGB8888:
3652 return PLANE_CTL_FORMAT_XRGB_8888;
3653 case DRM_FORMAT_XRGB2101010:
3654 return PLANE_CTL_FORMAT_XRGB_2101010;
3655 case DRM_FORMAT_XBGR2101010:
3656 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3657 case DRM_FORMAT_XBGR16161616F:
3658 case DRM_FORMAT_ABGR16161616F:
3659 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
3660 case DRM_FORMAT_XRGB16161616F:
3661 case DRM_FORMAT_ARGB16161616F:
3662 return PLANE_CTL_FORMAT_XRGB_16161616F;
3663 case DRM_FORMAT_YUYV:
3664 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3665 case DRM_FORMAT_YVYU:
3666 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3667 case DRM_FORMAT_UYVY:
3668 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3669 case DRM_FORMAT_VYUY:
3670 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3671 case DRM_FORMAT_NV12:
3672 return PLANE_CTL_FORMAT_NV12;
3673 case DRM_FORMAT_P010:
3674 return PLANE_CTL_FORMAT_P010;
3675 case DRM_FORMAT_P012:
3676 return PLANE_CTL_FORMAT_P012;
3677 case DRM_FORMAT_P016:
3678 return PLANE_CTL_FORMAT_P016;
3679 case DRM_FORMAT_Y210:
3680 return PLANE_CTL_FORMAT_Y210;
3681 case DRM_FORMAT_Y212:
3682 return PLANE_CTL_FORMAT_Y212;
3683 case DRM_FORMAT_Y216:
3684 return PLANE_CTL_FORMAT_Y216;
3685 case DRM_FORMAT_XVYU2101010:
3686 return PLANE_CTL_FORMAT_Y410;
3687 case DRM_FORMAT_XVYU12_16161616:
3688 return PLANE_CTL_FORMAT_Y412;
3689 case DRM_FORMAT_XVYU16161616:
3690 return PLANE_CTL_FORMAT_Y416;
3692 MISSING_CASE(pixel_format);
3698 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
3700 if (!plane_state->base.fb->format->has_alpha)
3701 return PLANE_CTL_ALPHA_DISABLE;
3703 switch (plane_state->base.pixel_blend_mode) {
3704 case DRM_MODE_BLEND_PIXEL_NONE:
3705 return PLANE_CTL_ALPHA_DISABLE;
3706 case DRM_MODE_BLEND_PREMULTI:
3707 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3708 case DRM_MODE_BLEND_COVERAGE:
3709 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
3711 MISSING_CASE(plane_state->base.pixel_blend_mode);
3712 return PLANE_CTL_ALPHA_DISABLE;
3716 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
3718 if (!plane_state->base.fb->format->has_alpha)
3719 return PLANE_COLOR_ALPHA_DISABLE;
3721 switch (plane_state->base.pixel_blend_mode) {
3722 case DRM_MODE_BLEND_PIXEL_NONE:
3723 return PLANE_COLOR_ALPHA_DISABLE;
3724 case DRM_MODE_BLEND_PREMULTI:
3725 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3726 case DRM_MODE_BLEND_COVERAGE:
3727 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
3729 MISSING_CASE(plane_state->base.pixel_blend_mode);
3730 return PLANE_COLOR_ALPHA_DISABLE;
3734 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
3736 switch (fb_modifier) {
3737 case DRM_FORMAT_MOD_LINEAR:
3739 case I915_FORMAT_MOD_X_TILED:
3740 return PLANE_CTL_TILED_X;
3741 case I915_FORMAT_MOD_Y_TILED:
3742 return PLANE_CTL_TILED_Y;
3743 case I915_FORMAT_MOD_Y_TILED_CCS:
3744 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3745 case I915_FORMAT_MOD_Yf_TILED:
3746 return PLANE_CTL_TILED_YF;
3747 case I915_FORMAT_MOD_Yf_TILED_CCS:
3748 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3750 MISSING_CASE(fb_modifier);
3756 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3759 case DRM_MODE_ROTATE_0:
3762 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3763 * while i915 HW rotation is clockwise, thats why this swapping.
3765 case DRM_MODE_ROTATE_90:
3766 return PLANE_CTL_ROTATE_270;
3767 case DRM_MODE_ROTATE_180:
3768 return PLANE_CTL_ROTATE_180;
3769 case DRM_MODE_ROTATE_270:
3770 return PLANE_CTL_ROTATE_90;
3772 MISSING_CASE(rotate);
3778 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3783 case DRM_MODE_REFLECT_X:
3784 return PLANE_CTL_FLIP_HORIZONTAL;
3785 case DRM_MODE_REFLECT_Y:
3787 MISSING_CASE(reflect);
3793 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3795 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3798 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3801 if (crtc_state->gamma_enable)
3802 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
3804 if (crtc_state->csc_enable)
3805 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
3810 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3811 const struct intel_plane_state *plane_state)
3813 struct drm_i915_private *dev_priv =
3814 to_i915(plane_state->base.plane->dev);
3815 const struct drm_framebuffer *fb = plane_state->base.fb;
3816 unsigned int rotation = plane_state->base.rotation;
3817 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3820 plane_ctl = PLANE_CTL_ENABLE;
3822 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3823 plane_ctl |= skl_plane_ctl_alpha(plane_state);
3824 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3826 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3827 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3829 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3830 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3833 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3834 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3835 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3837 if (INTEL_GEN(dev_priv) >= 10)
3838 plane_ctl |= cnl_plane_ctl_flip(rotation &
3839 DRM_MODE_REFLECT_MASK);
3841 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3842 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3843 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3844 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3849 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
3851 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3852 u32 plane_color_ctl = 0;
3854 if (INTEL_GEN(dev_priv) >= 11)
3855 return plane_color_ctl;
3857 if (crtc_state->gamma_enable)
3858 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3860 if (crtc_state->csc_enable)
3861 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3863 return plane_color_ctl;
3866 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3867 const struct intel_plane_state *plane_state)
3869 struct drm_i915_private *dev_priv =
3870 to_i915(plane_state->base.plane->dev);
3871 const struct drm_framebuffer *fb = plane_state->base.fb;
3872 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3873 u32 plane_color_ctl = 0;
3875 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3876 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
3878 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
3879 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3880 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3882 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
3884 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3885 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3886 } else if (fb->format->is_yuv) {
3887 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
3890 return plane_color_ctl;
3894 __intel_display_resume(struct drm_device *dev,
3895 struct drm_atomic_state *state,
3896 struct drm_modeset_acquire_ctx *ctx)
3898 struct drm_crtc_state *crtc_state;
3899 struct drm_crtc *crtc;
3902 intel_modeset_setup_hw_state(dev, ctx);
3903 i915_redisable_vga(to_i915(dev));
3909 * We've duplicated the state, pointers to the old state are invalid.
3911 * Don't attempt to use the old state until we commit the duplicated state.
3913 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3915 * Force recalculation even if we restore
3916 * current state. With fast modeset this may not result
3917 * in a modeset when the state is compatible.
3919 crtc_state->mode_changed = true;
3922 /* ignore any reset values/BIOS leftovers in the WM registers */
3923 if (!HAS_GMCH(to_i915(dev)))
3924 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3926 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3928 WARN_ON(ret == -EDEADLK);
3932 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3934 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
3935 intel_has_gpu_reset(dev_priv));
3938 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3940 struct drm_device *dev = &dev_priv->drm;
3941 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3942 struct drm_atomic_state *state;
3945 /* reset doesn't touch the display */
3946 if (!i915_modparams.force_reset_modeset_test &&
3947 !gpu_reset_clobbers_display(dev_priv))
3950 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3951 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3952 wake_up_all(&dev_priv->gpu_error.wait_queue);
3954 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3955 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3956 i915_gem_set_wedged(dev_priv);
3960 * Need mode_config.mutex so that we don't
3961 * trample ongoing ->detect() and whatnot.
3963 mutex_lock(&dev->mode_config.mutex);
3964 drm_modeset_acquire_init(ctx, 0);
3966 ret = drm_modeset_lock_all_ctx(dev, ctx);
3967 if (ret != -EDEADLK)
3970 drm_modeset_backoff(ctx);
3973 * Disabling the crtcs gracefully seems nicer. Also the
3974 * g33 docs say we should at least disable all the planes.
3976 state = drm_atomic_helper_duplicate_state(dev, ctx);
3977 if (IS_ERR(state)) {
3978 ret = PTR_ERR(state);
3979 DRM_ERROR("Duplicating state failed with %i\n", ret);
3983 ret = drm_atomic_helper_disable_all(dev, ctx);
3985 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3986 drm_atomic_state_put(state);
3990 dev_priv->modeset_restore_state = state;
3991 state->acquire_ctx = ctx;
3994 void intel_finish_reset(struct drm_i915_private *dev_priv)
3996 struct drm_device *dev = &dev_priv->drm;
3997 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3998 struct drm_atomic_state *state;
4001 /* reset doesn't touch the display */
4002 if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
4005 state = fetch_and_zero(&dev_priv->modeset_restore_state);
4009 /* reset doesn't touch the display */
4010 if (!gpu_reset_clobbers_display(dev_priv)) {
4011 /* for testing only restore the display */
4012 ret = __intel_display_resume(dev, state, ctx);
4014 DRM_ERROR("Restoring old state failed with %i\n", ret);
4017 * The display has been reset as well,
4018 * so need a full re-initialization.
4020 intel_pps_unlock_regs_wa(dev_priv);
4021 intel_modeset_init_hw(dev);
4022 intel_init_clock_gating(dev_priv);
4024 spin_lock_irq(&dev_priv->irq_lock);
4025 if (dev_priv->display.hpd_irq_setup)
4026 dev_priv->display.hpd_irq_setup(dev_priv);
4027 spin_unlock_irq(&dev_priv->irq_lock);
4029 ret = __intel_display_resume(dev, state, ctx);
4031 DRM_ERROR("Restoring old state failed with %i\n", ret);
4033 intel_hpd_init(dev_priv);
4036 drm_atomic_state_put(state);
4038 drm_modeset_drop_locks(ctx);
4039 drm_modeset_acquire_fini(ctx);
4040 mutex_unlock(&dev->mode_config.mutex);
4042 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
4045 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4047 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4048 enum pipe pipe = crtc->pipe;
4051 tmp = I915_READ(PIPE_CHICKEN(pipe));
4054 * Display WA #1153: icl
4055 * enable hardware to bypass the alpha math
4056 * and rounding for per-pixel values 00 and 0xff
4058 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4060 * Display WA # 1605353570: icl
4061 * Set the pixel rounding bit to 1 for allowing
4062 * passthrough of Frame buffer pixels unmodified
4065 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4066 I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4069 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
4070 const struct intel_crtc_state *new_crtc_state)
4072 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
4073 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4075 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
4076 crtc->base.mode = new_crtc_state->base.mode;
4079 * Update pipe size and adjust fitter if needed: the reason for this is
4080 * that in compute_mode_changes we check the native mode (not the pfit
4081 * mode) to see if we can flip rather than do a full mode set. In the
4082 * fastboot case, we'll flip, but if we don't update the pipesrc and
4083 * pfit state, we'll end up with a big fb scanned out into the wrong
4087 I915_WRITE(PIPESRC(crtc->pipe),
4088 ((new_crtc_state->pipe_src_w - 1) << 16) |
4089 (new_crtc_state->pipe_src_h - 1));
4091 /* on skylake this is done by detaching scalers */
4092 if (INTEL_GEN(dev_priv) >= 9) {
4093 skl_detach_scalers(new_crtc_state);
4095 if (new_crtc_state->pch_pfit.enabled)
4096 skylake_pfit_enable(new_crtc_state);
4097 } else if (HAS_PCH_SPLIT(dev_priv)) {
4098 if (new_crtc_state->pch_pfit.enabled)
4099 ironlake_pfit_enable(new_crtc_state);
4100 else if (old_crtc_state->pch_pfit.enabled)
4101 ironlake_pfit_disable(old_crtc_state);
4104 if (INTEL_GEN(dev_priv) >= 11)
4105 icl_set_pipe_chicken(crtc);
4108 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4110 struct drm_device *dev = crtc->base.dev;
4111 struct drm_i915_private *dev_priv = to_i915(dev);
4112 int pipe = crtc->pipe;
4116 /* enable normal train */
4117 reg = FDI_TX_CTL(pipe);
4118 temp = I915_READ(reg);
4119 if (IS_IVYBRIDGE(dev_priv)) {
4120 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4121 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4123 temp &= ~FDI_LINK_TRAIN_NONE;
4124 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4126 I915_WRITE(reg, temp);
4128 reg = FDI_RX_CTL(pipe);
4129 temp = I915_READ(reg);
4130 if (HAS_PCH_CPT(dev_priv)) {
4131 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4132 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4134 temp &= ~FDI_LINK_TRAIN_NONE;
4135 temp |= FDI_LINK_TRAIN_NONE;
4137 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4139 /* wait one idle pattern time */
4143 /* IVB wants error correction enabled */
4144 if (IS_IVYBRIDGE(dev_priv))
4145 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4146 FDI_FE_ERRC_ENABLE);
4149 /* The FDI link training functions for ILK/Ibexpeak. */
4150 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4151 const struct intel_crtc_state *crtc_state)
4153 struct drm_device *dev = crtc->base.dev;
4154 struct drm_i915_private *dev_priv = to_i915(dev);
4155 int pipe = crtc->pipe;
4159 /* FDI needs bits from pipe first */
4160 assert_pipe_enabled(dev_priv, pipe);
4162 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4164 reg = FDI_RX_IMR(pipe);
4165 temp = I915_READ(reg);
4166 temp &= ~FDI_RX_SYMBOL_LOCK;
4167 temp &= ~FDI_RX_BIT_LOCK;
4168 I915_WRITE(reg, temp);
4172 /* enable CPU FDI TX and PCH FDI RX */
4173 reg = FDI_TX_CTL(pipe);
4174 temp = I915_READ(reg);
4175 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4176 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4177 temp &= ~FDI_LINK_TRAIN_NONE;
4178 temp |= FDI_LINK_TRAIN_PATTERN_1;
4179 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4181 reg = FDI_RX_CTL(pipe);
4182 temp = I915_READ(reg);
4183 temp &= ~FDI_LINK_TRAIN_NONE;
4184 temp |= FDI_LINK_TRAIN_PATTERN_1;
4185 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4190 /* Ironlake workaround, enable clock pointer after FDI enable*/
4191 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4192 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4193 FDI_RX_PHASE_SYNC_POINTER_EN);
4195 reg = FDI_RX_IIR(pipe);
4196 for (tries = 0; tries < 5; tries++) {
4197 temp = I915_READ(reg);
4198 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4200 if ((temp & FDI_RX_BIT_LOCK)) {
4201 DRM_DEBUG_KMS("FDI train 1 done.\n");
4202 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4207 DRM_ERROR("FDI train 1 fail!\n");
4210 reg = FDI_TX_CTL(pipe);
4211 temp = I915_READ(reg);
4212 temp &= ~FDI_LINK_TRAIN_NONE;
4213 temp |= FDI_LINK_TRAIN_PATTERN_2;
4214 I915_WRITE(reg, temp);
4216 reg = FDI_RX_CTL(pipe);
4217 temp = I915_READ(reg);
4218 temp &= ~FDI_LINK_TRAIN_NONE;
4219 temp |= FDI_LINK_TRAIN_PATTERN_2;
4220 I915_WRITE(reg, temp);
4225 reg = FDI_RX_IIR(pipe);
4226 for (tries = 0; tries < 5; tries++) {
4227 temp = I915_READ(reg);
4228 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4230 if (temp & FDI_RX_SYMBOL_LOCK) {
4231 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4232 DRM_DEBUG_KMS("FDI train 2 done.\n");
4237 DRM_ERROR("FDI train 2 fail!\n");
4239 DRM_DEBUG_KMS("FDI train done\n");
4243 static const int snb_b_fdi_train_param[] = {
4244 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4245 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4246 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4247 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4250 /* The FDI link training functions for SNB/Cougarpoint. */
4251 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4252 const struct intel_crtc_state *crtc_state)
4254 struct drm_device *dev = crtc->base.dev;
4255 struct drm_i915_private *dev_priv = to_i915(dev);
4256 int pipe = crtc->pipe;
4260 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4262 reg = FDI_RX_IMR(pipe);
4263 temp = I915_READ(reg);
4264 temp &= ~FDI_RX_SYMBOL_LOCK;
4265 temp &= ~FDI_RX_BIT_LOCK;
4266 I915_WRITE(reg, temp);
4271 /* enable CPU FDI TX and PCH FDI RX */
4272 reg = FDI_TX_CTL(pipe);
4273 temp = I915_READ(reg);
4274 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4275 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4276 temp &= ~FDI_LINK_TRAIN_NONE;
4277 temp |= FDI_LINK_TRAIN_PATTERN_1;
4278 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4280 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4281 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4283 I915_WRITE(FDI_RX_MISC(pipe),
4284 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4286 reg = FDI_RX_CTL(pipe);
4287 temp = I915_READ(reg);
4288 if (HAS_PCH_CPT(dev_priv)) {
4289 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4290 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4292 temp &= ~FDI_LINK_TRAIN_NONE;
4293 temp |= FDI_LINK_TRAIN_PATTERN_1;
4295 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4300 for (i = 0; i < 4; i++) {
4301 reg = FDI_TX_CTL(pipe);
4302 temp = I915_READ(reg);
4303 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4304 temp |= snb_b_fdi_train_param[i];
4305 I915_WRITE(reg, temp);
4310 for (retry = 0; retry < 5; retry++) {
4311 reg = FDI_RX_IIR(pipe);
4312 temp = I915_READ(reg);
4313 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4314 if (temp & FDI_RX_BIT_LOCK) {
4315 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4316 DRM_DEBUG_KMS("FDI train 1 done.\n");
4325 DRM_ERROR("FDI train 1 fail!\n");
4328 reg = FDI_TX_CTL(pipe);
4329 temp = I915_READ(reg);
4330 temp &= ~FDI_LINK_TRAIN_NONE;
4331 temp |= FDI_LINK_TRAIN_PATTERN_2;
4332 if (IS_GEN(dev_priv, 6)) {
4333 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4335 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4337 I915_WRITE(reg, temp);
4339 reg = FDI_RX_CTL(pipe);
4340 temp = I915_READ(reg);
4341 if (HAS_PCH_CPT(dev_priv)) {
4342 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4343 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4345 temp &= ~FDI_LINK_TRAIN_NONE;
4346 temp |= FDI_LINK_TRAIN_PATTERN_2;
4348 I915_WRITE(reg, temp);
4353 for (i = 0; i < 4; i++) {
4354 reg = FDI_TX_CTL(pipe);
4355 temp = I915_READ(reg);
4356 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4357 temp |= snb_b_fdi_train_param[i];
4358 I915_WRITE(reg, temp);
4363 for (retry = 0; retry < 5; retry++) {
4364 reg = FDI_RX_IIR(pipe);
4365 temp = I915_READ(reg);
4366 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4367 if (temp & FDI_RX_SYMBOL_LOCK) {
4368 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4369 DRM_DEBUG_KMS("FDI train 2 done.\n");
4378 DRM_ERROR("FDI train 2 fail!\n");
4380 DRM_DEBUG_KMS("FDI train done.\n");
4383 /* Manual link training for Ivy Bridge A0 parts */
4384 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4385 const struct intel_crtc_state *crtc_state)
4387 struct drm_device *dev = crtc->base.dev;
4388 struct drm_i915_private *dev_priv = to_i915(dev);
4389 int pipe = crtc->pipe;
4393 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4395 reg = FDI_RX_IMR(pipe);
4396 temp = I915_READ(reg);
4397 temp &= ~FDI_RX_SYMBOL_LOCK;
4398 temp &= ~FDI_RX_BIT_LOCK;
4399 I915_WRITE(reg, temp);
4404 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4405 I915_READ(FDI_RX_IIR(pipe)));
4407 /* Try each vswing and preemphasis setting twice before moving on */
4408 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4409 /* disable first in case we need to retry */
4410 reg = FDI_TX_CTL(pipe);
4411 temp = I915_READ(reg);
4412 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4413 temp &= ~FDI_TX_ENABLE;
4414 I915_WRITE(reg, temp);
4416 reg = FDI_RX_CTL(pipe);
4417 temp = I915_READ(reg);
4418 temp &= ~FDI_LINK_TRAIN_AUTO;
4419 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4420 temp &= ~FDI_RX_ENABLE;
4421 I915_WRITE(reg, temp);
4423 /* enable CPU FDI TX and PCH FDI RX */
4424 reg = FDI_TX_CTL(pipe);
4425 temp = I915_READ(reg);
4426 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4427 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4428 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4429 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4430 temp |= snb_b_fdi_train_param[j/2];
4431 temp |= FDI_COMPOSITE_SYNC;
4432 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4434 I915_WRITE(FDI_RX_MISC(pipe),
4435 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4437 reg = FDI_RX_CTL(pipe);
4438 temp = I915_READ(reg);
4439 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4440 temp |= FDI_COMPOSITE_SYNC;
4441 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4444 udelay(1); /* should be 0.5us */
4446 for (i = 0; i < 4; i++) {
4447 reg = FDI_RX_IIR(pipe);
4448 temp = I915_READ(reg);
4449 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4451 if (temp & FDI_RX_BIT_LOCK ||
4452 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4453 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4454 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4458 udelay(1); /* should be 0.5us */
4461 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4466 reg = FDI_TX_CTL(pipe);
4467 temp = I915_READ(reg);
4468 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4469 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4470 I915_WRITE(reg, temp);
4472 reg = FDI_RX_CTL(pipe);
4473 temp = I915_READ(reg);
4474 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4475 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4476 I915_WRITE(reg, temp);
4479 udelay(2); /* should be 1.5us */
4481 for (i = 0; i < 4; i++) {
4482 reg = FDI_RX_IIR(pipe);
4483 temp = I915_READ(reg);
4484 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4486 if (temp & FDI_RX_SYMBOL_LOCK ||
4487 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4488 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4489 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4493 udelay(2); /* should be 1.5us */
4496 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4500 DRM_DEBUG_KMS("FDI train done.\n");
4503 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4506 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4507 int pipe = intel_crtc->pipe;
4511 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4512 reg = FDI_RX_CTL(pipe);
4513 temp = I915_READ(reg);
4514 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4515 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4516 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4517 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4522 /* Switch from Rawclk to PCDclk */
4523 temp = I915_READ(reg);
4524 I915_WRITE(reg, temp | FDI_PCDCLK);
4529 /* Enable CPU FDI TX PLL, always on for Ironlake */
4530 reg = FDI_TX_CTL(pipe);
4531 temp = I915_READ(reg);
4532 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4533 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4540 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4542 struct drm_device *dev = intel_crtc->base.dev;
4543 struct drm_i915_private *dev_priv = to_i915(dev);
4544 int pipe = intel_crtc->pipe;
4548 /* Switch from PCDclk to Rawclk */
4549 reg = FDI_RX_CTL(pipe);
4550 temp = I915_READ(reg);
4551 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4553 /* Disable CPU FDI TX PLL */
4554 reg = FDI_TX_CTL(pipe);
4555 temp = I915_READ(reg);
4556 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4561 reg = FDI_RX_CTL(pipe);
4562 temp = I915_READ(reg);
4563 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4565 /* Wait for the clocks to turn off. */
4570 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4572 struct drm_device *dev = crtc->dev;
4573 struct drm_i915_private *dev_priv = to_i915(dev);
4574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4575 int pipe = intel_crtc->pipe;
4579 /* disable CPU FDI tx and PCH FDI rx */
4580 reg = FDI_TX_CTL(pipe);
4581 temp = I915_READ(reg);
4582 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4585 reg = FDI_RX_CTL(pipe);
4586 temp = I915_READ(reg);
4587 temp &= ~(0x7 << 16);
4588 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4589 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4594 /* Ironlake workaround, disable clock pointer after downing FDI */
4595 if (HAS_PCH_IBX(dev_priv))
4596 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4598 /* still set train pattern 1 */
4599 reg = FDI_TX_CTL(pipe);
4600 temp = I915_READ(reg);
4601 temp &= ~FDI_LINK_TRAIN_NONE;
4602 temp |= FDI_LINK_TRAIN_PATTERN_1;
4603 I915_WRITE(reg, temp);
4605 reg = FDI_RX_CTL(pipe);
4606 temp = I915_READ(reg);
4607 if (HAS_PCH_CPT(dev_priv)) {
4608 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4609 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4611 temp &= ~FDI_LINK_TRAIN_NONE;
4612 temp |= FDI_LINK_TRAIN_PATTERN_1;
4614 /* BPC in FDI rx is consistent with that in PIPECONF */
4615 temp &= ~(0x07 << 16);
4616 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4617 I915_WRITE(reg, temp);
4623 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4625 struct drm_crtc *crtc;
4628 drm_for_each_crtc(crtc, &dev_priv->drm) {
4629 struct drm_crtc_commit *commit;
4630 spin_lock(&crtc->commit_lock);
4631 commit = list_first_entry_or_null(&crtc->commit_list,
4632 struct drm_crtc_commit, commit_entry);
4633 cleanup_done = commit ?
4634 try_wait_for_completion(&commit->cleanup_done) : true;
4635 spin_unlock(&crtc->commit_lock);
4640 drm_crtc_wait_one_vblank(crtc);
4648 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4652 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4654 mutex_lock(&dev_priv->sb_lock);
4656 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4657 temp |= SBI_SSCCTL_DISABLE;
4658 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4660 mutex_unlock(&dev_priv->sb_lock);
4663 /* Program iCLKIP clock to the desired frequency */
4664 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
4666 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4667 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4668 int clock = crtc_state->base.adjusted_mode.crtc_clock;
4669 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4672 lpt_disable_iclkip(dev_priv);
4674 /* The iCLK virtual clock root frequency is in MHz,
4675 * but the adjusted_mode->crtc_clock in in KHz. To get the
4676 * divisors, it is necessary to divide one by another, so we
4677 * convert the virtual clock precision to KHz here for higher
4680 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4681 u32 iclk_virtual_root_freq = 172800 * 1000;
4682 u32 iclk_pi_range = 64;
4683 u32 desired_divisor;
4685 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4687 divsel = (desired_divisor / iclk_pi_range) - 2;
4688 phaseinc = desired_divisor % iclk_pi_range;
4691 * Near 20MHz is a corner case which is
4692 * out of range for the 7-bit divisor
4698 /* This should not happen with any sane values */
4699 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4700 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4701 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4702 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4704 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4711 mutex_lock(&dev_priv->sb_lock);
4713 /* Program SSCDIVINTPHASE6 */
4714 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4715 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4716 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4717 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4718 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4719 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4720 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4721 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4723 /* Program SSCAUXDIV */
4724 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4725 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4726 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4727 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4729 /* Enable modulator and associated divider */
4730 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4731 temp &= ~SBI_SSCCTL_DISABLE;
4732 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4734 mutex_unlock(&dev_priv->sb_lock);
4736 /* Wait for initialization time */
4739 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4742 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4744 u32 divsel, phaseinc, auxdiv;
4745 u32 iclk_virtual_root_freq = 172800 * 1000;
4746 u32 iclk_pi_range = 64;
4747 u32 desired_divisor;
4750 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4753 mutex_lock(&dev_priv->sb_lock);
4755 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4756 if (temp & SBI_SSCCTL_DISABLE) {
4757 mutex_unlock(&dev_priv->sb_lock);
4761 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4762 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4763 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4764 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4765 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4767 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4768 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4769 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4771 mutex_unlock(&dev_priv->sb_lock);
4773 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4775 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4776 desired_divisor << auxdiv);
4779 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
4780 enum pipe pch_transcoder)
4782 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4783 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4784 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4786 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4787 I915_READ(HTOTAL(cpu_transcoder)));
4788 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4789 I915_READ(HBLANK(cpu_transcoder)));
4790 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4791 I915_READ(HSYNC(cpu_transcoder)));
4793 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4794 I915_READ(VTOTAL(cpu_transcoder)));
4795 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4796 I915_READ(VBLANK(cpu_transcoder)));
4797 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4798 I915_READ(VSYNC(cpu_transcoder)));
4799 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4800 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4803 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
4807 temp = I915_READ(SOUTH_CHICKEN1);
4808 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4811 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4812 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4814 temp &= ~FDI_BC_BIFURCATION_SELECT;
4816 temp |= FDI_BC_BIFURCATION_SELECT;
4818 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4819 I915_WRITE(SOUTH_CHICKEN1, temp);
4820 POSTING_READ(SOUTH_CHICKEN1);
4823 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
4825 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4826 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4828 switch (crtc->pipe) {
4832 if (crtc_state->fdi_lanes > 2)
4833 cpt_set_fdi_bc_bifurcation(dev_priv, false);
4835 cpt_set_fdi_bc_bifurcation(dev_priv, true);
4839 cpt_set_fdi_bc_bifurcation(dev_priv, true);
4848 * Finds the encoder associated with the given CRTC. This can only be
4849 * used when we know that the CRTC isn't feeding multiple encoders!
4851 static struct intel_encoder *
4852 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
4853 const struct intel_crtc_state *crtc_state)
4855 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4856 const struct drm_connector_state *connector_state;
4857 const struct drm_connector *connector;
4858 struct intel_encoder *encoder = NULL;
4859 int num_encoders = 0;
4862 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4863 if (connector_state->crtc != &crtc->base)
4866 encoder = to_intel_encoder(connector_state->best_encoder);
4870 WARN(num_encoders != 1, "%d encoders for pipe %c\n",
4871 num_encoders, pipe_name(crtc->pipe));
4877 * Enable PCH resources required for PCH ports:
4879 * - FDI training & RX/TX
4880 * - update transcoder timings
4881 * - DP transcoding bits
4884 static void ironlake_pch_enable(const struct intel_atomic_state *state,
4885 const struct intel_crtc_state *crtc_state)
4887 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4888 struct drm_device *dev = crtc->base.dev;
4889 struct drm_i915_private *dev_priv = to_i915(dev);
4890 int pipe = crtc->pipe;
4893 assert_pch_transcoder_disabled(dev_priv, pipe);
4895 if (IS_IVYBRIDGE(dev_priv))
4896 ivybridge_update_fdi_bc_bifurcation(crtc_state);
4898 /* Write the TU size bits before fdi link training, so that error
4899 * detection works. */
4900 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4901 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4903 /* For PCH output, training FDI link */
4904 dev_priv->display.fdi_link_train(crtc, crtc_state);
4906 /* We need to program the right clock selection before writing the pixel
4907 * mutliplier into the DPLL. */
4908 if (HAS_PCH_CPT(dev_priv)) {
4911 temp = I915_READ(PCH_DPLL_SEL);
4912 temp |= TRANS_DPLL_ENABLE(pipe);
4913 sel = TRANS_DPLLB_SEL(pipe);
4914 if (crtc_state->shared_dpll ==
4915 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4919 I915_WRITE(PCH_DPLL_SEL, temp);
4922 /* XXX: pch pll's can be enabled any time before we enable the PCH
4923 * transcoder, and we actually should do this to not upset any PCH
4924 * transcoder that already use the clock when we share it.
4926 * Note that enable_shared_dpll tries to do the right thing, but
4927 * get_shared_dpll unconditionally resets the pll - we need that to have
4928 * the right LVDS enable sequence. */
4929 intel_enable_shared_dpll(crtc_state);
4931 /* set transcoder timing, panel must allow it */
4932 assert_panel_unlocked(dev_priv, pipe);
4933 ironlake_pch_transcoder_set_timings(crtc_state, pipe);
4935 intel_fdi_normal_train(crtc);
4937 /* For PCH DP, enable TRANS_DP_CTL */
4938 if (HAS_PCH_CPT(dev_priv) &&
4939 intel_crtc_has_dp_encoder(crtc_state)) {
4940 const struct drm_display_mode *adjusted_mode =
4941 &crtc_state->base.adjusted_mode;
4942 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4943 i915_reg_t reg = TRANS_DP_CTL(pipe);
4946 temp = I915_READ(reg);
4947 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4948 TRANS_DP_SYNC_MASK |
4950 temp |= TRANS_DP_OUTPUT_ENABLE;
4951 temp |= bpc << 9; /* same format but at 11:9 */
4953 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4954 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4955 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4956 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4958 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
4959 WARN_ON(port < PORT_B || port > PORT_D);
4960 temp |= TRANS_DP_PORT_SEL(port);
4962 I915_WRITE(reg, temp);
4965 ironlake_enable_pch_transcoder(crtc_state);
4968 static void lpt_pch_enable(const struct intel_atomic_state *state,
4969 const struct intel_crtc_state *crtc_state)
4971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4972 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4973 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4975 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4977 lpt_program_iclkip(crtc_state);
4979 /* Set transcoder timing. */
4980 ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
4982 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4985 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4987 struct drm_i915_private *dev_priv = to_i915(dev);
4988 i915_reg_t dslreg = PIPEDSL(pipe);
4991 temp = I915_READ(dslreg);
4993 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4994 if (wait_for(I915_READ(dslreg) != temp, 5))
4995 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
5000 * The hardware phase 0.0 refers to the center of the pixel.
5001 * We want to start from the top/left edge which is phase
5002 * -0.5. That matches how the hardware calculates the scaling
5003 * factors (from top-left of the first pixel to bottom-right
5004 * of the last pixel, as opposed to the pixel centers).
5006 * For 4:2:0 subsampled chroma planes we obviously have to
5007 * adjust that so that the chroma sample position lands in
5010 * Note that for packed YCbCr 4:2:2 formats there is no way to
5011 * control chroma siting. The hardware simply replicates the
5012 * chroma samples for both of the luma samples, and thus we don't
5013 * actually get the expected MPEG2 chroma siting convention :(
5014 * The same behaviour is observed on pre-SKL platforms as well.
5016 * Theory behind the formula (note that we ignore sub-pixel
5017 * source coordinates):
5018 * s = source sample position
5019 * d = destination sample position
5024 * | | 1.5 (initial phase)
5032 * | -0.375 (initial phase)
5039 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5041 int phase = -0x8000;
5045 phase += (sub - 1) * 0x8000 / sub;
5047 phase += scale / (2 * sub);
5050 * Hardware initial phase limited to [-0.5:1.5].
5051 * Since the max hardware scale factor is 3.0, we
5052 * should never actually excdeed 1.0 here.
5054 WARN_ON(phase < -0x8000 || phase > 0x18000);
5057 phase = 0x10000 + phase;
5059 trip = PS_PHASE_TRIP;
5061 return ((phase >> 2) & PS_PHASE_MASK) | trip;
5064 #define SKL_MIN_SRC_W 8
5065 #define SKL_MAX_SRC_W 4096
5066 #define SKL_MIN_SRC_H 8
5067 #define SKL_MAX_SRC_H 4096
5068 #define SKL_MIN_DST_W 8
5069 #define SKL_MAX_DST_W 4096
5070 #define SKL_MIN_DST_H 8
5071 #define SKL_MAX_DST_H 4096
5072 #define ICL_MAX_SRC_W 5120
5073 #define ICL_MAX_SRC_H 4096
5074 #define ICL_MAX_DST_W 5120
5075 #define ICL_MAX_DST_H 4096
5076 #define SKL_MIN_YUV_420_SRC_W 16
5077 #define SKL_MIN_YUV_420_SRC_H 16
5080 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5081 unsigned int scaler_user, int *scaler_id,
5082 int src_w, int src_h, int dst_w, int dst_h,
5083 const struct drm_format_info *format, bool need_scaler)
5085 struct intel_crtc_scaler_state *scaler_state =
5086 &crtc_state->scaler_state;
5087 struct intel_crtc *intel_crtc =
5088 to_intel_crtc(crtc_state->base.crtc);
5089 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5090 const struct drm_display_mode *adjusted_mode =
5091 &crtc_state->base.adjusted_mode;
5094 * Src coordinates are already rotated by 270 degrees for
5095 * the 90/270 degree plane rotation cases (to match the
5096 * GTT mapping), hence no need to account for rotation here.
5098 if (src_w != dst_w || src_h != dst_h)
5102 * Scaling/fitting not supported in IF-ID mode in GEN9+
5103 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5104 * Once NV12 is enabled, handle it here while allocating scaler
5107 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
5108 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5109 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5114 * if plane is being disabled or scaler is no more required or force detach
5115 * - free scaler binded to this plane/crtc
5116 * - in order to do this, update crtc->scaler_usage
5118 * Here scaler state in crtc_state is set free so that
5119 * scaler can be assigned to other user. Actual register
5120 * update to free the scaler is done in plane/panel-fit programming.
5121 * For this purpose crtc/plane_state->scaler_id isn't reset here.
5123 if (force_detach || !need_scaler) {
5124 if (*scaler_id >= 0) {
5125 scaler_state->scaler_users &= ~(1 << scaler_user);
5126 scaler_state->scalers[*scaler_id].in_use = 0;
5128 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5129 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5130 intel_crtc->pipe, scaler_user, *scaler_id,
5131 scaler_state->scaler_users);
5137 if (format && is_planar_yuv_format(format->format) &&
5138 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5139 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5144 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5145 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5146 (INTEL_GEN(dev_priv) >= 11 &&
5147 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5148 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5149 (INTEL_GEN(dev_priv) < 11 &&
5150 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5151 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5152 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5153 "size is out of scaler range\n",
5154 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5158 /* mark this plane as a scaler user in crtc_state */
5159 scaler_state->scaler_users |= (1 << scaler_user);
5160 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5161 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5162 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5163 scaler_state->scaler_users);
5169 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5171 * @state: crtc's scaler state
5174 * 0 - scaler_usage updated successfully
5175 * error - requested scaling cannot be supported or other error condition
5177 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5179 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
5180 bool need_scaler = false;
5182 if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5185 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
5186 &state->scaler_state.scaler_id,
5187 state->pipe_src_w, state->pipe_src_h,
5188 adjusted_mode->crtc_hdisplay,
5189 adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5193 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5194 * @crtc_state: crtc's scaler state
5195 * @plane_state: atomic plane state to update
5198 * 0 - scaler_usage updated successfully
5199 * error - requested scaling cannot be supported or other error condition
5201 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5202 struct intel_plane_state *plane_state)
5204 struct intel_plane *intel_plane =
5205 to_intel_plane(plane_state->base.plane);
5206 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5207 struct drm_framebuffer *fb = plane_state->base.fb;
5209 bool force_detach = !fb || !plane_state->base.visible;
5210 bool need_scaler = false;
5212 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5213 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5214 fb && is_planar_yuv_format(fb->format->format))
5217 ret = skl_update_scaler(crtc_state, force_detach,
5218 drm_plane_index(&intel_plane->base),
5219 &plane_state->scaler_id,
5220 drm_rect_width(&plane_state->base.src) >> 16,
5221 drm_rect_height(&plane_state->base.src) >> 16,
5222 drm_rect_width(&plane_state->base.dst),
5223 drm_rect_height(&plane_state->base.dst),
5224 fb ? fb->format : NULL, need_scaler);
5226 if (ret || plane_state->scaler_id < 0)
5229 /* check colorkey */
5230 if (plane_state->ckey.flags) {
5231 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5232 intel_plane->base.base.id,
5233 intel_plane->base.name);
5237 /* Check src format */
5238 switch (fb->format->format) {
5239 case DRM_FORMAT_RGB565:
5240 case DRM_FORMAT_XBGR8888:
5241 case DRM_FORMAT_XRGB8888:
5242 case DRM_FORMAT_ABGR8888:
5243 case DRM_FORMAT_ARGB8888:
5244 case DRM_FORMAT_XRGB2101010:
5245 case DRM_FORMAT_XBGR2101010:
5246 case DRM_FORMAT_XBGR16161616F:
5247 case DRM_FORMAT_ABGR16161616F:
5248 case DRM_FORMAT_XRGB16161616F:
5249 case DRM_FORMAT_ARGB16161616F:
5250 case DRM_FORMAT_YUYV:
5251 case DRM_FORMAT_YVYU:
5252 case DRM_FORMAT_UYVY:
5253 case DRM_FORMAT_VYUY:
5254 case DRM_FORMAT_NV12:
5255 case DRM_FORMAT_P010:
5256 case DRM_FORMAT_P012:
5257 case DRM_FORMAT_P016:
5258 case DRM_FORMAT_Y210:
5259 case DRM_FORMAT_Y212:
5260 case DRM_FORMAT_Y216:
5261 case DRM_FORMAT_XVYU2101010:
5262 case DRM_FORMAT_XVYU12_16161616:
5263 case DRM_FORMAT_XVYU16161616:
5266 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5267 intel_plane->base.base.id, intel_plane->base.name,
5268 fb->base.id, fb->format->format);
5275 static void skylake_scaler_disable(struct intel_crtc *crtc)
5279 for (i = 0; i < crtc->num_scalers; i++)
5280 skl_detach_scaler(crtc, i);
5283 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5286 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5287 enum pipe pipe = crtc->pipe;
5288 const struct intel_crtc_scaler_state *scaler_state =
5289 &crtc_state->scaler_state;
5291 if (crtc_state->pch_pfit.enabled) {
5292 u16 uv_rgb_hphase, uv_rgb_vphase;
5293 int pfit_w, pfit_h, hscale, vscale;
5296 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5299 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5300 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5302 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5303 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5305 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5306 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5308 id = scaler_state->scaler_id;
5309 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5310 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5311 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5312 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5313 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5314 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5315 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5316 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5320 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5323 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5324 int pipe = crtc->pipe;
5326 if (crtc_state->pch_pfit.enabled) {
5327 /* Force use of hard-coded filter coefficients
5328 * as some pre-programmed values are broken,
5331 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5332 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5333 PF_PIPE_SEL_IVB(pipe));
5335 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5336 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5337 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5341 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5343 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5344 struct drm_device *dev = crtc->base.dev;
5345 struct drm_i915_private *dev_priv = to_i915(dev);
5347 if (!crtc_state->ips_enabled)
5351 * We can only enable IPS after we enable a plane and wait for a vblank
5352 * This function is called from post_plane_update, which is run after
5355 WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5357 if (IS_BROADWELL(dev_priv)) {
5358 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5359 IPS_ENABLE | IPS_PCODE_CONTROL));
5360 /* Quoting Art Runyan: "its not safe to expect any particular
5361 * value in IPS_CTL bit 31 after enabling IPS through the
5362 * mailbox." Moreover, the mailbox may return a bogus state,
5363 * so we need to just enable it and continue on.
5366 I915_WRITE(IPS_CTL, IPS_ENABLE);
5367 /* The bit only becomes 1 in the next vblank, so this wait here
5368 * is essentially intel_wait_for_vblank. If we don't have this
5369 * and don't wait for vblanks until the end of crtc_enable, then
5370 * the HW state readout code will complain that the expected
5371 * IPS_CTL value is not the one we read. */
5372 if (intel_wait_for_register(&dev_priv->uncore,
5373 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
5375 DRM_ERROR("Timed out waiting for IPS enable\n");
5379 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5381 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5382 struct drm_device *dev = crtc->base.dev;
5383 struct drm_i915_private *dev_priv = to_i915(dev);
5385 if (!crtc_state->ips_enabled)
5388 if (IS_BROADWELL(dev_priv)) {
5389 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5391 * Wait for PCODE to finish disabling IPS. The BSpec specified
5392 * 42ms timeout value leads to occasional timeouts so use 100ms
5395 if (intel_wait_for_register(&dev_priv->uncore,
5396 IPS_CTL, IPS_ENABLE, 0,
5398 DRM_ERROR("Timed out waiting for IPS disable\n");
5400 I915_WRITE(IPS_CTL, 0);
5401 POSTING_READ(IPS_CTL);
5404 /* We need to wait for a vblank before we can disable the plane. */
5405 intel_wait_for_vblank(dev_priv, crtc->pipe);
5408 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5410 if (intel_crtc->overlay) {
5411 struct drm_device *dev = intel_crtc->base.dev;
5413 mutex_lock(&dev->struct_mutex);
5414 (void) intel_overlay_switch_off(intel_crtc->overlay);
5415 mutex_unlock(&dev->struct_mutex);
5418 /* Let userspace switch the overlay on again. In most cases userspace
5419 * has to recompute where to put it anyway.
5424 * intel_post_enable_primary - Perform operations after enabling primary plane
5425 * @crtc: the CRTC whose primary plane was just enabled
5426 * @new_crtc_state: the enabling state
5428 * Performs potentially sleeping operations that must be done after the primary
5429 * plane is enabled, such as updating FBC and IPS. Note that this may be
5430 * called due to an explicit primary plane update, or due to an implicit
5431 * re-enable that is caused when a sprite plane is updated to no longer
5432 * completely hide the primary plane.
5435 intel_post_enable_primary(struct drm_crtc *crtc,
5436 const struct intel_crtc_state *new_crtc_state)
5438 struct drm_device *dev = crtc->dev;
5439 struct drm_i915_private *dev_priv = to_i915(dev);
5440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5441 int pipe = intel_crtc->pipe;
5444 * Gen2 reports pipe underruns whenever all planes are disabled.
5445 * So don't enable underrun reporting before at least some planes
5447 * FIXME: Need to fix the logic to work when we turn off all planes
5448 * but leave the pipe running.
5450 if (IS_GEN(dev_priv, 2))
5451 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5453 /* Underruns don't always raise interrupts, so check manually. */
5454 intel_check_cpu_fifo_underruns(dev_priv);
5455 intel_check_pch_fifo_underruns(dev_priv);
5458 /* FIXME get rid of this and use pre_plane_update */
5460 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5462 struct drm_device *dev = crtc->dev;
5463 struct drm_i915_private *dev_priv = to_i915(dev);
5464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5465 int pipe = intel_crtc->pipe;
5468 * Gen2 reports pipe underruns whenever all planes are disabled.
5469 * So disable underrun reporting before all the planes get disabled.
5471 if (IS_GEN(dev_priv, 2))
5472 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5474 hsw_disable_ips(to_intel_crtc_state(crtc->state));
5477 * Vblank time updates from the shadow to live plane control register
5478 * are blocked if the memory self-refresh mode is active at that
5479 * moment. So to make sure the plane gets truly disabled, disable
5480 * first the self-refresh mode. The self-refresh enable bit in turn
5481 * will be checked/applied by the HW only at the next frame start
5482 * event which is after the vblank start event, so we need to have a
5483 * wait-for-vblank between disabling the plane and the pipe.
5485 if (HAS_GMCH(dev_priv) &&
5486 intel_set_memory_cxsr(dev_priv, false))
5487 intel_wait_for_vblank(dev_priv, pipe);
5490 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5491 const struct intel_crtc_state *new_crtc_state)
5493 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5494 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5496 if (!old_crtc_state->ips_enabled)
5499 if (needs_modeset(&new_crtc_state->base))
5503 * Workaround : Do not read or write the pipe palette/gamma data while
5504 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5506 * Disable IPS before we program the LUT.
5508 if (IS_HASWELL(dev_priv) &&
5509 (new_crtc_state->base.color_mgmt_changed ||
5510 new_crtc_state->update_pipe) &&
5511 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5514 return !new_crtc_state->ips_enabled;
5517 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5518 const struct intel_crtc_state *new_crtc_state)
5520 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5521 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5523 if (!new_crtc_state->ips_enabled)
5526 if (needs_modeset(&new_crtc_state->base))
5530 * Workaround : Do not read or write the pipe palette/gamma data while
5531 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5533 * Re-enable IPS after the LUT has been programmed.
5535 if (IS_HASWELL(dev_priv) &&
5536 (new_crtc_state->base.color_mgmt_changed ||
5537 new_crtc_state->update_pipe) &&
5538 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5542 * We can't read out IPS on broadwell, assume the worst and
5543 * forcibly enable IPS on the first fastset.
5545 if (new_crtc_state->update_pipe &&
5546 old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5549 return !old_crtc_state->ips_enabled;
5552 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5553 const struct intel_crtc_state *crtc_state)
5555 if (!crtc_state->nv12_planes)
5558 /* WA Display #0827: Gen9:all */
5559 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
5565 static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
5566 const struct intel_crtc_state *crtc_state)
5568 /* Wa_2006604312:icl */
5569 if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
5575 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5577 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5578 struct drm_device *dev = crtc->base.dev;
5579 struct drm_i915_private *dev_priv = to_i915(dev);
5580 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5581 struct intel_crtc_state *pipe_config =
5582 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5584 struct drm_plane *primary = crtc->base.primary;
5585 struct drm_plane_state *old_primary_state =
5586 drm_atomic_get_old_plane_state(old_state, primary);
5588 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5590 if (pipe_config->update_wm_post && pipe_config->base.active)
5591 intel_update_watermarks(crtc);
5593 if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5594 hsw_enable_ips(pipe_config);
5596 if (old_primary_state) {
5597 struct drm_plane_state *new_primary_state =
5598 drm_atomic_get_new_plane_state(old_state, primary);
5600 intel_fbc_post_update(crtc);
5602 if (new_primary_state->visible &&
5603 (needs_modeset(&pipe_config->base) ||
5604 !old_primary_state->visible))
5605 intel_post_enable_primary(&crtc->base, pipe_config);
5608 if (needs_nv12_wa(dev_priv, old_crtc_state) &&
5609 !needs_nv12_wa(dev_priv, pipe_config))
5610 skl_wa_827(dev_priv, crtc->pipe, false);
5612 if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
5613 !needs_scalerclk_wa(dev_priv, pipe_config))
5614 icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
5617 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5618 struct intel_crtc_state *pipe_config)
5620 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5621 struct drm_device *dev = crtc->base.dev;
5622 struct drm_i915_private *dev_priv = to_i915(dev);
5623 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5624 struct drm_plane *primary = crtc->base.primary;
5625 struct drm_plane_state *old_primary_state =
5626 drm_atomic_get_old_plane_state(old_state, primary);
5627 bool modeset = needs_modeset(&pipe_config->base);
5628 struct intel_atomic_state *old_intel_state =
5629 to_intel_atomic_state(old_state);
5631 if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5632 hsw_disable_ips(old_crtc_state);
5634 if (old_primary_state) {
5635 struct intel_plane_state *new_primary_state =
5636 intel_atomic_get_new_plane_state(old_intel_state,
5637 to_intel_plane(primary));
5639 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
5641 * Gen2 reports pipe underruns whenever all planes are disabled.
5642 * So disable underrun reporting before all the planes get disabled.
5644 if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
5645 (modeset || !new_primary_state->base.visible))
5646 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5649 /* Display WA 827 */
5650 if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
5651 needs_nv12_wa(dev_priv, pipe_config))
5652 skl_wa_827(dev_priv, crtc->pipe, true);
5654 /* Wa_2006604312:icl */
5655 if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
5656 needs_scalerclk_wa(dev_priv, pipe_config))
5657 icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
5660 * Vblank time updates from the shadow to live plane control register
5661 * are blocked if the memory self-refresh mode is active at that
5662 * moment. So to make sure the plane gets truly disabled, disable
5663 * first the self-refresh mode. The self-refresh enable bit in turn
5664 * will be checked/applied by the HW only at the next frame start
5665 * event which is after the vblank start event, so we need to have a
5666 * wait-for-vblank between disabling the plane and the pipe.
5668 if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
5669 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5670 intel_wait_for_vblank(dev_priv, crtc->pipe);
5673 * IVB workaround: must disable low power watermarks for at least
5674 * one frame before enabling scaling. LP watermarks can be re-enabled
5675 * when scaling is disabled.
5677 * WaCxSRDisabledForSpriteScaling:ivb
5679 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
5680 old_crtc_state->base.active)
5681 intel_wait_for_vblank(dev_priv, crtc->pipe);
5684 * If we're doing a modeset, we're done. No need to do any pre-vblank
5685 * watermark programming here.
5687 if (needs_modeset(&pipe_config->base))
5691 * For platforms that support atomic watermarks, program the
5692 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5693 * will be the intermediate values that are safe for both pre- and
5694 * post- vblank; when vblank happens, the 'active' values will be set
5695 * to the final 'target' values and we'll do this again to get the
5696 * optimal watermarks. For gen9+ platforms, the values we program here
5697 * will be the final target values which will get automatically latched
5698 * at vblank time; no further programming will be necessary.
5700 * If a platform hasn't been transitioned to atomic watermarks yet,
5701 * we'll continue to update watermarks the old way, if flags tell
5704 if (dev_priv->display.initial_watermarks != NULL)
5705 dev_priv->display.initial_watermarks(old_intel_state,
5707 else if (pipe_config->update_wm_pre)
5708 intel_update_watermarks(crtc);
5711 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
5712 struct intel_crtc *crtc)
5714 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5715 const struct intel_crtc_state *new_crtc_state =
5716 intel_atomic_get_new_crtc_state(state, crtc);
5717 unsigned int update_mask = new_crtc_state->update_planes;
5718 const struct intel_plane_state *old_plane_state;
5719 struct intel_plane *plane;
5720 unsigned fb_bits = 0;
5723 intel_crtc_dpms_overlay_disable(crtc);
5725 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
5726 if (crtc->pipe != plane->pipe ||
5727 !(update_mask & BIT(plane->id)))
5730 intel_disable_plane(plane, new_crtc_state);
5732 if (old_plane_state->base.visible)
5733 fb_bits |= plane->frontbuffer_bit;
5736 intel_frontbuffer_flip(dev_priv, fb_bits);
5739 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5740 struct intel_crtc_state *crtc_state,
5741 struct drm_atomic_state *old_state)
5743 struct drm_connector_state *conn_state;
5744 struct drm_connector *conn;
5747 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5748 struct intel_encoder *encoder =
5749 to_intel_encoder(conn_state->best_encoder);
5751 if (conn_state->crtc != crtc)
5754 if (encoder->pre_pll_enable)
5755 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5759 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5760 struct intel_crtc_state *crtc_state,
5761 struct drm_atomic_state *old_state)
5763 struct drm_connector_state *conn_state;
5764 struct drm_connector *conn;
5767 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5768 struct intel_encoder *encoder =
5769 to_intel_encoder(conn_state->best_encoder);
5771 if (conn_state->crtc != crtc)
5774 if (encoder->pre_enable)
5775 encoder->pre_enable(encoder, crtc_state, conn_state);
5779 static void intel_encoders_enable(struct drm_crtc *crtc,
5780 struct intel_crtc_state *crtc_state,
5781 struct drm_atomic_state *old_state)
5783 struct drm_connector_state *conn_state;
5784 struct drm_connector *conn;
5787 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5788 struct intel_encoder *encoder =
5789 to_intel_encoder(conn_state->best_encoder);
5791 if (conn_state->crtc != crtc)
5794 if (encoder->enable)
5795 encoder->enable(encoder, crtc_state, conn_state);
5796 intel_opregion_notify_encoder(encoder, true);
5800 static void intel_encoders_disable(struct drm_crtc *crtc,
5801 struct intel_crtc_state *old_crtc_state,
5802 struct drm_atomic_state *old_state)
5804 struct drm_connector_state *old_conn_state;
5805 struct drm_connector *conn;
5808 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5809 struct intel_encoder *encoder =
5810 to_intel_encoder(old_conn_state->best_encoder);
5812 if (old_conn_state->crtc != crtc)
5815 intel_opregion_notify_encoder(encoder, false);
5816 if (encoder->disable)
5817 encoder->disable(encoder, old_crtc_state, old_conn_state);
5821 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5822 struct intel_crtc_state *old_crtc_state,
5823 struct drm_atomic_state *old_state)
5825 struct drm_connector_state *old_conn_state;
5826 struct drm_connector *conn;
5829 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5830 struct intel_encoder *encoder =
5831 to_intel_encoder(old_conn_state->best_encoder);
5833 if (old_conn_state->crtc != crtc)
5836 if (encoder->post_disable)
5837 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5841 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5842 struct intel_crtc_state *old_crtc_state,
5843 struct drm_atomic_state *old_state)
5845 struct drm_connector_state *old_conn_state;
5846 struct drm_connector *conn;
5849 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5850 struct intel_encoder *encoder =
5851 to_intel_encoder(old_conn_state->best_encoder);
5853 if (old_conn_state->crtc != crtc)
5856 if (encoder->post_pll_disable)
5857 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5861 static void intel_encoders_update_pipe(struct drm_crtc *crtc,
5862 struct intel_crtc_state *crtc_state,
5863 struct drm_atomic_state *old_state)
5865 struct drm_connector_state *conn_state;
5866 struct drm_connector *conn;
5869 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5870 struct intel_encoder *encoder =
5871 to_intel_encoder(conn_state->best_encoder);
5873 if (conn_state->crtc != crtc)
5876 if (encoder->update_pipe)
5877 encoder->update_pipe(encoder, crtc_state, conn_state);
5881 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
5883 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5884 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
5886 plane->disable_plane(plane, crtc_state);
5889 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5890 struct drm_atomic_state *old_state)
5892 struct drm_crtc *crtc = pipe_config->base.crtc;
5893 struct drm_device *dev = crtc->dev;
5894 struct drm_i915_private *dev_priv = to_i915(dev);
5895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5896 int pipe = intel_crtc->pipe;
5897 struct intel_atomic_state *old_intel_state =
5898 to_intel_atomic_state(old_state);
5900 if (WARN_ON(intel_crtc->active))
5904 * Sometimes spurious CPU pipe underruns happen during FDI
5905 * training, at least with VGA+HDMI cloning. Suppress them.
5907 * On ILK we get an occasional spurious CPU pipe underruns
5908 * between eDP port A enable and vdd enable. Also PCH port
5909 * enable seems to result in the occasional CPU pipe underrun.
5911 * Spurious PCH underruns also occur during PCH enabling.
5913 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5914 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5916 if (pipe_config->has_pch_encoder)
5917 intel_prepare_shared_dpll(pipe_config);
5919 if (intel_crtc_has_dp_encoder(pipe_config))
5920 intel_dp_set_m_n(pipe_config, M1_N1);
5922 intel_set_pipe_timings(pipe_config);
5923 intel_set_pipe_src_size(pipe_config);
5925 if (pipe_config->has_pch_encoder) {
5926 intel_cpu_transcoder_set_m_n(pipe_config,
5927 &pipe_config->fdi_m_n, NULL);
5930 ironlake_set_pipeconf(pipe_config);
5932 intel_crtc->active = true;
5934 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5936 if (pipe_config->has_pch_encoder) {
5937 /* Note: FDI PLL enabling _must_ be done before we enable the
5938 * cpu pipes, hence this is separate from all the other fdi/pch
5940 ironlake_fdi_pll_enable(pipe_config);
5942 assert_fdi_tx_disabled(dev_priv, pipe);
5943 assert_fdi_rx_disabled(dev_priv, pipe);
5946 ironlake_pfit_enable(pipe_config);
5949 * On ILK+ LUT must be loaded before the pipe is running but with
5952 intel_color_load_luts(pipe_config);
5953 intel_color_commit(pipe_config);
5954 /* update DSPCNTR to configure gamma for pipe bottom color */
5955 intel_disable_primary_plane(pipe_config);
5957 if (dev_priv->display.initial_watermarks != NULL)
5958 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5959 intel_enable_pipe(pipe_config);
5961 if (pipe_config->has_pch_encoder)
5962 ironlake_pch_enable(old_intel_state, pipe_config);
5964 assert_vblank_disabled(crtc);
5965 intel_crtc_vblank_on(pipe_config);
5967 intel_encoders_enable(crtc, pipe_config, old_state);
5969 if (HAS_PCH_CPT(dev_priv))
5970 cpt_verify_modeset(dev, intel_crtc->pipe);
5973 * Must wait for vblank to avoid spurious PCH FIFO underruns.
5974 * And a second vblank wait is needed at least on ILK with
5975 * some interlaced HDMI modes. Let's do the double wait always
5976 * in case there are more corner cases we don't know about.
5978 if (pipe_config->has_pch_encoder) {
5979 intel_wait_for_vblank(dev_priv, pipe);
5980 intel_wait_for_vblank(dev_priv, pipe);
5982 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5983 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5986 /* IPS only exists on ULT machines and is tied to pipe A. */
5987 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5989 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5992 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5993 enum pipe pipe, bool apply)
5995 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5996 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6003 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
6006 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6008 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6009 enum pipe pipe = crtc->pipe;
6012 val = MBUS_DBOX_A_CREDIT(2);
6013 val |= MBUS_DBOX_BW_CREDIT(1);
6014 val |= MBUS_DBOX_B_CREDIT(8);
6016 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
6019 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
6020 struct drm_atomic_state *old_state)
6022 struct drm_crtc *crtc = pipe_config->base.crtc;
6023 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6025 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
6026 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6027 struct intel_atomic_state *old_intel_state =
6028 to_intel_atomic_state(old_state);
6029 bool psl_clkgate_wa;
6031 if (WARN_ON(intel_crtc->active))
6034 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6036 if (pipe_config->shared_dpll)
6037 intel_enable_shared_dpll(pipe_config);
6039 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6041 if (intel_crtc_has_dp_encoder(pipe_config))
6042 intel_dp_set_m_n(pipe_config, M1_N1);
6044 if (!transcoder_is_dsi(cpu_transcoder))
6045 intel_set_pipe_timings(pipe_config);
6047 intel_set_pipe_src_size(pipe_config);
6049 if (cpu_transcoder != TRANSCODER_EDP &&
6050 !transcoder_is_dsi(cpu_transcoder)) {
6051 I915_WRITE(PIPE_MULT(cpu_transcoder),
6052 pipe_config->pixel_multiplier - 1);
6055 if (pipe_config->has_pch_encoder) {
6056 intel_cpu_transcoder_set_m_n(pipe_config,
6057 &pipe_config->fdi_m_n, NULL);
6060 if (!transcoder_is_dsi(cpu_transcoder))
6061 haswell_set_pipeconf(pipe_config);
6063 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6064 bdw_set_pipemisc(pipe_config);
6066 intel_crtc->active = true;
6068 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6069 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
6070 pipe_config->pch_pfit.enabled;
6072 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
6074 if (INTEL_GEN(dev_priv) >= 9)
6075 skylake_pfit_enable(pipe_config);
6077 ironlake_pfit_enable(pipe_config);
6080 * On ILK+ LUT must be loaded before the pipe is running but with
6083 intel_color_load_luts(pipe_config);
6084 intel_color_commit(pipe_config);
6085 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6086 if (INTEL_GEN(dev_priv) < 9)
6087 intel_disable_primary_plane(pipe_config);
6089 if (INTEL_GEN(dev_priv) >= 11)
6090 icl_set_pipe_chicken(intel_crtc);
6092 intel_ddi_set_pipe_settings(pipe_config);
6093 if (!transcoder_is_dsi(cpu_transcoder))
6094 intel_ddi_enable_transcoder_func(pipe_config);
6096 if (dev_priv->display.initial_watermarks != NULL)
6097 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
6099 if (INTEL_GEN(dev_priv) >= 11)
6100 icl_pipe_mbus_enable(intel_crtc);
6102 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6103 if (!transcoder_is_dsi(cpu_transcoder))
6104 intel_enable_pipe(pipe_config);
6106 if (pipe_config->has_pch_encoder)
6107 lpt_pch_enable(old_intel_state, pipe_config);
6109 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
6110 intel_ddi_set_vc_payload_alloc(pipe_config, true);
6112 assert_vblank_disabled(crtc);
6113 intel_crtc_vblank_on(pipe_config);
6115 intel_encoders_enable(crtc, pipe_config, old_state);
6117 if (psl_clkgate_wa) {
6118 intel_wait_for_vblank(dev_priv, pipe);
6119 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6122 /* If we change the relative order between pipe/planes enabling, we need
6123 * to change the workaround. */
6124 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
6125 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6126 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6127 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6131 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6133 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6134 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6135 enum pipe pipe = crtc->pipe;
6137 /* To avoid upsetting the power well on haswell only disable the pfit if
6138 * it's in use. The hw state code will make sure we get this right. */
6139 if (old_crtc_state->pch_pfit.enabled) {
6140 I915_WRITE(PF_CTL(pipe), 0);
6141 I915_WRITE(PF_WIN_POS(pipe), 0);
6142 I915_WRITE(PF_WIN_SZ(pipe), 0);
6146 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
6147 struct drm_atomic_state *old_state)
6149 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6150 struct drm_device *dev = crtc->dev;
6151 struct drm_i915_private *dev_priv = to_i915(dev);
6152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6153 int pipe = intel_crtc->pipe;
6156 * Sometimes spurious CPU pipe underruns happen when the
6157 * pipe is already disabled, but FDI RX/TX is still enabled.
6158 * Happens at least with VGA+HDMI cloning. Suppress them.
6160 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6161 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6163 intel_encoders_disable(crtc, old_crtc_state, old_state);
6165 drm_crtc_vblank_off(crtc);
6166 assert_vblank_disabled(crtc);
6168 intel_disable_pipe(old_crtc_state);
6170 ironlake_pfit_disable(old_crtc_state);
6172 if (old_crtc_state->has_pch_encoder)
6173 ironlake_fdi_disable(crtc);
6175 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6177 if (old_crtc_state->has_pch_encoder) {
6178 ironlake_disable_pch_transcoder(dev_priv, pipe);
6180 if (HAS_PCH_CPT(dev_priv)) {
6184 /* disable TRANS_DP_CTL */
6185 reg = TRANS_DP_CTL(pipe);
6186 temp = I915_READ(reg);
6187 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6188 TRANS_DP_PORT_SEL_MASK);
6189 temp |= TRANS_DP_PORT_SEL_NONE;
6190 I915_WRITE(reg, temp);
6192 /* disable DPLL_SEL */
6193 temp = I915_READ(PCH_DPLL_SEL);
6194 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6195 I915_WRITE(PCH_DPLL_SEL, temp);
6198 ironlake_fdi_pll_disable(intel_crtc);
6201 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6202 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6205 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
6206 struct drm_atomic_state *old_state)
6208 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6209 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6211 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6213 intel_encoders_disable(crtc, old_crtc_state, old_state);
6215 drm_crtc_vblank_off(crtc);
6216 assert_vblank_disabled(crtc);
6218 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6219 if (!transcoder_is_dsi(cpu_transcoder))
6220 intel_disable_pipe(old_crtc_state);
6222 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
6223 intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
6225 if (!transcoder_is_dsi(cpu_transcoder))
6226 intel_ddi_disable_transcoder_func(old_crtc_state);
6228 intel_dsc_disable(old_crtc_state);
6230 if (INTEL_GEN(dev_priv) >= 9)
6231 skylake_scaler_disable(intel_crtc);
6233 ironlake_pfit_disable(old_crtc_state);
6235 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6237 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6240 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6242 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6243 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6245 if (!crtc_state->gmch_pfit.control)
6249 * The panel fitter should only be adjusted whilst the pipe is disabled,
6250 * according to register description and PRM.
6252 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6253 assert_pipe_disabled(dev_priv, crtc->pipe);
6255 I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6256 I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6258 /* Border color in case we don't scale up to the full screen. Black by
6259 * default, change to something else for debugging. */
6260 I915_WRITE(BCLRPAT(crtc->pipe), 0);
6263 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
6265 if (port == PORT_NONE)
6268 if (IS_ELKHARTLAKE(dev_priv))
6269 return port <= PORT_C;
6271 if (INTEL_GEN(dev_priv) >= 11)
6272 return port <= PORT_B;
6277 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
6279 if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6280 return port >= PORT_C && port <= PORT_F;
6285 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6287 if (!intel_port_is_tc(dev_priv, port))
6288 return PORT_TC_NONE;
6290 return port - PORT_C;
6293 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6297 return POWER_DOMAIN_PORT_DDI_A_LANES;
6299 return POWER_DOMAIN_PORT_DDI_B_LANES;
6301 return POWER_DOMAIN_PORT_DDI_C_LANES;
6303 return POWER_DOMAIN_PORT_DDI_D_LANES;
6305 return POWER_DOMAIN_PORT_DDI_E_LANES;
6307 return POWER_DOMAIN_PORT_DDI_F_LANES;
6310 return POWER_DOMAIN_PORT_OTHER;
6314 enum intel_display_power_domain
6315 intel_aux_power_domain(struct intel_digital_port *dig_port)
6317 switch (dig_port->aux_ch) {
6319 return POWER_DOMAIN_AUX_A;
6321 return POWER_DOMAIN_AUX_B;
6323 return POWER_DOMAIN_AUX_C;
6325 return POWER_DOMAIN_AUX_D;
6327 return POWER_DOMAIN_AUX_E;
6329 return POWER_DOMAIN_AUX_F;
6331 MISSING_CASE(dig_port->aux_ch);
6332 return POWER_DOMAIN_AUX_A;
6336 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
6337 struct intel_crtc_state *crtc_state)
6339 struct drm_device *dev = crtc->dev;
6340 struct drm_i915_private *dev_priv = to_i915(dev);
6341 struct drm_encoder *encoder;
6342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6343 enum pipe pipe = intel_crtc->pipe;
6345 enum transcoder transcoder = crtc_state->cpu_transcoder;
6347 if (!crtc_state->base.active)
6350 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6351 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6352 if (crtc_state->pch_pfit.enabled ||
6353 crtc_state->pch_pfit.force_thru)
6354 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6356 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
6357 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6359 mask |= BIT_ULL(intel_encoder->power_domain);
6362 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6363 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6365 if (crtc_state->shared_dpll)
6366 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
6372 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
6373 struct intel_crtc_state *crtc_state)
6375 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6377 enum intel_display_power_domain domain;
6378 u64 domains, new_domains, old_domains;
6380 old_domains = intel_crtc->enabled_power_domains;
6381 intel_crtc->enabled_power_domains = new_domains =
6382 get_crtc_power_domains(crtc, crtc_state);
6384 domains = new_domains & ~old_domains;
6386 for_each_power_domain(domain, domains)
6387 intel_display_power_get(dev_priv, domain);
6389 return old_domains & ~new_domains;
6392 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
6395 enum intel_display_power_domain domain;
6397 for_each_power_domain(domain, domains)
6398 intel_display_power_put_unchecked(dev_priv, domain);
6401 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6402 struct drm_atomic_state *old_state)
6404 struct intel_atomic_state *old_intel_state =
6405 to_intel_atomic_state(old_state);
6406 struct drm_crtc *crtc = pipe_config->base.crtc;
6407 struct drm_device *dev = crtc->dev;
6408 struct drm_i915_private *dev_priv = to_i915(dev);
6409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6410 int pipe = intel_crtc->pipe;
6412 if (WARN_ON(intel_crtc->active))
6415 if (intel_crtc_has_dp_encoder(pipe_config))
6416 intel_dp_set_m_n(pipe_config, M1_N1);
6418 intel_set_pipe_timings(pipe_config);
6419 intel_set_pipe_src_size(pipe_config);
6421 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6422 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6423 I915_WRITE(CHV_CANVAS(pipe), 0);
6426 i9xx_set_pipeconf(pipe_config);
6428 intel_crtc->active = true;
6430 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6432 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6434 if (IS_CHERRYVIEW(dev_priv)) {
6435 chv_prepare_pll(intel_crtc, pipe_config);
6436 chv_enable_pll(intel_crtc, pipe_config);
6438 vlv_prepare_pll(intel_crtc, pipe_config);
6439 vlv_enable_pll(intel_crtc, pipe_config);
6442 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6444 i9xx_pfit_enable(pipe_config);
6446 intel_color_load_luts(pipe_config);
6447 intel_color_commit(pipe_config);
6448 /* update DSPCNTR to configure gamma for pipe bottom color */
6449 intel_disable_primary_plane(pipe_config);
6451 dev_priv->display.initial_watermarks(old_intel_state,
6453 intel_enable_pipe(pipe_config);
6455 assert_vblank_disabled(crtc);
6456 intel_crtc_vblank_on(pipe_config);
6458 intel_encoders_enable(crtc, pipe_config, old_state);
6461 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
6463 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6466 I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
6467 I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
6470 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6471 struct drm_atomic_state *old_state)
6473 struct intel_atomic_state *old_intel_state =
6474 to_intel_atomic_state(old_state);
6475 struct drm_crtc *crtc = pipe_config->base.crtc;
6476 struct drm_device *dev = crtc->dev;
6477 struct drm_i915_private *dev_priv = to_i915(dev);
6478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6479 enum pipe pipe = intel_crtc->pipe;
6481 if (WARN_ON(intel_crtc->active))
6484 i9xx_set_pll_dividers(pipe_config);
6486 if (intel_crtc_has_dp_encoder(pipe_config))
6487 intel_dp_set_m_n(pipe_config, M1_N1);
6489 intel_set_pipe_timings(pipe_config);
6490 intel_set_pipe_src_size(pipe_config);
6492 i9xx_set_pipeconf(pipe_config);
6494 intel_crtc->active = true;
6496 if (!IS_GEN(dev_priv, 2))
6497 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6499 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6501 i9xx_enable_pll(intel_crtc, pipe_config);
6503 i9xx_pfit_enable(pipe_config);
6505 intel_color_load_luts(pipe_config);
6506 intel_color_commit(pipe_config);
6507 /* update DSPCNTR to configure gamma for pipe bottom color */
6508 intel_disable_primary_plane(pipe_config);
6510 if (dev_priv->display.initial_watermarks != NULL)
6511 dev_priv->display.initial_watermarks(old_intel_state,
6514 intel_update_watermarks(intel_crtc);
6515 intel_enable_pipe(pipe_config);
6517 assert_vblank_disabled(crtc);
6518 intel_crtc_vblank_on(pipe_config);
6520 intel_encoders_enable(crtc, pipe_config, old_state);
6523 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6525 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6526 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6528 if (!old_crtc_state->gmch_pfit.control)
6531 assert_pipe_disabled(dev_priv, crtc->pipe);
6533 DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
6534 I915_READ(PFIT_CONTROL));
6535 I915_WRITE(PFIT_CONTROL, 0);
6538 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6539 struct drm_atomic_state *old_state)
6541 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6542 struct drm_device *dev = crtc->dev;
6543 struct drm_i915_private *dev_priv = to_i915(dev);
6544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6545 int pipe = intel_crtc->pipe;
6548 * On gen2 planes are double buffered but the pipe isn't, so we must
6549 * wait for planes to fully turn off before disabling the pipe.
6551 if (IS_GEN(dev_priv, 2))
6552 intel_wait_for_vblank(dev_priv, pipe);
6554 intel_encoders_disable(crtc, old_crtc_state, old_state);
6556 drm_crtc_vblank_off(crtc);
6557 assert_vblank_disabled(crtc);
6559 intel_disable_pipe(old_crtc_state);
6561 i9xx_pfit_disable(old_crtc_state);
6563 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6565 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
6566 if (IS_CHERRYVIEW(dev_priv))
6567 chv_disable_pll(dev_priv, pipe);
6568 else if (IS_VALLEYVIEW(dev_priv))
6569 vlv_disable_pll(dev_priv, pipe);
6571 i9xx_disable_pll(old_crtc_state);
6574 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6576 if (!IS_GEN(dev_priv, 2))
6577 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6579 if (!dev_priv->display.initial_watermarks)
6580 intel_update_watermarks(intel_crtc);
6582 /* clock the pipe down to 640x480@60 to potentially save power */
6583 if (IS_I830(dev_priv))
6584 i830_enable_pipe(dev_priv, pipe);
6587 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6588 struct drm_modeset_acquire_ctx *ctx)
6590 struct intel_encoder *encoder;
6591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6592 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6593 enum intel_display_power_domain domain;
6594 struct intel_plane *plane;
6596 struct drm_atomic_state *state;
6597 struct intel_crtc_state *crtc_state;
6600 if (!intel_crtc->active)
6603 for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
6604 const struct intel_plane_state *plane_state =
6605 to_intel_plane_state(plane->base.state);
6607 if (plane_state->base.visible)
6608 intel_plane_disable_noatomic(intel_crtc, plane);
6611 state = drm_atomic_state_alloc(crtc->dev);
6613 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6614 crtc->base.id, crtc->name);
6618 state->acquire_ctx = ctx;
6620 /* Everything's already locked, -EDEADLK can't happen. */
6621 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6622 ret = drm_atomic_add_affected_connectors(state, crtc);
6624 WARN_ON(IS_ERR(crtc_state) || ret);
6626 dev_priv->display.crtc_disable(crtc_state, state);
6628 drm_atomic_state_put(state);
6630 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6631 crtc->base.id, crtc->name);
6633 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6634 crtc->state->active = false;
6635 intel_crtc->active = false;
6636 crtc->enabled = false;
6637 crtc->state->connector_mask = 0;
6638 crtc->state->encoder_mask = 0;
6640 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6641 encoder->base.crtc = NULL;
6643 intel_fbc_disable(intel_crtc);
6644 intel_update_watermarks(intel_crtc);
6645 intel_disable_shared_dpll(to_intel_crtc_state(crtc->state));
6647 domains = intel_crtc->enabled_power_domains;
6648 for_each_power_domain(domain, domains)
6649 intel_display_power_put_unchecked(dev_priv, domain);
6650 intel_crtc->enabled_power_domains = 0;
6652 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6653 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6654 dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
6658 * turn all crtc's off, but do not adjust state
6659 * This has to be paired with a call to intel_modeset_setup_hw_state.
6661 int intel_display_suspend(struct drm_device *dev)
6663 struct drm_i915_private *dev_priv = to_i915(dev);
6664 struct drm_atomic_state *state;
6667 state = drm_atomic_helper_suspend(dev);
6668 ret = PTR_ERR_OR_ZERO(state);
6670 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6672 dev_priv->modeset_restore_state = state;
6676 void intel_encoder_destroy(struct drm_encoder *encoder)
6678 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6680 drm_encoder_cleanup(encoder);
6681 kfree(intel_encoder);
6684 /* Cross check the actual hw state with our own modeset state tracking (and it's
6685 * internal consistency). */
6686 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6687 struct drm_connector_state *conn_state)
6689 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6691 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6692 connector->base.base.id,
6693 connector->base.name);
6695 if (connector->get_hw_state(connector)) {
6696 struct intel_encoder *encoder = connector->encoder;
6698 I915_STATE_WARN(!crtc_state,
6699 "connector enabled without attached crtc\n");
6704 I915_STATE_WARN(!crtc_state->active,
6705 "connector is active, but attached crtc isn't\n");
6707 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6710 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6711 "atomic encoder doesn't match attached encoder\n");
6713 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6714 "attached encoder crtc differs from connector crtc\n");
6716 I915_STATE_WARN(crtc_state && crtc_state->active,
6717 "attached crtc is active, but connector isn't\n");
6718 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6719 "best encoder set without crtc!\n");
6723 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6725 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6726 return crtc_state->fdi_lanes;
6731 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6732 struct intel_crtc_state *pipe_config)
6734 struct drm_i915_private *dev_priv = to_i915(dev);
6735 struct drm_atomic_state *state = pipe_config->base.state;
6736 struct intel_crtc *other_crtc;
6737 struct intel_crtc_state *other_crtc_state;
6739 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6740 pipe_name(pipe), pipe_config->fdi_lanes);
6741 if (pipe_config->fdi_lanes > 4) {
6742 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6743 pipe_name(pipe), pipe_config->fdi_lanes);
6747 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6748 if (pipe_config->fdi_lanes > 2) {
6749 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6750 pipe_config->fdi_lanes);
6757 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6760 /* Ivybridge 3 pipe is really complicated */
6765 if (pipe_config->fdi_lanes <= 2)
6768 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6770 intel_atomic_get_crtc_state(state, other_crtc);
6771 if (IS_ERR(other_crtc_state))
6772 return PTR_ERR(other_crtc_state);
6774 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6775 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6776 pipe_name(pipe), pipe_config->fdi_lanes);
6781 if (pipe_config->fdi_lanes > 2) {
6782 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6783 pipe_name(pipe), pipe_config->fdi_lanes);
6787 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6789 intel_atomic_get_crtc_state(state, other_crtc);
6790 if (IS_ERR(other_crtc_state))
6791 return PTR_ERR(other_crtc_state);
6793 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6794 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6804 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6805 struct intel_crtc_state *pipe_config)
6807 struct drm_device *dev = intel_crtc->base.dev;
6808 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6809 int lane, link_bw, fdi_dotclock, ret;
6810 bool needs_recompute = false;
6813 /* FDI is a binary signal running at ~2.7GHz, encoding
6814 * each output octet as 10 bits. The actual frequency
6815 * is stored as a divider into a 100MHz clock, and the
6816 * mode pixel clock is stored in units of 1KHz.
6817 * Hence the bw of each lane in terms of the mode signal
6820 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6822 fdi_dotclock = adjusted_mode->crtc_clock;
6824 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6825 pipe_config->pipe_bpp);
6827 pipe_config->fdi_lanes = lane;
6829 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6830 link_bw, &pipe_config->fdi_m_n, false);
6832 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6833 if (ret == -EDEADLK)
6836 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6837 pipe_config->pipe_bpp -= 2*3;
6838 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6839 pipe_config->pipe_bpp);
6840 needs_recompute = true;
6841 pipe_config->bw_constrained = true;
6846 if (needs_recompute)
6852 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6854 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6855 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6857 /* IPS only exists on ULT machines and is tied to pipe A. */
6858 if (!hsw_crtc_supports_ips(crtc))
6861 if (!i915_modparams.enable_ips)
6864 if (crtc_state->pipe_bpp > 24)
6868 * We compare against max which means we must take
6869 * the increased cdclk requirement into account when
6870 * calculating the new cdclk.
6872 * Should measure whether using a lower cdclk w/o IPS
6874 if (IS_BROADWELL(dev_priv) &&
6875 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6881 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6883 struct drm_i915_private *dev_priv =
6884 to_i915(crtc_state->base.crtc->dev);
6885 struct intel_atomic_state *intel_state =
6886 to_intel_atomic_state(crtc_state->base.state);
6888 if (!hsw_crtc_state_ips_capable(crtc_state))
6892 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
6893 * enabled and disabled dynamically based on package C states,
6894 * user space can't make reliable use of the CRCs, so let's just
6895 * completely disable it.
6897 if (crtc_state->crc_enabled)
6900 /* IPS should be fine as long as at least one plane is enabled. */
6901 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6904 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6905 if (IS_BROADWELL(dev_priv) &&
6906 crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
6912 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6914 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6916 /* GDG double wide on either pipe, otherwise pipe A only */
6917 return INTEL_GEN(dev_priv) < 4 &&
6918 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6921 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6925 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6928 * We only use IF-ID interlacing. If we ever use
6929 * PF-ID we'll need to adjust the pixel_rate here.
6932 if (pipe_config->pch_pfit.enabled) {
6933 u64 pipe_w, pipe_h, pfit_w, pfit_h;
6934 u32 pfit_size = pipe_config->pch_pfit.size;
6936 pipe_w = pipe_config->pipe_src_w;
6937 pipe_h = pipe_config->pipe_src_h;
6939 pfit_w = (pfit_size >> 16) & 0xFFFF;
6940 pfit_h = pfit_size & 0xFFFF;
6941 if (pipe_w < pfit_w)
6943 if (pipe_h < pfit_h)
6946 if (WARN_ON(!pfit_w || !pfit_h))
6949 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
6956 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6958 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6960 if (HAS_GMCH(dev_priv))
6961 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6962 crtc_state->pixel_rate =
6963 crtc_state->base.adjusted_mode.crtc_clock;
6965 crtc_state->pixel_rate =
6966 ilk_pipe_pixel_rate(crtc_state);
6969 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6970 struct intel_crtc_state *pipe_config)
6972 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6973 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6974 int clock_limit = dev_priv->max_dotclk_freq;
6976 if (INTEL_GEN(dev_priv) < 4) {
6977 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6980 * Enable double wide mode when the dot clock
6981 * is > 90% of the (display) core speed.
6983 if (intel_crtc_supports_double_wide(crtc) &&
6984 adjusted_mode->crtc_clock > clock_limit) {
6985 clock_limit = dev_priv->max_dotclk_freq;
6986 pipe_config->double_wide = true;
6990 if (adjusted_mode->crtc_clock > clock_limit) {
6991 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6992 adjusted_mode->crtc_clock, clock_limit,
6993 yesno(pipe_config->double_wide));
6997 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
6998 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
6999 pipe_config->base.ctm) {
7001 * There is only one pipe CSC unit per pipe, and we need that
7002 * for output conversion from RGB->YCBCR. So if CTM is already
7003 * applied we can't support YCBCR420 output.
7005 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
7010 * Pipe horizontal size must be even in:
7012 * - LVDS dual channel mode
7013 * - Double wide pipe
7015 if (pipe_config->pipe_src_w & 1) {
7016 if (pipe_config->double_wide) {
7017 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7021 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7022 intel_is_dual_link_lvds(dev_priv)) {
7023 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7028 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7029 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7031 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7032 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7035 intel_crtc_compute_pixel_rate(pipe_config);
7037 if (pipe_config->has_pch_encoder)
7038 return ironlake_fdi_compute_config(crtc, pipe_config);
7044 intel_reduce_m_n_ratio(u32 *num, u32 *den)
7046 while (*num > DATA_LINK_M_N_MASK ||
7047 *den > DATA_LINK_M_N_MASK) {
7053 static void compute_m_n(unsigned int m, unsigned int n,
7054 u32 *ret_m, u32 *ret_n,
7058 * Several DP dongles in particular seem to be fussy about
7059 * too large link M/N values. Give N value as 0x8000 that
7060 * should be acceptable by specific devices. 0x8000 is the
7061 * specified fixed N value for asynchronous clock mode,
7062 * which the devices expect also in synchronous clock mode.
7067 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7069 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
7070 intel_reduce_m_n_ratio(ret_m, ret_n);
7074 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
7075 int pixel_clock, int link_clock,
7076 struct intel_link_m_n *m_n,
7081 compute_m_n(bits_per_pixel * pixel_clock,
7082 link_clock * nlanes * 8,
7083 &m_n->gmch_m, &m_n->gmch_n,
7086 compute_m_n(pixel_clock, link_clock,
7087 &m_n->link_m, &m_n->link_n,
7091 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7093 if (i915_modparams.panel_use_ssc >= 0)
7094 return i915_modparams.panel_use_ssc != 0;
7095 return dev_priv->vbt.lvds_use_ssc
7096 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7099 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7101 return (1 << dpll->n) << 16 | dpll->m2;
7104 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7106 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7109 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7110 struct intel_crtc_state *crtc_state,
7111 struct dpll *reduced_clock)
7113 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7116 if (IS_PINEVIEW(dev_priv)) {
7117 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7119 fp2 = pnv_dpll_compute_fp(reduced_clock);
7121 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7123 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7126 crtc_state->dpll_hw_state.fp0 = fp;
7128 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7130 crtc_state->dpll_hw_state.fp1 = fp2;
7132 crtc_state->dpll_hw_state.fp1 = fp;
7136 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7142 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7143 * and set it to a reasonable value instead.
7145 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7146 reg_val &= 0xffffff00;
7147 reg_val |= 0x00000030;
7148 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7150 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7151 reg_val &= 0x00ffffff;
7152 reg_val |= 0x8c000000;
7153 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7155 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7156 reg_val &= 0xffffff00;
7157 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7159 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7160 reg_val &= 0x00ffffff;
7161 reg_val |= 0xb0000000;
7162 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7165 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7166 const struct intel_link_m_n *m_n)
7168 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7169 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7170 enum pipe pipe = crtc->pipe;
7172 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7173 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7174 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7175 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7178 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7179 enum transcoder transcoder)
7181 if (IS_HASWELL(dev_priv))
7182 return transcoder == TRANSCODER_EDP;
7185 * Strictly speaking some registers are available before
7186 * gen7, but we only support DRRS on gen7+
7188 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7191 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7192 const struct intel_link_m_n *m_n,
7193 const struct intel_link_m_n *m2_n2)
7195 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7196 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7197 enum pipe pipe = crtc->pipe;
7198 enum transcoder transcoder = crtc_state->cpu_transcoder;
7200 if (INTEL_GEN(dev_priv) >= 5) {
7201 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7202 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7203 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7204 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7206 * M2_N2 registers are set only if DRRS is supported
7207 * (to make sure the registers are not unnecessarily accessed).
7209 if (m2_n2 && crtc_state->has_drrs &&
7210 transcoder_has_m2_n2(dev_priv, transcoder)) {
7211 I915_WRITE(PIPE_DATA_M2(transcoder),
7212 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7213 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7214 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7215 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7218 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7219 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7220 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7221 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7225 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7227 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7230 dp_m_n = &crtc_state->dp_m_n;
7231 dp_m2_n2 = &crtc_state->dp_m2_n2;
7232 } else if (m_n == M2_N2) {
7235 * M2_N2 registers are not supported. Hence m2_n2 divider value
7236 * needs to be programmed into M1_N1.
7238 dp_m_n = &crtc_state->dp_m2_n2;
7240 DRM_ERROR("Unsupported divider value\n");
7244 if (crtc_state->has_pch_encoder)
7245 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7247 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7250 static void vlv_compute_dpll(struct intel_crtc *crtc,
7251 struct intel_crtc_state *pipe_config)
7253 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7254 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7255 if (crtc->pipe != PIPE_A)
7256 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7258 /* DPLL not used with DSI, but still need the rest set up */
7259 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7260 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7261 DPLL_EXT_BUFFER_ENABLE_VLV;
7263 pipe_config->dpll_hw_state.dpll_md =
7264 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7267 static void chv_compute_dpll(struct intel_crtc *crtc,
7268 struct intel_crtc_state *pipe_config)
7270 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7271 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7272 if (crtc->pipe != PIPE_A)
7273 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7275 /* DPLL not used with DSI, but still need the rest set up */
7276 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7277 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7279 pipe_config->dpll_hw_state.dpll_md =
7280 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7283 static void vlv_prepare_pll(struct intel_crtc *crtc,
7284 const struct intel_crtc_state *pipe_config)
7286 struct drm_device *dev = crtc->base.dev;
7287 struct drm_i915_private *dev_priv = to_i915(dev);
7288 enum pipe pipe = crtc->pipe;
7290 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7291 u32 coreclk, reg_val;
7294 I915_WRITE(DPLL(pipe),
7295 pipe_config->dpll_hw_state.dpll &
7296 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7298 /* No need to actually set up the DPLL with DSI */
7299 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7302 vlv_dpio_get(dev_priv);
7304 bestn = pipe_config->dpll.n;
7305 bestm1 = pipe_config->dpll.m1;
7306 bestm2 = pipe_config->dpll.m2;
7307 bestp1 = pipe_config->dpll.p1;
7308 bestp2 = pipe_config->dpll.p2;
7310 /* See eDP HDMI DPIO driver vbios notes doc */
7312 /* PLL B needs special handling */
7314 vlv_pllb_recal_opamp(dev_priv, pipe);
7316 /* Set up Tx target for periodic Rcomp update */
7317 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7319 /* Disable target IRef on PLL */
7320 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7321 reg_val &= 0x00ffffff;
7322 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7324 /* Disable fast lock */
7325 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7327 /* Set idtafcrecal before PLL is enabled */
7328 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7329 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7330 mdiv |= ((bestn << DPIO_N_SHIFT));
7331 mdiv |= (1 << DPIO_K_SHIFT);
7334 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7335 * but we don't support that).
7336 * Note: don't use the DAC post divider as it seems unstable.
7338 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7339 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7341 mdiv |= DPIO_ENABLE_CALIBRATION;
7342 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7344 /* Set HBR and RBR LPF coefficients */
7345 if (pipe_config->port_clock == 162000 ||
7346 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
7347 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
7348 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7351 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7354 if (intel_crtc_has_dp_encoder(pipe_config)) {
7355 /* Use SSC source */
7357 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7360 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7362 } else { /* HDMI or VGA */
7363 /* Use bend source */
7365 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7368 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7372 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7373 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7374 if (intel_crtc_has_dp_encoder(pipe_config))
7375 coreclk |= 0x01000000;
7376 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7378 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7380 vlv_dpio_put(dev_priv);
7383 static void chv_prepare_pll(struct intel_crtc *crtc,
7384 const struct intel_crtc_state *pipe_config)
7386 struct drm_device *dev = crtc->base.dev;
7387 struct drm_i915_private *dev_priv = to_i915(dev);
7388 enum pipe pipe = crtc->pipe;
7389 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7390 u32 loopfilter, tribuf_calcntr;
7391 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7395 /* Enable Refclk and SSC */
7396 I915_WRITE(DPLL(pipe),
7397 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7399 /* No need to actually set up the DPLL with DSI */
7400 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7403 bestn = pipe_config->dpll.n;
7404 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7405 bestm1 = pipe_config->dpll.m1;
7406 bestm2 = pipe_config->dpll.m2 >> 22;
7407 bestp1 = pipe_config->dpll.p1;
7408 bestp2 = pipe_config->dpll.p2;
7409 vco = pipe_config->dpll.vco;
7413 vlv_dpio_get(dev_priv);
7415 /* p1 and p2 divider */
7416 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7417 5 << DPIO_CHV_S1_DIV_SHIFT |
7418 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7419 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7420 1 << DPIO_CHV_K_DIV_SHIFT);
7422 /* Feedback post-divider - m2 */
7423 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7425 /* Feedback refclk divider - n and m1 */
7426 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7427 DPIO_CHV_M1_DIV_BY_2 |
7428 1 << DPIO_CHV_N_DIV_SHIFT);
7430 /* M2 fraction division */
7431 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7433 /* M2 fraction division enable */
7434 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7435 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7436 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7438 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7439 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7441 /* Program digital lock detect threshold */
7442 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7443 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7444 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7445 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7447 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7448 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7451 if (vco == 5400000) {
7452 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7453 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7454 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7455 tribuf_calcntr = 0x9;
7456 } else if (vco <= 6200000) {
7457 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7458 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7459 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7460 tribuf_calcntr = 0x9;
7461 } else if (vco <= 6480000) {
7462 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7463 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7464 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7465 tribuf_calcntr = 0x8;
7467 /* Not supported. Apply the same limits as in the max case */
7468 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7469 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7470 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7473 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7475 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7476 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7477 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7478 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7481 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7482 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7485 vlv_dpio_put(dev_priv);
7489 * vlv_force_pll_on - forcibly enable just the PLL
7490 * @dev_priv: i915 private structure
7491 * @pipe: pipe PLL to enable
7492 * @dpll: PLL configuration
7494 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7495 * in cases where we need the PLL enabled even when @pipe is not going to
7498 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
7499 const struct dpll *dpll)
7501 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7502 struct intel_crtc_state *pipe_config;
7504 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7508 pipe_config->base.crtc = &crtc->base;
7509 pipe_config->pixel_multiplier = 1;
7510 pipe_config->dpll = *dpll;
7512 if (IS_CHERRYVIEW(dev_priv)) {
7513 chv_compute_dpll(crtc, pipe_config);
7514 chv_prepare_pll(crtc, pipe_config);
7515 chv_enable_pll(crtc, pipe_config);
7517 vlv_compute_dpll(crtc, pipe_config);
7518 vlv_prepare_pll(crtc, pipe_config);
7519 vlv_enable_pll(crtc, pipe_config);
7528 * vlv_force_pll_off - forcibly disable just the PLL
7529 * @dev_priv: i915 private structure
7530 * @pipe: pipe PLL to disable
7532 * Disable the PLL for @pipe. To be used in cases where we need
7533 * the PLL enabled even when @pipe is not going to be enabled.
7535 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
7537 if (IS_CHERRYVIEW(dev_priv))
7538 chv_disable_pll(dev_priv, pipe);
7540 vlv_disable_pll(dev_priv, pipe);
7543 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7544 struct intel_crtc_state *crtc_state,
7545 struct dpll *reduced_clock)
7547 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7549 struct dpll *clock = &crtc_state->dpll;
7551 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7553 dpll = DPLL_VGA_MODE_DIS;
7555 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7556 dpll |= DPLLB_MODE_LVDS;
7558 dpll |= DPLLB_MODE_DAC_SERIAL;
7560 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7561 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7562 dpll |= (crtc_state->pixel_multiplier - 1)
7563 << SDVO_MULTIPLIER_SHIFT_HIRES;
7566 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7567 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7568 dpll |= DPLL_SDVO_HIGH_SPEED;
7570 if (intel_crtc_has_dp_encoder(crtc_state))
7571 dpll |= DPLL_SDVO_HIGH_SPEED;
7573 /* compute bitmask from p1 value */
7574 if (IS_PINEVIEW(dev_priv))
7575 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7577 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7578 if (IS_G4X(dev_priv) && reduced_clock)
7579 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7581 switch (clock->p2) {
7583 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7586 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7589 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7592 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7595 if (INTEL_GEN(dev_priv) >= 4)
7596 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7598 if (crtc_state->sdvo_tv_clock)
7599 dpll |= PLL_REF_INPUT_TVCLKINBC;
7600 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7601 intel_panel_use_ssc(dev_priv))
7602 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7604 dpll |= PLL_REF_INPUT_DREFCLK;
7606 dpll |= DPLL_VCO_ENABLE;
7607 crtc_state->dpll_hw_state.dpll = dpll;
7609 if (INTEL_GEN(dev_priv) >= 4) {
7610 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7611 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7612 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7616 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7617 struct intel_crtc_state *crtc_state,
7618 struct dpll *reduced_clock)
7620 struct drm_device *dev = crtc->base.dev;
7621 struct drm_i915_private *dev_priv = to_i915(dev);
7623 struct dpll *clock = &crtc_state->dpll;
7625 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7627 dpll = DPLL_VGA_MODE_DIS;
7629 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7630 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7633 dpll |= PLL_P1_DIVIDE_BY_TWO;
7635 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7637 dpll |= PLL_P2_DIVIDE_BY_4;
7642 * "[Almador Errata}: For the correct operation of the muxed DVO pins
7643 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
7644 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
7645 * Enable) must be set to “1” in both the DPLL A Control Register
7646 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
7648 * For simplicity We simply keep both bits always enabled in
7649 * both DPLLS. The spec says we should disable the DVO 2X clock
7650 * when not needed, but this seems to work fine in practice.
7652 if (IS_I830(dev_priv) ||
7653 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7654 dpll |= DPLL_DVO_2X_MODE;
7656 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7657 intel_panel_use_ssc(dev_priv))
7658 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7660 dpll |= PLL_REF_INPUT_DREFCLK;
7662 dpll |= DPLL_VCO_ENABLE;
7663 crtc_state->dpll_hw_state.dpll = dpll;
7666 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
7668 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7669 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7670 enum pipe pipe = crtc->pipe;
7671 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
7672 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
7673 u32 crtc_vtotal, crtc_vblank_end;
7676 /* We need to be careful not to changed the adjusted mode, for otherwise
7677 * the hw state checker will get angry at the mismatch. */
7678 crtc_vtotal = adjusted_mode->crtc_vtotal;
7679 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7681 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7682 /* the chip adds 2 halflines automatically */
7684 crtc_vblank_end -= 1;
7686 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
7687 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7689 vsyncshift = adjusted_mode->crtc_hsync_start -
7690 adjusted_mode->crtc_htotal / 2;
7692 vsyncshift += adjusted_mode->crtc_htotal;
7695 if (INTEL_GEN(dev_priv) > 3)
7696 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7698 I915_WRITE(HTOTAL(cpu_transcoder),
7699 (adjusted_mode->crtc_hdisplay - 1) |
7700 ((adjusted_mode->crtc_htotal - 1) << 16));
7701 I915_WRITE(HBLANK(cpu_transcoder),
7702 (adjusted_mode->crtc_hblank_start - 1) |
7703 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7704 I915_WRITE(HSYNC(cpu_transcoder),
7705 (adjusted_mode->crtc_hsync_start - 1) |
7706 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7708 I915_WRITE(VTOTAL(cpu_transcoder),
7709 (adjusted_mode->crtc_vdisplay - 1) |
7710 ((crtc_vtotal - 1) << 16));
7711 I915_WRITE(VBLANK(cpu_transcoder),
7712 (adjusted_mode->crtc_vblank_start - 1) |
7713 ((crtc_vblank_end - 1) << 16));
7714 I915_WRITE(VSYNC(cpu_transcoder),
7715 (adjusted_mode->crtc_vsync_start - 1) |
7716 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7718 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7719 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7720 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7722 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7723 (pipe == PIPE_B || pipe == PIPE_C))
7724 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7728 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
7730 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7731 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7732 enum pipe pipe = crtc->pipe;
7734 /* pipesrc controls the size that is scaled from, which should
7735 * always be the user's requested size.
7737 I915_WRITE(PIPESRC(pipe),
7738 ((crtc_state->pipe_src_w - 1) << 16) |
7739 (crtc_state->pipe_src_h - 1));
7742 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7743 struct intel_crtc_state *pipe_config)
7745 struct drm_device *dev = crtc->base.dev;
7746 struct drm_i915_private *dev_priv = to_i915(dev);
7747 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7750 tmp = I915_READ(HTOTAL(cpu_transcoder));
7751 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7752 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7754 if (!transcoder_is_dsi(cpu_transcoder)) {
7755 tmp = I915_READ(HBLANK(cpu_transcoder));
7756 pipe_config->base.adjusted_mode.crtc_hblank_start =
7758 pipe_config->base.adjusted_mode.crtc_hblank_end =
7759 ((tmp >> 16) & 0xffff) + 1;
7761 tmp = I915_READ(HSYNC(cpu_transcoder));
7762 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7763 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7765 tmp = I915_READ(VTOTAL(cpu_transcoder));
7766 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7767 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7769 if (!transcoder_is_dsi(cpu_transcoder)) {
7770 tmp = I915_READ(VBLANK(cpu_transcoder));
7771 pipe_config->base.adjusted_mode.crtc_vblank_start =
7773 pipe_config->base.adjusted_mode.crtc_vblank_end =
7774 ((tmp >> 16) & 0xffff) + 1;
7776 tmp = I915_READ(VSYNC(cpu_transcoder));
7777 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7778 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7780 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7781 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7782 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7783 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7787 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7788 struct intel_crtc_state *pipe_config)
7790 struct drm_device *dev = crtc->base.dev;
7791 struct drm_i915_private *dev_priv = to_i915(dev);
7794 tmp = I915_READ(PIPESRC(crtc->pipe));
7795 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7796 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7798 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7799 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7802 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7803 struct intel_crtc_state *pipe_config)
7805 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7806 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7807 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7808 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7810 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7811 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7812 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7813 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7815 mode->flags = pipe_config->base.adjusted_mode.flags;
7816 mode->type = DRM_MODE_TYPE_DRIVER;
7818 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7820 mode->hsync = drm_mode_hsync(mode);
7821 mode->vrefresh = drm_mode_vrefresh(mode);
7822 drm_mode_set_name(mode);
7825 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
7827 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7828 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7833 /* we keep both pipes enabled on 830 */
7834 if (IS_I830(dev_priv))
7835 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
7837 if (crtc_state->double_wide)
7838 pipeconf |= PIPECONF_DOUBLE_WIDE;
7840 /* only g4x and later have fancy bpc/dither controls */
7841 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7842 IS_CHERRYVIEW(dev_priv)) {
7843 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7844 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
7845 pipeconf |= PIPECONF_DITHER_EN |
7846 PIPECONF_DITHER_TYPE_SP;
7848 switch (crtc_state->pipe_bpp) {
7850 pipeconf |= PIPECONF_6BPC;
7853 pipeconf |= PIPECONF_8BPC;
7856 pipeconf |= PIPECONF_10BPC;
7859 /* Case prevented by intel_choose_pipe_bpp_dither. */
7864 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7865 if (INTEL_GEN(dev_priv) < 4 ||
7866 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
7867 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7869 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7871 pipeconf |= PIPECONF_PROGRESSIVE;
7874 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7875 crtc_state->limited_color_range)
7876 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7878 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
7880 I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
7881 POSTING_READ(PIPECONF(crtc->pipe));
7884 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7885 struct intel_crtc_state *crtc_state)
7887 struct drm_device *dev = crtc->base.dev;
7888 struct drm_i915_private *dev_priv = to_i915(dev);
7889 const struct intel_limit *limit;
7892 memset(&crtc_state->dpll_hw_state, 0,
7893 sizeof(crtc_state->dpll_hw_state));
7895 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7896 if (intel_panel_use_ssc(dev_priv)) {
7897 refclk = dev_priv->vbt.lvds_ssc_freq;
7898 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7901 limit = &intel_limits_i8xx_lvds;
7902 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7903 limit = &intel_limits_i8xx_dvo;
7905 limit = &intel_limits_i8xx_dac;
7908 if (!crtc_state->clock_set &&
7909 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7910 refclk, NULL, &crtc_state->dpll)) {
7911 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7915 i8xx_compute_dpll(crtc, crtc_state, NULL);
7920 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7921 struct intel_crtc_state *crtc_state)
7923 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7924 const struct intel_limit *limit;
7927 memset(&crtc_state->dpll_hw_state, 0,
7928 sizeof(crtc_state->dpll_hw_state));
7930 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7931 if (intel_panel_use_ssc(dev_priv)) {
7932 refclk = dev_priv->vbt.lvds_ssc_freq;
7933 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7936 if (intel_is_dual_link_lvds(dev_priv))
7937 limit = &intel_limits_g4x_dual_channel_lvds;
7939 limit = &intel_limits_g4x_single_channel_lvds;
7940 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7941 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7942 limit = &intel_limits_g4x_hdmi;
7943 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7944 limit = &intel_limits_g4x_sdvo;
7946 /* The option is for other outputs */
7947 limit = &intel_limits_i9xx_sdvo;
7950 if (!crtc_state->clock_set &&
7951 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7952 refclk, NULL, &crtc_state->dpll)) {
7953 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7957 i9xx_compute_dpll(crtc, crtc_state, NULL);
7962 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7963 struct intel_crtc_state *crtc_state)
7965 struct drm_device *dev = crtc->base.dev;
7966 struct drm_i915_private *dev_priv = to_i915(dev);
7967 const struct intel_limit *limit;
7970 memset(&crtc_state->dpll_hw_state, 0,
7971 sizeof(crtc_state->dpll_hw_state));
7973 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7974 if (intel_panel_use_ssc(dev_priv)) {
7975 refclk = dev_priv->vbt.lvds_ssc_freq;
7976 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7979 limit = &intel_limits_pineview_lvds;
7981 limit = &intel_limits_pineview_sdvo;
7984 if (!crtc_state->clock_set &&
7985 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7986 refclk, NULL, &crtc_state->dpll)) {
7987 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7991 i9xx_compute_dpll(crtc, crtc_state, NULL);
7996 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7997 struct intel_crtc_state *crtc_state)
7999 struct drm_device *dev = crtc->base.dev;
8000 struct drm_i915_private *dev_priv = to_i915(dev);
8001 const struct intel_limit *limit;
8004 memset(&crtc_state->dpll_hw_state, 0,
8005 sizeof(crtc_state->dpll_hw_state));
8007 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8008 if (intel_panel_use_ssc(dev_priv)) {
8009 refclk = dev_priv->vbt.lvds_ssc_freq;
8010 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8013 limit = &intel_limits_i9xx_lvds;
8015 limit = &intel_limits_i9xx_sdvo;
8018 if (!crtc_state->clock_set &&
8019 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8020 refclk, NULL, &crtc_state->dpll)) {
8021 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8025 i9xx_compute_dpll(crtc, crtc_state, NULL);
8030 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8031 struct intel_crtc_state *crtc_state)
8033 int refclk = 100000;
8034 const struct intel_limit *limit = &intel_limits_chv;
8036 memset(&crtc_state->dpll_hw_state, 0,
8037 sizeof(crtc_state->dpll_hw_state));
8039 if (!crtc_state->clock_set &&
8040 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8041 refclk, NULL, &crtc_state->dpll)) {
8042 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8046 chv_compute_dpll(crtc, crtc_state);
8051 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8052 struct intel_crtc_state *crtc_state)
8054 int refclk = 100000;
8055 const struct intel_limit *limit = &intel_limits_vlv;
8057 memset(&crtc_state->dpll_hw_state, 0,
8058 sizeof(crtc_state->dpll_hw_state));
8060 if (!crtc_state->clock_set &&
8061 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8062 refclk, NULL, &crtc_state->dpll)) {
8063 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8067 vlv_compute_dpll(crtc, crtc_state);
8072 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
8074 if (IS_I830(dev_priv))
8077 return INTEL_GEN(dev_priv) >= 4 ||
8078 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
8081 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8082 struct intel_crtc_state *pipe_config)
8084 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8087 if (!i9xx_has_pfit(dev_priv))
8090 tmp = I915_READ(PFIT_CONTROL);
8091 if (!(tmp & PFIT_ENABLE))
8094 /* Check whether the pfit is attached to our pipe. */
8095 if (INTEL_GEN(dev_priv) < 4) {
8096 if (crtc->pipe != PIPE_B)
8099 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8103 pipe_config->gmch_pfit.control = tmp;
8104 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8107 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8108 struct intel_crtc_state *pipe_config)
8110 struct drm_device *dev = crtc->base.dev;
8111 struct drm_i915_private *dev_priv = to_i915(dev);
8112 int pipe = pipe_config->cpu_transcoder;
8115 int refclk = 100000;
8117 /* In case of DSI, DPLL will not be used */
8118 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8121 vlv_dpio_get(dev_priv);
8122 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8123 vlv_dpio_put(dev_priv);
8125 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8126 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8127 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8128 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8129 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8131 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8135 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8136 struct intel_initial_plane_config *plane_config)
8138 struct drm_device *dev = crtc->base.dev;
8139 struct drm_i915_private *dev_priv = to_i915(dev);
8140 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8141 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8143 u32 val, base, offset;
8144 int fourcc, pixel_format;
8145 unsigned int aligned_height;
8146 struct drm_framebuffer *fb;
8147 struct intel_framebuffer *intel_fb;
8149 if (!plane->get_hw_state(plane, &pipe))
8152 WARN_ON(pipe != crtc->pipe);
8154 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8156 DRM_DEBUG_KMS("failed to alloc fb\n");
8160 fb = &intel_fb->base;
8164 val = I915_READ(DSPCNTR(i9xx_plane));
8166 if (INTEL_GEN(dev_priv) >= 4) {
8167 if (val & DISPPLANE_TILED) {
8168 plane_config->tiling = I915_TILING_X;
8169 fb->modifier = I915_FORMAT_MOD_X_TILED;
8172 if (val & DISPPLANE_ROTATE_180)
8173 plane_config->rotation = DRM_MODE_ROTATE_180;
8176 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8177 val & DISPPLANE_MIRROR)
8178 plane_config->rotation |= DRM_MODE_REFLECT_X;
8180 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8181 fourcc = i9xx_format_to_fourcc(pixel_format);
8182 fb->format = drm_format_info(fourcc);
8184 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8185 offset = I915_READ(DSPOFFSET(i9xx_plane));
8186 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8187 } else if (INTEL_GEN(dev_priv) >= 4) {
8188 if (plane_config->tiling)
8189 offset = I915_READ(DSPTILEOFF(i9xx_plane));
8191 offset = I915_READ(DSPLINOFF(i9xx_plane));
8192 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8194 base = I915_READ(DSPADDR(i9xx_plane));
8196 plane_config->base = base;
8198 val = I915_READ(PIPESRC(pipe));
8199 fb->width = ((val >> 16) & 0xfff) + 1;
8200 fb->height = ((val >> 0) & 0xfff) + 1;
8202 val = I915_READ(DSPSTRIDE(i9xx_plane));
8203 fb->pitches[0] = val & 0xffffffc0;
8205 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8207 plane_config->size = fb->pitches[0] * aligned_height;
8209 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8210 crtc->base.name, plane->base.name, fb->width, fb->height,
8211 fb->format->cpp[0] * 8, base, fb->pitches[0],
8212 plane_config->size);
8214 plane_config->fb = intel_fb;
8217 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8218 struct intel_crtc_state *pipe_config)
8220 struct drm_device *dev = crtc->base.dev;
8221 struct drm_i915_private *dev_priv = to_i915(dev);
8222 int pipe = pipe_config->cpu_transcoder;
8223 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8225 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8226 int refclk = 100000;
8228 /* In case of DSI, DPLL will not be used */
8229 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8232 vlv_dpio_get(dev_priv);
8233 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8234 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8235 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8236 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8237 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8238 vlv_dpio_put(dev_priv);
8240 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8241 clock.m2 = (pll_dw0 & 0xff) << 22;
8242 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8243 clock.m2 |= pll_dw2 & 0x3fffff;
8244 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8245 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8246 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8248 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8251 static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
8252 struct intel_crtc_state *pipe_config)
8254 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8255 enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
8257 pipe_config->lspcon_downsampling = false;
8259 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8260 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
8262 if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8263 bool ycbcr420_enabled = tmp & PIPEMISC_YUV420_ENABLE;
8264 bool blend = tmp & PIPEMISC_YUV420_MODE_FULL_BLEND;
8266 if (ycbcr420_enabled) {
8267 /* We support 4:2:0 in full blend mode only */
8269 output = INTEL_OUTPUT_FORMAT_INVALID;
8270 else if (!(IS_GEMINILAKE(dev_priv) ||
8271 INTEL_GEN(dev_priv) >= 10))
8272 output = INTEL_OUTPUT_FORMAT_INVALID;
8274 output = INTEL_OUTPUT_FORMAT_YCBCR420;
8277 * Currently there is no interface defined to
8278 * check user preference between RGB/YCBCR444
8279 * or YCBCR420. So the only possible case for
8280 * YCBCR444 usage is driving YCBCR420 output
8281 * with LSPCON, when pipe is configured for
8282 * YCBCR444 output and LSPCON takes care of
8285 pipe_config->lspcon_downsampling = true;
8286 output = INTEL_OUTPUT_FORMAT_YCBCR444;
8291 pipe_config->output_format = output;
8294 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8296 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8297 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8298 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8299 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8302 tmp = I915_READ(DSPCNTR(i9xx_plane));
8304 if (tmp & DISPPLANE_GAMMA_ENABLE)
8305 crtc_state->gamma_enable = true;
8307 if (!HAS_GMCH(dev_priv) &&
8308 tmp & DISPPLANE_PIPE_CSC_ENABLE)
8309 crtc_state->csc_enable = true;
8312 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8313 struct intel_crtc_state *pipe_config)
8315 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8316 enum intel_display_power_domain power_domain;
8317 intel_wakeref_t wakeref;
8321 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8322 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8326 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8327 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8328 pipe_config->shared_dpll = NULL;
8332 tmp = I915_READ(PIPECONF(crtc->pipe));
8333 if (!(tmp & PIPECONF_ENABLE))
8336 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8337 IS_CHERRYVIEW(dev_priv)) {
8338 switch (tmp & PIPECONF_BPC_MASK) {
8340 pipe_config->pipe_bpp = 18;
8343 pipe_config->pipe_bpp = 24;
8345 case PIPECONF_10BPC:
8346 pipe_config->pipe_bpp = 30;
8353 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8354 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8355 pipe_config->limited_color_range = true;
8357 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
8358 PIPECONF_GAMMA_MODE_SHIFT;
8360 if (IS_CHERRYVIEW(dev_priv))
8361 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
8363 i9xx_get_pipe_color_config(pipe_config);
8365 if (INTEL_GEN(dev_priv) < 4)
8366 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8368 intel_get_pipe_timings(crtc, pipe_config);
8369 intel_get_pipe_src_size(crtc, pipe_config);
8371 i9xx_get_pfit_config(crtc, pipe_config);
8373 if (INTEL_GEN(dev_priv) >= 4) {
8374 /* No way to read it out on pipes B and C */
8375 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8376 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8378 tmp = I915_READ(DPLL_MD(crtc->pipe));
8379 pipe_config->pixel_multiplier =
8380 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8381 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8382 pipe_config->dpll_hw_state.dpll_md = tmp;
8383 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8384 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8385 tmp = I915_READ(DPLL(crtc->pipe));
8386 pipe_config->pixel_multiplier =
8387 ((tmp & SDVO_MULTIPLIER_MASK)
8388 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8390 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8391 * port and will be fixed up in the encoder->get_config
8393 pipe_config->pixel_multiplier = 1;
8395 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8396 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8397 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8398 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8400 /* Mask out read-only status bits. */
8401 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8402 DPLL_PORTC_READY_MASK |
8403 DPLL_PORTB_READY_MASK);
8406 if (IS_CHERRYVIEW(dev_priv))
8407 chv_crtc_clock_get(crtc, pipe_config);
8408 else if (IS_VALLEYVIEW(dev_priv))
8409 vlv_crtc_clock_get(crtc, pipe_config);
8411 i9xx_crtc_clock_get(crtc, pipe_config);
8414 * Normally the dotclock is filled in by the encoder .get_config()
8415 * but in case the pipe is enabled w/o any ports we need a sane
8418 pipe_config->base.adjusted_mode.crtc_clock =
8419 pipe_config->port_clock / pipe_config->pixel_multiplier;
8424 intel_display_power_put(dev_priv, power_domain, wakeref);
8429 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
8431 struct intel_encoder *encoder;
8434 bool has_lvds = false;
8435 bool has_cpu_edp = false;
8436 bool has_panel = false;
8437 bool has_ck505 = false;
8438 bool can_ssc = false;
8439 bool using_ssc_source = false;
8441 /* We need to take the global config into account */
8442 for_each_intel_encoder(&dev_priv->drm, encoder) {
8443 switch (encoder->type) {
8444 case INTEL_OUTPUT_LVDS:
8448 case INTEL_OUTPUT_EDP:
8450 if (encoder->port == PORT_A)
8458 if (HAS_PCH_IBX(dev_priv)) {
8459 has_ck505 = dev_priv->vbt.display_clock_mode;
8460 can_ssc = has_ck505;
8466 /* Check if any DPLLs are using the SSC source */
8467 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8468 u32 temp = I915_READ(PCH_DPLL(i));
8470 if (!(temp & DPLL_VCO_ENABLE))
8473 if ((temp & PLL_REF_INPUT_MASK) ==
8474 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8475 using_ssc_source = true;
8480 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8481 has_panel, has_lvds, has_ck505, using_ssc_source);
8483 /* Ironlake: try to setup display ref clock before DPLL
8484 * enabling. This is only under driver's control after
8485 * PCH B stepping, previous chipset stepping should be
8486 * ignoring this setting.
8488 val = I915_READ(PCH_DREF_CONTROL);
8490 /* As we must carefully and slowly disable/enable each source in turn,
8491 * compute the final state we want first and check if we need to
8492 * make any changes at all.
8495 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8497 final |= DREF_NONSPREAD_CK505_ENABLE;
8499 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8501 final &= ~DREF_SSC_SOURCE_MASK;
8502 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8503 final &= ~DREF_SSC1_ENABLE;
8506 final |= DREF_SSC_SOURCE_ENABLE;
8508 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8509 final |= DREF_SSC1_ENABLE;
8512 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8513 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8515 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8517 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8518 } else if (using_ssc_source) {
8519 final |= DREF_SSC_SOURCE_ENABLE;
8520 final |= DREF_SSC1_ENABLE;
8526 /* Always enable nonspread source */
8527 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8530 val |= DREF_NONSPREAD_CK505_ENABLE;
8532 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8535 val &= ~DREF_SSC_SOURCE_MASK;
8536 val |= DREF_SSC_SOURCE_ENABLE;
8538 /* SSC must be turned on before enabling the CPU output */
8539 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8540 DRM_DEBUG_KMS("Using SSC on panel\n");
8541 val |= DREF_SSC1_ENABLE;
8543 val &= ~DREF_SSC1_ENABLE;
8545 /* Get SSC going before enabling the outputs */
8546 I915_WRITE(PCH_DREF_CONTROL, val);
8547 POSTING_READ(PCH_DREF_CONTROL);
8550 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8552 /* Enable CPU source on CPU attached eDP */
8554 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8555 DRM_DEBUG_KMS("Using SSC on eDP\n");
8556 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8558 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8560 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8562 I915_WRITE(PCH_DREF_CONTROL, val);
8563 POSTING_READ(PCH_DREF_CONTROL);
8566 DRM_DEBUG_KMS("Disabling CPU source output\n");
8568 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8570 /* Turn off CPU output */
8571 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8573 I915_WRITE(PCH_DREF_CONTROL, val);
8574 POSTING_READ(PCH_DREF_CONTROL);
8577 if (!using_ssc_source) {
8578 DRM_DEBUG_KMS("Disabling SSC source\n");
8580 /* Turn off the SSC source */
8581 val &= ~DREF_SSC_SOURCE_MASK;
8582 val |= DREF_SSC_SOURCE_DISABLE;
8585 val &= ~DREF_SSC1_ENABLE;
8587 I915_WRITE(PCH_DREF_CONTROL, val);
8588 POSTING_READ(PCH_DREF_CONTROL);
8593 BUG_ON(val != final);
8596 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8600 tmp = I915_READ(SOUTH_CHICKEN2);
8601 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8602 I915_WRITE(SOUTH_CHICKEN2, tmp);
8604 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8605 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8606 DRM_ERROR("FDI mPHY reset assert timeout\n");
8608 tmp = I915_READ(SOUTH_CHICKEN2);
8609 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8610 I915_WRITE(SOUTH_CHICKEN2, tmp);
8612 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8613 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8614 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8617 /* WaMPhyProgramming:hsw */
8618 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8622 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8623 tmp &= ~(0xFF << 24);
8624 tmp |= (0x12 << 24);
8625 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8627 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8629 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8631 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8633 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8635 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8636 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8637 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8639 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8640 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8641 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8643 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8646 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8648 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8651 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8653 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8656 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8658 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8661 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8663 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8664 tmp &= ~(0xFF << 16);
8665 tmp |= (0x1C << 16);
8666 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8668 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8669 tmp &= ~(0xFF << 16);
8670 tmp |= (0x1C << 16);
8671 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8673 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8675 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8677 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8679 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8681 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8682 tmp &= ~(0xF << 28);
8684 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8686 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8687 tmp &= ~(0xF << 28);
8689 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8692 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8693 * Programming" based on the parameters passed:
8694 * - Sequence to enable CLKOUT_DP
8695 * - Sequence to enable CLKOUT_DP without spread
8696 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8698 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
8699 bool with_spread, bool with_fdi)
8703 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8705 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
8706 with_fdi, "LP PCH doesn't have FDI\n"))
8709 mutex_lock(&dev_priv->sb_lock);
8711 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8712 tmp &= ~SBI_SSCCTL_DISABLE;
8713 tmp |= SBI_SSCCTL_PATHALT;
8714 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8719 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8720 tmp &= ~SBI_SSCCTL_PATHALT;
8721 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8724 lpt_reset_fdi_mphy(dev_priv);
8725 lpt_program_fdi_mphy(dev_priv);
8729 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8730 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8731 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8732 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8734 mutex_unlock(&dev_priv->sb_lock);
8737 /* Sequence to disable CLKOUT_DP */
8738 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8742 mutex_lock(&dev_priv->sb_lock);
8744 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8745 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8746 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8747 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8749 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8750 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8751 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8752 tmp |= SBI_SSCCTL_PATHALT;
8753 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8756 tmp |= SBI_SSCCTL_DISABLE;
8757 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8760 mutex_unlock(&dev_priv->sb_lock);
8763 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8765 static const u16 sscdivintphase[] = {
8766 [BEND_IDX( 50)] = 0x3B23,
8767 [BEND_IDX( 45)] = 0x3B23,
8768 [BEND_IDX( 40)] = 0x3C23,
8769 [BEND_IDX( 35)] = 0x3C23,
8770 [BEND_IDX( 30)] = 0x3D23,
8771 [BEND_IDX( 25)] = 0x3D23,
8772 [BEND_IDX( 20)] = 0x3E23,
8773 [BEND_IDX( 15)] = 0x3E23,
8774 [BEND_IDX( 10)] = 0x3F23,
8775 [BEND_IDX( 5)] = 0x3F23,
8776 [BEND_IDX( 0)] = 0x0025,
8777 [BEND_IDX( -5)] = 0x0025,
8778 [BEND_IDX(-10)] = 0x0125,
8779 [BEND_IDX(-15)] = 0x0125,
8780 [BEND_IDX(-20)] = 0x0225,
8781 [BEND_IDX(-25)] = 0x0225,
8782 [BEND_IDX(-30)] = 0x0325,
8783 [BEND_IDX(-35)] = 0x0325,
8784 [BEND_IDX(-40)] = 0x0425,
8785 [BEND_IDX(-45)] = 0x0425,
8786 [BEND_IDX(-50)] = 0x0525,
8791 * steps -50 to 50 inclusive, in steps of 5
8792 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8793 * change in clock period = -(steps / 10) * 5.787 ps
8795 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8798 int idx = BEND_IDX(steps);
8800 if (WARN_ON(steps % 5 != 0))
8803 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8806 mutex_lock(&dev_priv->sb_lock);
8808 if (steps % 10 != 0)
8812 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8814 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8816 tmp |= sscdivintphase[idx];
8817 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8819 mutex_unlock(&dev_priv->sb_lock);
8824 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8826 struct intel_encoder *encoder;
8827 bool has_vga = false;
8829 for_each_intel_encoder(&dev_priv->drm, encoder) {
8830 switch (encoder->type) {
8831 case INTEL_OUTPUT_ANALOG:
8840 lpt_bend_clkout_dp(dev_priv, 0);
8841 lpt_enable_clkout_dp(dev_priv, true, true);
8843 lpt_disable_clkout_dp(dev_priv);
8848 * Initialize reference clocks when the driver loads
8850 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8852 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8853 ironlake_init_pch_refclk(dev_priv);
8854 else if (HAS_PCH_LPT(dev_priv))
8855 lpt_init_pch_refclk(dev_priv);
8858 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
8860 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8861 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8862 enum pipe pipe = crtc->pipe;
8867 switch (crtc_state->pipe_bpp) {
8869 val |= PIPECONF_6BPC;
8872 val |= PIPECONF_8BPC;
8875 val |= PIPECONF_10BPC;
8878 val |= PIPECONF_12BPC;
8881 /* Case prevented by intel_choose_pipe_bpp_dither. */
8885 if (crtc_state->dither)
8886 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8888 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8889 val |= PIPECONF_INTERLACED_ILK;
8891 val |= PIPECONF_PROGRESSIVE;
8893 if (crtc_state->limited_color_range)
8894 val |= PIPECONF_COLOR_RANGE_SELECT;
8896 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8898 I915_WRITE(PIPECONF(pipe), val);
8899 POSTING_READ(PIPECONF(pipe));
8902 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
8904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8905 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8906 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8909 if (IS_HASWELL(dev_priv) && crtc_state->dither)
8910 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8912 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8913 val |= PIPECONF_INTERLACED_ILK;
8915 val |= PIPECONF_PROGRESSIVE;
8917 I915_WRITE(PIPECONF(cpu_transcoder), val);
8918 POSTING_READ(PIPECONF(cpu_transcoder));
8921 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
8923 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8924 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8927 switch (crtc_state->pipe_bpp) {
8929 val |= PIPEMISC_DITHER_6_BPC;
8932 val |= PIPEMISC_DITHER_8_BPC;
8935 val |= PIPEMISC_DITHER_10_BPC;
8938 val |= PIPEMISC_DITHER_12_BPC;
8941 MISSING_CASE(crtc_state->pipe_bpp);
8945 if (crtc_state->dither)
8946 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8948 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8949 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
8950 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
8952 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
8953 val |= PIPEMISC_YUV420_ENABLE |
8954 PIPEMISC_YUV420_MODE_FULL_BLEND;
8956 if (INTEL_GEN(dev_priv) >= 11 &&
8957 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
8958 BIT(PLANE_CURSOR))) == 0)
8959 val |= PIPEMISC_HDR_MODE_PRECISION;
8961 I915_WRITE(PIPEMISC(crtc->pipe), val);
8964 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
8966 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8969 tmp = I915_READ(PIPEMISC(crtc->pipe));
8971 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
8972 case PIPEMISC_DITHER_6_BPC:
8974 case PIPEMISC_DITHER_8_BPC:
8976 case PIPEMISC_DITHER_10_BPC:
8978 case PIPEMISC_DITHER_12_BPC:
8986 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8989 * Account for spread spectrum to avoid
8990 * oversubscribing the link. Max center spread
8991 * is 2.5%; use 5% for safety's sake.
8993 u32 bps = target_clock * bpp * 21 / 20;
8994 return DIV_ROUND_UP(bps, link_bw * 8);
8997 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8999 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9002 static void ironlake_compute_dpll(struct intel_crtc *crtc,
9003 struct intel_crtc_state *crtc_state,
9004 struct dpll *reduced_clock)
9006 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9010 /* Enable autotuning of the PLL clock (if permissible) */
9012 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9013 if ((intel_panel_use_ssc(dev_priv) &&
9014 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9015 (HAS_PCH_IBX(dev_priv) &&
9016 intel_is_dual_link_lvds(dev_priv)))
9018 } else if (crtc_state->sdvo_tv_clock) {
9022 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9024 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9027 if (reduced_clock) {
9028 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9030 if (reduced_clock->m < factor * reduced_clock->n)
9038 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9039 dpll |= DPLLB_MODE_LVDS;
9041 dpll |= DPLLB_MODE_DAC_SERIAL;
9043 dpll |= (crtc_state->pixel_multiplier - 1)
9044 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9046 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9047 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9048 dpll |= DPLL_SDVO_HIGH_SPEED;
9050 if (intel_crtc_has_dp_encoder(crtc_state))
9051 dpll |= DPLL_SDVO_HIGH_SPEED;
9054 * The high speed IO clock is only really required for
9055 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9056 * possible to share the DPLL between CRT and HDMI. Enabling
9057 * the clock needlessly does no real harm, except use up a
9058 * bit of power potentially.
9060 * We'll limit this to IVB with 3 pipes, since it has only two
9061 * DPLLs and so DPLL sharing is the only way to get three pipes
9062 * driving PCH ports at the same time. On SNB we could do this,
9063 * and potentially avoid enabling the second DPLL, but it's not
9064 * clear if it''s a win or loss power wise. No point in doing
9065 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9067 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9068 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9069 dpll |= DPLL_SDVO_HIGH_SPEED;
9071 /* compute bitmask from p1 value */
9072 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9074 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9076 switch (crtc_state->dpll.p2) {
9078 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9081 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9084 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9087 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9091 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9092 intel_panel_use_ssc(dev_priv))
9093 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9095 dpll |= PLL_REF_INPUT_DREFCLK;
9097 dpll |= DPLL_VCO_ENABLE;
9099 crtc_state->dpll_hw_state.dpll = dpll;
9100 crtc_state->dpll_hw_state.fp0 = fp;
9101 crtc_state->dpll_hw_state.fp1 = fp2;
9104 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9105 struct intel_crtc_state *crtc_state)
9107 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9108 const struct intel_limit *limit;
9109 int refclk = 120000;
9111 memset(&crtc_state->dpll_hw_state, 0,
9112 sizeof(crtc_state->dpll_hw_state));
9114 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9115 if (!crtc_state->has_pch_encoder)
9118 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9119 if (intel_panel_use_ssc(dev_priv)) {
9120 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9121 dev_priv->vbt.lvds_ssc_freq);
9122 refclk = dev_priv->vbt.lvds_ssc_freq;
9125 if (intel_is_dual_link_lvds(dev_priv)) {
9126 if (refclk == 100000)
9127 limit = &intel_limits_ironlake_dual_lvds_100m;
9129 limit = &intel_limits_ironlake_dual_lvds;
9131 if (refclk == 100000)
9132 limit = &intel_limits_ironlake_single_lvds_100m;
9134 limit = &intel_limits_ironlake_single_lvds;
9137 limit = &intel_limits_ironlake_dac;
9140 if (!crtc_state->clock_set &&
9141 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9142 refclk, NULL, &crtc_state->dpll)) {
9143 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9147 ironlake_compute_dpll(crtc, crtc_state, NULL);
9149 if (!intel_get_shared_dpll(crtc_state, NULL)) {
9150 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9151 pipe_name(crtc->pipe));
9158 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9159 struct intel_link_m_n *m_n)
9161 struct drm_device *dev = crtc->base.dev;
9162 struct drm_i915_private *dev_priv = to_i915(dev);
9163 enum pipe pipe = crtc->pipe;
9165 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9166 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9167 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9169 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9170 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9171 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9174 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9175 enum transcoder transcoder,
9176 struct intel_link_m_n *m_n,
9177 struct intel_link_m_n *m2_n2)
9179 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9180 enum pipe pipe = crtc->pipe;
9182 if (INTEL_GEN(dev_priv) >= 5) {
9183 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9184 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9185 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9187 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9188 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9189 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9191 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9192 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9193 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9194 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9196 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9197 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9198 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9201 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9202 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9203 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9205 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9206 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9207 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9211 void intel_dp_get_m_n(struct intel_crtc *crtc,
9212 struct intel_crtc_state *pipe_config)
9214 if (pipe_config->has_pch_encoder)
9215 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9217 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9218 &pipe_config->dp_m_n,
9219 &pipe_config->dp_m2_n2);
9222 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9223 struct intel_crtc_state *pipe_config)
9225 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9226 &pipe_config->fdi_m_n, NULL);
9229 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9230 struct intel_crtc_state *pipe_config)
9232 struct drm_device *dev = crtc->base.dev;
9233 struct drm_i915_private *dev_priv = to_i915(dev);
9234 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9239 /* find scaler attached to this pipe */
9240 for (i = 0; i < crtc->num_scalers; i++) {
9241 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9242 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9244 pipe_config->pch_pfit.enabled = true;
9245 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9246 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9247 scaler_state->scalers[i].in_use = true;
9252 scaler_state->scaler_id = id;
9254 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9256 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9261 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9262 struct intel_initial_plane_config *plane_config)
9264 struct drm_device *dev = crtc->base.dev;
9265 struct drm_i915_private *dev_priv = to_i915(dev);
9266 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9267 enum plane_id plane_id = plane->id;
9269 u32 val, base, offset, stride_mult, tiling, alpha;
9270 int fourcc, pixel_format;
9271 unsigned int aligned_height;
9272 struct drm_framebuffer *fb;
9273 struct intel_framebuffer *intel_fb;
9275 if (!plane->get_hw_state(plane, &pipe))
9278 WARN_ON(pipe != crtc->pipe);
9280 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9282 DRM_DEBUG_KMS("failed to alloc fb\n");
9286 fb = &intel_fb->base;
9290 val = I915_READ(PLANE_CTL(pipe, plane_id));
9292 if (INTEL_GEN(dev_priv) >= 11)
9293 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
9295 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9297 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
9298 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
9299 alpha &= PLANE_COLOR_ALPHA_MASK;
9301 alpha = val & PLANE_CTL_ALPHA_MASK;
9304 fourcc = skl_format_to_fourcc(pixel_format,
9305 val & PLANE_CTL_ORDER_RGBX, alpha);
9306 fb->format = drm_format_info(fourcc);
9308 tiling = val & PLANE_CTL_TILED_MASK;
9310 case PLANE_CTL_TILED_LINEAR:
9311 fb->modifier = DRM_FORMAT_MOD_LINEAR;
9313 case PLANE_CTL_TILED_X:
9314 plane_config->tiling = I915_TILING_X;
9315 fb->modifier = I915_FORMAT_MOD_X_TILED;
9317 case PLANE_CTL_TILED_Y:
9318 plane_config->tiling = I915_TILING_Y;
9319 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9320 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
9322 fb->modifier = I915_FORMAT_MOD_Y_TILED;
9324 case PLANE_CTL_TILED_YF:
9325 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9326 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
9328 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9331 MISSING_CASE(tiling);
9336 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
9337 * while i915 HW rotation is clockwise, thats why this swapping.
9339 switch (val & PLANE_CTL_ROTATE_MASK) {
9340 case PLANE_CTL_ROTATE_0:
9341 plane_config->rotation = DRM_MODE_ROTATE_0;
9343 case PLANE_CTL_ROTATE_90:
9344 plane_config->rotation = DRM_MODE_ROTATE_270;
9346 case PLANE_CTL_ROTATE_180:
9347 plane_config->rotation = DRM_MODE_ROTATE_180;
9349 case PLANE_CTL_ROTATE_270:
9350 plane_config->rotation = DRM_MODE_ROTATE_90;
9354 if (INTEL_GEN(dev_priv) >= 10 &&
9355 val & PLANE_CTL_FLIP_HORIZONTAL)
9356 plane_config->rotation |= DRM_MODE_REFLECT_X;
9358 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
9359 plane_config->base = base;
9361 offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
9363 val = I915_READ(PLANE_SIZE(pipe, plane_id));
9364 fb->height = ((val >> 16) & 0xfff) + 1;
9365 fb->width = ((val >> 0) & 0x1fff) + 1;
9367 val = I915_READ(PLANE_STRIDE(pipe, plane_id));
9368 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
9369 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9371 aligned_height = intel_fb_align_height(fb, 0, fb->height);
9373 plane_config->size = fb->pitches[0] * aligned_height;
9375 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9376 crtc->base.name, plane->base.name, fb->width, fb->height,
9377 fb->format->cpp[0] * 8, base, fb->pitches[0],
9378 plane_config->size);
9380 plane_config->fb = intel_fb;
9387 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9388 struct intel_crtc_state *pipe_config)
9390 struct drm_device *dev = crtc->base.dev;
9391 struct drm_i915_private *dev_priv = to_i915(dev);
9394 tmp = I915_READ(PF_CTL(crtc->pipe));
9396 if (tmp & PF_ENABLE) {
9397 pipe_config->pch_pfit.enabled = true;
9398 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9399 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9401 /* We currently do not free assignements of panel fitters on
9402 * ivb/hsw (since we don't use the higher upscaling modes which
9403 * differentiates them) so just WARN about this case for now. */
9404 if (IS_GEN(dev_priv, 7)) {
9405 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9406 PF_PIPE_SEL_IVB(crtc->pipe));
9411 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9412 struct intel_crtc_state *pipe_config)
9414 struct drm_device *dev = crtc->base.dev;
9415 struct drm_i915_private *dev_priv = to_i915(dev);
9416 enum intel_display_power_domain power_domain;
9417 intel_wakeref_t wakeref;
9421 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9422 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9426 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9427 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9428 pipe_config->shared_dpll = NULL;
9431 tmp = I915_READ(PIPECONF(crtc->pipe));
9432 if (!(tmp & PIPECONF_ENABLE))
9435 switch (tmp & PIPECONF_BPC_MASK) {
9437 pipe_config->pipe_bpp = 18;
9440 pipe_config->pipe_bpp = 24;
9442 case PIPECONF_10BPC:
9443 pipe_config->pipe_bpp = 30;
9445 case PIPECONF_12BPC:
9446 pipe_config->pipe_bpp = 36;
9452 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9453 pipe_config->limited_color_range = true;
9455 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
9456 PIPECONF_GAMMA_MODE_SHIFT;
9458 pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
9460 i9xx_get_pipe_color_config(pipe_config);
9462 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9463 struct intel_shared_dpll *pll;
9464 enum intel_dpll_id pll_id;
9466 pipe_config->has_pch_encoder = true;
9468 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9469 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9470 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9472 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9474 if (HAS_PCH_IBX(dev_priv)) {
9476 * The pipe->pch transcoder and pch transcoder->pll
9479 pll_id = (enum intel_dpll_id) crtc->pipe;
9481 tmp = I915_READ(PCH_DPLL_SEL);
9482 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9483 pll_id = DPLL_ID_PCH_PLL_B;
9485 pll_id= DPLL_ID_PCH_PLL_A;
9488 pipe_config->shared_dpll =
9489 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9490 pll = pipe_config->shared_dpll;
9492 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9493 &pipe_config->dpll_hw_state));
9495 tmp = pipe_config->dpll_hw_state.dpll;
9496 pipe_config->pixel_multiplier =
9497 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9498 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9500 ironlake_pch_clock_get(crtc, pipe_config);
9502 pipe_config->pixel_multiplier = 1;
9505 intel_get_pipe_timings(crtc, pipe_config);
9506 intel_get_pipe_src_size(crtc, pipe_config);
9508 ironlake_get_pfit_config(crtc, pipe_config);
9513 intel_display_power_put(dev_priv, power_domain, wakeref);
9517 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9518 struct intel_crtc_state *crtc_state)
9520 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9521 struct intel_atomic_state *state =
9522 to_intel_atomic_state(crtc_state->base.state);
9524 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
9525 INTEL_GEN(dev_priv) >= 11) {
9526 struct intel_encoder *encoder =
9527 intel_get_crtc_new_encoder(state, crtc_state);
9529 if (!intel_get_shared_dpll(crtc_state, encoder)) {
9530 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9531 pipe_name(crtc->pipe));
9539 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9541 struct intel_crtc_state *pipe_config)
9543 enum intel_dpll_id id;
9546 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9547 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9549 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9552 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9555 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
9557 struct intel_crtc_state *pipe_config)
9559 enum intel_dpll_id id;
9562 /* TODO: TBT pll not implemented. */
9563 if (intel_port_is_combophy(dev_priv, port)) {
9564 temp = I915_READ(DPCLKA_CFGCR0_ICL) &
9565 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9566 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9567 } else if (intel_port_is_tc(dev_priv, port)) {
9568 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
9570 WARN(1, "Invalid port %x\n", port);
9574 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9577 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9579 struct intel_crtc_state *pipe_config)
9581 enum intel_dpll_id id;
9585 id = DPLL_ID_SKL_DPLL0;
9588 id = DPLL_ID_SKL_DPLL1;
9591 id = DPLL_ID_SKL_DPLL2;
9594 DRM_ERROR("Incorrect port type\n");
9598 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9601 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9603 struct intel_crtc_state *pipe_config)
9605 enum intel_dpll_id id;
9608 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9609 id = temp >> (port * 3 + 1);
9611 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9614 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9617 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9619 struct intel_crtc_state *pipe_config)
9621 enum intel_dpll_id id;
9622 u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9624 switch (ddi_pll_sel) {
9625 case PORT_CLK_SEL_WRPLL1:
9626 id = DPLL_ID_WRPLL1;
9628 case PORT_CLK_SEL_WRPLL2:
9629 id = DPLL_ID_WRPLL2;
9631 case PORT_CLK_SEL_SPLL:
9634 case PORT_CLK_SEL_LCPLL_810:
9635 id = DPLL_ID_LCPLL_810;
9637 case PORT_CLK_SEL_LCPLL_1350:
9638 id = DPLL_ID_LCPLL_1350;
9640 case PORT_CLK_SEL_LCPLL_2700:
9641 id = DPLL_ID_LCPLL_2700;
9644 MISSING_CASE(ddi_pll_sel);
9646 case PORT_CLK_SEL_NONE:
9650 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9653 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9654 struct intel_crtc_state *pipe_config,
9655 u64 *power_domain_mask,
9656 intel_wakeref_t *wakerefs)
9658 struct drm_device *dev = crtc->base.dev;
9659 struct drm_i915_private *dev_priv = to_i915(dev);
9660 enum intel_display_power_domain power_domain;
9661 unsigned long panel_transcoder_mask = 0;
9662 unsigned long enabled_panel_transcoders = 0;
9663 enum transcoder panel_transcoder;
9667 if (INTEL_GEN(dev_priv) >= 11)
9668 panel_transcoder_mask |=
9669 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
9671 if (HAS_TRANSCODER_EDP(dev_priv))
9672 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
9675 * The pipe->transcoder mapping is fixed with the exception of the eDP
9676 * and DSI transcoders handled below.
9678 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9681 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9682 * consistency and less surprising code; it's in always on power).
9684 for_each_set_bit(panel_transcoder,
9685 &panel_transcoder_mask,
9686 ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
9687 bool force_thru = false;
9688 enum pipe trans_pipe;
9690 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
9691 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
9695 * Log all enabled ones, only use the first one.
9697 * FIXME: This won't work for two separate DSI displays.
9699 enabled_panel_transcoders |= BIT(panel_transcoder);
9700 if (enabled_panel_transcoders != BIT(panel_transcoder))
9703 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9705 WARN(1, "unknown pipe linked to transcoder %s\n",
9706 transcoder_name(panel_transcoder));
9708 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9711 case TRANS_DDI_EDP_INPUT_A_ON:
9712 trans_pipe = PIPE_A;
9714 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9715 trans_pipe = PIPE_B;
9717 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9718 trans_pipe = PIPE_C;
9722 if (trans_pipe == crtc->pipe) {
9723 pipe_config->cpu_transcoder = panel_transcoder;
9724 pipe_config->pch_pfit.force_thru = force_thru;
9729 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
9731 WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
9732 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
9734 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9735 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
9737 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
9741 wakerefs[power_domain] = wf;
9742 *power_domain_mask |= BIT_ULL(power_domain);
9744 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9746 return tmp & PIPECONF_ENABLE;
9749 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9750 struct intel_crtc_state *pipe_config,
9751 u64 *power_domain_mask,
9752 intel_wakeref_t *wakerefs)
9754 struct drm_device *dev = crtc->base.dev;
9755 struct drm_i915_private *dev_priv = to_i915(dev);
9756 enum intel_display_power_domain power_domain;
9757 enum transcoder cpu_transcoder;
9762 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9764 cpu_transcoder = TRANSCODER_DSI_A;
9766 cpu_transcoder = TRANSCODER_DSI_C;
9768 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9769 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
9771 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
9775 wakerefs[power_domain] = wf;
9776 *power_domain_mask |= BIT_ULL(power_domain);
9779 * The PLL needs to be enabled with a valid divider
9780 * configuration, otherwise accessing DSI registers will hang
9781 * the machine. See BSpec North Display Engine
9782 * registers/MIPI[BXT]. We can break out here early, since we
9783 * need the same DSI PLL to be enabled for both DSI ports.
9785 if (!bxt_dsi_pll_is_enabled(dev_priv))
9788 /* XXX: this works for video mode only */
9789 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9790 if (!(tmp & DPI_ENABLE))
9793 tmp = I915_READ(MIPI_CTRL(port));
9794 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9797 pipe_config->cpu_transcoder = cpu_transcoder;
9801 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9804 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9805 struct intel_crtc_state *pipe_config)
9807 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9808 struct intel_shared_dpll *pll;
9812 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9814 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9816 if (INTEL_GEN(dev_priv) >= 11)
9817 icelake_get_ddi_pll(dev_priv, port, pipe_config);
9818 else if (IS_CANNONLAKE(dev_priv))
9819 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9820 else if (IS_GEN9_BC(dev_priv))
9821 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9822 else if (IS_GEN9_LP(dev_priv))
9823 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9825 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9827 pll = pipe_config->shared_dpll;
9829 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9830 &pipe_config->dpll_hw_state));
9834 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9835 * DDI E. So just check whether this pipe is wired to DDI E and whether
9836 * the PCH transcoder is on.
9838 if (INTEL_GEN(dev_priv) < 9 &&
9839 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9840 pipe_config->has_pch_encoder = true;
9842 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9843 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9844 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9846 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9850 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9851 struct intel_crtc_state *pipe_config)
9853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9854 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
9855 enum intel_display_power_domain power_domain;
9856 u64 power_domain_mask;
9859 intel_crtc_init_scalers(crtc, pipe_config);
9861 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9862 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
9866 wakerefs[power_domain] = wf;
9867 power_domain_mask = BIT_ULL(power_domain);
9869 pipe_config->shared_dpll = NULL;
9871 active = hsw_get_transcoder_state(crtc, pipe_config,
9872 &power_domain_mask, wakerefs);
9874 if (IS_GEN9_LP(dev_priv) &&
9875 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9876 &power_domain_mask, wakerefs)) {
9884 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
9885 INTEL_GEN(dev_priv) >= 11) {
9886 haswell_get_ddi_port_state(crtc, pipe_config);
9887 intel_get_pipe_timings(crtc, pipe_config);
9890 intel_get_pipe_src_size(crtc, pipe_config);
9891 intel_get_crtc_ycbcr_config(crtc, pipe_config);
9893 pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
9895 pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
9897 if (INTEL_GEN(dev_priv) >= 9) {
9898 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
9900 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
9901 pipe_config->gamma_enable = true;
9903 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
9904 pipe_config->csc_enable = true;
9906 i9xx_get_pipe_color_config(pipe_config);
9909 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9910 WARN_ON(power_domain_mask & BIT_ULL(power_domain));
9912 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
9914 wakerefs[power_domain] = wf;
9915 power_domain_mask |= BIT_ULL(power_domain);
9917 if (INTEL_GEN(dev_priv) >= 9)
9918 skylake_get_pfit_config(crtc, pipe_config);
9920 ironlake_get_pfit_config(crtc, pipe_config);
9923 if (hsw_crtc_supports_ips(crtc)) {
9924 if (IS_HASWELL(dev_priv))
9925 pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
9928 * We cannot readout IPS state on broadwell, set to
9929 * true so we can set it to a defined state on first
9932 pipe_config->ips_enabled = true;
9936 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9937 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9938 pipe_config->pixel_multiplier =
9939 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9941 pipe_config->pixel_multiplier = 1;
9945 for_each_power_domain(power_domain, power_domain_mask)
9946 intel_display_power_put(dev_priv,
9947 power_domain, wakerefs[power_domain]);
9952 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9954 struct drm_i915_private *dev_priv =
9955 to_i915(plane_state->base.plane->dev);
9956 const struct drm_framebuffer *fb = plane_state->base.fb;
9957 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9960 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
9961 base = obj->phys_handle->busaddr;
9963 base = intel_plane_ggtt_offset(plane_state);
9965 base += plane_state->color_plane[0].offset;
9967 /* ILK+ do this automagically */
9968 if (HAS_GMCH(dev_priv) &&
9969 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9970 base += (plane_state->base.crtc_h *
9971 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9976 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9978 int x = plane_state->base.crtc_x;
9979 int y = plane_state->base.crtc_y;
9983 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9986 pos |= x << CURSOR_X_SHIFT;
9989 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9992 pos |= y << CURSOR_Y_SHIFT;
9997 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9999 const struct drm_mode_config *config =
10000 &plane_state->base.plane->dev->mode_config;
10001 int width = plane_state->base.crtc_w;
10002 int height = plane_state->base.crtc_h;
10004 return width > 0 && width <= config->cursor_width &&
10005 height > 0 && height <= config->cursor_height;
10008 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10010 const struct drm_framebuffer *fb = plane_state->base.fb;
10011 unsigned int rotation = plane_state->base.rotation;
10016 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
10017 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
10019 ret = intel_plane_check_stride(plane_state);
10023 src_x = plane_state->base.src_x >> 16;
10024 src_y = plane_state->base.src_y >> 16;
10026 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10027 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10030 if (src_x != 0 || src_y != 0) {
10031 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10035 plane_state->color_plane[0].offset = offset;
10040 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10041 struct intel_plane_state *plane_state)
10043 const struct drm_framebuffer *fb = plane_state->base.fb;
10046 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10047 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10051 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
10053 DRM_PLANE_HELPER_NO_SCALING,
10054 DRM_PLANE_HELPER_NO_SCALING,
10059 if (!plane_state->base.visible)
10062 ret = intel_plane_check_src_coordinates(plane_state);
10066 ret = intel_cursor_check_surface(plane_state);
10073 static unsigned int
10074 i845_cursor_max_stride(struct intel_plane *plane,
10075 u32 pixel_format, u64 modifier,
10076 unsigned int rotation)
10081 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10085 if (crtc_state->gamma_enable)
10086 cntl |= CURSOR_GAMMA_ENABLE;
10091 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10092 const struct intel_plane_state *plane_state)
10094 return CURSOR_ENABLE |
10095 CURSOR_FORMAT_ARGB |
10096 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10099 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10101 int width = plane_state->base.crtc_w;
10104 * 845g/865g are only limited by the width of their cursors,
10105 * the height is arbitrary up to the precision of the register.
10107 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10110 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10111 struct intel_plane_state *plane_state)
10113 const struct drm_framebuffer *fb = plane_state->base.fb;
10116 ret = intel_check_cursor(crtc_state, plane_state);
10120 /* if we want to turn off the cursor ignore width and height */
10124 /* Check for which cursor types we support */
10125 if (!i845_cursor_size_ok(plane_state)) {
10126 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10127 plane_state->base.crtc_w,
10128 plane_state->base.crtc_h);
10132 WARN_ON(plane_state->base.visible &&
10133 plane_state->color_plane[0].stride != fb->pitches[0]);
10135 switch (fb->pitches[0]) {
10142 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10147 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
10152 static void i845_update_cursor(struct intel_plane *plane,
10153 const struct intel_crtc_state *crtc_state,
10154 const struct intel_plane_state *plane_state)
10156 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10157 u32 cntl = 0, base = 0, pos = 0, size = 0;
10158 unsigned long irqflags;
10160 if (plane_state && plane_state->base.visible) {
10161 unsigned int width = plane_state->base.crtc_w;
10162 unsigned int height = plane_state->base.crtc_h;
10164 cntl = plane_state->ctl |
10165 i845_cursor_ctl_crtc(crtc_state);
10167 size = (height << 12) | width;
10169 base = intel_cursor_base(plane_state);
10170 pos = intel_cursor_position(plane_state);
10173 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10175 /* On these chipsets we can only modify the base/size/stride
10176 * whilst the cursor is disabled.
10178 if (plane->cursor.base != base ||
10179 plane->cursor.size != size ||
10180 plane->cursor.cntl != cntl) {
10181 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
10182 I915_WRITE_FW(CURBASE(PIPE_A), base);
10183 I915_WRITE_FW(CURSIZE, size);
10184 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10185 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
10187 plane->cursor.base = base;
10188 plane->cursor.size = size;
10189 plane->cursor.cntl = cntl;
10191 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10194 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10197 static void i845_disable_cursor(struct intel_plane *plane,
10198 const struct intel_crtc_state *crtc_state)
10200 i845_update_cursor(plane, crtc_state, NULL);
10203 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
10206 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10207 enum intel_display_power_domain power_domain;
10208 intel_wakeref_t wakeref;
10211 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
10212 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10216 ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
10220 intel_display_power_put(dev_priv, power_domain, wakeref);
10225 static unsigned int
10226 i9xx_cursor_max_stride(struct intel_plane *plane,
10227 u32 pixel_format, u64 modifier,
10228 unsigned int rotation)
10230 return plane->base.dev->mode_config.cursor_width * 4;
10233 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10235 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
10236 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10239 if (INTEL_GEN(dev_priv) >= 11)
10242 if (crtc_state->gamma_enable)
10243 cntl = MCURSOR_GAMMA_ENABLE;
10245 if (crtc_state->csc_enable)
10246 cntl |= MCURSOR_PIPE_CSC_ENABLE;
10248 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10249 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
10254 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
10255 const struct intel_plane_state *plane_state)
10257 struct drm_i915_private *dev_priv =
10258 to_i915(plane_state->base.plane->dev);
10261 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
10262 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
10264 switch (plane_state->base.crtc_w) {
10266 cntl |= MCURSOR_MODE_64_ARGB_AX;
10269 cntl |= MCURSOR_MODE_128_ARGB_AX;
10272 cntl |= MCURSOR_MODE_256_ARGB_AX;
10275 MISSING_CASE(plane_state->base.crtc_w);
10279 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
10280 cntl |= MCURSOR_ROTATE_180;
10285 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
10287 struct drm_i915_private *dev_priv =
10288 to_i915(plane_state->base.plane->dev);
10289 int width = plane_state->base.crtc_w;
10290 int height = plane_state->base.crtc_h;
10292 if (!intel_cursor_size_ok(plane_state))
10295 /* Cursor width is limited to a few power-of-two sizes */
10306 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
10307 * height from 8 lines up to the cursor width, when the
10308 * cursor is not rotated. Everything else requires square
10311 if (HAS_CUR_FBC(dev_priv) &&
10312 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
10313 if (height < 8 || height > width)
10316 if (height != width)
10323 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
10324 struct intel_plane_state *plane_state)
10326 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
10327 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10328 const struct drm_framebuffer *fb = plane_state->base.fb;
10329 enum pipe pipe = plane->pipe;
10332 ret = intel_check_cursor(crtc_state, plane_state);
10336 /* if we want to turn off the cursor ignore width and height */
10340 /* Check for which cursor types we support */
10341 if (!i9xx_cursor_size_ok(plane_state)) {
10342 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10343 plane_state->base.crtc_w,
10344 plane_state->base.crtc_h);
10348 WARN_ON(plane_state->base.visible &&
10349 plane_state->color_plane[0].stride != fb->pitches[0]);
10351 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
10352 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
10353 fb->pitches[0], plane_state->base.crtc_w);
10358 * There's something wrong with the cursor on CHV pipe C.
10359 * If it straddles the left edge of the screen then
10360 * moving it away from the edge or disabling it often
10361 * results in a pipe underrun, and often that can lead to
10362 * dead pipe (constant underrun reported, and it scans
10363 * out just a solid color). To recover from that, the
10364 * display power well must be turned off and on again.
10365 * Refuse the put the cursor into that compromised position.
10367 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
10368 plane_state->base.visible && plane_state->base.crtc_x < 0) {
10369 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
10373 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
10378 static void i9xx_update_cursor(struct intel_plane *plane,
10379 const struct intel_crtc_state *crtc_state,
10380 const struct intel_plane_state *plane_state)
10382 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10383 enum pipe pipe = plane->pipe;
10384 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
10385 unsigned long irqflags;
10387 if (plane_state && plane_state->base.visible) {
10388 cntl = plane_state->ctl |
10389 i9xx_cursor_ctl_crtc(crtc_state);
10391 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
10392 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
10394 base = intel_cursor_base(plane_state);
10395 pos = intel_cursor_position(plane_state);
10398 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10401 * On some platforms writing CURCNTR first will also
10402 * cause CURPOS to be armed by the CURBASE write.
10403 * Without the CURCNTR write the CURPOS write would
10404 * arm itself. Thus we always update CURCNTR before
10407 * On other platforms CURPOS always requires the
10408 * CURBASE write to arm the update. Additonally
10409 * a write to any of the cursor register will cancel
10410 * an already armed cursor update. Thus leaving out
10411 * the CURBASE write after CURPOS could lead to a
10412 * cursor that doesn't appear to move, or even change
10413 * shape. Thus we always write CURBASE.
10415 * The other registers are armed by by the CURBASE write
10416 * except when the plane is getting enabled at which time
10417 * the CURCNTR write arms the update.
10420 if (INTEL_GEN(dev_priv) >= 9)
10421 skl_write_cursor_wm(plane, crtc_state);
10423 if (plane->cursor.base != base ||
10424 plane->cursor.size != fbc_ctl ||
10425 plane->cursor.cntl != cntl) {
10426 if (HAS_CUR_FBC(dev_priv))
10427 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
10428 I915_WRITE_FW(CURCNTR(pipe), cntl);
10429 I915_WRITE_FW(CURPOS(pipe), pos);
10430 I915_WRITE_FW(CURBASE(pipe), base);
10432 plane->cursor.base = base;
10433 plane->cursor.size = fbc_ctl;
10434 plane->cursor.cntl = cntl;
10436 I915_WRITE_FW(CURPOS(pipe), pos);
10437 I915_WRITE_FW(CURBASE(pipe), base);
10440 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10443 static void i9xx_disable_cursor(struct intel_plane *plane,
10444 const struct intel_crtc_state *crtc_state)
10446 i9xx_update_cursor(plane, crtc_state, NULL);
10449 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
10452 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10453 enum intel_display_power_domain power_domain;
10454 intel_wakeref_t wakeref;
10459 * Not 100% correct for planes that can move between pipes,
10460 * but that's only the case for gen2-3 which don't have any
10461 * display power wells.
10463 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
10464 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10468 val = I915_READ(CURCNTR(plane->pipe));
10470 ret = val & MCURSOR_MODE;
10472 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10473 *pipe = plane->pipe;
10475 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
10476 MCURSOR_PIPE_SELECT_SHIFT;
10478 intel_display_power_put(dev_priv, power_domain, wakeref);
10483 /* VESA 640x480x72Hz mode to set on the pipe */
10484 static const struct drm_display_mode load_detect_mode = {
10485 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10486 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10489 struct drm_framebuffer *
10490 intel_framebuffer_create(struct drm_i915_gem_object *obj,
10491 struct drm_mode_fb_cmd2 *mode_cmd)
10493 struct intel_framebuffer *intel_fb;
10496 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10498 return ERR_PTR(-ENOMEM);
10500 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
10504 return &intel_fb->base;
10508 return ERR_PTR(ret);
10511 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
10512 struct drm_crtc *crtc)
10514 struct drm_plane *plane;
10515 struct drm_plane_state *plane_state;
10518 ret = drm_atomic_add_affected_planes(state, crtc);
10522 for_each_new_plane_in_state(state, plane, plane_state, i) {
10523 if (plane_state->crtc != crtc)
10526 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
10530 drm_atomic_set_fb_for_plane(plane_state, NULL);
10536 int intel_get_load_detect_pipe(struct drm_connector *connector,
10537 const struct drm_display_mode *mode,
10538 struct intel_load_detect_pipe *old,
10539 struct drm_modeset_acquire_ctx *ctx)
10541 struct intel_crtc *intel_crtc;
10542 struct intel_encoder *intel_encoder =
10543 intel_attached_encoder(connector);
10544 struct drm_crtc *possible_crtc;
10545 struct drm_encoder *encoder = &intel_encoder->base;
10546 struct drm_crtc *crtc = NULL;
10547 struct drm_device *dev = encoder->dev;
10548 struct drm_i915_private *dev_priv = to_i915(dev);
10549 struct drm_mode_config *config = &dev->mode_config;
10550 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10551 struct drm_connector_state *connector_state;
10552 struct intel_crtc_state *crtc_state;
10555 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10556 connector->base.id, connector->name,
10557 encoder->base.id, encoder->name);
10559 old->restore_state = NULL;
10561 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
10564 * Algorithm gets a little messy:
10566 * - if the connector already has an assigned crtc, use it (but make
10567 * sure it's on first)
10569 * - try to find the first unused crtc that can drive this connector,
10570 * and use that if we find one
10573 /* See if we already have a CRTC for this connector */
10574 if (connector->state->crtc) {
10575 crtc = connector->state->crtc;
10577 ret = drm_modeset_lock(&crtc->mutex, ctx);
10581 /* Make sure the crtc and connector are running */
10585 /* Find an unused one (if possible) */
10586 for_each_crtc(dev, possible_crtc) {
10588 if (!(encoder->possible_crtcs & (1 << i)))
10591 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10595 if (possible_crtc->state->enable) {
10596 drm_modeset_unlock(&possible_crtc->mutex);
10600 crtc = possible_crtc;
10605 * If we didn't find an unused CRTC, don't use any.
10608 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10614 intel_crtc = to_intel_crtc(crtc);
10616 state = drm_atomic_state_alloc(dev);
10617 restore_state = drm_atomic_state_alloc(dev);
10618 if (!state || !restore_state) {
10623 state->acquire_ctx = ctx;
10624 restore_state->acquire_ctx = ctx;
10626 connector_state = drm_atomic_get_connector_state(state, connector);
10627 if (IS_ERR(connector_state)) {
10628 ret = PTR_ERR(connector_state);
10632 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10636 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10637 if (IS_ERR(crtc_state)) {
10638 ret = PTR_ERR(crtc_state);
10642 crtc_state->base.active = crtc_state->base.enable = true;
10645 mode = &load_detect_mode;
10647 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10651 ret = intel_modeset_disable_planes(state, crtc);
10655 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10657 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10659 ret = drm_atomic_add_affected_planes(restore_state, crtc);
10661 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10665 ret = drm_atomic_commit(state);
10667 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10671 old->restore_state = restore_state;
10672 drm_atomic_state_put(state);
10674 /* let the connector get through one full cycle before testing */
10675 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10680 drm_atomic_state_put(state);
10683 if (restore_state) {
10684 drm_atomic_state_put(restore_state);
10685 restore_state = NULL;
10688 if (ret == -EDEADLK)
10694 void intel_release_load_detect_pipe(struct drm_connector *connector,
10695 struct intel_load_detect_pipe *old,
10696 struct drm_modeset_acquire_ctx *ctx)
10698 struct intel_encoder *intel_encoder =
10699 intel_attached_encoder(connector);
10700 struct drm_encoder *encoder = &intel_encoder->base;
10701 struct drm_atomic_state *state = old->restore_state;
10704 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10705 connector->base.id, connector->name,
10706 encoder->base.id, encoder->name);
10711 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10713 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10714 drm_atomic_state_put(state);
10717 static int i9xx_pll_refclk(struct drm_device *dev,
10718 const struct intel_crtc_state *pipe_config)
10720 struct drm_i915_private *dev_priv = to_i915(dev);
10721 u32 dpll = pipe_config->dpll_hw_state.dpll;
10723 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10724 return dev_priv->vbt.lvds_ssc_freq;
10725 else if (HAS_PCH_SPLIT(dev_priv))
10727 else if (!IS_GEN(dev_priv, 2))
10733 /* Returns the clock of the currently programmed mode of the given pipe. */
10734 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10735 struct intel_crtc_state *pipe_config)
10737 struct drm_device *dev = crtc->base.dev;
10738 struct drm_i915_private *dev_priv = to_i915(dev);
10739 int pipe = pipe_config->cpu_transcoder;
10740 u32 dpll = pipe_config->dpll_hw_state.dpll;
10744 int refclk = i9xx_pll_refclk(dev, pipe_config);
10746 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10747 fp = pipe_config->dpll_hw_state.fp0;
10749 fp = pipe_config->dpll_hw_state.fp1;
10751 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10752 if (IS_PINEVIEW(dev_priv)) {
10753 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10754 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10756 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10757 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10760 if (!IS_GEN(dev_priv, 2)) {
10761 if (IS_PINEVIEW(dev_priv))
10762 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10763 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10765 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10766 DPLL_FPA01_P1_POST_DIV_SHIFT);
10768 switch (dpll & DPLL_MODE_MASK) {
10769 case DPLLB_MODE_DAC_SERIAL:
10770 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10773 case DPLLB_MODE_LVDS:
10774 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10778 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10779 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10783 if (IS_PINEVIEW(dev_priv))
10784 port_clock = pnv_calc_dpll_params(refclk, &clock);
10786 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10788 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10789 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10792 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10793 DPLL_FPA01_P1_POST_DIV_SHIFT);
10795 if (lvds & LVDS_CLKB_POWER_UP)
10800 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10803 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10804 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10806 if (dpll & PLL_P2_DIVIDE_BY_4)
10812 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10816 * This value includes pixel_multiplier. We will use
10817 * port_clock to compute adjusted_mode.crtc_clock in the
10818 * encoder's get_config() function.
10820 pipe_config->port_clock = port_clock;
10823 int intel_dotclock_calculate(int link_freq,
10824 const struct intel_link_m_n *m_n)
10827 * The calculation for the data clock is:
10828 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10829 * But we want to avoid losing precison if possible, so:
10830 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10832 * and the link clock is simpler:
10833 * link_clock = (m * link_clock) / n
10839 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10842 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10843 struct intel_crtc_state *pipe_config)
10845 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10847 /* read out port_clock from the DPLL */
10848 i9xx_crtc_clock_get(crtc, pipe_config);
10851 * In case there is an active pipe without active ports,
10852 * we may need some idea for the dotclock anyway.
10853 * Calculate one based on the FDI configuration.
10855 pipe_config->base.adjusted_mode.crtc_clock =
10856 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10857 &pipe_config->fdi_m_n);
10860 /* Returns the currently programmed mode of the given encoder. */
10861 struct drm_display_mode *
10862 intel_encoder_current_mode(struct intel_encoder *encoder)
10864 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10865 struct intel_crtc_state *crtc_state;
10866 struct drm_display_mode *mode;
10867 struct intel_crtc *crtc;
10870 if (!encoder->get_hw_state(encoder, &pipe))
10873 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10875 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10879 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10885 crtc_state->base.crtc = &crtc->base;
10887 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10893 encoder->get_config(encoder, crtc_state);
10895 intel_mode_from_pipe_config(mode, crtc_state);
10902 static void intel_crtc_destroy(struct drm_crtc *crtc)
10904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10906 drm_crtc_cleanup(crtc);
10911 * intel_wm_need_update - Check whether watermarks need updating
10912 * @cur: current plane state
10913 * @new: new plane state
10915 * Check current plane state versus the new one to determine whether
10916 * watermarks need to be recalculated.
10918 * Returns true or false.
10920 static bool intel_wm_need_update(struct intel_plane_state *cur,
10921 struct intel_plane_state *new)
10923 /* Update watermarks on tiling or size changes. */
10924 if (new->base.visible != cur->base.visible)
10927 if (!cur->base.fb || !new->base.fb)
10930 if (cur->base.fb->modifier != new->base.fb->modifier ||
10931 cur->base.rotation != new->base.rotation ||
10932 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10933 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10934 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10935 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10941 static bool needs_scaling(const struct intel_plane_state *state)
10943 int src_w = drm_rect_width(&state->base.src) >> 16;
10944 int src_h = drm_rect_height(&state->base.src) >> 16;
10945 int dst_w = drm_rect_width(&state->base.dst);
10946 int dst_h = drm_rect_height(&state->base.dst);
10948 return (src_w != dst_w || src_h != dst_h);
10951 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10952 struct drm_crtc_state *crtc_state,
10953 const struct intel_plane_state *old_plane_state,
10954 struct drm_plane_state *plane_state)
10956 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10957 struct drm_crtc *crtc = crtc_state->crtc;
10958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10959 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10960 struct drm_device *dev = crtc->dev;
10961 struct drm_i915_private *dev_priv = to_i915(dev);
10962 bool mode_changed = needs_modeset(crtc_state);
10963 bool was_crtc_enabled = old_crtc_state->base.active;
10964 bool is_crtc_enabled = crtc_state->active;
10965 bool turn_off, turn_on, visible, was_visible;
10966 struct drm_framebuffer *fb = plane_state->fb;
10969 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10970 ret = skl_update_scaler_plane(
10971 to_intel_crtc_state(crtc_state),
10972 to_intel_plane_state(plane_state));
10977 was_visible = old_plane_state->base.visible;
10978 visible = plane_state->visible;
10980 if (!was_crtc_enabled && WARN_ON(was_visible))
10981 was_visible = false;
10984 * Visibility is calculated as if the crtc was on, but
10985 * after scaler setup everything depends on it being off
10986 * when the crtc isn't active.
10988 * FIXME this is wrong for watermarks. Watermarks should also
10989 * be computed as if the pipe would be active. Perhaps move
10990 * per-plane wm computation to the .check_plane() hook, and
10991 * only combine the results from all planes in the current place?
10993 if (!is_crtc_enabled) {
10994 plane_state->visible = visible = false;
10995 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10998 if (!was_visible && !visible)
11001 if (fb != old_plane_state->base.fb)
11002 pipe_config->fb_changed = true;
11004 turn_off = was_visible && (!visible || mode_changed);
11005 turn_on = visible && (!was_visible || mode_changed);
11007 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11008 intel_crtc->base.base.id, intel_crtc->base.name,
11009 plane->base.base.id, plane->base.name,
11010 fb ? fb->base.id : -1);
11012 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11013 plane->base.base.id, plane->base.name,
11014 was_visible, visible,
11015 turn_off, turn_on, mode_changed);
11018 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11019 pipe_config->update_wm_pre = true;
11021 /* must disable cxsr around plane enable/disable */
11022 if (plane->id != PLANE_CURSOR)
11023 pipe_config->disable_cxsr = true;
11024 } else if (turn_off) {
11025 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11026 pipe_config->update_wm_post = true;
11028 /* must disable cxsr around plane enable/disable */
11029 if (plane->id != PLANE_CURSOR)
11030 pipe_config->disable_cxsr = true;
11031 } else if (intel_wm_need_update(to_intel_plane_state(plane->base.state),
11032 to_intel_plane_state(plane_state))) {
11033 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11034 /* FIXME bollocks */
11035 pipe_config->update_wm_pre = true;
11036 pipe_config->update_wm_post = true;
11040 if (visible || was_visible)
11041 pipe_config->fb_bits |= plane->frontbuffer_bit;
11044 * ILK/SNB DVSACNTR/Sprite Enable
11045 * IVB SPR_CTL/Sprite Enable
11046 * "When in Self Refresh Big FIFO mode, a write to enable the
11047 * plane will be internally buffered and delayed while Big FIFO
11048 * mode is exiting."
11050 * Which means that enabling the sprite can take an extra frame
11051 * when we start in big FIFO mode (LP1+). Thus we need to drop
11052 * down to LP0 and wait for vblank in order to make sure the
11053 * sprite gets enabled on the next vblank after the register write.
11054 * Doing otherwise would risk enabling the sprite one frame after
11055 * we've already signalled flip completion. We can resume LP1+
11056 * once the sprite has been enabled.
11059 * WaCxSRDisabledForSpriteScaling:ivb
11060 * IVB SPR_SCALE/Scaling Enable
11061 * "Low Power watermarks must be disabled for at least one
11062 * frame before enabling sprite scaling, and kept disabled
11063 * until sprite scaling is disabled."
11065 * ILK/SNB DVSASCALE/Scaling Enable
11066 * "When in Self Refresh Big FIFO mode, scaling enable will be
11067 * masked off while Big FIFO mode is exiting."
11069 * Despite the w/a only being listed for IVB we assume that
11070 * the ILK/SNB note has similar ramifications, hence we apply
11071 * the w/a on all three platforms.
11073 * With experimental results seems this is needed also for primary
11074 * plane, not only sprite plane.
11076 if (plane->id != PLANE_CURSOR &&
11077 (IS_GEN_RANGE(dev_priv, 5, 6) ||
11078 IS_IVYBRIDGE(dev_priv)) &&
11079 (turn_on || (!needs_scaling(old_plane_state) &&
11080 needs_scaling(to_intel_plane_state(plane_state)))))
11081 pipe_config->disable_lp_wm = true;
11086 static bool encoders_cloneable(const struct intel_encoder *a,
11087 const struct intel_encoder *b)
11089 /* masks could be asymmetric, so check both ways */
11090 return a == b || (a->cloneable & (1 << b->type) &&
11091 b->cloneable & (1 << a->type));
11094 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11095 struct intel_crtc *crtc,
11096 struct intel_encoder *encoder)
11098 struct intel_encoder *source_encoder;
11099 struct drm_connector *connector;
11100 struct drm_connector_state *connector_state;
11103 for_each_new_connector_in_state(state, connector, connector_state, i) {
11104 if (connector_state->crtc != &crtc->base)
11108 to_intel_encoder(connector_state->best_encoder);
11109 if (!encoders_cloneable(encoder, source_encoder))
11116 static int icl_add_linked_planes(struct intel_atomic_state *state)
11118 struct intel_plane *plane, *linked;
11119 struct intel_plane_state *plane_state, *linked_plane_state;
11122 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11123 linked = plane_state->linked_plane;
11128 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11129 if (IS_ERR(linked_plane_state))
11130 return PTR_ERR(linked_plane_state);
11132 WARN_ON(linked_plane_state->linked_plane != plane);
11133 WARN_ON(linked_plane_state->slave == plane_state->slave);
11139 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
11141 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
11142 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11143 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
11144 struct intel_plane *plane, *linked;
11145 struct intel_plane_state *plane_state;
11148 if (INTEL_GEN(dev_priv) < 11)
11152 * Destroy all old plane links and make the slave plane invisible
11153 * in the crtc_state->active_planes mask.
11155 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11156 if (plane->pipe != crtc->pipe || !plane_state->linked_plane)
11159 plane_state->linked_plane = NULL;
11160 if (plane_state->slave && !plane_state->base.visible) {
11161 crtc_state->active_planes &= ~BIT(plane->id);
11162 crtc_state->update_planes |= BIT(plane->id);
11165 plane_state->slave = false;
11168 if (!crtc_state->nv12_planes)
11171 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11172 struct intel_plane_state *linked_state = NULL;
11174 if (plane->pipe != crtc->pipe ||
11175 !(crtc_state->nv12_planes & BIT(plane->id)))
11178 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
11179 if (!icl_is_nv12_y_plane(linked->id))
11182 if (crtc_state->active_planes & BIT(linked->id))
11185 linked_state = intel_atomic_get_plane_state(state, linked);
11186 if (IS_ERR(linked_state))
11187 return PTR_ERR(linked_state);
11192 if (!linked_state) {
11193 DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
11194 hweight8(crtc_state->nv12_planes));
11199 plane_state->linked_plane = linked;
11201 linked_state->slave = true;
11202 linked_state->linked_plane = plane;
11203 crtc_state->active_planes |= BIT(linked->id);
11204 crtc_state->update_planes |= BIT(linked->id);
11205 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
11211 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11212 struct drm_crtc_state *crtc_state)
11214 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11216 struct intel_crtc_state *pipe_config =
11217 to_intel_crtc_state(crtc_state);
11219 bool mode_changed = needs_modeset(crtc_state);
11221 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
11222 mode_changed && !crtc_state->active)
11223 pipe_config->update_wm_post = true;
11225 if (mode_changed && crtc_state->enable &&
11226 dev_priv->display.crtc_compute_clock &&
11227 !WARN_ON(pipe_config->shared_dpll)) {
11228 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11234 if (mode_changed || pipe_config->update_pipe ||
11235 crtc_state->color_mgmt_changed) {
11236 ret = intel_color_check(pipe_config);
11242 if (dev_priv->display.compute_pipe_wm) {
11243 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11245 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11250 if (dev_priv->display.compute_intermediate_wm) {
11251 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11255 * Calculate 'intermediate' watermarks that satisfy both the
11256 * old state and the new state. We can program these
11259 ret = dev_priv->display.compute_intermediate_wm(pipe_config);
11261 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11266 if (INTEL_GEN(dev_priv) >= 9) {
11267 if (mode_changed || pipe_config->update_pipe)
11268 ret = skl_update_scaler_crtc(pipe_config);
11271 ret = icl_check_nv12_planes(pipe_config);
11273 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
11276 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11280 if (HAS_IPS(dev_priv))
11281 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
11286 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11287 .atomic_check = intel_crtc_atomic_check,
11290 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11292 struct intel_connector *connector;
11293 struct drm_connector_list_iter conn_iter;
11295 drm_connector_list_iter_begin(dev, &conn_iter);
11296 for_each_intel_connector_iter(connector, &conn_iter) {
11297 if (connector->base.state->crtc)
11298 drm_connector_put(&connector->base);
11300 if (connector->base.encoder) {
11301 connector->base.state->best_encoder =
11302 connector->base.encoder;
11303 connector->base.state->crtc =
11304 connector->base.encoder->crtc;
11306 drm_connector_get(&connector->base);
11308 connector->base.state->best_encoder = NULL;
11309 connector->base.state->crtc = NULL;
11312 drm_connector_list_iter_end(&conn_iter);
11316 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
11317 struct intel_crtc_state *pipe_config)
11319 struct drm_connector *connector = conn_state->connector;
11320 const struct drm_display_info *info = &connector->display_info;
11323 switch (conn_state->max_bpc) {
11340 if (bpp < pipe_config->pipe_bpp) {
11341 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
11342 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
11343 connector->base.id, connector->name,
11344 bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
11345 pipe_config->pipe_bpp);
11347 pipe_config->pipe_bpp = bpp;
11354 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11355 struct intel_crtc_state *pipe_config)
11357 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11358 struct drm_atomic_state *state = pipe_config->base.state;
11359 struct drm_connector *connector;
11360 struct drm_connector_state *connector_state;
11363 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11364 IS_CHERRYVIEW(dev_priv)))
11366 else if (INTEL_GEN(dev_priv) >= 5)
11371 pipe_config->pipe_bpp = bpp;
11373 /* Clamp display bpp to connector max bpp */
11374 for_each_new_connector_in_state(state, connector, connector_state, i) {
11377 if (connector_state->crtc != &crtc->base)
11380 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
11388 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11390 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11391 "type: 0x%x flags: 0x%x\n",
11393 mode->crtc_hdisplay, mode->crtc_hsync_start,
11394 mode->crtc_hsync_end, mode->crtc_htotal,
11395 mode->crtc_vdisplay, mode->crtc_vsync_start,
11396 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11400 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11401 unsigned int lane_count, struct intel_link_m_n *m_n)
11403 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11405 m_n->gmch_m, m_n->gmch_n,
11406 m_n->link_m, m_n->link_n, m_n->tu);
11410 intel_dump_infoframe(struct drm_i915_private *dev_priv,
11411 const union hdmi_infoframe *frame)
11413 if ((drm_debug & DRM_UT_KMS) == 0)
11416 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
11419 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
11421 static const char * const output_type_str[] = {
11422 OUTPUT_TYPE(UNUSED),
11423 OUTPUT_TYPE(ANALOG),
11427 OUTPUT_TYPE(TVOUT),
11433 OUTPUT_TYPE(DP_MST),
11438 static void snprintf_output_types(char *buf, size_t len,
11439 unsigned int output_types)
11446 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
11449 if ((output_types & BIT(i)) == 0)
11452 r = snprintf(str, len, "%s%s",
11453 str != buf ? "," : "", output_type_str[i]);
11459 output_types &= ~BIT(i);
11462 WARN_ON_ONCE(output_types != 0);
11465 static const char * const output_format_str[] = {
11466 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
11467 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
11468 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
11469 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
11472 static const char *output_formats(enum intel_output_format format)
11474 if (format >= ARRAY_SIZE(output_format_str))
11475 format = INTEL_OUTPUT_FORMAT_INVALID;
11476 return output_format_str[format];
11479 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11480 struct intel_crtc_state *pipe_config,
11481 const char *context)
11483 struct drm_device *dev = crtc->base.dev;
11484 struct drm_i915_private *dev_priv = to_i915(dev);
11485 struct drm_plane *plane;
11486 struct intel_plane *intel_plane;
11487 struct intel_plane_state *state;
11488 struct drm_framebuffer *fb;
11491 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11492 crtc->base.base.id, crtc->base.name, context);
11494 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
11495 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
11496 buf, pipe_config->output_types);
11498 DRM_DEBUG_KMS("output format: %s\n",
11499 output_formats(pipe_config->output_format));
11501 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11502 transcoder_name(pipe_config->cpu_transcoder),
11503 pipe_config->pipe_bpp, pipe_config->dither);
11505 if (pipe_config->has_pch_encoder)
11506 intel_dump_m_n_config(pipe_config, "fdi",
11507 pipe_config->fdi_lanes,
11508 &pipe_config->fdi_m_n);
11510 if (intel_crtc_has_dp_encoder(pipe_config)) {
11511 intel_dump_m_n_config(pipe_config, "dp m_n",
11512 pipe_config->lane_count, &pipe_config->dp_m_n);
11513 if (pipe_config->has_drrs)
11514 intel_dump_m_n_config(pipe_config, "dp m2_n2",
11515 pipe_config->lane_count,
11516 &pipe_config->dp_m2_n2);
11519 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11520 pipe_config->has_audio, pipe_config->has_infoframe);
11522 DRM_DEBUG_KMS("infoframes enabled: 0x%x\n",
11523 pipe_config->infoframes.enable);
11525 if (pipe_config->infoframes.enable &
11526 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
11527 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
11528 if (pipe_config->infoframes.enable &
11529 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
11530 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
11531 if (pipe_config->infoframes.enable &
11532 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
11533 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
11534 if (pipe_config->infoframes.enable &
11535 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
11536 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
11538 DRM_DEBUG_KMS("requested mode:\n");
11539 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11540 DRM_DEBUG_KMS("adjusted mode:\n");
11541 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11542 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11543 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11544 pipe_config->port_clock,
11545 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11546 pipe_config->pixel_rate);
11548 if (INTEL_GEN(dev_priv) >= 9)
11549 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11551 pipe_config->scaler_state.scaler_users,
11552 pipe_config->scaler_state.scaler_id);
11554 if (HAS_GMCH(dev_priv))
11555 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11556 pipe_config->gmch_pfit.control,
11557 pipe_config->gmch_pfit.pgm_ratios,
11558 pipe_config->gmch_pfit.lvds_border_bits);
11560 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
11561 pipe_config->pch_pfit.pos,
11562 pipe_config->pch_pfit.size,
11563 enableddisabled(pipe_config->pch_pfit.enabled),
11564 yesno(pipe_config->pch_pfit.force_thru));
11566 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11567 pipe_config->ips_enabled, pipe_config->double_wide);
11569 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11571 DRM_DEBUG_KMS("planes on this crtc\n");
11572 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11573 struct drm_format_name_buf format_name;
11574 intel_plane = to_intel_plane(plane);
11575 if (intel_plane->pipe != crtc->pipe)
11578 state = to_intel_plane_state(plane->state);
11579 fb = state->base.fb;
11581 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11582 plane->base.id, plane->name, state->scaler_id);
11586 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11587 plane->base.id, plane->name,
11588 fb->base.id, fb->width, fb->height,
11589 drm_get_format_name(fb->format->format, &format_name));
11590 if (INTEL_GEN(dev_priv) >= 9)
11591 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11593 state->base.src.x1 >> 16,
11594 state->base.src.y1 >> 16,
11595 drm_rect_width(&state->base.src) >> 16,
11596 drm_rect_height(&state->base.src) >> 16,
11597 state->base.dst.x1, state->base.dst.y1,
11598 drm_rect_width(&state->base.dst),
11599 drm_rect_height(&state->base.dst));
11603 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11605 struct drm_device *dev = state->dev;
11606 struct drm_connector *connector;
11607 struct drm_connector_list_iter conn_iter;
11608 unsigned int used_ports = 0;
11609 unsigned int used_mst_ports = 0;
11613 * Walk the connector list instead of the encoder
11614 * list to detect the problem on ddi platforms
11615 * where there's just one encoder per digital port.
11617 drm_connector_list_iter_begin(dev, &conn_iter);
11618 drm_for_each_connector_iter(connector, &conn_iter) {
11619 struct drm_connector_state *connector_state;
11620 struct intel_encoder *encoder;
11622 connector_state = drm_atomic_get_new_connector_state(state, connector);
11623 if (!connector_state)
11624 connector_state = connector->state;
11626 if (!connector_state->best_encoder)
11629 encoder = to_intel_encoder(connector_state->best_encoder);
11631 WARN_ON(!connector_state->crtc);
11633 switch (encoder->type) {
11634 unsigned int port_mask;
11635 case INTEL_OUTPUT_DDI:
11636 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11638 /* else: fall through */
11639 case INTEL_OUTPUT_DP:
11640 case INTEL_OUTPUT_HDMI:
11641 case INTEL_OUTPUT_EDP:
11642 port_mask = 1 << encoder->port;
11644 /* the same port mustn't appear more than once */
11645 if (used_ports & port_mask)
11648 used_ports |= port_mask;
11650 case INTEL_OUTPUT_DP_MST:
11652 1 << encoder->port;
11658 drm_connector_list_iter_end(&conn_iter);
11660 /* can't mix MST and SST/HDMI on the same port */
11661 if (used_ports & used_mst_ports)
11668 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11670 struct drm_i915_private *dev_priv =
11671 to_i915(crtc_state->base.crtc->dev);
11672 struct intel_crtc_state *saved_state;
11674 saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
11678 /* FIXME: before the switch to atomic started, a new pipe_config was
11679 * kzalloc'd. Code that depends on any field being zero should be
11680 * fixed, so that the crtc_state can be safely duplicated. For now,
11681 * only fields that are know to not cause problems are preserved. */
11683 saved_state->scaler_state = crtc_state->scaler_state;
11684 saved_state->shared_dpll = crtc_state->shared_dpll;
11685 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
11686 saved_state->crc_enabled = crtc_state->crc_enabled;
11687 if (IS_G4X(dev_priv) ||
11688 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11689 saved_state->wm = crtc_state->wm;
11691 /* Keep base drm_crtc_state intact, only clear our extended struct */
11692 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11693 memcpy(&crtc_state->base + 1, &saved_state->base + 1,
11694 sizeof(*crtc_state) - sizeof(crtc_state->base));
11696 kfree(saved_state);
11701 intel_modeset_pipe_config(struct drm_crtc *crtc,
11702 struct intel_crtc_state *pipe_config)
11704 struct drm_atomic_state *state = pipe_config->base.state;
11705 struct intel_encoder *encoder;
11706 struct drm_connector *connector;
11707 struct drm_connector_state *connector_state;
11712 ret = clear_intel_crtc_state(pipe_config);
11716 pipe_config->cpu_transcoder =
11717 (enum transcoder) to_intel_crtc(crtc)->pipe;
11720 * Sanitize sync polarity flags based on requested ones. If neither
11721 * positive or negative polarity is requested, treat this as meaning
11722 * negative polarity.
11724 if (!(pipe_config->base.adjusted_mode.flags &
11725 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11726 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11728 if (!(pipe_config->base.adjusted_mode.flags &
11729 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11730 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11732 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11737 base_bpp = pipe_config->pipe_bpp;
11740 * Determine the real pipe dimensions. Note that stereo modes can
11741 * increase the actual pipe size due to the frame doubling and
11742 * insertion of additional space for blanks between the frame. This
11743 * is stored in the crtc timings. We use the requested mode to do this
11744 * computation to clearly distinguish it from the adjusted mode, which
11745 * can be changed by the connectors in the below retry loop.
11747 drm_mode_get_hv_timing(&pipe_config->base.mode,
11748 &pipe_config->pipe_src_w,
11749 &pipe_config->pipe_src_h);
11751 for_each_new_connector_in_state(state, connector, connector_state, i) {
11752 if (connector_state->crtc != crtc)
11755 encoder = to_intel_encoder(connector_state->best_encoder);
11757 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11758 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11763 * Determine output_types before calling the .compute_config()
11764 * hooks so that the hooks can use this information safely.
11766 if (encoder->compute_output_type)
11767 pipe_config->output_types |=
11768 BIT(encoder->compute_output_type(encoder, pipe_config,
11771 pipe_config->output_types |= BIT(encoder->type);
11775 /* Ensure the port clock defaults are reset when retrying. */
11776 pipe_config->port_clock = 0;
11777 pipe_config->pixel_multiplier = 1;
11779 /* Fill in default crtc timings, allow encoders to overwrite them. */
11780 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11781 CRTC_STEREO_DOUBLE);
11783 /* Pass our mode to the connectors and the CRTC to give them a chance to
11784 * adjust it according to limitations or connector properties, and also
11785 * a chance to reject the mode entirely.
11787 for_each_new_connector_in_state(state, connector, connector_state, i) {
11788 if (connector_state->crtc != crtc)
11791 encoder = to_intel_encoder(connector_state->best_encoder);
11792 ret = encoder->compute_config(encoder, pipe_config,
11795 if (ret != -EDEADLK)
11796 DRM_DEBUG_KMS("Encoder config failure: %d\n",
11802 /* Set default port clock if not overwritten by the encoder. Needs to be
11803 * done afterwards in case the encoder adjusts the mode. */
11804 if (!pipe_config->port_clock)
11805 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11806 * pipe_config->pixel_multiplier;
11808 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11809 if (ret == -EDEADLK)
11812 DRM_DEBUG_KMS("CRTC fixup failed\n");
11816 if (ret == RETRY) {
11817 if (WARN(!retry, "loop in pipe configuration computation\n"))
11820 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11822 goto encoder_retry;
11825 /* Dithering seems to not pass-through bits correctly when it should, so
11826 * only enable it on 6bpc panels and when its not a compliance
11827 * test requesting 6bpc video pattern.
11829 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11830 !pipe_config->dither_force_disable;
11831 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11832 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11837 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11841 if (clock1 == clock2)
11844 if (!clock1 || !clock2)
11847 diff = abs(clock1 - clock2);
11849 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11856 intel_compare_m_n(unsigned int m, unsigned int n,
11857 unsigned int m2, unsigned int n2,
11860 if (m == m2 && n == n2)
11863 if (exact || !m || !n || !m2 || !n2)
11866 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11873 } else if (n < n2) {
11883 return intel_fuzzy_clock_check(m, m2);
11887 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11888 struct intel_link_m_n *m2_n2,
11891 if (m_n->tu == m2_n2->tu &&
11892 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11893 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11894 intel_compare_m_n(m_n->link_m, m_n->link_n,
11895 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11906 intel_compare_infoframe(const union hdmi_infoframe *a,
11907 const union hdmi_infoframe *b)
11909 return memcmp(a, b, sizeof(*a)) == 0;
11913 pipe_config_infoframe_err(struct drm_i915_private *dev_priv,
11914 bool adjust, const char *name,
11915 const union hdmi_infoframe *a,
11916 const union hdmi_infoframe *b)
11919 if ((drm_debug & DRM_UT_KMS) == 0)
11922 drm_dbg(DRM_UT_KMS, "mismatch in %s infoframe", name);
11923 drm_dbg(DRM_UT_KMS, "expected:");
11924 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
11925 drm_dbg(DRM_UT_KMS, "found");
11926 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
11928 drm_err("mismatch in %s infoframe", name);
11929 drm_err("expected:");
11930 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
11932 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
11936 static void __printf(3, 4)
11937 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11939 struct va_format vaf;
11942 va_start(args, format);
11947 drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
11949 drm_err("mismatch in %s %pV", name, &vaf);
11954 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
11956 if (i915_modparams.fastboot != -1)
11957 return i915_modparams.fastboot;
11959 /* Enable fastboot by default on Skylake and newer */
11960 if (INTEL_GEN(dev_priv) >= 9)
11963 /* Enable fastboot by default on VLV and CHV */
11964 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11967 /* Disabled by default on all others */
11972 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11973 struct intel_crtc_state *current_config,
11974 struct intel_crtc_state *pipe_config,
11978 bool fixup_inherited = adjust &&
11979 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
11980 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
11982 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
11983 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
11987 #define PIPE_CONF_CHECK_X(name) do { \
11988 if (current_config->name != pipe_config->name) { \
11989 pipe_config_err(adjust, __stringify(name), \
11990 "(expected 0x%08x, found 0x%08x)\n", \
11991 current_config->name, \
11992 pipe_config->name); \
11997 #define PIPE_CONF_CHECK_I(name) do { \
11998 if (current_config->name != pipe_config->name) { \
11999 pipe_config_err(adjust, __stringify(name), \
12000 "(expected %i, found %i)\n", \
12001 current_config->name, \
12002 pipe_config->name); \
12007 #define PIPE_CONF_CHECK_BOOL(name) do { \
12008 if (current_config->name != pipe_config->name) { \
12009 pipe_config_err(adjust, __stringify(name), \
12010 "(expected %s, found %s)\n", \
12011 yesno(current_config->name), \
12012 yesno(pipe_config->name)); \
12018 * Checks state where we only read out the enabling, but not the entire
12019 * state itself (like full infoframes or ELD for audio). These states
12020 * require a full modeset on bootup to fix up.
12022 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
12023 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
12024 PIPE_CONF_CHECK_BOOL(name); \
12026 pipe_config_err(adjust, __stringify(name), \
12027 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
12028 yesno(current_config->name), \
12029 yesno(pipe_config->name)); \
12034 #define PIPE_CONF_CHECK_P(name) do { \
12035 if (current_config->name != pipe_config->name) { \
12036 pipe_config_err(adjust, __stringify(name), \
12037 "(expected %p, found %p)\n", \
12038 current_config->name, \
12039 pipe_config->name); \
12044 #define PIPE_CONF_CHECK_M_N(name) do { \
12045 if (!intel_compare_link_m_n(¤t_config->name, \
12046 &pipe_config->name,\
12048 pipe_config_err(adjust, __stringify(name), \
12049 "(expected tu %i gmch %i/%i link %i/%i, " \
12050 "found tu %i, gmch %i/%i link %i/%i)\n", \
12051 current_config->name.tu, \
12052 current_config->name.gmch_m, \
12053 current_config->name.gmch_n, \
12054 current_config->name.link_m, \
12055 current_config->name.link_n, \
12056 pipe_config->name.tu, \
12057 pipe_config->name.gmch_m, \
12058 pipe_config->name.gmch_n, \
12059 pipe_config->name.link_m, \
12060 pipe_config->name.link_n); \
12065 /* This is required for BDW+ where there is only one set of registers for
12066 * switching between high and low RR.
12067 * This macro can be used whenever a comparison has to be made between one
12068 * hw state and multiple sw state variables.
12070 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
12071 if (!intel_compare_link_m_n(¤t_config->name, \
12072 &pipe_config->name, adjust) && \
12073 !intel_compare_link_m_n(¤t_config->alt_name, \
12074 &pipe_config->name, adjust)) { \
12075 pipe_config_err(adjust, __stringify(name), \
12076 "(expected tu %i gmch %i/%i link %i/%i, " \
12077 "or tu %i gmch %i/%i link %i/%i, " \
12078 "found tu %i, gmch %i/%i link %i/%i)\n", \
12079 current_config->name.tu, \
12080 current_config->name.gmch_m, \
12081 current_config->name.gmch_n, \
12082 current_config->name.link_m, \
12083 current_config->name.link_n, \
12084 current_config->alt_name.tu, \
12085 current_config->alt_name.gmch_m, \
12086 current_config->alt_name.gmch_n, \
12087 current_config->alt_name.link_m, \
12088 current_config->alt_name.link_n, \
12089 pipe_config->name.tu, \
12090 pipe_config->name.gmch_m, \
12091 pipe_config->name.gmch_n, \
12092 pipe_config->name.link_m, \
12093 pipe_config->name.link_n); \
12098 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
12099 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12100 pipe_config_err(adjust, __stringify(name), \
12101 "(%x) (expected %i, found %i)\n", \
12103 current_config->name & (mask), \
12104 pipe_config->name & (mask)); \
12109 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
12110 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12111 pipe_config_err(adjust, __stringify(name), \
12112 "(expected %i, found %i)\n", \
12113 current_config->name, \
12114 pipe_config->name); \
12119 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
12120 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
12121 &pipe_config->infoframes.name)) { \
12122 pipe_config_infoframe_err(dev_priv, adjust, __stringify(name), \
12123 ¤t_config->infoframes.name, \
12124 &pipe_config->infoframes.name); \
12129 #define PIPE_CONF_QUIRK(quirk) \
12130 ((current_config->quirks | pipe_config->quirks) & (quirk))
12132 PIPE_CONF_CHECK_I(cpu_transcoder);
12134 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
12135 PIPE_CONF_CHECK_I(fdi_lanes);
12136 PIPE_CONF_CHECK_M_N(fdi_m_n);
12138 PIPE_CONF_CHECK_I(lane_count);
12139 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12141 if (INTEL_GEN(dev_priv) < 8) {
12142 PIPE_CONF_CHECK_M_N(dp_m_n);
12144 if (current_config->has_drrs)
12145 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12147 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12149 PIPE_CONF_CHECK_X(output_types);
12151 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12152 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12153 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12154 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12155 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12156 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12158 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12159 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12160 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12161 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12162 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12163 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12165 PIPE_CONF_CHECK_I(pixel_multiplier);
12166 PIPE_CONF_CHECK_I(output_format);
12167 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
12168 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
12169 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12170 PIPE_CONF_CHECK_BOOL(limited_color_range);
12172 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
12173 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
12174 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
12176 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
12178 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12179 DRM_MODE_FLAG_INTERLACE);
12181 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12182 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12183 DRM_MODE_FLAG_PHSYNC);
12184 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12185 DRM_MODE_FLAG_NHSYNC);
12186 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12187 DRM_MODE_FLAG_PVSYNC);
12188 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12189 DRM_MODE_FLAG_NVSYNC);
12192 PIPE_CONF_CHECK_X(gmch_pfit.control);
12193 /* pfit ratios are autocomputed by the hw on gen4+ */
12194 if (INTEL_GEN(dev_priv) < 4)
12195 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12196 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12199 * Changing the EDP transcoder input mux
12200 * (A_ONOFF vs. A_ON) requires a full modeset.
12202 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
12205 PIPE_CONF_CHECK_I(pipe_src_w);
12206 PIPE_CONF_CHECK_I(pipe_src_h);
12208 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
12209 if (current_config->pch_pfit.enabled) {
12210 PIPE_CONF_CHECK_X(pch_pfit.pos);
12211 PIPE_CONF_CHECK_X(pch_pfit.size);
12214 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12215 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
12217 PIPE_CONF_CHECK_X(gamma_mode);
12218 if (IS_CHERRYVIEW(dev_priv))
12219 PIPE_CONF_CHECK_X(cgm_mode);
12221 PIPE_CONF_CHECK_X(csc_mode);
12222 PIPE_CONF_CHECK_BOOL(gamma_enable);
12223 PIPE_CONF_CHECK_BOOL(csc_enable);
12226 PIPE_CONF_CHECK_BOOL(double_wide);
12228 PIPE_CONF_CHECK_P(shared_dpll);
12229 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12230 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12231 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12232 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12233 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12234 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12235 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12236 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12237 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12238 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
12239 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
12240 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
12241 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
12242 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
12243 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
12244 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
12245 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
12246 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
12247 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
12248 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
12249 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
12250 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
12251 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
12252 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
12253 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
12254 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
12255 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
12256 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
12257 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
12258 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
12259 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
12261 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12262 PIPE_CONF_CHECK_X(dsi_pll.div);
12264 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
12265 PIPE_CONF_CHECK_I(pipe_bpp);
12267 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12268 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12270 PIPE_CONF_CHECK_I(min_voltage_level);
12272 PIPE_CONF_CHECK_X(infoframes.enable);
12273 PIPE_CONF_CHECK_X(infoframes.gcp);
12274 PIPE_CONF_CHECK_INFOFRAME(avi);
12275 PIPE_CONF_CHECK_INFOFRAME(spd);
12276 PIPE_CONF_CHECK_INFOFRAME(hdmi);
12278 #undef PIPE_CONF_CHECK_X
12279 #undef PIPE_CONF_CHECK_I
12280 #undef PIPE_CONF_CHECK_BOOL
12281 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
12282 #undef PIPE_CONF_CHECK_P
12283 #undef PIPE_CONF_CHECK_FLAGS
12284 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12285 #undef PIPE_CONF_QUIRK
12290 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12291 const struct intel_crtc_state *pipe_config)
12293 if (pipe_config->has_pch_encoder) {
12294 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12295 &pipe_config->fdi_m_n);
12296 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12299 * FDI already provided one idea for the dotclock.
12300 * Yell if the encoder disagrees.
12302 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12303 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12304 fdi_dotclock, dotclock);
12308 static void verify_wm_state(struct drm_crtc *crtc,
12309 struct drm_crtc_state *new_state)
12311 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12312 struct skl_hw_state {
12313 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
12314 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
12315 struct skl_ddb_allocation ddb;
12316 struct skl_pipe_wm wm;
12318 struct skl_ddb_allocation *sw_ddb;
12319 struct skl_pipe_wm *sw_wm;
12320 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
12321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12322 const enum pipe pipe = intel_crtc->pipe;
12323 int plane, level, max_level = ilk_wm_max_level(dev_priv);
12325 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
12328 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
12332 skl_pipe_wm_get_hw_state(intel_crtc, &hw->wm);
12333 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
12335 skl_pipe_ddb_get_hw_state(intel_crtc, hw->ddb_y, hw->ddb_uv);
12337 skl_ddb_get_hw_state(dev_priv, &hw->ddb);
12338 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12340 if (INTEL_GEN(dev_priv) >= 11 &&
12341 hw->ddb.enabled_slices != sw_ddb->enabled_slices)
12342 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
12343 sw_ddb->enabled_slices,
12344 hw->ddb.enabled_slices);
12347 for_each_universal_plane(dev_priv, pipe, plane) {
12348 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12350 hw_plane_wm = &hw->wm.planes[plane];
12351 sw_plane_wm = &sw_wm->planes[plane];
12354 for (level = 0; level <= max_level; level++) {
12355 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12356 &sw_plane_wm->wm[level]))
12359 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12360 pipe_name(pipe), plane + 1, level,
12361 sw_plane_wm->wm[level].plane_en,
12362 sw_plane_wm->wm[level].plane_res_b,
12363 sw_plane_wm->wm[level].plane_res_l,
12364 hw_plane_wm->wm[level].plane_en,
12365 hw_plane_wm->wm[level].plane_res_b,
12366 hw_plane_wm->wm[level].plane_res_l);
12369 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12370 &sw_plane_wm->trans_wm)) {
12371 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12372 pipe_name(pipe), plane + 1,
12373 sw_plane_wm->trans_wm.plane_en,
12374 sw_plane_wm->trans_wm.plane_res_b,
12375 sw_plane_wm->trans_wm.plane_res_l,
12376 hw_plane_wm->trans_wm.plane_en,
12377 hw_plane_wm->trans_wm.plane_res_b,
12378 hw_plane_wm->trans_wm.plane_res_l);
12382 hw_ddb_entry = &hw->ddb_y[plane];
12383 sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[plane];
12385 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12386 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12387 pipe_name(pipe), plane + 1,
12388 sw_ddb_entry->start, sw_ddb_entry->end,
12389 hw_ddb_entry->start, hw_ddb_entry->end);
12395 * If the cursor plane isn't active, we may not have updated it's ddb
12396 * allocation. In that case since the ddb allocation will be updated
12397 * once the plane becomes visible, we can skip this check
12400 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12402 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
12403 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
12406 for (level = 0; level <= max_level; level++) {
12407 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12408 &sw_plane_wm->wm[level]))
12411 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12412 pipe_name(pipe), level,
12413 sw_plane_wm->wm[level].plane_en,
12414 sw_plane_wm->wm[level].plane_res_b,
12415 sw_plane_wm->wm[level].plane_res_l,
12416 hw_plane_wm->wm[level].plane_en,
12417 hw_plane_wm->wm[level].plane_res_b,
12418 hw_plane_wm->wm[level].plane_res_l);
12421 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12422 &sw_plane_wm->trans_wm)) {
12423 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12425 sw_plane_wm->trans_wm.plane_en,
12426 sw_plane_wm->trans_wm.plane_res_b,
12427 sw_plane_wm->trans_wm.plane_res_l,
12428 hw_plane_wm->trans_wm.plane_en,
12429 hw_plane_wm->trans_wm.plane_res_b,
12430 hw_plane_wm->trans_wm.plane_res_l);
12434 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
12435 sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[PLANE_CURSOR];
12437 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12438 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12440 sw_ddb_entry->start, sw_ddb_entry->end,
12441 hw_ddb_entry->start, hw_ddb_entry->end);
12449 verify_connector_state(struct drm_device *dev,
12450 struct drm_atomic_state *state,
12451 struct drm_crtc *crtc)
12453 struct drm_connector *connector;
12454 struct drm_connector_state *new_conn_state;
12457 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
12458 struct drm_encoder *encoder = connector->encoder;
12459 struct drm_crtc_state *crtc_state = NULL;
12461 if (new_conn_state->crtc != crtc)
12465 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
12467 intel_connector_verify_state(crtc_state, new_conn_state);
12469 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
12470 "connector's atomic encoder doesn't match legacy encoder\n");
12475 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
12477 struct intel_encoder *encoder;
12478 struct drm_connector *connector;
12479 struct drm_connector_state *old_conn_state, *new_conn_state;
12482 for_each_intel_encoder(dev, encoder) {
12483 bool enabled = false, found = false;
12486 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12487 encoder->base.base.id,
12488 encoder->base.name);
12490 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
12491 new_conn_state, i) {
12492 if (old_conn_state->best_encoder == &encoder->base)
12495 if (new_conn_state->best_encoder != &encoder->base)
12497 found = enabled = true;
12499 I915_STATE_WARN(new_conn_state->crtc !=
12500 encoder->base.crtc,
12501 "connector's crtc doesn't match encoder crtc\n");
12507 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12508 "encoder's enabled state mismatch "
12509 "(expected %i, found %i)\n",
12510 !!encoder->base.crtc, enabled);
12512 if (!encoder->base.crtc) {
12515 active = encoder->get_hw_state(encoder, &pipe);
12516 I915_STATE_WARN(active,
12517 "encoder detached but still enabled on pipe %c.\n",
12524 verify_crtc_state(struct drm_crtc *crtc,
12525 struct drm_crtc_state *old_crtc_state,
12526 struct drm_crtc_state *new_crtc_state)
12528 struct drm_device *dev = crtc->dev;
12529 struct drm_i915_private *dev_priv = to_i915(dev);
12530 struct intel_encoder *encoder;
12531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12532 struct intel_crtc_state *pipe_config, *sw_config;
12533 struct drm_atomic_state *old_state;
12536 old_state = old_crtc_state->state;
12537 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12538 pipe_config = to_intel_crtc_state(old_crtc_state);
12539 memset(pipe_config, 0, sizeof(*pipe_config));
12540 pipe_config->base.crtc = crtc;
12541 pipe_config->base.state = old_state;
12543 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12545 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12547 /* we keep both pipes enabled on 830 */
12548 if (IS_I830(dev_priv))
12549 active = new_crtc_state->active;
12551 I915_STATE_WARN(new_crtc_state->active != active,
12552 "crtc active state doesn't match with hw state "
12553 "(expected %i, found %i)\n", new_crtc_state->active, active);
12555 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12556 "transitional active state does not match atomic hw state "
12557 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12559 for_each_encoder_on_crtc(dev, crtc, encoder) {
12562 active = encoder->get_hw_state(encoder, &pipe);
12563 I915_STATE_WARN(active != new_crtc_state->active,
12564 "[ENCODER:%i] active %i with crtc active %i\n",
12565 encoder->base.base.id, active, new_crtc_state->active);
12567 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12568 "Encoder connected to wrong pipe %c\n",
12572 encoder->get_config(encoder, pipe_config);
12575 intel_crtc_compute_pixel_rate(pipe_config);
12577 if (!new_crtc_state->active)
12580 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12582 sw_config = to_intel_crtc_state(new_crtc_state);
12583 if (!intel_pipe_config_compare(dev_priv, sw_config,
12584 pipe_config, false)) {
12585 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12586 intel_dump_pipe_config(intel_crtc, pipe_config,
12588 intel_dump_pipe_config(intel_crtc, sw_config,
12594 intel_verify_planes(struct intel_atomic_state *state)
12596 struct intel_plane *plane;
12597 const struct intel_plane_state *plane_state;
12600 for_each_new_intel_plane_in_state(state, plane,
12602 assert_plane(plane, plane_state->slave ||
12603 plane_state->base.visible);
12607 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12608 struct intel_shared_dpll *pll,
12609 struct drm_crtc *crtc,
12610 struct drm_crtc_state *new_state)
12612 struct intel_dpll_hw_state dpll_hw_state;
12613 unsigned int crtc_mask;
12616 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12618 DRM_DEBUG_KMS("%s\n", pll->info->name);
12620 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
12622 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
12623 I915_STATE_WARN(!pll->on && pll->active_mask,
12624 "pll in active use but not on in sw tracking\n");
12625 I915_STATE_WARN(pll->on && !pll->active_mask,
12626 "pll is on but not used by any active crtc\n");
12627 I915_STATE_WARN(pll->on != active,
12628 "pll on state mismatch (expected %i, found %i)\n",
12633 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12634 "more active pll users than references: %x vs %x\n",
12635 pll->active_mask, pll->state.crtc_mask);
12640 crtc_mask = drm_crtc_mask(crtc);
12642 if (new_state->active)
12643 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12644 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12645 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12647 I915_STATE_WARN(pll->active_mask & crtc_mask,
12648 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12649 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12651 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12652 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12653 crtc_mask, pll->state.crtc_mask);
12655 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12657 sizeof(dpll_hw_state)),
12658 "pll hw state mismatch\n");
12662 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12663 struct drm_crtc_state *old_crtc_state,
12664 struct drm_crtc_state *new_crtc_state)
12666 struct drm_i915_private *dev_priv = to_i915(dev);
12667 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12668 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12670 if (new_state->shared_dpll)
12671 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12673 if (old_state->shared_dpll &&
12674 old_state->shared_dpll != new_state->shared_dpll) {
12675 unsigned int crtc_mask = drm_crtc_mask(crtc);
12676 struct intel_shared_dpll *pll = old_state->shared_dpll;
12678 I915_STATE_WARN(pll->active_mask & crtc_mask,
12679 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12680 pipe_name(drm_crtc_index(crtc)));
12681 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12682 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12683 pipe_name(drm_crtc_index(crtc)));
12688 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12689 struct drm_atomic_state *state,
12690 struct drm_crtc_state *old_state,
12691 struct drm_crtc_state *new_state)
12693 if (!needs_modeset(new_state) &&
12694 !to_intel_crtc_state(new_state)->update_pipe)
12697 verify_wm_state(crtc, new_state);
12698 verify_connector_state(crtc->dev, state, crtc);
12699 verify_crtc_state(crtc, old_state, new_state);
12700 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12704 verify_disabled_dpll_state(struct drm_device *dev)
12706 struct drm_i915_private *dev_priv = to_i915(dev);
12709 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12710 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12714 intel_modeset_verify_disabled(struct drm_device *dev,
12715 struct drm_atomic_state *state)
12717 verify_encoder_state(dev, state);
12718 verify_connector_state(dev, state, NULL);
12719 verify_disabled_dpll_state(dev);
12722 static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
12724 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
12725 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12728 * The scanline counter increments at the leading edge of hsync.
12730 * On most platforms it starts counting from vtotal-1 on the
12731 * first active line. That means the scanline counter value is
12732 * always one less than what we would expect. Ie. just after
12733 * start of vblank, which also occurs at start of hsync (on the
12734 * last active line), the scanline counter will read vblank_start-1.
12736 * On gen2 the scanline counter starts counting from 1 instead
12737 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12738 * to keep the value positive), instead of adding one.
12740 * On HSW+ the behaviour of the scanline counter depends on the output
12741 * type. For DP ports it behaves like most other platforms, but on HDMI
12742 * there's an extra 1 line difference. So we need to add two instead of
12743 * one to the value.
12745 * On VLV/CHV DSI the scanline counter would appear to increment
12746 * approx. 1/3 of a scanline before start of vblank. Unfortunately
12747 * that means we can't tell whether we're in vblank or not while
12748 * we're on that particular line. We must still set scanline_offset
12749 * to 1 so that the vblank timestamps come out correct when we query
12750 * the scanline counter from within the vblank interrupt handler.
12751 * However if queried just before the start of vblank we'll get an
12752 * answer that's slightly in the future.
12754 if (IS_GEN(dev_priv, 2)) {
12755 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
12758 vtotal = adjusted_mode->crtc_vtotal;
12759 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12762 crtc->scanline_offset = vtotal - 1;
12763 } else if (HAS_DDI(dev_priv) &&
12764 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
12765 crtc->scanline_offset = 2;
12767 crtc->scanline_offset = 1;
12770 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12772 struct drm_device *dev = state->dev;
12773 struct drm_i915_private *dev_priv = to_i915(dev);
12774 struct drm_crtc *crtc;
12775 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12778 if (!dev_priv->display.crtc_compute_clock)
12781 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12783 struct intel_shared_dpll *old_dpll =
12784 to_intel_crtc_state(old_crtc_state)->shared_dpll;
12786 if (!needs_modeset(new_crtc_state))
12789 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12794 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12799 * This implements the workaround described in the "notes" section of the mode
12800 * set sequence documentation. When going from no pipes or single pipe to
12801 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12802 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12804 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12806 struct drm_crtc_state *crtc_state;
12807 struct intel_crtc *intel_crtc;
12808 struct drm_crtc *crtc;
12809 struct intel_crtc_state *first_crtc_state = NULL;
12810 struct intel_crtc_state *other_crtc_state = NULL;
12811 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12814 /* look at all crtc's that are going to be enabled in during modeset */
12815 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12816 intel_crtc = to_intel_crtc(crtc);
12818 if (!crtc_state->active || !needs_modeset(crtc_state))
12821 if (first_crtc_state) {
12822 other_crtc_state = to_intel_crtc_state(crtc_state);
12825 first_crtc_state = to_intel_crtc_state(crtc_state);
12826 first_pipe = intel_crtc->pipe;
12830 /* No workaround needed? */
12831 if (!first_crtc_state)
12834 /* w/a possibly needed, check how many crtc's are already enabled. */
12835 for_each_intel_crtc(state->dev, intel_crtc) {
12836 struct intel_crtc_state *pipe_config;
12838 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12839 if (IS_ERR(pipe_config))
12840 return PTR_ERR(pipe_config);
12842 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12844 if (!pipe_config->base.active ||
12845 needs_modeset(&pipe_config->base))
12848 /* 2 or more enabled crtcs means no need for w/a */
12849 if (enabled_pipe != INVALID_PIPE)
12852 enabled_pipe = intel_crtc->pipe;
12855 if (enabled_pipe != INVALID_PIPE)
12856 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12857 else if (other_crtc_state)
12858 other_crtc_state->hsw_workaround_pipe = first_pipe;
12863 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12865 struct drm_crtc *crtc;
12867 /* Add all pipes to the state */
12868 for_each_crtc(state->dev, crtc) {
12869 struct drm_crtc_state *crtc_state;
12871 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12872 if (IS_ERR(crtc_state))
12873 return PTR_ERR(crtc_state);
12879 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12881 struct drm_crtc *crtc;
12884 * Add all pipes to the state, and force
12885 * a modeset on all the active ones.
12887 for_each_crtc(state->dev, crtc) {
12888 struct drm_crtc_state *crtc_state;
12891 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12892 if (IS_ERR(crtc_state))
12893 return PTR_ERR(crtc_state);
12895 if (!crtc_state->active || needs_modeset(crtc_state))
12898 crtc_state->mode_changed = true;
12900 ret = drm_atomic_add_affected_connectors(state, crtc);
12904 ret = drm_atomic_add_affected_planes(state, crtc);
12912 static int intel_modeset_checks(struct drm_atomic_state *state)
12914 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12915 struct drm_i915_private *dev_priv = to_i915(state->dev);
12916 struct drm_crtc *crtc;
12917 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12920 if (!check_digital_port_conflicts(state)) {
12921 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12925 /* keep the current setting */
12926 if (!intel_state->cdclk.force_min_cdclk_changed)
12927 intel_state->cdclk.force_min_cdclk =
12928 dev_priv->cdclk.force_min_cdclk;
12930 intel_state->modeset = true;
12931 intel_state->active_crtcs = dev_priv->active_crtcs;
12932 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12933 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12934 intel_state->cdclk.pipe = INVALID_PIPE;
12936 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12937 if (new_crtc_state->active)
12938 intel_state->active_crtcs |= 1 << i;
12940 intel_state->active_crtcs &= ~(1 << i);
12942 if (old_crtc_state->active != new_crtc_state->active)
12943 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12947 * See if the config requires any additional preparation, e.g.
12948 * to adjust global state with pipes off. We need to do this
12949 * here so we can get the modeset_pipe updated config for the new
12950 * mode set on this crtc. For other crtcs we need to use the
12951 * adjusted_mode bits in the crtc directly.
12953 if (dev_priv->display.modeset_calc_cdclk) {
12956 ret = dev_priv->display.modeset_calc_cdclk(state);
12961 * Writes to dev_priv->cdclk.logical must protected by
12962 * holding all the crtc locks, even if we don't end up
12963 * touching the hardware
12965 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
12966 &intel_state->cdclk.logical)) {
12967 ret = intel_lock_all_pipes(state);
12972 if (is_power_of_2(intel_state->active_crtcs)) {
12973 struct drm_crtc *crtc;
12974 struct drm_crtc_state *crtc_state;
12976 pipe = ilog2(intel_state->active_crtcs);
12977 crtc = &intel_get_crtc_for_pipe(dev_priv, pipe)->base;
12978 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
12979 if (crtc_state && needs_modeset(crtc_state))
12980 pipe = INVALID_PIPE;
12982 pipe = INVALID_PIPE;
12985 /* All pipes must be switched off while we change the cdclk. */
12986 if (pipe != INVALID_PIPE &&
12987 intel_cdclk_needs_cd2x_update(dev_priv,
12988 &dev_priv->cdclk.actual,
12989 &intel_state->cdclk.actual)) {
12990 ret = intel_lock_all_pipes(state);
12994 intel_state->cdclk.pipe = pipe;
12995 } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
12996 &intel_state->cdclk.actual)) {
12997 ret = intel_modeset_all_pipes(state);
13001 intel_state->cdclk.pipe = INVALID_PIPE;
13004 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
13005 intel_state->cdclk.logical.cdclk,
13006 intel_state->cdclk.actual.cdclk);
13007 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
13008 intel_state->cdclk.logical.voltage_level,
13009 intel_state->cdclk.actual.voltage_level);
13012 intel_modeset_clear_plls(state);
13014 if (IS_HASWELL(dev_priv))
13015 return haswell_mode_set_planes_workaround(state);
13021 * Handle calculation of various watermark data at the end of the atomic check
13022 * phase. The code here should be run after the per-crtc and per-plane 'check'
13023 * handlers to ensure that all derived state has been updated.
13025 static int calc_watermark_data(struct intel_atomic_state *state)
13027 struct drm_device *dev = state->base.dev;
13028 struct drm_i915_private *dev_priv = to_i915(dev);
13030 /* Is there platform-specific watermark information to calculate? */
13031 if (dev_priv->display.compute_global_watermarks)
13032 return dev_priv->display.compute_global_watermarks(state);
13038 * intel_atomic_check - validate state object
13040 * @state: state to validate
13042 static int intel_atomic_check(struct drm_device *dev,
13043 struct drm_atomic_state *state)
13045 struct drm_i915_private *dev_priv = to_i915(dev);
13046 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13047 struct drm_crtc *crtc;
13048 struct drm_crtc_state *old_crtc_state, *crtc_state;
13050 bool any_ms = intel_state->cdclk.force_min_cdclk_changed;
13052 /* Catch I915_MODE_FLAG_INHERITED */
13053 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
13055 if (crtc_state->mode.private_flags !=
13056 old_crtc_state->mode.private_flags)
13057 crtc_state->mode_changed = true;
13060 ret = drm_atomic_helper_check_modeset(dev, state);
13064 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
13065 struct intel_crtc_state *pipe_config =
13066 to_intel_crtc_state(crtc_state);
13068 if (!needs_modeset(crtc_state))
13071 if (!crtc_state->enable) {
13076 ret = intel_modeset_pipe_config(crtc, pipe_config);
13077 if (ret == -EDEADLK)
13080 intel_dump_pipe_config(to_intel_crtc(crtc),
13081 pipe_config, "[failed]");
13085 if (intel_pipe_config_compare(dev_priv,
13086 to_intel_crtc_state(old_crtc_state),
13087 pipe_config, true)) {
13088 crtc_state->mode_changed = false;
13089 pipe_config->update_pipe = true;
13092 if (needs_modeset(crtc_state))
13095 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13096 needs_modeset(crtc_state) ?
13097 "[modeset]" : "[fastset]");
13100 ret = drm_dp_mst_atomic_check(state);
13105 ret = intel_modeset_checks(state);
13110 intel_state->cdclk.logical = dev_priv->cdclk.logical;
13113 ret = icl_add_linked_planes(intel_state);
13117 ret = drm_atomic_helper_check_planes(dev, state);
13121 intel_fbc_choose_crtc(dev_priv, intel_state);
13122 return calc_watermark_data(intel_state);
13125 static int intel_atomic_prepare_commit(struct drm_device *dev,
13126 struct drm_atomic_state *state)
13128 return drm_atomic_helper_prepare_planes(dev, state);
13131 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13133 struct drm_device *dev = crtc->base.dev;
13134 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
13136 if (!vblank->max_vblank_count)
13137 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
13139 return dev->driver->get_vblank_counter(dev, crtc->pipe);
13142 static void intel_update_crtc(struct drm_crtc *crtc,
13143 struct drm_atomic_state *state,
13144 struct drm_crtc_state *old_crtc_state,
13145 struct drm_crtc_state *new_crtc_state)
13147 struct drm_device *dev = crtc->dev;
13148 struct drm_i915_private *dev_priv = to_i915(dev);
13149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13150 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
13151 bool modeset = needs_modeset(new_crtc_state);
13152 struct intel_plane_state *new_plane_state =
13153 intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
13154 to_intel_plane(crtc->primary));
13157 update_scanline_offset(pipe_config);
13158 dev_priv->display.crtc_enable(pipe_config, state);
13160 /* vblanks work again, re-enable pipe CRC. */
13161 intel_crtc_enable_pipe_crc(intel_crtc);
13163 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
13166 if (pipe_config->update_pipe)
13167 intel_encoders_update_pipe(crtc, pipe_config, state);
13170 if (pipe_config->update_pipe && !pipe_config->enable_fbc)
13171 intel_fbc_disable(intel_crtc);
13172 else if (new_plane_state)
13173 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
13175 intel_begin_crtc_commit(to_intel_atomic_state(state), intel_crtc);
13177 if (INTEL_GEN(dev_priv) >= 9)
13178 skl_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
13180 i9xx_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
13182 intel_finish_crtc_commit(to_intel_atomic_state(state), intel_crtc);
13185 static void intel_update_crtcs(struct drm_atomic_state *state)
13187 struct drm_crtc *crtc;
13188 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13191 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13192 if (!new_crtc_state->active)
13195 intel_update_crtc(crtc, state, old_crtc_state,
13200 static void skl_update_crtcs(struct drm_atomic_state *state)
13202 struct drm_i915_private *dev_priv = to_i915(state->dev);
13203 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13204 struct drm_crtc *crtc;
13205 struct intel_crtc *intel_crtc;
13206 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13207 struct intel_crtc_state *cstate;
13208 unsigned int updated = 0;
13212 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
13213 u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
13214 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
13216 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
13217 /* ignore allocations for crtc's that have been turned off. */
13218 if (new_crtc_state->active)
13219 entries[i] = to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
13221 /* If 2nd DBuf slice required, enable it here */
13222 if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
13223 icl_dbuf_slices_update(dev_priv, required_slices);
13226 * Whenever the number of active pipes changes, we need to make sure we
13227 * update the pipes in the right order so that their ddb allocations
13228 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
13229 * cause pipe underruns and other bad stuff.
13234 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13235 bool vbl_wait = false;
13236 unsigned int cmask = drm_crtc_mask(crtc);
13238 intel_crtc = to_intel_crtc(crtc);
13239 cstate = to_intel_crtc_state(new_crtc_state);
13240 pipe = intel_crtc->pipe;
13242 if (updated & cmask || !cstate->base.active)
13245 if (skl_ddb_allocation_overlaps(&cstate->wm.skl.ddb,
13247 INTEL_INFO(dev_priv)->num_pipes, i))
13251 entries[i] = cstate->wm.skl.ddb;
13254 * If this is an already active pipe, it's DDB changed,
13255 * and this isn't the last pipe that needs updating
13256 * then we need to wait for a vblank to pass for the
13257 * new ddb allocation to take effect.
13259 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
13260 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
13261 !new_crtc_state->active_changed &&
13262 intel_state->wm_results.dirty_pipes != updated)
13265 intel_update_crtc(crtc, state, old_crtc_state,
13269 intel_wait_for_vblank(dev_priv, pipe);
13273 } while (progress);
13275 /* If 2nd DBuf slice is no more required disable it */
13276 if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
13277 icl_dbuf_slices_update(dev_priv, required_slices);
13280 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
13282 struct intel_atomic_state *state, *next;
13283 struct llist_node *freed;
13285 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
13286 llist_for_each_entry_safe(state, next, freed, freed)
13287 drm_atomic_state_put(&state->base);
13290 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
13292 struct drm_i915_private *dev_priv =
13293 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
13295 intel_atomic_helper_free_state(dev_priv);
13298 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
13300 struct wait_queue_entry wait_fence, wait_reset;
13301 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
13303 init_wait_entry(&wait_fence, 0);
13304 init_wait_entry(&wait_reset, 0);
13306 prepare_to_wait(&intel_state->commit_ready.wait,
13307 &wait_fence, TASK_UNINTERRUPTIBLE);
13308 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
13309 &wait_reset, TASK_UNINTERRUPTIBLE);
13312 if (i915_sw_fence_done(&intel_state->commit_ready)
13313 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
13318 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
13319 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
13322 static void intel_atomic_cleanup_work(struct work_struct *work)
13324 struct drm_atomic_state *state =
13325 container_of(work, struct drm_atomic_state, commit_work);
13326 struct drm_i915_private *i915 = to_i915(state->dev);
13328 drm_atomic_helper_cleanup_planes(&i915->drm, state);
13329 drm_atomic_helper_commit_cleanup_done(state);
13330 drm_atomic_state_put(state);
13332 intel_atomic_helper_free_state(i915);
13335 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13337 struct drm_device *dev = state->dev;
13338 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13339 struct drm_i915_private *dev_priv = to_i915(dev);
13340 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13341 struct intel_crtc_state *new_intel_crtc_state, *old_intel_crtc_state;
13342 struct drm_crtc *crtc;
13343 struct intel_crtc *intel_crtc;
13344 u64 put_domains[I915_MAX_PIPES] = {};
13345 intel_wakeref_t wakeref = 0;
13348 intel_atomic_commit_fence_wait(intel_state);
13350 drm_atomic_helper_wait_for_dependencies(state);
13352 if (intel_state->modeset)
13353 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13355 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13356 old_intel_crtc_state = to_intel_crtc_state(old_crtc_state);
13357 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13358 intel_crtc = to_intel_crtc(crtc);
13360 if (needs_modeset(new_crtc_state) ||
13361 to_intel_crtc_state(new_crtc_state)->update_pipe) {
13363 put_domains[intel_crtc->pipe] =
13364 modeset_get_crtc_power_domains(crtc,
13365 new_intel_crtc_state);
13368 if (!needs_modeset(new_crtc_state))
13371 intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state);
13373 if (old_crtc_state->active) {
13374 intel_crtc_disable_planes(intel_state, intel_crtc);
13377 * We need to disable pipe CRC before disabling the pipe,
13378 * or we race against vblank off.
13380 intel_crtc_disable_pipe_crc(intel_crtc);
13382 dev_priv->display.crtc_disable(old_intel_crtc_state, state);
13383 intel_crtc->active = false;
13384 intel_fbc_disable(intel_crtc);
13385 intel_disable_shared_dpll(old_intel_crtc_state);
13388 * Underruns don't always raise
13389 * interrupts, so check manually.
13391 intel_check_cpu_fifo_underruns(dev_priv);
13392 intel_check_pch_fifo_underruns(dev_priv);
13394 /* FIXME unify this for all platforms */
13395 if (!new_crtc_state->active &&
13396 !HAS_GMCH(dev_priv) &&
13397 dev_priv->display.initial_watermarks)
13398 dev_priv->display.initial_watermarks(intel_state,
13399 new_intel_crtc_state);
13403 /* FIXME: Eventually get rid of our intel_crtc->config pointer */
13404 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
13405 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
13407 if (intel_state->modeset) {
13408 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13410 intel_set_cdclk_pre_plane_update(dev_priv,
13411 &intel_state->cdclk.actual,
13412 &dev_priv->cdclk.actual,
13413 intel_state->cdclk.pipe);
13416 * SKL workaround: bspec recommends we disable the SAGV when we
13417 * have more then one pipe enabled
13419 if (!intel_can_enable_sagv(state))
13420 intel_disable_sagv(dev_priv);
13422 intel_modeset_verify_disabled(dev, state);
13425 /* Complete the events for pipes that have now been disabled */
13426 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13427 bool modeset = needs_modeset(new_crtc_state);
13429 /* Complete events for now disable pipes here. */
13430 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
13431 spin_lock_irq(&dev->event_lock);
13432 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
13433 spin_unlock_irq(&dev->event_lock);
13435 new_crtc_state->event = NULL;
13439 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13440 dev_priv->display.update_crtcs(state);
13442 if (intel_state->modeset)
13443 intel_set_cdclk_post_plane_update(dev_priv,
13444 &intel_state->cdclk.actual,
13445 &dev_priv->cdclk.actual,
13446 intel_state->cdclk.pipe);
13448 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13449 * already, but still need the state for the delayed optimization. To
13451 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13452 * - schedule that vblank worker _before_ calling hw_done
13453 * - at the start of commit_tail, cancel it _synchrously
13454 * - switch over to the vblank wait helper in the core after that since
13455 * we don't need out special handling any more.
13457 drm_atomic_helper_wait_for_flip_done(dev, state);
13459 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13460 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13462 if (new_crtc_state->active &&
13463 !needs_modeset(new_crtc_state) &&
13464 (new_intel_crtc_state->base.color_mgmt_changed ||
13465 new_intel_crtc_state->update_pipe))
13466 intel_color_load_luts(new_intel_crtc_state);
13470 * Now that the vblank has passed, we can go ahead and program the
13471 * optimal watermarks on platforms that need two-step watermark
13474 * TODO: Move this (and other cleanup) to an async worker eventually.
13476 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13477 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13479 if (dev_priv->display.optimize_watermarks)
13480 dev_priv->display.optimize_watermarks(intel_state,
13481 new_intel_crtc_state);
13484 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13485 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13487 if (put_domains[i])
13488 modeset_put_power_domains(dev_priv, put_domains[i]);
13490 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
13493 if (intel_state->modeset)
13494 intel_verify_planes(intel_state);
13496 if (intel_state->modeset && intel_can_enable_sagv(state))
13497 intel_enable_sagv(dev_priv);
13499 drm_atomic_helper_commit_hw_done(state);
13501 if (intel_state->modeset) {
13502 /* As one of the primary mmio accessors, KMS has a high
13503 * likelihood of triggering bugs in unclaimed access. After we
13504 * finish modesetting, see if an error has been flagged, and if
13505 * so enable debugging for the next modeset - and hope we catch
13508 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
13509 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
13513 * Defer the cleanup of the old state to a separate worker to not
13514 * impede the current task (userspace for blocking modesets) that
13515 * are executed inline. For out-of-line asynchronous modesets/flips,
13516 * deferring to a new worker seems overkill, but we would place a
13517 * schedule point (cond_resched()) here anyway to keep latencies
13520 INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);
13521 queue_work(system_highpri_wq, &state->commit_work);
13524 static void intel_atomic_commit_work(struct work_struct *work)
13526 struct drm_atomic_state *state =
13527 container_of(work, struct drm_atomic_state, commit_work);
13529 intel_atomic_commit_tail(state);
13532 static int __i915_sw_fence_call
13533 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13534 enum i915_sw_fence_notify notify)
13536 struct intel_atomic_state *state =
13537 container_of(fence, struct intel_atomic_state, commit_ready);
13540 case FENCE_COMPLETE:
13541 /* we do blocking waits in the worker, nothing to do here */
13545 struct intel_atomic_helper *helper =
13546 &to_i915(state->base.dev)->atomic_helper;
13548 if (llist_add(&state->freed, &helper->free_list))
13549 schedule_work(&helper->free_work);
13554 return NOTIFY_DONE;
13557 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13559 struct drm_plane_state *old_plane_state, *new_plane_state;
13560 struct drm_plane *plane;
13563 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13564 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13565 intel_fb_obj(new_plane_state->fb),
13566 to_intel_plane(plane)->frontbuffer_bit);
13570 * intel_atomic_commit - commit validated state object
13572 * @state: the top-level driver state object
13573 * @nonblock: nonblocking commit
13575 * This function commits a top-level state object that has been validated
13576 * with drm_atomic_helper_check().
13579 * Zero for success or -errno.
13581 static int intel_atomic_commit(struct drm_device *dev,
13582 struct drm_atomic_state *state,
13585 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13586 struct drm_i915_private *dev_priv = to_i915(dev);
13589 drm_atomic_state_get(state);
13590 i915_sw_fence_init(&intel_state->commit_ready,
13591 intel_atomic_commit_ready);
13594 * The intel_legacy_cursor_update() fast path takes care
13595 * of avoiding the vblank waits for simple cursor
13596 * movement and flips. For cursor on/off and size changes,
13597 * we want to perform the vblank waits so that watermark
13598 * updates happen during the correct frames. Gen9+ have
13599 * double buffered watermarks and so shouldn't need this.
13601 * Unset state->legacy_cursor_update before the call to
13602 * drm_atomic_helper_setup_commit() because otherwise
13603 * drm_atomic_helper_wait_for_flip_done() is a noop and
13604 * we get FIFO underruns because we didn't wait
13607 * FIXME doing watermarks and fb cleanup from a vblank worker
13608 * (assuming we had any) would solve these problems.
13610 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
13611 struct intel_crtc_state *new_crtc_state;
13612 struct intel_crtc *crtc;
13615 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
13616 if (new_crtc_state->wm.need_postvbl_update ||
13617 new_crtc_state->update_wm_post)
13618 state->legacy_cursor_update = false;
13621 ret = intel_atomic_prepare_commit(dev, state);
13623 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13624 i915_sw_fence_commit(&intel_state->commit_ready);
13628 ret = drm_atomic_helper_setup_commit(state, nonblock);
13630 ret = drm_atomic_helper_swap_state(state, true);
13633 i915_sw_fence_commit(&intel_state->commit_ready);
13635 drm_atomic_helper_cleanup_planes(dev, state);
13638 dev_priv->wm.distrust_bios_wm = false;
13639 intel_shared_dpll_swap_state(state);
13640 intel_atomic_track_fbs(state);
13642 if (intel_state->modeset) {
13643 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
13644 sizeof(intel_state->min_cdclk));
13645 memcpy(dev_priv->min_voltage_level,
13646 intel_state->min_voltage_level,
13647 sizeof(intel_state->min_voltage_level));
13648 dev_priv->active_crtcs = intel_state->active_crtcs;
13649 dev_priv->cdclk.force_min_cdclk =
13650 intel_state->cdclk.force_min_cdclk;
13652 intel_cdclk_swap_state(intel_state);
13655 drm_atomic_state_get(state);
13656 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13658 i915_sw_fence_commit(&intel_state->commit_ready);
13659 if (nonblock && intel_state->modeset) {
13660 queue_work(dev_priv->modeset_wq, &state->commit_work);
13661 } else if (nonblock) {
13662 queue_work(system_unbound_wq, &state->commit_work);
13664 if (intel_state->modeset)
13665 flush_workqueue(dev_priv->modeset_wq);
13666 intel_atomic_commit_tail(state);
13672 static const struct drm_crtc_funcs intel_crtc_funcs = {
13673 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13674 .set_config = drm_atomic_helper_set_config,
13675 .destroy = intel_crtc_destroy,
13676 .page_flip = drm_atomic_helper_page_flip,
13677 .atomic_duplicate_state = intel_crtc_duplicate_state,
13678 .atomic_destroy_state = intel_crtc_destroy_state,
13679 .set_crc_source = intel_crtc_set_crc_source,
13680 .verify_crc_source = intel_crtc_verify_crc_source,
13681 .get_crc_sources = intel_crtc_get_crc_sources,
13684 struct wait_rps_boost {
13685 struct wait_queue_entry wait;
13687 struct drm_crtc *crtc;
13688 struct i915_request *request;
13691 static int do_rps_boost(struct wait_queue_entry *_wait,
13692 unsigned mode, int sync, void *key)
13694 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
13695 struct i915_request *rq = wait->request;
13698 * If we missed the vblank, but the request is already running it
13699 * is reasonable to assume that it will complete before the next
13700 * vblank without our intervention, so leave RPS alone.
13702 if (!i915_request_started(rq))
13703 gen6_rps_boost(rq);
13704 i915_request_put(rq);
13706 drm_crtc_vblank_put(wait->crtc);
13708 list_del(&wait->wait.entry);
13713 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
13714 struct dma_fence *fence)
13716 struct wait_rps_boost *wait;
13718 if (!dma_fence_is_i915(fence))
13721 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
13724 if (drm_crtc_vblank_get(crtc))
13727 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
13729 drm_crtc_vblank_put(crtc);
13733 wait->request = to_request(dma_fence_get(fence));
13736 wait->wait.func = do_rps_boost;
13737 wait->wait.flags = 0;
13739 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
13742 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
13744 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
13745 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13746 struct drm_framebuffer *fb = plane_state->base.fb;
13747 struct i915_vma *vma;
13749 if (plane->id == PLANE_CURSOR &&
13750 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
13751 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13752 const int align = intel_cursor_alignment(dev_priv);
13755 err = i915_gem_object_attach_phys(obj, align);
13760 vma = intel_pin_and_fence_fb_obj(fb,
13761 &plane_state->view,
13762 intel_plane_uses_fence(plane_state),
13763 &plane_state->flags);
13765 return PTR_ERR(vma);
13767 plane_state->vma = vma;
13772 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
13774 struct i915_vma *vma;
13776 vma = fetch_and_zero(&old_plane_state->vma);
13778 intel_unpin_fb_vma(vma, old_plane_state->flags);
13781 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
13783 struct i915_sched_attr attr = {
13784 .priority = I915_PRIORITY_DISPLAY,
13787 i915_gem_object_wait_priority(obj, 0, &attr);
13791 * intel_prepare_plane_fb - Prepare fb for usage on plane
13792 * @plane: drm plane to prepare for
13793 * @new_state: the plane state being prepared
13795 * Prepares a framebuffer for usage on a display plane. Generally this
13796 * involves pinning the underlying object and updating the frontbuffer tracking
13797 * bits. Some older platforms need special physical address handling for
13800 * Must be called with struct_mutex held.
13802 * Returns 0 on success, negative error code on failure.
13805 intel_prepare_plane_fb(struct drm_plane *plane,
13806 struct drm_plane_state *new_state)
13808 struct intel_atomic_state *intel_state =
13809 to_intel_atomic_state(new_state->state);
13810 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13811 struct drm_framebuffer *fb = new_state->fb;
13812 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13813 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13817 struct drm_crtc_state *crtc_state =
13818 drm_atomic_get_new_crtc_state(new_state->state,
13819 plane->state->crtc);
13821 /* Big Hammer, we also need to ensure that any pending
13822 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13823 * current scanout is retired before unpinning the old
13824 * framebuffer. Note that we rely on userspace rendering
13825 * into the buffer attached to the pipe they are waiting
13826 * on. If not, userspace generates a GPU hang with IPEHR
13827 * point to the MI_WAIT_FOR_EVENT.
13829 * This should only fail upon a hung GPU, in which case we
13830 * can safely continue.
13832 if (needs_modeset(crtc_state)) {
13833 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13834 old_obj->resv, NULL,
13842 if (new_state->fence) { /* explicit fencing */
13843 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13845 I915_FENCE_TIMEOUT,
13854 ret = i915_gem_object_pin_pages(obj);
13858 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13860 i915_gem_object_unpin_pages(obj);
13864 ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
13866 mutex_unlock(&dev_priv->drm.struct_mutex);
13867 i915_gem_object_unpin_pages(obj);
13871 fb_obj_bump_render_priority(obj);
13872 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13874 if (!new_state->fence) { /* implicit fencing */
13875 struct dma_fence *fence;
13877 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13879 false, I915_FENCE_TIMEOUT,
13884 fence = reservation_object_get_excl_rcu(obj->resv);
13886 add_rps_boost_after_vblank(new_state->crtc, fence);
13887 dma_fence_put(fence);
13890 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
13894 * We declare pageflips to be interactive and so merit a small bias
13895 * towards upclocking to deliver the frame on time. By only changing
13896 * the RPS thresholds to sample more regularly and aim for higher
13897 * clocks we can hopefully deliver low power workloads (like kodi)
13898 * that are not quite steady state without resorting to forcing
13899 * maximum clocks following a vblank miss (see do_rps_boost()).
13901 if (!intel_state->rps_interactive) {
13902 intel_rps_mark_interactive(dev_priv, true);
13903 intel_state->rps_interactive = true;
13910 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13911 * @plane: drm plane to clean up for
13912 * @old_state: the state from the previous modeset
13914 * Cleans up a framebuffer that has just been removed from a plane.
13916 * Must be called with struct_mutex held.
13919 intel_cleanup_plane_fb(struct drm_plane *plane,
13920 struct drm_plane_state *old_state)
13922 struct intel_atomic_state *intel_state =
13923 to_intel_atomic_state(old_state->state);
13924 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13926 if (intel_state->rps_interactive) {
13927 intel_rps_mark_interactive(dev_priv, false);
13928 intel_state->rps_interactive = false;
13931 /* Should only be called after a successful intel_prepare_plane_fb()! */
13932 mutex_lock(&dev_priv->drm.struct_mutex);
13933 intel_plane_unpin_fb(to_intel_plane_state(old_state));
13934 mutex_unlock(&dev_priv->drm.struct_mutex);
13938 skl_max_scale(const struct intel_crtc_state *crtc_state,
13941 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
13942 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13943 int max_scale, mult;
13944 int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
13946 if (!crtc_state->base.enable)
13947 return DRM_PLANE_HELPER_NO_SCALING;
13949 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13950 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13952 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
13955 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13956 return DRM_PLANE_HELPER_NO_SCALING;
13959 * skl max scale is lower of:
13960 * close to 3 but not 3, -1 is for that purpose
13964 mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
13965 tmpclk1 = (1 << 16) * mult - 1;
13966 tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
13967 max_scale = min(tmpclk1, tmpclk2);
13972 static void intel_begin_crtc_commit(struct intel_atomic_state *state,
13973 struct intel_crtc *crtc)
13975 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13976 struct intel_crtc_state *old_crtc_state =
13977 intel_atomic_get_old_crtc_state(state, crtc);
13978 struct intel_crtc_state *new_crtc_state =
13979 intel_atomic_get_new_crtc_state(state, crtc);
13980 bool modeset = needs_modeset(&new_crtc_state->base);
13982 /* Perform vblank evasion around commit operation */
13983 intel_pipe_update_start(new_crtc_state);
13988 if (new_crtc_state->base.color_mgmt_changed ||
13989 new_crtc_state->update_pipe)
13990 intel_color_commit(new_crtc_state);
13992 if (new_crtc_state->update_pipe)
13993 intel_update_pipe_config(old_crtc_state, new_crtc_state);
13994 else if (INTEL_GEN(dev_priv) >= 9)
13995 skl_detach_scalers(new_crtc_state);
13997 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
13998 bdw_set_pipemisc(new_crtc_state);
14001 if (dev_priv->display.atomic_update_watermarks)
14002 dev_priv->display.atomic_update_watermarks(state,
14006 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14007 struct intel_crtc_state *crtc_state)
14009 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14011 if (!IS_GEN(dev_priv, 2))
14012 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14014 if (crtc_state->has_pch_encoder) {
14015 enum pipe pch_transcoder =
14016 intel_crtc_pch_transcoder(crtc);
14018 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14022 static void intel_finish_crtc_commit(struct intel_atomic_state *state,
14023 struct intel_crtc *crtc)
14025 struct intel_crtc_state *old_crtc_state =
14026 intel_atomic_get_old_crtc_state(state, crtc);
14027 struct intel_crtc_state *new_crtc_state =
14028 intel_atomic_get_new_crtc_state(state, crtc);
14030 intel_pipe_update_end(new_crtc_state);
14032 if (new_crtc_state->update_pipe &&
14033 !needs_modeset(&new_crtc_state->base) &&
14034 old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
14035 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14039 * intel_plane_destroy - destroy a plane
14040 * @plane: plane to destroy
14042 * Common destruction function for all types of planes (primary, cursor,
14045 void intel_plane_destroy(struct drm_plane *plane)
14047 drm_plane_cleanup(plane);
14048 kfree(to_intel_plane(plane));
14051 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
14052 u32 format, u64 modifier)
14054 switch (modifier) {
14055 case DRM_FORMAT_MOD_LINEAR:
14056 case I915_FORMAT_MOD_X_TILED:
14063 case DRM_FORMAT_C8:
14064 case DRM_FORMAT_RGB565:
14065 case DRM_FORMAT_XRGB1555:
14066 case DRM_FORMAT_XRGB8888:
14067 return modifier == DRM_FORMAT_MOD_LINEAR ||
14068 modifier == I915_FORMAT_MOD_X_TILED;
14074 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
14075 u32 format, u64 modifier)
14077 switch (modifier) {
14078 case DRM_FORMAT_MOD_LINEAR:
14079 case I915_FORMAT_MOD_X_TILED:
14086 case DRM_FORMAT_C8:
14087 case DRM_FORMAT_RGB565:
14088 case DRM_FORMAT_XRGB8888:
14089 case DRM_FORMAT_XBGR8888:
14090 case DRM_FORMAT_XRGB2101010:
14091 case DRM_FORMAT_XBGR2101010:
14092 return modifier == DRM_FORMAT_MOD_LINEAR ||
14093 modifier == I915_FORMAT_MOD_X_TILED;
14099 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
14100 u32 format, u64 modifier)
14102 return modifier == DRM_FORMAT_MOD_LINEAR &&
14103 format == DRM_FORMAT_ARGB8888;
14106 static const struct drm_plane_funcs i965_plane_funcs = {
14107 .update_plane = drm_atomic_helper_update_plane,
14108 .disable_plane = drm_atomic_helper_disable_plane,
14109 .destroy = intel_plane_destroy,
14110 .atomic_get_property = intel_plane_atomic_get_property,
14111 .atomic_set_property = intel_plane_atomic_set_property,
14112 .atomic_duplicate_state = intel_plane_duplicate_state,
14113 .atomic_destroy_state = intel_plane_destroy_state,
14114 .format_mod_supported = i965_plane_format_mod_supported,
14117 static const struct drm_plane_funcs i8xx_plane_funcs = {
14118 .update_plane = drm_atomic_helper_update_plane,
14119 .disable_plane = drm_atomic_helper_disable_plane,
14120 .destroy = intel_plane_destroy,
14121 .atomic_get_property = intel_plane_atomic_get_property,
14122 .atomic_set_property = intel_plane_atomic_set_property,
14123 .atomic_duplicate_state = intel_plane_duplicate_state,
14124 .atomic_destroy_state = intel_plane_destroy_state,
14125 .format_mod_supported = i8xx_plane_format_mod_supported,
14129 intel_legacy_cursor_update(struct drm_plane *plane,
14130 struct drm_crtc *crtc,
14131 struct drm_framebuffer *fb,
14132 int crtc_x, int crtc_y,
14133 unsigned int crtc_w, unsigned int crtc_h,
14134 u32 src_x, u32 src_y,
14135 u32 src_w, u32 src_h,
14136 struct drm_modeset_acquire_ctx *ctx)
14138 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
14140 struct drm_plane_state *old_plane_state, *new_plane_state;
14141 struct intel_plane *intel_plane = to_intel_plane(plane);
14142 struct drm_framebuffer *old_fb;
14143 struct intel_crtc_state *crtc_state =
14144 to_intel_crtc_state(crtc->state);
14145 struct intel_crtc_state *new_crtc_state;
14148 * When crtc is inactive or there is a modeset pending,
14149 * wait for it to complete in the slowpath
14151 if (!crtc_state->base.active || needs_modeset(&crtc_state->base) ||
14152 crtc_state->update_pipe)
14155 old_plane_state = plane->state;
14157 * Don't do an async update if there is an outstanding commit modifying
14158 * the plane. This prevents our async update's changes from getting
14159 * overridden by a previous synchronous update's state.
14161 if (old_plane_state->commit &&
14162 !try_wait_for_completion(&old_plane_state->commit->hw_done))
14166 * If any parameters change that may affect watermarks,
14167 * take the slowpath. Only changing fb or position should be
14170 if (old_plane_state->crtc != crtc ||
14171 old_plane_state->src_w != src_w ||
14172 old_plane_state->src_h != src_h ||
14173 old_plane_state->crtc_w != crtc_w ||
14174 old_plane_state->crtc_h != crtc_h ||
14175 !old_plane_state->fb != !fb)
14178 new_plane_state = intel_plane_duplicate_state(plane);
14179 if (!new_plane_state)
14182 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(crtc));
14183 if (!new_crtc_state) {
14188 drm_atomic_set_fb_for_plane(new_plane_state, fb);
14190 new_plane_state->src_x = src_x;
14191 new_plane_state->src_y = src_y;
14192 new_plane_state->src_w = src_w;
14193 new_plane_state->src_h = src_h;
14194 new_plane_state->crtc_x = crtc_x;
14195 new_plane_state->crtc_y = crtc_y;
14196 new_plane_state->crtc_w = crtc_w;
14197 new_plane_state->crtc_h = crtc_h;
14199 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
14200 to_intel_plane_state(old_plane_state),
14201 to_intel_plane_state(new_plane_state));
14205 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
14209 ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
14213 intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP);
14215 old_fb = old_plane_state->fb;
14216 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
14217 intel_plane->frontbuffer_bit);
14219 /* Swap plane state */
14220 plane->state = new_plane_state;
14223 * We cannot swap crtc_state as it may be in use by an atomic commit or
14224 * page flip that's running simultaneously. If we swap crtc_state and
14225 * destroy the old state, we will cause a use-after-free there.
14227 * Only update active_planes, which is needed for our internal
14228 * bookkeeping. Either value will do the right thing when updating
14229 * planes atomically. If the cursor was part of the atomic update then
14230 * we would have taken the slowpath.
14232 crtc_state->active_planes = new_crtc_state->active_planes;
14234 if (plane->state->visible)
14235 intel_update_plane(intel_plane, crtc_state,
14236 to_intel_plane_state(plane->state));
14238 intel_disable_plane(intel_plane, crtc_state);
14240 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
14243 mutex_unlock(&dev_priv->drm.struct_mutex);
14245 if (new_crtc_state)
14246 intel_crtc_destroy_state(crtc, &new_crtc_state->base);
14248 intel_plane_destroy_state(plane, new_plane_state);
14250 intel_plane_destroy_state(plane, old_plane_state);
14254 return drm_atomic_helper_update_plane(plane, crtc, fb,
14255 crtc_x, crtc_y, crtc_w, crtc_h,
14256 src_x, src_y, src_w, src_h, ctx);
14259 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
14260 .update_plane = intel_legacy_cursor_update,
14261 .disable_plane = drm_atomic_helper_disable_plane,
14262 .destroy = intel_plane_destroy,
14263 .atomic_get_property = intel_plane_atomic_get_property,
14264 .atomic_set_property = intel_plane_atomic_set_property,
14265 .atomic_duplicate_state = intel_plane_duplicate_state,
14266 .atomic_destroy_state = intel_plane_destroy_state,
14267 .format_mod_supported = intel_cursor_format_mod_supported,
14270 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
14271 enum i9xx_plane_id i9xx_plane)
14273 if (!HAS_FBC(dev_priv))
14276 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
14277 return i9xx_plane == PLANE_A; /* tied to pipe A */
14278 else if (IS_IVYBRIDGE(dev_priv))
14279 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
14280 i9xx_plane == PLANE_C;
14281 else if (INTEL_GEN(dev_priv) >= 4)
14282 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
14284 return i9xx_plane == PLANE_A;
14287 static struct intel_plane *
14288 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
14290 struct intel_plane *plane;
14291 const struct drm_plane_funcs *plane_funcs;
14292 unsigned int supported_rotations;
14293 unsigned int possible_crtcs;
14294 const u64 *modifiers;
14295 const u32 *formats;
14299 if (INTEL_GEN(dev_priv) >= 9)
14300 return skl_universal_plane_create(dev_priv, pipe,
14303 plane = intel_plane_alloc();
14307 plane->pipe = pipe;
14309 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14310 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14312 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
14313 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
14315 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
14316 plane->id = PLANE_PRIMARY;
14317 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
14319 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
14320 if (plane->has_fbc) {
14321 struct intel_fbc *fbc = &dev_priv->fbc;
14323 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
14326 if (INTEL_GEN(dev_priv) >= 4) {
14327 formats = i965_primary_formats;
14328 num_formats = ARRAY_SIZE(i965_primary_formats);
14329 modifiers = i9xx_format_modifiers;
14331 plane->max_stride = i9xx_plane_max_stride;
14332 plane->update_plane = i9xx_update_plane;
14333 plane->disable_plane = i9xx_disable_plane;
14334 plane->get_hw_state = i9xx_plane_get_hw_state;
14335 plane->check_plane = i9xx_plane_check;
14337 plane_funcs = &i965_plane_funcs;
14339 formats = i8xx_primary_formats;
14340 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14341 modifiers = i9xx_format_modifiers;
14343 plane->max_stride = i9xx_plane_max_stride;
14344 plane->update_plane = i9xx_update_plane;
14345 plane->disable_plane = i9xx_disable_plane;
14346 plane->get_hw_state = i9xx_plane_get_hw_state;
14347 plane->check_plane = i9xx_plane_check;
14349 plane_funcs = &i8xx_plane_funcs;
14352 possible_crtcs = BIT(pipe);
14354 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
14355 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
14356 possible_crtcs, plane_funcs,
14357 formats, num_formats, modifiers,
14358 DRM_PLANE_TYPE_PRIMARY,
14359 "primary %c", pipe_name(pipe));
14361 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
14362 possible_crtcs, plane_funcs,
14363 formats, num_formats, modifiers,
14364 DRM_PLANE_TYPE_PRIMARY,
14366 plane_name(plane->i9xx_plane));
14370 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
14371 supported_rotations =
14372 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
14373 DRM_MODE_REFLECT_X;
14374 } else if (INTEL_GEN(dev_priv) >= 4) {
14375 supported_rotations =
14376 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
14378 supported_rotations = DRM_MODE_ROTATE_0;
14381 if (INTEL_GEN(dev_priv) >= 4)
14382 drm_plane_create_rotation_property(&plane->base,
14384 supported_rotations);
14386 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
14391 intel_plane_free(plane);
14393 return ERR_PTR(ret);
14396 static struct intel_plane *
14397 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
14400 unsigned int possible_crtcs;
14401 struct intel_plane *cursor;
14404 cursor = intel_plane_alloc();
14405 if (IS_ERR(cursor))
14408 cursor->pipe = pipe;
14409 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
14410 cursor->id = PLANE_CURSOR;
14411 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
14413 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14414 cursor->max_stride = i845_cursor_max_stride;
14415 cursor->update_plane = i845_update_cursor;
14416 cursor->disable_plane = i845_disable_cursor;
14417 cursor->get_hw_state = i845_cursor_get_hw_state;
14418 cursor->check_plane = i845_check_cursor;
14420 cursor->max_stride = i9xx_cursor_max_stride;
14421 cursor->update_plane = i9xx_update_cursor;
14422 cursor->disable_plane = i9xx_disable_cursor;
14423 cursor->get_hw_state = i9xx_cursor_get_hw_state;
14424 cursor->check_plane = i9xx_check_cursor;
14427 cursor->cursor.base = ~0;
14428 cursor->cursor.cntl = ~0;
14430 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
14431 cursor->cursor.size = ~0;
14433 possible_crtcs = BIT(pipe);
14435 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
14436 possible_crtcs, &intel_cursor_plane_funcs,
14437 intel_cursor_formats,
14438 ARRAY_SIZE(intel_cursor_formats),
14439 cursor_format_modifiers,
14440 DRM_PLANE_TYPE_CURSOR,
14441 "cursor %c", pipe_name(pipe));
14445 if (INTEL_GEN(dev_priv) >= 4)
14446 drm_plane_create_rotation_property(&cursor->base,
14448 DRM_MODE_ROTATE_0 |
14449 DRM_MODE_ROTATE_180);
14451 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14456 intel_plane_free(cursor);
14458 return ERR_PTR(ret);
14461 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
14462 struct intel_crtc_state *crtc_state)
14464 struct intel_crtc_scaler_state *scaler_state =
14465 &crtc_state->scaler_state;
14466 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14469 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
14470 if (!crtc->num_scalers)
14473 for (i = 0; i < crtc->num_scalers; i++) {
14474 struct intel_scaler *scaler = &scaler_state->scalers[i];
14476 scaler->in_use = 0;
14480 scaler_state->scaler_id = -1;
14483 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
14485 struct intel_crtc *intel_crtc;
14486 struct intel_crtc_state *crtc_state = NULL;
14487 struct intel_plane *primary = NULL;
14488 struct intel_plane *cursor = NULL;
14491 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14495 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14500 intel_crtc->config = crtc_state;
14501 intel_crtc->base.state = &crtc_state->base;
14502 crtc_state->base.crtc = &intel_crtc->base;
14504 primary = intel_primary_plane_create(dev_priv, pipe);
14505 if (IS_ERR(primary)) {
14506 ret = PTR_ERR(primary);
14509 intel_crtc->plane_ids_mask |= BIT(primary->id);
14511 for_each_sprite(dev_priv, pipe, sprite) {
14512 struct intel_plane *plane;
14514 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
14515 if (IS_ERR(plane)) {
14516 ret = PTR_ERR(plane);
14519 intel_crtc->plane_ids_mask |= BIT(plane->id);
14522 cursor = intel_cursor_plane_create(dev_priv, pipe);
14523 if (IS_ERR(cursor)) {
14524 ret = PTR_ERR(cursor);
14527 intel_crtc->plane_ids_mask |= BIT(cursor->id);
14529 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
14530 &primary->base, &cursor->base,
14532 "pipe %c", pipe_name(pipe));
14536 intel_crtc->pipe = pipe;
14538 /* initialize shared scalers */
14539 intel_crtc_init_scalers(intel_crtc, crtc_state);
14541 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
14542 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
14543 dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
14545 if (INTEL_GEN(dev_priv) < 9) {
14546 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
14548 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14549 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
14550 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
14553 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14555 intel_color_init(intel_crtc);
14557 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14563 * drm_mode_config_cleanup() will free up any
14564 * crtcs/planes already initialized.
14572 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
14573 struct drm_file *file)
14575 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14576 struct drm_crtc *drmmode_crtc;
14577 struct intel_crtc *crtc;
14579 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
14583 crtc = to_intel_crtc(drmmode_crtc);
14584 pipe_from_crtc_id->pipe = crtc->pipe;
14589 static int intel_encoder_clones(struct intel_encoder *encoder)
14591 struct drm_device *dev = encoder->base.dev;
14592 struct intel_encoder *source_encoder;
14593 int index_mask = 0;
14596 for_each_intel_encoder(dev, source_encoder) {
14597 if (encoders_cloneable(encoder, source_encoder))
14598 index_mask |= (1 << entry);
14606 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
14608 if (!IS_MOBILE(dev_priv))
14611 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14614 if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14620 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
14622 if (INTEL_GEN(dev_priv) >= 9)
14625 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14628 if (HAS_PCH_LPT_H(dev_priv) &&
14629 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14632 /* DDI E can't be used if DDI A requires 4 lanes */
14633 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14636 if (!dev_priv->vbt.int_crt_support)
14642 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14647 if (HAS_DDI(dev_priv))
14650 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14651 * everywhere where registers can be write protected.
14653 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14658 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14659 u32 val = I915_READ(PP_CONTROL(pps_idx));
14661 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14662 I915_WRITE(PP_CONTROL(pps_idx), val);
14666 static void intel_pps_init(struct drm_i915_private *dev_priv)
14668 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14669 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14670 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14671 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14673 dev_priv->pps_mmio_base = PPS_BASE;
14675 intel_pps_unlock_regs_wa(dev_priv);
14678 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14680 struct intel_encoder *encoder;
14681 bool dpd_is_edp = false;
14683 intel_pps_init(dev_priv);
14685 if (!HAS_DISPLAY(dev_priv))
14688 if (IS_ELKHARTLAKE(dev_priv)) {
14689 intel_ddi_init(dev_priv, PORT_A);
14690 intel_ddi_init(dev_priv, PORT_B);
14691 intel_ddi_init(dev_priv, PORT_C);
14692 icl_dsi_init(dev_priv);
14693 } else if (INTEL_GEN(dev_priv) >= 11) {
14694 intel_ddi_init(dev_priv, PORT_A);
14695 intel_ddi_init(dev_priv, PORT_B);
14696 intel_ddi_init(dev_priv, PORT_C);
14697 intel_ddi_init(dev_priv, PORT_D);
14698 intel_ddi_init(dev_priv, PORT_E);
14700 * On some ICL SKUs port F is not present. No strap bits for
14701 * this, so rely on VBT.
14702 * Work around broken VBTs on SKUs known to have no port F.
14704 if (IS_ICL_WITH_PORT_F(dev_priv) &&
14705 intel_bios_is_port_present(dev_priv, PORT_F))
14706 intel_ddi_init(dev_priv, PORT_F);
14708 icl_dsi_init(dev_priv);
14709 } else if (IS_GEN9_LP(dev_priv)) {
14711 * FIXME: Broxton doesn't support port detection via the
14712 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14713 * detect the ports.
14715 intel_ddi_init(dev_priv, PORT_A);
14716 intel_ddi_init(dev_priv, PORT_B);
14717 intel_ddi_init(dev_priv, PORT_C);
14719 vlv_dsi_init(dev_priv);
14720 } else if (HAS_DDI(dev_priv)) {
14723 if (intel_ddi_crt_present(dev_priv))
14724 intel_crt_init(dev_priv);
14727 * Haswell uses DDI functions to detect digital outputs.
14728 * On SKL pre-D0 the strap isn't connected, so we assume
14731 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14732 /* WaIgnoreDDIAStrap: skl */
14733 if (found || IS_GEN9_BC(dev_priv))
14734 intel_ddi_init(dev_priv, PORT_A);
14736 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
14738 found = I915_READ(SFUSE_STRAP);
14740 if (found & SFUSE_STRAP_DDIB_DETECTED)
14741 intel_ddi_init(dev_priv, PORT_B);
14742 if (found & SFUSE_STRAP_DDIC_DETECTED)
14743 intel_ddi_init(dev_priv, PORT_C);
14744 if (found & SFUSE_STRAP_DDID_DETECTED)
14745 intel_ddi_init(dev_priv, PORT_D);
14746 if (found & SFUSE_STRAP_DDIF_DETECTED)
14747 intel_ddi_init(dev_priv, PORT_F);
14749 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14751 if (IS_GEN9_BC(dev_priv) &&
14752 intel_bios_is_port_present(dev_priv, PORT_E))
14753 intel_ddi_init(dev_priv, PORT_E);
14755 } else if (HAS_PCH_SPLIT(dev_priv)) {
14759 * intel_edp_init_connector() depends on this completing first,
14760 * to prevent the registration of both eDP and LVDS and the
14761 * incorrect sharing of the PPS.
14763 intel_lvds_init(dev_priv);
14764 intel_crt_init(dev_priv);
14766 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
14768 if (ilk_has_edp_a(dev_priv))
14769 intel_dp_init(dev_priv, DP_A, PORT_A);
14771 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14772 /* PCH SDVOB multiplex with HDMIB */
14773 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14775 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14776 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14777 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14780 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14781 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14783 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14784 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14786 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14787 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14789 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14790 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14791 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14792 bool has_edp, has_port;
14794 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
14795 intel_crt_init(dev_priv);
14798 * The DP_DETECTED bit is the latched state of the DDC
14799 * SDA pin at boot. However since eDP doesn't require DDC
14800 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14801 * eDP ports may have been muxed to an alternate function.
14802 * Thus we can't rely on the DP_DETECTED bit alone to detect
14803 * eDP ports. Consult the VBT as well as DP_DETECTED to
14804 * detect eDP ports.
14806 * Sadly the straps seem to be missing sometimes even for HDMI
14807 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14808 * and VBT for the presence of the port. Additionally we can't
14809 * trust the port type the VBT declares as we've seen at least
14810 * HDMI ports that the VBT claim are DP or eDP.
14812 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
14813 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14814 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14815 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14816 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14817 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14819 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
14820 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14821 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14822 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14823 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14824 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14826 if (IS_CHERRYVIEW(dev_priv)) {
14828 * eDP not supported on port D,
14829 * so no need to worry about it
14831 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14832 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14833 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14834 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14835 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14838 vlv_dsi_init(dev_priv);
14839 } else if (IS_PINEVIEW(dev_priv)) {
14840 intel_lvds_init(dev_priv);
14841 intel_crt_init(dev_priv);
14842 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
14843 bool found = false;
14845 if (IS_MOBILE(dev_priv))
14846 intel_lvds_init(dev_priv);
14848 intel_crt_init(dev_priv);
14850 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14851 DRM_DEBUG_KMS("probing SDVOB\n");
14852 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14853 if (!found && IS_G4X(dev_priv)) {
14854 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14855 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14858 if (!found && IS_G4X(dev_priv))
14859 intel_dp_init(dev_priv, DP_B, PORT_B);
14862 /* Before G4X SDVOC doesn't have its own detect register */
14864 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14865 DRM_DEBUG_KMS("probing SDVOC\n");
14866 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14869 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14871 if (IS_G4X(dev_priv)) {
14872 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14873 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14875 if (IS_G4X(dev_priv))
14876 intel_dp_init(dev_priv, DP_C, PORT_C);
14879 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14880 intel_dp_init(dev_priv, DP_D, PORT_D);
14882 if (SUPPORTS_TV(dev_priv))
14883 intel_tv_init(dev_priv);
14884 } else if (IS_GEN(dev_priv, 2)) {
14885 if (IS_I85X(dev_priv))
14886 intel_lvds_init(dev_priv);
14888 intel_crt_init(dev_priv);
14889 intel_dvo_init(dev_priv);
14892 intel_psr_init(dev_priv);
14894 for_each_intel_encoder(&dev_priv->drm, encoder) {
14895 encoder->base.possible_crtcs = encoder->crtc_mask;
14896 encoder->base.possible_clones =
14897 intel_encoder_clones(encoder);
14900 intel_init_pch_refclk(dev_priv);
14902 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14905 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14907 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14908 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14910 drm_framebuffer_cleanup(fb);
14912 i915_gem_object_lock(obj);
14913 WARN_ON(!obj->framebuffer_references--);
14914 i915_gem_object_unlock(obj);
14916 i915_gem_object_put(obj);
14921 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14922 struct drm_file *file,
14923 unsigned int *handle)
14925 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14927 if (obj->userptr.mm) {
14928 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14932 return drm_gem_handle_create(file, &obj->base, handle);
14935 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14936 struct drm_file *file,
14937 unsigned flags, unsigned color,
14938 struct drm_clip_rect *clips,
14939 unsigned num_clips)
14941 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14943 i915_gem_object_flush_if_display(obj);
14944 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14949 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14950 .destroy = intel_user_framebuffer_destroy,
14951 .create_handle = intel_user_framebuffer_create_handle,
14952 .dirty = intel_user_framebuffer_dirty,
14956 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14957 u32 pixel_format, u64 fb_modifier)
14959 struct intel_crtc *crtc;
14960 struct intel_plane *plane;
14963 * We assume the primary plane for pipe A has
14964 * the highest stride limits of them all.
14966 crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
14967 plane = to_intel_plane(crtc->base.primary);
14969 return plane->max_stride(plane, pixel_format, fb_modifier,
14970 DRM_MODE_ROTATE_0);
14973 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14974 struct drm_i915_gem_object *obj,
14975 struct drm_mode_fb_cmd2 *mode_cmd)
14977 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14978 struct drm_framebuffer *fb = &intel_fb->base;
14980 unsigned int tiling, stride;
14984 i915_gem_object_lock(obj);
14985 obj->framebuffer_references++;
14986 tiling = i915_gem_object_get_tiling(obj);
14987 stride = i915_gem_object_get_stride(obj);
14988 i915_gem_object_unlock(obj);
14990 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14992 * If there's a fence, enforce that
14993 * the fb modifier and tiling mode match.
14995 if (tiling != I915_TILING_NONE &&
14996 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14997 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
15001 if (tiling == I915_TILING_X) {
15002 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15003 } else if (tiling == I915_TILING_Y) {
15004 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
15009 if (!drm_any_plane_has_format(&dev_priv->drm,
15010 mode_cmd->pixel_format,
15011 mode_cmd->modifier[0])) {
15012 struct drm_format_name_buf format_name;
15014 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
15015 drm_get_format_name(mode_cmd->pixel_format,
15017 mode_cmd->modifier[0]);
15022 * gen2/3 display engine uses the fence if present,
15023 * so the tiling mode must match the fb modifier exactly.
15025 if (INTEL_GEN(dev_priv) < 4 &&
15026 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15027 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
15031 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->pixel_format,
15032 mode_cmd->modifier[0]);
15033 if (mode_cmd->pitches[0] > pitch_limit) {
15034 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
15035 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
15036 "tiled" : "linear",
15037 mode_cmd->pitches[0], pitch_limit);
15042 * If there's a fence, enforce that
15043 * the fb pitch and fence stride match.
15045 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
15046 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
15047 mode_cmd->pitches[0], stride);
15051 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15052 if (mode_cmd->offsets[0] != 0)
15055 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
15057 for (i = 0; i < fb->format->num_planes; i++) {
15058 u32 stride_alignment;
15060 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
15061 DRM_DEBUG_KMS("bad plane %d handle\n", i);
15065 stride_alignment = intel_fb_stride_alignment(fb, i);
15068 * Display WA #0531: skl,bxt,kbl,glk
15070 * Render decompression and plane width > 3840
15071 * combined with horizontal panning requires the
15072 * plane stride to be a multiple of 4. We'll just
15073 * require the entire fb to accommodate that to avoid
15074 * potential runtime errors at plane configuration time.
15076 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
15077 is_ccs_modifier(fb->modifier))
15078 stride_alignment *= 4;
15080 if (fb->pitches[i] & (stride_alignment - 1)) {
15081 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
15082 i, fb->pitches[i], stride_alignment);
15086 fb->obj[i] = &obj->base;
15089 ret = intel_fill_fb_info(dev_priv, fb);
15093 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
15095 DRM_ERROR("framebuffer init failed %d\n", ret);
15102 i915_gem_object_lock(obj);
15103 obj->framebuffer_references--;
15104 i915_gem_object_unlock(obj);
15108 static struct drm_framebuffer *
15109 intel_user_framebuffer_create(struct drm_device *dev,
15110 struct drm_file *filp,
15111 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15113 struct drm_framebuffer *fb;
15114 struct drm_i915_gem_object *obj;
15115 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15117 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15119 return ERR_PTR(-ENOENT);
15121 fb = intel_framebuffer_create(obj, &mode_cmd);
15123 i915_gem_object_put(obj);
15128 static void intel_atomic_state_free(struct drm_atomic_state *state)
15130 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
15132 drm_atomic_state_default_release(state);
15134 i915_sw_fence_fini(&intel_state->commit_ready);
15139 static enum drm_mode_status
15140 intel_mode_valid(struct drm_device *dev,
15141 const struct drm_display_mode *mode)
15143 struct drm_i915_private *dev_priv = to_i915(dev);
15144 int hdisplay_max, htotal_max;
15145 int vdisplay_max, vtotal_max;
15148 * Can't reject DBLSCAN here because Xorg ddxen can add piles
15149 * of DBLSCAN modes to the output's mode list when they detect
15150 * the scaling mode property on the connector. And they don't
15151 * ask the kernel to validate those modes in any way until
15152 * modeset time at which point the client gets a protocol error.
15153 * So in order to not upset those clients we silently ignore the
15154 * DBLSCAN flag on such connectors. For other connectors we will
15155 * reject modes with the DBLSCAN flag in encoder->compute_config().
15156 * And we always reject DBLSCAN modes in connector->mode_valid()
15157 * as we never want such modes on the connector's mode list.
15160 if (mode->vscan > 1)
15161 return MODE_NO_VSCAN;
15163 if (mode->flags & DRM_MODE_FLAG_HSKEW)
15164 return MODE_H_ILLEGAL;
15166 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
15167 DRM_MODE_FLAG_NCSYNC |
15168 DRM_MODE_FLAG_PCSYNC))
15171 if (mode->flags & (DRM_MODE_FLAG_BCAST |
15172 DRM_MODE_FLAG_PIXMUX |
15173 DRM_MODE_FLAG_CLKDIV2))
15176 if (INTEL_GEN(dev_priv) >= 9 ||
15177 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
15178 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
15179 vdisplay_max = 4096;
15182 } else if (INTEL_GEN(dev_priv) >= 3) {
15183 hdisplay_max = 4096;
15184 vdisplay_max = 4096;
15188 hdisplay_max = 2048;
15189 vdisplay_max = 2048;
15194 if (mode->hdisplay > hdisplay_max ||
15195 mode->hsync_start > htotal_max ||
15196 mode->hsync_end > htotal_max ||
15197 mode->htotal > htotal_max)
15198 return MODE_H_ILLEGAL;
15200 if (mode->vdisplay > vdisplay_max ||
15201 mode->vsync_start > vtotal_max ||
15202 mode->vsync_end > vtotal_max ||
15203 mode->vtotal > vtotal_max)
15204 return MODE_V_ILLEGAL;
15209 static const struct drm_mode_config_funcs intel_mode_funcs = {
15210 .fb_create = intel_user_framebuffer_create,
15211 .get_format_info = intel_get_format_info,
15212 .output_poll_changed = intel_fbdev_output_poll_changed,
15213 .mode_valid = intel_mode_valid,
15214 .atomic_check = intel_atomic_check,
15215 .atomic_commit = intel_atomic_commit,
15216 .atomic_state_alloc = intel_atomic_state_alloc,
15217 .atomic_state_clear = intel_atomic_state_clear,
15218 .atomic_state_free = intel_atomic_state_free,
15222 * intel_init_display_hooks - initialize the display modesetting hooks
15223 * @dev_priv: device private
15225 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15227 intel_init_cdclk_hooks(dev_priv);
15229 if (INTEL_GEN(dev_priv) >= 9) {
15230 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15231 dev_priv->display.get_initial_plane_config =
15232 skylake_get_initial_plane_config;
15233 dev_priv->display.crtc_compute_clock =
15234 haswell_crtc_compute_clock;
15235 dev_priv->display.crtc_enable = haswell_crtc_enable;
15236 dev_priv->display.crtc_disable = haswell_crtc_disable;
15237 } else if (HAS_DDI(dev_priv)) {
15238 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15239 dev_priv->display.get_initial_plane_config =
15240 i9xx_get_initial_plane_config;
15241 dev_priv->display.crtc_compute_clock =
15242 haswell_crtc_compute_clock;
15243 dev_priv->display.crtc_enable = haswell_crtc_enable;
15244 dev_priv->display.crtc_disable = haswell_crtc_disable;
15245 } else if (HAS_PCH_SPLIT(dev_priv)) {
15246 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15247 dev_priv->display.get_initial_plane_config =
15248 i9xx_get_initial_plane_config;
15249 dev_priv->display.crtc_compute_clock =
15250 ironlake_crtc_compute_clock;
15251 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15252 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15253 } else if (IS_CHERRYVIEW(dev_priv)) {
15254 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15255 dev_priv->display.get_initial_plane_config =
15256 i9xx_get_initial_plane_config;
15257 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15258 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15259 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15260 } else if (IS_VALLEYVIEW(dev_priv)) {
15261 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15262 dev_priv->display.get_initial_plane_config =
15263 i9xx_get_initial_plane_config;
15264 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15265 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15266 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15267 } else if (IS_G4X(dev_priv)) {
15268 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15269 dev_priv->display.get_initial_plane_config =
15270 i9xx_get_initial_plane_config;
15271 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15272 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15273 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15274 } else if (IS_PINEVIEW(dev_priv)) {
15275 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15276 dev_priv->display.get_initial_plane_config =
15277 i9xx_get_initial_plane_config;
15278 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15279 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15280 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15281 } else if (!IS_GEN(dev_priv, 2)) {
15282 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15283 dev_priv->display.get_initial_plane_config =
15284 i9xx_get_initial_plane_config;
15285 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15286 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15287 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15289 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15290 dev_priv->display.get_initial_plane_config =
15291 i9xx_get_initial_plane_config;
15292 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15293 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15294 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15297 if (IS_GEN(dev_priv, 5)) {
15298 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15299 } else if (IS_GEN(dev_priv, 6)) {
15300 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15301 } else if (IS_IVYBRIDGE(dev_priv)) {
15302 /* FIXME: detect B0+ stepping and use auto training */
15303 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15304 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15305 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15308 if (INTEL_GEN(dev_priv) >= 9)
15309 dev_priv->display.update_crtcs = skl_update_crtcs;
15311 dev_priv->display.update_crtcs = intel_update_crtcs;
15314 static i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
15316 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15317 return VLV_VGACNTRL;
15318 else if (INTEL_GEN(dev_priv) >= 5)
15319 return CPU_VGACNTRL;
15324 /* Disable the VGA plane that we never use */
15325 static void i915_disable_vga(struct drm_i915_private *dev_priv)
15327 struct pci_dev *pdev = dev_priv->drm.pdev;
15329 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15331 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15332 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
15333 outb(SR01, VGA_SR_INDEX);
15334 sr1 = inb(VGA_SR_DATA);
15335 outb(sr1 | 1<<5, VGA_SR_DATA);
15336 vga_put(pdev, VGA_RSRC_LEGACY_IO);
15339 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15340 POSTING_READ(vga_reg);
15343 void intel_modeset_init_hw(struct drm_device *dev)
15345 struct drm_i915_private *dev_priv = to_i915(dev);
15347 intel_update_cdclk(dev_priv);
15348 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
15349 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
15353 * Calculate what we think the watermarks should be for the state we've read
15354 * out of the hardware and then immediately program those watermarks so that
15355 * we ensure the hardware settings match our internal state.
15357 * We can calculate what we think WM's should be by creating a duplicate of the
15358 * current state (which was constructed during hardware readout) and running it
15359 * through the atomic check code to calculate new watermark values in the
15362 static void sanitize_watermarks(struct drm_device *dev)
15364 struct drm_i915_private *dev_priv = to_i915(dev);
15365 struct drm_atomic_state *state;
15366 struct intel_atomic_state *intel_state;
15367 struct drm_crtc *crtc;
15368 struct drm_crtc_state *cstate;
15369 struct drm_modeset_acquire_ctx ctx;
15373 /* Only supported on platforms that use atomic watermark design */
15374 if (!dev_priv->display.optimize_watermarks)
15378 * We need to hold connection_mutex before calling duplicate_state so
15379 * that the connector loop is protected.
15381 drm_modeset_acquire_init(&ctx, 0);
15383 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15384 if (ret == -EDEADLK) {
15385 drm_modeset_backoff(&ctx);
15387 } else if (WARN_ON(ret)) {
15391 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15392 if (WARN_ON(IS_ERR(state)))
15395 intel_state = to_intel_atomic_state(state);
15398 * Hardware readout is the only time we don't want to calculate
15399 * intermediate watermarks (since we don't trust the current
15402 if (!HAS_GMCH(dev_priv))
15403 intel_state->skip_intermediate_wm = true;
15405 ret = intel_atomic_check(dev, state);
15408 * If we fail here, it means that the hardware appears to be
15409 * programmed in a way that shouldn't be possible, given our
15410 * understanding of watermark requirements. This might mean a
15411 * mistake in the hardware readout code or a mistake in the
15412 * watermark calculations for a given platform. Raise a WARN
15413 * so that this is noticeable.
15415 * If this actually happens, we'll have to just leave the
15416 * BIOS-programmed watermarks untouched and hope for the best.
15418 WARN(true, "Could not determine valid watermarks for inherited state\n");
15422 /* Write calculated watermark values back */
15423 for_each_new_crtc_in_state(state, crtc, cstate, i) {
15424 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15426 cs->wm.need_postvbl_update = true;
15427 dev_priv->display.optimize_watermarks(intel_state, cs);
15429 to_intel_crtc_state(crtc->state)->wm = cs->wm;
15433 drm_atomic_state_put(state);
15435 drm_modeset_drop_locks(&ctx);
15436 drm_modeset_acquire_fini(&ctx);
15439 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
15441 if (IS_GEN(dev_priv, 5)) {
15443 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
15445 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
15446 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
15447 dev_priv->fdi_pll_freq = 270000;
15452 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
15455 static int intel_initial_commit(struct drm_device *dev)
15457 struct drm_atomic_state *state = NULL;
15458 struct drm_modeset_acquire_ctx ctx;
15459 struct drm_crtc *crtc;
15460 struct drm_crtc_state *crtc_state;
15463 state = drm_atomic_state_alloc(dev);
15467 drm_modeset_acquire_init(&ctx, 0);
15470 state->acquire_ctx = &ctx;
15472 drm_for_each_crtc(crtc, dev) {
15473 crtc_state = drm_atomic_get_crtc_state(state, crtc);
15474 if (IS_ERR(crtc_state)) {
15475 ret = PTR_ERR(crtc_state);
15479 if (crtc_state->active) {
15480 ret = drm_atomic_add_affected_planes(state, crtc);
15485 * FIXME hack to force a LUT update to avoid the
15486 * plane update forcing the pipe gamma on without
15487 * having a proper LUT loaded. Remove once we
15488 * have readout for pipe gamma enable.
15490 crtc_state->color_mgmt_changed = true;
15494 ret = drm_atomic_commit(state);
15497 if (ret == -EDEADLK) {
15498 drm_atomic_state_clear(state);
15499 drm_modeset_backoff(&ctx);
15503 drm_atomic_state_put(state);
15505 drm_modeset_drop_locks(&ctx);
15506 drm_modeset_acquire_fini(&ctx);
15511 int intel_modeset_init(struct drm_device *dev)
15513 struct drm_i915_private *dev_priv = to_i915(dev);
15514 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15516 struct intel_crtc *crtc;
15519 dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
15521 drm_mode_config_init(dev);
15523 dev->mode_config.min_width = 0;
15524 dev->mode_config.min_height = 0;
15526 dev->mode_config.preferred_depth = 24;
15527 dev->mode_config.prefer_shadow = 1;
15529 dev->mode_config.allow_fb_modifiers = true;
15531 dev->mode_config.funcs = &intel_mode_funcs;
15533 init_llist_head(&dev_priv->atomic_helper.free_list);
15534 INIT_WORK(&dev_priv->atomic_helper.free_work,
15535 intel_atomic_helper_free_state_worker);
15537 intel_init_quirks(dev_priv);
15539 intel_fbc_init(dev_priv);
15541 intel_init_pm(dev_priv);
15544 * There may be no VBT; and if the BIOS enabled SSC we can
15545 * just keep using it to avoid unnecessary flicker. Whereas if the
15546 * BIOS isn't using it, don't assume it will work even if the VBT
15547 * indicates as much.
15549 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15550 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15553 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15554 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15555 bios_lvds_use_ssc ? "en" : "dis",
15556 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15557 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15561 /* maximum framebuffer dimensions */
15562 if (IS_GEN(dev_priv, 2)) {
15563 dev->mode_config.max_width = 2048;
15564 dev->mode_config.max_height = 2048;
15565 } else if (IS_GEN(dev_priv, 3)) {
15566 dev->mode_config.max_width = 4096;
15567 dev->mode_config.max_height = 4096;
15569 dev->mode_config.max_width = 8192;
15570 dev->mode_config.max_height = 8192;
15573 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15574 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15575 dev->mode_config.cursor_height = 1023;
15576 } else if (IS_GEN(dev_priv, 2)) {
15577 dev->mode_config.cursor_width = 64;
15578 dev->mode_config.cursor_height = 64;
15580 dev->mode_config.cursor_width = 256;
15581 dev->mode_config.cursor_height = 256;
15584 dev->mode_config.fb_base = ggtt->gmadr.start;
15586 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15587 INTEL_INFO(dev_priv)->num_pipes,
15588 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15590 for_each_pipe(dev_priv, pipe) {
15591 ret = intel_crtc_init(dev_priv, pipe);
15593 drm_mode_config_cleanup(dev);
15598 intel_shared_dpll_init(dev);
15599 intel_update_fdi_pll_freq(dev_priv);
15601 intel_update_czclk(dev_priv);
15602 intel_modeset_init_hw(dev);
15604 intel_hdcp_component_init(dev_priv);
15606 if (dev_priv->max_cdclk_freq == 0)
15607 intel_update_max_cdclk(dev_priv);
15609 /* Just disable it once at startup */
15610 i915_disable_vga(dev_priv);
15611 intel_setup_outputs(dev_priv);
15613 drm_modeset_lock_all(dev);
15614 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15615 drm_modeset_unlock_all(dev);
15617 for_each_intel_crtc(dev, crtc) {
15618 struct intel_initial_plane_config plane_config = {};
15624 * Note that reserving the BIOS fb up front prevents us
15625 * from stuffing other stolen allocations like the ring
15626 * on top. This prevents some ugliness at boot time, and
15627 * can even allow for smooth boot transitions if the BIOS
15628 * fb is large enough for the active pipe configuration.
15630 dev_priv->display.get_initial_plane_config(crtc,
15634 * If the fb is shared between multiple heads, we'll
15635 * just get the first one.
15637 intel_find_initial_plane_obj(crtc, &plane_config);
15641 * Make sure hardware watermarks really match the state we read out.
15642 * Note that we need to do this after reconstructing the BIOS fb's
15643 * since the watermark calculation done here will use pstate->fb.
15645 if (!HAS_GMCH(dev_priv))
15646 sanitize_watermarks(dev);
15649 * Force all active planes to recompute their states. So that on
15650 * mode_setcrtc after probe, all the intel_plane_state variables
15651 * are already calculated and there is no assert_plane warnings
15654 ret = intel_initial_commit(dev);
15656 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
15661 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15663 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15664 /* 640x480@60Hz, ~25175 kHz */
15665 struct dpll clock = {
15675 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15677 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15678 pipe_name(pipe), clock.vco, clock.dot);
15680 fp = i9xx_dpll_compute_fp(&clock);
15681 dpll = DPLL_DVO_2X_MODE |
15682 DPLL_VGA_MODE_DIS |
15683 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15684 PLL_P2_DIVIDE_BY_4 |
15685 PLL_REF_INPUT_DREFCLK |
15688 I915_WRITE(FP0(pipe), fp);
15689 I915_WRITE(FP1(pipe), fp);
15691 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15692 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15693 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15694 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15695 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15696 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15697 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15700 * Apparently we need to have VGA mode enabled prior to changing
15701 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15702 * dividers, even though the register value does change.
15704 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15705 I915_WRITE(DPLL(pipe), dpll);
15707 /* Wait for the clocks to stabilize. */
15708 POSTING_READ(DPLL(pipe));
15711 /* The pixel multiplier can only be updated once the
15712 * DPLL is enabled and the clocks are stable.
15714 * So write it again.
15716 I915_WRITE(DPLL(pipe), dpll);
15718 /* We do this three times for luck */
15719 for (i = 0; i < 3 ; i++) {
15720 I915_WRITE(DPLL(pipe), dpll);
15721 POSTING_READ(DPLL(pipe));
15722 udelay(150); /* wait for warmup */
15725 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15726 POSTING_READ(PIPECONF(pipe));
15728 intel_wait_for_pipe_scanline_moving(crtc);
15731 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15733 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15735 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15738 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
15739 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
15740 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
15741 WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
15742 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
15744 I915_WRITE(PIPECONF(pipe), 0);
15745 POSTING_READ(PIPECONF(pipe));
15747 intel_wait_for_pipe_scanline_stopped(crtc);
15749 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15750 POSTING_READ(DPLL(pipe));
15754 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15756 struct intel_crtc *crtc;
15758 if (INTEL_GEN(dev_priv) >= 4)
15761 for_each_intel_crtc(&dev_priv->drm, crtc) {
15762 struct intel_plane *plane =
15763 to_intel_plane(crtc->base.primary);
15764 struct intel_crtc *plane_crtc;
15767 if (!plane->get_hw_state(plane, &pipe))
15770 if (pipe == crtc->pipe)
15773 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
15774 plane->base.base.id, plane->base.name);
15776 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15777 intel_plane_disable_noatomic(plane_crtc, plane);
15781 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15783 struct drm_device *dev = crtc->base.dev;
15784 struct intel_encoder *encoder;
15786 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15792 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15794 struct drm_device *dev = encoder->base.dev;
15795 struct intel_connector *connector;
15797 for_each_connector_on_encoder(dev, &encoder->base, connector)
15803 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15804 enum pipe pch_transcoder)
15806 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15807 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
15810 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15811 struct drm_modeset_acquire_ctx *ctx)
15813 struct drm_device *dev = crtc->base.dev;
15814 struct drm_i915_private *dev_priv = to_i915(dev);
15815 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
15816 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
15818 /* Clear any frame start delays used for debugging left by the BIOS */
15819 if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
15820 i915_reg_t reg = PIPECONF(cpu_transcoder);
15823 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15826 if (crtc_state->base.active) {
15827 struct intel_plane *plane;
15829 /* Disable everything but the primary plane */
15830 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15831 const struct intel_plane_state *plane_state =
15832 to_intel_plane_state(plane->base.state);
15834 if (plane_state->base.visible &&
15835 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
15836 intel_plane_disable_noatomic(crtc, plane);
15840 * Disable any background color set by the BIOS, but enable the
15841 * gamma and CSC to match how we program our planes.
15843 if (INTEL_GEN(dev_priv) >= 9)
15844 I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
15845 SKL_BOTTOM_COLOR_GAMMA_ENABLE |
15846 SKL_BOTTOM_COLOR_CSC_ENABLE);
15849 /* Adjust the state of the output pipe according to whether we
15850 * have active connectors/encoders. */
15851 if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
15852 intel_crtc_disable_noatomic(&crtc->base, ctx);
15854 if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
15856 * We start out with underrun reporting disabled to avoid races.
15857 * For correct bookkeeping mark this on active crtcs.
15859 * Also on gmch platforms we dont have any hardware bits to
15860 * disable the underrun reporting. Which means we need to start
15861 * out with underrun reporting disabled also on inactive pipes,
15862 * since otherwise we'll complain about the garbage we read when
15863 * e.g. coming up after runtime pm.
15865 * No protection against concurrent access is required - at
15866 * worst a fifo underrun happens which also sets this to false.
15868 crtc->cpu_fifo_underrun_disabled = true;
15870 * We track the PCH trancoder underrun reporting state
15871 * within the crtc. With crtc for pipe A housing the underrun
15872 * reporting state for PCH transcoder A, crtc for pipe B housing
15873 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15874 * and marking underrun reporting as disabled for the non-existing
15875 * PCH transcoders B and C would prevent enabling the south
15876 * error interrupt (see cpt_can_enable_serr_int()).
15878 if (has_pch_trancoder(dev_priv, crtc->pipe))
15879 crtc->pch_fifo_underrun_disabled = true;
15883 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
15885 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
15888 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
15889 * the hardware when a high res displays plugged in. DPLL P
15890 * divider is zero, and the pipe timings are bonkers. We'll
15891 * try to disable everything in that case.
15893 * FIXME would be nice to be able to sanitize this state
15894 * without several WARNs, but for now let's take the easy
15897 return IS_GEN(dev_priv, 6) &&
15898 crtc_state->base.active &&
15899 crtc_state->shared_dpll &&
15900 crtc_state->port_clock == 0;
15903 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15905 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
15906 struct intel_connector *connector;
15907 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
15908 struct intel_crtc_state *crtc_state = crtc ?
15909 to_intel_crtc_state(crtc->base.state) : NULL;
15911 /* We need to check both for a crtc link (meaning that the
15912 * encoder is active and trying to read from a pipe) and the
15913 * pipe itself being active. */
15914 bool has_active_crtc = crtc_state &&
15915 crtc_state->base.active;
15917 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
15918 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
15919 pipe_name(crtc->pipe));
15920 has_active_crtc = false;
15923 connector = intel_encoder_find_connector(encoder);
15924 if (connector && !has_active_crtc) {
15925 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15926 encoder->base.base.id,
15927 encoder->base.name);
15929 /* Connector is active, but has no active pipe. This is
15930 * fallout from our resume register restoring. Disable
15931 * the encoder manually again. */
15933 struct drm_encoder *best_encoder;
15935 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15936 encoder->base.base.id,
15937 encoder->base.name);
15939 /* avoid oopsing in case the hooks consult best_encoder */
15940 best_encoder = connector->base.state->best_encoder;
15941 connector->base.state->best_encoder = &encoder->base;
15943 if (encoder->disable)
15944 encoder->disable(encoder, crtc_state,
15945 connector->base.state);
15946 if (encoder->post_disable)
15947 encoder->post_disable(encoder, crtc_state,
15948 connector->base.state);
15950 connector->base.state->best_encoder = best_encoder;
15952 encoder->base.crtc = NULL;
15954 /* Inconsistent output/port/pipe state happens presumably due to
15955 * a bug in one of the get_hw_state functions. Or someplace else
15956 * in our code, like the register restore mess on resume. Clamp
15957 * things to off as a safer default. */
15959 connector->base.dpms = DRM_MODE_DPMS_OFF;
15960 connector->base.encoder = NULL;
15963 /* notify opregion of the sanitized encoder state */
15964 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
15966 if (INTEL_GEN(dev_priv) >= 11)
15967 icl_sanitize_encoder_pll_mapping(encoder);
15970 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15972 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15974 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15975 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15976 i915_disable_vga(dev_priv);
15980 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15982 intel_wakeref_t wakeref;
15985 * This function can be called both from intel_modeset_setup_hw_state or
15986 * at a very early point in our resume sequence, where the power well
15987 * structures are not yet restored. Since this function is at a very
15988 * paranoid "someone might have enabled VGA while we were not looking"
15989 * level, just check if the power well is enabled instead of trying to
15990 * follow the "don't touch the power well if we don't need it" policy
15991 * the rest of the driver uses.
15993 wakeref = intel_display_power_get_if_enabled(dev_priv,
15998 i915_redisable_vga_power_on(dev_priv);
16000 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA, wakeref);
16003 /* FIXME read out full plane state for all planes */
16004 static void readout_plane_state(struct drm_i915_private *dev_priv)
16006 struct intel_plane *plane;
16007 struct intel_crtc *crtc;
16009 for_each_intel_plane(&dev_priv->drm, plane) {
16010 struct intel_plane_state *plane_state =
16011 to_intel_plane_state(plane->base.state);
16012 struct intel_crtc_state *crtc_state;
16013 enum pipe pipe = PIPE_A;
16016 visible = plane->get_hw_state(plane, &pipe);
16018 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16019 crtc_state = to_intel_crtc_state(crtc->base.state);
16021 intel_set_plane_visible(crtc_state, plane_state, visible);
16023 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
16024 plane->base.base.id, plane->base.name,
16025 enableddisabled(visible), pipe_name(pipe));
16028 for_each_intel_crtc(&dev_priv->drm, crtc) {
16029 struct intel_crtc_state *crtc_state =
16030 to_intel_crtc_state(crtc->base.state);
16032 fixup_active_planes(crtc_state);
16036 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16038 struct drm_i915_private *dev_priv = to_i915(dev);
16040 struct intel_crtc *crtc;
16041 struct intel_encoder *encoder;
16042 struct intel_connector *connector;
16043 struct drm_connector_list_iter conn_iter;
16046 dev_priv->active_crtcs = 0;
16048 for_each_intel_crtc(dev, crtc) {
16049 struct intel_crtc_state *crtc_state =
16050 to_intel_crtc_state(crtc->base.state);
16052 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16053 memset(crtc_state, 0, sizeof(*crtc_state));
16054 crtc_state->base.crtc = &crtc->base;
16056 crtc_state->base.active = crtc_state->base.enable =
16057 dev_priv->display.get_pipe_config(crtc, crtc_state);
16059 crtc->base.enabled = crtc_state->base.enable;
16060 crtc->active = crtc_state->base.active;
16062 if (crtc_state->base.active)
16063 dev_priv->active_crtcs |= 1 << crtc->pipe;
16065 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16066 crtc->base.base.id, crtc->base.name,
16067 enableddisabled(crtc_state->base.active));
16070 readout_plane_state(dev_priv);
16072 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16073 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16075 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
16076 &pll->state.hw_state);
16077 pll->state.crtc_mask = 0;
16078 for_each_intel_crtc(dev, crtc) {
16079 struct intel_crtc_state *crtc_state =
16080 to_intel_crtc_state(crtc->base.state);
16082 if (crtc_state->base.active &&
16083 crtc_state->shared_dpll == pll)
16084 pll->state.crtc_mask |= 1 << crtc->pipe;
16086 pll->active_mask = pll->state.crtc_mask;
16088 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16089 pll->info->name, pll->state.crtc_mask, pll->on);
16092 for_each_intel_encoder(dev, encoder) {
16095 if (encoder->get_hw_state(encoder, &pipe)) {
16096 struct intel_crtc_state *crtc_state;
16098 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16099 crtc_state = to_intel_crtc_state(crtc->base.state);
16101 encoder->base.crtc = &crtc->base;
16102 encoder->get_config(encoder, crtc_state);
16104 encoder->base.crtc = NULL;
16107 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16108 encoder->base.base.id, encoder->base.name,
16109 enableddisabled(encoder->base.crtc),
16113 drm_connector_list_iter_begin(dev, &conn_iter);
16114 for_each_intel_connector_iter(connector, &conn_iter) {
16115 if (connector->get_hw_state(connector)) {
16116 connector->base.dpms = DRM_MODE_DPMS_ON;
16118 encoder = connector->encoder;
16119 connector->base.encoder = &encoder->base;
16121 if (encoder->base.crtc &&
16122 encoder->base.crtc->state->active) {
16124 * This has to be done during hardware readout
16125 * because anything calling .crtc_disable may
16126 * rely on the connector_mask being accurate.
16128 encoder->base.crtc->state->connector_mask |=
16129 drm_connector_mask(&connector->base);
16130 encoder->base.crtc->state->encoder_mask |=
16131 drm_encoder_mask(&encoder->base);
16135 connector->base.dpms = DRM_MODE_DPMS_OFF;
16136 connector->base.encoder = NULL;
16138 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16139 connector->base.base.id, connector->base.name,
16140 enableddisabled(connector->base.encoder));
16142 drm_connector_list_iter_end(&conn_iter);
16144 for_each_intel_crtc(dev, crtc) {
16145 struct intel_crtc_state *crtc_state =
16146 to_intel_crtc_state(crtc->base.state);
16149 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16150 if (crtc_state->base.active) {
16151 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
16152 crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
16153 crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
16154 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
16155 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16158 * The initial mode needs to be set in order to keep
16159 * the atomic core happy. It wants a valid mode if the
16160 * crtc's enabled, so we do the above call.
16162 * But we don't set all the derived state fully, hence
16163 * set a flag to indicate that a full recalculation is
16164 * needed on the next commit.
16166 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
16168 intel_crtc_compute_pixel_rate(crtc_state);
16170 if (dev_priv->display.modeset_calc_cdclk) {
16171 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
16172 if (WARN_ON(min_cdclk < 0))
16176 drm_calc_timestamping_constants(&crtc->base,
16177 &crtc_state->base.adjusted_mode);
16178 update_scanline_offset(crtc_state);
16181 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
16182 dev_priv->min_voltage_level[crtc->pipe] =
16183 crtc_state->min_voltage_level;
16185 intel_pipe_config_sanity_check(dev_priv, crtc_state);
16190 get_encoder_power_domains(struct drm_i915_private *dev_priv)
16192 struct intel_encoder *encoder;
16194 for_each_intel_encoder(&dev_priv->drm, encoder) {
16195 struct intel_crtc_state *crtc_state;
16197 if (!encoder->get_power_domains)
16201 * MST-primary and inactive encoders don't have a crtc state
16202 * and neither of these require any power domain references.
16204 if (!encoder->base.crtc)
16207 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
16208 encoder->get_power_domains(encoder, crtc_state);
16212 static void intel_early_display_was(struct drm_i915_private *dev_priv)
16214 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
16215 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
16216 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
16219 if (IS_HASWELL(dev_priv)) {
16221 * WaRsPkgCStateDisplayPMReq:hsw
16222 * System hang if this isn't done before disabling all planes!
16224 I915_WRITE(CHICKEN_PAR1_1,
16225 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
16229 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
16230 enum port port, i915_reg_t hdmi_reg)
16232 u32 val = I915_READ(hdmi_reg);
16234 if (val & SDVO_ENABLE ||
16235 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
16238 DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
16241 val &= ~SDVO_PIPE_SEL_MASK;
16242 val |= SDVO_PIPE_SEL(PIPE_A);
16244 I915_WRITE(hdmi_reg, val);
16247 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
16248 enum port port, i915_reg_t dp_reg)
16250 u32 val = I915_READ(dp_reg);
16252 if (val & DP_PORT_EN ||
16253 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
16256 DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
16259 val &= ~DP_PIPE_SEL_MASK;
16260 val |= DP_PIPE_SEL(PIPE_A);
16262 I915_WRITE(dp_reg, val);
16265 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
16268 * The BIOS may select transcoder B on some of the PCH
16269 * ports even it doesn't enable the port. This would trip
16270 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
16271 * Sanitize the transcoder select bits to prevent that. We
16272 * assume that the BIOS never actually enabled the port,
16273 * because if it did we'd actually have to toggle the port
16274 * on and back off to make the transcoder A select stick
16275 * (see. intel_dp_link_down(), intel_disable_hdmi(),
16276 * intel_disable_sdvo()).
16278 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
16279 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
16280 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
16282 /* PCH SDVOB multiplex with HDMIB */
16283 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
16284 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
16285 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
16288 /* Scan out the current hw modeset state,
16289 * and sanitizes it to the current state
16292 intel_modeset_setup_hw_state(struct drm_device *dev,
16293 struct drm_modeset_acquire_ctx *ctx)
16295 struct drm_i915_private *dev_priv = to_i915(dev);
16296 struct intel_crtc_state *crtc_state;
16297 struct intel_encoder *encoder;
16298 struct intel_crtc *crtc;
16299 intel_wakeref_t wakeref;
16302 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
16304 intel_early_display_was(dev_priv);
16305 intel_modeset_readout_hw_state(dev);
16307 /* HW state is read out, now we need to sanitize this mess. */
16308 get_encoder_power_domains(dev_priv);
16310 if (HAS_PCH_IBX(dev_priv))
16311 ibx_sanitize_pch_ports(dev_priv);
16314 * intel_sanitize_plane_mapping() may need to do vblank
16315 * waits, so we need vblank interrupts restored beforehand.
16317 for_each_intel_crtc(&dev_priv->drm, crtc) {
16318 crtc_state = to_intel_crtc_state(crtc->base.state);
16320 drm_crtc_vblank_reset(&crtc->base);
16322 if (crtc_state->base.active)
16323 intel_crtc_vblank_on(crtc_state);
16326 intel_sanitize_plane_mapping(dev_priv);
16328 for_each_intel_encoder(dev, encoder)
16329 intel_sanitize_encoder(encoder);
16331 for_each_intel_crtc(&dev_priv->drm, crtc) {
16332 crtc_state = to_intel_crtc_state(crtc->base.state);
16333 intel_sanitize_crtc(crtc, ctx);
16334 intel_dump_pipe_config(crtc, crtc_state,
16335 "[setup_hw_state]");
16338 intel_modeset_update_connector_atomic_state(dev);
16340 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16341 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16343 if (!pll->on || pll->active_mask)
16346 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
16349 pll->info->funcs->disable(dev_priv, pll);
16353 if (IS_G4X(dev_priv)) {
16354 g4x_wm_get_hw_state(dev_priv);
16355 g4x_wm_sanitize(dev_priv);
16356 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16357 vlv_wm_get_hw_state(dev_priv);
16358 vlv_wm_sanitize(dev_priv);
16359 } else if (INTEL_GEN(dev_priv) >= 9) {
16360 skl_wm_get_hw_state(dev_priv);
16361 } else if (HAS_PCH_SPLIT(dev_priv)) {
16362 ilk_wm_get_hw_state(dev_priv);
16365 for_each_intel_crtc(dev, crtc) {
16368 crtc_state = to_intel_crtc_state(crtc->base.state);
16369 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc_state);
16370 if (WARN_ON(put_domains))
16371 modeset_put_power_domains(dev_priv, put_domains);
16374 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
16376 intel_fbc_init_pipe_state(dev_priv);
16379 void intel_display_resume(struct drm_device *dev)
16381 struct drm_i915_private *dev_priv = to_i915(dev);
16382 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16383 struct drm_modeset_acquire_ctx ctx;
16386 dev_priv->modeset_restore_state = NULL;
16388 state->acquire_ctx = &ctx;
16390 drm_modeset_acquire_init(&ctx, 0);
16393 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16394 if (ret != -EDEADLK)
16397 drm_modeset_backoff(&ctx);
16401 ret = __intel_display_resume(dev, state, &ctx);
16403 intel_enable_ipc(dev_priv);
16404 drm_modeset_drop_locks(&ctx);
16405 drm_modeset_acquire_fini(&ctx);
16408 DRM_ERROR("Restoring old state failed with %i\n", ret);
16410 drm_atomic_state_put(state);
16413 static void intel_hpd_poll_fini(struct drm_device *dev)
16415 struct intel_connector *connector;
16416 struct drm_connector_list_iter conn_iter;
16418 /* Kill all the work that may have been queued by hpd. */
16419 drm_connector_list_iter_begin(dev, &conn_iter);
16420 for_each_intel_connector_iter(connector, &conn_iter) {
16421 if (connector->modeset_retry_work.func)
16422 cancel_work_sync(&connector->modeset_retry_work);
16423 if (connector->hdcp.shim) {
16424 cancel_delayed_work_sync(&connector->hdcp.check_work);
16425 cancel_work_sync(&connector->hdcp.prop_work);
16428 drm_connector_list_iter_end(&conn_iter);
16431 void intel_modeset_cleanup(struct drm_device *dev)
16433 struct drm_i915_private *dev_priv = to_i915(dev);
16435 flush_workqueue(dev_priv->modeset_wq);
16437 flush_work(&dev_priv->atomic_helper.free_work);
16438 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
16441 * Interrupts and polling as the first thing to avoid creating havoc.
16442 * Too much stuff here (turning of connectors, ...) would
16443 * experience fancy races otherwise.
16445 intel_irq_uninstall(dev_priv);
16448 * Due to the hpd irq storm handling the hotplug work can re-arm the
16449 * poll handlers. Hence disable polling after hpd handling is shut down.
16451 intel_hpd_poll_fini(dev);
16453 /* poll work can call into fbdev, hence clean that up afterwards */
16454 intel_fbdev_fini(dev_priv);
16456 intel_unregister_dsm_handler();
16458 intel_fbc_global_disable(dev_priv);
16460 /* flush any delayed tasks or pending work */
16461 flush_scheduled_work();
16463 intel_hdcp_component_fini(dev_priv);
16465 drm_mode_config_cleanup(dev);
16467 intel_overlay_cleanup(dev_priv);
16469 intel_gmbus_teardown(dev_priv);
16471 destroy_workqueue(dev_priv->modeset_wq);
16473 intel_fbc_cleanup_cfb(dev_priv);
16477 * set vga decode state - true == enable VGA decode
16479 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
16481 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16484 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16485 DRM_ERROR("failed to read control word\n");
16489 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16493 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16495 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16497 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16498 DRM_ERROR("failed to write control word\n");
16505 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
16507 struct intel_display_error_state {
16509 u32 power_well_driver;
16511 struct intel_cursor_error_state {
16516 } cursor[I915_MAX_PIPES];
16518 struct intel_pipe_error_state {
16519 bool power_domain_on;
16522 } pipe[I915_MAX_PIPES];
16524 struct intel_plane_error_state {
16532 } plane[I915_MAX_PIPES];
16534 struct intel_transcoder_error_state {
16536 bool power_domain_on;
16537 enum transcoder cpu_transcoder;
16550 struct intel_display_error_state *
16551 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16553 struct intel_display_error_state *error;
16554 int transcoders[] = {
16562 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
16564 if (!HAS_DISPLAY(dev_priv))
16567 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16571 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16572 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
16574 for_each_pipe(dev_priv, i) {
16575 error->pipe[i].power_domain_on =
16576 __intel_display_power_is_enabled(dev_priv,
16577 POWER_DOMAIN_PIPE(i));
16578 if (!error->pipe[i].power_domain_on)
16581 error->cursor[i].control = I915_READ(CURCNTR(i));
16582 error->cursor[i].position = I915_READ(CURPOS(i));
16583 error->cursor[i].base = I915_READ(CURBASE(i));
16585 error->plane[i].control = I915_READ(DSPCNTR(i));
16586 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16587 if (INTEL_GEN(dev_priv) <= 3) {
16588 error->plane[i].size = I915_READ(DSPSIZE(i));
16589 error->plane[i].pos = I915_READ(DSPPOS(i));
16591 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16592 error->plane[i].addr = I915_READ(DSPADDR(i));
16593 if (INTEL_GEN(dev_priv) >= 4) {
16594 error->plane[i].surface = I915_READ(DSPSURF(i));
16595 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16598 error->pipe[i].source = I915_READ(PIPESRC(i));
16600 if (HAS_GMCH(dev_priv))
16601 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16604 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
16605 enum transcoder cpu_transcoder = transcoders[i];
16607 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
16610 error->transcoder[i].available = true;
16611 error->transcoder[i].power_domain_on =
16612 __intel_display_power_is_enabled(dev_priv,
16613 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16614 if (!error->transcoder[i].power_domain_on)
16617 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16619 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16620 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16621 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16622 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16623 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16624 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16625 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16631 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16634 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16635 struct intel_display_error_state *error)
16637 struct drm_i915_private *dev_priv = m->i915;
16643 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
16644 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16645 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16646 error->power_well_driver);
16647 for_each_pipe(dev_priv, i) {
16648 err_printf(m, "Pipe [%d]:\n", i);
16649 err_printf(m, " Power: %s\n",
16650 onoff(error->pipe[i].power_domain_on));
16651 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16652 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16654 err_printf(m, "Plane [%d]:\n", i);
16655 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16656 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16657 if (INTEL_GEN(dev_priv) <= 3) {
16658 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16659 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16661 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16662 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16663 if (INTEL_GEN(dev_priv) >= 4) {
16664 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16665 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16668 err_printf(m, "Cursor [%d]:\n", i);
16669 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16670 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16671 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16674 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
16675 if (!error->transcoder[i].available)
16678 err_printf(m, "CPU transcoder: %s\n",
16679 transcoder_name(error->transcoder[i].cpu_transcoder));
16680 err_printf(m, " Power: %s\n",
16681 onoff(error->transcoder[i].power_domain_on));
16682 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16683 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16684 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16685 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16686 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16687 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16688 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);