drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include "drmP.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "drm_dp_helper.h"
  38
  39 #include "drm_crtc_helper.h"
  40
  41 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  42
  43 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  44 static void intel_update_watermarks(struct drm_device *dev);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  46
  47 typedef struct {
  48     /* given values */
  49     int n;
  50     int m1, m2;
  51     int p1, p2;
  52     /* derived values */
  53     int dot;
  54     int vco;
  55     int m;
  56     int p;
  57 } intel_clock_t;
  58
  59 typedef struct {
  60     int min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64     int dot_limit;
  65     int p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 #define INTEL_P2_NUM                  2
  69 typedef struct intel_limit intel_limit_t;
  70 struct intel_limit {
  71     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  72     intel_p2_t      p2;
  73     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  74                       int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define PINEVIEW_VCO_MIN                1700000
 106 #define PINEVIEW_VCO_MAX                3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* Pineview's Ncounter is a ring counter */
 110 #define PINEVIEW_N_MIN                3
 111 #define PINEVIEW_N_MAX                6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define PINEVIEW_M_MIN                2
 115 #define PINEVIEW_M_MAX              256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* Pineview M1 is reserved, and must be 0 */
 121 #define PINEVIEW_M1_MIN               0
 122 #define PINEVIEW_M1_MAX               0
 123 #define PINEVIEW_M2_MIN               0
 124 #define PINEVIEW_M2_MAX               254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define PINEVIEW_P_LVDS_MIN                   7
 130 #define PINEVIEW_P_LVDS_MAX                  112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* Ironlake / Sandybridge */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IRONLAKE_DOT_MIN         25000
 242 #define IRONLAKE_DOT_MAX         350000
 243 #define IRONLAKE_VCO_MIN         1760000
 244 #define IRONLAKE_VCO_MAX         3510000
 245 #define IRONLAKE_M1_MIN          12
 246 #define IRONLAKE_M1_MAX          22
 247 #define IRONLAKE_M2_MIN          5
 248 #define IRONLAKE_M2_MAX          9
 249 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 250
 251 /* We have parameter ranges for different type of outputs. */
 252
 253 /* DAC & HDMI Refclk 120Mhz */
 254 #define IRONLAKE_DAC_N_MIN      1
 255 #define IRONLAKE_DAC_N_MAX      5
 256 #define IRONLAKE_DAC_M_MIN      79
 257 #define IRONLAKE_DAC_M_MAX      127
 258 #define IRONLAKE_DAC_P_MIN      5
 259 #define IRONLAKE_DAC_P_MAX      80
 260 #define IRONLAKE_DAC_P1_MIN     1
 261 #define IRONLAKE_DAC_P1_MAX     8
 262 #define IRONLAKE_DAC_P2_SLOW    10
 263 #define IRONLAKE_DAC_P2_FAST    5
 264
 265 /* LVDS single-channel 120Mhz refclk */
 266 #define IRONLAKE_LVDS_S_N_MIN   1
 267 #define IRONLAKE_LVDS_S_N_MAX   3
 268 #define IRONLAKE_LVDS_S_M_MIN   79
 269 #define IRONLAKE_LVDS_S_M_MAX   118
 270 #define IRONLAKE_LVDS_S_P_MIN   28
 271 #define IRONLAKE_LVDS_S_P_MAX   112
 272 #define IRONLAKE_LVDS_S_P1_MIN  2
 273 #define IRONLAKE_LVDS_S_P1_MAX  8
 274 #define IRONLAKE_LVDS_S_P2_SLOW 14
 275 #define IRONLAKE_LVDS_S_P2_FAST 14
 276
 277 /* LVDS dual-channel 120Mhz refclk */
 278 #define IRONLAKE_LVDS_D_N_MIN   1
 279 #define IRONLAKE_LVDS_D_N_MAX   3
 280 #define IRONLAKE_LVDS_D_M_MIN   79
 281 #define IRONLAKE_LVDS_D_M_MAX   127
 282 #define IRONLAKE_LVDS_D_P_MIN   14
 283 #define IRONLAKE_LVDS_D_P_MAX   56
 284 #define IRONLAKE_LVDS_D_P1_MIN  2
 285 #define IRONLAKE_LVDS_D_P1_MAX  8
 286 #define IRONLAKE_LVDS_D_P2_SLOW 7
 287 #define IRONLAKE_LVDS_D_P2_FAST 7
 288
 289 /* LVDS single-channel 100Mhz refclk */
 290 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 291 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 292 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 293 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 294 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 295 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 296 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 297 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 298 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 299 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 300
 301 /* LVDS dual-channel 100Mhz refclk */
 302 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 303 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 304 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 305 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 306 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 307 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 308 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 309 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 310 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 311 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 312
 313 /* DisplayPort */
 314 #define IRONLAKE_DP_N_MIN               1
 315 #define IRONLAKE_DP_N_MAX               2
 316 #define IRONLAKE_DP_M_MIN               81
 317 #define IRONLAKE_DP_M_MAX               90
 318 #define IRONLAKE_DP_P_MIN               10
 319 #define IRONLAKE_DP_P_MAX               20
 320 #define IRONLAKE_DP_P2_FAST             10
 321 #define IRONLAKE_DP_P2_SLOW             10
 322 #define IRONLAKE_DP_P2_LIMIT            0
 323 #define IRONLAKE_DP_P1_MIN              1
 324 #define IRONLAKE_DP_P1_MAX              2
 325
 326 static bool
 327 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 328                     int target, int refclk, intel_clock_t *best_clock);
 329 static bool
 330 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 331                         int target, int refclk, intel_clock_t *best_clock);
 332
 333 static bool
 334 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 335                       int target, int refclk, intel_clock_t *best_clock);
 336 static bool
 337 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 338                            int target, int refclk, intel_clock_t *best_clock);
 339
 340 static const intel_limit_t intel_limits_i8xx_dvo = {
 341         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 342         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 343         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 344         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 345         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 346         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 347         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 348         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 349         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 350                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 351         .find_pll = intel_find_best_PLL,
 352 };
 353
 354 static const intel_limit_t intel_limits_i8xx_lvds = {
 355         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 356         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 357         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 358         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 359         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 360         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 361         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 362         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 363         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 364                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 365         .find_pll = intel_find_best_PLL,
 366 };
 367
 368 static const intel_limit_t intel_limits_i9xx_sdvo = {
 369         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 370         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 371         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 372         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 373         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 374         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 375         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 376         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 377         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 378                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 379         .find_pll = intel_find_best_PLL,
 380 };
 381
 382 static const intel_limit_t intel_limits_i9xx_lvds = {
 383         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 384         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 385         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 386         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 387         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 388         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 389         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 390         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 391         /* The single-channel range is 25-112Mhz, and dual-channel
 392          * is 80-224Mhz.  Prefer single channel as much as possible.
 393          */
 394         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 395                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 396         .find_pll = intel_find_best_PLL,
 397 };
 398
 399     /* below parameter and function is for G4X Chipset Family*/
 400 static const intel_limit_t intel_limits_g4x_sdvo = {
 401         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 402         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 403         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 404         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 405         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 406         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 407         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 408         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 409         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 410                  .p2_slow = G4X_P2_SDVO_SLOW,
 411                  .p2_fast = G4X_P2_SDVO_FAST
 412         },
 413         .find_pll = intel_g4x_find_best_PLL,
 414 };
 415
 416 static const intel_limit_t intel_limits_g4x_hdmi = {
 417         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 418         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 419         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 420         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 421         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 422         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 423         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 424         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 425         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 426                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 427                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430 };
 431
 432 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 433         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 434                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 435         .vco = { .min = G4X_VCO_MIN,
 436                  .max = G4X_VCO_MAX },
 437         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 438                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 439         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 440                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 441         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 442                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 443         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 444                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 445         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 447         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 448                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 449         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 450                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 451                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 452         },
 453         .find_pll = intel_g4x_find_best_PLL,
 454 };
 455
 456 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 457         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 458                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 459         .vco = { .min = G4X_VCO_MIN,
 460                  .max = G4X_VCO_MAX },
 461         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 462                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 463         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 464                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 465         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 466                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 467         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 468                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 469         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 471         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 472                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 473         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 474                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 475                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 476         },
 477         .find_pll = intel_g4x_find_best_PLL,
 478 };
 479
 480 static const intel_limit_t intel_limits_g4x_display_port = {
 481         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 482                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 483         .vco = { .min = G4X_VCO_MIN,
 484                  .max = G4X_VCO_MAX},
 485         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 486                  .max = G4X_N_DISPLAY_PORT_MAX },
 487         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 488                  .max = G4X_M_DISPLAY_PORT_MAX },
 489         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 490                  .max = G4X_M1_DISPLAY_PORT_MAX },
 491         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 492                  .max = G4X_M2_DISPLAY_PORT_MAX },
 493         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 494                  .max = G4X_P_DISPLAY_PORT_MAX },
 495         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 496                  .max = G4X_P1_DISPLAY_PORT_MAX},
 497         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 498                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 499                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 500         .find_pll = intel_find_pll_g4x_dp,
 501 };
 502
 503 static const intel_limit_t intel_limits_pineview_sdvo = {
 504         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 505         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 506         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 507         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 508         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 509         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 510         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 511         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 512         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 513                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 514         .find_pll = intel_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t intel_limits_pineview_lvds = {
 518         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 519         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 520         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 521         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 522         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 523         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 524         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 525         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 526         /* Pineview only supports single-channel mode. */
 527         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_ironlake_dac = {
 533         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 534         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 535         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 536         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 537         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 538         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 539         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 540         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 541         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 542                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 543                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 544         .find_pll = intel_g4x_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 551         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 555         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 558                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_display_port = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,
 609                  .max = IRONLAKE_DOT_MAX },
 610         .vco = { .min = IRONLAKE_VCO_MIN,
 611                  .max = IRONLAKE_VCO_MAX},
 612         .n   = { .min = IRONLAKE_DP_N_MIN,
 613                  .max = IRONLAKE_DP_N_MAX },
 614         .m   = { .min = IRONLAKE_DP_M_MIN,
 615                  .max = IRONLAKE_DP_M_MAX },
 616         .m1  = { .min = IRONLAKE_M1_MIN,
 617                  .max = IRONLAKE_M1_MAX },
 618         .m2  = { .min = IRONLAKE_M2_MIN,
 619                  .max = IRONLAKE_M2_MAX },
 620         .p   = { .min = IRONLAKE_DP_P_MIN,
 621                  .max = IRONLAKE_DP_P_MAX },
 622         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 623                  .max = IRONLAKE_DP_P1_MAX},
 624         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 625                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 626                  .p2_fast = IRONLAKE_DP_P2_FAST },
 627         .find_pll = intel_find_pll_ironlake_dp,
 628 };
 629
 630 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 631 {
 632         struct drm_device *dev = crtc->dev;
 633         struct drm_i915_private *dev_priv = dev->dev_private;
 634         const intel_limit_t *limit;
 635         int refclk = 120;
 636
 637         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 638                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 639                         refclk = 100;
 640
 641                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 642                     LVDS_CLKB_POWER_UP) {
 643                         /* LVDS dual channel */
 644                         if (refclk == 100)
 645                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 646                         else
 647                                 limit = &intel_limits_ironlake_dual_lvds;
 648                 } else {
 649                         if (refclk == 100)
 650                                 limit = &intel_limits_ironlake_single_lvds_100m;
 651                         else
 652                                 limit = &intel_limits_ironlake_single_lvds;
 653                 }
 654         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 655                         HAS_eDP)
 656                 limit = &intel_limits_ironlake_display_port;
 657         else
 658                 limit = &intel_limits_ironlake_dac;
 659
 660         return limit;
 661 }
 662
 663 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 664 {
 665         struct drm_device *dev = crtc->dev;
 666         struct drm_i915_private *dev_priv = dev->dev_private;
 667         const intel_limit_t *limit;
 668
 669         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 670                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 671                     LVDS_CLKB_POWER_UP)
 672                         /* LVDS with dual channel */
 673                         limit = &intel_limits_g4x_dual_channel_lvds;
 674                 else
 675                         /* LVDS with dual channel */
 676                         limit = &intel_limits_g4x_single_channel_lvds;
 677         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 678                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 679                 limit = &intel_limits_g4x_hdmi;
 680         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 681                 limit = &intel_limits_g4x_sdvo;
 682         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 683                 limit = &intel_limits_g4x_display_port;
 684         } else /* The option is for other outputs */
 685                 limit = &intel_limits_i9xx_sdvo;
 686
 687         return limit;
 688 }
 689
 690 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 691 {
 692         struct drm_device *dev = crtc->dev;
 693         const intel_limit_t *limit;
 694
 695         if (HAS_PCH_SPLIT(dev))
 696                 limit = intel_ironlake_limit(crtc);
 697         else if (IS_G4X(dev)) {
 698                 limit = intel_g4x_limit(crtc);
 699         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 700                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 701                         limit = &intel_limits_i9xx_lvds;
 702                 else
 703                         limit = &intel_limits_i9xx_sdvo;
 704         } else if (IS_PINEVIEW(dev)) {
 705                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 706                         limit = &intel_limits_pineview_lvds;
 707                 else
 708                         limit = &intel_limits_pineview_sdvo;
 709         } else {
 710                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 711                         limit = &intel_limits_i8xx_lvds;
 712                 else
 713                         limit = &intel_limits_i8xx_dvo;
 714         }
 715         return limit;
 716 }
 717
 718 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 719 static void pineview_clock(int refclk, intel_clock_t *clock)
 720 {
 721         clock->m = clock->m2 + 2;
 722         clock->p = clock->p1 * clock->p2;
 723         clock->vco = refclk * clock->m / clock->n;
 724         clock->dot = clock->vco / clock->p;
 725 }
 726
 727 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 728 {
 729         if (IS_PINEVIEW(dev)) {
 730                 pineview_clock(refclk, clock);
 731                 return;
 732         }
 733         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / (clock->n + 2);
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 /**
 740  * Returns whether any output on the specified pipe is of the specified type
 741  */
 742 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 743 {
 744     struct drm_device *dev = crtc->dev;
 745     struct drm_mode_config *mode_config = &dev->mode_config;
 746     struct drm_encoder *l_entry;
 747
 748     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 749             if (l_entry && l_entry->crtc == crtc) {
 750                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 751                     if (intel_encoder->type == type)
 752                             return true;
 753             }
 754     }
 755     return false;
 756 }
 757
 758 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 759 /**
 760  * Returns whether the given set of divisors are valid for a given refclk with
 761  * the given connectors.
 762  */
 763
 764 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 765 {
 766         const intel_limit_t *limit = intel_limit (crtc);
 767         struct drm_device *dev = crtc->dev;
 768
 769         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 770                 INTELPllInvalid ("p1 out of range\n");
 771         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 772                 INTELPllInvalid ("p out of range\n");
 773         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 774                 INTELPllInvalid ("m2 out of range\n");
 775         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 776                 INTELPllInvalid ("m1 out of range\n");
 777         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 778                 INTELPllInvalid ("m1 <= m2\n");
 779         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 780                 INTELPllInvalid ("m out of range\n");
 781         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 782                 INTELPllInvalid ("n out of range\n");
 783         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 784                 INTELPllInvalid ("vco out of range\n");
 785         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 786          * connector, etc., rather than just a single range.
 787          */
 788         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 789                 INTELPllInvalid ("dot out of range\n");
 790
 791         return true;
 792 }
 793
 794 static bool
 795 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 796                     int target, int refclk, intel_clock_t *best_clock)
 797
 798 {
 799         struct drm_device *dev = crtc->dev;
 800         struct drm_i915_private *dev_priv = dev->dev_private;
 801         intel_clock_t clock;
 802         int err = target;
 803
 804         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 805             (I915_READ(LVDS)) != 0) {
 806                 /*
 807                  * For LVDS, if the panel is on, just rely on its current
 808                  * settings for dual-channel.  We haven't figured out how to
 809                  * reliably set up different single/dual channel state, if we
 810                  * even can.
 811                  */
 812                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 813                     LVDS_CLKB_POWER_UP)
 814                         clock.p2 = limit->p2.p2_fast;
 815                 else
 816                         clock.p2 = limit->p2.p2_slow;
 817         } else {
 818                 if (target < limit->p2.dot_limit)
 819                         clock.p2 = limit->p2.p2_slow;
 820                 else
 821                         clock.p2 = limit->p2.p2_fast;
 822         }
 823
 824         memset (best_clock, 0, sizeof (*best_clock));
 825
 826         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 827              clock.m1++) {
 828                 for (clock.m2 = limit->m2.min;
 829                      clock.m2 <= limit->m2.max; clock.m2++) {
 830                         /* m1 is always 0 in Pineview */
 831                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 832                                 break;
 833                         for (clock.n = limit->n.min;
 834                              clock.n <= limit->n.max; clock.n++) {
 835                                 for (clock.p1 = limit->p1.min;
 836                                         clock.p1 <= limit->p1.max; clock.p1++) {
 837                                         int this_err;
 838
 839                                         intel_clock(dev, refclk, &clock);
 840
 841                                         if (!intel_PLL_is_valid(crtc, &clock))
 842                                                 continue;
 843
 844                                         this_err = abs(clock.dot - target);
 845                                         if (this_err < err) {
 846                                                 *best_clock = clock;
 847                                                 err = this_err;
 848                                         }
 849                                 }
 850                         }
 851                 }
 852         }
 853
 854         return (err != target);
 855 }
 856
 857 static bool
 858 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 859                         int target, int refclk, intel_clock_t *best_clock)
 860 {
 861         struct drm_device *dev = crtc->dev;
 862         struct drm_i915_private *dev_priv = dev->dev_private;
 863         intel_clock_t clock;
 864         int max_n;
 865         bool found;
 866         /* approximately equals target * 0.00488 */
 867         int err_most = (target >> 8) + (target >> 10);
 868         found = false;
 869
 870         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 871                 int lvds_reg;
 872
 873                 if (HAS_PCH_SPLIT(dev))
 874                         lvds_reg = PCH_LVDS;
 875                 else
 876                         lvds_reg = LVDS;
 877                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 878                     LVDS_CLKB_POWER_UP)
 879                         clock.p2 = limit->p2.p2_fast;
 880                 else
 881                         clock.p2 = limit->p2.p2_slow;
 882         } else {
 883                 if (target < limit->p2.dot_limit)
 884                         clock.p2 = limit->p2.p2_slow;
 885                 else
 886                         clock.p2 = limit->p2.p2_fast;
 887         }
 888
 889         memset(best_clock, 0, sizeof(*best_clock));
 890         max_n = limit->n.max;
 891         /* based on hardware requirement, prefer smaller n to precision */
 892         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 893                 /* based on hardware requirement, prefere larger m1,m2 */
 894                 for (clock.m1 = limit->m1.max;
 895                      clock.m1 >= limit->m1.min; clock.m1--) {
 896                         for (clock.m2 = limit->m2.max;
 897                              clock.m2 >= limit->m2.min; clock.m2--) {
 898                                 for (clock.p1 = limit->p1.max;
 899                                      clock.p1 >= limit->p1.min; clock.p1--) {
 900                                         int this_err;
 901
 902                                         intel_clock(dev, refclk, &clock);
 903                                         if (!intel_PLL_is_valid(crtc, &clock))
 904                                                 continue;
 905                                         this_err = abs(clock.dot - target) ;
 906                                         if (this_err < err_most) {
 907                                                 *best_clock = clock;
 908                                                 err_most = this_err;
 909                                                 max_n = clock.n;
 910                                                 found = true;
 911                                         }
 912                                 }
 913                         }
 914                 }
 915         }
 916         return found;
 917 }
 918
 919 static bool
 920 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 921                            int target, int refclk, intel_clock_t *best_clock)
 922 {
 923         struct drm_device *dev = crtc->dev;
 924         intel_clock_t clock;
 925
 926         /* return directly when it is eDP */
 927         if (HAS_eDP)
 928                 return true;
 929
 930         if (target < 200000) {
 931                 clock.n = 1;
 932                 clock.p1 = 2;
 933                 clock.p2 = 10;
 934                 clock.m1 = 12;
 935                 clock.m2 = 9;
 936         } else {
 937                 clock.n = 2;
 938                 clock.p1 = 1;
 939                 clock.p2 = 10;
 940                 clock.m1 = 14;
 941                 clock.m2 = 8;
 942         }
 943         intel_clock(dev, refclk, &clock);
 944         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 945         return true;
 946 }
 947
 948 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 949 static bool
 950 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 951                       int target, int refclk, intel_clock_t *best_clock)
 952 {
 953     intel_clock_t clock;
 954     if (target < 200000) {
 955         clock.p1 = 2;
 956         clock.p2 = 10;
 957         clock.n = 2;
 958         clock.m1 = 23;
 959         clock.m2 = 8;
 960     } else {
 961         clock.p1 = 1;
 962         clock.p2 = 10;
 963         clock.n = 1;
 964         clock.m1 = 14;
 965         clock.m2 = 2;
 966     }
 967     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 968     clock.p = (clock.p1 * clock.p2);
 969     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 970     clock.vco = 0;
 971     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 972     return true;
 973 }
 974
 975 void
 976 intel_wait_for_vblank(struct drm_device *dev)
 977 {
 978         /* Wait for 20ms, i.e. one cycle at 50hz. */
 979         msleep(20);
 980 }
 981
 982 /* Parameters have changed, update FBC info */
 983 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 984 {
 985         struct drm_device *dev = crtc->dev;
 986         struct drm_i915_private *dev_priv = dev->dev_private;
 987         struct drm_framebuffer *fb = crtc->fb;
 988         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 989         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
 990         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 991         int plane, i;
 992         u32 fbc_ctl, fbc_ctl2;
 993
 994         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 995
 996         if (fb->pitch < dev_priv->cfb_pitch)
 997                 dev_priv->cfb_pitch = fb->pitch;
 998
 999         /* FBC_CTL wants 64B units */
1000         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1001         dev_priv->cfb_fence = obj_priv->fence_reg;
1002         dev_priv->cfb_plane = intel_crtc->plane;
1003         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1004
1005         /* Clear old tags */
1006         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1007                 I915_WRITE(FBC_TAG + (i * 4), 0);
1008
1009         /* Set it up... */
1010         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1011         if (obj_priv->tiling_mode != I915_TILING_NONE)
1012                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1013         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1014         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1015
1016         /* enable it... */
1017         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1018         if (IS_I945GM(dev))
1019                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1020         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1021         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1022         if (obj_priv->tiling_mode != I915_TILING_NONE)
1023                 fbc_ctl |= dev_priv->cfb_fence;
1024         I915_WRITE(FBC_CONTROL, fbc_ctl);
1025
1026         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1027                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1028 }
1029
1030 void i8xx_disable_fbc(struct drm_device *dev)
1031 {
1032         struct drm_i915_private *dev_priv = dev->dev_private;
1033         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1034         u32 fbc_ctl;
1035
1036         if (!I915_HAS_FBC(dev))
1037                 return;
1038
1039         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1040                 return; /* Already off, just return */
1041
1042         /* Disable compression */
1043         fbc_ctl = I915_READ(FBC_CONTROL);
1044         fbc_ctl &= ~FBC_CTL_EN;
1045         I915_WRITE(FBC_CONTROL, fbc_ctl);
1046
1047         /* Wait for compressing bit to clear */
1048         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1049                 if (time_after(jiffies, timeout)) {
1050                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1051                         break;
1052                 }
1053                 ; /* do nothing */
1054         }
1055
1056         intel_wait_for_vblank(dev);
1057
1058         DRM_DEBUG_KMS("disabled FBC\n");
1059 }
1060
1061 static bool i8xx_fbc_enabled(struct drm_device *dev)
1062 {
1063         struct drm_i915_private *dev_priv = dev->dev_private;
1064
1065         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1066 }
1067
1068 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1069 {
1070         struct drm_device *dev = crtc->dev;
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         struct drm_framebuffer *fb = crtc->fb;
1073         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1074         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1076         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1077                      DPFC_CTL_PLANEB);
1078         unsigned long stall_watermark = 200;
1079         u32 dpfc_ctl;
1080
1081         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1082         dev_priv->cfb_fence = obj_priv->fence_reg;
1083         dev_priv->cfb_plane = intel_crtc->plane;
1084
1085         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1086         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1087                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1088                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1089         } else {
1090                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1091         }
1092
1093         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1094         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1095                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1096                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1097         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1098
1099         /* enable it... */
1100         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1101
1102         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1103 }
1104
1105 void g4x_disable_fbc(struct drm_device *dev)
1106 {
1107         struct drm_i915_private *dev_priv = dev->dev_private;
1108         u32 dpfc_ctl;
1109
1110         /* Disable compression */
1111         dpfc_ctl = I915_READ(DPFC_CONTROL);
1112         dpfc_ctl &= ~DPFC_CTL_EN;
1113         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1114         intel_wait_for_vblank(dev);
1115
1116         DRM_DEBUG_KMS("disabled FBC\n");
1117 }
1118
1119 static bool g4x_fbc_enabled(struct drm_device *dev)
1120 {
1121         struct drm_i915_private *dev_priv = dev->dev_private;
1122
1123         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1124 }
1125
1126 bool intel_fbc_enabled(struct drm_device *dev)
1127 {
1128         struct drm_i915_private *dev_priv = dev->dev_private;
1129
1130         if (!dev_priv->display.fbc_enabled)
1131                 return false;
1132
1133         return dev_priv->display.fbc_enabled(dev);
1134 }
1135
1136 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1137 {
1138         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1139
1140         if (!dev_priv->display.enable_fbc)
1141                 return;
1142
1143         dev_priv->display.enable_fbc(crtc, interval);
1144 }
1145
1146 void intel_disable_fbc(struct drm_device *dev)
1147 {
1148         struct drm_i915_private *dev_priv = dev->dev_private;
1149
1150         if (!dev_priv->display.disable_fbc)
1151                 return;
1152
1153         dev_priv->display.disable_fbc(dev);
1154 }
1155
1156 /**
1157  * intel_update_fbc - enable/disable FBC as needed
1158  * @crtc: CRTC to point the compressor at
1159  * @mode: mode in use
1160  *
1161  * Set up the framebuffer compression hardware at mode set time.  We
1162  * enable it if possible:
1163  *   - plane A only (on pre-965)
1164  *   - no pixel mulitply/line duplication
1165  *   - no alpha buffer discard
1166  *   - no dual wide
1167  *   - framebuffer <= 2048 in width, 1536 in height
1168  *
1169  * We can't assume that any compression will take place (worst case),
1170  * so the compressed buffer has to be the same size as the uncompressed
1171  * one.  It also must reside (along with the line length buffer) in
1172  * stolen memory.
1173  *
1174  * We need to enable/disable FBC on a global basis.
1175  */
1176 static void intel_update_fbc(struct drm_crtc *crtc,
1177                              struct drm_display_mode *mode)
1178 {
1179         struct drm_device *dev = crtc->dev;
1180         struct drm_i915_private *dev_priv = dev->dev_private;
1181         struct drm_framebuffer *fb = crtc->fb;
1182         struct intel_framebuffer *intel_fb;
1183         struct drm_i915_gem_object *obj_priv;
1184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1185         int plane = intel_crtc->plane;
1186
1187         if (!i915_powersave)
1188                 return;
1189
1190         if (!I915_HAS_FBC(dev))
1191                 return;
1192
1193         if (!crtc->fb)
1194                 return;
1195
1196         intel_fb = to_intel_framebuffer(fb);
1197         obj_priv = to_intel_bo(intel_fb->obj);
1198
1199         /*
1200          * If FBC is already on, we just have to verify that we can
1201          * keep it that way...
1202          * Need to disable if:
1203          *   - changing FBC params (stride, fence, mode)
1204          *   - new fb is too large to fit in compressed buffer
1205          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1206          */
1207         if (intel_fb->obj->size > dev_priv->cfb_size) {
1208                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1209                                 "compression\n");
1210                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1211                 goto out_disable;
1212         }
1213         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1214             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1215                 DRM_DEBUG_KMS("mode incompatible with compression, "
1216                                 "disabling\n");
1217                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1218                 goto out_disable;
1219         }
1220         if ((mode->hdisplay > 2048) ||
1221             (mode->vdisplay > 1536)) {
1222                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1223                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1224                 goto out_disable;
1225         }
1226         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1227                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1228                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1229                 goto out_disable;
1230         }
1231         if (obj_priv->tiling_mode != I915_TILING_X) {
1232                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1233                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1234                 goto out_disable;
1235         }
1236
1237         if (intel_fbc_enabled(dev)) {
1238                 /* We can re-enable it in this case, but need to update pitch */
1239                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1240                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1241                     (plane != dev_priv->cfb_plane))
1242                         intel_disable_fbc(dev);
1243         }
1244
1245         /* Now try to turn it back on if possible */
1246         if (!intel_fbc_enabled(dev))
1247                 intel_enable_fbc(crtc, 500);
1248
1249         return;
1250
1251 out_disable:
1252         /* Multiple disables should be harmless */
1253         if (intel_fbc_enabled(dev)) {
1254                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1255                 intel_disable_fbc(dev);
1256         }
1257 }
1258
1259 static int
1260 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1261 {
1262         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1263         u32 alignment;
1264         int ret;
1265
1266         switch (obj_priv->tiling_mode) {
1267         case I915_TILING_NONE:
1268                 alignment = 64 * 1024;
1269                 break;
1270         case I915_TILING_X:
1271                 /* pin() will align the object as required by fence */
1272                 alignment = 0;
1273                 break;
1274         case I915_TILING_Y:
1275                 /* FIXME: Is this true? */
1276                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1277                 return -EINVAL;
1278         default:
1279                 BUG();
1280         }
1281
1282         ret = i915_gem_object_pin(obj, alignment);
1283         if (ret != 0)
1284                 return ret;
1285
1286         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1287          * fence, whereas 965+ only requires a fence if using
1288          * framebuffer compression.  For simplicity, we always install
1289          * a fence as the cost is not that onerous.
1290          */
1291         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1292             obj_priv->tiling_mode != I915_TILING_NONE) {
1293                 ret = i915_gem_object_get_fence_reg(obj);
1294                 if (ret != 0) {
1295                         i915_gem_object_unpin(obj);
1296                         return ret;
1297                 }
1298         }
1299
1300         return 0;
1301 }
1302
1303 static int
1304 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1305                     struct drm_framebuffer *old_fb)
1306 {
1307         struct drm_device *dev = crtc->dev;
1308         struct drm_i915_private *dev_priv = dev->dev_private;
1309         struct drm_i915_master_private *master_priv;
1310         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1311         struct intel_framebuffer *intel_fb;
1312         struct drm_i915_gem_object *obj_priv;
1313         struct drm_gem_object *obj;
1314         int pipe = intel_crtc->pipe;
1315         int plane = intel_crtc->plane;
1316         unsigned long Start, Offset;
1317         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1318         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1319         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1320         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1321         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1322         u32 dspcntr;
1323         int ret;
1324
1325         /* no fb bound */
1326         if (!crtc->fb) {
1327                 DRM_DEBUG_KMS("No FB bound\n");
1328                 return 0;
1329         }
1330
1331         switch (plane) {
1332         case 0:
1333         case 1:
1334                 break;
1335         default:
1336                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1337                 return -EINVAL;
1338         }
1339
1340         intel_fb = to_intel_framebuffer(crtc->fb);
1341         obj = intel_fb->obj;
1342         obj_priv = to_intel_bo(obj);
1343
1344         mutex_lock(&dev->struct_mutex);
1345         ret = intel_pin_and_fence_fb_obj(dev, obj);
1346         if (ret != 0) {
1347                 mutex_unlock(&dev->struct_mutex);
1348                 return ret;
1349         }
1350
1351         ret = i915_gem_object_set_to_display_plane(obj);
1352         if (ret != 0) {
1353                 i915_gem_object_unpin(obj);
1354                 mutex_unlock(&dev->struct_mutex);
1355                 return ret;
1356         }
1357
1358         dspcntr = I915_READ(dspcntr_reg);
1359         /* Mask out pixel format bits in case we change it */
1360         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1361         switch (crtc->fb->bits_per_pixel) {
1362         case 8:
1363                 dspcntr |= DISPPLANE_8BPP;
1364                 break;
1365         case 16:
1366                 if (crtc->fb->depth == 15)
1367                         dspcntr |= DISPPLANE_15_16BPP;
1368                 else
1369                         dspcntr |= DISPPLANE_16BPP;
1370                 break;
1371         case 24:
1372         case 32:
1373                 if (crtc->fb->depth == 30)
1374                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1375                 else
1376                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1377                 break;
1378         default:
1379                 DRM_ERROR("Unknown color depth\n");
1380                 i915_gem_object_unpin(obj);
1381                 mutex_unlock(&dev->struct_mutex);
1382                 return -EINVAL;
1383         }
1384         if (IS_I965G(dev)) {
1385                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1386                         dspcntr |= DISPPLANE_TILED;
1387                 else
1388                         dspcntr &= ~DISPPLANE_TILED;
1389         }
1390
1391         if (HAS_PCH_SPLIT(dev))
1392                 /* must disable */
1393                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1394
1395         I915_WRITE(dspcntr_reg, dspcntr);
1396
1397         Start = obj_priv->gtt_offset;
1398         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1399
1400         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1401                       Start, Offset, x, y, crtc->fb->pitch);
1402         I915_WRITE(dspstride, crtc->fb->pitch);
1403         if (IS_I965G(dev)) {
1404                 I915_WRITE(dspbase, Offset);
1405                 I915_READ(dspbase);
1406                 I915_WRITE(dspsurf, Start);
1407                 I915_READ(dspsurf);
1408                 I915_WRITE(dsptileoff, (y << 16) | x);
1409         } else {
1410                 I915_WRITE(dspbase, Start + Offset);
1411                 I915_READ(dspbase);
1412         }
1413
1414         if ((IS_I965G(dev) || plane == 0))
1415                 intel_update_fbc(crtc, &crtc->mode);
1416
1417         intel_wait_for_vblank(dev);
1418
1419         if (old_fb) {
1420                 intel_fb = to_intel_framebuffer(old_fb);
1421                 obj_priv = to_intel_bo(intel_fb->obj);
1422                 i915_gem_object_unpin(intel_fb->obj);
1423         }
1424         intel_increase_pllclock(crtc, true);
1425
1426         mutex_unlock(&dev->struct_mutex);
1427
1428         if (!dev->primary->master)
1429                 return 0;
1430
1431         master_priv = dev->primary->master->driver_priv;
1432         if (!master_priv->sarea_priv)
1433                 return 0;
1434
1435         if (pipe) {
1436                 master_priv->sarea_priv->pipeB_x = x;
1437                 master_priv->sarea_priv->pipeB_y = y;
1438         } else {
1439                 master_priv->sarea_priv->pipeA_x = x;
1440                 master_priv->sarea_priv->pipeA_y = y;
1441         }
1442
1443         return 0;
1444 }
1445
1446 /* Disable the VGA plane that we never use */
1447 static void i915_disable_vga (struct drm_device *dev)
1448 {
1449         struct drm_i915_private *dev_priv = dev->dev_private;
1450         u8 sr1;
1451         u32 vga_reg;
1452
1453         if (HAS_PCH_SPLIT(dev))
1454                 vga_reg = CPU_VGACNTRL;
1455         else
1456                 vga_reg = VGACNTRL;
1457
1458         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1459                 return;
1460
1461         I915_WRITE8(VGA_SR_INDEX, 1);
1462         sr1 = I915_READ8(VGA_SR_DATA);
1463         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1464         udelay(100);
1465
1466         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1467 }
1468
1469 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1470 {
1471         struct drm_device *dev = crtc->dev;
1472         struct drm_i915_private *dev_priv = dev->dev_private;
1473         u32 dpa_ctl;
1474
1475         DRM_DEBUG_KMS("\n");
1476         dpa_ctl = I915_READ(DP_A);
1477         dpa_ctl &= ~DP_PLL_ENABLE;
1478         I915_WRITE(DP_A, dpa_ctl);
1479 }
1480
1481 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1482 {
1483         struct drm_device *dev = crtc->dev;
1484         struct drm_i915_private *dev_priv = dev->dev_private;
1485         u32 dpa_ctl;
1486
1487         dpa_ctl = I915_READ(DP_A);
1488         dpa_ctl |= DP_PLL_ENABLE;
1489         I915_WRITE(DP_A, dpa_ctl);
1490         udelay(200);
1491 }
1492
1493
1494 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1495 {
1496         struct drm_device *dev = crtc->dev;
1497         struct drm_i915_private *dev_priv = dev->dev_private;
1498         u32 dpa_ctl;
1499
1500         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1501         dpa_ctl = I915_READ(DP_A);
1502         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1503
1504         if (clock < 200000) {
1505                 u32 temp;
1506                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1507                 /* workaround for 160Mhz:
1508                    1) program 0x4600c bits 15:0 = 0x8124
1509                    2) program 0x46010 bit 0 = 1
1510                    3) program 0x46034 bit 24 = 1
1511                    4) program 0x64000 bit 14 = 1
1512                    */
1513                 temp = I915_READ(0x4600c);
1514                 temp &= 0xffff0000;
1515                 I915_WRITE(0x4600c, temp | 0x8124);
1516
1517                 temp = I915_READ(0x46010);
1518                 I915_WRITE(0x46010, temp | 1);
1519
1520                 temp = I915_READ(0x46034);
1521                 I915_WRITE(0x46034, temp | (1 << 24));
1522         } else {
1523                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1524         }
1525         I915_WRITE(DP_A, dpa_ctl);
1526
1527         udelay(500);
1528 }
1529
1530 /* The FDI link training functions for ILK/Ibexpeak. */
1531 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1532 {
1533         struct drm_device *dev = crtc->dev;
1534         struct drm_i915_private *dev_priv = dev->dev_private;
1535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1536         int pipe = intel_crtc->pipe;
1537         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1538         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1539         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1540         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1541         u32 temp, tries = 0;
1542
1543         /* enable CPU FDI TX and PCH FDI RX */
1544         temp = I915_READ(fdi_tx_reg);
1545         temp |= FDI_TX_ENABLE;
1546         temp &= ~(7 << 19);
1547         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1548         temp &= ~FDI_LINK_TRAIN_NONE;
1549         temp |= FDI_LINK_TRAIN_PATTERN_1;
1550         I915_WRITE(fdi_tx_reg, temp);
1551         I915_READ(fdi_tx_reg);
1552
1553         temp = I915_READ(fdi_rx_reg);
1554         temp &= ~FDI_LINK_TRAIN_NONE;
1555         temp |= FDI_LINK_TRAIN_PATTERN_1;
1556         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1557         I915_READ(fdi_rx_reg);
1558         udelay(150);
1559
1560         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1561            for train result */
1562         temp = I915_READ(fdi_rx_imr_reg);
1563         temp &= ~FDI_RX_SYMBOL_LOCK;
1564         temp &= ~FDI_RX_BIT_LOCK;
1565         I915_WRITE(fdi_rx_imr_reg, temp);
1566         I915_READ(fdi_rx_imr_reg);
1567         udelay(150);
1568
1569         for (;;) {
1570                 temp = I915_READ(fdi_rx_iir_reg);
1571                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1572
1573                 if ((temp & FDI_RX_BIT_LOCK)) {
1574                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1575                         I915_WRITE(fdi_rx_iir_reg,
1576                                    temp | FDI_RX_BIT_LOCK);
1577                         break;
1578                 }
1579
1580                 tries++;
1581
1582                 if (tries > 5) {
1583                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1584                         break;
1585                 }
1586         }
1587
1588         /* Train 2 */
1589         temp = I915_READ(fdi_tx_reg);
1590         temp &= ~FDI_LINK_TRAIN_NONE;
1591         temp |= FDI_LINK_TRAIN_PATTERN_2;
1592         I915_WRITE(fdi_tx_reg, temp);
1593
1594         temp = I915_READ(fdi_rx_reg);
1595         temp &= ~FDI_LINK_TRAIN_NONE;
1596         temp |= FDI_LINK_TRAIN_PATTERN_2;
1597         I915_WRITE(fdi_rx_reg, temp);
1598         udelay(150);
1599
1600         tries = 0;
1601
1602         for (;;) {
1603                 temp = I915_READ(fdi_rx_iir_reg);
1604                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1605
1606                 if (temp & FDI_RX_SYMBOL_LOCK) {
1607                         I915_WRITE(fdi_rx_iir_reg,
1608                                    temp | FDI_RX_SYMBOL_LOCK);
1609                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1610                         break;
1611                 }
1612
1613                 tries++;
1614
1615                 if (tries > 5) {
1616                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1617                         break;
1618                 }
1619         }
1620
1621         DRM_DEBUG_KMS("FDI train done\n");
1622 }
1623
1624 static int snb_b_fdi_train_param [] = {
1625         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1626         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1627         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1628         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1629 };
1630
1631 /* The FDI link training functions for SNB/Cougarpoint. */
1632 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1633 {
1634         struct drm_device *dev = crtc->dev;
1635         struct drm_i915_private *dev_priv = dev->dev_private;
1636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1637         int pipe = intel_crtc->pipe;
1638         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1639         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1640         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1641         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1642         u32 temp, i;
1643
1644         /* enable CPU FDI TX and PCH FDI RX */
1645         temp = I915_READ(fdi_tx_reg);
1646         temp |= FDI_TX_ENABLE;
1647         temp &= ~(7 << 19);
1648         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1649         temp &= ~FDI_LINK_TRAIN_NONE;
1650         temp |= FDI_LINK_TRAIN_PATTERN_1;
1651         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1652         /* SNB-B */
1653         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1654         I915_WRITE(fdi_tx_reg, temp);
1655         I915_READ(fdi_tx_reg);
1656
1657         temp = I915_READ(fdi_rx_reg);
1658         if (HAS_PCH_CPT(dev)) {
1659                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1660                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1661         } else {
1662                 temp &= ~FDI_LINK_TRAIN_NONE;
1663                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1664         }
1665         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1666         I915_READ(fdi_rx_reg);
1667         udelay(150);
1668
1669         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1670            for train result */
1671         temp = I915_READ(fdi_rx_imr_reg);
1672         temp &= ~FDI_RX_SYMBOL_LOCK;
1673         temp &= ~FDI_RX_BIT_LOCK;
1674         I915_WRITE(fdi_rx_imr_reg, temp);
1675         I915_READ(fdi_rx_imr_reg);
1676         udelay(150);
1677
1678         for (i = 0; i < 4; i++ ) {
1679                 temp = I915_READ(fdi_tx_reg);
1680                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1681                 temp |= snb_b_fdi_train_param[i];
1682                 I915_WRITE(fdi_tx_reg, temp);
1683                 udelay(500);
1684
1685                 temp = I915_READ(fdi_rx_iir_reg);
1686                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1687
1688                 if (temp & FDI_RX_BIT_LOCK) {
1689                         I915_WRITE(fdi_rx_iir_reg,
1690                                    temp | FDI_RX_BIT_LOCK);
1691                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1692                         break;
1693                 }
1694         }
1695         if (i == 4)
1696                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1697
1698         /* Train 2 */
1699         temp = I915_READ(fdi_tx_reg);
1700         temp &= ~FDI_LINK_TRAIN_NONE;
1701         temp |= FDI_LINK_TRAIN_PATTERN_2;
1702         if (IS_GEN6(dev)) {
1703                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1704                 /* SNB-B */
1705                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1706         }
1707         I915_WRITE(fdi_tx_reg, temp);
1708
1709         temp = I915_READ(fdi_rx_reg);
1710         if (HAS_PCH_CPT(dev)) {
1711                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1712                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1713         } else {
1714                 temp &= ~FDI_LINK_TRAIN_NONE;
1715                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1716         }
1717         I915_WRITE(fdi_rx_reg, temp);
1718         udelay(150);
1719
1720         for (i = 0; i < 4; i++ ) {
1721                 temp = I915_READ(fdi_tx_reg);
1722                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1723                 temp |= snb_b_fdi_train_param[i];
1724                 I915_WRITE(fdi_tx_reg, temp);
1725                 udelay(500);
1726
1727                 temp = I915_READ(fdi_rx_iir_reg);
1728                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1729
1730                 if (temp & FDI_RX_SYMBOL_LOCK) {
1731                         I915_WRITE(fdi_rx_iir_reg,
1732                                    temp | FDI_RX_SYMBOL_LOCK);
1733                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1734                         break;
1735                 }
1736         }
1737         if (i == 4)
1738                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1739
1740         DRM_DEBUG_KMS("FDI train done.\n");
1741 }
1742
1743 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1744 {
1745         struct drm_device *dev = crtc->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1748         int pipe = intel_crtc->pipe;
1749         int plane = intel_crtc->plane;
1750         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1751         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1752         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1753         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1754         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1755         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1756         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1757         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1758         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1759         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1760         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1761         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1762         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1763         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1764         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1765         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1766         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1767         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1768         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1769         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1770         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1771         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1772         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1773         u32 temp;
1774         int n;
1775         u32 pipe_bpc;
1776
1777         temp = I915_READ(pipeconf_reg);
1778         pipe_bpc = temp & PIPE_BPC_MASK;
1779
1780         /* XXX: When our outputs are all unaware of DPMS modes other than off
1781          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1782          */
1783         switch (mode) {
1784         case DRM_MODE_DPMS_ON:
1785         case DRM_MODE_DPMS_STANDBY:
1786         case DRM_MODE_DPMS_SUSPEND:
1787                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1788
1789                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1790                         temp = I915_READ(PCH_LVDS);
1791                         if ((temp & LVDS_PORT_EN) == 0) {
1792                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1793                                 POSTING_READ(PCH_LVDS);
1794                         }
1795                 }
1796
1797                 if (HAS_eDP) {
1798                         /* enable eDP PLL */
1799                         ironlake_enable_pll_edp(crtc);
1800                 } else {
1801
1802                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1803                         temp = I915_READ(fdi_rx_reg);
1804                         /*
1805                          * make the BPC in FDI Rx be consistent with that in
1806                          * pipeconf reg.
1807                          */
1808                         temp &= ~(0x7 << 16);
1809                         temp |= (pipe_bpc << 11);
1810                         temp &= ~(7 << 19);
1811                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1812                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1813                         I915_READ(fdi_rx_reg);
1814                         udelay(200);
1815
1816                         /* Switch from Rawclk to PCDclk */
1817                         temp = I915_READ(fdi_rx_reg);
1818                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1819                         I915_READ(fdi_rx_reg);
1820                         udelay(200);
1821
1822                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1823                         temp = I915_READ(fdi_tx_reg);
1824                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1825                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1826                                 I915_READ(fdi_tx_reg);
1827                                 udelay(100);
1828                         }
1829                 }
1830
1831                 /* Enable panel fitting for LVDS */
1832                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1833                         temp = I915_READ(pf_ctl_reg);
1834                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1835
1836                         /* currently full aspect */
1837                         I915_WRITE(pf_win_pos, 0);
1838
1839                         I915_WRITE(pf_win_size,
1840                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1841                                    (dev_priv->panel_fixed_mode->vdisplay));
1842                 }
1843
1844                 /* Enable CPU pipe */
1845                 temp = I915_READ(pipeconf_reg);
1846                 if ((temp & PIPEACONF_ENABLE) == 0) {
1847                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1848                         I915_READ(pipeconf_reg);
1849                         udelay(100);
1850                 }
1851
1852                 /* configure and enable CPU plane */
1853                 temp = I915_READ(dspcntr_reg);
1854                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1855                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1856                         /* Flush the plane changes */
1857                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1858                 }
1859
1860                 if (!HAS_eDP) {
1861                         /* For PCH output, training FDI link */
1862                         if (IS_GEN6(dev))
1863                                 gen6_fdi_link_train(crtc);
1864                         else
1865                                 ironlake_fdi_link_train(crtc);
1866
1867                         /* enable PCH DPLL */
1868                         temp = I915_READ(pch_dpll_reg);
1869                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1870                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1871                                 I915_READ(pch_dpll_reg);
1872                         }
1873                         udelay(200);
1874
1875                         if (HAS_PCH_CPT(dev)) {
1876                                 /* Be sure PCH DPLL SEL is set */
1877                                 temp = I915_READ(PCH_DPLL_SEL);
1878                                 if (trans_dpll_sel == 0 &&
1879                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1880                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1881                                 else if (trans_dpll_sel == 1 &&
1882                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1883                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1884                                 I915_WRITE(PCH_DPLL_SEL, temp);
1885                                 I915_READ(PCH_DPLL_SEL);
1886                         }
1887
1888                         /* set transcoder timing */
1889                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1890                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1891                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1892
1893                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1894                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1895                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1896
1897                         /* enable normal train */
1898                         temp = I915_READ(fdi_tx_reg);
1899                         temp &= ~FDI_LINK_TRAIN_NONE;
1900                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1901                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1902                         I915_READ(fdi_tx_reg);
1903
1904                         temp = I915_READ(fdi_rx_reg);
1905                         if (HAS_PCH_CPT(dev)) {
1906                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1907                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1908                         } else {
1909                                 temp &= ~FDI_LINK_TRAIN_NONE;
1910                                 temp |= FDI_LINK_TRAIN_NONE;
1911                         }
1912                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1913                         I915_READ(fdi_rx_reg);
1914
1915                         /* wait one idle pattern time */
1916                         udelay(100);
1917
1918                         /* For PCH DP, enable TRANS_DP_CTL */
1919                         if (HAS_PCH_CPT(dev) &&
1920                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1921                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1922                                 int reg;
1923
1924                                 reg = I915_READ(trans_dp_ctl);
1925                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
1926                                 reg = TRANS_DP_OUTPUT_ENABLE |
1927                                       TRANS_DP_ENH_FRAMING |
1928                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
1929                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
1930
1931                                 switch (intel_trans_dp_port_sel(crtc)) {
1932                                 case PCH_DP_B:
1933                                         reg |= TRANS_DP_PORT_SEL_B;
1934                                         break;
1935                                 case PCH_DP_C:
1936                                         reg |= TRANS_DP_PORT_SEL_C;
1937                                         break;
1938                                 case PCH_DP_D:
1939                                         reg |= TRANS_DP_PORT_SEL_D;
1940                                         break;
1941                                 default:
1942                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1943                                         reg |= TRANS_DP_PORT_SEL_B;
1944                                         break;
1945                                 }
1946
1947                                 I915_WRITE(trans_dp_ctl, reg);
1948                                 POSTING_READ(trans_dp_ctl);
1949                         }
1950
1951                         /* enable PCH transcoder */
1952                         temp = I915_READ(transconf_reg);
1953                         /*
1954                          * make the BPC in transcoder be consistent with
1955                          * that in pipeconf reg.
1956                          */
1957                         temp &= ~PIPE_BPC_MASK;
1958                         temp |= pipe_bpc;
1959                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1960                         I915_READ(transconf_reg);
1961
1962                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1963                                 ;
1964
1965                 }
1966
1967                 intel_crtc_load_lut(crtc);
1968
1969         break;
1970         case DRM_MODE_DPMS_OFF:
1971                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1972
1973                 drm_vblank_off(dev, pipe);
1974                 /* Disable display plane */
1975                 temp = I915_READ(dspcntr_reg);
1976                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1977                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1978                         /* Flush the plane changes */
1979                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1980                         I915_READ(dspbase_reg);
1981                 }
1982
1983                 i915_disable_vga(dev);
1984
1985                 /* disable cpu pipe, disable after all planes disabled */
1986                 temp = I915_READ(pipeconf_reg);
1987                 if ((temp & PIPEACONF_ENABLE) != 0) {
1988                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1989                         I915_READ(pipeconf_reg);
1990                         n = 0;
1991                         /* wait for cpu pipe off, pipe state */
1992                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1993                                 n++;
1994                                 if (n < 60) {
1995                                         udelay(500);
1996                                         continue;
1997                                 } else {
1998                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1999                                                                 pipe);
2000                                         break;
2001                                 }
2002                         }
2003                 } else
2004                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2005
2006                 udelay(100);
2007
2008                 /* Disable PF */
2009                 temp = I915_READ(pf_ctl_reg);
2010                 if ((temp & PF_ENABLE) != 0) {
2011                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2012                         I915_READ(pf_ctl_reg);
2013                 }
2014                 I915_WRITE(pf_win_size, 0);
2015                 POSTING_READ(pf_win_size);
2016
2017
2018                 /* disable CPU FDI tx and PCH FDI rx */
2019                 temp = I915_READ(fdi_tx_reg);
2020                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2021                 I915_READ(fdi_tx_reg);
2022
2023                 temp = I915_READ(fdi_rx_reg);
2024                 /* BPC in FDI rx is consistent with that in pipeconf */
2025                 temp &= ~(0x07 << 16);
2026                 temp |= (pipe_bpc << 11);
2027                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2028                 I915_READ(fdi_rx_reg);
2029
2030                 udelay(100);
2031
2032                 /* still set train pattern 1 */
2033                 temp = I915_READ(fdi_tx_reg);
2034                 temp &= ~FDI_LINK_TRAIN_NONE;
2035                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2036                 I915_WRITE(fdi_tx_reg, temp);
2037                 POSTING_READ(fdi_tx_reg);
2038
2039                 temp = I915_READ(fdi_rx_reg);
2040                 if (HAS_PCH_CPT(dev)) {
2041                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2042                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2043                 } else {
2044                         temp &= ~FDI_LINK_TRAIN_NONE;
2045                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2046                 }
2047                 I915_WRITE(fdi_rx_reg, temp);
2048                 POSTING_READ(fdi_rx_reg);
2049
2050                 udelay(100);
2051
2052                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2053                         temp = I915_READ(PCH_LVDS);
2054                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2055                         I915_READ(PCH_LVDS);
2056                         udelay(100);
2057                 }
2058
2059                 /* disable PCH transcoder */
2060                 temp = I915_READ(transconf_reg);
2061                 if ((temp & TRANS_ENABLE) != 0) {
2062                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2063                         I915_READ(transconf_reg);
2064                         n = 0;
2065                         /* wait for PCH transcoder off, transcoder state */
2066                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2067                                 n++;
2068                                 if (n < 60) {
2069                                         udelay(500);
2070                                         continue;
2071                                 } else {
2072                                         DRM_DEBUG_KMS("transcoder %d off "
2073                                                         "delay\n", pipe);
2074                                         break;
2075                                 }
2076                         }
2077                 }
2078
2079                 temp = I915_READ(transconf_reg);
2080                 /* BPC in transcoder is consistent with that in pipeconf */
2081                 temp &= ~PIPE_BPC_MASK;
2082                 temp |= pipe_bpc;
2083                 I915_WRITE(transconf_reg, temp);
2084                 I915_READ(transconf_reg);
2085                 udelay(100);
2086
2087                 if (HAS_PCH_CPT(dev)) {
2088                         /* disable TRANS_DP_CTL */
2089                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2090                         int reg;
2091
2092                         reg = I915_READ(trans_dp_ctl);
2093                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2094                         I915_WRITE(trans_dp_ctl, reg);
2095                         POSTING_READ(trans_dp_ctl);
2096
2097                         /* disable DPLL_SEL */
2098                         temp = I915_READ(PCH_DPLL_SEL);
2099                         if (trans_dpll_sel == 0)
2100                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2101                         else
2102                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2103                         I915_WRITE(PCH_DPLL_SEL, temp);
2104                         I915_READ(PCH_DPLL_SEL);
2105
2106                 }
2107
2108                 /* disable PCH DPLL */
2109                 temp = I915_READ(pch_dpll_reg);
2110                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2111                 I915_READ(pch_dpll_reg);
2112
2113                 if (HAS_eDP) {
2114                         ironlake_disable_pll_edp(crtc);
2115                 }
2116
2117                 /* Switch from PCDclk to Rawclk */
2118                 temp = I915_READ(fdi_rx_reg);
2119                 temp &= ~FDI_SEL_PCDCLK;
2120                 I915_WRITE(fdi_rx_reg, temp);
2121                 I915_READ(fdi_rx_reg);
2122
2123                 /* Disable CPU FDI TX PLL */
2124                 temp = I915_READ(fdi_tx_reg);
2125                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2126                 I915_READ(fdi_tx_reg);
2127                 udelay(100);
2128
2129                 temp = I915_READ(fdi_rx_reg);
2130                 temp &= ~FDI_RX_PLL_ENABLE;
2131                 I915_WRITE(fdi_rx_reg, temp);
2132                 I915_READ(fdi_rx_reg);
2133
2134                 /* Wait for the clocks to turn off. */
2135                 udelay(100);
2136                 break;
2137         }
2138 }
2139
2140 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2141 {
2142         struct intel_overlay *overlay;
2143         int ret;
2144
2145         if (!enable && intel_crtc->overlay) {
2146                 overlay = intel_crtc->overlay;
2147                 mutex_lock(&overlay->dev->struct_mutex);
2148                 for (;;) {
2149                         ret = intel_overlay_switch_off(overlay);
2150                         if (ret == 0)
2151                                 break;
2152
2153                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2154                         if (ret != 0) {
2155                                 /* overlay doesn't react anymore. Usually
2156                                  * results in a black screen and an unkillable
2157                                  * X server. */
2158                                 BUG();
2159                                 overlay->hw_wedged = HW_WEDGED;
2160                                 break;
2161                         }
2162                 }
2163                 mutex_unlock(&overlay->dev->struct_mutex);
2164         }
2165         /* Let userspace switch the overlay on again. In most cases userspace
2166          * has to recompute where to put it anyway. */
2167
2168         return;
2169 }
2170
2171 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2172 {
2173         struct drm_device *dev = crtc->dev;
2174         struct drm_i915_private *dev_priv = dev->dev_private;
2175         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2176         int pipe = intel_crtc->pipe;
2177         int plane = intel_crtc->plane;
2178         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2179         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2180         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2181         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2182         u32 temp;
2183
2184         /* XXX: When our outputs are all unaware of DPMS modes other than off
2185          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2186          */
2187         switch (mode) {
2188         case DRM_MODE_DPMS_ON:
2189         case DRM_MODE_DPMS_STANDBY:
2190         case DRM_MODE_DPMS_SUSPEND:
2191                 intel_update_watermarks(dev);
2192
2193                 /* Enable the DPLL */
2194                 temp = I915_READ(dpll_reg);
2195                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2196                         I915_WRITE(dpll_reg, temp);
2197                         I915_READ(dpll_reg);
2198                         /* Wait for the clocks to stabilize. */
2199                         udelay(150);
2200                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2201                         I915_READ(dpll_reg);
2202                         /* Wait for the clocks to stabilize. */
2203                         udelay(150);
2204                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2205                         I915_READ(dpll_reg);
2206                         /* Wait for the clocks to stabilize. */
2207                         udelay(150);
2208                 }
2209
2210                 /* Enable the pipe */
2211                 temp = I915_READ(pipeconf_reg);
2212                 if ((temp & PIPEACONF_ENABLE) == 0)
2213                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2214
2215                 /* Enable the plane */
2216                 temp = I915_READ(dspcntr_reg);
2217                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2218                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2219                         /* Flush the plane changes */
2220                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2221                 }
2222
2223                 intel_crtc_load_lut(crtc);
2224
2225                 if ((IS_I965G(dev) || plane == 0))
2226                         intel_update_fbc(crtc, &crtc->mode);
2227
2228                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2229                 intel_crtc_dpms_overlay(intel_crtc, true);
2230         break;
2231         case DRM_MODE_DPMS_OFF:
2232                 intel_update_watermarks(dev);
2233
2234                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2235                 intel_crtc_dpms_overlay(intel_crtc, false);
2236                 drm_vblank_off(dev, pipe);
2237
2238                 if (dev_priv->cfb_plane == plane &&
2239                     dev_priv->display.disable_fbc)
2240                         dev_priv->display.disable_fbc(dev);
2241
2242                 /* Disable the VGA plane that we never use */
2243                 i915_disable_vga(dev);
2244
2245                 /* Disable display plane */
2246                 temp = I915_READ(dspcntr_reg);
2247                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2248                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2249                         /* Flush the plane changes */
2250                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2251                         I915_READ(dspbase_reg);
2252                 }
2253
2254                 if (!IS_I9XX(dev)) {
2255                         /* Wait for vblank for the disable to take effect */
2256                         intel_wait_for_vblank(dev);
2257                 }
2258
2259                 /* Next, disable display pipes */
2260                 temp = I915_READ(pipeconf_reg);
2261                 if ((temp & PIPEACONF_ENABLE) != 0) {
2262                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2263                         I915_READ(pipeconf_reg);
2264                 }
2265
2266                 /* Wait for vblank for the disable to take effect. */
2267                 intel_wait_for_vblank(dev);
2268
2269                 temp = I915_READ(dpll_reg);
2270                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2271                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2272                         I915_READ(dpll_reg);
2273                 }
2274
2275                 /* Wait for the clocks to turn off. */
2276                 udelay(150);
2277                 break;
2278         }
2279 }
2280
2281 /**
2282  * Sets the power management mode of the pipe and plane.
2283  *
2284  * This code should probably grow support for turning the cursor off and back
2285  * on appropriately at the same time as we're turning the pipe off/on.
2286  */
2287 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2288 {
2289         struct drm_device *dev = crtc->dev;
2290         struct drm_i915_private *dev_priv = dev->dev_private;
2291         struct drm_i915_master_private *master_priv;
2292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2293         int pipe = intel_crtc->pipe;
2294         bool enabled;
2295
2296         dev_priv->display.dpms(crtc, mode);
2297
2298         intel_crtc->dpms_mode = mode;
2299
2300         if (!dev->primary->master)
2301                 return;
2302
2303         master_priv = dev->primary->master->driver_priv;
2304         if (!master_priv->sarea_priv)
2305                 return;
2306
2307         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2308
2309         switch (pipe) {
2310         case 0:
2311                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2312                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2313                 break;
2314         case 1:
2315                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2316                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2317                 break;
2318         default:
2319                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2320                 break;
2321         }
2322 }
2323
2324 static void intel_crtc_prepare (struct drm_crtc *crtc)
2325 {
2326         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2327         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2328 }
2329
2330 static void intel_crtc_commit (struct drm_crtc *crtc)
2331 {
2332         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2333         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2334 }
2335
2336 void intel_encoder_prepare (struct drm_encoder *encoder)
2337 {
2338         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2339         /* lvds has its own version of prepare see intel_lvds_prepare */
2340         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2341 }
2342
2343 void intel_encoder_commit (struct drm_encoder *encoder)
2344 {
2345         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2346         /* lvds has its own version of commit see intel_lvds_commit */
2347         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2348 }
2349
2350 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2351                                   struct drm_display_mode *mode,
2352                                   struct drm_display_mode *adjusted_mode)
2353 {
2354         struct drm_device *dev = crtc->dev;
2355         if (HAS_PCH_SPLIT(dev)) {
2356                 /* FDI link clock is fixed at 2.7G */
2357                 if (mode->clock * 3 > 27000 * 4)
2358                         return MODE_CLOCK_HIGH;
2359         }
2360
2361         drm_mode_set_crtcinfo(adjusted_mode, 0);
2362         return true;
2363 }
2364
2365 static int i945_get_display_clock_speed(struct drm_device *dev)
2366 {
2367         return 400000;
2368 }
2369
2370 static int i915_get_display_clock_speed(struct drm_device *dev)
2371 {
2372         return 333000;
2373 }
2374
2375 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2376 {
2377         return 200000;
2378 }
2379
2380 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2381 {
2382         u16 gcfgc = 0;
2383
2384         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2385
2386         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2387                 return 133000;
2388         else {
2389                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2390                 case GC_DISPLAY_CLOCK_333_MHZ:
2391                         return 333000;
2392                 default:
2393                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2394                         return 190000;
2395                 }
2396         }
2397 }
2398
2399 static int i865_get_display_clock_speed(struct drm_device *dev)
2400 {
2401         return 266000;
2402 }
2403
2404 static int i855_get_display_clock_speed(struct drm_device *dev)
2405 {
2406         u16 hpllcc = 0;
2407         /* Assume that the hardware is in the high speed state.  This
2408          * should be the default.
2409          */
2410         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2411         case GC_CLOCK_133_200:
2412         case GC_CLOCK_100_200:
2413                 return 200000;
2414         case GC_CLOCK_166_250:
2415                 return 250000;
2416         case GC_CLOCK_100_133:
2417                 return 133000;
2418         }
2419
2420         /* Shouldn't happen */
2421         return 0;
2422 }
2423
2424 static int i830_get_display_clock_speed(struct drm_device *dev)
2425 {
2426         return 133000;
2427 }
2428
2429 /**
2430  * Return the pipe currently connected to the panel fitter,
2431  * or -1 if the panel fitter is not present or not in use
2432  */
2433 int intel_panel_fitter_pipe (struct drm_device *dev)
2434 {
2435         struct drm_i915_private *dev_priv = dev->dev_private;
2436         u32  pfit_control;
2437
2438         /* i830 doesn't have a panel fitter */
2439         if (IS_I830(dev))
2440                 return -1;
2441
2442         pfit_control = I915_READ(PFIT_CONTROL);
2443
2444         /* See if the panel fitter is in use */
2445         if ((pfit_control & PFIT_ENABLE) == 0)
2446                 return -1;
2447
2448         /* 965 can place panel fitter on either pipe */
2449         if (IS_I965G(dev))
2450                 return (pfit_control >> 29) & 0x3;
2451
2452         /* older chips can only use pipe 1 */
2453         return 1;
2454 }
2455
2456 struct fdi_m_n {
2457         u32        tu;
2458         u32        gmch_m;
2459         u32        gmch_n;
2460         u32        link_m;
2461         u32        link_n;
2462 };
2463
2464 static void
2465 fdi_reduce_ratio(u32 *num, u32 *den)
2466 {
2467         while (*num > 0xffffff || *den > 0xffffff) {
2468                 *num >>= 1;
2469                 *den >>= 1;
2470         }
2471 }
2472
2473 #define DATA_N 0x800000
2474 #define LINK_N 0x80000
2475
2476 static void
2477 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2478                      int link_clock, struct fdi_m_n *m_n)
2479 {
2480         u64 temp;
2481
2482         m_n->tu = 64; /* default size */
2483
2484         temp = (u64) DATA_N * pixel_clock;
2485         temp = div_u64(temp, link_clock);
2486         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2487         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2488         m_n->gmch_n = DATA_N;
2489         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2490
2491         temp = (u64) LINK_N * pixel_clock;
2492         m_n->link_m = div_u64(temp, link_clock);
2493         m_n->link_n = LINK_N;
2494         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2495 }
2496
2497
2498 struct intel_watermark_params {
2499         unsigned long fifo_size;
2500         unsigned long max_wm;
2501         unsigned long default_wm;
2502         unsigned long guard_size;
2503         unsigned long cacheline_size;
2504 };
2505
2506 /* Pineview has different values for various configs */
2507 static struct intel_watermark_params pineview_display_wm = {
2508         PINEVIEW_DISPLAY_FIFO,
2509         PINEVIEW_MAX_WM,
2510         PINEVIEW_DFT_WM,
2511         PINEVIEW_GUARD_WM,
2512         PINEVIEW_FIFO_LINE_SIZE
2513 };
2514 static struct intel_watermark_params pineview_display_hplloff_wm = {
2515         PINEVIEW_DISPLAY_FIFO,
2516         PINEVIEW_MAX_WM,
2517         PINEVIEW_DFT_HPLLOFF_WM,
2518         PINEVIEW_GUARD_WM,
2519         PINEVIEW_FIFO_LINE_SIZE
2520 };
2521 static struct intel_watermark_params pineview_cursor_wm = {
2522         PINEVIEW_CURSOR_FIFO,
2523         PINEVIEW_CURSOR_MAX_WM,
2524         PINEVIEW_CURSOR_DFT_WM,
2525         PINEVIEW_CURSOR_GUARD_WM,
2526         PINEVIEW_FIFO_LINE_SIZE,
2527 };
2528 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2529         PINEVIEW_CURSOR_FIFO,
2530         PINEVIEW_CURSOR_MAX_WM,
2531         PINEVIEW_CURSOR_DFT_WM,
2532         PINEVIEW_CURSOR_GUARD_WM,
2533         PINEVIEW_FIFO_LINE_SIZE
2534 };
2535 static struct intel_watermark_params g4x_wm_info = {
2536         G4X_FIFO_SIZE,
2537         G4X_MAX_WM,
2538         G4X_MAX_WM,
2539         2,
2540         G4X_FIFO_LINE_SIZE,
2541 };
2542 static struct intel_watermark_params i945_wm_info = {
2543         I945_FIFO_SIZE,
2544         I915_MAX_WM,
2545         1,
2546         2,
2547         I915_FIFO_LINE_SIZE
2548 };
2549 static struct intel_watermark_params i915_wm_info = {
2550         I915_FIFO_SIZE,
2551         I915_MAX_WM,
2552         1,
2553         2,
2554         I915_FIFO_LINE_SIZE
2555 };
2556 static struct intel_watermark_params i855_wm_info = {
2557         I855GM_FIFO_SIZE,
2558         I915_MAX_WM,
2559         1,
2560         2,
2561         I830_FIFO_LINE_SIZE
2562 };
2563 static struct intel_watermark_params i830_wm_info = {
2564         I830_FIFO_SIZE,
2565         I915_MAX_WM,
2566         1,
2567         2,
2568         I830_FIFO_LINE_SIZE
2569 };
2570
2571 static struct intel_watermark_params ironlake_display_wm_info = {
2572         ILK_DISPLAY_FIFO,
2573         ILK_DISPLAY_MAXWM,
2574         ILK_DISPLAY_DFTWM,
2575         2,
2576         ILK_FIFO_LINE_SIZE
2577 };
2578
2579 static struct intel_watermark_params ironlake_display_srwm_info = {
2580         ILK_DISPLAY_SR_FIFO,
2581         ILK_DISPLAY_MAX_SRWM,
2582         ILK_DISPLAY_DFT_SRWM,
2583         2,
2584         ILK_FIFO_LINE_SIZE
2585 };
2586
2587 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2588         ILK_CURSOR_SR_FIFO,
2589         ILK_CURSOR_MAX_SRWM,
2590         ILK_CURSOR_DFT_SRWM,
2591         2,
2592         ILK_FIFO_LINE_SIZE
2593 };
2594
2595 /**
2596  * intel_calculate_wm - calculate watermark level
2597  * @clock_in_khz: pixel clock
2598  * @wm: chip FIFO params
2599  * @pixel_size: display pixel size
2600  * @latency_ns: memory latency for the platform
2601  *
2602  * Calculate the watermark level (the level at which the display plane will
2603  * start fetching from memory again).  Each chip has a different display
2604  * FIFO size and allocation, so the caller needs to figure that out and pass
2605  * in the correct intel_watermark_params structure.
2606  *
2607  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2608  * on the pixel size.  When it reaches the watermark level, it'll start
2609  * fetching FIFO line sized based chunks from memory until the FIFO fills
2610  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2611  * will occur, and a display engine hang could result.
2612  */
2613 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2614                                         struct intel_watermark_params *wm,
2615                                         int pixel_size,
2616                                         unsigned long latency_ns)
2617 {
2618         long entries_required, wm_size;
2619
2620         /*
2621          * Note: we need to make sure we don't overflow for various clock &
2622          * latency values.
2623          * clocks go from a few thousand to several hundred thousand.
2624          * latency is usually a few thousand
2625          */
2626         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2627                 1000;
2628         entries_required /= wm->cacheline_size;
2629
2630         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2631
2632         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2633
2634         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2635
2636         /* Don't promote wm_size to unsigned... */
2637         if (wm_size > (long)wm->max_wm)
2638                 wm_size = wm->max_wm;
2639         if (wm_size <= 0)
2640                 wm_size = wm->default_wm;
2641         return wm_size;
2642 }
2643
2644 struct cxsr_latency {
2645         int is_desktop;
2646         int is_ddr3;
2647         unsigned long fsb_freq;
2648         unsigned long mem_freq;
2649         unsigned long display_sr;
2650         unsigned long display_hpll_disable;
2651         unsigned long cursor_sr;
2652         unsigned long cursor_hpll_disable;
2653 };
2654
2655 static struct cxsr_latency cxsr_latency_table[] = {
2656         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2657         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2658         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2659         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2660         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2661
2662         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2663         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2664         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2665         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2666         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2667
2668         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2669         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2670         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2671         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2672         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2673
2674         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2675         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2676         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2677         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2678         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2679
2680         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2681         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2682         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2683         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2684         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2685
2686         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2687         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2688         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2689         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2690         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2691 };
2692
2693 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2694                                                    int fsb, int mem)
2695 {
2696         int i;
2697         struct cxsr_latency *latency;
2698
2699         if (fsb == 0 || mem == 0)
2700                 return NULL;
2701
2702         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2703                 latency = &cxsr_latency_table[i];
2704                 if (is_desktop == latency->is_desktop &&
2705                     is_ddr3 == latency->is_ddr3 &&
2706                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2707                         return latency;
2708         }
2709
2710         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2711
2712         return NULL;
2713 }
2714
2715 static void pineview_disable_cxsr(struct drm_device *dev)
2716 {
2717         struct drm_i915_private *dev_priv = dev->dev_private;
2718         u32 reg;
2719
2720         /* deactivate cxsr */
2721         reg = I915_READ(DSPFW3);
2722         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2723         I915_WRITE(DSPFW3, reg);
2724         DRM_INFO("Big FIFO is disabled\n");
2725 }
2726
2727 /*
2728  * Latency for FIFO fetches is dependent on several factors:
2729  *   - memory configuration (speed, channels)
2730  *   - chipset
2731  *   - current MCH state
2732  * It can be fairly high in some situations, so here we assume a fairly
2733  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2734  * set this value too high, the FIFO will fetch frequently to stay full)
2735  * and power consumption (set it too low to save power and we might see
2736  * FIFO underruns and display "flicker").
2737  *
2738  * A value of 5us seems to be a good balance; safe for very low end
2739  * platforms but not overly aggressive on lower latency configs.
2740  */
2741 static const int latency_ns = 5000;
2742
2743 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2744 {
2745         struct drm_i915_private *dev_priv = dev->dev_private;
2746         uint32_t dsparb = I915_READ(DSPARB);
2747         int size;
2748
2749         if (plane == 0)
2750                 size = dsparb & 0x7f;
2751         else
2752                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2753                         (dsparb & 0x7f);
2754
2755         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2756                         plane ? "B" : "A", size);
2757
2758         return size;
2759 }
2760
2761 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2762 {
2763         struct drm_i915_private *dev_priv = dev->dev_private;
2764         uint32_t dsparb = I915_READ(DSPARB);
2765         int size;
2766
2767         if (plane == 0)
2768                 size = dsparb & 0x1ff;
2769         else
2770                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2771                         (dsparb & 0x1ff);
2772         size >>= 1; /* Convert to cachelines */
2773
2774         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2775                         plane ? "B" : "A", size);
2776
2777         return size;
2778 }
2779
2780 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2781 {
2782         struct drm_i915_private *dev_priv = dev->dev_private;
2783         uint32_t dsparb = I915_READ(DSPARB);
2784         int size;
2785
2786         size = dsparb & 0x7f;
2787         size >>= 2; /* Convert to cachelines */
2788
2789         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2790                         plane ? "B" : "A",
2791                   size);
2792
2793         return size;
2794 }
2795
2796 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2797 {
2798         struct drm_i915_private *dev_priv = dev->dev_private;
2799         uint32_t dsparb = I915_READ(DSPARB);
2800         int size;
2801
2802         size = dsparb & 0x7f;
2803         size >>= 1; /* Convert to cachelines */
2804
2805         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2806                         plane ? "B" : "A", size);
2807
2808         return size;
2809 }
2810
2811 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2812                           int planeb_clock, int sr_hdisplay, int pixel_size)
2813 {
2814         struct drm_i915_private *dev_priv = dev->dev_private;
2815         u32 reg;
2816         unsigned long wm;
2817         struct cxsr_latency *latency;
2818         int sr_clock;
2819
2820         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2821                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2822         if (!latency) {
2823                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2824                 pineview_disable_cxsr(dev);
2825                 return;
2826         }
2827
2828         if (!planea_clock || !planeb_clock) {
2829                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2830
2831                 /* Display SR */
2832                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2833                                         pixel_size, latency->display_sr);
2834                 reg = I915_READ(DSPFW1);
2835                 reg &= ~DSPFW_SR_MASK;
2836                 reg |= wm << DSPFW_SR_SHIFT;
2837                 I915_WRITE(DSPFW1, reg);
2838                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2839
2840                 /* cursor SR */
2841                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2842                                         pixel_size, latency->cursor_sr);
2843                 reg = I915_READ(DSPFW3);
2844                 reg &= ~DSPFW_CURSOR_SR_MASK;
2845                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2846                 I915_WRITE(DSPFW3, reg);
2847
2848                 /* Display HPLL off SR */
2849                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2850                                         pixel_size, latency->display_hpll_disable);
2851                 reg = I915_READ(DSPFW3);
2852                 reg &= ~DSPFW_HPLL_SR_MASK;
2853                 reg |= wm & DSPFW_HPLL_SR_MASK;
2854                 I915_WRITE(DSPFW3, reg);
2855
2856                 /* cursor HPLL off SR */
2857                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2858                                         pixel_size, latency->cursor_hpll_disable);
2859                 reg = I915_READ(DSPFW3);
2860                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2861                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2862                 I915_WRITE(DSPFW3, reg);
2863                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2864
2865                 /* activate cxsr */
2866                 reg = I915_READ(DSPFW3);
2867                 reg |= PINEVIEW_SELF_REFRESH_EN;
2868                 I915_WRITE(DSPFW3, reg);
2869                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2870         } else {
2871                 pineview_disable_cxsr(dev);
2872                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2873         }
2874 }
2875
2876 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2877                           int planeb_clock, int sr_hdisplay, int pixel_size)
2878 {
2879         struct drm_i915_private *dev_priv = dev->dev_private;
2880         int total_size, cacheline_size;
2881         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2882         struct intel_watermark_params planea_params, planeb_params;
2883         unsigned long line_time_us;
2884         int sr_clock, sr_entries = 0, entries_required;
2885
2886         /* Create copies of the base settings for each pipe */
2887         planea_params = planeb_params = g4x_wm_info;
2888
2889         /* Grab a couple of global values before we overwrite them */
2890         total_size = planea_params.fifo_size;
2891         cacheline_size = planea_params.cacheline_size;
2892
2893         /*
2894          * Note: we need to make sure we don't overflow for various clock &
2895          * latency values.
2896          * clocks go from a few thousand to several hundred thousand.
2897          * latency is usually a few thousand
2898          */
2899         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2900                 1000;
2901         entries_required /= G4X_FIFO_LINE_SIZE;
2902         planea_wm = entries_required + planea_params.guard_size;
2903
2904         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2905                 1000;
2906         entries_required /= G4X_FIFO_LINE_SIZE;
2907         planeb_wm = entries_required + planeb_params.guard_size;
2908
2909         cursora_wm = cursorb_wm = 16;
2910         cursor_sr = 32;
2911
2912         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2913
2914         /* Calc sr entries for one plane configs */
2915         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2916                 /* self-refresh has much higher latency */
2917                 static const int sr_latency_ns = 12000;
2918
2919                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2920                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2921
2922                 /* Use ns/us then divide to preserve precision */
2923                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2924                               pixel_size * sr_hdisplay) / 1000;
2925                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2926                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2927                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2928         } else {
2929                 /* Turn off self refresh if both pipes are enabled */
2930                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2931                                         & ~FW_BLC_SELF_EN);
2932         }
2933
2934         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2935                   planea_wm, planeb_wm, sr_entries);
2936
2937         planea_wm &= 0x3f;
2938         planeb_wm &= 0x3f;
2939
2940         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2941                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2942                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2943         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2944                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2945         /* HPLL off in SR has some issues on G4x... disable it */
2946         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2947                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2948 }
2949
2950 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2951                            int planeb_clock, int sr_hdisplay, int pixel_size)
2952 {
2953         struct drm_i915_private *dev_priv = dev->dev_private;
2954         unsigned long line_time_us;
2955         int sr_clock, sr_entries, srwm = 1;
2956
2957         /* Calc sr entries for one plane configs */
2958         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2959                 /* self-refresh has much higher latency */
2960                 static const int sr_latency_ns = 12000;
2961
2962                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2963                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2964
2965                 /* Use ns/us then divide to preserve precision */
2966                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2967                               pixel_size * sr_hdisplay) / 1000;
2968                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2969                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2970                 srwm = I945_FIFO_SIZE - sr_entries;
2971                 if (srwm < 0)
2972                         srwm = 1;
2973                 srwm &= 0x3f;
2974                 if (IS_I965GM(dev))
2975                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2976         } else {
2977                 /* Turn off self refresh if both pipes are enabled */
2978                 if (IS_I965GM(dev))
2979                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2980                                    & ~FW_BLC_SELF_EN);
2981         }
2982
2983         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2984                       srwm);
2985
2986         /* 965 has limitations... */
2987         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2988                    (8 << 0));
2989         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2990 }
2991
2992 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2993                            int planeb_clock, int sr_hdisplay, int pixel_size)
2994 {
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996         uint32_t fwater_lo;
2997         uint32_t fwater_hi;
2998         int total_size, cacheline_size, cwm, srwm = 1;
2999         int planea_wm, planeb_wm;
3000         struct intel_watermark_params planea_params, planeb_params;
3001         unsigned long line_time_us;
3002         int sr_clock, sr_entries = 0;
3003
3004         /* Create copies of the base settings for each pipe */
3005         if (IS_I965GM(dev) || IS_I945GM(dev))
3006                 planea_params = planeb_params = i945_wm_info;
3007         else if (IS_I9XX(dev))
3008                 planea_params = planeb_params = i915_wm_info;
3009         else
3010                 planea_params = planeb_params = i855_wm_info;
3011
3012         /* Grab a couple of global values before we overwrite them */
3013         total_size = planea_params.fifo_size;
3014         cacheline_size = planea_params.cacheline_size;
3015
3016         /* Update per-plane FIFO sizes */
3017         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3018         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3019
3020         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3021                                        pixel_size, latency_ns);
3022         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3023                                        pixel_size, latency_ns);
3024         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3025
3026         /*
3027          * Overlay gets an aggressive default since video jitter is bad.
3028          */
3029         cwm = 2;
3030
3031         /* Calc sr entries for one plane configs */
3032         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3033             (!planea_clock || !planeb_clock)) {
3034                 /* self-refresh has much higher latency */
3035                 static const int sr_latency_ns = 6000;
3036
3037                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3038                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3039
3040                 /* Use ns/us then divide to preserve precision */
3041                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3042                               pixel_size * sr_hdisplay) / 1000;
3043                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3044                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3045                 srwm = total_size - sr_entries;
3046                 if (srwm < 0)
3047                         srwm = 1;
3048
3049                 if (IS_I945G(dev) || IS_I945GM(dev))
3050                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3051                 else if (IS_I915GM(dev)) {
3052                         /* 915M has a smaller SRWM field */
3053                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3054                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3055                 }
3056         } else {
3057                 /* Turn off self refresh if both pipes are enabled */
3058                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3059                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3060                                    & ~FW_BLC_SELF_EN);
3061                 } else if (IS_I915GM(dev)) {
3062                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3063                 }
3064         }
3065
3066         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3067                   planea_wm, planeb_wm, cwm, srwm);
3068
3069         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3070         fwater_hi = (cwm & 0x1f);
3071
3072         /* Set request length to 8 cachelines per fetch */
3073         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3074         fwater_hi = fwater_hi | (1 << 8);
3075
3076         I915_WRITE(FW_BLC, fwater_lo);
3077         I915_WRITE(FW_BLC2, fwater_hi);
3078 }
3079
3080 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3081                            int unused2, int pixel_size)
3082 {
3083         struct drm_i915_private *dev_priv = dev->dev_private;
3084         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3085         int planea_wm;
3086
3087         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3088
3089         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3090                                        pixel_size, latency_ns);
3091         fwater_lo |= (3<<8) | planea_wm;
3092
3093         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3094
3095         I915_WRITE(FW_BLC, fwater_lo);
3096 }
3097
3098 #define ILK_LP0_PLANE_LATENCY           700
3099
3100 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3101                        int planeb_clock, int sr_hdisplay, int pixel_size)
3102 {
3103         struct drm_i915_private *dev_priv = dev->dev_private;
3104         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3105         int sr_wm, cursor_wm;
3106         unsigned long line_time_us;
3107         int sr_clock, entries_required;
3108         u32 reg_value;
3109
3110         /* Calculate and update the watermark for plane A */
3111         if (planea_clock) {
3112                 entries_required = ((planea_clock / 1000) * pixel_size *
3113                                      ILK_LP0_PLANE_LATENCY) / 1000;
3114                 entries_required = DIV_ROUND_UP(entries_required,
3115                                    ironlake_display_wm_info.cacheline_size);
3116                 planea_wm = entries_required +
3117                             ironlake_display_wm_info.guard_size;
3118
3119                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3120                         planea_wm = ironlake_display_wm_info.max_wm;
3121
3122                 cursora_wm = 16;
3123                 reg_value = I915_READ(WM0_PIPEA_ILK);
3124                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3125                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3126                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3127                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3128                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3129                                 "cursor: %d\n", planea_wm, cursora_wm);
3130         }
3131         /* Calculate and update the watermark for plane B */
3132         if (planeb_clock) {
3133                 entries_required = ((planeb_clock / 1000) * pixel_size *
3134                                      ILK_LP0_PLANE_LATENCY) / 1000;
3135                 entries_required = DIV_ROUND_UP(entries_required,
3136                                    ironlake_display_wm_info.cacheline_size);
3137                 planeb_wm = entries_required +
3138                             ironlake_display_wm_info.guard_size;
3139
3140                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3141                         planeb_wm = ironlake_display_wm_info.max_wm;
3142
3143                 cursorb_wm = 16;
3144                 reg_value = I915_READ(WM0_PIPEB_ILK);
3145                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3146                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3147                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3148                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3149                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3150                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3151         }
3152
3153         /*
3154          * Calculate and update the self-refresh watermark only when one
3155          * display plane is used.
3156          */
3157         if (!planea_clock || !planeb_clock) {
3158                 int line_count;
3159                 /* Read the self-refresh latency. The unit is 0.5us */
3160                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3161
3162                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3163                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3164
3165                 /* Use ns/us then divide to preserve precision */
3166                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3167                                / 1000;
3168
3169                 /* calculate the self-refresh watermark for display plane */
3170                 entries_required = line_count * sr_hdisplay * pixel_size;
3171                 entries_required = DIV_ROUND_UP(entries_required,
3172                                    ironlake_display_srwm_info.cacheline_size);
3173                 sr_wm = entries_required +
3174                         ironlake_display_srwm_info.guard_size;
3175
3176                 /* calculate the self-refresh watermark for display cursor */
3177                 entries_required = line_count * pixel_size * 64;
3178                 entries_required = DIV_ROUND_UP(entries_required,
3179                                    ironlake_cursor_srwm_info.cacheline_size);
3180                 cursor_wm = entries_required +
3181                             ironlake_cursor_srwm_info.guard_size;
3182
3183                 /* configure watermark and enable self-refresh */
3184                 reg_value = I915_READ(WM1_LP_ILK);
3185                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3186                                WM1_LP_CURSOR_MASK);
3187                 reg_value |= WM1_LP_SR_EN |
3188                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3189                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3190
3191                 I915_WRITE(WM1_LP_ILK, reg_value);
3192                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3193                                 "cursor %d\n", sr_wm, cursor_wm);
3194
3195         } else {
3196                 /* Turn off self refresh if both pipes are enabled */
3197                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3198         }
3199 }
3200 /**
3201  * intel_update_watermarks - update FIFO watermark values based on current modes
3202  *
3203  * Calculate watermark values for the various WM regs based on current mode
3204  * and plane configuration.
3205  *
3206  * There are several cases to deal with here:
3207  *   - normal (i.e. non-self-refresh)
3208  *   - self-refresh (SR) mode
3209  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3210  *   - lines are small relative to FIFO size (buffer can hold more than 2
3211  *     lines), so need to account for TLB latency
3212  *
3213  *   The normal calculation is:
3214  *     watermark = dotclock * bytes per pixel * latency
3215  *   where latency is platform & configuration dependent (we assume pessimal
3216  *   values here).
3217  *
3218  *   The SR calculation is:
3219  *     watermark = (trunc(latency/line time)+1) * surface width *
3220  *       bytes per pixel
3221  *   where
3222  *     line time = htotal / dotclock
3223  *   and latency is assumed to be high, as above.
3224  *
3225  * The final value programmed to the register should always be rounded up,
3226  * and include an extra 2 entries to account for clock crossings.
3227  *
3228  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3229  * to set the non-SR watermarks to 8.
3230   */
3231 static void intel_update_watermarks(struct drm_device *dev)
3232 {
3233         struct drm_i915_private *dev_priv = dev->dev_private;
3234         struct drm_crtc *crtc;
3235         struct intel_crtc *intel_crtc;
3236         int sr_hdisplay = 0;
3237         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3238         int enabled = 0, pixel_size = 0;
3239
3240         if (!dev_priv->display.update_wm)
3241                 return;
3242
3243         /* Get the clock config from both planes */
3244         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3245                 intel_crtc = to_intel_crtc(crtc);
3246                 if (crtc->enabled) {
3247                         enabled++;
3248                         if (intel_crtc->plane == 0) {
3249                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3250                                           intel_crtc->pipe, crtc->mode.clock);
3251                                 planea_clock = crtc->mode.clock;
3252                         } else {
3253                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3254                                           intel_crtc->pipe, crtc->mode.clock);
3255                                 planeb_clock = crtc->mode.clock;
3256                         }
3257                         sr_hdisplay = crtc->mode.hdisplay;
3258                         sr_clock = crtc->mode.clock;
3259                         if (crtc->fb)
3260                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3261                         else
3262                                 pixel_size = 4; /* by default */
3263                 }
3264         }
3265
3266         if (enabled <= 0)
3267                 return;
3268
3269         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3270                                     sr_hdisplay, pixel_size);
3271 }
3272
3273 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3274                                struct drm_display_mode *mode,
3275                                struct drm_display_mode *adjusted_mode,
3276                                int x, int y,
3277                                struct drm_framebuffer *old_fb)
3278 {
3279         struct drm_device *dev = crtc->dev;
3280         struct drm_i915_private *dev_priv = dev->dev_private;
3281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3282         int pipe = intel_crtc->pipe;
3283         int plane = intel_crtc->plane;
3284         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3285         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3286         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3287         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3288         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3289         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3290         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3291         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3292         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3293         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3294         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3295         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3296         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3297         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3298         int refclk, num_connectors = 0;
3299         intel_clock_t clock, reduced_clock;
3300         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3301         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3302         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3303         bool is_edp = false;
3304         struct drm_mode_config *mode_config = &dev->mode_config;
3305         struct drm_encoder *encoder;
3306         struct intel_encoder *intel_encoder = NULL;
3307         const intel_limit_t *limit;
3308         int ret;
3309         struct fdi_m_n m_n = {0};
3310         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3311         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3312         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3313         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3314         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3315         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3316         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3317         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3318         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3319         int lvds_reg = LVDS;
3320         u32 temp;
3321         int sdvo_pixel_multiply;
3322         int target_clock;
3323
3324         drm_vblank_pre_modeset(dev, pipe);
3325
3326         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3327
3328                 if (!encoder || encoder->crtc != crtc)
3329                         continue;
3330
3331                 intel_encoder = enc_to_intel_encoder(encoder);
3332
3333                 switch (intel_encoder->type) {
3334                 case INTEL_OUTPUT_LVDS:
3335                         is_lvds = true;
3336                         break;
3337                 case INTEL_OUTPUT_SDVO:
3338                 case INTEL_OUTPUT_HDMI:
3339                         is_sdvo = true;
3340                         if (intel_encoder->needs_tv_clock)
3341                                 is_tv = true;
3342                         break;
3343                 case INTEL_OUTPUT_DVO:
3344                         is_dvo = true;
3345                         break;
3346                 case INTEL_OUTPUT_TVOUT:
3347                         is_tv = true;
3348                         break;
3349                 case INTEL_OUTPUT_ANALOG:
3350                         is_crt = true;
3351                         break;
3352                 case INTEL_OUTPUT_DISPLAYPORT:
3353                         is_dp = true;
3354                         break;
3355                 case INTEL_OUTPUT_EDP:
3356                         is_edp = true;
3357                         break;
3358                 }
3359
3360                 num_connectors++;
3361         }
3362
3363         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3364                 refclk = dev_priv->lvds_ssc_freq * 1000;
3365                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3366                                         refclk / 1000);
3367         } else if (IS_I9XX(dev)) {
3368                 refclk = 96000;
3369                 if (HAS_PCH_SPLIT(dev))
3370                         refclk = 120000; /* 120Mhz refclk */
3371         } else {
3372                 refclk = 48000;
3373         }
3374
3375
3376         /*
3377          * Returns a set of divisors for the desired target clock with the given
3378          * refclk, or FALSE.  The returned values represent the clock equation:
3379          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3380          */
3381         limit = intel_limit(crtc);
3382         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3383         if (!ok) {
3384                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3385                 drm_vblank_post_modeset(dev, pipe);
3386                 return -EINVAL;
3387         }
3388
3389         if (is_lvds && dev_priv->lvds_downclock_avail) {
3390                 has_reduced_clock = limit->find_pll(limit, crtc,
3391                                                             dev_priv->lvds_downclock,
3392                                                             refclk,
3393                                                             &reduced_clock);
3394                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3395                         /*
3396                          * If the different P is found, it means that we can't
3397                          * switch the display clock by using the FP0/FP1.
3398                          * In such case we will disable the LVDS downclock
3399                          * feature.
3400                          */
3401                         DRM_DEBUG_KMS("Different P is found for "
3402                                                 "LVDS clock/downclock\n");
3403                         has_reduced_clock = 0;
3404                 }
3405         }
3406         /* SDVO TV has fixed PLL values depend on its clock range,
3407            this mirrors vbios setting. */
3408         if (is_sdvo && is_tv) {
3409                 if (adjusted_mode->clock >= 100000
3410                                 && adjusted_mode->clock < 140500) {
3411                         clock.p1 = 2;
3412                         clock.p2 = 10;
3413                         clock.n = 3;
3414                         clock.m1 = 16;
3415                         clock.m2 = 8;
3416                 } else if (adjusted_mode->clock >= 140500
3417                                 && adjusted_mode->clock <= 200000) {
3418                         clock.p1 = 1;
3419                         clock.p2 = 10;
3420                         clock.n = 6;
3421                         clock.m1 = 12;
3422                         clock.m2 = 8;
3423                 }
3424         }
3425
3426         /* FDI link */
3427         if (HAS_PCH_SPLIT(dev)) {
3428                 int lane = 0, link_bw, bpp;
3429                 /* eDP doesn't require FDI link, so just set DP M/N
3430                    according to current link config */
3431                 if (is_edp) {
3432                         target_clock = mode->clock;
3433                         intel_edp_link_config(intel_encoder,
3434                                         &lane, &link_bw);
3435                 } else {
3436                         /* DP over FDI requires target mode clock
3437                            instead of link clock */
3438                         if (is_dp)
3439                                 target_clock = mode->clock;
3440                         else
3441                                 target_clock = adjusted_mode->clock;
3442                         link_bw = 270000;
3443                 }
3444
3445                 /* determine panel color depth */
3446                 temp = I915_READ(pipeconf_reg);
3447                 temp &= ~PIPE_BPC_MASK;
3448                 if (is_lvds) {
3449                         int lvds_reg = I915_READ(PCH_LVDS);
3450                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3451                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3452                                 temp |= PIPE_8BPC;
3453                         else
3454                                 temp |= PIPE_6BPC;
3455                 } else if (is_edp) {
3456                         switch (dev_priv->edp_bpp/3) {
3457                         case 8:
3458                                 temp |= PIPE_8BPC;
3459                                 break;
3460                         case 10:
3461                                 temp |= PIPE_10BPC;
3462                                 break;
3463                         case 6:
3464                                 temp |= PIPE_6BPC;
3465                                 break;
3466                         case 12:
3467                                 temp |= PIPE_12BPC;
3468                                 break;
3469                         }
3470                 } else
3471                         temp |= PIPE_8BPC;
3472                 I915_WRITE(pipeconf_reg, temp);
3473                 I915_READ(pipeconf_reg);
3474
3475                 switch (temp & PIPE_BPC_MASK) {
3476                 case PIPE_8BPC:
3477                         bpp = 24;
3478                         break;
3479                 case PIPE_10BPC:
3480                         bpp = 30;
3481                         break;
3482                 case PIPE_6BPC:
3483                         bpp = 18;
3484                         break;
3485                 case PIPE_12BPC:
3486                         bpp = 36;
3487                         break;
3488                 default:
3489                         DRM_ERROR("unknown pipe bpc value\n");
3490                         bpp = 24;
3491                 }
3492
3493                 if (!lane) {
3494                         /*
3495                          * Account for spread spectrum to avoid
3496                          * oversubscribing the link. Max center spread
3497                          * is 2.5%; use 5% for safety's sake.
3498                          */
3499                         u32 bps = target_clock * bpp * 21 / 20;
3500                         lane = bps / (link_bw * 8) + 1;
3501                 }
3502
3503                 intel_crtc->fdi_lanes = lane;
3504
3505                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3506         }
3507
3508         /* Ironlake: try to setup display ref clock before DPLL
3509          * enabling. This is only under driver's control after
3510          * PCH B stepping, previous chipset stepping should be
3511          * ignoring this setting.
3512          */
3513         if (HAS_PCH_SPLIT(dev)) {
3514                 temp = I915_READ(PCH_DREF_CONTROL);
3515                 /* Always enable nonspread source */
3516                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3517                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3518                 I915_WRITE(PCH_DREF_CONTROL, temp);
3519                 POSTING_READ(PCH_DREF_CONTROL);
3520
3521                 temp &= ~DREF_SSC_SOURCE_MASK;
3522                 temp |= DREF_SSC_SOURCE_ENABLE;
3523                 I915_WRITE(PCH_DREF_CONTROL, temp);
3524                 POSTING_READ(PCH_DREF_CONTROL);
3525
3526                 udelay(200);
3527
3528                 if (is_edp) {
3529                         if (dev_priv->lvds_use_ssc) {
3530                                 temp |= DREF_SSC1_ENABLE;
3531                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3532                                 POSTING_READ(PCH_DREF_CONTROL);
3533
3534                                 udelay(200);
3535
3536                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3537                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3538                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3539                                 POSTING_READ(PCH_DREF_CONTROL);
3540                         } else {
3541                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3542                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3543                                 POSTING_READ(PCH_DREF_CONTROL);
3544                         }
3545                 }
3546         }
3547
3548         if (IS_PINEVIEW(dev)) {
3549                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3550                 if (has_reduced_clock)
3551                         fp2 = (1 << reduced_clock.n) << 16 |
3552                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3553         } else {
3554                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3555                 if (has_reduced_clock)
3556                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3557                                 reduced_clock.m2;
3558         }
3559
3560         if (!HAS_PCH_SPLIT(dev))
3561                 dpll = DPLL_VGA_MODE_DIS;
3562
3563         if (IS_I9XX(dev)) {
3564                 if (is_lvds)
3565                         dpll |= DPLLB_MODE_LVDS;
3566                 else
3567                         dpll |= DPLLB_MODE_DAC_SERIAL;
3568                 if (is_sdvo) {
3569                         dpll |= DPLL_DVO_HIGH_SPEED;
3570                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3571                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3572                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3573                         else if (HAS_PCH_SPLIT(dev))
3574                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3575                 }
3576                 if (is_dp)
3577                         dpll |= DPLL_DVO_HIGH_SPEED;
3578
3579                 /* compute bitmask from p1 value */
3580                 if (IS_PINEVIEW(dev))
3581                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3582                 else {
3583                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3584                         /* also FPA1 */
3585                         if (HAS_PCH_SPLIT(dev))
3586                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3587                         if (IS_G4X(dev) && has_reduced_clock)
3588                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3589                 }
3590                 switch (clock.p2) {
3591                 case 5:
3592                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3593                         break;
3594                 case 7:
3595                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3596                         break;
3597                 case 10:
3598                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3599                         break;
3600                 case 14:
3601                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3602                         break;
3603                 }
3604                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3605                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3606         } else {
3607                 if (is_lvds) {
3608                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3609                 } else {
3610                         if (clock.p1 == 2)
3611                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3612                         else
3613                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3614                         if (clock.p2 == 4)
3615                                 dpll |= PLL_P2_DIVIDE_BY_4;
3616                 }
3617         }
3618
3619         if (is_sdvo && is_tv)
3620                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3621         else if (is_tv)
3622                 /* XXX: just matching BIOS for now */
3623                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3624                 dpll |= 3;
3625         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3626                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3627         else
3628                 dpll |= PLL_REF_INPUT_DREFCLK;
3629
3630         /* setup pipeconf */
3631         pipeconf = I915_READ(pipeconf_reg);
3632
3633         /* Set up the display plane register */
3634         dspcntr = DISPPLANE_GAMMA_ENABLE;
3635
3636         /* Ironlake's plane is forced to pipe, bit 24 is to
3637            enable color space conversion */
3638         if (!HAS_PCH_SPLIT(dev)) {
3639                 if (pipe == 0)
3640                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3641                 else
3642                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3643         }
3644
3645         if (pipe == 0 && !IS_I965G(dev)) {
3646                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3647                  * core speed.
3648                  *
3649                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3650                  * pipe == 0 check?
3651                  */
3652                 if (mode->clock >
3653                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3654                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3655                 else
3656                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3657         }
3658
3659         dspcntr |= DISPLAY_PLANE_ENABLE;
3660         pipeconf |= PIPEACONF_ENABLE;
3661         dpll |= DPLL_VCO_ENABLE;
3662
3663
3664         /* Disable the panel fitter if it was on our pipe */
3665         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3666                 I915_WRITE(PFIT_CONTROL, 0);
3667
3668         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3669         drm_mode_debug_printmodeline(mode);
3670
3671         /* assign to Ironlake registers */
3672         if (HAS_PCH_SPLIT(dev)) {
3673                 fp_reg = pch_fp_reg;
3674                 dpll_reg = pch_dpll_reg;
3675         }
3676
3677         if (is_edp) {
3678                 ironlake_disable_pll_edp(crtc);
3679         } else if ((dpll & DPLL_VCO_ENABLE)) {
3680                 I915_WRITE(fp_reg, fp);
3681                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3682                 I915_READ(dpll_reg);
3683                 udelay(150);
3684         }
3685
3686         /* enable transcoder DPLL */
3687         if (HAS_PCH_CPT(dev)) {
3688                 temp = I915_READ(PCH_DPLL_SEL);
3689                 if (trans_dpll_sel == 0)
3690                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3691                 else
3692                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3693                 I915_WRITE(PCH_DPLL_SEL, temp);
3694                 I915_READ(PCH_DPLL_SEL);
3695                 udelay(150);
3696         }
3697
3698         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3699          * This is an exception to the general rule that mode_set doesn't turn
3700          * things on.
3701          */
3702         if (is_lvds) {
3703                 u32 lvds;
3704
3705                 if (HAS_PCH_SPLIT(dev))
3706                         lvds_reg = PCH_LVDS;
3707
3708                 lvds = I915_READ(lvds_reg);
3709                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3710                 if (pipe == 1) {
3711                         if (HAS_PCH_CPT(dev))
3712                                 lvds |= PORT_TRANS_B_SEL_CPT;
3713                         else
3714                                 lvds |= LVDS_PIPEB_SELECT;
3715                 } else {
3716                         if (HAS_PCH_CPT(dev))
3717                                 lvds &= ~PORT_TRANS_SEL_MASK;
3718                         else
3719                                 lvds &= ~LVDS_PIPEB_SELECT;
3720                 }
3721                 /* set the corresponsding LVDS_BORDER bit */
3722                 lvds |= dev_priv->lvds_border_bits;
3723                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3724                  * set the DPLLs for dual-channel mode or not.
3725                  */
3726                 if (clock.p2 == 7)
3727                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3728                 else
3729                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3730
3731                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3732                  * appropriately here, but we need to look more thoroughly into how
3733                  * panels behave in the two modes.
3734                  */
3735                 /* set the dithering flag */
3736                 if (IS_I965G(dev)) {
3737                         if (dev_priv->lvds_dither) {
3738                                 if (HAS_PCH_SPLIT(dev)) {
3739                                         pipeconf |= PIPE_ENABLE_DITHER;
3740                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
3741                                 } else
3742                                         lvds |= LVDS_ENABLE_DITHER;
3743                         } else {
3744                                 if (HAS_PCH_SPLIT(dev)) {
3745                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3746                                         pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3747                                 } else
3748                                         lvds &= ~LVDS_ENABLE_DITHER;
3749                         }
3750                 }
3751                 I915_WRITE(lvds_reg, lvds);
3752                 I915_READ(lvds_reg);
3753         }
3754         if (is_dp)
3755                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3756         else if (HAS_PCH_SPLIT(dev)) {
3757                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3758                 if (pipe == 0) {
3759                         I915_WRITE(TRANSA_DATA_M1, 0);
3760                         I915_WRITE(TRANSA_DATA_N1, 0);
3761                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3762                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3763                 } else {
3764                         I915_WRITE(TRANSB_DATA_M1, 0);
3765                         I915_WRITE(TRANSB_DATA_N1, 0);
3766                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3767                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3768                 }
3769         }
3770
3771         if (!is_edp) {
3772                 I915_WRITE(fp_reg, fp);
3773                 I915_WRITE(dpll_reg, dpll);
3774                 I915_READ(dpll_reg);
3775                 /* Wait for the clocks to stabilize. */
3776                 udelay(150);
3777
3778                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3779                         if (is_sdvo) {
3780                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3781                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3782                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3783                         } else
3784                                 I915_WRITE(dpll_md_reg, 0);
3785                 } else {
3786                         /* write it again -- the BIOS does, after all */
3787                         I915_WRITE(dpll_reg, dpll);
3788                 }
3789                 I915_READ(dpll_reg);
3790                 /* Wait for the clocks to stabilize. */
3791                 udelay(150);
3792         }
3793
3794         if (is_lvds && has_reduced_clock && i915_powersave) {
3795                 I915_WRITE(fp_reg + 4, fp2);
3796                 intel_crtc->lowfreq_avail = true;
3797                 if (HAS_PIPE_CXSR(dev)) {
3798                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3799                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3800                 }
3801         } else {
3802                 I915_WRITE(fp_reg + 4, fp);
3803                 intel_crtc->lowfreq_avail = false;
3804                 if (HAS_PIPE_CXSR(dev)) {
3805                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3806                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3807                 }
3808         }
3809
3810         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3811                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3812                 /* the chip adds 2 halflines automatically */
3813                 adjusted_mode->crtc_vdisplay -= 1;
3814                 adjusted_mode->crtc_vtotal -= 1;
3815                 adjusted_mode->crtc_vblank_start -= 1;
3816                 adjusted_mode->crtc_vblank_end -= 1;
3817                 adjusted_mode->crtc_vsync_end -= 1;
3818                 adjusted_mode->crtc_vsync_start -= 1;
3819         } else
3820                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
3821
3822         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3823                    ((adjusted_mode->crtc_htotal - 1) << 16));
3824         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3825                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3826         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3827                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3828         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3829                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3830         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3831                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3832         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3833                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3834         /* pipesrc and dspsize control the size that is scaled from, which should
3835          * always be the user's requested size.
3836          */
3837         if (!HAS_PCH_SPLIT(dev)) {
3838                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3839                                 (mode->hdisplay - 1));
3840                 I915_WRITE(dsppos_reg, 0);
3841         }
3842         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3843
3844         if (HAS_PCH_SPLIT(dev)) {
3845                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3846                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3847                 I915_WRITE(link_m1_reg, m_n.link_m);
3848                 I915_WRITE(link_n1_reg, m_n.link_n);
3849
3850                 if (is_edp) {
3851                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3852                 } else {
3853                         /* enable FDI RX PLL too */
3854                         temp = I915_READ(fdi_rx_reg);
3855                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3856                         I915_READ(fdi_rx_reg);
3857                         udelay(200);
3858
3859                         /* enable FDI TX PLL too */
3860                         temp = I915_READ(fdi_tx_reg);
3861                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3862                         I915_READ(fdi_tx_reg);
3863
3864                         /* enable FDI RX PCDCLK */
3865                         temp = I915_READ(fdi_rx_reg);
3866                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3867                         I915_READ(fdi_rx_reg);
3868                         udelay(200);
3869                 }
3870         }
3871
3872         I915_WRITE(pipeconf_reg, pipeconf);
3873         I915_READ(pipeconf_reg);
3874
3875         intel_wait_for_vblank(dev);
3876
3877         if (IS_IRONLAKE(dev)) {
3878                 /* enable address swizzle for tiling buffer */
3879                 temp = I915_READ(DISP_ARB_CTL);
3880                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3881         }
3882
3883         I915_WRITE(dspcntr_reg, dspcntr);
3884
3885         /* Flush the plane changes */
3886         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3887
3888         if ((IS_I965G(dev) || plane == 0))
3889                 intel_update_fbc(crtc, &crtc->mode);
3890
3891         intel_update_watermarks(dev);
3892
3893         drm_vblank_post_modeset(dev, pipe);
3894
3895         return ret;
3896 }
3897
3898 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3899 void intel_crtc_load_lut(struct drm_crtc *crtc)
3900 {
3901         struct drm_device *dev = crtc->dev;
3902         struct drm_i915_private *dev_priv = dev->dev_private;
3903         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3904         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3905         int i;
3906
3907         /* The clocks have to be on to load the palette. */
3908         if (!crtc->enabled)
3909                 return;
3910
3911         /* use legacy palette for Ironlake */
3912         if (HAS_PCH_SPLIT(dev))
3913                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3914                                                    LGC_PALETTE_B;
3915
3916         for (i = 0; i < 256; i++) {
3917                 I915_WRITE(palreg + 4 * i,
3918                            (intel_crtc->lut_r[i] << 16) |
3919                            (intel_crtc->lut_g[i] << 8) |
3920                            intel_crtc->lut_b[i]);
3921         }
3922 }
3923
3924 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3925                                  struct drm_file *file_priv,
3926                                  uint32_t handle,
3927                                  uint32_t width, uint32_t height)
3928 {
3929         struct drm_device *dev = crtc->dev;
3930         struct drm_i915_private *dev_priv = dev->dev_private;
3931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3932         struct drm_gem_object *bo;
3933         struct drm_i915_gem_object *obj_priv;
3934         int pipe = intel_crtc->pipe;
3935         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3936         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3937         uint32_t temp = I915_READ(control);
3938         size_t addr;
3939         int ret;
3940
3941         DRM_DEBUG_KMS("\n");
3942
3943         /* if we want to turn off the cursor ignore width and height */
3944         if (!handle) {
3945                 DRM_DEBUG_KMS("cursor off\n");
3946                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3947                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3948                         temp |= CURSOR_MODE_DISABLE;
3949                 } else {
3950                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3951                 }
3952                 addr = 0;
3953                 bo = NULL;
3954                 mutex_lock(&dev->struct_mutex);
3955                 goto finish;
3956         }
3957
3958         /* Currently we only support 64x64 cursors */
3959         if (width != 64 || height != 64) {
3960                 DRM_ERROR("we currently only support 64x64 cursors\n");
3961                 return -EINVAL;
3962         }
3963
3964         bo = drm_gem_object_lookup(dev, file_priv, handle);
3965         if (!bo)
3966                 return -ENOENT;
3967
3968         obj_priv = to_intel_bo(bo);
3969
3970         if (bo->size < width * height * 4) {
3971                 DRM_ERROR("buffer is to small\n");
3972                 ret = -ENOMEM;
3973                 goto fail;
3974         }
3975
3976         /* we only need to pin inside GTT if cursor is non-phy */
3977         mutex_lock(&dev->struct_mutex);
3978         if (!dev_priv->info->cursor_needs_physical) {
3979                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3980                 if (ret) {
3981                         DRM_ERROR("failed to pin cursor bo\n");
3982                         goto fail_locked;
3983                 }
3984
3985                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
3986                 if (ret) {
3987                         DRM_ERROR("failed to move cursor bo into the GTT\n");
3988                         goto fail_unpin;
3989                 }
3990
3991                 addr = obj_priv->gtt_offset;
3992         } else {
3993                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3994                 if (ret) {
3995                         DRM_ERROR("failed to attach phys object\n");
3996                         goto fail_locked;
3997                 }
3998                 addr = obj_priv->phys_obj->handle->busaddr;
3999         }
4000
4001         if (!IS_I9XX(dev))
4002                 I915_WRITE(CURSIZE, (height << 12) | width);
4003
4004         /* Hooray for CUR*CNTR differences */
4005         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4006                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4007                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4008                 temp |= (pipe << 28); /* Connect to correct pipe */
4009         } else {
4010                 temp &= ~(CURSOR_FORMAT_MASK);
4011                 temp |= CURSOR_ENABLE;
4012                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4013         }
4014
4015  finish:
4016         I915_WRITE(control, temp);
4017         I915_WRITE(base, addr);
4018
4019         if (intel_crtc->cursor_bo) {
4020                 if (dev_priv->info->cursor_needs_physical) {
4021                         if (intel_crtc->cursor_bo != bo)
4022                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4023                 } else
4024                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4025                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4026         }
4027
4028         mutex_unlock(&dev->struct_mutex);
4029
4030         intel_crtc->cursor_addr = addr;
4031         intel_crtc->cursor_bo = bo;
4032
4033         return 0;
4034 fail_unpin:
4035         i915_gem_object_unpin(bo);
4036 fail_locked:
4037         mutex_unlock(&dev->struct_mutex);
4038 fail:
4039         drm_gem_object_unreference_unlocked(bo);
4040         return ret;
4041 }
4042
4043 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4044 {
4045         struct drm_device *dev = crtc->dev;
4046         struct drm_i915_private *dev_priv = dev->dev_private;
4047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4048         struct intel_framebuffer *intel_fb;
4049         int pipe = intel_crtc->pipe;
4050         uint32_t temp = 0;
4051         uint32_t adder;
4052
4053         if (crtc->fb) {
4054                 intel_fb = to_intel_framebuffer(crtc->fb);
4055                 intel_mark_busy(dev, intel_fb->obj);
4056         }
4057
4058         if (x < 0) {
4059                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4060                 x = -x;
4061         }
4062         if (y < 0) {
4063                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4064                 y = -y;
4065         }
4066
4067         temp |= x << CURSOR_X_SHIFT;
4068         temp |= y << CURSOR_Y_SHIFT;
4069
4070         adder = intel_crtc->cursor_addr;
4071         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
4072         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
4073
4074         return 0;
4075 }
4076
4077 /** Sets the color ramps on behalf of RandR */
4078 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4079                                  u16 blue, int regno)
4080 {
4081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4082
4083         intel_crtc->lut_r[regno] = red >> 8;
4084         intel_crtc->lut_g[regno] = green >> 8;
4085         intel_crtc->lut_b[regno] = blue >> 8;
4086 }
4087
4088 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4089                              u16 *blue, int regno)
4090 {
4091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4092
4093         *red = intel_crtc->lut_r[regno] << 8;
4094         *green = intel_crtc->lut_g[regno] << 8;
4095         *blue = intel_crtc->lut_b[regno] << 8;
4096 }
4097
4098 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4099                                  u16 *blue, uint32_t size)
4100 {
4101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4102         int i;
4103
4104         if (size != 256)
4105                 return;
4106
4107         for (i = 0; i < 256; i++) {
4108                 intel_crtc->lut_r[i] = red[i] >> 8;
4109                 intel_crtc->lut_g[i] = green[i] >> 8;
4110                 intel_crtc->lut_b[i] = blue[i] >> 8;
4111         }
4112
4113         intel_crtc_load_lut(crtc);
4114 }
4115
4116 /**
4117  * Get a pipe with a simple mode set on it for doing load-based monitor
4118  * detection.
4119  *
4120  * It will be up to the load-detect code to adjust the pipe as appropriate for
4121  * its requirements.  The pipe will be connected to no other encoders.
4122  *
4123  * Currently this code will only succeed if there is a pipe with no encoders
4124  * configured for it.  In the future, it could choose to temporarily disable
4125  * some outputs to free up a pipe for its use.
4126  *
4127  * \return crtc, or NULL if no pipes are available.
4128  */
4129
4130 /* VESA 640x480x72Hz mode to set on the pipe */
4131 static struct drm_display_mode load_detect_mode = {
4132         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4133                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4134 };
4135
4136 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4137                                             struct drm_connector *connector,
4138                                             struct drm_display_mode *mode,
4139                                             int *dpms_mode)
4140 {
4141         struct intel_crtc *intel_crtc;
4142         struct drm_crtc *possible_crtc;
4143         struct drm_crtc *supported_crtc =NULL;
4144         struct drm_encoder *encoder = &intel_encoder->enc;
4145         struct drm_crtc *crtc = NULL;
4146         struct drm_device *dev = encoder->dev;
4147         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4148         struct drm_crtc_helper_funcs *crtc_funcs;
4149         int i = -1;
4150
4151         /*
4152          * Algorithm gets a little messy:
4153          *   - if the connector already has an assigned crtc, use it (but make
4154          *     sure it's on first)
4155          *   - try to find the first unused crtc that can drive this connector,
4156          *     and use that if we find one
4157          *   - if there are no unused crtcs available, try to use the first
4158          *     one we found that supports the connector
4159          */
4160
4161         /* See if we already have a CRTC for this connector */
4162         if (encoder->crtc) {
4163                 crtc = encoder->crtc;
4164                 /* Make sure the crtc and connector are running */
4165                 intel_crtc = to_intel_crtc(crtc);
4166                 *dpms_mode = intel_crtc->dpms_mode;
4167                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4168                         crtc_funcs = crtc->helper_private;
4169                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4170                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4171                 }
4172                 return crtc;
4173         }
4174
4175         /* Find an unused one (if possible) */
4176         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4177                 i++;
4178                 if (!(encoder->possible_crtcs & (1 << i)))
4179                         continue;
4180                 if (!possible_crtc->enabled) {
4181                         crtc = possible_crtc;
4182                         break;
4183                 }
4184                 if (!supported_crtc)
4185                         supported_crtc = possible_crtc;
4186         }
4187
4188         /*
4189          * If we didn't find an unused CRTC, don't use any.
4190          */
4191         if (!crtc) {
4192                 return NULL;
4193         }
4194
4195         encoder->crtc = crtc;
4196         connector->encoder = encoder;
4197         intel_encoder->load_detect_temp = true;
4198
4199         intel_crtc = to_intel_crtc(crtc);
4200         *dpms_mode = intel_crtc->dpms_mode;
4201
4202         if (!crtc->enabled) {
4203                 if (!mode)
4204                         mode = &load_detect_mode;
4205                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4206         } else {
4207                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4208                         crtc_funcs = crtc->helper_private;
4209                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4210                 }
4211
4212                 /* Add this connector to the crtc */
4213                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4214                 encoder_funcs->commit(encoder);
4215         }
4216         /* let the connector get through one full cycle before testing */
4217         intel_wait_for_vblank(dev);
4218
4219         return crtc;
4220 }
4221
4222 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4223                                     struct drm_connector *connector, int dpms_mode)
4224 {
4225         struct drm_encoder *encoder = &intel_encoder->enc;
4226         struct drm_device *dev = encoder->dev;
4227         struct drm_crtc *crtc = encoder->crtc;
4228         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4229         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4230
4231         if (intel_encoder->load_detect_temp) {
4232                 encoder->crtc = NULL;
4233                 connector->encoder = NULL;
4234                 intel_encoder->load_detect_temp = false;
4235                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4236                 drm_helper_disable_unused_functions(dev);
4237         }
4238
4239         /* Switch crtc and encoder back off if necessary */
4240         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4241                 if (encoder->crtc == crtc)
4242                         encoder_funcs->dpms(encoder, dpms_mode);
4243                 crtc_funcs->dpms(crtc, dpms_mode);
4244         }
4245 }
4246
4247 /* Returns the clock of the currently programmed mode of the given pipe. */
4248 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4249 {
4250         struct drm_i915_private *dev_priv = dev->dev_private;
4251         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4252         int pipe = intel_crtc->pipe;
4253         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4254         u32 fp;
4255         intel_clock_t clock;
4256
4257         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4258                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4259         else
4260                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4261
4262         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4263         if (IS_PINEVIEW(dev)) {
4264                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4265                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4266         } else {
4267                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4268                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4269         }
4270
4271         if (IS_I9XX(dev)) {
4272                 if (IS_PINEVIEW(dev))
4273                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4274                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4275                 else
4276                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4277                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4278
4279                 switch (dpll & DPLL_MODE_MASK) {
4280                 case DPLLB_MODE_DAC_SERIAL:
4281                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4282                                 5 : 10;
4283                         break;
4284                 case DPLLB_MODE_LVDS:
4285                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4286                                 7 : 14;
4287                         break;
4288                 default:
4289                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4290                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4291                         return 0;
4292                 }
4293
4294                 /* XXX: Handle the 100Mhz refclk */
4295                 intel_clock(dev, 96000, &clock);
4296         } else {
4297                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4298
4299                 if (is_lvds) {
4300                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4301                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4302                         clock.p2 = 14;
4303
4304                         if ((dpll & PLL_REF_INPUT_MASK) ==
4305                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4306                                 /* XXX: might not be 66MHz */
4307                                 intel_clock(dev, 66000, &clock);
4308                         } else
4309                                 intel_clock(dev, 48000, &clock);
4310                 } else {
4311                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4312                                 clock.p1 = 2;
4313                         else {
4314                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4315                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4316                         }
4317                         if (dpll & PLL_P2_DIVIDE_BY_4)
4318                                 clock.p2 = 4;
4319                         else
4320                                 clock.p2 = 2;
4321
4322                         intel_clock(dev, 48000, &clock);
4323                 }
4324         }
4325
4326         /* XXX: It would be nice to validate the clocks, but we can't reuse
4327          * i830PllIsValid() because it relies on the xf86_config connector
4328          * configuration being accurate, which it isn't necessarily.
4329          */
4330
4331         return clock.dot;
4332 }
4333
4334 /** Returns the currently programmed mode of the given pipe. */
4335 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4336                                              struct drm_crtc *crtc)
4337 {
4338         struct drm_i915_private *dev_priv = dev->dev_private;
4339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4340         int pipe = intel_crtc->pipe;
4341         struct drm_display_mode *mode;
4342         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4343         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4344         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4345         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4346
4347         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4348         if (!mode)
4349                 return NULL;
4350
4351         mode->clock = intel_crtc_clock_get(dev, crtc);
4352         mode->hdisplay = (htot & 0xffff) + 1;
4353         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4354         mode->hsync_start = (hsync & 0xffff) + 1;
4355         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4356         mode->vdisplay = (vtot & 0xffff) + 1;
4357         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4358         mode->vsync_start = (vsync & 0xffff) + 1;
4359         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4360
4361         drm_mode_set_name(mode);
4362         drm_mode_set_crtcinfo(mode, 0);
4363
4364         return mode;
4365 }
4366
4367 #define GPU_IDLE_TIMEOUT 500 /* ms */
4368
4369 /* When this timer fires, we've been idle for awhile */
4370 static void intel_gpu_idle_timer(unsigned long arg)
4371 {
4372         struct drm_device *dev = (struct drm_device *)arg;
4373         drm_i915_private_t *dev_priv = dev->dev_private;
4374
4375         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4376
4377         dev_priv->busy = false;
4378
4379         queue_work(dev_priv->wq, &dev_priv->idle_work);
4380 }
4381
4382 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4383
4384 static void intel_crtc_idle_timer(unsigned long arg)
4385 {
4386         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4387         struct drm_crtc *crtc = &intel_crtc->base;
4388         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4389
4390         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4391
4392         intel_crtc->busy = false;
4393
4394         queue_work(dev_priv->wq, &dev_priv->idle_work);
4395 }
4396
4397 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4398 {
4399         struct drm_device *dev = crtc->dev;
4400         drm_i915_private_t *dev_priv = dev->dev_private;
4401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4402         int pipe = intel_crtc->pipe;
4403         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4404         int dpll = I915_READ(dpll_reg);
4405
4406         if (HAS_PCH_SPLIT(dev))
4407                 return;
4408
4409         if (!dev_priv->lvds_downclock_avail)
4410                 return;
4411
4412         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4413                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4414
4415                 /* Unlock panel regs */
4416                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4417
4418                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4419                 I915_WRITE(dpll_reg, dpll);
4420                 dpll = I915_READ(dpll_reg);
4421                 intel_wait_for_vblank(dev);
4422                 dpll = I915_READ(dpll_reg);
4423                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4424                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4425
4426                 /* ...and lock them again */
4427                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4428         }
4429
4430         /* Schedule downclock */
4431         if (schedule)
4432                 mod_timer(&intel_crtc->idle_timer, jiffies +
4433                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4434 }
4435
4436 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4437 {
4438         struct drm_device *dev = crtc->dev;
4439         drm_i915_private_t *dev_priv = dev->dev_private;
4440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4441         int pipe = intel_crtc->pipe;
4442         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4443         int dpll = I915_READ(dpll_reg);
4444
4445         if (HAS_PCH_SPLIT(dev))
4446                 return;
4447
4448         if (!dev_priv->lvds_downclock_avail)
4449                 return;
4450
4451         /*
4452          * Since this is called by a timer, we should never get here in
4453          * the manual case.
4454          */
4455         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4456                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4457
4458                 /* Unlock panel regs */
4459                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4460
4461                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4462                 I915_WRITE(dpll_reg, dpll);
4463                 dpll = I915_READ(dpll_reg);
4464                 intel_wait_for_vblank(dev);
4465                 dpll = I915_READ(dpll_reg);
4466                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4467                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4468
4469                 /* ...and lock them again */
4470                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4471         }
4472
4473 }
4474
4475 /**
4476  * intel_idle_update - adjust clocks for idleness
4477  * @work: work struct
4478  *
4479  * Either the GPU or display (or both) went idle.  Check the busy status
4480  * here and adjust the CRTC and GPU clocks as necessary.
4481  */
4482 static void intel_idle_update(struct work_struct *work)
4483 {
4484         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4485                                                     idle_work);
4486         struct drm_device *dev = dev_priv->dev;
4487         struct drm_crtc *crtc;
4488         struct intel_crtc *intel_crtc;
4489         int enabled = 0;
4490
4491         if (!i915_powersave)
4492                 return;
4493
4494         mutex_lock(&dev->struct_mutex);
4495
4496         i915_update_gfx_val(dev_priv);
4497
4498         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4499                 /* Skip inactive CRTCs */
4500                 if (!crtc->fb)
4501                         continue;
4502
4503                 enabled++;
4504                 intel_crtc = to_intel_crtc(crtc);
4505                 if (!intel_crtc->busy)
4506                         intel_decrease_pllclock(crtc);
4507         }
4508
4509         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4510                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4511                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4512         }
4513
4514         mutex_unlock(&dev->struct_mutex);
4515 }
4516
4517 /**
4518  * intel_mark_busy - mark the GPU and possibly the display busy
4519  * @dev: drm device
4520  * @obj: object we're operating on
4521  *
4522  * Callers can use this function to indicate that the GPU is busy processing
4523  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4524  * buffer), we'll also mark the display as busy, so we know to increase its
4525  * clock frequency.
4526  */
4527 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4528 {
4529         drm_i915_private_t *dev_priv = dev->dev_private;
4530         struct drm_crtc *crtc = NULL;
4531         struct intel_framebuffer *intel_fb;
4532         struct intel_crtc *intel_crtc;
4533
4534         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4535                 return;
4536
4537         if (!dev_priv->busy) {
4538                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4539                         u32 fw_blc_self;
4540
4541                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4542                         fw_blc_self = I915_READ(FW_BLC_SELF);
4543                         fw_blc_self &= ~FW_BLC_SELF_EN;
4544                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4545                 }
4546                 dev_priv->busy = true;
4547         } else
4548                 mod_timer(&dev_priv->idle_timer, jiffies +
4549                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4550
4551         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4552                 if (!crtc->fb)
4553                         continue;
4554
4555                 intel_crtc = to_intel_crtc(crtc);
4556                 intel_fb = to_intel_framebuffer(crtc->fb);
4557                 if (intel_fb->obj == obj) {
4558                         if (!intel_crtc->busy) {
4559                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4560                                         u32 fw_blc_self;
4561
4562                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4563                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4564                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4565                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4566                                 }
4567                                 /* Non-busy -> busy, upclock */
4568                                 intel_increase_pllclock(crtc, true);
4569                                 intel_crtc->busy = true;
4570                         } else {
4571                                 /* Busy -> busy, put off timer */
4572                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4573                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4574                         }
4575                 }
4576         }
4577 }
4578
4579 static void intel_crtc_destroy(struct drm_crtc *crtc)
4580 {
4581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4582
4583         drm_crtc_cleanup(crtc);
4584         kfree(intel_crtc);
4585 }
4586
4587 struct intel_unpin_work {
4588         struct work_struct work;
4589         struct drm_device *dev;
4590         struct drm_gem_object *old_fb_obj;
4591         struct drm_gem_object *pending_flip_obj;
4592         struct drm_pending_vblank_event *event;
4593         int pending;
4594 };
4595
4596 static void intel_unpin_work_fn(struct work_struct *__work)
4597 {
4598         struct intel_unpin_work *work =
4599                 container_of(__work, struct intel_unpin_work, work);
4600
4601         mutex_lock(&work->dev->struct_mutex);
4602         i915_gem_object_unpin(work->old_fb_obj);
4603         drm_gem_object_unreference(work->pending_flip_obj);
4604         drm_gem_object_unreference(work->old_fb_obj);
4605         mutex_unlock(&work->dev->struct_mutex);
4606         kfree(work);
4607 }
4608
4609 static void do_intel_finish_page_flip(struct drm_device *dev,
4610                                       struct drm_crtc *crtc)
4611 {
4612         drm_i915_private_t *dev_priv = dev->dev_private;
4613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4614         struct intel_unpin_work *work;
4615         struct drm_i915_gem_object *obj_priv;
4616         struct drm_pending_vblank_event *e;
4617         struct timeval now;
4618         unsigned long flags;
4619
4620         /* Ignore early vblank irqs */
4621         if (intel_crtc == NULL)
4622                 return;
4623
4624         spin_lock_irqsave(&dev->event_lock, flags);
4625         work = intel_crtc->unpin_work;
4626         if (work == NULL || !work->pending) {
4627                 spin_unlock_irqrestore(&dev->event_lock, flags);
4628                 return;
4629         }
4630
4631         intel_crtc->unpin_work = NULL;
4632         drm_vblank_put(dev, intel_crtc->pipe);
4633
4634         if (work->event) {
4635                 e = work->event;
4636                 do_gettimeofday(&now);
4637                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4638                 e->event.tv_sec = now.tv_sec;
4639                 e->event.tv_usec = now.tv_usec;
4640                 list_add_tail(&e->base.link,
4641                               &e->base.file_priv->event_list);
4642                 wake_up_interruptible(&e->base.file_priv->event_wait);
4643         }
4644
4645         spin_unlock_irqrestore(&dev->event_lock, flags);
4646
4647         obj_priv = to_intel_bo(work->pending_flip_obj);
4648
4649         /* Initial scanout buffer will have a 0 pending flip count */
4650         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4651             atomic_dec_and_test(&obj_priv->pending_flip))
4652                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4653         schedule_work(&work->work);
4654
4655         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4656 }
4657
4658 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4659 {
4660         drm_i915_private_t *dev_priv = dev->dev_private;
4661         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4662
4663         do_intel_finish_page_flip(dev, crtc);
4664 }
4665
4666 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4667 {
4668         drm_i915_private_t *dev_priv = dev->dev_private;
4669         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4670
4671         do_intel_finish_page_flip(dev, crtc);
4672 }
4673
4674 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4675 {
4676         drm_i915_private_t *dev_priv = dev->dev_private;
4677         struct intel_crtc *intel_crtc =
4678                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4679         unsigned long flags;
4680
4681         spin_lock_irqsave(&dev->event_lock, flags);
4682         if (intel_crtc->unpin_work) {
4683                 intel_crtc->unpin_work->pending = 1;
4684         } else {
4685                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4686         }
4687         spin_unlock_irqrestore(&dev->event_lock, flags);
4688 }
4689
4690 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4691                                 struct drm_framebuffer *fb,
4692                                 struct drm_pending_vblank_event *event)
4693 {
4694         struct drm_device *dev = crtc->dev;
4695         struct drm_i915_private *dev_priv = dev->dev_private;
4696         struct intel_framebuffer *intel_fb;
4697         struct drm_i915_gem_object *obj_priv;
4698         struct drm_gem_object *obj;
4699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4700         struct intel_unpin_work *work;
4701         unsigned long flags;
4702         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4703         int ret, pipesrc;
4704         u32 flip_mask;
4705
4706         work = kzalloc(sizeof *work, GFP_KERNEL);
4707         if (work == NULL)
4708                 return -ENOMEM;
4709
4710         work->event = event;
4711         work->dev = crtc->dev;
4712         intel_fb = to_intel_framebuffer(crtc->fb);
4713         work->old_fb_obj = intel_fb->obj;
4714         INIT_WORK(&work->work, intel_unpin_work_fn);
4715
4716         /* We borrow the event spin lock for protecting unpin_work */
4717         spin_lock_irqsave(&dev->event_lock, flags);
4718         if (intel_crtc->unpin_work) {
4719                 spin_unlock_irqrestore(&dev->event_lock, flags);
4720                 kfree(work);
4721
4722                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4723                 return -EBUSY;
4724         }
4725         intel_crtc->unpin_work = work;
4726         spin_unlock_irqrestore(&dev->event_lock, flags);
4727
4728         intel_fb = to_intel_framebuffer(fb);
4729         obj = intel_fb->obj;
4730
4731         mutex_lock(&dev->struct_mutex);
4732         ret = intel_pin_and_fence_fb_obj(dev, obj);
4733         if (ret != 0) {
4734                 mutex_unlock(&dev->struct_mutex);
4735
4736                 spin_lock_irqsave(&dev->event_lock, flags);
4737                 intel_crtc->unpin_work = NULL;
4738                 spin_unlock_irqrestore(&dev->event_lock, flags);
4739
4740                 kfree(work);
4741
4742                 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4743                                  to_intel_bo(obj));
4744                 return ret;
4745         }
4746
4747         /* Reference the objects for the scheduled work. */
4748         drm_gem_object_reference(work->old_fb_obj);
4749         drm_gem_object_reference(obj);
4750
4751         crtc->fb = fb;
4752         i915_gem_object_flush_write_domain(obj);
4753         drm_vblank_get(dev, intel_crtc->pipe);
4754         obj_priv = to_intel_bo(obj);
4755         atomic_inc(&obj_priv->pending_flip);
4756         work->pending_flip_obj = obj;
4757
4758         if (intel_crtc->plane)
4759                 flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4760         else
4761                 flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
4762
4763         /* Wait for any previous flip to finish */
4764         if (IS_GEN3(dev))
4765                 while (I915_READ(ISR) & flip_mask)
4766                         ;
4767
4768         BEGIN_LP_RING(4);
4769         if (IS_I965G(dev)) {
4770                 OUT_RING(MI_DISPLAY_FLIP |
4771                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4772                 OUT_RING(fb->pitch);
4773                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4774                 pipesrc = I915_READ(pipesrc_reg);
4775                 OUT_RING(pipesrc & 0x0fff0fff);
4776         } else {
4777                 OUT_RING(MI_DISPLAY_FLIP_I915 |
4778                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4779                 OUT_RING(fb->pitch);
4780                 OUT_RING(obj_priv->gtt_offset);
4781                 OUT_RING(MI_NOOP);
4782         }
4783         ADVANCE_LP_RING();
4784
4785         mutex_unlock(&dev->struct_mutex);
4786
4787         trace_i915_flip_request(intel_crtc->plane, obj);
4788
4789         return 0;
4790 }
4791
4792 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4793         .dpms = intel_crtc_dpms,
4794         .mode_fixup = intel_crtc_mode_fixup,
4795         .mode_set = intel_crtc_mode_set,
4796         .mode_set_base = intel_pipe_set_base,
4797         .prepare = intel_crtc_prepare,
4798         .commit = intel_crtc_commit,
4799         .load_lut = intel_crtc_load_lut,
4800 };
4801
4802 static const struct drm_crtc_funcs intel_crtc_funcs = {
4803         .cursor_set = intel_crtc_cursor_set,
4804         .cursor_move = intel_crtc_cursor_move,
4805         .gamma_set = intel_crtc_gamma_set,
4806         .set_config = drm_crtc_helper_set_config,
4807         .destroy = intel_crtc_destroy,
4808         .page_flip = intel_crtc_page_flip,
4809 };
4810
4811
4812 static void intel_crtc_init(struct drm_device *dev, int pipe)
4813 {
4814         drm_i915_private_t *dev_priv = dev->dev_private;
4815         struct intel_crtc *intel_crtc;
4816         int i;
4817
4818         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4819         if (intel_crtc == NULL)
4820                 return;
4821
4822         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4823
4824         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4825         intel_crtc->pipe = pipe;
4826         intel_crtc->plane = pipe;
4827         for (i = 0; i < 256; i++) {
4828                 intel_crtc->lut_r[i] = i;
4829                 intel_crtc->lut_g[i] = i;
4830                 intel_crtc->lut_b[i] = i;
4831         }
4832
4833         /* Swap pipes & planes for FBC on pre-965 */
4834         intel_crtc->pipe = pipe;
4835         intel_crtc->plane = pipe;
4836         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4837                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4838                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4839         }
4840
4841         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4842                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4843         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4844         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4845
4846         intel_crtc->cursor_addr = 0;
4847         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4848         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4849
4850         intel_crtc->busy = false;
4851
4852         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4853                     (unsigned long)intel_crtc);
4854 }
4855
4856 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4857                                 struct drm_file *file_priv)
4858 {
4859         drm_i915_private_t *dev_priv = dev->dev_private;
4860         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4861         struct drm_mode_object *drmmode_obj;
4862         struct intel_crtc *crtc;
4863
4864         if (!dev_priv) {
4865                 DRM_ERROR("called with no initialization\n");
4866                 return -EINVAL;
4867         }
4868
4869         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4870                         DRM_MODE_OBJECT_CRTC);
4871
4872         if (!drmmode_obj) {
4873                 DRM_ERROR("no such CRTC id\n");
4874                 return -EINVAL;
4875         }
4876
4877         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4878         pipe_from_crtc_id->pipe = crtc->pipe;
4879
4880         return 0;
4881 }
4882
4883 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4884 {
4885         struct drm_crtc *crtc = NULL;
4886
4887         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4888                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4889                 if (intel_crtc->pipe == pipe)
4890                         break;
4891         }
4892         return crtc;
4893 }
4894
4895 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4896 {
4897         int index_mask = 0;
4898         struct drm_encoder *encoder;
4899         int entry = 0;
4900
4901         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4902                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4903                 if (type_mask & intel_encoder->clone_mask)
4904                         index_mask |= (1 << entry);
4905                 entry++;
4906         }
4907         return index_mask;
4908 }
4909
4910
4911 static void intel_setup_outputs(struct drm_device *dev)
4912 {
4913         struct drm_i915_private *dev_priv = dev->dev_private;
4914         struct drm_encoder *encoder;
4915
4916         intel_crt_init(dev);
4917
4918         /* Set up integrated LVDS */
4919         if (IS_MOBILE(dev) && !IS_I830(dev))
4920                 intel_lvds_init(dev);
4921
4922         if (HAS_PCH_SPLIT(dev)) {
4923                 int found;
4924
4925                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4926                         intel_dp_init(dev, DP_A);
4927
4928                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4929                         /* PCH SDVOB multiplex with HDMIB */
4930                         found = intel_sdvo_init(dev, PCH_SDVOB);
4931                         if (!found)
4932                                 intel_hdmi_init(dev, HDMIB);
4933                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4934                                 intel_dp_init(dev, PCH_DP_B);
4935                 }
4936
4937                 if (I915_READ(HDMIC) & PORT_DETECTED)
4938                         intel_hdmi_init(dev, HDMIC);
4939
4940                 if (I915_READ(HDMID) & PORT_DETECTED)
4941                         intel_hdmi_init(dev, HDMID);
4942
4943                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4944                         intel_dp_init(dev, PCH_DP_C);
4945
4946                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4947                         intel_dp_init(dev, PCH_DP_D);
4948
4949         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4950                 bool found = false;
4951
4952                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4953                         DRM_DEBUG_KMS("probing SDVOB\n");
4954                         found = intel_sdvo_init(dev, SDVOB);
4955                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4956                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4957                                 intel_hdmi_init(dev, SDVOB);
4958                         }
4959
4960                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4961                                 DRM_DEBUG_KMS("probing DP_B\n");
4962                                 intel_dp_init(dev, DP_B);
4963                         }
4964                 }
4965
4966                 /* Before G4X SDVOC doesn't have its own detect register */
4967
4968                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4969                         DRM_DEBUG_KMS("probing SDVOC\n");
4970                         found = intel_sdvo_init(dev, SDVOC);
4971                 }
4972
4973                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4974
4975                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4976                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4977                                 intel_hdmi_init(dev, SDVOC);
4978                         }
4979                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4980                                 DRM_DEBUG_KMS("probing DP_C\n");
4981                                 intel_dp_init(dev, DP_C);
4982                         }
4983                 }
4984
4985                 if (SUPPORTS_INTEGRATED_DP(dev) &&
4986                     (I915_READ(DP_D) & DP_DETECTED)) {
4987                         DRM_DEBUG_KMS("probing DP_D\n");
4988                         intel_dp_init(dev, DP_D);
4989                 }
4990         } else if (IS_GEN2(dev))
4991                 intel_dvo_init(dev);
4992
4993         if (SUPPORTS_TV(dev))
4994                 intel_tv_init(dev);
4995
4996         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4997                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4998
4999                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5000                 encoder->possible_clones = intel_encoder_clones(dev,
5001                                                 intel_encoder->clone_mask);
5002         }
5003 }
5004
5005 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5006 {
5007         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5008
5009         drm_framebuffer_cleanup(fb);
5010         drm_gem_object_unreference_unlocked(intel_fb->obj);
5011
5012         kfree(intel_fb);
5013 }
5014
5015 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5016                                                 struct drm_file *file_priv,
5017                                                 unsigned int *handle)
5018 {
5019         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5020         struct drm_gem_object *object = intel_fb->obj;
5021
5022         return drm_gem_handle_create(file_priv, object, handle);
5023 }
5024
5025 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5026         .destroy = intel_user_framebuffer_destroy,
5027         .create_handle = intel_user_framebuffer_create_handle,
5028 };
5029
5030 int intel_framebuffer_init(struct drm_device *dev,
5031                            struct intel_framebuffer *intel_fb,
5032                            struct drm_mode_fb_cmd *mode_cmd,
5033                            struct drm_gem_object *obj)
5034 {
5035         int ret;
5036
5037         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5038         if (ret) {
5039                 DRM_ERROR("framebuffer init failed %d\n", ret);
5040                 return ret;
5041         }
5042
5043         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5044         intel_fb->obj = obj;
5045         return 0;
5046 }
5047
5048 static struct drm_framebuffer *
5049 intel_user_framebuffer_create(struct drm_device *dev,
5050                               struct drm_file *filp,
5051                               struct drm_mode_fb_cmd *mode_cmd)
5052 {
5053         struct drm_gem_object *obj;
5054         struct intel_framebuffer *intel_fb;
5055         int ret;
5056
5057         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5058         if (!obj)
5059                 return NULL;
5060
5061         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5062         if (!intel_fb)
5063                 return NULL;
5064
5065         ret = intel_framebuffer_init(dev, intel_fb,
5066                                      mode_cmd, obj);
5067         if (ret) {
5068                 drm_gem_object_unreference_unlocked(obj);
5069                 kfree(intel_fb);
5070                 return NULL;
5071         }
5072
5073         return &intel_fb->base;
5074 }
5075
5076 static const struct drm_mode_config_funcs intel_mode_funcs = {
5077         .fb_create = intel_user_framebuffer_create,
5078         .output_poll_changed = intel_fb_output_poll_changed,
5079 };
5080
5081 static struct drm_gem_object *
5082 intel_alloc_power_context(struct drm_device *dev)
5083 {
5084         struct drm_gem_object *pwrctx;
5085         int ret;
5086
5087         pwrctx = i915_gem_alloc_object(dev, 4096);
5088         if (!pwrctx) {
5089                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5090                 return NULL;
5091         }
5092
5093         mutex_lock(&dev->struct_mutex);
5094         ret = i915_gem_object_pin(pwrctx, 4096);
5095         if (ret) {
5096                 DRM_ERROR("failed to pin power context: %d\n", ret);
5097                 goto err_unref;
5098         }
5099
5100         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5101         if (ret) {
5102                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5103                 goto err_unpin;
5104         }
5105         mutex_unlock(&dev->struct_mutex);
5106
5107         return pwrctx;
5108
5109 err_unpin:
5110         i915_gem_object_unpin(pwrctx);
5111 err_unref:
5112         drm_gem_object_unreference(pwrctx);
5113         mutex_unlock(&dev->struct_mutex);
5114         return NULL;
5115 }
5116
5117 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5118 {
5119         struct drm_i915_private *dev_priv = dev->dev_private;
5120         u16 rgvswctl;
5121
5122         rgvswctl = I915_READ16(MEMSWCTL);
5123         if (rgvswctl & MEMCTL_CMD_STS) {
5124                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5125                 return false; /* still busy with another command */
5126         }
5127
5128         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5129                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5130         I915_WRITE16(MEMSWCTL, rgvswctl);
5131         POSTING_READ16(MEMSWCTL);
5132
5133         rgvswctl |= MEMCTL_CMD_STS;
5134         I915_WRITE16(MEMSWCTL, rgvswctl);
5135
5136         return true;
5137 }
5138
5139 void ironlake_enable_drps(struct drm_device *dev)
5140 {
5141         struct drm_i915_private *dev_priv = dev->dev_private;
5142         u32 rgvmodectl = I915_READ(MEMMODECTL);
5143         u8 fmax, fmin, fstart, vstart;
5144         int i = 0;
5145
5146         /* 100ms RC evaluation intervals */
5147         I915_WRITE(RCUPEI, 100000);
5148         I915_WRITE(RCDNEI, 100000);
5149
5150         /* Set max/min thresholds to 90ms and 80ms respectively */
5151         I915_WRITE(RCBMAXAVG, 90000);
5152         I915_WRITE(RCBMINAVG, 80000);
5153
5154         I915_WRITE(MEMIHYST, 1);
5155
5156         /* Set up min, max, and cur for interrupt handling */
5157         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5158         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5159         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5160                 MEMMODE_FSTART_SHIFT;
5161         fstart = fmax;
5162
5163         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5164                 PXVFREQ_PX_SHIFT;
5165
5166         dev_priv->fmax = fstart; /* IPS callback will increase this */
5167         dev_priv->fstart = fstart;
5168
5169         dev_priv->max_delay = fmax;
5170         dev_priv->min_delay = fmin;
5171         dev_priv->cur_delay = fstart;
5172
5173         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5174                          fstart);
5175
5176         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5177
5178         /*
5179          * Interrupts will be enabled in ironlake_irq_postinstall
5180          */
5181
5182         I915_WRITE(VIDSTART, vstart);
5183         POSTING_READ(VIDSTART);
5184
5185         rgvmodectl |= MEMMODE_SWMODE_EN;
5186         I915_WRITE(MEMMODECTL, rgvmodectl);
5187
5188         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5189                 if (i++ > 100) {
5190                         DRM_ERROR("stuck trying to change perf mode\n");
5191                         break;
5192                 }
5193                 msleep(1);
5194         }
5195         msleep(1);
5196
5197         ironlake_set_drps(dev, fstart);
5198
5199         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5200                 I915_READ(0x112e0);
5201         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5202         dev_priv->last_count2 = I915_READ(0x112f4);
5203         getrawmonotonic(&dev_priv->last_time2);
5204 }
5205
5206 void ironlake_disable_drps(struct drm_device *dev)
5207 {
5208         struct drm_i915_private *dev_priv = dev->dev_private;
5209         u16 rgvswctl = I915_READ16(MEMSWCTL);
5210
5211         /* Ack interrupts, disable EFC interrupt */
5212         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5213         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5214         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5215         I915_WRITE(DEIIR, DE_PCU_EVENT);
5216         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5217
5218         /* Go back to the starting frequency */
5219         ironlake_set_drps(dev, dev_priv->fstart);
5220         msleep(1);
5221         rgvswctl |= MEMCTL_CMD_STS;
5222         I915_WRITE(MEMSWCTL, rgvswctl);
5223         msleep(1);
5224
5225 }
5226
5227 static unsigned long intel_pxfreq(u32 vidfreq)
5228 {
5229         unsigned long freq;
5230         int div = (vidfreq & 0x3f0000) >> 16;
5231         int post = (vidfreq & 0x3000) >> 12;
5232         int pre = (vidfreq & 0x7);
5233
5234         if (!pre)
5235                 return 0;
5236
5237         freq = ((div * 133333) / ((1<<post) * pre));
5238
5239         return freq;
5240 }
5241
5242 void intel_init_emon(struct drm_device *dev)
5243 {
5244         struct drm_i915_private *dev_priv = dev->dev_private;
5245         u32 lcfuse;
5246         u8 pxw[16];
5247         int i;
5248
5249         /* Disable to program */
5250         I915_WRITE(ECR, 0);
5251         POSTING_READ(ECR);
5252
5253         /* Program energy weights for various events */
5254         I915_WRITE(SDEW, 0x15040d00);
5255         I915_WRITE(CSIEW0, 0x007f0000);
5256         I915_WRITE(CSIEW1, 0x1e220004);
5257         I915_WRITE(CSIEW2, 0x04000004);
5258
5259         for (i = 0; i < 5; i++)
5260                 I915_WRITE(PEW + (i * 4), 0);
5261         for (i = 0; i < 3; i++)
5262                 I915_WRITE(DEW + (i * 4), 0);
5263
5264         /* Program P-state weights to account for frequency power adjustment */
5265         for (i = 0; i < 16; i++) {
5266                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5267                 unsigned long freq = intel_pxfreq(pxvidfreq);
5268                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5269                         PXVFREQ_PX_SHIFT;
5270                 unsigned long val;
5271
5272                 val = vid * vid;
5273                 val *= (freq / 1000);
5274                 val *= 255;
5275                 val /= (127*127*900);
5276                 if (val > 0xff)
5277                         DRM_ERROR("bad pxval: %ld\n", val);
5278                 pxw[i] = val;
5279         }
5280         /* Render standby states get 0 weight */
5281         pxw[14] = 0;
5282         pxw[15] = 0;
5283
5284         for (i = 0; i < 4; i++) {
5285                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5286                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5287                 I915_WRITE(PXW + (i * 4), val);
5288         }
5289
5290         /* Adjust magic regs to magic values (more experimental results) */
5291         I915_WRITE(OGW0, 0);
5292         I915_WRITE(OGW1, 0);
5293         I915_WRITE(EG0, 0x00007f00);
5294         I915_WRITE(EG1, 0x0000000e);
5295         I915_WRITE(EG2, 0x000e0000);
5296         I915_WRITE(EG3, 0x68000300);
5297         I915_WRITE(EG4, 0x42000000);
5298         I915_WRITE(EG5, 0x00140031);
5299         I915_WRITE(EG6, 0);
5300         I915_WRITE(EG7, 0);
5301
5302         for (i = 0; i < 8; i++)
5303                 I915_WRITE(PXWL + (i * 4), 0);
5304
5305         /* Enable PMON + select events */
5306         I915_WRITE(ECR, 0x80000019);
5307
5308         lcfuse = I915_READ(LCFUSE02);
5309
5310         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5311 }
5312
5313 void intel_init_clock_gating(struct drm_device *dev)
5314 {
5315         struct drm_i915_private *dev_priv = dev->dev_private;
5316
5317         /*
5318          * Disable clock gating reported to work incorrectly according to the
5319          * specs, but enable as much else as we can.
5320          */
5321         if (HAS_PCH_SPLIT(dev)) {
5322                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5323
5324                 if (IS_IRONLAKE(dev)) {
5325                         /* Required for FBC */
5326                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5327                         /* Required for CxSR */
5328                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5329
5330                         I915_WRITE(PCH_3DCGDIS0,
5331                                    MARIUNIT_CLOCK_GATE_DISABLE |
5332                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5333                 }
5334
5335                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5336
5337                 /*
5338                  * According to the spec the following bits should be set in
5339                  * order to enable memory self-refresh
5340                  * The bit 22/21 of 0x42004
5341                  * The bit 5 of 0x42020
5342                  * The bit 15 of 0x45000
5343                  */
5344                 if (IS_IRONLAKE(dev)) {
5345                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5346                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5347                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5348                         I915_WRITE(ILK_DSPCLK_GATE,
5349                                         (I915_READ(ILK_DSPCLK_GATE) |
5350                                                 ILK_DPARB_CLK_GATE));
5351                         I915_WRITE(DISP_ARB_CTL,
5352                                         (I915_READ(DISP_ARB_CTL) |
5353                                                 DISP_FBC_WM_DIS));
5354                 }
5355                 return;
5356         } else if (IS_G4X(dev)) {
5357                 uint32_t dspclk_gate;
5358                 I915_WRITE(RENCLK_GATE_D1, 0);
5359                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5360                        GS_UNIT_CLOCK_GATE_DISABLE |
5361                        CL_UNIT_CLOCK_GATE_DISABLE);
5362                 I915_WRITE(RAMCLK_GATE_D, 0);
5363                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5364                         OVRUNIT_CLOCK_GATE_DISABLE |
5365                         OVCUNIT_CLOCK_GATE_DISABLE;
5366                 if (IS_GM45(dev))
5367                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5368                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5369         } else if (IS_I965GM(dev)) {
5370                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5371                 I915_WRITE(RENCLK_GATE_D2, 0);
5372                 I915_WRITE(DSPCLK_GATE_D, 0);
5373                 I915_WRITE(RAMCLK_GATE_D, 0);
5374                 I915_WRITE16(DEUC, 0);
5375         } else if (IS_I965G(dev)) {
5376                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5377                        I965_RCC_CLOCK_GATE_DISABLE |
5378                        I965_RCPB_CLOCK_GATE_DISABLE |
5379                        I965_ISC_CLOCK_GATE_DISABLE |
5380                        I965_FBC_CLOCK_GATE_DISABLE);
5381                 I915_WRITE(RENCLK_GATE_D2, 0);
5382         } else if (IS_I9XX(dev)) {
5383                 u32 dstate = I915_READ(D_STATE);
5384
5385                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5386                         DSTATE_DOT_CLOCK_GATING;
5387                 I915_WRITE(D_STATE, dstate);
5388         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5389                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5390         } else if (IS_I830(dev)) {
5391                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5392         }
5393
5394         /*
5395          * GPU can automatically power down the render unit if given a page
5396          * to save state.
5397          */
5398         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5399                 struct drm_i915_gem_object *obj_priv = NULL;
5400
5401                 if (dev_priv->pwrctx) {
5402                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5403                 } else {
5404                         struct drm_gem_object *pwrctx;
5405
5406                         pwrctx = intel_alloc_power_context(dev);
5407                         if (pwrctx) {
5408                                 dev_priv->pwrctx = pwrctx;
5409                                 obj_priv = to_intel_bo(pwrctx);
5410                         }
5411                 }
5412
5413                 if (obj_priv) {
5414                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5415                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5416                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5417                 }
5418         }
5419 }
5420
5421 /* Set up chip specific display functions */
5422 static void intel_init_display(struct drm_device *dev)
5423 {
5424         struct drm_i915_private *dev_priv = dev->dev_private;
5425
5426         /* We always want a DPMS function */
5427         if (HAS_PCH_SPLIT(dev))
5428                 dev_priv->display.dpms = ironlake_crtc_dpms;
5429         else
5430                 dev_priv->display.dpms = i9xx_crtc_dpms;
5431
5432         if (I915_HAS_FBC(dev)) {
5433                 if (IS_GM45(dev)) {
5434                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5435                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5436                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5437                 } else if (IS_I965GM(dev)) {
5438                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5439                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5440                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5441                 }
5442                 /* 855GM needs testing */
5443         }
5444
5445         /* Returns the core display clock speed */
5446         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5447                 dev_priv->display.get_display_clock_speed =
5448                         i945_get_display_clock_speed;
5449         else if (IS_I915G(dev))
5450                 dev_priv->display.get_display_clock_speed =
5451                         i915_get_display_clock_speed;
5452         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5453                 dev_priv->display.get_display_clock_speed =
5454                         i9xx_misc_get_display_clock_speed;
5455         else if (IS_I915GM(dev))
5456                 dev_priv->display.get_display_clock_speed =
5457                         i915gm_get_display_clock_speed;
5458         else if (IS_I865G(dev))
5459                 dev_priv->display.get_display_clock_speed =
5460                         i865_get_display_clock_speed;
5461         else if (IS_I85X(dev))
5462                 dev_priv->display.get_display_clock_speed =
5463                         i855_get_display_clock_speed;
5464         else /* 852, 830 */
5465                 dev_priv->display.get_display_clock_speed =
5466                         i830_get_display_clock_speed;
5467
5468         /* For FIFO watermark updates */
5469         if (HAS_PCH_SPLIT(dev)) {
5470                 if (IS_IRONLAKE(dev)) {
5471                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5472                                 dev_priv->display.update_wm = ironlake_update_wm;
5473                         else {
5474                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5475                                               "Disable CxSR\n");
5476                                 dev_priv->display.update_wm = NULL;
5477                         }
5478                 } else
5479                         dev_priv->display.update_wm = NULL;
5480         } else if (IS_PINEVIEW(dev)) {
5481                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5482                                             dev_priv->is_ddr3,
5483                                             dev_priv->fsb_freq,
5484                                             dev_priv->mem_freq)) {
5485                         DRM_INFO("failed to find known CxSR latency "
5486                                  "(found ddr%s fsb freq %d, mem freq %d), "
5487                                  "disabling CxSR\n",
5488                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5489                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5490                         /* Disable CxSR and never update its watermark again */
5491                         pineview_disable_cxsr(dev);
5492                         dev_priv->display.update_wm = NULL;
5493                 } else
5494                         dev_priv->display.update_wm = pineview_update_wm;
5495         } else if (IS_G4X(dev))
5496                 dev_priv->display.update_wm = g4x_update_wm;
5497         else if (IS_I965G(dev))
5498                 dev_priv->display.update_wm = i965_update_wm;
5499         else if (IS_I9XX(dev)) {
5500                 dev_priv->display.update_wm = i9xx_update_wm;
5501                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5502         } else if (IS_I85X(dev)) {
5503                 dev_priv->display.update_wm = i9xx_update_wm;
5504                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5505         } else {
5506                 dev_priv->display.update_wm = i830_update_wm;
5507                 if (IS_845G(dev))
5508                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5509                 else
5510                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5511         }
5512 }
5513
5514 void intel_modeset_init(struct drm_device *dev)
5515 {
5516         struct drm_i915_private *dev_priv = dev->dev_private;
5517         int i;
5518
5519         drm_mode_config_init(dev);
5520
5521         dev->mode_config.min_width = 0;
5522         dev->mode_config.min_height = 0;
5523
5524         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5525
5526         intel_init_display(dev);
5527
5528         if (IS_I965G(dev)) {
5529                 dev->mode_config.max_width = 8192;
5530                 dev->mode_config.max_height = 8192;
5531         } else if (IS_I9XX(dev)) {
5532                 dev->mode_config.max_width = 4096;
5533                 dev->mode_config.max_height = 4096;
5534         } else {
5535                 dev->mode_config.max_width = 2048;
5536                 dev->mode_config.max_height = 2048;
5537         }
5538
5539         /* set memory base */
5540         if (IS_I9XX(dev))
5541                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5542         else
5543                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5544
5545         if (IS_MOBILE(dev) || IS_I9XX(dev))
5546                 dev_priv->num_pipe = 2;
5547         else
5548                 dev_priv->num_pipe = 1;
5549         DRM_DEBUG_KMS("%d display pipe%s available.\n",
5550                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
5551
5552         for (i = 0; i < dev_priv->num_pipe; i++) {
5553                 intel_crtc_init(dev, i);
5554         }
5555
5556         intel_setup_outputs(dev);
5557
5558         intel_init_clock_gating(dev);
5559
5560         if (IS_IRONLAKE_M(dev)) {
5561                 ironlake_enable_drps(dev);
5562                 intel_init_emon(dev);
5563         }
5564
5565         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5566         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5567                     (unsigned long)dev);
5568
5569         intel_setup_overlay(dev);
5570 }
5571
5572 void intel_modeset_cleanup(struct drm_device *dev)
5573 {
5574         struct drm_i915_private *dev_priv = dev->dev_private;
5575         struct drm_crtc *crtc;
5576         struct intel_crtc *intel_crtc;
5577
5578         mutex_lock(&dev->struct_mutex);
5579
5580         drm_kms_helper_poll_fini(dev);
5581         intel_fbdev_fini(dev);
5582
5583         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5584                 /* Skip inactive CRTCs */
5585                 if (!crtc->fb)
5586                         continue;
5587
5588                 intel_crtc = to_intel_crtc(crtc);
5589                 intel_increase_pllclock(crtc, false);
5590                 del_timer_sync(&intel_crtc->idle_timer);
5591         }
5592
5593         del_timer_sync(&dev_priv->idle_timer);
5594
5595         if (dev_priv->display.disable_fbc)
5596                 dev_priv->display.disable_fbc(dev);
5597
5598         if (dev_priv->pwrctx) {
5599                 struct drm_i915_gem_object *obj_priv;
5600
5601                 obj_priv = to_intel_bo(dev_priv->pwrctx);
5602                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5603                 I915_READ(PWRCTXA);
5604                 i915_gem_object_unpin(dev_priv->pwrctx);
5605                 drm_gem_object_unreference(dev_priv->pwrctx);
5606         }
5607
5608         if (IS_IRONLAKE_M(dev))
5609                 ironlake_disable_drps(dev);
5610
5611         mutex_unlock(&dev->struct_mutex);
5612
5613         drm_mode_config_cleanup(dev);
5614 }
5615
5616
5617 /*
5618  * Return which encoder is currently attached for connector.
5619  */
5620 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5621 {
5622         struct drm_mode_object *obj;
5623         struct drm_encoder *encoder;
5624         int i;
5625
5626         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5627                 if (connector->encoder_ids[i] == 0)
5628                         break;
5629
5630                 obj = drm_mode_object_find(connector->dev,
5631                                            connector->encoder_ids[i],
5632                                            DRM_MODE_OBJECT_ENCODER);
5633                 if (!obj)
5634                         continue;
5635
5636                 encoder = obj_to_encoder(obj);
5637                 return encoder;
5638         }
5639         return NULL;
5640 }
5641
5642 /*
5643  * set vga decode state - true == enable VGA decode
5644  */
5645 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5646 {
5647         struct drm_i915_private *dev_priv = dev->dev_private;
5648         u16 gmch_ctrl;
5649
5650         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5651         if (state)
5652                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5653         else
5654                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5655         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5656         return 0;
5657 }