drm/i915: use new fb debug hooks
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "drm_dp_helper.h"
37
38 #include "drm_crtc_helper.h"
39
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41
42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
43 static void intel_update_watermarks(struct drm_device *dev);
44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
45
46 typedef struct {
47     /* given values */
48     int n;
49     int m1, m2;
50     int p1, p2;
51     /* derived values */
52     int dot;
53     int vco;
54     int m;
55     int p;
56 } intel_clock_t;
57
58 typedef struct {
59     int min, max;
60 } intel_range_t;
61
62 typedef struct {
63     int dot_limit;
64     int p2_slow, p2_fast;
65 } intel_p2_t;
66
67 #define INTEL_P2_NUM                  2
68 typedef struct intel_limit intel_limit_t;
69 struct intel_limit {
70     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
71     intel_p2_t      p2;
72     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
73                       int, int, intel_clock_t *);
74 };
75
76 #define I8XX_DOT_MIN              25000
77 #define I8XX_DOT_MAX             350000
78 #define I8XX_VCO_MIN             930000
79 #define I8XX_VCO_MAX            1400000
80 #define I8XX_N_MIN                    3
81 #define I8XX_N_MAX                   16
82 #define I8XX_M_MIN                   96
83 #define I8XX_M_MAX                  140
84 #define I8XX_M1_MIN                  18
85 #define I8XX_M1_MAX                  26
86 #define I8XX_M2_MIN                   6
87 #define I8XX_M2_MAX                  16
88 #define I8XX_P_MIN                    4
89 #define I8XX_P_MAX                  128
90 #define I8XX_P1_MIN                   2
91 #define I8XX_P1_MAX                  33
92 #define I8XX_P1_LVDS_MIN              1
93 #define I8XX_P1_LVDS_MAX              6
94 #define I8XX_P2_SLOW                  4
95 #define I8XX_P2_FAST                  2
96 #define I8XX_P2_LVDS_SLOW             14
97 #define I8XX_P2_LVDS_FAST             7
98 #define I8XX_P2_SLOW_LIMIT       165000
99
100 #define I9XX_DOT_MIN              20000
101 #define I9XX_DOT_MAX             400000
102 #define I9XX_VCO_MIN            1400000
103 #define I9XX_VCO_MAX            2800000
104 #define PINEVIEW_VCO_MIN                1700000
105 #define PINEVIEW_VCO_MAX                3500000
106 #define I9XX_N_MIN                    1
107 #define I9XX_N_MAX                    6
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN                3
110 #define PINEVIEW_N_MAX                6
111 #define I9XX_M_MIN                   70
112 #define I9XX_M_MAX                  120
113 #define PINEVIEW_M_MIN                2
114 #define PINEVIEW_M_MAX              256
115 #define I9XX_M1_MIN                  10
116 #define I9XX_M1_MAX                  22
117 #define I9XX_M2_MIN                   5
118 #define I9XX_M2_MAX                   9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN               0
121 #define PINEVIEW_M1_MAX               0
122 #define PINEVIEW_M2_MIN               0
123 #define PINEVIEW_M2_MAX               254
124 #define I9XX_P_SDVO_DAC_MIN           5
125 #define I9XX_P_SDVO_DAC_MAX          80
126 #define I9XX_P_LVDS_MIN               7
127 #define I9XX_P_LVDS_MAX              98
128 #define PINEVIEW_P_LVDS_MIN                   7
129 #define PINEVIEW_P_LVDS_MAX                  112
130 #define I9XX_P1_MIN                   1
131 #define I9XX_P1_MAX                   8
132 #define I9XX_P2_SDVO_DAC_SLOW                10
133 #define I9XX_P2_SDVO_DAC_FAST                 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
135 #define I9XX_P2_LVDS_SLOW                    14
136 #define I9XX_P2_LVDS_FAST                     7
137 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
138
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN           25000
141 #define G4X_DOT_SDVO_MAX           270000
142 #define G4X_VCO_MIN                1750000
143 #define G4X_VCO_MAX                3500000
144 #define G4X_N_SDVO_MIN             1
145 #define G4X_N_SDVO_MAX             4
146 #define G4X_M_SDVO_MIN             104
147 #define G4X_M_SDVO_MAX             138
148 #define G4X_M1_SDVO_MIN            17
149 #define G4X_M1_SDVO_MAX            23
150 #define G4X_M2_SDVO_MIN            5
151 #define G4X_M2_SDVO_MAX            11
152 #define G4X_P_SDVO_MIN             10
153 #define G4X_P_SDVO_MAX             30
154 #define G4X_P1_SDVO_MIN            1
155 #define G4X_P1_SDVO_MAX            3
156 #define G4X_P2_SDVO_SLOW           10
157 #define G4X_P2_SDVO_FAST           10
158 #define G4X_P2_SDVO_LIMIT          270000
159
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN           22000
162 #define G4X_DOT_HDMI_DAC_MAX           400000
163 #define G4X_N_HDMI_DAC_MIN             1
164 #define G4X_N_HDMI_DAC_MAX             4
165 #define G4X_M_HDMI_DAC_MIN             104
166 #define G4X_M_HDMI_DAC_MAX             138
167 #define G4X_M1_HDMI_DAC_MIN            16
168 #define G4X_M1_HDMI_DAC_MAX            23
169 #define G4X_M2_HDMI_DAC_MIN            5
170 #define G4X_M2_HDMI_DAC_MAX            11
171 #define G4X_P_HDMI_DAC_MIN             5
172 #define G4X_P_HDMI_DAC_MAX             80
173 #define G4X_P1_HDMI_DAC_MIN            1
174 #define G4X_P1_HDMI_DAC_MAX            8
175 #define G4X_P2_HDMI_DAC_SLOW           10
176 #define G4X_P2_HDMI_DAC_FAST           5
177 #define G4X_P2_HDMI_DAC_LIMIT          165000
178
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
197
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
216
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN           161670
219 #define G4X_DOT_DISPLAY_PORT_MAX           227000
220 #define G4X_N_DISPLAY_PORT_MIN             1
221 #define G4X_N_DISPLAY_PORT_MAX             2
222 #define G4X_M_DISPLAY_PORT_MIN             97
223 #define G4X_M_DISPLAY_PORT_MAX             108
224 #define G4X_M1_DISPLAY_PORT_MIN            0x10
225 #define G4X_M1_DISPLAY_PORT_MAX            0x12
226 #define G4X_M2_DISPLAY_PORT_MIN            0x05
227 #define G4X_M2_DISPLAY_PORT_MAX            0x06
228 #define G4X_P_DISPLAY_PORT_MIN             10
229 #define G4X_P_DISPLAY_PORT_MAX             20
230 #define G4X_P1_DISPLAY_PORT_MIN            1
231 #define G4X_P1_DISPLAY_PORT_MAX            2
232 #define G4X_P2_DISPLAY_PORT_SLOW           10
233 #define G4X_P2_DISPLAY_PORT_FAST           10
234 #define G4X_P2_DISPLAY_PORT_LIMIT          0
235
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238    N/M1/M2, so here the range value for them is (actual_value-2).
239  */
240 #define IRONLAKE_DOT_MIN         25000
241 #define IRONLAKE_DOT_MAX         350000
242 #define IRONLAKE_VCO_MIN         1760000
243 #define IRONLAKE_VCO_MAX         3510000
244 #define IRONLAKE_M1_MIN          12
245 #define IRONLAKE_M1_MAX          22
246 #define IRONLAKE_M2_MIN          5
247 #define IRONLAKE_M2_MAX          9
248 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
249
250 /* We have parameter ranges for different type of outputs. */
251
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN      1
254 #define IRONLAKE_DAC_N_MAX      5
255 #define IRONLAKE_DAC_M_MIN      79
256 #define IRONLAKE_DAC_M_MAX      127
257 #define IRONLAKE_DAC_P_MIN      5
258 #define IRONLAKE_DAC_P_MAX      80
259 #define IRONLAKE_DAC_P1_MIN     1
260 #define IRONLAKE_DAC_P1_MAX     8
261 #define IRONLAKE_DAC_P2_SLOW    10
262 #define IRONLAKE_DAC_P2_FAST    5
263
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN   1
266 #define IRONLAKE_LVDS_S_N_MAX   3
267 #define IRONLAKE_LVDS_S_M_MIN   79
268 #define IRONLAKE_LVDS_S_M_MAX   118
269 #define IRONLAKE_LVDS_S_P_MIN   28
270 #define IRONLAKE_LVDS_S_P_MAX   112
271 #define IRONLAKE_LVDS_S_P1_MIN  2
272 #define IRONLAKE_LVDS_S_P1_MAX  8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
275
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN   1
278 #define IRONLAKE_LVDS_D_N_MAX   3
279 #define IRONLAKE_LVDS_D_M_MIN   79
280 #define IRONLAKE_LVDS_D_M_MAX   127
281 #define IRONLAKE_LVDS_D_P_MIN   14
282 #define IRONLAKE_LVDS_D_P_MAX   56
283 #define IRONLAKE_LVDS_D_P1_MIN  2
284 #define IRONLAKE_LVDS_D_P1_MAX  8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
287
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
299
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
311
312 /* DisplayPort */
313 #define IRONLAKE_DP_N_MIN               1
314 #define IRONLAKE_DP_N_MAX               2
315 #define IRONLAKE_DP_M_MIN               81
316 #define IRONLAKE_DP_M_MAX               90
317 #define IRONLAKE_DP_P_MIN               10
318 #define IRONLAKE_DP_P_MAX               20
319 #define IRONLAKE_DP_P2_FAST             10
320 #define IRONLAKE_DP_P2_SLOW             10
321 #define IRONLAKE_DP_P2_LIMIT            0
322 #define IRONLAKE_DP_P1_MIN              1
323 #define IRONLAKE_DP_P1_MAX              2
324
325 static bool
326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
327                     int target, int refclk, intel_clock_t *best_clock);
328 static bool
329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
330                         int target, int refclk, intel_clock_t *best_clock);
331
332 static bool
333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
334                       int target, int refclk, intel_clock_t *best_clock);
335 static bool
336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
337                            int target, int refclk, intel_clock_t *best_clock);
338
339 static const intel_limit_t intel_limits_i8xx_dvo = {
340         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
341         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
342         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
343         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
344         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
345         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
346         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
347         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
348         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
349                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
350         .find_pll = intel_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_i8xx_lvds = {
354         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
355         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
356         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
357         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
358         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
359         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
360         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
361         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
362         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
363                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
364         .find_pll = intel_find_best_PLL,
365 };
366         
367 static const intel_limit_t intel_limits_i9xx_sdvo = {
368         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
369         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
370         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
371         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
372         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
373         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
374         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
375         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
376         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
377                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
378         .find_pll = intel_find_best_PLL,
379 };
380
381 static const intel_limit_t intel_limits_i9xx_lvds = {
382         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
383         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
384         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
385         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
386         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
387         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
388         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
389         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
390         /* The single-channel range is 25-112Mhz, and dual-channel
391          * is 80-224Mhz.  Prefer single channel as much as possible.
392          */
393         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
394                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
395         .find_pll = intel_find_best_PLL,
396 };
397
398     /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo = {
400         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
401         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
402         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
403         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
404         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
405         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
406         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
407         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
408         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
409                  .p2_slow = G4X_P2_SDVO_SLOW,
410                  .p2_fast = G4X_P2_SDVO_FAST
411         },
412         .find_pll = intel_g4x_find_best_PLL,
413 };
414
415 static const intel_limit_t intel_limits_g4x_hdmi = {
416         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
418         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
419         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
420         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
421         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
422         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
423         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
424         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
425                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
426                  .p2_fast = G4X_P2_HDMI_DAC_FAST
427         },
428         .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
432         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
433                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
434         .vco = { .min = G4X_VCO_MIN,
435                  .max = G4X_VCO_MAX },
436         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
437                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
438         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
439                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
440         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
441                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
442         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
443                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
444         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
445                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
446         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
447                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
448         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
449                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
450                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
451         },
452         .find_pll = intel_g4x_find_best_PLL,
453 };
454
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
456         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
457                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
458         .vco = { .min = G4X_VCO_MIN,
459                  .max = G4X_VCO_MAX },
460         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
461                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
462         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
463                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
464         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
465                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
466         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
467                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
468         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
469                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
470         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
471                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
472         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
473                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
474                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
475         },
476         .find_pll = intel_g4x_find_best_PLL,
477 };
478
479 static const intel_limit_t intel_limits_g4x_display_port = {
480         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
481                  .max = G4X_DOT_DISPLAY_PORT_MAX },
482         .vco = { .min = G4X_VCO_MIN,
483                  .max = G4X_VCO_MAX},
484         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
485                  .max = G4X_N_DISPLAY_PORT_MAX },
486         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
487                  .max = G4X_M_DISPLAY_PORT_MAX },
488         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
489                  .max = G4X_M1_DISPLAY_PORT_MAX },
490         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
491                  .max = G4X_M2_DISPLAY_PORT_MAX },
492         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
493                  .max = G4X_P_DISPLAY_PORT_MAX },
494         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
495                  .max = G4X_P1_DISPLAY_PORT_MAX},
496         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
497                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
498                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
499         .find_pll = intel_find_pll_g4x_dp,
500 };
501
502 static const intel_limit_t intel_limits_pineview_sdvo = {
503         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
504         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
505         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
506         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
507         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
508         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
509         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
510         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
511         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
512                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
513         .find_pll = intel_find_best_PLL,
514 };
515
516 static const intel_limit_t intel_limits_pineview_lvds = {
517         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
518         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
519         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
520         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
521         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
522         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
523         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
524         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
525         /* Pineview only supports single-channel mode. */
526         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
527                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
528         .find_pll = intel_find_best_PLL,
529 };
530
531 static const intel_limit_t intel_limits_ironlake_dac = {
532         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
533         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
534         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
535         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
536         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
537         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
538         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
539         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
540         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
541                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
542                  .p2_fast = IRONLAKE_DAC_P2_FAST },
543         .find_pll = intel_g4x_find_best_PLL,
544 };
545
546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
547         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
548         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
549         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
550         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
551         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
552         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
553         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
554         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
555         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
556                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
557                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
558         .find_pll = intel_g4x_find_best_PLL,
559 };
560
561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
562         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
563         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
564         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
565         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
566         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
567         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
568         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
569         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
570         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
571                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
572                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
573         .find_pll = intel_g4x_find_best_PLL,
574 };
575
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
577         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
578         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
579         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
580         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
581         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
582         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
583         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
584         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
585         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
586                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
587                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
588         .find_pll = intel_g4x_find_best_PLL,
589 };
590
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
592         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
593         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
594         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
595         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
596         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
597         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
598         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
599         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
600         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
601                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
602                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
603         .find_pll = intel_g4x_find_best_PLL,
604 };
605
606 static const intel_limit_t intel_limits_ironlake_display_port = {
607         .dot = { .min = IRONLAKE_DOT_MIN,
608                  .max = IRONLAKE_DOT_MAX },
609         .vco = { .min = IRONLAKE_VCO_MIN,
610                  .max = IRONLAKE_VCO_MAX},
611         .n   = { .min = IRONLAKE_DP_N_MIN,
612                  .max = IRONLAKE_DP_N_MAX },
613         .m   = { .min = IRONLAKE_DP_M_MIN,
614                  .max = IRONLAKE_DP_M_MAX },
615         .m1  = { .min = IRONLAKE_M1_MIN,
616                  .max = IRONLAKE_M1_MAX },
617         .m2  = { .min = IRONLAKE_M2_MIN,
618                  .max = IRONLAKE_M2_MAX },
619         .p   = { .min = IRONLAKE_DP_P_MIN,
620                  .max = IRONLAKE_DP_P_MAX },
621         .p1  = { .min = IRONLAKE_DP_P1_MIN,
622                  .max = IRONLAKE_DP_P1_MAX},
623         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
624                  .p2_slow = IRONLAKE_DP_P2_SLOW,
625                  .p2_fast = IRONLAKE_DP_P2_FAST },
626         .find_pll = intel_find_pll_ironlake_dp,
627 };
628
629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
630 {
631         struct drm_device *dev = crtc->dev;
632         struct drm_i915_private *dev_priv = dev->dev_private;
633         const intel_limit_t *limit;
634         int refclk = 120;
635
636         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
638                         refclk = 100;
639
640                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
641                     LVDS_CLKB_POWER_UP) {
642                         /* LVDS dual channel */
643                         if (refclk == 100)
644                                 limit = &intel_limits_ironlake_dual_lvds_100m;
645                         else
646                                 limit = &intel_limits_ironlake_dual_lvds;
647                 } else {
648                         if (refclk == 100)
649                                 limit = &intel_limits_ironlake_single_lvds_100m;
650                         else
651                                 limit = &intel_limits_ironlake_single_lvds;
652                 }
653         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
654                         HAS_eDP)
655                 limit = &intel_limits_ironlake_display_port;
656         else
657                 limit = &intel_limits_ironlake_dac;
658
659         return limit;
660 }
661
662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
663 {
664         struct drm_device *dev = crtc->dev;
665         struct drm_i915_private *dev_priv = dev->dev_private;
666         const intel_limit_t *limit;
667
668         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
669                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
670                     LVDS_CLKB_POWER_UP)
671                         /* LVDS with dual channel */
672                         limit = &intel_limits_g4x_dual_channel_lvds;
673                 else
674                         /* LVDS with dual channel */
675                         limit = &intel_limits_g4x_single_channel_lvds;
676         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
677                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
678                 limit = &intel_limits_g4x_hdmi;
679         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
680                 limit = &intel_limits_g4x_sdvo;
681         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
682                 limit = &intel_limits_g4x_display_port;
683         } else /* The option is for other outputs */
684                 limit = &intel_limits_i9xx_sdvo;
685
686         return limit;
687 }
688
689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
690 {
691         struct drm_device *dev = crtc->dev;
692         const intel_limit_t *limit;
693
694         if (HAS_PCH_SPLIT(dev))
695                 limit = intel_ironlake_limit(crtc);
696         else if (IS_G4X(dev)) {
697                 limit = intel_g4x_limit(crtc);
698         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
699                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
700                         limit = &intel_limits_i9xx_lvds;
701                 else
702                         limit = &intel_limits_i9xx_sdvo;
703         } else if (IS_PINEVIEW(dev)) {
704                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705                         limit = &intel_limits_pineview_lvds;
706                 else
707                         limit = &intel_limits_pineview_sdvo;
708         } else {
709                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710                         limit = &intel_limits_i8xx_lvds;
711                 else
712                         limit = &intel_limits_i8xx_dvo;
713         }
714         return limit;
715 }
716
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk, intel_clock_t *clock)
719 {
720         clock->m = clock->m2 + 2;
721         clock->p = clock->p1 * clock->p2;
722         clock->vco = refclk * clock->m / clock->n;
723         clock->dot = clock->vco / clock->p;
724 }
725
726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
727 {
728         if (IS_PINEVIEW(dev)) {
729                 pineview_clock(refclk, clock);
730                 return;
731         }
732         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
733         clock->p = clock->p1 * clock->p2;
734         clock->vco = refclk * clock->m / (clock->n + 2);
735         clock->dot = clock->vco / clock->p;
736 }
737
738 /**
739  * Returns whether any output on the specified pipe is of the specified type
740  */
741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742 {
743     struct drm_device *dev = crtc->dev;
744     struct drm_mode_config *mode_config = &dev->mode_config;
745     struct drm_encoder *l_entry;
746
747     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
748             if (l_entry && l_entry->crtc == crtc) {
749                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
750                     if (intel_encoder->type == type)
751                             return true;
752             }
753     }
754     return false;
755 }
756
757 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
758 /**
759  * Returns whether the given set of divisors are valid for a given refclk with
760  * the given connectors.
761  */
762
763 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
764 {
765         const intel_limit_t *limit = intel_limit (crtc);
766         struct drm_device *dev = crtc->dev;
767
768         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
769                 INTELPllInvalid ("p1 out of range\n");
770         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
771                 INTELPllInvalid ("p out of range\n");
772         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
773                 INTELPllInvalid ("m2 out of range\n");
774         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
775                 INTELPllInvalid ("m1 out of range\n");
776         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
777                 INTELPllInvalid ("m1 <= m2\n");
778         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
779                 INTELPllInvalid ("m out of range\n");
780         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
781                 INTELPllInvalid ("n out of range\n");
782         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
783                 INTELPllInvalid ("vco out of range\n");
784         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785          * connector, etc., rather than just a single range.
786          */
787         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
788                 INTELPllInvalid ("dot out of range\n");
789
790         return true;
791 }
792
793 static bool
794 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
795                     int target, int refclk, intel_clock_t *best_clock)
796
797 {
798         struct drm_device *dev = crtc->dev;
799         struct drm_i915_private *dev_priv = dev->dev_private;
800         intel_clock_t clock;
801         int err = target;
802
803         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
804             (I915_READ(LVDS)) != 0) {
805                 /*
806                  * For LVDS, if the panel is on, just rely on its current
807                  * settings for dual-channel.  We haven't figured out how to
808                  * reliably set up different single/dual channel state, if we
809                  * even can.
810                  */
811                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
812                     LVDS_CLKB_POWER_UP)
813                         clock.p2 = limit->p2.p2_fast;
814                 else
815                         clock.p2 = limit->p2.p2_slow;
816         } else {
817                 if (target < limit->p2.dot_limit)
818                         clock.p2 = limit->p2.p2_slow;
819                 else
820                         clock.p2 = limit->p2.p2_fast;
821         }
822
823         memset (best_clock, 0, sizeof (*best_clock));
824
825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826              clock.m1++) {
827                 for (clock.m2 = limit->m2.min;
828                      clock.m2 <= limit->m2.max; clock.m2++) {
829                         /* m1 is always 0 in Pineview */
830                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
831                                 break;
832                         for (clock.n = limit->n.min;
833                              clock.n <= limit->n.max; clock.n++) {
834                                 for (clock.p1 = limit->p1.min;
835                                         clock.p1 <= limit->p1.max; clock.p1++) {
836                                         int this_err;
837
838                                         intel_clock(dev, refclk, &clock);
839
840                                         if (!intel_PLL_is_valid(crtc, &clock))
841                                                 continue;
842
843                                         this_err = abs(clock.dot - target);
844                                         if (this_err < err) {
845                                                 *best_clock = clock;
846                                                 err = this_err;
847                                         }
848                                 }
849                         }
850                 }
851         }
852
853         return (err != target);
854 }
855
856 static bool
857 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
858                         int target, int refclk, intel_clock_t *best_clock)
859 {
860         struct drm_device *dev = crtc->dev;
861         struct drm_i915_private *dev_priv = dev->dev_private;
862         intel_clock_t clock;
863         int max_n;
864         bool found;
865         /* approximately equals target * 0.00585 */
866         int err_most = (target >> 8) + (target >> 9);
867         found = false;
868
869         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
870                 int lvds_reg;
871
872                 if (HAS_PCH_SPLIT(dev))
873                         lvds_reg = PCH_LVDS;
874                 else
875                         lvds_reg = LVDS;
876                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
877                     LVDS_CLKB_POWER_UP)
878                         clock.p2 = limit->p2.p2_fast;
879                 else
880                         clock.p2 = limit->p2.p2_slow;
881         } else {
882                 if (target < limit->p2.dot_limit)
883                         clock.p2 = limit->p2.p2_slow;
884                 else
885                         clock.p2 = limit->p2.p2_fast;
886         }
887
888         memset(best_clock, 0, sizeof(*best_clock));
889         max_n = limit->n.max;
890         /* based on hardware requirement, prefer smaller n to precision */
891         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
892                 /* based on hardware requirement, prefere larger m1,m2 */
893                 for (clock.m1 = limit->m1.max;
894                      clock.m1 >= limit->m1.min; clock.m1--) {
895                         for (clock.m2 = limit->m2.max;
896                              clock.m2 >= limit->m2.min; clock.m2--) {
897                                 for (clock.p1 = limit->p1.max;
898                                      clock.p1 >= limit->p1.min; clock.p1--) {
899                                         int this_err;
900
901                                         intel_clock(dev, refclk, &clock);
902                                         if (!intel_PLL_is_valid(crtc, &clock))
903                                                 continue;
904                                         this_err = abs(clock.dot - target) ;
905                                         if (this_err < err_most) {
906                                                 *best_clock = clock;
907                                                 err_most = this_err;
908                                                 max_n = clock.n;
909                                                 found = true;
910                                         }
911                                 }
912                         }
913                 }
914         }
915         return found;
916 }
917
918 static bool
919 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
920                            int target, int refclk, intel_clock_t *best_clock)
921 {
922         struct drm_device *dev = crtc->dev;
923         intel_clock_t clock;
924
925         /* return directly when it is eDP */
926         if (HAS_eDP)
927                 return true;
928
929         if (target < 200000) {
930                 clock.n = 1;
931                 clock.p1 = 2;
932                 clock.p2 = 10;
933                 clock.m1 = 12;
934                 clock.m2 = 9;
935         } else {
936                 clock.n = 2;
937                 clock.p1 = 1;
938                 clock.p2 = 10;
939                 clock.m1 = 14;
940                 clock.m2 = 8;
941         }
942         intel_clock(dev, refclk, &clock);
943         memcpy(best_clock, &clock, sizeof(intel_clock_t));
944         return true;
945 }
946
947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
948 static bool
949 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
950                       int target, int refclk, intel_clock_t *best_clock)
951 {
952     intel_clock_t clock;
953     if (target < 200000) {
954         clock.p1 = 2;
955         clock.p2 = 10;
956         clock.n = 2;
957         clock.m1 = 23;
958         clock.m2 = 8;
959     } else {
960         clock.p1 = 1;
961         clock.p2 = 10;
962         clock.n = 1;
963         clock.m1 = 14;
964         clock.m2 = 2;
965     }
966     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
967     clock.p = (clock.p1 * clock.p2);
968     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
969     clock.vco = 0;
970     memcpy(best_clock, &clock, sizeof(intel_clock_t));
971     return true;
972 }
973
974 void
975 intel_wait_for_vblank(struct drm_device *dev)
976 {
977         /* Wait for 20ms, i.e. one cycle at 50hz. */
978         if (in_dbg_master())
979                 mdelay(20); /* The kernel debugger cannot call msleep() */
980         else
981                 msleep(20);
982 }
983
984 /* Parameters have changed, update FBC info */
985 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
986 {
987         struct drm_device *dev = crtc->dev;
988         struct drm_i915_private *dev_priv = dev->dev_private;
989         struct drm_framebuffer *fb = crtc->fb;
990         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
991         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
993         int plane, i;
994         u32 fbc_ctl, fbc_ctl2;
995
996         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
997
998         if (fb->pitch < dev_priv->cfb_pitch)
999                 dev_priv->cfb_pitch = fb->pitch;
1000
1001         /* FBC_CTL wants 64B units */
1002         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1003         dev_priv->cfb_fence = obj_priv->fence_reg;
1004         dev_priv->cfb_plane = intel_crtc->plane;
1005         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1006
1007         /* Clear old tags */
1008         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1009                 I915_WRITE(FBC_TAG + (i * 4), 0);
1010
1011         /* Set it up... */
1012         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1013         if (obj_priv->tiling_mode != I915_TILING_NONE)
1014                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1015         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1016         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1017
1018         /* enable it... */
1019         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1020         if (IS_I945GM(dev))
1021                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1022         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1023         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1024         if (obj_priv->tiling_mode != I915_TILING_NONE)
1025                 fbc_ctl |= dev_priv->cfb_fence;
1026         I915_WRITE(FBC_CONTROL, fbc_ctl);
1027
1028         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1029                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1030 }
1031
1032 void i8xx_disable_fbc(struct drm_device *dev)
1033 {
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1036         u32 fbc_ctl;
1037
1038         if (!I915_HAS_FBC(dev))
1039                 return;
1040
1041         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1042                 return; /* Already off, just return */
1043
1044         /* Disable compression */
1045         fbc_ctl = I915_READ(FBC_CONTROL);
1046         fbc_ctl &= ~FBC_CTL_EN;
1047         I915_WRITE(FBC_CONTROL, fbc_ctl);
1048
1049         /* Wait for compressing bit to clear */
1050         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1051                 if (time_after(jiffies, timeout)) {
1052                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1053                         break;
1054                 }
1055                 ; /* do nothing */
1056         }
1057
1058         intel_wait_for_vblank(dev);
1059
1060         DRM_DEBUG_KMS("disabled FBC\n");
1061 }
1062
1063 static bool i8xx_fbc_enabled(struct drm_device *dev)
1064 {
1065         struct drm_i915_private *dev_priv = dev->dev_private;
1066
1067         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1068 }
1069
1070 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1071 {
1072         struct drm_device *dev = crtc->dev;
1073         struct drm_i915_private *dev_priv = dev->dev_private;
1074         struct drm_framebuffer *fb = crtc->fb;
1075         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1076         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1078         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1079                      DPFC_CTL_PLANEB);
1080         unsigned long stall_watermark = 200;
1081         u32 dpfc_ctl;
1082
1083         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1084         dev_priv->cfb_fence = obj_priv->fence_reg;
1085         dev_priv->cfb_plane = intel_crtc->plane;
1086
1087         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1088         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1089                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1090                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1091         } else {
1092                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1093         }
1094
1095         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1096         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1097                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1098                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1099         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1100
1101         /* enable it... */
1102         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1103
1104         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1105 }
1106
1107 void g4x_disable_fbc(struct drm_device *dev)
1108 {
1109         struct drm_i915_private *dev_priv = dev->dev_private;
1110         u32 dpfc_ctl;
1111
1112         /* Disable compression */
1113         dpfc_ctl = I915_READ(DPFC_CONTROL);
1114         dpfc_ctl &= ~DPFC_CTL_EN;
1115         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1116         intel_wait_for_vblank(dev);
1117
1118         DRM_DEBUG_KMS("disabled FBC\n");
1119 }
1120
1121 static bool g4x_fbc_enabled(struct drm_device *dev)
1122 {
1123         struct drm_i915_private *dev_priv = dev->dev_private;
1124
1125         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1126 }
1127
1128 bool intel_fbc_enabled(struct drm_device *dev)
1129 {
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131
1132         if (!dev_priv->display.fbc_enabled)
1133                 return false;
1134
1135         return dev_priv->display.fbc_enabled(dev);
1136 }
1137
1138 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1139 {
1140         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1141
1142         if (!dev_priv->display.enable_fbc)
1143                 return;
1144
1145         dev_priv->display.enable_fbc(crtc, interval);
1146 }
1147
1148 void intel_disable_fbc(struct drm_device *dev)
1149 {
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151
1152         if (!dev_priv->display.disable_fbc)
1153                 return;
1154
1155         dev_priv->display.disable_fbc(dev);
1156 }
1157
1158 /**
1159  * intel_update_fbc - enable/disable FBC as needed
1160  * @crtc: CRTC to point the compressor at
1161  * @mode: mode in use
1162  *
1163  * Set up the framebuffer compression hardware at mode set time.  We
1164  * enable it if possible:
1165  *   - plane A only (on pre-965)
1166  *   - no pixel mulitply/line duplication
1167  *   - no alpha buffer discard
1168  *   - no dual wide
1169  *   - framebuffer <= 2048 in width, 1536 in height
1170  *
1171  * We can't assume that any compression will take place (worst case),
1172  * so the compressed buffer has to be the same size as the uncompressed
1173  * one.  It also must reside (along with the line length buffer) in
1174  * stolen memory.
1175  *
1176  * We need to enable/disable FBC on a global basis.
1177  */
1178 static void intel_update_fbc(struct drm_crtc *crtc,
1179                              struct drm_display_mode *mode)
1180 {
1181         struct drm_device *dev = crtc->dev;
1182         struct drm_i915_private *dev_priv = dev->dev_private;
1183         struct drm_framebuffer *fb = crtc->fb;
1184         struct intel_framebuffer *intel_fb;
1185         struct drm_i915_gem_object *obj_priv;
1186         struct drm_crtc *tmp_crtc;
1187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1188         int plane = intel_crtc->plane;
1189         int crtcs_enabled = 0;
1190
1191         DRM_DEBUG_KMS("\n");
1192
1193         if (!i915_powersave)
1194                 return;
1195
1196         if (!I915_HAS_FBC(dev))
1197                 return;
1198
1199         if (!crtc->fb)
1200                 return;
1201
1202         intel_fb = to_intel_framebuffer(fb);
1203         obj_priv = to_intel_bo(intel_fb->obj);
1204
1205         /*
1206          * If FBC is already on, we just have to verify that we can
1207          * keep it that way...
1208          * Need to disable if:
1209          *   - more than one pipe is active
1210          *   - changing FBC params (stride, fence, mode)
1211          *   - new fb is too large to fit in compressed buffer
1212          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1213          */
1214         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1215                 if (tmp_crtc->enabled)
1216                         crtcs_enabled++;
1217         }
1218         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1219         if (crtcs_enabled > 1) {
1220                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1221                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1222                 goto out_disable;
1223         }
1224         if (intel_fb->obj->size > dev_priv->cfb_size) {
1225                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1226                                 "compression\n");
1227                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1228                 goto out_disable;
1229         }
1230         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1231             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1232                 DRM_DEBUG_KMS("mode incompatible with compression, "
1233                                 "disabling\n");
1234                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1235                 goto out_disable;
1236         }
1237         if ((mode->hdisplay > 2048) ||
1238             (mode->vdisplay > 1536)) {
1239                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1240                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1241                 goto out_disable;
1242         }
1243         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1244                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1245                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1246                 goto out_disable;
1247         }
1248         if (obj_priv->tiling_mode != I915_TILING_X) {
1249                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1250                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1251                 goto out_disable;
1252         }
1253
1254         if (intel_fbc_enabled(dev)) {
1255                 /* We can re-enable it in this case, but need to update pitch */
1256                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1257                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1258                     (plane != dev_priv->cfb_plane))
1259                         intel_disable_fbc(dev);
1260         }
1261
1262         /* Now try to turn it back on if possible */
1263         if (!intel_fbc_enabled(dev))
1264                 intel_enable_fbc(crtc, 500);
1265
1266         return;
1267
1268 out_disable:
1269         /* Multiple disables should be harmless */
1270         if (intel_fbc_enabled(dev)) {
1271                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1272                 intel_disable_fbc(dev);
1273         }
1274 }
1275
1276 int
1277 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1278 {
1279         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1280         u32 alignment;
1281         int ret;
1282
1283         switch (obj_priv->tiling_mode) {
1284         case I915_TILING_NONE:
1285                 alignment = 64 * 1024;
1286                 break;
1287         case I915_TILING_X:
1288                 /* pin() will align the object as required by fence */
1289                 alignment = 0;
1290                 break;
1291         case I915_TILING_Y:
1292                 /* FIXME: Is this true? */
1293                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1294                 return -EINVAL;
1295         default:
1296                 BUG();
1297         }
1298
1299         ret = i915_gem_object_pin(obj, alignment);
1300         if (ret != 0)
1301                 return ret;
1302
1303         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1304          * fence, whereas 965+ only requires a fence if using
1305          * framebuffer compression.  For simplicity, we always install
1306          * a fence as the cost is not that onerous.
1307          */
1308         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1309             obj_priv->tiling_mode != I915_TILING_NONE) {
1310                 ret = i915_gem_object_get_fence_reg(obj);
1311                 if (ret != 0) {
1312                         i915_gem_object_unpin(obj);
1313                         return ret;
1314                 }
1315         }
1316
1317         return 0;
1318 }
1319
1320 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1321 static int
1322 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1323                            int x, int y)
1324 {
1325         struct drm_device *dev = crtc->dev;
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1328         struct intel_framebuffer *intel_fb;
1329         struct drm_i915_gem_object *obj_priv;
1330         struct drm_gem_object *obj;
1331         int plane = intel_crtc->plane;
1332         unsigned long Start, Offset;
1333         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1334         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1335         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1336         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1337         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1338         u32 dspcntr;
1339
1340         switch (plane) {
1341         case 0:
1342         case 1:
1343                 break;
1344         default:
1345                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1346                 return -EINVAL;
1347         }
1348
1349         intel_fb = to_intel_framebuffer(fb);
1350         obj = intel_fb->obj;
1351         obj_priv = to_intel_bo(obj);
1352
1353         dspcntr = I915_READ(dspcntr_reg);
1354         /* Mask out pixel format bits in case we change it */
1355         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1356         switch (fb->bits_per_pixel) {
1357         case 8:
1358                 dspcntr |= DISPPLANE_8BPP;
1359                 break;
1360         case 16:
1361                 if (fb->depth == 15)
1362                         dspcntr |= DISPPLANE_15_16BPP;
1363                 else
1364                         dspcntr |= DISPPLANE_16BPP;
1365                 break;
1366         case 24:
1367         case 32:
1368                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1369                 break;
1370         default:
1371                 DRM_ERROR("Unknown color depth\n");
1372                 return -EINVAL;
1373         }
1374         if (IS_I965G(dev)) {
1375                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1376                         dspcntr |= DISPPLANE_TILED;
1377                 else
1378                         dspcntr &= ~DISPPLANE_TILED;
1379         }
1380
1381         if (IS_IRONLAKE(dev))
1382                 /* must disable */
1383                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1384
1385         I915_WRITE(dspcntr_reg, dspcntr);
1386
1387         Start = obj_priv->gtt_offset;
1388         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1389
1390         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1391         I915_WRITE(dspstride, fb->pitch);
1392         if (IS_I965G(dev)) {
1393                 I915_WRITE(dspbase, Offset);
1394                 I915_READ(dspbase);
1395                 I915_WRITE(dspsurf, Start);
1396                 I915_READ(dspsurf);
1397                 I915_WRITE(dsptileoff, (y << 16) | x);
1398         } else {
1399                 I915_WRITE(dspbase, Start + Offset);
1400                 I915_READ(dspbase);
1401         }
1402
1403         if ((IS_I965G(dev) || plane == 0))
1404                 intel_update_fbc(crtc, &crtc->mode);
1405
1406         intel_wait_for_vblank(dev);
1407         intel_increase_pllclock(crtc, true);
1408
1409         return 0;
1410 }
1411
1412 static int
1413 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1414                     struct drm_framebuffer *old_fb)
1415 {
1416         struct drm_device *dev = crtc->dev;
1417         struct drm_i915_private *dev_priv = dev->dev_private;
1418         struct drm_i915_master_private *master_priv;
1419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1420         struct intel_framebuffer *intel_fb;
1421         struct drm_i915_gem_object *obj_priv;
1422         struct drm_gem_object *obj;
1423         int pipe = intel_crtc->pipe;
1424         int plane = intel_crtc->plane;
1425         unsigned long Start, Offset;
1426         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1427         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1428         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1429         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1430         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1431         u32 dspcntr;
1432         int ret;
1433
1434         /* no fb bound */
1435         if (!crtc->fb) {
1436                 DRM_DEBUG_KMS("No FB bound\n");
1437                 return 0;
1438         }
1439
1440         switch (plane) {
1441         case 0:
1442         case 1:
1443                 break;
1444         default:
1445                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1446                 return -EINVAL;
1447         }
1448
1449         intel_fb = to_intel_framebuffer(crtc->fb);
1450         obj = intel_fb->obj;
1451         obj_priv = to_intel_bo(obj);
1452
1453         mutex_lock(&dev->struct_mutex);
1454         ret = intel_pin_and_fence_fb_obj(dev, obj);
1455         if (ret != 0) {
1456                 mutex_unlock(&dev->struct_mutex);
1457                 return ret;
1458         }
1459
1460         ret = i915_gem_object_set_to_display_plane(obj);
1461         if (ret != 0) {
1462                 i915_gem_object_unpin(obj);
1463                 mutex_unlock(&dev->struct_mutex);
1464                 return ret;
1465         }
1466
1467         dspcntr = I915_READ(dspcntr_reg);
1468         /* Mask out pixel format bits in case we change it */
1469         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1470         switch (crtc->fb->bits_per_pixel) {
1471         case 8:
1472                 dspcntr |= DISPPLANE_8BPP;
1473                 break;
1474         case 16:
1475                 if (crtc->fb->depth == 15)
1476                         dspcntr |= DISPPLANE_15_16BPP;
1477                 else
1478                         dspcntr |= DISPPLANE_16BPP;
1479                 break;
1480         case 24:
1481         case 32:
1482                 if (crtc->fb->depth == 30)
1483                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1484                 else
1485                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1486                 break;
1487         default:
1488                 DRM_ERROR("Unknown color depth\n");
1489                 i915_gem_object_unpin(obj);
1490                 mutex_unlock(&dev->struct_mutex);
1491                 return -EINVAL;
1492         }
1493         if (IS_I965G(dev)) {
1494                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1495                         dspcntr |= DISPPLANE_TILED;
1496                 else
1497                         dspcntr &= ~DISPPLANE_TILED;
1498         }
1499
1500         if (HAS_PCH_SPLIT(dev))
1501                 /* must disable */
1502                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1503
1504         I915_WRITE(dspcntr_reg, dspcntr);
1505
1506         Start = obj_priv->gtt_offset;
1507         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1508
1509         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1510                       Start, Offset, x, y, crtc->fb->pitch);
1511         I915_WRITE(dspstride, crtc->fb->pitch);
1512         if (IS_I965G(dev)) {
1513                 I915_WRITE(dspbase, Offset);
1514                 I915_READ(dspbase);
1515                 I915_WRITE(dspsurf, Start);
1516                 I915_READ(dspsurf);
1517                 I915_WRITE(dsptileoff, (y << 16) | x);
1518         } else {
1519                 I915_WRITE(dspbase, Start + Offset);
1520                 I915_READ(dspbase);
1521         }
1522
1523         if ((IS_I965G(dev) || plane == 0))
1524                 intel_update_fbc(crtc, &crtc->mode);
1525
1526         intel_wait_for_vblank(dev);
1527
1528         if (old_fb) {
1529                 intel_fb = to_intel_framebuffer(old_fb);
1530                 obj_priv = to_intel_bo(intel_fb->obj);
1531                 i915_gem_object_unpin(intel_fb->obj);
1532         }
1533         intel_increase_pllclock(crtc, true);
1534
1535         mutex_unlock(&dev->struct_mutex);
1536
1537         if (!dev->primary->master)
1538                 return 0;
1539
1540         master_priv = dev->primary->master->driver_priv;
1541         if (!master_priv->sarea_priv)
1542                 return 0;
1543
1544         if (pipe) {
1545                 master_priv->sarea_priv->pipeB_x = x;
1546                 master_priv->sarea_priv->pipeB_y = y;
1547         } else {
1548                 master_priv->sarea_priv->pipeA_x = x;
1549                 master_priv->sarea_priv->pipeA_y = y;
1550         }
1551
1552         return 0;
1553 }
1554
1555 /* Disable the VGA plane that we never use */
1556 static void i915_disable_vga (struct drm_device *dev)
1557 {
1558         struct drm_i915_private *dev_priv = dev->dev_private;
1559         u8 sr1;
1560         u32 vga_reg;
1561
1562         if (HAS_PCH_SPLIT(dev))
1563                 vga_reg = CPU_VGACNTRL;
1564         else
1565                 vga_reg = VGACNTRL;
1566
1567         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1568                 return;
1569
1570         I915_WRITE8(VGA_SR_INDEX, 1);
1571         sr1 = I915_READ8(VGA_SR_DATA);
1572         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1573         udelay(100);
1574
1575         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1576 }
1577
1578 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1579 {
1580         struct drm_device *dev = crtc->dev;
1581         struct drm_i915_private *dev_priv = dev->dev_private;
1582         u32 dpa_ctl;
1583
1584         DRM_DEBUG_KMS("\n");
1585         dpa_ctl = I915_READ(DP_A);
1586         dpa_ctl &= ~DP_PLL_ENABLE;
1587         I915_WRITE(DP_A, dpa_ctl);
1588 }
1589
1590 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1591 {
1592         struct drm_device *dev = crtc->dev;
1593         struct drm_i915_private *dev_priv = dev->dev_private;
1594         u32 dpa_ctl;
1595
1596         dpa_ctl = I915_READ(DP_A);
1597         dpa_ctl |= DP_PLL_ENABLE;
1598         I915_WRITE(DP_A, dpa_ctl);
1599         udelay(200);
1600 }
1601
1602
1603 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1604 {
1605         struct drm_device *dev = crtc->dev;
1606         struct drm_i915_private *dev_priv = dev->dev_private;
1607         u32 dpa_ctl;
1608
1609         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1610         dpa_ctl = I915_READ(DP_A);
1611         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1612
1613         if (clock < 200000) {
1614                 u32 temp;
1615                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1616                 /* workaround for 160Mhz:
1617                    1) program 0x4600c bits 15:0 = 0x8124
1618                    2) program 0x46010 bit 0 = 1
1619                    3) program 0x46034 bit 24 = 1
1620                    4) program 0x64000 bit 14 = 1
1621                    */
1622                 temp = I915_READ(0x4600c);
1623                 temp &= 0xffff0000;
1624                 I915_WRITE(0x4600c, temp | 0x8124);
1625
1626                 temp = I915_READ(0x46010);
1627                 I915_WRITE(0x46010, temp | 1);
1628
1629                 temp = I915_READ(0x46034);
1630                 I915_WRITE(0x46034, temp | (1 << 24));
1631         } else {
1632                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1633         }
1634         I915_WRITE(DP_A, dpa_ctl);
1635
1636         udelay(500);
1637 }
1638
1639 /* The FDI link training functions for ILK/Ibexpeak. */
1640 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1641 {
1642         struct drm_device *dev = crtc->dev;
1643         struct drm_i915_private *dev_priv = dev->dev_private;
1644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1645         int pipe = intel_crtc->pipe;
1646         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1647         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1648         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1649         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1650         u32 temp, tries = 0;
1651
1652         /* enable CPU FDI TX and PCH FDI RX */
1653         temp = I915_READ(fdi_tx_reg);
1654         temp |= FDI_TX_ENABLE;
1655         temp &= ~(7 << 19);
1656         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1657         temp &= ~FDI_LINK_TRAIN_NONE;
1658         temp |= FDI_LINK_TRAIN_PATTERN_1;
1659         I915_WRITE(fdi_tx_reg, temp);
1660         I915_READ(fdi_tx_reg);
1661
1662         temp = I915_READ(fdi_rx_reg);
1663         temp &= ~FDI_LINK_TRAIN_NONE;
1664         temp |= FDI_LINK_TRAIN_PATTERN_1;
1665         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1666         I915_READ(fdi_rx_reg);
1667         udelay(150);
1668
1669         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1670            for train result */
1671         temp = I915_READ(fdi_rx_imr_reg);
1672         temp &= ~FDI_RX_SYMBOL_LOCK;
1673         temp &= ~FDI_RX_BIT_LOCK;
1674         I915_WRITE(fdi_rx_imr_reg, temp);
1675         I915_READ(fdi_rx_imr_reg);
1676         udelay(150);
1677
1678         for (;;) {
1679                 temp = I915_READ(fdi_rx_iir_reg);
1680                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1681
1682                 if ((temp & FDI_RX_BIT_LOCK)) {
1683                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1684                         I915_WRITE(fdi_rx_iir_reg,
1685                                    temp | FDI_RX_BIT_LOCK);
1686                         break;
1687                 }
1688
1689                 tries++;
1690
1691                 if (tries > 5) {
1692                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1693                         break;
1694                 }
1695         }
1696
1697         /* Train 2 */
1698         temp = I915_READ(fdi_tx_reg);
1699         temp &= ~FDI_LINK_TRAIN_NONE;
1700         temp |= FDI_LINK_TRAIN_PATTERN_2;
1701         I915_WRITE(fdi_tx_reg, temp);
1702
1703         temp = I915_READ(fdi_rx_reg);
1704         temp &= ~FDI_LINK_TRAIN_NONE;
1705         temp |= FDI_LINK_TRAIN_PATTERN_2;
1706         I915_WRITE(fdi_rx_reg, temp);
1707         udelay(150);
1708
1709         tries = 0;
1710
1711         for (;;) {
1712                 temp = I915_READ(fdi_rx_iir_reg);
1713                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1714
1715                 if (temp & FDI_RX_SYMBOL_LOCK) {
1716                         I915_WRITE(fdi_rx_iir_reg,
1717                                    temp | FDI_RX_SYMBOL_LOCK);
1718                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1719                         break;
1720                 }
1721
1722                 tries++;
1723
1724                 if (tries > 5) {
1725                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1726                         break;
1727                 }
1728         }
1729
1730         DRM_DEBUG_KMS("FDI train done\n");
1731 }
1732
1733 static int snb_b_fdi_train_param [] = {
1734         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1735         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1736         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1737         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1738 };
1739
1740 /* The FDI link training functions for SNB/Cougarpoint. */
1741 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1742 {
1743         struct drm_device *dev = crtc->dev;
1744         struct drm_i915_private *dev_priv = dev->dev_private;
1745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1746         int pipe = intel_crtc->pipe;
1747         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1748         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1749         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1750         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1751         u32 temp, i;
1752
1753         /* enable CPU FDI TX and PCH FDI RX */
1754         temp = I915_READ(fdi_tx_reg);
1755         temp |= FDI_TX_ENABLE;
1756         temp &= ~(7 << 19);
1757         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1758         temp &= ~FDI_LINK_TRAIN_NONE;
1759         temp |= FDI_LINK_TRAIN_PATTERN_1;
1760         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1761         /* SNB-B */
1762         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1763         I915_WRITE(fdi_tx_reg, temp);
1764         I915_READ(fdi_tx_reg);
1765
1766         temp = I915_READ(fdi_rx_reg);
1767         if (HAS_PCH_CPT(dev)) {
1768                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1769                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1770         } else {
1771                 temp &= ~FDI_LINK_TRAIN_NONE;
1772                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1773         }
1774         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1775         I915_READ(fdi_rx_reg);
1776         udelay(150);
1777
1778         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1779            for train result */
1780         temp = I915_READ(fdi_rx_imr_reg);
1781         temp &= ~FDI_RX_SYMBOL_LOCK;
1782         temp &= ~FDI_RX_BIT_LOCK;
1783         I915_WRITE(fdi_rx_imr_reg, temp);
1784         I915_READ(fdi_rx_imr_reg);
1785         udelay(150);
1786
1787         for (i = 0; i < 4; i++ ) {
1788                 temp = I915_READ(fdi_tx_reg);
1789                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1790                 temp |= snb_b_fdi_train_param[i];
1791                 I915_WRITE(fdi_tx_reg, temp);
1792                 udelay(500);
1793
1794                 temp = I915_READ(fdi_rx_iir_reg);
1795                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1796
1797                 if (temp & FDI_RX_BIT_LOCK) {
1798                         I915_WRITE(fdi_rx_iir_reg,
1799                                    temp | FDI_RX_BIT_LOCK);
1800                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1801                         break;
1802                 }
1803         }
1804         if (i == 4)
1805                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1806
1807         /* Train 2 */
1808         temp = I915_READ(fdi_tx_reg);
1809         temp &= ~FDI_LINK_TRAIN_NONE;
1810         temp |= FDI_LINK_TRAIN_PATTERN_2;
1811         if (IS_GEN6(dev)) {
1812                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1813                 /* SNB-B */
1814                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1815         }
1816         I915_WRITE(fdi_tx_reg, temp);
1817
1818         temp = I915_READ(fdi_rx_reg);
1819         if (HAS_PCH_CPT(dev)) {
1820                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1821                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1822         } else {
1823                 temp &= ~FDI_LINK_TRAIN_NONE;
1824                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1825         }
1826         I915_WRITE(fdi_rx_reg, temp);
1827         udelay(150);
1828
1829         for (i = 0; i < 4; i++ ) {
1830                 temp = I915_READ(fdi_tx_reg);
1831                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1832                 temp |= snb_b_fdi_train_param[i];
1833                 I915_WRITE(fdi_tx_reg, temp);
1834                 udelay(500);
1835
1836                 temp = I915_READ(fdi_rx_iir_reg);
1837                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1838
1839                 if (temp & FDI_RX_SYMBOL_LOCK) {
1840                         I915_WRITE(fdi_rx_iir_reg,
1841                                    temp | FDI_RX_SYMBOL_LOCK);
1842                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1843                         break;
1844                 }
1845         }
1846         if (i == 4)
1847                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1848
1849         DRM_DEBUG_KMS("FDI train done.\n");
1850 }
1851
1852 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1853 {
1854         struct drm_device *dev = crtc->dev;
1855         struct drm_i915_private *dev_priv = dev->dev_private;
1856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1857         int pipe = intel_crtc->pipe;
1858         int plane = intel_crtc->plane;
1859         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1860         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1861         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1862         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1863         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1864         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1865         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1866         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1867         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1868         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1869         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1870         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1871         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1872         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1873         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1874         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1875         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1876         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1877         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1878         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1879         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1880         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1881         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1882         u32 temp;
1883         int n;
1884         u32 pipe_bpc;
1885
1886         temp = I915_READ(pipeconf_reg);
1887         pipe_bpc = temp & PIPE_BPC_MASK;
1888
1889         /* XXX: When our outputs are all unaware of DPMS modes other than off
1890          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1891          */
1892         switch (mode) {
1893         case DRM_MODE_DPMS_ON:
1894         case DRM_MODE_DPMS_STANDBY:
1895         case DRM_MODE_DPMS_SUSPEND:
1896                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1897
1898                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1899                         temp = I915_READ(PCH_LVDS);
1900                         if ((temp & LVDS_PORT_EN) == 0) {
1901                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1902                                 POSTING_READ(PCH_LVDS);
1903                         }
1904                 }
1905
1906                 if (HAS_eDP) {
1907                         /* enable eDP PLL */
1908                         ironlake_enable_pll_edp(crtc);
1909                 } else {
1910
1911                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1912                         temp = I915_READ(fdi_rx_reg);
1913                         /*
1914                          * make the BPC in FDI Rx be consistent with that in
1915                          * pipeconf reg.
1916                          */
1917                         temp &= ~(0x7 << 16);
1918                         temp |= (pipe_bpc << 11);
1919                         temp &= ~(7 << 19);
1920                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1921                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1922                         I915_READ(fdi_rx_reg);
1923                         udelay(200);
1924
1925                         /* Switch from Rawclk to PCDclk */
1926                         temp = I915_READ(fdi_rx_reg);
1927                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1928                         I915_READ(fdi_rx_reg);
1929                         udelay(200);
1930
1931                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1932                         temp = I915_READ(fdi_tx_reg);
1933                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1934                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1935                                 I915_READ(fdi_tx_reg);
1936                                 udelay(100);
1937                         }
1938                 }
1939
1940                 /* Enable panel fitting for LVDS */
1941                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1942                         temp = I915_READ(pf_ctl_reg);
1943                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1944
1945                         /* currently full aspect */
1946                         I915_WRITE(pf_win_pos, 0);
1947
1948                         I915_WRITE(pf_win_size,
1949                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1950                                    (dev_priv->panel_fixed_mode->vdisplay));
1951                 }
1952
1953                 /* Enable CPU pipe */
1954                 temp = I915_READ(pipeconf_reg);
1955                 if ((temp & PIPEACONF_ENABLE) == 0) {
1956                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1957                         I915_READ(pipeconf_reg);
1958                         udelay(100);
1959                 }
1960
1961                 /* configure and enable CPU plane */
1962                 temp = I915_READ(dspcntr_reg);
1963                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1964                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1965                         /* Flush the plane changes */
1966                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1967                 }
1968
1969                 if (!HAS_eDP) {
1970                         /* For PCH output, training FDI link */
1971                         if (IS_GEN6(dev))
1972                                 gen6_fdi_link_train(crtc);
1973                         else
1974                                 ironlake_fdi_link_train(crtc);
1975
1976                         /* enable PCH DPLL */
1977                         temp = I915_READ(pch_dpll_reg);
1978                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1979                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1980                                 I915_READ(pch_dpll_reg);
1981                         }
1982                         udelay(200);
1983
1984                         if (HAS_PCH_CPT(dev)) {
1985                                 /* Be sure PCH DPLL SEL is set */
1986                                 temp = I915_READ(PCH_DPLL_SEL);
1987                                 if (trans_dpll_sel == 0 &&
1988                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1989                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1990                                 else if (trans_dpll_sel == 1 &&
1991                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1992                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1993                                 I915_WRITE(PCH_DPLL_SEL, temp);
1994                                 I915_READ(PCH_DPLL_SEL);
1995                         }
1996
1997                         /* set transcoder timing */
1998                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1999                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2000                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2001
2002                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2003                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2004                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2005
2006                         /* enable normal train */
2007                         temp = I915_READ(fdi_tx_reg);
2008                         temp &= ~FDI_LINK_TRAIN_NONE;
2009                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2010                                         FDI_TX_ENHANCE_FRAME_ENABLE);
2011                         I915_READ(fdi_tx_reg);
2012
2013                         temp = I915_READ(fdi_rx_reg);
2014                         if (HAS_PCH_CPT(dev)) {
2015                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2016                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2017                         } else {
2018                                 temp &= ~FDI_LINK_TRAIN_NONE;
2019                                 temp |= FDI_LINK_TRAIN_NONE;
2020                         }
2021                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2022                         I915_READ(fdi_rx_reg);
2023
2024                         /* wait one idle pattern time */
2025                         udelay(100);
2026
2027                         /* For PCH DP, enable TRANS_DP_CTL */
2028                         if (HAS_PCH_CPT(dev) &&
2029                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2030                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2031                                 int reg;
2032
2033                                 reg = I915_READ(trans_dp_ctl);
2034                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
2035                                 reg = TRANS_DP_OUTPUT_ENABLE |
2036                                       TRANS_DP_ENH_FRAMING |
2037                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
2038                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
2039
2040                                 switch (intel_trans_dp_port_sel(crtc)) {
2041                                 case PCH_DP_B:
2042                                         reg |= TRANS_DP_PORT_SEL_B;
2043                                         break;
2044                                 case PCH_DP_C:
2045                                         reg |= TRANS_DP_PORT_SEL_C;
2046                                         break;
2047                                 case PCH_DP_D:
2048                                         reg |= TRANS_DP_PORT_SEL_D;
2049                                         break;
2050                                 default:
2051                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2052                                         reg |= TRANS_DP_PORT_SEL_B;
2053                                         break;
2054                                 }
2055
2056                                 I915_WRITE(trans_dp_ctl, reg);
2057                                 POSTING_READ(trans_dp_ctl);
2058                         }
2059
2060                         /* enable PCH transcoder */
2061                         temp = I915_READ(transconf_reg);
2062                         /*
2063                          * make the BPC in transcoder be consistent with
2064                          * that in pipeconf reg.
2065                          */
2066                         temp &= ~PIPE_BPC_MASK;
2067                         temp |= pipe_bpc;
2068                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2069                         I915_READ(transconf_reg);
2070
2071                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
2072                                 ;
2073
2074                 }
2075
2076                 intel_crtc_load_lut(crtc);
2077
2078         break;
2079         case DRM_MODE_DPMS_OFF:
2080                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
2081
2082                 drm_vblank_off(dev, pipe);
2083                 /* Disable display plane */
2084                 temp = I915_READ(dspcntr_reg);
2085                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2086                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2087                         /* Flush the plane changes */
2088                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2089                         I915_READ(dspbase_reg);
2090                 }
2091
2092                 i915_disable_vga(dev);
2093
2094                 /* disable cpu pipe, disable after all planes disabled */
2095                 temp = I915_READ(pipeconf_reg);
2096                 if ((temp & PIPEACONF_ENABLE) != 0) {
2097                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2098                         I915_READ(pipeconf_reg);
2099                         n = 0;
2100                         /* wait for cpu pipe off, pipe state */
2101                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2102                                 n++;
2103                                 if (n < 60) {
2104                                         udelay(500);
2105                                         continue;
2106                                 } else {
2107                                         DRM_DEBUG_KMS("pipe %d off delay\n",
2108                                                                 pipe);
2109                                         break;
2110                                 }
2111                         }
2112                 } else
2113                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2114
2115                 udelay(100);
2116
2117                 /* Disable PF */
2118                 temp = I915_READ(pf_ctl_reg);
2119                 if ((temp & PF_ENABLE) != 0) {
2120                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2121                         I915_READ(pf_ctl_reg);
2122                 }
2123                 I915_WRITE(pf_win_size, 0);
2124                 POSTING_READ(pf_win_size);
2125
2126
2127                 /* disable CPU FDI tx and PCH FDI rx */
2128                 temp = I915_READ(fdi_tx_reg);
2129                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2130                 I915_READ(fdi_tx_reg);
2131
2132                 temp = I915_READ(fdi_rx_reg);
2133                 /* BPC in FDI rx is consistent with that in pipeconf */
2134                 temp &= ~(0x07 << 16);
2135                 temp |= (pipe_bpc << 11);
2136                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2137                 I915_READ(fdi_rx_reg);
2138
2139                 udelay(100);
2140
2141                 /* still set train pattern 1 */
2142                 temp = I915_READ(fdi_tx_reg);
2143                 temp &= ~FDI_LINK_TRAIN_NONE;
2144                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2145                 I915_WRITE(fdi_tx_reg, temp);
2146                 POSTING_READ(fdi_tx_reg);
2147
2148                 temp = I915_READ(fdi_rx_reg);
2149                 if (HAS_PCH_CPT(dev)) {
2150                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2151                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2152                 } else {
2153                         temp &= ~FDI_LINK_TRAIN_NONE;
2154                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2155                 }
2156                 I915_WRITE(fdi_rx_reg, temp);
2157                 POSTING_READ(fdi_rx_reg);
2158
2159                 udelay(100);
2160
2161                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2162                         temp = I915_READ(PCH_LVDS);
2163                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2164                         I915_READ(PCH_LVDS);
2165                         udelay(100);
2166                 }
2167
2168                 /* disable PCH transcoder */
2169                 temp = I915_READ(transconf_reg);
2170                 if ((temp & TRANS_ENABLE) != 0) {
2171                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2172                         I915_READ(transconf_reg);
2173                         n = 0;
2174                         /* wait for PCH transcoder off, transcoder state */
2175                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2176                                 n++;
2177                                 if (n < 60) {
2178                                         udelay(500);
2179                                         continue;
2180                                 } else {
2181                                         DRM_DEBUG_KMS("transcoder %d off "
2182                                                         "delay\n", pipe);
2183                                         break;
2184                                 }
2185                         }
2186                 }
2187
2188                 temp = I915_READ(transconf_reg);
2189                 /* BPC in transcoder is consistent with that in pipeconf */
2190                 temp &= ~PIPE_BPC_MASK;
2191                 temp |= pipe_bpc;
2192                 I915_WRITE(transconf_reg, temp);
2193                 I915_READ(transconf_reg);
2194                 udelay(100);
2195
2196                 if (HAS_PCH_CPT(dev)) {
2197                         /* disable TRANS_DP_CTL */
2198                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2199                         int reg;
2200
2201                         reg = I915_READ(trans_dp_ctl);
2202                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2203                         I915_WRITE(trans_dp_ctl, reg);
2204                         POSTING_READ(trans_dp_ctl);
2205
2206                         /* disable DPLL_SEL */
2207                         temp = I915_READ(PCH_DPLL_SEL);
2208                         if (trans_dpll_sel == 0)
2209                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2210                         else
2211                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2212                         I915_WRITE(PCH_DPLL_SEL, temp);
2213                         I915_READ(PCH_DPLL_SEL);
2214
2215                 }
2216
2217                 /* disable PCH DPLL */
2218                 temp = I915_READ(pch_dpll_reg);
2219                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2220                 I915_READ(pch_dpll_reg);
2221
2222                 if (HAS_eDP) {
2223                         ironlake_disable_pll_edp(crtc);
2224                 }
2225
2226                 /* Switch from PCDclk to Rawclk */
2227                 temp = I915_READ(fdi_rx_reg);
2228                 temp &= ~FDI_SEL_PCDCLK;
2229                 I915_WRITE(fdi_rx_reg, temp);
2230                 I915_READ(fdi_rx_reg);
2231
2232                 /* Disable CPU FDI TX PLL */
2233                 temp = I915_READ(fdi_tx_reg);
2234                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2235                 I915_READ(fdi_tx_reg);
2236                 udelay(100);
2237
2238                 temp = I915_READ(fdi_rx_reg);
2239                 temp &= ~FDI_RX_PLL_ENABLE;
2240                 I915_WRITE(fdi_rx_reg, temp);
2241                 I915_READ(fdi_rx_reg);
2242
2243                 /* Wait for the clocks to turn off. */
2244                 udelay(100);
2245                 break;
2246         }
2247 }
2248
2249 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2250 {
2251         struct intel_overlay *overlay;
2252         int ret;
2253
2254         if (!enable && intel_crtc->overlay) {
2255                 overlay = intel_crtc->overlay;
2256                 mutex_lock(&overlay->dev->struct_mutex);
2257                 for (;;) {
2258                         ret = intel_overlay_switch_off(overlay);
2259                         if (ret == 0)
2260                                 break;
2261
2262                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2263                         if (ret != 0) {
2264                                 /* overlay doesn't react anymore. Usually
2265                                  * results in a black screen and an unkillable
2266                                  * X server. */
2267                                 BUG();
2268                                 overlay->hw_wedged = HW_WEDGED;
2269                                 break;
2270                         }
2271                 }
2272                 mutex_unlock(&overlay->dev->struct_mutex);
2273         }
2274         /* Let userspace switch the overlay on again. In most cases userspace
2275          * has to recompute where to put it anyway. */
2276
2277         return;
2278 }
2279
2280 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2281 {
2282         struct drm_device *dev = crtc->dev;
2283         struct drm_i915_private *dev_priv = dev->dev_private;
2284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2285         int pipe = intel_crtc->pipe;
2286         int plane = intel_crtc->plane;
2287         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2288         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2289         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2290         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2291         u32 temp;
2292
2293         /* XXX: When our outputs are all unaware of DPMS modes other than off
2294          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2295          */
2296         switch (mode) {
2297         case DRM_MODE_DPMS_ON:
2298         case DRM_MODE_DPMS_STANDBY:
2299         case DRM_MODE_DPMS_SUSPEND:
2300                 intel_update_watermarks(dev);
2301
2302                 /* Enable the DPLL */
2303                 temp = I915_READ(dpll_reg);
2304                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2305                         I915_WRITE(dpll_reg, temp);
2306                         I915_READ(dpll_reg);
2307                         /* Wait for the clocks to stabilize. */
2308                         udelay(150);
2309                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2310                         I915_READ(dpll_reg);
2311                         /* Wait for the clocks to stabilize. */
2312                         udelay(150);
2313                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2314                         I915_READ(dpll_reg);
2315                         /* Wait for the clocks to stabilize. */
2316                         udelay(150);
2317                 }
2318
2319                 /* Enable the pipe */
2320                 temp = I915_READ(pipeconf_reg);
2321                 if ((temp & PIPEACONF_ENABLE) == 0)
2322                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2323
2324                 /* Enable the plane */
2325                 temp = I915_READ(dspcntr_reg);
2326                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2327                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2328                         /* Flush the plane changes */
2329                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2330                 }
2331
2332                 intel_crtc_load_lut(crtc);
2333
2334                 if ((IS_I965G(dev) || plane == 0))
2335                         intel_update_fbc(crtc, &crtc->mode);
2336
2337                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2338                 intel_crtc_dpms_overlay(intel_crtc, true);
2339         break;
2340         case DRM_MODE_DPMS_OFF:
2341                 intel_update_watermarks(dev);
2342
2343                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2344                 intel_crtc_dpms_overlay(intel_crtc, false);
2345                 drm_vblank_off(dev, pipe);
2346
2347                 if (dev_priv->cfb_plane == plane &&
2348                     dev_priv->display.disable_fbc)
2349                         dev_priv->display.disable_fbc(dev);
2350
2351                 /* Disable the VGA plane that we never use */
2352                 i915_disable_vga(dev);
2353
2354                 /* Disable display plane */
2355                 temp = I915_READ(dspcntr_reg);
2356                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2357                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2358                         /* Flush the plane changes */
2359                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2360                         I915_READ(dspbase_reg);
2361                 }
2362
2363                 if (!IS_I9XX(dev)) {
2364                         /* Wait for vblank for the disable to take effect */
2365                         intel_wait_for_vblank(dev);
2366                 }
2367
2368                 /* Don't disable pipe A or pipe A PLLs if needed */
2369                 if (pipeconf_reg == PIPEACONF &&
2370                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2371                         goto skip_pipe_off;
2372
2373                 /* Next, disable display pipes */
2374                 temp = I915_READ(pipeconf_reg);
2375                 if ((temp & PIPEACONF_ENABLE) != 0) {
2376                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2377                         I915_READ(pipeconf_reg);
2378                 }
2379
2380                 /* Wait for vblank for the disable to take effect. */
2381                 intel_wait_for_vblank(dev);
2382
2383                 temp = I915_READ(dpll_reg);
2384                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2385                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2386                         I915_READ(dpll_reg);
2387                 }
2388         skip_pipe_off:
2389                 /* Wait for the clocks to turn off. */
2390                 udelay(150);
2391                 break;
2392         }
2393 }
2394
2395 /**
2396  * Sets the power management mode of the pipe and plane.
2397  *
2398  * This code should probably grow support for turning the cursor off and back
2399  * on appropriately at the same time as we're turning the pipe off/on.
2400  */
2401 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2402 {
2403         struct drm_device *dev = crtc->dev;
2404         struct drm_i915_private *dev_priv = dev->dev_private;
2405         struct drm_i915_master_private *master_priv;
2406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2407         int pipe = intel_crtc->pipe;
2408         bool enabled;
2409
2410         dev_priv->display.dpms(crtc, mode);
2411
2412         intel_crtc->dpms_mode = mode;
2413
2414         if (!dev->primary->master)
2415                 return;
2416
2417         master_priv = dev->primary->master->driver_priv;
2418         if (!master_priv->sarea_priv)
2419                 return;
2420
2421         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2422
2423         switch (pipe) {
2424         case 0:
2425                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2426                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2427                 break;
2428         case 1:
2429                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2430                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2431                 break;
2432         default:
2433                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2434                 break;
2435         }
2436 }
2437
2438 static void intel_crtc_prepare (struct drm_crtc *crtc)
2439 {
2440         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2441         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2442 }
2443
2444 static void intel_crtc_commit (struct drm_crtc *crtc)
2445 {
2446         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2447         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2448 }
2449
2450 void intel_encoder_prepare (struct drm_encoder *encoder)
2451 {
2452         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2453         /* lvds has its own version of prepare see intel_lvds_prepare */
2454         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2455 }
2456
2457 void intel_encoder_commit (struct drm_encoder *encoder)
2458 {
2459         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2460         /* lvds has its own version of commit see intel_lvds_commit */
2461         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2462 }
2463
2464 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2465                                   struct drm_display_mode *mode,
2466                                   struct drm_display_mode *adjusted_mode)
2467 {
2468         struct drm_device *dev = crtc->dev;
2469         if (HAS_PCH_SPLIT(dev)) {
2470                 /* FDI link clock is fixed at 2.7G */
2471                 if (mode->clock * 3 > 27000 * 4)
2472                         return MODE_CLOCK_HIGH;
2473         }
2474         return true;
2475 }
2476
2477 static int i945_get_display_clock_speed(struct drm_device *dev)
2478 {
2479         return 400000;
2480 }
2481
2482 static int i915_get_display_clock_speed(struct drm_device *dev)
2483 {
2484         return 333000;
2485 }
2486
2487 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2488 {
2489         return 200000;
2490 }
2491
2492 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2493 {
2494         u16 gcfgc = 0;
2495
2496         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2497
2498         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2499                 return 133000;
2500         else {
2501                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2502                 case GC_DISPLAY_CLOCK_333_MHZ:
2503                         return 333000;
2504                 default:
2505                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2506                         return 190000;
2507                 }
2508         }
2509 }
2510
2511 static int i865_get_display_clock_speed(struct drm_device *dev)
2512 {
2513         return 266000;
2514 }
2515
2516 static int i855_get_display_clock_speed(struct drm_device *dev)
2517 {
2518         u16 hpllcc = 0;
2519         /* Assume that the hardware is in the high speed state.  This
2520          * should be the default.
2521          */
2522         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2523         case GC_CLOCK_133_200:
2524         case GC_CLOCK_100_200:
2525                 return 200000;
2526         case GC_CLOCK_166_250:
2527                 return 250000;
2528         case GC_CLOCK_100_133:
2529                 return 133000;
2530         }
2531
2532         /* Shouldn't happen */
2533         return 0;
2534 }
2535
2536 static int i830_get_display_clock_speed(struct drm_device *dev)
2537 {
2538         return 133000;
2539 }
2540
2541 /**
2542  * Return the pipe currently connected to the panel fitter,
2543  * or -1 if the panel fitter is not present or not in use
2544  */
2545 int intel_panel_fitter_pipe (struct drm_device *dev)
2546 {
2547         struct drm_i915_private *dev_priv = dev->dev_private;
2548         u32  pfit_control;
2549
2550         /* i830 doesn't have a panel fitter */
2551         if (IS_I830(dev))
2552                 return -1;
2553
2554         pfit_control = I915_READ(PFIT_CONTROL);
2555
2556         /* See if the panel fitter is in use */
2557         if ((pfit_control & PFIT_ENABLE) == 0)
2558                 return -1;
2559
2560         /* 965 can place panel fitter on either pipe */
2561         if (IS_I965G(dev))
2562                 return (pfit_control >> 29) & 0x3;
2563
2564         /* older chips can only use pipe 1 */
2565         return 1;
2566 }
2567
2568 struct fdi_m_n {
2569         u32        tu;
2570         u32        gmch_m;
2571         u32        gmch_n;
2572         u32        link_m;
2573         u32        link_n;
2574 };
2575
2576 static void
2577 fdi_reduce_ratio(u32 *num, u32 *den)
2578 {
2579         while (*num > 0xffffff || *den > 0xffffff) {
2580                 *num >>= 1;
2581                 *den >>= 1;
2582         }
2583 }
2584
2585 #define DATA_N 0x800000
2586 #define LINK_N 0x80000
2587
2588 static void
2589 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2590                      int link_clock, struct fdi_m_n *m_n)
2591 {
2592         u64 temp;
2593
2594         m_n->tu = 64; /* default size */
2595
2596         temp = (u64) DATA_N * pixel_clock;
2597         temp = div_u64(temp, link_clock);
2598         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2599         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2600         m_n->gmch_n = DATA_N;
2601         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2602
2603         temp = (u64) LINK_N * pixel_clock;
2604         m_n->link_m = div_u64(temp, link_clock);
2605         m_n->link_n = LINK_N;
2606         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2607 }
2608
2609
2610 struct intel_watermark_params {
2611         unsigned long fifo_size;
2612         unsigned long max_wm;
2613         unsigned long default_wm;
2614         unsigned long guard_size;
2615         unsigned long cacheline_size;
2616 };
2617
2618 /* Pineview has different values for various configs */
2619 static struct intel_watermark_params pineview_display_wm = {
2620         PINEVIEW_DISPLAY_FIFO,
2621         PINEVIEW_MAX_WM,
2622         PINEVIEW_DFT_WM,
2623         PINEVIEW_GUARD_WM,
2624         PINEVIEW_FIFO_LINE_SIZE
2625 };
2626 static struct intel_watermark_params pineview_display_hplloff_wm = {
2627         PINEVIEW_DISPLAY_FIFO,
2628         PINEVIEW_MAX_WM,
2629         PINEVIEW_DFT_HPLLOFF_WM,
2630         PINEVIEW_GUARD_WM,
2631         PINEVIEW_FIFO_LINE_SIZE
2632 };
2633 static struct intel_watermark_params pineview_cursor_wm = {
2634         PINEVIEW_CURSOR_FIFO,
2635         PINEVIEW_CURSOR_MAX_WM,
2636         PINEVIEW_CURSOR_DFT_WM,
2637         PINEVIEW_CURSOR_GUARD_WM,
2638         PINEVIEW_FIFO_LINE_SIZE,
2639 };
2640 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2641         PINEVIEW_CURSOR_FIFO,
2642         PINEVIEW_CURSOR_MAX_WM,
2643         PINEVIEW_CURSOR_DFT_WM,
2644         PINEVIEW_CURSOR_GUARD_WM,
2645         PINEVIEW_FIFO_LINE_SIZE
2646 };
2647 static struct intel_watermark_params g4x_wm_info = {
2648         G4X_FIFO_SIZE,
2649         G4X_MAX_WM,
2650         G4X_MAX_WM,
2651         2,
2652         G4X_FIFO_LINE_SIZE,
2653 };
2654 static struct intel_watermark_params i945_wm_info = {
2655         I945_FIFO_SIZE,
2656         I915_MAX_WM,
2657         1,
2658         2,
2659         I915_FIFO_LINE_SIZE
2660 };
2661 static struct intel_watermark_params i915_wm_info = {
2662         I915_FIFO_SIZE,
2663         I915_MAX_WM,
2664         1,
2665         2,
2666         I915_FIFO_LINE_SIZE
2667 };
2668 static struct intel_watermark_params i855_wm_info = {
2669         I855GM_FIFO_SIZE,
2670         I915_MAX_WM,
2671         1,
2672         2,
2673         I830_FIFO_LINE_SIZE
2674 };
2675 static struct intel_watermark_params i830_wm_info = {
2676         I830_FIFO_SIZE,
2677         I915_MAX_WM,
2678         1,
2679         2,
2680         I830_FIFO_LINE_SIZE
2681 };
2682
2683 static struct intel_watermark_params ironlake_display_wm_info = {
2684         ILK_DISPLAY_FIFO,
2685         ILK_DISPLAY_MAXWM,
2686         ILK_DISPLAY_DFTWM,
2687         2,
2688         ILK_FIFO_LINE_SIZE
2689 };
2690
2691 static struct intel_watermark_params ironlake_display_srwm_info = {
2692         ILK_DISPLAY_SR_FIFO,
2693         ILK_DISPLAY_MAX_SRWM,
2694         ILK_DISPLAY_DFT_SRWM,
2695         2,
2696         ILK_FIFO_LINE_SIZE
2697 };
2698
2699 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2700         ILK_CURSOR_SR_FIFO,
2701         ILK_CURSOR_MAX_SRWM,
2702         ILK_CURSOR_DFT_SRWM,
2703         2,
2704         ILK_FIFO_LINE_SIZE
2705 };
2706
2707 /**
2708  * intel_calculate_wm - calculate watermark level
2709  * @clock_in_khz: pixel clock
2710  * @wm: chip FIFO params
2711  * @pixel_size: display pixel size
2712  * @latency_ns: memory latency for the platform
2713  *
2714  * Calculate the watermark level (the level at which the display plane will
2715  * start fetching from memory again).  Each chip has a different display
2716  * FIFO size and allocation, so the caller needs to figure that out and pass
2717  * in the correct intel_watermark_params structure.
2718  *
2719  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2720  * on the pixel size.  When it reaches the watermark level, it'll start
2721  * fetching FIFO line sized based chunks from memory until the FIFO fills
2722  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2723  * will occur, and a display engine hang could result.
2724  */
2725 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2726                                         struct intel_watermark_params *wm,
2727                                         int pixel_size,
2728                                         unsigned long latency_ns)
2729 {
2730         long entries_required, wm_size;
2731
2732         /*
2733          * Note: we need to make sure we don't overflow for various clock &
2734          * latency values.
2735          * clocks go from a few thousand to several hundred thousand.
2736          * latency is usually a few thousand
2737          */
2738         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2739                 1000;
2740         entries_required /= wm->cacheline_size;
2741
2742         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2743
2744         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2745
2746         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2747
2748         /* Don't promote wm_size to unsigned... */
2749         if (wm_size > (long)wm->max_wm)
2750                 wm_size = wm->max_wm;
2751         if (wm_size <= 0)
2752                 wm_size = wm->default_wm;
2753         return wm_size;
2754 }
2755
2756 struct cxsr_latency {
2757         int is_desktop;
2758         int is_ddr3;
2759         unsigned long fsb_freq;
2760         unsigned long mem_freq;
2761         unsigned long display_sr;
2762         unsigned long display_hpll_disable;
2763         unsigned long cursor_sr;
2764         unsigned long cursor_hpll_disable;
2765 };
2766
2767 static struct cxsr_latency cxsr_latency_table[] = {
2768         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2769         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2770         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2771         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2772         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2773
2774         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2775         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2776         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2777         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2778         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2779
2780         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2781         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2782         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2783         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2784         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2785
2786         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2787         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2788         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2789         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2790         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2791
2792         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2793         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2794         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2795         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2796         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2797
2798         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2799         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2800         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2801         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2802         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2803 };
2804
2805 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3, 
2806                                                    int fsb, int mem)
2807 {
2808         int i;
2809         struct cxsr_latency *latency;
2810
2811         if (fsb == 0 || mem == 0)
2812                 return NULL;
2813
2814         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2815                 latency = &cxsr_latency_table[i];
2816                 if (is_desktop == latency->is_desktop &&
2817                     is_ddr3 == latency->is_ddr3 &&
2818                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2819                         return latency;
2820         }
2821
2822         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2823
2824         return NULL;
2825 }
2826
2827 static void pineview_disable_cxsr(struct drm_device *dev)
2828 {
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         u32 reg;
2831
2832         /* deactivate cxsr */
2833         reg = I915_READ(DSPFW3);
2834         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2835         I915_WRITE(DSPFW3, reg);
2836         DRM_INFO("Big FIFO is disabled\n");
2837 }
2838
2839 /*
2840  * Latency for FIFO fetches is dependent on several factors:
2841  *   - memory configuration (speed, channels)
2842  *   - chipset
2843  *   - current MCH state
2844  * It can be fairly high in some situations, so here we assume a fairly
2845  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2846  * set this value too high, the FIFO will fetch frequently to stay full)
2847  * and power consumption (set it too low to save power and we might see
2848  * FIFO underruns and display "flicker").
2849  *
2850  * A value of 5us seems to be a good balance; safe for very low end
2851  * platforms but not overly aggressive on lower latency configs.
2852  */
2853 static const int latency_ns = 5000;
2854
2855 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2856 {
2857         struct drm_i915_private *dev_priv = dev->dev_private;
2858         uint32_t dsparb = I915_READ(DSPARB);
2859         int size;
2860
2861         if (plane == 0)
2862                 size = dsparb & 0x7f;
2863         else
2864                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2865                         (dsparb & 0x7f);
2866
2867         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2868                         plane ? "B" : "A", size);
2869
2870         return size;
2871 }
2872
2873 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2874 {
2875         struct drm_i915_private *dev_priv = dev->dev_private;
2876         uint32_t dsparb = I915_READ(DSPARB);
2877         int size;
2878
2879         if (plane == 0)
2880                 size = dsparb & 0x1ff;
2881         else
2882                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2883                         (dsparb & 0x1ff);
2884         size >>= 1; /* Convert to cachelines */
2885
2886         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2887                         plane ? "B" : "A", size);
2888
2889         return size;
2890 }
2891
2892 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2893 {
2894         struct drm_i915_private *dev_priv = dev->dev_private;
2895         uint32_t dsparb = I915_READ(DSPARB);
2896         int size;
2897
2898         size = dsparb & 0x7f;
2899         size >>= 2; /* Convert to cachelines */
2900
2901         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2902                         plane ? "B" : "A",
2903                   size);
2904
2905         return size;
2906 }
2907
2908 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2909 {
2910         struct drm_i915_private *dev_priv = dev->dev_private;
2911         uint32_t dsparb = I915_READ(DSPARB);
2912         int size;
2913
2914         size = dsparb & 0x7f;
2915         size >>= 1; /* Convert to cachelines */
2916
2917         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2918                         plane ? "B" : "A", size);
2919
2920         return size;
2921 }
2922
2923 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2924                           int planeb_clock, int sr_hdisplay, int pixel_size)
2925 {
2926         struct drm_i915_private *dev_priv = dev->dev_private;
2927         u32 reg;
2928         unsigned long wm;
2929         struct cxsr_latency *latency;
2930         int sr_clock;
2931
2932         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 
2933                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2934         if (!latency) {
2935                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2936                 pineview_disable_cxsr(dev);
2937                 return;
2938         }
2939
2940         if (!planea_clock || !planeb_clock) {
2941                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2942
2943                 /* Display SR */
2944                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2945                                         pixel_size, latency->display_sr);
2946                 reg = I915_READ(DSPFW1);
2947                 reg &= ~DSPFW_SR_MASK;
2948                 reg |= wm << DSPFW_SR_SHIFT;
2949                 I915_WRITE(DSPFW1, reg);
2950                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2951
2952                 /* cursor SR */
2953                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2954                                         pixel_size, latency->cursor_sr);
2955                 reg = I915_READ(DSPFW3);
2956                 reg &= ~DSPFW_CURSOR_SR_MASK;
2957                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2958                 I915_WRITE(DSPFW3, reg);
2959
2960                 /* Display HPLL off SR */
2961                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2962                                         pixel_size, latency->display_hpll_disable);
2963                 reg = I915_READ(DSPFW3);
2964                 reg &= ~DSPFW_HPLL_SR_MASK;
2965                 reg |= wm & DSPFW_HPLL_SR_MASK;
2966                 I915_WRITE(DSPFW3, reg);
2967
2968                 /* cursor HPLL off SR */
2969                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2970                                         pixel_size, latency->cursor_hpll_disable);
2971                 reg = I915_READ(DSPFW3);
2972                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2973                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2974                 I915_WRITE(DSPFW3, reg);
2975                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2976
2977                 /* activate cxsr */
2978                 reg = I915_READ(DSPFW3);
2979                 reg |= PINEVIEW_SELF_REFRESH_EN;
2980                 I915_WRITE(DSPFW3, reg);
2981                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2982         } else {
2983                 pineview_disable_cxsr(dev);
2984                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2985         }
2986 }
2987
2988 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2989                           int planeb_clock, int sr_hdisplay, int pixel_size)
2990 {
2991         struct drm_i915_private *dev_priv = dev->dev_private;
2992         int total_size, cacheline_size;
2993         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2994         struct intel_watermark_params planea_params, planeb_params;
2995         unsigned long line_time_us;
2996         int sr_clock, sr_entries = 0, entries_required;
2997
2998         /* Create copies of the base settings for each pipe */
2999         planea_params = planeb_params = g4x_wm_info;
3000
3001         /* Grab a couple of global values before we overwrite them */
3002         total_size = planea_params.fifo_size;
3003         cacheline_size = planea_params.cacheline_size;
3004