drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include "drmP.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "drm_dp_helper.h"
  37
  38 #include "drm_crtc_helper.h"
  39
  40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  41
  42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  43 static void intel_update_watermarks(struct drm_device *dev);
  44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  45
  46 typedef struct {
  47     /* given values */
  48     int n;
  49     int m1, m2;
  50     int p1, p2;
  51     /* derived values */
  52     int dot;
  53     int vco;
  54     int m;
  55     int p;
  56 } intel_clock_t;
  57
  58 typedef struct {
  59     int min, max;
  60 } intel_range_t;
  61
  62 typedef struct {
  63     int dot_limit;
  64     int p2_slow, p2_fast;
  65 } intel_p2_t;
  66
  67 #define INTEL_P2_NUM                  2
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71     intel_p2_t      p2;
  72     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  73                       int, int, intel_clock_t *);
  74 };
  75
  76 #define I8XX_DOT_MIN              25000
  77 #define I8XX_DOT_MAX             350000
  78 #define I8XX_VCO_MIN             930000
  79 #define I8XX_VCO_MAX            1400000
  80 #define I8XX_N_MIN                    3
  81 #define I8XX_N_MAX                   16
  82 #define I8XX_M_MIN                   96
  83 #define I8XX_M_MAX                  140
  84 #define I8XX_M1_MIN                  18
  85 #define I8XX_M1_MAX                  26
  86 #define I8XX_M2_MIN                   6
  87 #define I8XX_M2_MAX                  16
  88 #define I8XX_P_MIN                    4
  89 #define I8XX_P_MAX                  128
  90 #define I8XX_P1_MIN                   2
  91 #define I8XX_P1_MAX                  33
  92 #define I8XX_P1_LVDS_MIN              1
  93 #define I8XX_P1_LVDS_MAX              6
  94 #define I8XX_P2_SLOW                  4
  95 #define I8XX_P2_FAST                  2
  96 #define I8XX_P2_LVDS_SLOW             14
  97 #define I8XX_P2_LVDS_FAST             7
  98 #define I8XX_P2_SLOW_LIMIT       165000
  99
 100 #define I9XX_DOT_MIN              20000
 101 #define I9XX_DOT_MAX             400000
 102 #define I9XX_VCO_MIN            1400000
 103 #define I9XX_VCO_MAX            2800000
 104 #define PINEVIEW_VCO_MIN                1700000
 105 #define PINEVIEW_VCO_MAX                3500000
 106 #define I9XX_N_MIN                    1
 107 #define I9XX_N_MAX                    6
 108 /* Pineview's Ncounter is a ring counter */
 109 #define PINEVIEW_N_MIN                3
 110 #define PINEVIEW_N_MAX                6
 111 #define I9XX_M_MIN                   70
 112 #define I9XX_M_MAX                  120
 113 #define PINEVIEW_M_MIN                2
 114 #define PINEVIEW_M_MAX              256
 115 #define I9XX_M1_MIN                  10
 116 #define I9XX_M1_MAX                  22
 117 #define I9XX_M2_MIN                   5
 118 #define I9XX_M2_MAX                   9
 119 /* Pineview M1 is reserved, and must be 0 */
 120 #define PINEVIEW_M1_MIN               0
 121 #define PINEVIEW_M1_MAX               0
 122 #define PINEVIEW_M2_MIN               0
 123 #define PINEVIEW_M2_MAX               254
 124 #define I9XX_P_SDVO_DAC_MIN           5
 125 #define I9XX_P_SDVO_DAC_MAX          80
 126 #define I9XX_P_LVDS_MIN               7
 127 #define I9XX_P_LVDS_MAX              98
 128 #define PINEVIEW_P_LVDS_MIN                   7
 129 #define PINEVIEW_P_LVDS_MAX                  112
 130 #define I9XX_P1_MIN                   1
 131 #define I9XX_P1_MAX                   8
 132 #define I9XX_P2_SDVO_DAC_SLOW                10
 133 #define I9XX_P2_SDVO_DAC_FAST                 5
 134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 135 #define I9XX_P2_LVDS_SLOW                    14
 136 #define I9XX_P2_LVDS_FAST                     7
 137 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 138
 139 /*The parameter is for SDVO on G4x platform*/
 140 #define G4X_DOT_SDVO_MIN           25000
 141 #define G4X_DOT_SDVO_MAX           270000
 142 #define G4X_VCO_MIN                1750000
 143 #define G4X_VCO_MAX                3500000
 144 #define G4X_N_SDVO_MIN             1
 145 #define G4X_N_SDVO_MAX             4
 146 #define G4X_M_SDVO_MIN             104
 147 #define G4X_M_SDVO_MAX             138
 148 #define G4X_M1_SDVO_MIN            17
 149 #define G4X_M1_SDVO_MAX            23
 150 #define G4X_M2_SDVO_MIN            5
 151 #define G4X_M2_SDVO_MAX            11
 152 #define G4X_P_SDVO_MIN             10
 153 #define G4X_P_SDVO_MAX             30
 154 #define G4X_P1_SDVO_MIN            1
 155 #define G4X_P1_SDVO_MAX            3
 156 #define G4X_P2_SDVO_SLOW           10
 157 #define G4X_P2_SDVO_FAST           10
 158 #define G4X_P2_SDVO_LIMIT          270000
 159
 160 /*The parameter is for HDMI_DAC on G4x platform*/
 161 #define G4X_DOT_HDMI_DAC_MIN           22000
 162 #define G4X_DOT_HDMI_DAC_MAX           400000
 163 #define G4X_N_HDMI_DAC_MIN             1
 164 #define G4X_N_HDMI_DAC_MAX             4
 165 #define G4X_M_HDMI_DAC_MIN             104
 166 #define G4X_M_HDMI_DAC_MAX             138
 167 #define G4X_M1_HDMI_DAC_MIN            16
 168 #define G4X_M1_HDMI_DAC_MAX            23
 169 #define G4X_M2_HDMI_DAC_MIN            5
 170 #define G4X_M2_HDMI_DAC_MAX            11
 171 #define G4X_P_HDMI_DAC_MIN             5
 172 #define G4X_P_HDMI_DAC_MAX             80
 173 #define G4X_P1_HDMI_DAC_MIN            1
 174 #define G4X_P1_HDMI_DAC_MAX            8
 175 #define G4X_P2_HDMI_DAC_SLOW           10
 176 #define G4X_P2_HDMI_DAC_FAST           5
 177 #define G4X_P2_HDMI_DAC_LIMIT          165000
 178
 179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 197
 198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 216
 217 /*The parameter is for DISPLAY PORT on G4x platform*/
 218 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 219 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 220 #define G4X_N_DISPLAY_PORT_MIN             1
 221 #define G4X_N_DISPLAY_PORT_MAX             2
 222 #define G4X_M_DISPLAY_PORT_MIN             97
 223 #define G4X_M_DISPLAY_PORT_MAX             108
 224 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 225 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 226 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 227 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 228 #define G4X_P_DISPLAY_PORT_MIN             10
 229 #define G4X_P_DISPLAY_PORT_MAX             20
 230 #define G4X_P1_DISPLAY_PORT_MIN            1
 231 #define G4X_P1_DISPLAY_PORT_MAX            2
 232 #define G4X_P2_DISPLAY_PORT_SLOW           10
 233 #define G4X_P2_DISPLAY_PORT_FAST           10
 234 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 235
 236 /* Ironlake / Sandybridge */
 237 /* as we calculate clock using (register_value + 2) for
 238    N/M1/M2, so here the range value for them is (actual_value-2).
 239  */
 240 #define IRONLAKE_DOT_MIN         25000
 241 #define IRONLAKE_DOT_MAX         350000
 242 #define IRONLAKE_VCO_MIN         1760000
 243 #define IRONLAKE_VCO_MAX         3510000
 244 #define IRONLAKE_M1_MIN          12
 245 #define IRONLAKE_M1_MAX          22
 246 #define IRONLAKE_M2_MIN          5
 247 #define IRONLAKE_M2_MAX          9
 248 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 249
 250 /* We have parameter ranges for different type of outputs. */
 251
 252 /* DAC & HDMI Refclk 120Mhz */
 253 #define IRONLAKE_DAC_N_MIN      1
 254 #define IRONLAKE_DAC_N_MAX      5
 255 #define IRONLAKE_DAC_M_MIN      79
 256 #define IRONLAKE_DAC_M_MAX      127
 257 #define IRONLAKE_DAC_P_MIN      5
 258 #define IRONLAKE_DAC_P_MAX      80
 259 #define IRONLAKE_DAC_P1_MIN     1
 260 #define IRONLAKE_DAC_P1_MAX     8
 261 #define IRONLAKE_DAC_P2_SLOW    10
 262 #define IRONLAKE_DAC_P2_FAST    5
 263
 264 /* LVDS single-channel 120Mhz refclk */
 265 #define IRONLAKE_LVDS_S_N_MIN   1
 266 #define IRONLAKE_LVDS_S_N_MAX   3
 267 #define IRONLAKE_LVDS_S_M_MIN   79
 268 #define IRONLAKE_LVDS_S_M_MAX   118
 269 #define IRONLAKE_LVDS_S_P_MIN   28
 270 #define IRONLAKE_LVDS_S_P_MAX   112
 271 #define IRONLAKE_LVDS_S_P1_MIN  2
 272 #define IRONLAKE_LVDS_S_P1_MAX  8
 273 #define IRONLAKE_LVDS_S_P2_SLOW 14
 274 #define IRONLAKE_LVDS_S_P2_FAST 14
 275
 276 /* LVDS dual-channel 120Mhz refclk */
 277 #define IRONLAKE_LVDS_D_N_MIN   1
 278 #define IRONLAKE_LVDS_D_N_MAX   3
 279 #define IRONLAKE_LVDS_D_M_MIN   79
 280 #define IRONLAKE_LVDS_D_M_MAX   127
 281 #define IRONLAKE_LVDS_D_P_MIN   14
 282 #define IRONLAKE_LVDS_D_P_MAX   56
 283 #define IRONLAKE_LVDS_D_P1_MIN  2
 284 #define IRONLAKE_LVDS_D_P1_MAX  8
 285 #define IRONLAKE_LVDS_D_P2_SLOW 7
 286 #define IRONLAKE_LVDS_D_P2_FAST 7
 287
 288 /* LVDS single-channel 100Mhz refclk */
 289 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 290 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 291 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 292 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 293 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 294 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 295 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 296 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 298 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 299
 300 /* LVDS dual-channel 100Mhz refclk */
 301 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 302 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 303 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 304 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 305 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 306 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 307 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 308 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 310 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 311
 312 /* DisplayPort */
 313 #define IRONLAKE_DP_N_MIN               1
 314 #define IRONLAKE_DP_N_MAX               2
 315 #define IRONLAKE_DP_M_MIN               81
 316 #define IRONLAKE_DP_M_MAX               90
 317 #define IRONLAKE_DP_P_MIN               10
 318 #define IRONLAKE_DP_P_MAX               20
 319 #define IRONLAKE_DP_P2_FAST             10
 320 #define IRONLAKE_DP_P2_SLOW             10
 321 #define IRONLAKE_DP_P2_LIMIT            0
 322 #define IRONLAKE_DP_P1_MIN              1
 323 #define IRONLAKE_DP_P1_MAX              2
 324
 325 static bool
 326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 327                     int target, int refclk, intel_clock_t *best_clock);
 328 static bool
 329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 330                         int target, int refclk, intel_clock_t *best_clock);
 331
 332 static bool
 333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 334                       int target, int refclk, intel_clock_t *best_clock);
 335 static bool
 336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 337                            int target, int refclk, intel_clock_t *best_clock);
 338
 339 static const intel_limit_t intel_limits_i8xx_dvo = {
 340         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 341         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 342         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 343         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 344         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 345         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 346         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 347         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 348         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 349                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 350         .find_pll = intel_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_i8xx_lvds = {
 354         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 355         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 356         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 357         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 358         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 359         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 360         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 361         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 362         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 363                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 364         .find_pll = intel_find_best_PLL,
 365 };
 366
 367 static const intel_limit_t intel_limits_i9xx_sdvo = {
 368         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 369         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 370         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 371         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 372         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 373         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 374         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 375         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 376         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 377                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 378         .find_pll = intel_find_best_PLL,
 379 };
 380
 381 static const intel_limit_t intel_limits_i9xx_lvds = {
 382         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 383         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 384         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 385         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 386         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 387         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 388         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 389         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 390         /* The single-channel range is 25-112Mhz, and dual-channel
 391          * is 80-224Mhz.  Prefer single channel as much as possible.
 392          */
 393         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 394                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 395         .find_pll = intel_find_best_PLL,
 396 };
 397
 398     /* below parameter and function is for G4X Chipset Family*/
 399 static const intel_limit_t intel_limits_g4x_sdvo = {
 400         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 401         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 402         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 403         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 404         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 405         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 406         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 407         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 408         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 409                  .p2_slow = G4X_P2_SDVO_SLOW,
 410                  .p2_fast = G4X_P2_SDVO_FAST
 411         },
 412         .find_pll = intel_g4x_find_best_PLL,
 413 };
 414
 415 static const intel_limit_t intel_limits_g4x_hdmi = {
 416         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 419         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 420         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 421         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 422         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 423         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 424         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 425                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 426                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 432         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 433                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 434         .vco = { .min = G4X_VCO_MIN,
 435                  .max = G4X_VCO_MAX },
 436         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 437                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 438         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 439                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 440         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 441                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 442         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 443                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 444         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 445                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 446         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 447                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 448         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 449                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 450                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 451         },
 452         .find_pll = intel_g4x_find_best_PLL,
 453 };
 454
 455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 456         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 457                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 458         .vco = { .min = G4X_VCO_MIN,
 459                  .max = G4X_VCO_MAX },
 460         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 461                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 462         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 463                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 464         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 465                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 466         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 467                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 468         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 469                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 470         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 471                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 472         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 473                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 474                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 475         },
 476         .find_pll = intel_g4x_find_best_PLL,
 477 };
 478
 479 static const intel_limit_t intel_limits_g4x_display_port = {
 480         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 481                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 482         .vco = { .min = G4X_VCO_MIN,
 483                  .max = G4X_VCO_MAX},
 484         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 485                  .max = G4X_N_DISPLAY_PORT_MAX },
 486         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 487                  .max = G4X_M_DISPLAY_PORT_MAX },
 488         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 489                  .max = G4X_M1_DISPLAY_PORT_MAX },
 490         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 491                  .max = G4X_M2_DISPLAY_PORT_MAX },
 492         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 493                  .max = G4X_P_DISPLAY_PORT_MAX },
 494         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 495                  .max = G4X_P1_DISPLAY_PORT_MAX},
 496         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 497                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 498                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 499         .find_pll = intel_find_pll_g4x_dp,
 500 };
 501
 502 static const intel_limit_t intel_limits_pineview_sdvo = {
 503         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 504         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 505         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 506         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 507         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 508         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 509         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 510         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 511         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 512                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 513         .find_pll = intel_find_best_PLL,
 514 };
 515
 516 static const intel_limit_t intel_limits_pineview_lvds = {
 517         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 518         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 519         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 520         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 521         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 522         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 523         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 524         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 525         /* Pineview only supports single-channel mode. */
 526         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 527                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 528         .find_pll = intel_find_best_PLL,
 529 };
 530
 531 static const intel_limit_t intel_limits_ironlake_dac = {
 532         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 533         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 534         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 535         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 536         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 537         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 538         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 539         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 540         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 541                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 542                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 543         .find_pll = intel_g4x_find_best_PLL,
 544 };
 545
 546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 547         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 548         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 549         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 550         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 551         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 552         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 553         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 554         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 555         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 556                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 557                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 558         .find_pll = intel_g4x_find_best_PLL,
 559 };
 560
 561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 562         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 563         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 564         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 565         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 566         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 567         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 568         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 569         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 570         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 571                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 572                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 573         .find_pll = intel_g4x_find_best_PLL,
 574 };
 575
 576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 577         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 578         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 579         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 580         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 581         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 582         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 583         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 584         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 585         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 586                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 587                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 588         .find_pll = intel_g4x_find_best_PLL,
 589 };
 590
 591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 592         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 593         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 594         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 595         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 596         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 597         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 598         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 599         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 600         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 601                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 602                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 603         .find_pll = intel_g4x_find_best_PLL,
 604 };
 605
 606 static const intel_limit_t intel_limits_ironlake_display_port = {
 607         .dot = { .min = IRONLAKE_DOT_MIN,
 608                  .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,
 610                  .max = IRONLAKE_VCO_MAX},
 611         .n   = { .min = IRONLAKE_DP_N_MIN,
 612                  .max = IRONLAKE_DP_N_MAX },
 613         .m   = { .min = IRONLAKE_DP_M_MIN,
 614                  .max = IRONLAKE_DP_M_MAX },
 615         .m1  = { .min = IRONLAKE_M1_MIN,
 616                  .max = IRONLAKE_M1_MAX },
 617         .m2  = { .min = IRONLAKE_M2_MIN,
 618                  .max = IRONLAKE_M2_MAX },
 619         .p   = { .min = IRONLAKE_DP_P_MIN,
 620                  .max = IRONLAKE_DP_P_MAX },
 621         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 622                  .max = IRONLAKE_DP_P1_MAX},
 623         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 624                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 625                  .p2_fast = IRONLAKE_DP_P2_FAST },
 626         .find_pll = intel_find_pll_ironlake_dp,
 627 };
 628
 629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 630 {
 631         struct drm_device *dev = crtc->dev;
 632         struct drm_i915_private *dev_priv = dev->dev_private;
 633         const intel_limit_t *limit;
 634         int refclk = 120;
 635
 636         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 637                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 638                         refclk = 100;
 639
 640                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 641                     LVDS_CLKB_POWER_UP) {
 642                         /* LVDS dual channel */
 643                         if (refclk == 100)
 644                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 645                         else
 646                                 limit = &intel_limits_ironlake_dual_lvds;
 647                 } else {
 648                         if (refclk == 100)
 649                                 limit = &intel_limits_ironlake_single_lvds_100m;
 650                         else
 651                                 limit = &intel_limits_ironlake_single_lvds;
 652                 }
 653         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 654                         HAS_eDP)
 655                 limit = &intel_limits_ironlake_display_port;
 656         else
 657                 limit = &intel_limits_ironlake_dac;
 658
 659         return limit;
 660 }
 661
 662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 663 {
 664         struct drm_device *dev = crtc->dev;
 665         struct drm_i915_private *dev_priv = dev->dev_private;
 666         const intel_limit_t *limit;
 667
 668         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 670                     LVDS_CLKB_POWER_UP)
 671                         /* LVDS with dual channel */
 672                         limit = &intel_limits_g4x_dual_channel_lvds;
 673                 else
 674                         /* LVDS with dual channel */
 675                         limit = &intel_limits_g4x_single_channel_lvds;
 676         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 677                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 678                 limit = &intel_limits_g4x_hdmi;
 679         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 680                 limit = &intel_limits_g4x_sdvo;
 681         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 682                 limit = &intel_limits_g4x_display_port;
 683         } else /* The option is for other outputs */
 684                 limit = &intel_limits_i9xx_sdvo;
 685
 686         return limit;
 687 }
 688
 689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 690 {
 691         struct drm_device *dev = crtc->dev;
 692         const intel_limit_t *limit;
 693
 694         if (HAS_PCH_SPLIT(dev))
 695                 limit = intel_ironlake_limit(crtc);
 696         else if (IS_G4X(dev)) {
 697                 limit = intel_g4x_limit(crtc);
 698         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 699                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 700                         limit = &intel_limits_i9xx_lvds;
 701                 else
 702                         limit = &intel_limits_i9xx_sdvo;
 703         } else if (IS_PINEVIEW(dev)) {
 704                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 705                         limit = &intel_limits_pineview_lvds;
 706                 else
 707                         limit = &intel_limits_pineview_sdvo;
 708         } else {
 709                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 710                         limit = &intel_limits_i8xx_lvds;
 711                 else
 712                         limit = &intel_limits_i8xx_dvo;
 713         }
 714         return limit;
 715 }
 716
 717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 718 static void pineview_clock(int refclk, intel_clock_t *clock)
 719 {
 720         clock->m = clock->m2 + 2;
 721         clock->p = clock->p1 * clock->p2;
 722         clock->vco = refclk * clock->m / clock->n;
 723         clock->dot = clock->vco / clock->p;
 724 }
 725
 726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 727 {
 728         if (IS_PINEVIEW(dev)) {
 729                 pineview_clock(refclk, clock);
 730                 return;
 731         }
 732         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 733         clock->p = clock->p1 * clock->p2;
 734         clock->vco = refclk * clock->m / (clock->n + 2);
 735         clock->dot = clock->vco / clock->p;
 736 }
 737
 738 /**
 739  * Returns whether any output on the specified pipe is of the specified type
 740  */
 741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 742 {
 743     struct drm_device *dev = crtc->dev;
 744     struct drm_mode_config *mode_config = &dev->mode_config;
 745     struct drm_encoder *l_entry;
 746
 747     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 748             if (l_entry && l_entry->crtc == crtc) {
 749                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 750                     if (intel_encoder->type == type)
 751                             return true;
 752             }
 753     }
 754     return false;
 755 }
 756
 757 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 758 /**
 759  * Returns whether the given set of divisors are valid for a given refclk with
 760  * the given connectors.
 761  */
 762
 763 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 764 {
 765         const intel_limit_t *limit = intel_limit (crtc);
 766         struct drm_device *dev = crtc->dev;
 767
 768         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 769                 INTELPllInvalid ("p1 out of range\n");
 770         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 771                 INTELPllInvalid ("p out of range\n");
 772         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 773                 INTELPllInvalid ("m2 out of range\n");
 774         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 775                 INTELPllInvalid ("m1 out of range\n");
 776         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 777                 INTELPllInvalid ("m1 <= m2\n");
 778         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 779                 INTELPllInvalid ("m out of range\n");
 780         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 781                 INTELPllInvalid ("n out of range\n");
 782         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 783                 INTELPllInvalid ("vco out of range\n");
 784         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 785          * connector, etc., rather than just a single range.
 786          */
 787         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 788                 INTELPllInvalid ("dot out of range\n");
 789
 790         return true;
 791 }
 792
 793 static bool
 794 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 795                     int target, int refclk, intel_clock_t *best_clock)
 796
 797 {
 798         struct drm_device *dev = crtc->dev;
 799         struct drm_i915_private *dev_priv = dev->dev_private;
 800         intel_clock_t clock;
 801         int err = target;
 802
 803         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 804             (I915_READ(LVDS)) != 0) {
 805                 /*
 806                  * For LVDS, if the panel is on, just rely on its current
 807                  * settings for dual-channel.  We haven't figured out how to
 808                  * reliably set up different single/dual channel state, if we
 809                  * even can.
 810                  */
 811                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 812                     LVDS_CLKB_POWER_UP)
 813                         clock.p2 = limit->p2.p2_fast;
 814                 else
 815                         clock.p2 = limit->p2.p2_slow;
 816         } else {
 817                 if (target < limit->p2.dot_limit)
 818                         clock.p2 = limit->p2.p2_slow;
 819                 else
 820                         clock.p2 = limit->p2.p2_fast;
 821         }
 822
 823         memset (best_clock, 0, sizeof (*best_clock));
 824
 825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 826              clock.m1++) {
 827                 for (clock.m2 = limit->m2.min;
 828                      clock.m2 <= limit->m2.max; clock.m2++) {
 829                         /* m1 is always 0 in Pineview */
 830                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 831                                 break;
 832                         for (clock.n = limit->n.min;
 833                              clock.n <= limit->n.max; clock.n++) {
 834                                 for (clock.p1 = limit->p1.min;
 835                                         clock.p1 <= limit->p1.max; clock.p1++) {
 836                                         int this_err;
 837
 838                                         intel_clock(dev, refclk, &clock);
 839
 840                                         if (!intel_PLL_is_valid(crtc, &clock))
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err) {
 845                                                 *best_clock = clock;
 846                                                 err = this_err;
 847                                         }
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         return (err != target);
 854 }
 855
 856 static bool
 857 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 858                         int target, int refclk, intel_clock_t *best_clock)
 859 {
 860         struct drm_device *dev = crtc->dev;
 861         struct drm_i915_private *dev_priv = dev->dev_private;
 862         intel_clock_t clock;
 863         int max_n;
 864         bool found;
 865         /* approximately equals target * 0.00488 */
 866         int err_most = (target >> 8) + (target >> 10);
 867         found = false;
 868
 869         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 870                 int lvds_reg;
 871
 872                 if (HAS_PCH_SPLIT(dev))
 873                         lvds_reg = PCH_LVDS;
 874                 else
 875                         lvds_reg = LVDS;
 876                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 877                     LVDS_CLKB_POWER_UP)
 878                         clock.p2 = limit->p2.p2_fast;
 879                 else
 880                         clock.p2 = limit->p2.p2_slow;
 881         } else {
 882                 if (target < limit->p2.dot_limit)
 883                         clock.p2 = limit->p2.p2_slow;
 884                 else
 885                         clock.p2 = limit->p2.p2_fast;
 886         }
 887
 888         memset(best_clock, 0, sizeof(*best_clock));
 889         max_n = limit->n.max;
 890         /* based on hardware requirement, prefer smaller n to precision */
 891         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 892                 /* based on hardware requirement, prefere larger m1,m2 */
 893                 for (clock.m1 = limit->m1.max;
 894                      clock.m1 >= limit->m1.min; clock.m1--) {
 895                         for (clock.m2 = limit->m2.max;
 896                              clock.m2 >= limit->m2.min; clock.m2--) {
 897                                 for (clock.p1 = limit->p1.max;
 898                                      clock.p1 >= limit->p1.min; clock.p1--) {
 899                                         int this_err;
 900
 901                                         intel_clock(dev, refclk, &clock);
 902                                         if (!intel_PLL_is_valid(crtc, &clock))
 903                                                 continue;
 904                                         this_err = abs(clock.dot - target) ;
 905                                         if (this_err < err_most) {
 906                                                 *best_clock = clock;
 907                                                 err_most = this_err;
 908                                                 max_n = clock.n;
 909                                                 found = true;
 910                                         }
 911                                 }
 912                         }
 913                 }
 914         }
 915         return found;
 916 }
 917
 918 static bool
 919 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 920                            int target, int refclk, intel_clock_t *best_clock)
 921 {
 922         struct drm_device *dev = crtc->dev;
 923         intel_clock_t clock;
 924
 925         /* return directly when it is eDP */
 926         if (HAS_eDP)
 927                 return true;
 928
 929         if (target < 200000) {
 930                 clock.n = 1;
 931                 clock.p1 = 2;
 932                 clock.p2 = 10;
 933                 clock.m1 = 12;
 934                 clock.m2 = 9;
 935         } else {
 936                 clock.n = 2;
 937                 clock.p1 = 1;
 938                 clock.p2 = 10;
 939                 clock.m1 = 14;
 940                 clock.m2 = 8;
 941         }
 942         intel_clock(dev, refclk, &clock);
 943         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 944         return true;
 945 }
 946
 947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 948 static bool
 949 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 950                       int target, int refclk, intel_clock_t *best_clock)
 951 {
 952     intel_clock_t clock;
 953     if (target < 200000) {
 954         clock.p1 = 2;
 955         clock.p2 = 10;
 956         clock.n = 2;
 957         clock.m1 = 23;
 958         clock.m2 = 8;
 959     } else {
 960         clock.p1 = 1;
 961         clock.p2 = 10;
 962         clock.n = 1;
 963         clock.m1 = 14;
 964         clock.m2 = 2;
 965     }
 966     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 967     clock.p = (clock.p1 * clock.p2);
 968     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 969     clock.vco = 0;
 970     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 971     return true;
 972 }
 973
 974 void
 975 intel_wait_for_vblank(struct drm_device *dev)
 976 {
 977         /* Wait for 20ms, i.e. one cycle at 50hz. */
 978         msleep(20);
 979 }
 980
 981 /* Parameters have changed, update FBC info */
 982 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 983 {
 984         struct drm_device *dev = crtc->dev;
 985         struct drm_i915_private *dev_priv = dev->dev_private;
 986         struct drm_framebuffer *fb = crtc->fb;
 987         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 988         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
 989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 990         int plane, i;
 991         u32 fbc_ctl, fbc_ctl2;
 992
 993         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 994
 995         if (fb->pitch < dev_priv->cfb_pitch)
 996                 dev_priv->cfb_pitch = fb->pitch;
 997
 998         /* FBC_CTL wants 64B units */
 999         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1000         dev_priv->cfb_fence = obj_priv->fence_reg;
1001         dev_priv->cfb_plane = intel_crtc->plane;
1002         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1003
1004         /* Clear old tags */
1005         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1006                 I915_WRITE(FBC_TAG + (i * 4), 0);
1007
1008         /* Set it up... */
1009         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1010         if (obj_priv->tiling_mode != I915_TILING_NONE)
1011                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1012         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1013         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1014
1015         /* enable it... */
1016         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1017         if (IS_I945GM(dev))
1018                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1019         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1020         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1021         if (obj_priv->tiling_mode != I915_TILING_NONE)
1022                 fbc_ctl |= dev_priv->cfb_fence;
1023         I915_WRITE(FBC_CONTROL, fbc_ctl);
1024
1025         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1026                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1027 }
1028
1029 void i8xx_disable_fbc(struct drm_device *dev)
1030 {
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1033         u32 fbc_ctl;
1034
1035         if (!I915_HAS_FBC(dev))
1036                 return;
1037
1038         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1039                 return; /* Already off, just return */
1040
1041         /* Disable compression */
1042         fbc_ctl = I915_READ(FBC_CONTROL);
1043         fbc_ctl &= ~FBC_CTL_EN;
1044         I915_WRITE(FBC_CONTROL, fbc_ctl);
1045
1046         /* Wait for compressing bit to clear */
1047         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1048                 if (time_after(jiffies, timeout)) {
1049                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1050                         break;
1051                 }
1052                 ; /* do nothing */
1053         }
1054
1055         intel_wait_for_vblank(dev);
1056
1057         DRM_DEBUG_KMS("disabled FBC\n");
1058 }
1059
1060 static bool i8xx_fbc_enabled(struct drm_device *dev)
1061 {
1062         struct drm_i915_private *dev_priv = dev->dev_private;
1063
1064         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1065 }
1066
1067 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1068 {
1069         struct drm_device *dev = crtc->dev;
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         struct drm_framebuffer *fb = crtc->fb;
1072         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1073         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1075         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1076                      DPFC_CTL_PLANEB);
1077         unsigned long stall_watermark = 200;
1078         u32 dpfc_ctl;
1079
1080         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1081         dev_priv->cfb_fence = obj_priv->fence_reg;
1082         dev_priv->cfb_plane = intel_crtc->plane;
1083
1084         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1085         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1086                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1087                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1088         } else {
1089                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1090         }
1091
1092         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1093         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1094                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1095                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1096         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1097
1098         /* enable it... */
1099         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1100
1101         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1102 }
1103
1104 void g4x_disable_fbc(struct drm_device *dev)
1105 {
1106         struct drm_i915_private *dev_priv = dev->dev_private;
1107         u32 dpfc_ctl;
1108
1109         /* Disable compression */
1110         dpfc_ctl = I915_READ(DPFC_CONTROL);
1111         dpfc_ctl &= ~DPFC_CTL_EN;
1112         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1113         intel_wait_for_vblank(dev);
1114
1115         DRM_DEBUG_KMS("disabled FBC\n");
1116 }
1117
1118 static bool g4x_fbc_enabled(struct drm_device *dev)
1119 {
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121
1122         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1123 }
1124
1125 bool intel_fbc_enabled(struct drm_device *dev)
1126 {
1127         struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129         if (!dev_priv->display.fbc_enabled)
1130                 return false;
1131
1132         return dev_priv->display.fbc_enabled(dev);
1133 }
1134
1135 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1136 {
1137         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1138
1139         if (!dev_priv->display.enable_fbc)
1140                 return;
1141
1142         dev_priv->display.enable_fbc(crtc, interval);
1143 }
1144
1145 void intel_disable_fbc(struct drm_device *dev)
1146 {
1147         struct drm_i915_private *dev_priv = dev->dev_private;
1148
1149         if (!dev_priv->display.disable_fbc)
1150                 return;
1151
1152         dev_priv->display.disable_fbc(dev);
1153 }
1154
1155 /**
1156  * intel_update_fbc - enable/disable FBC as needed
1157  * @crtc: CRTC to point the compressor at
1158  * @mode: mode in use
1159  *
1160  * Set up the framebuffer compression hardware at mode set time.  We
1161  * enable it if possible:
1162  *   - plane A only (on pre-965)
1163  *   - no pixel mulitply/line duplication
1164  *   - no alpha buffer discard
1165  *   - no dual wide
1166  *   - framebuffer <= 2048 in width, 1536 in height
1167  *
1168  * We can't assume that any compression will take place (worst case),
1169  * so the compressed buffer has to be the same size as the uncompressed
1170  * one.  It also must reside (along with the line length buffer) in
1171  * stolen memory.
1172  *
1173  * We need to enable/disable FBC on a global basis.
1174  */
1175 static void intel_update_fbc(struct drm_crtc *crtc,
1176                              struct drm_display_mode *mode)
1177 {
1178         struct drm_device *dev = crtc->dev;
1179         struct drm_i915_private *dev_priv = dev->dev_private;
1180         struct drm_framebuffer *fb = crtc->fb;
1181         struct intel_framebuffer *intel_fb;
1182         struct drm_i915_gem_object *obj_priv;
1183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1184         int plane = intel_crtc->plane;
1185
1186         if (!i915_powersave)
1187                 return;
1188
1189         if (!I915_HAS_FBC(dev))
1190                 return;
1191
1192         if (!crtc->fb)
1193                 return;
1194
1195         intel_fb = to_intel_framebuffer(fb);
1196         obj_priv = to_intel_bo(intel_fb->obj);
1197
1198         /*
1199          * If FBC is already on, we just have to verify that we can
1200          * keep it that way...
1201          * Need to disable if:
1202          *   - changing FBC params (stride, fence, mode)
1203          *   - new fb is too large to fit in compressed buffer
1204          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1205          */
1206         if (intel_fb->obj->size > dev_priv->cfb_size) {
1207                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1208                                 "compression\n");
1209                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1210                 goto out_disable;
1211         }
1212         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1213             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1214                 DRM_DEBUG_KMS("mode incompatible with compression, "
1215                                 "disabling\n");
1216                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1217                 goto out_disable;
1218         }
1219         if ((mode->hdisplay > 2048) ||
1220             (mode->vdisplay > 1536)) {
1221                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1222                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1223                 goto out_disable;
1224         }
1225         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1226                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1227                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1228                 goto out_disable;
1229         }
1230         if (obj_priv->tiling_mode != I915_TILING_X) {
1231                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1232                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1233                 goto out_disable;
1234         }
1235
1236         if (intel_fbc_enabled(dev)) {
1237                 /* We can re-enable it in this case, but need to update pitch */
1238                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1239                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1240                     (plane != dev_priv->cfb_plane))
1241                         intel_disable_fbc(dev);
1242         }
1243
1244         /* Now try to turn it back on if possible */
1245         if (!intel_fbc_enabled(dev))
1246                 intel_enable_fbc(crtc, 500);
1247
1248         return;
1249
1250 out_disable:
1251         /* Multiple disables should be harmless */
1252         if (intel_fbc_enabled(dev)) {
1253                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1254                 intel_disable_fbc(dev);
1255         }
1256 }
1257
1258 static int
1259 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1260 {
1261         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1262         u32 alignment;
1263         int ret;
1264
1265         switch (obj_priv->tiling_mode) {
1266         case I915_TILING_NONE:
1267                 alignment = 64 * 1024;
1268                 break;
1269         case I915_TILING_X:
1270                 /* pin() will align the object as required by fence */
1271                 alignment = 0;
1272                 break;
1273         case I915_TILING_Y:
1274                 /* FIXME: Is this true? */
1275                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1276                 return -EINVAL;
1277         default:
1278                 BUG();
1279         }
1280
1281         ret = i915_gem_object_pin(obj, alignment);
1282         if (ret != 0)
1283                 return ret;
1284
1285         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1286          * fence, whereas 965+ only requires a fence if using
1287          * framebuffer compression.  For simplicity, we always install
1288          * a fence as the cost is not that onerous.
1289          */
1290         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1291             obj_priv->tiling_mode != I915_TILING_NONE) {
1292                 ret = i915_gem_object_get_fence_reg(obj);
1293                 if (ret != 0) {
1294                         i915_gem_object_unpin(obj);
1295                         return ret;
1296                 }
1297         }
1298
1299         return 0;
1300 }
1301
1302 static int
1303 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1304                     struct drm_framebuffer *old_fb)
1305 {
1306         struct drm_device *dev = crtc->dev;
1307         struct drm_i915_private *dev_priv = dev->dev_private;
1308         struct drm_i915_master_private *master_priv;
1309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1310         struct intel_framebuffer *intel_fb;
1311         struct drm_i915_gem_object *obj_priv;
1312         struct drm_gem_object *obj;
1313         int pipe = intel_crtc->pipe;
1314         int plane = intel_crtc->plane;
1315         unsigned long Start, Offset;
1316         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1317         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1318         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1319         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1320         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1321         u32 dspcntr;
1322         int ret;
1323
1324         /* no fb bound */
1325         if (!crtc->fb) {
1326                 DRM_DEBUG_KMS("No FB bound\n");
1327                 return 0;
1328         }
1329
1330         switch (plane) {
1331         case 0:
1332         case 1:
1333                 break;
1334         default:
1335                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1336                 return -EINVAL;
1337         }
1338
1339         intel_fb = to_intel_framebuffer(crtc->fb);
1340         obj = intel_fb->obj;
1341         obj_priv = to_intel_bo(obj);
1342
1343         mutex_lock(&dev->struct_mutex);
1344         ret = intel_pin_and_fence_fb_obj(dev, obj);
1345         if (ret != 0) {
1346                 mutex_unlock(&dev->struct_mutex);
1347                 return ret;
1348         }
1349
1350         ret = i915_gem_object_set_to_display_plane(obj);
1351         if (ret != 0) {
1352                 i915_gem_object_unpin(obj);
1353                 mutex_unlock(&dev->struct_mutex);
1354                 return ret;
1355         }
1356
1357         dspcntr = I915_READ(dspcntr_reg);
1358         /* Mask out pixel format bits in case we change it */
1359         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1360         switch (crtc->fb->bits_per_pixel) {
1361         case 8:
1362                 dspcntr |= DISPPLANE_8BPP;
1363                 break;
1364         case 16:
1365                 if (crtc->fb->depth == 15)
1366                         dspcntr |= DISPPLANE_15_16BPP;
1367                 else
1368                         dspcntr |= DISPPLANE_16BPP;
1369                 break;
1370         case 24:
1371         case 32:
1372                 if (crtc->fb->depth == 30)
1373                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1374                 else
1375                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1376                 break;
1377         default:
1378                 DRM_ERROR("Unknown color depth\n");
1379                 i915_gem_object_unpin(obj);
1380                 mutex_unlock(&dev->struct_mutex);
1381                 return -EINVAL;
1382         }
1383         if (IS_I965G(dev)) {
1384                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1385                         dspcntr |= DISPPLANE_TILED;
1386                 else
1387                         dspcntr &= ~DISPPLANE_TILED;
1388         }
1389
1390         if (HAS_PCH_SPLIT(dev))
1391                 /* must disable */
1392                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1393
1394         I915_WRITE(dspcntr_reg, dspcntr);
1395
1396         Start = obj_priv->gtt_offset;
1397         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1398
1399         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1400                       Start, Offset, x, y, crtc->fb->pitch);
1401         I915_WRITE(dspstride, crtc->fb->pitch);
1402         if (IS_I965G(dev)) {
1403                 I915_WRITE(dspbase, Offset);
1404                 I915_READ(dspbase);
1405                 I915_WRITE(dspsurf, Start);
1406                 I915_READ(dspsurf);
1407                 I915_WRITE(dsptileoff, (y << 16) | x);
1408         } else {
1409                 I915_WRITE(dspbase, Start + Offset);
1410                 I915_READ(dspbase);
1411         }
1412
1413         if ((IS_I965G(dev) || plane == 0))
1414                 intel_update_fbc(crtc, &crtc->mode);
1415
1416         intel_wait_for_vblank(dev);
1417
1418         if (old_fb) {
1419                 intel_fb = to_intel_framebuffer(old_fb);
1420                 obj_priv = to_intel_bo(intel_fb->obj);
1421                 i915_gem_object_unpin(intel_fb->obj);
1422         }
1423         intel_increase_pllclock(crtc, true);
1424
1425         mutex_unlock(&dev->struct_mutex);
1426
1427         if (!dev->primary->master)
1428                 return 0;
1429
1430         master_priv = dev->primary->master->driver_priv;
1431         if (!master_priv->sarea_priv)
1432                 return 0;
1433
1434         if (pipe) {
1435                 master_priv->sarea_priv->pipeB_x = x;
1436                 master_priv->sarea_priv->pipeB_y = y;
1437         } else {
1438                 master_priv->sarea_priv->pipeA_x = x;
1439                 master_priv->sarea_priv->pipeA_y = y;
1440         }
1441
1442         return 0;
1443 }
1444
1445 /* Disable the VGA plane that we never use */
1446 static void i915_disable_vga (struct drm_device *dev)
1447 {
1448         struct drm_i915_private *dev_priv = dev->dev_private;
1449         u8 sr1;
1450         u32 vga_reg;
1451
1452         if (HAS_PCH_SPLIT(dev))
1453                 vga_reg = CPU_VGACNTRL;
1454         else
1455                 vga_reg = VGACNTRL;
1456
1457         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1458                 return;
1459
1460         I915_WRITE8(VGA_SR_INDEX, 1);
1461         sr1 = I915_READ8(VGA_SR_DATA);
1462         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1463         udelay(100);
1464
1465         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1466 }
1467
1468 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1469 {
1470         struct drm_device *dev = crtc->dev;
1471         struct drm_i915_private *dev_priv = dev->dev_private;
1472         u32 dpa_ctl;
1473
1474         DRM_DEBUG_KMS("\n");
1475         dpa_ctl = I915_READ(DP_A);
1476         dpa_ctl &= ~DP_PLL_ENABLE;
1477         I915_WRITE(DP_A, dpa_ctl);
1478 }
1479
1480 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1481 {
1482         struct drm_device *dev = crtc->dev;
1483         struct drm_i915_private *dev_priv = dev->dev_private;
1484         u32 dpa_ctl;
1485
1486         dpa_ctl = I915_READ(DP_A);
1487         dpa_ctl |= DP_PLL_ENABLE;
1488         I915_WRITE(DP_A, dpa_ctl);
1489         udelay(200);
1490 }
1491
1492
1493 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1494 {
1495         struct drm_device *dev = crtc->dev;
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497         u32 dpa_ctl;
1498
1499         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1500         dpa_ctl = I915_READ(DP_A);
1501         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1502
1503         if (clock < 200000) {
1504                 u32 temp;
1505                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1506                 /* workaround for 160Mhz:
1507                    1) program 0x4600c bits 15:0 = 0x8124
1508                    2) program 0x46010 bit 0 = 1
1509                    3) program 0x46034 bit 24 = 1
1510                    4) program 0x64000 bit 14 = 1
1511                    */
1512                 temp = I915_READ(0x4600c);
1513                 temp &= 0xffff0000;
1514                 I915_WRITE(0x4600c, temp | 0x8124);
1515
1516                 temp = I915_READ(0x46010);
1517                 I915_WRITE(0x46010, temp | 1);
1518
1519                 temp = I915_READ(0x46034);
1520                 I915_WRITE(0x46034, temp | (1 << 24));
1521         } else {
1522                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1523         }
1524         I915_WRITE(DP_A, dpa_ctl);
1525
1526         udelay(500);
1527 }
1528
1529 /* The FDI link training functions for ILK/Ibexpeak. */
1530 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1531 {
1532         struct drm_device *dev = crtc->dev;
1533         struct drm_i915_private *dev_priv = dev->dev_private;
1534         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1535         int pipe = intel_crtc->pipe;
1536         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1537         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1538         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1539         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1540         u32 temp, tries = 0;
1541
1542         /* enable CPU FDI TX and PCH FDI RX */
1543         temp = I915_READ(fdi_tx_reg);
1544         temp |= FDI_TX_ENABLE;
1545         temp &= ~(7 << 19);
1546         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1547         temp &= ~FDI_LINK_TRAIN_NONE;
1548         temp |= FDI_LINK_TRAIN_PATTERN_1;
1549         I915_WRITE(fdi_tx_reg, temp);
1550         I915_READ(fdi_tx_reg);
1551
1552         temp = I915_READ(fdi_rx_reg);
1553         temp &= ~FDI_LINK_TRAIN_NONE;
1554         temp |= FDI_LINK_TRAIN_PATTERN_1;
1555         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1556         I915_READ(fdi_rx_reg);
1557         udelay(150);
1558
1559         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1560            for train result */
1561         temp = I915_READ(fdi_rx_imr_reg);
1562         temp &= ~FDI_RX_SYMBOL_LOCK;
1563         temp &= ~FDI_RX_BIT_LOCK;
1564         I915_WRITE(fdi_rx_imr_reg, temp);
1565         I915_READ(fdi_rx_imr_reg);
1566         udelay(150);
1567
1568         for (;;) {
1569                 temp = I915_READ(fdi_rx_iir_reg);
1570                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1571
1572                 if ((temp & FDI_RX_BIT_LOCK)) {
1573                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1574                         I915_WRITE(fdi_rx_iir_reg,
1575                                    temp | FDI_RX_BIT_LOCK);
1576                         break;
1577                 }
1578
1579                 tries++;
1580
1581                 if (tries > 5) {
1582                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1583                         break;
1584                 }
1585         }
1586
1587         /* Train 2 */
1588         temp = I915_READ(fdi_tx_reg);
1589         temp &= ~FDI_LINK_TRAIN_NONE;
1590         temp |= FDI_LINK_TRAIN_PATTERN_2;
1591         I915_WRITE(fdi_tx_reg, temp);
1592
1593         temp = I915_READ(fdi_rx_reg);
1594         temp &= ~FDI_LINK_TRAIN_NONE;
1595         temp |= FDI_LINK_TRAIN_PATTERN_2;
1596         I915_WRITE(fdi_rx_reg, temp);
1597         udelay(150);
1598
1599         tries = 0;
1600
1601         for (;;) {
1602                 temp = I915_READ(fdi_rx_iir_reg);
1603                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1604
1605                 if (temp & FDI_RX_SYMBOL_LOCK) {
1606                         I915_WRITE(fdi_rx_iir_reg,
1607                                    temp | FDI_RX_SYMBOL_LOCK);
1608                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1609                         break;
1610                 }
1611
1612                 tries++;
1613
1614                 if (tries > 5) {
1615                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1616                         break;
1617                 }
1618         }
1619
1620         DRM_DEBUG_KMS("FDI train done\n");
1621 }
1622
1623 static int snb_b_fdi_train_param [] = {
1624         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1625         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1626         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1627         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1628 };
1629
1630 /* The FDI link training functions for SNB/Cougarpoint. */
1631 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1632 {
1633         struct drm_device *dev = crtc->dev;
1634         struct drm_i915_private *dev_priv = dev->dev_private;
1635         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1636         int pipe = intel_crtc->pipe;
1637         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1638         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1639         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1640         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1641         u32 temp, i;
1642
1643         /* enable CPU FDI TX and PCH FDI RX */
1644         temp = I915_READ(fdi_tx_reg);
1645         temp |= FDI_TX_ENABLE;
1646         temp &= ~(7 << 19);
1647         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1648         temp &= ~FDI_LINK_TRAIN_NONE;
1649         temp |= FDI_LINK_TRAIN_PATTERN_1;
1650         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1651         /* SNB-B */
1652         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1653         I915_WRITE(fdi_tx_reg, temp);
1654         I915_READ(fdi_tx_reg);
1655
1656         temp = I915_READ(fdi_rx_reg);
1657         if (HAS_PCH_CPT(dev)) {
1658                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1659                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1660         } else {
1661                 temp &= ~FDI_LINK_TRAIN_NONE;
1662                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1663         }
1664         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1665         I915_READ(fdi_rx_reg);
1666         udelay(150);
1667
1668         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1669            for train result */
1670         temp = I915_READ(fdi_rx_imr_reg);
1671         temp &= ~FDI_RX_SYMBOL_LOCK;
1672         temp &= ~FDI_RX_BIT_LOCK;
1673         I915_WRITE(fdi_rx_imr_reg, temp);
1674         I915_READ(fdi_rx_imr_reg);
1675         udelay(150);
1676
1677         for (i = 0; i < 4; i++ ) {
1678                 temp = I915_READ(fdi_tx_reg);
1679                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1680                 temp |= snb_b_fdi_train_param[i];
1681                 I915_WRITE(fdi_tx_reg, temp);
1682                 udelay(500);
1683
1684                 temp = I915_READ(fdi_rx_iir_reg);
1685                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1686
1687                 if (temp & FDI_RX_BIT_LOCK) {
1688                         I915_WRITE(fdi_rx_iir_reg,
1689                                    temp | FDI_RX_BIT_LOCK);
1690                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1691                         break;
1692                 }
1693         }
1694         if (i == 4)
1695                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1696
1697         /* Train 2 */
1698         temp = I915_READ(fdi_tx_reg);
1699         temp &= ~FDI_LINK_TRAIN_NONE;
1700         temp |= FDI_LINK_TRAIN_PATTERN_2;
1701         if (IS_GEN6(dev)) {
1702                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1703                 /* SNB-B */
1704                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1705         }
1706         I915_WRITE(fdi_tx_reg, temp);
1707
1708         temp = I915_READ(fdi_rx_reg);
1709         if (HAS_PCH_CPT(dev)) {
1710                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1711                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1712         } else {
1713                 temp &= ~FDI_LINK_TRAIN_NONE;
1714                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1715         }
1716         I915_WRITE(fdi_rx_reg, temp);
1717         udelay(150);
1718
1719         for (i = 0; i < 4; i++ ) {
1720                 temp = I915_READ(fdi_tx_reg);
1721                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1722                 temp |= snb_b_fdi_train_param[i];
1723                 I915_WRITE(fdi_tx_reg, temp);
1724                 udelay(500);
1725
1726                 temp = I915_READ(fdi_rx_iir_reg);
1727                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1728
1729                 if (temp & FDI_RX_SYMBOL_LOCK) {
1730                         I915_WRITE(fdi_rx_iir_reg,
1731                                    temp | FDI_RX_SYMBOL_LOCK);
1732                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1733                         break;
1734                 }
1735         }
1736         if (i == 4)
1737                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1738
1739         DRM_DEBUG_KMS("FDI train done.\n");
1740 }
1741
1742 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1743 {
1744         struct drm_device *dev = crtc->dev;
1745         struct drm_i915_private *dev_priv = dev->dev_private;
1746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1747         int pipe = intel_crtc->pipe;
1748         int plane = intel_crtc->plane;
1749         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1750         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1751         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1752         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1753         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1754         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1755         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1756         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1757         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1758         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1759         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1760         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1761         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1762         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1763         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1764         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1765         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1766         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1767         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1768         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1769         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1770         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1771         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1772         u32 temp;
1773         int n;
1774         u32 pipe_bpc;
1775
1776         temp = I915_READ(pipeconf_reg);
1777         pipe_bpc = temp & PIPE_BPC_MASK;
1778
1779         /* XXX: When our outputs are all unaware of DPMS modes other than off
1780          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1781          */
1782         switch (mode) {
1783         case DRM_MODE_DPMS_ON:
1784         case DRM_MODE_DPMS_STANDBY:
1785         case DRM_MODE_DPMS_SUSPEND:
1786                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1787
1788                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1789                         temp = I915_READ(PCH_LVDS);
1790                         if ((temp & LVDS_PORT_EN) == 0) {
1791                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1792                                 POSTING_READ(PCH_LVDS);
1793                         }
1794                 }
1795
1796                 if (HAS_eDP) {
1797                         /* enable eDP PLL */
1798                         ironlake_enable_pll_edp(crtc);
1799                 } else {
1800
1801                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1802                         temp = I915_READ(fdi_rx_reg);
1803                         /*
1804                          * make the BPC in FDI Rx be consistent with that in
1805                          * pipeconf reg.
1806                          */
1807                         temp &= ~(0x7 << 16);
1808                         temp |= (pipe_bpc << 11);
1809                         temp &= ~(7 << 19);
1810                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1811                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1812                         I915_READ(fdi_rx_reg);
1813                         udelay(200);
1814
1815                         /* Switch from Rawclk to PCDclk */
1816                         temp = I915_READ(fdi_rx_reg);
1817                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1818                         I915_READ(fdi_rx_reg);
1819                         udelay(200);
1820
1821                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1822                         temp = I915_READ(fdi_tx_reg);
1823                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1824                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1825                                 I915_READ(fdi_tx_reg);
1826                                 udelay(100);
1827                         }
1828                 }
1829
1830                 /* Enable panel fitting for LVDS */
1831                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1832                         temp = I915_READ(pf_ctl_reg);
1833                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1834
1835                         /* currently full aspect */
1836                         I915_WRITE(pf_win_pos, 0);
1837
1838                         I915_WRITE(pf_win_size,
1839                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1840                                    (dev_priv->panel_fixed_mode->vdisplay));
1841                 }
1842
1843                 /* Enable CPU pipe */
1844                 temp = I915_READ(pipeconf_reg);
1845                 if ((temp & PIPEACONF_ENABLE) == 0) {
1846                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1847                         I915_READ(pipeconf_reg);
1848                         udelay(100);
1849                 }
1850
1851                 /* configure and enable CPU plane */
1852                 temp = I915_READ(dspcntr_reg);
1853                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1854                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1855                         /* Flush the plane changes */
1856                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1857                 }
1858
1859                 if (!HAS_eDP) {
1860                         /* For PCH output, training FDI link */
1861                         if (IS_GEN6(dev))
1862                                 gen6_fdi_link_train(crtc);
1863                         else
1864                                 ironlake_fdi_link_train(crtc);
1865
1866                         /* enable PCH DPLL */
1867                         temp = I915_READ(pch_dpll_reg);
1868                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1869                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1870                                 I915_READ(pch_dpll_reg);
1871                         }
1872                         udelay(200);
1873
1874                         if (HAS_PCH_CPT(dev)) {
1875                                 /* Be sure PCH DPLL SEL is set */
1876                                 temp = I915_READ(PCH_DPLL_SEL);
1877                                 if (trans_dpll_sel == 0 &&
1878                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1879                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1880                                 else if (trans_dpll_sel == 1 &&
1881                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1882                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1883                                 I915_WRITE(PCH_DPLL_SEL, temp);
1884                                 I915_READ(PCH_DPLL_SEL);
1885                         }
1886
1887                         /* set transcoder timing */
1888                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1889                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1890                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1891
1892                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1893                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1894                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1895
1896                         /* enable normal train */
1897                         temp = I915_READ(fdi_tx_reg);
1898                         temp &= ~FDI_LINK_TRAIN_NONE;
1899                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1900                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1901                         I915_READ(fdi_tx_reg);
1902
1903                         temp = I915_READ(fdi_rx_reg);
1904                         if (HAS_PCH_CPT(dev)) {
1905                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1906                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1907                         } else {
1908                                 temp &= ~FDI_LINK_TRAIN_NONE;
1909                                 temp |= FDI_LINK_TRAIN_NONE;
1910                         }
1911                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1912                         I915_READ(fdi_rx_reg);
1913
1914                         /* wait one idle pattern time */
1915                         udelay(100);
1916
1917                         /* For PCH DP, enable TRANS_DP_CTL */
1918                         if (HAS_PCH_CPT(dev) &&
1919                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1920                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1921                                 int reg;
1922
1923                                 reg = I915_READ(trans_dp_ctl);
1924                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
1925                                 reg = TRANS_DP_OUTPUT_ENABLE |
1926                                       TRANS_DP_ENH_FRAMING |
1927                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
1928                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
1929
1930                                 switch (intel_trans_dp_port_sel(crtc)) {
1931                                 case PCH_DP_B:
1932                                         reg |= TRANS_DP_PORT_SEL_B;
1933                                         break;
1934                                 case PCH_DP_C:
1935                                         reg |= TRANS_DP_PORT_SEL_C;
1936                                         break;
1937                                 case PCH_DP_D:
1938                                         reg |= TRANS_DP_PORT_SEL_D;
1939                                         break;
1940                                 default:
1941                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1942                                         reg |= TRANS_DP_PORT_SEL_B;
1943                                         break;
1944                                 }
1945
1946                                 I915_WRITE(trans_dp_ctl, reg);
1947                                 POSTING_READ(trans_dp_ctl);
1948                         }
1949
1950                         /* enable PCH transcoder */
1951                         temp = I915_READ(transconf_reg);
1952                         /*
1953                          * make the BPC in transcoder be consistent with
1954                          * that in pipeconf reg.
1955                          */
1956                         temp &= ~PIPE_BPC_MASK;
1957                         temp |= pipe_bpc;
1958                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1959                         I915_READ(transconf_reg);
1960
1961                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1962                                 ;
1963
1964                 }
1965
1966                 intel_crtc_load_lut(crtc);
1967
1968         break;
1969         case DRM_MODE_DPMS_OFF:
1970                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1971
1972                 drm_vblank_off(dev, pipe);
1973                 /* Disable display plane */
1974                 temp = I915_READ(dspcntr_reg);
1975                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1976                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1977                         /* Flush the plane changes */
1978                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1979                         I915_READ(dspbase_reg);
1980                 }
1981
1982                 i915_disable_vga(dev);
1983
1984                 /* disable cpu pipe, disable after all planes disabled */
1985                 temp = I915_READ(pipeconf_reg);
1986                 if ((temp & PIPEACONF_ENABLE) != 0) {
1987                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1988                         I915_READ(pipeconf_reg);
1989                         n = 0;
1990                         /* wait for cpu pipe off, pipe state */
1991                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1992                                 n++;
1993                                 if (n < 60) {
1994                                         udelay(500);
1995                                         continue;
1996                                 } else {
1997                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1998                                                                 pipe);
1999                                         break;
2000                                 }
2001                         }
2002                 } else
2003                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2004
2005                 udelay(100);
2006
2007                 /* Disable PF */
2008                 temp = I915_READ(pf_ctl_reg);
2009                 if ((temp & PF_ENABLE) != 0) {
2010                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2011                         I915_READ(pf_ctl_reg);
2012                 }
2013                 I915_WRITE(pf_win_size, 0);
2014                 POSTING_READ(pf_win_size);
2015
2016
2017                 /* disable CPU FDI tx and PCH FDI rx */
2018                 temp = I915_READ(fdi_tx_reg);
2019                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2020                 I915_READ(fdi_tx_reg);
2021
2022                 temp = I915_READ(fdi_rx_reg);
2023                 /* BPC in FDI rx is consistent with that in pipeconf */
2024                 temp &= ~(0x07 << 16);
2025                 temp |= (pipe_bpc << 11);
2026                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2027                 I915_READ(fdi_rx_reg);
2028
2029                 udelay(100);
2030
2031                 /* still set train pattern 1 */
2032                 temp = I915_READ(fdi_tx_reg);
2033                 temp &= ~FDI_LINK_TRAIN_NONE;
2034                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2035                 I915_WRITE(fdi_tx_reg, temp);
2036                 POSTING_READ(fdi_tx_reg);
2037
2038                 temp = I915_READ(fdi_rx_reg);
2039                 if (HAS_PCH_CPT(dev)) {
2040                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2041                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2042                 } else {
2043                         temp &= ~FDI_LINK_TRAIN_NONE;
2044                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2045                 }
2046                 I915_WRITE(fdi_rx_reg, temp);
2047                 POSTING_READ(fdi_rx_reg);
2048
2049                 udelay(100);
2050
2051                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2052                         temp = I915_READ(PCH_LVDS);
2053                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2054                         I915_READ(PCH_LVDS);
2055                         udelay(100);
2056                 }
2057
2058                 /* disable PCH transcoder */
2059                 temp = I915_READ(transconf_reg);
2060                 if ((temp & TRANS_ENABLE) != 0) {
2061                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2062                         I915_READ(transconf_reg);
2063                         n = 0;
2064                         /* wait for PCH transcoder off, transcoder state */
2065                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2066                                 n++;
2067                                 if (n < 60) {
2068                                         udelay(500);
2069                                         continue;
2070                                 } else {
2071                                         DRM_DEBUG_KMS("transcoder %d off "
2072                                                         "delay\n", pipe);
2073                                         break;
2074                                 }
2075                         }
2076                 }
2077
2078                 temp = I915_READ(transconf_reg);
2079                 /* BPC in transcoder is consistent with that in pipeconf */
2080                 temp &= ~PIPE_BPC_MASK;
2081                 temp |= pipe_bpc;
2082                 I915_WRITE(transconf_reg, temp);
2083                 I915_READ(transconf_reg);
2084                 udelay(100);
2085
2086                 if (HAS_PCH_CPT(dev)) {
2087                         /* disable TRANS_DP_CTL */
2088                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2089                         int reg;
2090
2091                         reg = I915_READ(trans_dp_ctl);
2092                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2093                         I915_WRITE(trans_dp_ctl, reg);
2094                         POSTING_READ(trans_dp_ctl);
2095
2096                         /* disable DPLL_SEL */
2097                         temp = I915_READ(PCH_DPLL_SEL);
2098                         if (trans_dpll_sel == 0)
2099                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2100                         else
2101                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2102                         I915_WRITE(PCH_DPLL_SEL, temp);
2103                         I915_READ(PCH_DPLL_SEL);
2104
2105                 }
2106
2107                 /* disable PCH DPLL */
2108                 temp = I915_READ(pch_dpll_reg);
2109                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2110                 I915_READ(pch_dpll_reg);
2111
2112                 if (HAS_eDP) {
2113                         ironlake_disable_pll_edp(crtc);
2114                 }
2115
2116                 /* Switch from PCDclk to Rawclk */
2117                 temp = I915_READ(fdi_rx_reg);
2118                 temp &= ~FDI_SEL_PCDCLK;
2119                 I915_WRITE(fdi_rx_reg, temp);
2120                 I915_READ(fdi_rx_reg);
2121
2122                 /* Disable CPU FDI TX PLL */
2123                 temp = I915_READ(fdi_tx_reg);
2124                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2125                 I915_READ(fdi_tx_reg);
2126                 udelay(100);
2127
2128                 temp = I915_READ(fdi_rx_reg);
2129                 temp &= ~FDI_RX_PLL_ENABLE;
2130                 I915_WRITE(fdi_rx_reg, temp);
2131                 I915_READ(fdi_rx_reg);
2132
2133                 /* Wait for the clocks to turn off. */
2134                 udelay(100);
2135                 break;
2136         }
2137 }
2138
2139 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2140 {
2141         struct intel_overlay *overlay;
2142         int ret;
2143
2144         if (!enable && intel_crtc->overlay) {
2145                 overlay = intel_crtc->overlay;
2146                 mutex_lock(&overlay->dev->struct_mutex);
2147                 for (;;) {
2148                         ret = intel_overlay_switch_off(overlay);
2149                         if (ret == 0)
2150                                 break;
2151
2152                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2153                         if (ret != 0) {
2154                                 /* overlay doesn't react anymore. Usually
2155                                  * results in a black screen and an unkillable
2156                                  * X server. */
2157                                 BUG();
2158                                 overlay->hw_wedged = HW_WEDGED;
2159                                 break;
2160                         }
2161                 }
2162                 mutex_unlock(&overlay->dev->struct_mutex);
2163         }
2164         /* Let userspace switch the overlay on again. In most cases userspace
2165          * has to recompute where to put it anyway. */
2166
2167         return;
2168 }
2169
2170 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2171 {
2172         struct drm_device *dev = crtc->dev;
2173         struct drm_i915_private *dev_priv = dev->dev_private;
2174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2175         int pipe = intel_crtc->pipe;
2176         int plane = intel_crtc->plane;
2177         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2178         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2179         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2180         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2181         u32 temp;
2182
2183         /* XXX: When our outputs are all unaware of DPMS modes other than off
2184          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2185          */
2186         switch (mode) {
2187         case DRM_MODE_DPMS_ON:
2188         case DRM_MODE_DPMS_STANDBY:
2189         case DRM_MODE_DPMS_SUSPEND:
2190                 intel_update_watermarks(dev);
2191
2192                 /* Enable the DPLL */
2193                 temp = I915_READ(dpll_reg);
2194                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2195                         I915_WRITE(dpll_reg, temp);
2196                         I915_READ(dpll_reg);
2197                         /* Wait for the clocks to stabilize. */
2198                         udelay(150);
2199                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2200                         I915_READ(dpll_reg);
2201                         /* Wait for the clocks to stabilize. */
2202                         udelay(150);
2203                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2204                         I915_READ(dpll_reg);
2205                         /* Wait for the clocks to stabilize. */
2206                         udelay(150);
2207                 }
2208
2209                 /* Enable the pipe */
2210                 temp = I915_READ(pipeconf_reg);
2211                 if ((temp & PIPEACONF_ENABLE) == 0)
2212                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2213
2214                 /* Enable the plane */
2215                 temp = I915_READ(dspcntr_reg);
2216                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2217                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2218                         /* Flush the plane changes */
2219                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2220                 }
2221
2222                 intel_crtc_load_lut(crtc);
2223
2224                 if ((IS_I965G(dev) || plane == 0))
2225                         intel_update_fbc(crtc, &crtc->mode);
2226
2227                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2228                 intel_crtc_dpms_overlay(intel_crtc, true);
2229         break;
2230         case DRM_MODE_DPMS_OFF:
2231                 intel_update_watermarks(dev);
2232
2233                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2234                 intel_crtc_dpms_overlay(intel_crtc, false);
2235                 drm_vblank_off(dev, pipe);
2236
2237                 if (dev_priv->cfb_plane == plane &&
2238                     dev_priv->display.disable_fbc)
2239                         dev_priv->display.disable_fbc(dev);
2240
2241                 /* Disable the VGA plane that we never use */
2242                 i915_disable_vga(dev);
2243
2244                 /* Disable display plane */
2245                 temp = I915_READ(dspcntr_reg);
2246                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2247                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2248                         /* Flush the plane changes */
2249                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2250                         I915_READ(dspbase_reg);
2251                 }
2252
2253                 if (!IS_I9XX(dev)) {
2254                         /* Wait for vblank for the disable to take effect */
2255                         intel_wait_for_vblank(dev);
2256                 }
2257
2258                 /* Next, disable display pipes */
2259                 temp = I915_READ(pipeconf_reg);
2260                 if ((temp & PIPEACONF_ENABLE) != 0) {
2261                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2262                         I915_READ(pipeconf_reg);
2263                 }
2264
2265                 /* Wait for vblank for the disable to take effect. */
2266                 intel_wait_for_vblank(dev);
2267
2268                 temp = I915_READ(dpll_reg);
2269                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2270                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2271                         I915_READ(dpll_reg);
2272                 }
2273
2274                 /* Wait for the clocks to turn off. */
2275                 udelay(150);
2276                 break;
2277         }
2278 }
2279
2280 /**
2281  * Sets the power management mode of the pipe and plane.
2282  *
2283  * This code should probably grow support for turning the cursor off and back
2284  * on appropriately at the same time as we're turning the pipe off/on.
2285  */
2286 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2287 {
2288         struct drm_device *dev = crtc->dev;
2289         struct drm_i915_private *dev_priv = dev->dev_private;
2290         struct drm_i915_master_private *master_priv;
2291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2292         int pipe = intel_crtc->pipe;
2293         bool enabled;
2294
2295         dev_priv->display.dpms(crtc, mode);
2296
2297         intel_crtc->dpms_mode = mode;
2298
2299         if (!dev->primary->master)
2300                 return;
2301
2302         master_priv = dev->primary->master->driver_priv;
2303         if (!master_priv->sarea_priv)
2304                 return;
2305
2306         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2307
2308         switch (pipe) {
2309         case 0:
2310                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2311                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2312                 break;
2313         case 1:
2314                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2315                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2316                 break;
2317         default:
2318                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2319                 break;
2320         }
2321 }
2322
2323 static void intel_crtc_prepare (struct drm_crtc *crtc)
2324 {
2325         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2326         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2327 }
2328
2329 static void intel_crtc_commit (struct drm_crtc *crtc)
2330 {
2331         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2332         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2333 }
2334
2335 void intel_encoder_prepare (struct drm_encoder *encoder)
2336 {
2337         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2338         /* lvds has its own version of prepare see intel_lvds_prepare */
2339         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2340 }
2341
2342 void intel_encoder_commit (struct drm_encoder *encoder)
2343 {
2344         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2345         /* lvds has its own version of commit see intel_lvds_commit */
2346         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2347 }
2348
2349 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2350                                   struct drm_display_mode *mode,
2351                                   struct drm_display_mode *adjusted_mode)
2352 {
2353         struct drm_device *dev = crtc->dev;
2354         if (HAS_PCH_SPLIT(dev)) {
2355                 /* FDI link clock is fixed at 2.7G */
2356                 if (mode->clock * 3 > 27000 * 4)
2357                         return MODE_CLOCK_HIGH;
2358         }
2359
2360         drm_mode_set_crtcinfo(adjusted_mode, 0);
2361         return true;
2362 }
2363
2364 static int i945_get_display_clock_speed(struct drm_device *dev)
2365 {
2366         return 400000;
2367 }
2368
2369 static int i915_get_display_clock_speed(struct drm_device *dev)
2370 {
2371         return 333000;
2372 }
2373
2374 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2375 {
2376         return 200000;
2377 }
2378
2379 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2380 {
2381         u16 gcfgc = 0;
2382
2383         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2384
2385         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2386                 return 133000;
2387         else {
2388                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2389                 case GC_DISPLAY_CLOCK_333_MHZ:
2390                         return 333000;
2391                 default:
2392                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2393                         return 190000;
2394                 }
2395         }
2396 }
2397
2398 static int i865_get_display_clock_speed(struct drm_device *dev)
2399 {
2400         return 266000;
2401 }
2402
2403 static int i855_get_display_clock_speed(struct drm_device *dev)
2404 {
2405         u16 hpllcc = 0;
2406         /* Assume that the hardware is in the high speed state.  This
2407          * should be the default.
2408          */
2409         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2410         case GC_CLOCK_133_200:
2411         case GC_CLOCK_100_200:
2412                 return 200000;
2413         case GC_CLOCK_166_250:
2414                 return 250000;
2415         case GC_CLOCK_100_133:
2416                 return 133000;
2417         }
2418
2419         /* Shouldn't happen */
2420         return 0;
2421 }
2422
2423 static int i830_get_display_clock_speed(struct drm_device *dev)
2424 {
2425         return 133000;
2426 }
2427
2428 /**
2429  * Return the pipe currently connected to the panel fitter,
2430  * or -1 if the panel fitter is not present or not in use
2431  */
2432 int intel_panel_fitter_pipe (struct drm_device *dev)
2433 {
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         u32  pfit_control;
2436
2437         /* i830 doesn't have a panel fitter */
2438         if (IS_I830(dev))
2439                 return -1;
2440
2441         pfit_control = I915_READ(PFIT_CONTROL);
2442
2443         /* See if the panel fitter is in use */
2444         if ((pfit_control & PFIT_ENABLE) == 0)
2445                 return -1;
2446
2447         /* 965 can place panel fitter on either pipe */
2448         if (IS_I965G(dev))
2449                 return (pfit_control >> 29) & 0x3;
2450
2451         /* older chips can only use pipe 1 */
2452         return 1;
2453 }
2454
2455 struct fdi_m_n {
2456         u32        tu;
2457         u32        gmch_m;
2458         u32        gmch_n;
2459         u32        link_m;
2460         u32        link_n;
2461 };
2462
2463 static void
2464 fdi_reduce_ratio(u32 *num, u32 *den)
2465 {
2466         while (*num > 0xffffff || *den > 0xffffff) {
2467                 *num >>= 1;
2468                 *den >>= 1;
2469         }
2470 }
2471
2472 #define DATA_N 0x800000
2473 #define LINK_N 0x80000
2474
2475 static void
2476 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2477                      int link_clock, struct fdi_m_n *m_n)
2478 {
2479         u64 temp;
2480
2481         m_n->tu = 64; /* default size */
2482
2483         temp = (u64) DATA_N * pixel_clock;
2484         temp = div_u64(temp, link_clock);
2485         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2486         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2487         m_n->gmch_n = DATA_N;
2488         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2489
2490         temp = (u64) LINK_N * pixel_clock;
2491         m_n->link_m = div_u64(temp, link_clock);
2492         m_n->link_n = LINK_N;
2493         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2494 }
2495
2496
2497 struct intel_watermark_params {
2498         unsigned long fifo_size;
2499         unsigned long max_wm;
2500         unsigned long default_wm;
2501         unsigned long guard_size;
2502         unsigned long cacheline_size;
2503 };
2504
2505 /* Pineview has different values for various configs */
2506 static struct intel_watermark_params pineview_display_wm = {
2507         PINEVIEW_DISPLAY_FIFO,
2508         PINEVIEW_MAX_WM,
2509         PINEVIEW_DFT_WM,
2510         PINEVIEW_GUARD_WM,
2511         PINEVIEW_FIFO_LINE_SIZE
2512 };
2513 static struct intel_watermark_params pineview_display_hplloff_wm = {
2514         PINEVIEW_DISPLAY_FIFO,
2515         PINEVIEW_MAX_WM,
2516         PINEVIEW_DFT_HPLLOFF_WM,
2517         PINEVIEW_GUARD_WM,
2518         PINEVIEW_FIFO_LINE_SIZE
2519 };
2520 static struct intel_watermark_params pineview_cursor_wm = {
2521         PINEVIEW_CURSOR_FIFO,
2522         PINEVIEW_CURSOR_MAX_WM,
2523         PINEVIEW_CURSOR_DFT_WM,
2524         PINEVIEW_CURSOR_GUARD_WM,
2525         PINEVIEW_FIFO_LINE_SIZE,
2526 };
2527 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2528         PINEVIEW_CURSOR_FIFO,
2529         PINEVIEW_CURSOR_MAX_WM,
2530         PINEVIEW_CURSOR_DFT_WM,
2531         PINEVIEW_CURSOR_GUARD_WM,
2532         PINEVIEW_FIFO_LINE_SIZE
2533 };
2534 static struct intel_watermark_params g4x_wm_info = {
2535         G4X_FIFO_SIZE,
2536         G4X_MAX_WM,
2537         G4X_MAX_WM,
2538         2,
2539         G4X_FIFO_LINE_SIZE,
2540 };
2541 static struct intel_watermark_params i945_wm_info = {
2542         I945_FIFO_SIZE,
2543         I915_MAX_WM,
2544         1,
2545         2,
2546         I915_FIFO_LINE_SIZE
2547 };
2548 static struct intel_watermark_params i915_wm_info = {
2549         I915_FIFO_SIZE,
2550         I915_MAX_WM,
2551         1,
2552         2,
2553         I915_FIFO_LINE_SIZE
2554 };
2555 static struct intel_watermark_params i855_wm_info = {
2556         I855GM_FIFO_SIZE,
2557         I915_MAX_WM,
2558         1,
2559         2,
2560         I830_FIFO_LINE_SIZE
2561 };
2562 static struct intel_watermark_params i830_wm_info = {
2563         I830_FIFO_SIZE,
2564         I915_MAX_WM,
2565         1,
2566         2,
2567         I830_FIFO_LINE_SIZE
2568 };
2569
2570 static struct intel_watermark_params ironlake_display_wm_info = {
2571         ILK_DISPLAY_FIFO,
2572         ILK_DISPLAY_MAXWM,
2573         ILK_DISPLAY_DFTWM,
2574         2,
2575         ILK_FIFO_LINE_SIZE
2576 };
2577
2578 static struct intel_watermark_params ironlake_display_srwm_info = {
2579         ILK_DISPLAY_SR_FIFO,
2580         ILK_DISPLAY_MAX_SRWM,
2581         ILK_DISPLAY_DFT_SRWM,
2582         2,
2583         ILK_FIFO_LINE_SIZE
2584 };
2585
2586 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2587         ILK_CURSOR_SR_FIFO,
2588         ILK_CURSOR_MAX_SRWM,
2589         ILK_CURSOR_DFT_SRWM,
2590         2,
2591         ILK_FIFO_LINE_SIZE
2592 };
2593
2594 /**
2595  * intel_calculate_wm - calculate watermark level
2596  * @clock_in_khz: pixel clock
2597  * @wm: chip FIFO params
2598  * @pixel_size: display pixel size
2599  * @latency_ns: memory latency for the platform
2600  *
2601  * Calculate the watermark level (the level at which the display plane will
2602  * start fetching from memory again).  Each chip has a different display
2603  * FIFO size and allocation, so the caller needs to figure that out and pass
2604  * in the correct intel_watermark_params structure.
2605  *
2606  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2607  * on the pixel size.  When it reaches the watermark level, it'll start
2608  * fetching FIFO line sized based chunks from memory until the FIFO fills
2609  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2610  * will occur, and a display engine hang could result.
2611  */
2612 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2613                                         struct intel_watermark_params *wm,
2614                                         int pixel_size,
2615                                         unsigned long latency_ns)
2616 {
2617         long entries_required, wm_size;
2618
2619         /*
2620          * Note: we need to make sure we don't overflow for various clock &
2621          * latency values.
2622          * clocks go from a few thousand to several hundred thousand.
2623          * latency is usually a few thousand
2624          */
2625         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2626                 1000;
2627         entries_required /= wm->cacheline_size;
2628
2629         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2630
2631         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2632
2633         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2634
2635         /* Don't promote wm_size to unsigned... */
2636         if (wm_size > (long)wm->max_wm)
2637                 wm_size = wm->max_wm;
2638         if (wm_size <= 0)
2639                 wm_size = wm->default_wm;
2640         return wm_size;
2641 }
2642
2643 struct cxsr_latency {
2644         int is_desktop;
2645         int is_ddr3;
2646         unsigned long fsb_freq;
2647         unsigned long mem_freq;
2648         unsigned long display_sr;
2649         unsigned long display_hpll_disable;
2650         unsigned long cursor_sr;
2651         unsigned long cursor_hpll_disable;
2652 };
2653
2654 static struct cxsr_latency cxsr_latency_table[] = {
2655         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2656         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2657         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2658         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2659         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2660
2661         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2662         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2663         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2664         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2665         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2666
2667         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2668         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2669         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2670         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2671         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2672
2673         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2674         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2675         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2676         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2677         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2678
2679         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2680         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2681         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2682         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2683         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2684
2685         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2686         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2687         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2688         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2689         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2690 };
2691
2692 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2693                                                    int fsb, int mem)
2694 {
2695         int i;
2696         struct cxsr_latency *latency;
2697
2698         if (fsb == 0 || mem == 0)
2699                 return NULL;
2700
2701         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2702                 latency = &cxsr_latency_table[i];
2703                 if (is_desktop == latency->is_desktop &&
2704                     is_ddr3 == latency->is_ddr3 &&
2705                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2706                         return latency;
2707         }
2708
2709         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2710
2711         return NULL;
2712 }
2713
2714 static void pineview_disable_cxsr(struct drm_device *dev)
2715 {
2716         struct drm_i915_private *dev_priv = dev->dev_private;
2717         u32 reg;
2718
2719         /* deactivate cxsr */
2720         reg = I915_READ(DSPFW3);
2721         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2722         I915_WRITE(DSPFW3, reg);
2723         DRM_INFO("Big FIFO is disabled\n");
2724 }
2725
2726 /*
2727  * Latency for FIFO fetches is dependent on several factors:
2728  *   - memory configuration (speed, channels)
2729  *   - chipset
2730  *   - current MCH state
2731  * It can be fairly high in some situations, so here we assume a fairly
2732  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2733  * set this value too high, the FIFO will fetch frequently to stay full)
2734  * and power consumption (set it too low to save power and we might see
2735  * FIFO underruns and display "flicker").
2736  *
2737  * A value of 5us seems to be a good balance; safe for very low end
2738  * platforms but not overly aggressive on lower latency configs.
2739  */
2740 static const int latency_ns = 5000;
2741
2742 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2743 {
2744         struct drm_i915_private *dev_priv = dev->dev_private;
2745         uint32_t dsparb = I915_READ(DSPARB);
2746         int size;
2747
2748         if (plane == 0)
2749                 size = dsparb & 0x7f;
2750         else
2751                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2752                         (dsparb & 0x7f);
2753
2754         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2755                         plane ? "B" : "A", size);
2756
2757         return size;
2758 }
2759
2760 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2761 {
2762         struct drm_i915_private *dev_priv = dev->dev_private;
2763         uint32_t dsparb = I915_READ(DSPARB);
2764         int size;
2765
2766         if (plane == 0)
2767                 size = dsparb & 0x1ff;
2768         else
2769                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2770                         (dsparb & 0x1ff);
2771         size >>= 1; /* Convert to cachelines */
2772
2773         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2774                         plane ? "B" : "A", size);
2775
2776         return size;
2777 }
2778
2779 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2780 {
2781         struct drm_i915_private *dev_priv = dev->dev_private;
2782         uint32_t dsparb = I915_READ(DSPARB);
2783         int size;
2784
2785         size = dsparb & 0x7f;
2786         size >>= 2; /* Convert to cachelines */
2787
2788         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2789                         plane ? "B" : "A",
2790                   size);
2791
2792         return size;
2793 }
2794
2795 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2796 {
2797         struct drm_i915_private *dev_priv = dev->dev_private;
2798         uint32_t dsparb = I915_READ(DSPARB);
2799         int size;
2800
2801         size = dsparb & 0x7f;
2802         size >>= 1; /* Convert to cachelines */
2803
2804         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2805                         plane ? "B" : "A", size);
2806
2807         return size;
2808 }
2809
2810 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2811                           int planeb_clock, int sr_hdisplay, int pixel_size)
2812 {
2813         struct drm_i915_private *dev_priv = dev->dev_private;
2814         u32 reg;
2815         unsigned long wm;
2816         struct cxsr_latency *latency;
2817         int sr_clock;
2818
2819         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2820                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2821         if (!latency) {
2822                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2823                 pineview_disable_cxsr(dev);
2824                 return;
2825         }
2826
2827         if (!planea_clock || !planeb_clock) {
2828                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2829
2830                 /* Display SR */
2831                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2832                                         pixel_size, latency->display_sr);
2833                 reg = I915_READ(DSPFW1);
2834                 reg &= ~DSPFW_SR_MASK;
2835                 reg |= wm << DSPFW_SR_SHIFT;
2836                 I915_WRITE(DSPFW1, reg);
2837                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2838
2839                 /* cursor SR */
2840                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2841                                         pixel_size, latency->cursor_sr);
2842                 reg = I915_READ(DSPFW3);
2843                 reg &= ~DSPFW_CURSOR_SR_MASK;
2844                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2845                 I915_WRITE(DSPFW3, reg);
2846
2847                 /* Display HPLL off SR */
2848                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2849                                         pixel_size, latency->display_hpll_disable);
2850                 reg = I915_READ(DSPFW3);
2851                 reg &= ~DSPFW_HPLL_SR_MASK;
2852                 reg |= wm & DSPFW_HPLL_SR_MASK;
2853                 I915_WRITE(DSPFW3, reg);
2854
2855                 /* cursor HPLL off SR */
2856                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2857                                         pixel_size, latency->cursor_hpll_disable);
2858                 reg = I915_READ(DSPFW3);
2859                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2860                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2861                 I915_WRITE(DSPFW3, reg);
2862                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2863
2864                 /* activate cxsr */
2865                 reg = I915_READ(DSPFW3);
2866                 reg |= PINEVIEW_SELF_REFRESH_EN;
2867                 I915_WRITE(DSPFW3, reg);
2868                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2869         } else {
2870                 pineview_disable_cxsr(dev);
2871                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2872         }
2873 }
2874
2875 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2876                           int planeb_clock, int sr_hdisplay, int pixel_size)
2877 {
2878         struct drm_i915_private *dev_priv = dev->dev_private;
2879         int total_size, cacheline_size;
2880         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2881         struct intel_watermark_params planea_params, planeb_params;
2882         unsigned long line_time_us;
2883         int sr_clock, sr_entries = 0, entries_required;
2884
2885         /* Create copies of the base settings for each pipe */
2886         planea_params = planeb_params = g4x_wm_info;
2887
2888         /* Grab a couple of global values before we overwrite them */
2889         total_size = planea_params.fifo_size;
2890         cacheline_size = planea_params.cacheline_size;
2891
2892         /*
2893          * Note: we need to make sure we don't overflow for various clock &
2894          * latency values.
2895          * clocks go from a few thousand to several hundred thousand.
2896          * latency is usually a few thousand
2897          */
2898         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2899                 1000;
2900         entries_required /= G4X_FIFO_LINE_SIZE;
2901         planea_wm = entries_required + planea_params.guard_size;
2902
2903         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2904                 1000;
2905         entries_required /= G4X_FIFO_LINE_SIZE;
2906         planeb_wm = entries_required + planeb_params.guard_size;
2907
2908         cursora_wm = cursorb_wm = 16;
2909         cursor_sr = 32;
2910
2911         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2912
2913         /* Calc sr entries for one plane configs */
2914         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2915                 /* self-refresh has much higher latency */
2916                 static const int sr_latency_ns = 12000;
2917
2918                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2919                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2920
2921                 /* Use ns/us then divide to preserve precision */
2922                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2923                               pixel_size * sr_hdisplay) / 1000;
2924                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2925                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2926                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2927         } else {
2928                 /* Turn off self refresh if both pipes are enabled */
2929                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2930                                         & ~FW_BLC_SELF_EN);
2931         }
2932
2933         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2934                   planea_wm, planeb_wm, sr_entries);
2935
2936         planea_wm &= 0x3f;
2937         planeb_wm &= 0x3f;
2938
2939         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2940                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2941                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2942         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2943                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2944         /* HPLL off in SR has some issues on G4x... disable it */
2945         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2946                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2947 }
2948
2949 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2950                            int planeb_clock, int sr_hdisplay, int pixel_size)
2951 {
2952         struct drm_i915_private *dev_priv = dev->dev_private;
2953         unsigned long line_time_us;
2954         int sr_clock, sr_entries, srwm = 1;
2955
2956         /* Calc sr entries for one plane configs */
2957         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2958                 /* self-refresh has much higher latency */
2959                 static const int sr_latency_ns = 12000;
2960
2961                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2962                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2963
2964                 /* Use ns/us then divide to preserve precision */
2965                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2966                               pixel_size * sr_hdisplay) / 1000;
2967                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2968                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2969                 srwm = I945_FIFO_SIZE - sr_entries;
2970                 if (srwm < 0)
2971                         srwm = 1;
2972                 srwm &= 0x3f;
2973                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2974         } else {
2975                 /* Turn off self refresh if both pipes are enabled */
2976                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2977                                         & ~FW_BLC_SELF_EN);
2978         }
2979
2980         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2981                       srwm);
2982
2983         /* 965 has limitations... */
2984         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2985                    (8 << 0));
2986         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2987 }
2988
2989 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2990                            int planeb_clock, int sr_hdisplay, int pixel_size)
2991 {
2992         struct drm_i915_private *dev_priv = dev->dev_private;
2993         uint32_t fwater_lo;
2994         uint32_t fwater_hi;
2995         int total_size, cacheline_size, cwm, srwm = 1;
2996         int planea_wm, planeb_wm;
2997         struct intel_watermark_params planea_params, planeb_params;
2998         unsigned long line_time_us;
2999       &n