drm/i915: Get rid of intel_crtc->config in crtc_enable/disable functions, v2.
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <drm/drm_atomic_uapi.h>
50 #include <linux/dma_remapping.h>
51 #include <linux/reservation.h>
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t i8xx_primary_formats[] = {
55         DRM_FORMAT_C8,
56         DRM_FORMAT_RGB565,
57         DRM_FORMAT_XRGB1555,
58         DRM_FORMAT_XRGB8888,
59 };
60
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t i965_primary_formats[] = {
63         DRM_FORMAT_C8,
64         DRM_FORMAT_RGB565,
65         DRM_FORMAT_XRGB8888,
66         DRM_FORMAT_XBGR8888,
67         DRM_FORMAT_XRGB2101010,
68         DRM_FORMAT_XBGR2101010,
69 };
70
71 static const uint64_t i9xx_format_modifiers[] = {
72         I915_FORMAT_MOD_X_TILED,
73         DRM_FORMAT_MOD_LINEAR,
74         DRM_FORMAT_MOD_INVALID
75 };
76
77 static const uint32_t skl_primary_formats[] = {
78         DRM_FORMAT_C8,
79         DRM_FORMAT_RGB565,
80         DRM_FORMAT_XRGB8888,
81         DRM_FORMAT_XBGR8888,
82         DRM_FORMAT_ARGB8888,
83         DRM_FORMAT_ABGR8888,
84         DRM_FORMAT_XRGB2101010,
85         DRM_FORMAT_XBGR2101010,
86         DRM_FORMAT_YUYV,
87         DRM_FORMAT_YVYU,
88         DRM_FORMAT_UYVY,
89         DRM_FORMAT_VYUY,
90 };
91
92 static const uint32_t skl_pri_planar_formats[] = {
93         DRM_FORMAT_C8,
94         DRM_FORMAT_RGB565,
95         DRM_FORMAT_XRGB8888,
96         DRM_FORMAT_XBGR8888,
97         DRM_FORMAT_ARGB8888,
98         DRM_FORMAT_ABGR8888,
99         DRM_FORMAT_XRGB2101010,
100         DRM_FORMAT_XBGR2101010,
101         DRM_FORMAT_YUYV,
102         DRM_FORMAT_YVYU,
103         DRM_FORMAT_UYVY,
104         DRM_FORMAT_VYUY,
105         DRM_FORMAT_NV12,
106 };
107
108 static const uint64_t skl_format_modifiers_noccs[] = {
109         I915_FORMAT_MOD_Yf_TILED,
110         I915_FORMAT_MOD_Y_TILED,
111         I915_FORMAT_MOD_X_TILED,
112         DRM_FORMAT_MOD_LINEAR,
113         DRM_FORMAT_MOD_INVALID
114 };
115
116 static const uint64_t skl_format_modifiers_ccs[] = {
117         I915_FORMAT_MOD_Yf_TILED_CCS,
118         I915_FORMAT_MOD_Y_TILED_CCS,
119         I915_FORMAT_MOD_Yf_TILED,
120         I915_FORMAT_MOD_Y_TILED,
121         I915_FORMAT_MOD_X_TILED,
122         DRM_FORMAT_MOD_LINEAR,
123         DRM_FORMAT_MOD_INVALID
124 };
125
126 /* Cursor formats */
127 static const uint32_t intel_cursor_formats[] = {
128         DRM_FORMAT_ARGB8888,
129 };
130
131 static const uint64_t cursor_format_modifiers[] = {
132         DRM_FORMAT_MOD_LINEAR,
133         DRM_FORMAT_MOD_INVALID
134 };
135
136 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
137                                 struct intel_crtc_state *pipe_config);
138 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
139                                    struct intel_crtc_state *pipe_config);
140
141 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
142                                   struct drm_i915_gem_object *obj,
143                                   struct drm_mode_fb_cmd2 *mode_cmd);
144 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
145 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
146 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
147                                          struct intel_link_m_n *m_n,
148                                          struct intel_link_m_n *m2_n2);
149 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
150 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
151 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
152 static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state);
153 static void vlv_prepare_pll(struct intel_crtc *crtc,
154                             const struct intel_crtc_state *pipe_config);
155 static void chv_prepare_pll(struct intel_crtc *crtc,
156                             const struct intel_crtc_state *pipe_config);
157 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
158 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
159 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
160                                     struct intel_crtc_state *crtc_state);
161 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
162 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
163 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
164 static void intel_modeset_setup_hw_state(struct drm_device *dev,
165                                          struct drm_modeset_acquire_ctx *ctx);
166 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
167
168 struct intel_limit {
169         struct {
170                 int min, max;
171         } dot, vco, n, m, m1, m2, p, p1;
172
173         struct {
174                 int dot_limit;
175                 int p2_slow, p2_fast;
176         } p2;
177 };
178
179 /* returns HPLL frequency in kHz */
180 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
181 {
182         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
183
184         /* Obtain SKU information */
185         mutex_lock(&dev_priv->sb_lock);
186         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
187                 CCK_FUSE_HPLL_FREQ_MASK;
188         mutex_unlock(&dev_priv->sb_lock);
189
190         return vco_freq[hpll_freq] * 1000;
191 }
192
193 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
194                       const char *name, u32 reg, int ref_freq)
195 {
196         u32 val;
197         int divider;
198
199         mutex_lock(&dev_priv->sb_lock);
200         val = vlv_cck_read(dev_priv, reg);
201         mutex_unlock(&dev_priv->sb_lock);
202
203         divider = val & CCK_FREQUENCY_VALUES;
204
205         WARN((val & CCK_FREQUENCY_STATUS) !=
206              (divider << CCK_FREQUENCY_STATUS_SHIFT),
207              "%s change in progress\n", name);
208
209         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
210 }
211
212 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
213                            const char *name, u32 reg)
214 {
215         if (dev_priv->hpll_freq == 0)
216                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
217
218         return vlv_get_cck_clock(dev_priv, name, reg,
219                                  dev_priv->hpll_freq);
220 }
221
222 static void intel_update_czclk(struct drm_i915_private *dev_priv)
223 {
224         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
225                 return;
226
227         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
228                                                       CCK_CZ_CLOCK_CONTROL);
229
230         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
231 }
232
233 static inline u32 /* units of 100MHz */
234 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
235                     const struct intel_crtc_state *pipe_config)
236 {
237         if (HAS_DDI(dev_priv))
238                 return pipe_config->port_clock; /* SPLL */
239         else
240                 return dev_priv->fdi_pll_freq;
241 }
242
243 static const struct intel_limit intel_limits_i8xx_dac = {
244         .dot = { .min = 25000, .max = 350000 },
245         .vco = { .min = 908000, .max = 1512000 },
246         .n = { .min = 2, .max = 16 },
247         .m = { .min = 96, .max = 140 },
248         .m1 = { .min = 18, .max = 26 },
249         .m2 = { .min = 6, .max = 16 },
250         .p = { .min = 4, .max = 128 },
251         .p1 = { .min = 2, .max = 33 },
252         .p2 = { .dot_limit = 165000,
253                 .p2_slow = 4, .p2_fast = 2 },
254 };
255
256 static const struct intel_limit intel_limits_i8xx_dvo = {
257         .dot = { .min = 25000, .max = 350000 },
258         .vco = { .min = 908000, .max = 1512000 },
259         .n = { .min = 2, .max = 16 },
260         .m = { .min = 96, .max = 140 },
261         .m1 = { .min = 18, .max = 26 },
262         .m2 = { .min = 6, .max = 16 },
263         .p = { .min = 4, .max = 128 },
264         .p1 = { .min = 2, .max = 33 },
265         .p2 = { .dot_limit = 165000,
266                 .p2_slow = 4, .p2_fast = 4 },
267 };
268
269 static const struct intel_limit intel_limits_i8xx_lvds = {
270         .dot = { .min = 25000, .max = 350000 },
271         .vco = { .min = 908000, .max = 1512000 },
272         .n = { .min = 2, .max = 16 },
273         .m = { .min = 96, .max = 140 },
274         .m1 = { .min = 18, .max = 26 },
275         .m2 = { .min = 6, .max = 16 },
276         .p = { .min = 4, .max = 128 },
277         .p1 = { .min = 1, .max = 6 },
278         .p2 = { .dot_limit = 165000,
279                 .p2_slow = 14, .p2_fast = 7 },
280 };
281
282 static const struct intel_limit intel_limits_i9xx_sdvo = {
283         .dot = { .min = 20000, .max = 400000 },
284         .vco = { .min = 1400000, .max = 2800000 },
285         .n = { .min = 1, .max = 6 },
286         .m = { .min = 70, .max = 120 },
287         .m1 = { .min = 8, .max = 18 },
288         .m2 = { .min = 3, .max = 7 },
289         .p = { .min = 5, .max = 80 },
290         .p1 = { .min = 1, .max = 8 },
291         .p2 = { .dot_limit = 200000,
292                 .p2_slow = 10, .p2_fast = 5 },
293 };
294
295 static const struct intel_limit intel_limits_i9xx_lvds = {
296         .dot = { .min = 20000, .max = 400000 },
297         .vco = { .min = 1400000, .max = 2800000 },
298         .n = { .min = 1, .max = 6 },
299         .m = { .min = 70, .max = 120 },
300         .m1 = { .min = 8, .max = 18 },
301         .m2 = { .min = 3, .max = 7 },
302         .p = { .min = 7, .max = 98 },
303         .p1 = { .min = 1, .max = 8 },
304         .p2 = { .dot_limit = 112000,
305                 .p2_slow = 14, .p2_fast = 7 },
306 };
307
308
309 static const struct intel_limit intel_limits_g4x_sdvo = {
310         .dot = { .min = 25000, .max = 270000 },
311         .vco = { .min = 1750000, .max = 3500000},
312         .n = { .min = 1, .max = 4 },
313         .m = { .min = 104, .max = 138 },
314         .m1 = { .min = 17, .max = 23 },
315         .m2 = { .min = 5, .max = 11 },
316         .p = { .min = 10, .max = 30 },
317         .p1 = { .min = 1, .max = 3},
318         .p2 = { .dot_limit = 270000,
319                 .p2_slow = 10,
320                 .p2_fast = 10
321         },
322 };
323
324 static const struct intel_limit intel_limits_g4x_hdmi = {
325         .dot = { .min = 22000, .max = 400000 },
326         .vco = { .min = 1750000, .max = 3500000},
327         .n = { .min = 1, .max = 4 },
328         .m = { .min = 104, .max = 138 },
329         .m1 = { .min = 16, .max = 23 },
330         .m2 = { .min = 5, .max = 11 },
331         .p = { .min = 5, .max = 80 },
332         .p1 = { .min = 1, .max = 8},
333         .p2 = { .dot_limit = 165000,
334                 .p2_slow = 10, .p2_fast = 5 },
335 };
336
337 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
338         .dot = { .min = 20000, .max = 115000 },
339         .vco = { .min = 1750000, .max = 3500000 },
340         .n = { .min = 1, .max = 3 },
341         .m = { .min = 104, .max = 138 },
342         .m1 = { .min = 17, .max = 23 },
343         .m2 = { .min = 5, .max = 11 },
344         .p = { .min = 28, .max = 112 },
345         .p1 = { .min = 2, .max = 8 },
346         .p2 = { .dot_limit = 0,
347                 .p2_slow = 14, .p2_fast = 14
348         },
349 };
350
351 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
352         .dot = { .min = 80000, .max = 224000 },
353         .vco = { .min = 1750000, .max = 3500000 },
354         .n = { .min = 1, .max = 3 },
355         .m = { .min = 104, .max = 138 },
356         .m1 = { .min = 17, .max = 23 },
357         .m2 = { .min = 5, .max = 11 },
358         .p = { .min = 14, .max = 42 },
359         .p1 = { .min = 2, .max = 6 },
360         .p2 = { .dot_limit = 0,
361                 .p2_slow = 7, .p2_fast = 7
362         },
363 };
364
365 static const struct intel_limit intel_limits_pineview_sdvo = {
366         .dot = { .min = 20000, .max = 400000},
367         .vco = { .min = 1700000, .max = 3500000 },
368         /* Pineview's Ncounter is a ring counter */
369         .n = { .min = 3, .max = 6 },
370         .m = { .min = 2, .max = 256 },
371         /* Pineview only has one combined m divider, which we treat as m2. */
372         .m1 = { .min = 0, .max = 0 },
373         .m2 = { .min = 0, .max = 254 },
374         .p = { .min = 5, .max = 80 },
375         .p1 = { .min = 1, .max = 8 },
376         .p2 = { .dot_limit = 200000,
377                 .p2_slow = 10, .p2_fast = 5 },
378 };
379
380 static const struct intel_limit intel_limits_pineview_lvds = {
381         .dot = { .min = 20000, .max = 400000 },
382         .vco = { .min = 1700000, .max = 3500000 },
383         .n = { .min = 3, .max = 6 },
384         .m = { .min = 2, .max = 256 },
385         .m1 = { .min = 0, .max = 0 },
386         .m2 = { .min = 0, .max = 254 },
387         .p = { .min = 7, .max = 112 },
388         .p1 = { .min = 1, .max = 8 },
389         .p2 = { .dot_limit = 112000,
390                 .p2_slow = 14, .p2_fast = 14 },
391 };
392
393 /* Ironlake / Sandybridge
394  *
395  * We calculate clock using (register_value + 2) for N/M1/M2, so here
396  * the range value for them is (actual_value - 2).
397  */
398 static const struct intel_limit intel_limits_ironlake_dac = {
399         .dot = { .min = 25000, .max = 350000 },
400         .vco = { .min = 1760000, .max = 3510000 },
401         .n = { .min = 1, .max = 5 },
402         .m = { .min = 79, .max = 127 },
403         .m1 = { .min = 12, .max = 22 },
404         .m2 = { .min = 5, .max = 9 },
405         .p = { .min = 5, .max = 80 },
406         .p1 = { .min = 1, .max = 8 },
407         .p2 = { .dot_limit = 225000,
408                 .p2_slow = 10, .p2_fast = 5 },
409 };
410
411 static const struct intel_limit intel_limits_ironlake_single_lvds = {
412         .dot = { .min = 25000, .max = 350000 },
413         .vco = { .min = 1760000, .max = 3510000 },
414         .n = { .min = 1, .max = 3 },
415         .m = { .min = 79, .max = 118 },
416         .m1 = { .min = 12, .max = 22 },
417         .m2 = { .min = 5, .max = 9 },
418         .p = { .min = 28, .max = 112 },
419         .p1 = { .min = 2, .max = 8 },
420         .p2 = { .dot_limit = 225000,
421                 .p2_slow = 14, .p2_fast = 14 },
422 };
423
424 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
425         .dot = { .min = 25000, .max = 350000 },
426         .vco = { .min = 1760000, .max = 3510000 },
427         .n = { .min = 1, .max = 3 },
428         .m = { .min = 79, .max = 127 },
429         .m1 = { .min = 12, .max = 22 },
430         .m2 = { .min = 5, .max = 9 },
431         .p = { .min = 14, .max = 56 },
432         .p1 = { .min = 2, .max = 8 },
433         .p2 = { .dot_limit = 225000,
434                 .p2_slow = 7, .p2_fast = 7 },
435 };
436
437 /* LVDS 100mhz refclk limits. */
438 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
439         .dot = { .min = 25000, .max = 350000 },
440         .vco = { .min = 1760000, .max = 3510000 },
441         .n = { .min = 1, .max = 2 },
442         .m = { .min = 79, .max = 126 },
443         .m1 = { .min = 12, .max = 22 },
444         .m2 = { .min = 5, .max = 9 },
445         .p = { .min = 28, .max = 112 },
446         .p1 = { .min = 2, .max = 8 },
447         .p2 = { .dot_limit = 225000,
448                 .p2_slow = 14, .p2_fast = 14 },
449 };
450
451 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
452         .dot = { .min = 25000, .max = 350000 },
453         .vco = { .min = 1760000, .max = 3510000 },
454         .n = { .min = 1, .max = 3 },
455         .m = { .min = 79, .max = 126 },
456         .m1 = { .min = 12, .max = 22 },
457         .m2 = { .min = 5, .max = 9 },
458         .p = { .min = 14, .max = 42 },
459         .p1 = { .min = 2, .max = 6 },
460         .p2 = { .dot_limit = 225000,
461                 .p2_slow = 7, .p2_fast = 7 },
462 };
463
464 static const struct intel_limit intel_limits_vlv = {
465          /*
466           * These are the data rate limits (measured in fast clocks)
467           * since those are the strictest limits we have. The fast
468           * clock and actual rate limits are more relaxed, so checking
469           * them would make no difference.
470           */
471         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
472         .vco = { .min = 4000000, .max = 6000000 },
473         .n = { .min = 1, .max = 7 },
474         .m1 = { .min = 2, .max = 3 },
475         .m2 = { .min = 11, .max = 156 },
476         .p1 = { .min = 2, .max = 3 },
477         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
478 };
479
480 static const struct intel_limit intel_limits_chv = {
481         /*
482          * These are the data rate limits (measured in fast clocks)
483          * since those are the strictest limits we have.  The fast
484          * clock and actual rate limits are more relaxed, so checking
485          * them would make no difference.
486          */
487         .dot = { .min = 25000 * 5, .max = 540000 * 5},
488         .vco = { .min = 4800000, .max = 6480000 },
489         .n = { .min = 1, .max = 1 },
490         .m1 = { .min = 2, .max = 2 },
491         .m2 = { .min = 24 << 22, .max = 175 << 22 },
492         .p1 = { .min = 2, .max = 4 },
493         .p2 = { .p2_slow = 1, .p2_fast = 14 },
494 };
495
496 static const struct intel_limit intel_limits_bxt = {
497         /* FIXME: find real dot limits */
498         .dot = { .min = 0, .max = INT_MAX },
499         .vco = { .min = 4800000, .max = 6700000 },
500         .n = { .min = 1, .max = 1 },
501         .m1 = { .min = 2, .max = 2 },
502         /* FIXME: find real m2 limits */
503         .m2 = { .min = 2 << 22, .max = 255 << 22 },
504         .p1 = { .min = 2, .max = 4 },
505         .p2 = { .p2_slow = 1, .p2_fast = 20 },
506 };
507
508 static void
509 skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
510 {
511         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
512                 return;
513
514         if (enable)
515                 I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
516         else
517                 I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);
518 }
519
520 static void
521 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
522 {
523         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
524                 return;
525
526         if (enable)
527                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
528                            DUPS1_GATING_DIS | DUPS2_GATING_DIS);
529         else
530                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
531                            I915_READ(CLKGATE_DIS_PSL(pipe)) &
532                            ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
533 }
534
535 static bool
536 needs_modeset(const struct drm_crtc_state *state)
537 {
538         return drm_atomic_crtc_needs_modeset(state);
539 }
540
541 /*
542  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
543  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
544  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
545  * The helpers' return value is the rate of the clock that is fed to the
546  * display engine's pipe which can be the above fast dot clock rate or a
547  * divided-down version of it.
548  */
549 /* m1 is reserved as 0 in Pineview, n is a ring counter */
550 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
551 {
552         clock->m = clock->m2 + 2;
553         clock->p = clock->p1 * clock->p2;
554         if (WARN_ON(clock->n == 0 || clock->p == 0))
555                 return 0;
556         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558
559         return clock->dot;
560 }
561
562 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
563 {
564         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
565 }
566
567 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
568 {
569         clock->m = i9xx_dpll_compute_m(clock);
570         clock->p = clock->p1 * clock->p2;
571         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
572                 return 0;
573         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
574         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
575
576         return clock->dot;
577 }
578
579 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
580 {
581         clock->m = clock->m1 * clock->m2;
582         clock->p = clock->p1 * clock->p2;
583         if (WARN_ON(clock->n == 0 || clock->p == 0))
584                 return 0;
585         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
586         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
587
588         return clock->dot / 5;
589 }
590
591 int chv_calc_dpll_params(int refclk, struct dpll *clock)
592 {
593         clock->m = clock->m1 * clock->m2;
594         clock->p = clock->p1 * clock->p2;
595         if (WARN_ON(clock->n == 0 || clock->p == 0))
596                 return 0;
597         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
598                         clock->n << 22);
599         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
600
601         return clock->dot / 5;
602 }
603
604 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
605
606 /*
607  * Returns whether the given set of divisors are valid for a given refclk with
608  * the given connectors.
609  */
610 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
611                                const struct intel_limit *limit,
612                                const struct dpll *clock)
613 {
614         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
615                 INTELPllInvalid("n out of range\n");
616         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
617                 INTELPllInvalid("p1 out of range\n");
618         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
619                 INTELPllInvalid("m2 out of range\n");
620         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
621                 INTELPllInvalid("m1 out of range\n");
622
623         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
624             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
625                 if (clock->m1 <= clock->m2)
626                         INTELPllInvalid("m1 <= m2\n");
627
628         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
629             !IS_GEN9_LP(dev_priv)) {
630                 if (clock->p < limit->p.min || limit->p.max < clock->p)
631                         INTELPllInvalid("p out of range\n");
632                 if (clock->m < limit->m.min || limit->m.max < clock->m)
633                         INTELPllInvalid("m out of range\n");
634         }
635
636         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
637                 INTELPllInvalid("vco out of range\n");
638         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
639          * connector, etc., rather than just a single range.
640          */
641         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
642                 INTELPllInvalid("dot out of range\n");
643
644         return true;
645 }
646
647 static int
648 i9xx_select_p2_div(const struct intel_limit *limit,
649                    const struct intel_crtc_state *crtc_state,
650                    int target)
651 {
652         struct drm_device *dev = crtc_state->base.crtc->dev;
653
654         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
655                 /*
656                  * For LVDS just rely on its current settings for dual-channel.
657                  * We haven't figured out how to reliably set up different
658                  * single/dual channel state, if we even can.
659                  */
660                 if (intel_is_dual_link_lvds(dev))
661                         return limit->p2.p2_fast;
662                 else
663                         return limit->p2.p2_slow;
664         } else {
665                 if (target < limit->p2.dot_limit)
666                         return limit->p2.p2_slow;
667                 else
668                         return limit->p2.p2_fast;
669         }
670 }
671
672 /*
673  * Returns a set of divisors for the desired target clock with the given
674  * refclk, or FALSE.  The returned values represent the clock equation:
675  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
676  *
677  * Target and reference clocks are specified in kHz.
678  *
679  * If match_clock is provided, then best_clock P divider must match the P
680  * divider from @match_clock used for LVDS downclocking.
681  */
682 static bool
683 i9xx_find_best_dpll(const struct intel_limit *limit,
684                     struct intel_crtc_state *crtc_state,
685                     int target, int refclk, struct dpll *match_clock,
686                     struct dpll *best_clock)
687 {
688         struct drm_device *dev = crtc_state->base.crtc->dev;
689         struct dpll clock;
690         int err = target;
691
692         memset(best_clock, 0, sizeof(*best_clock));
693
694         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
695
696         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
697              clock.m1++) {
698                 for (clock.m2 = limit->m2.min;
699                      clock.m2 <= limit->m2.max; clock.m2++) {
700                         if (clock.m2 >= clock.m1)
701                                 break;
702                         for (clock.n = limit->n.min;
703                              clock.n <= limit->n.max; clock.n++) {
704                                 for (clock.p1 = limit->p1.min;
705                                         clock.p1 <= limit->p1.max; clock.p1++) {
706                                         int this_err;
707
708                                         i9xx_calc_dpll_params(refclk, &clock);
709                                         if (!intel_PLL_is_valid(to_i915(dev),
710                                                                 limit,
711                                                                 &clock))
712                                                 continue;
713                                         if (match_clock &&
714                                             clock.p != match_clock->p)
715                                                 continue;
716
717                                         this_err = abs(clock.dot - target);
718                                         if (this_err < err) {
719                                                 *best_clock = clock;
720                                                 err = this_err;
721                                         }
722                                 }
723                         }
724                 }
725         }
726
727         return (err != target);
728 }
729
730 /*
731  * Returns a set of divisors for the desired target clock with the given
732  * refclk, or FALSE.  The returned values represent the clock equation:
733  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
734  *
735  * Target and reference clocks are specified in kHz.
736  *
737  * If match_clock is provided, then best_clock P divider must match the P
738  * divider from @match_clock used for LVDS downclocking.
739  */
740 static bool
741 pnv_find_best_dpll(const struct intel_limit *limit,
742                    struct intel_crtc_state *crtc_state,
743                    int target, int refclk, struct dpll *match_clock,
744                    struct dpll *best_clock)
745 {
746         struct drm_device *dev = crtc_state->base.crtc->dev;
747         struct dpll clock;
748         int err = target;
749
750         memset(best_clock, 0, sizeof(*best_clock));
751
752         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
753
754         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
755              clock.m1++) {
756                 for (clock.m2 = limit->m2.min;
757                      clock.m2 <= limit->m2.max; clock.m2++) {
758                         for (clock.n = limit->n.min;
759                              clock.n <= limit->n.max; clock.n++) {
760                                 for (clock.p1 = limit->p1.min;
761                                         clock.p1 <= limit->p1.max; clock.p1++) {
762                                         int this_err;
763
764                                         pnv_calc_dpll_params(refclk, &clock);
765                                         if (!intel_PLL_is_valid(to_i915(dev),
766                                                                 limit,
767                                                                 &clock))
768                                                 continue;
769                                         if (match_clock &&
770                                             clock.p != match_clock->p)
771                                                 continue;
772
773                                         this_err = abs(clock.dot - target);
774                                         if (this_err < err) {
775                                                 *best_clock = clock;
776                                                 err = this_err;
777                                         }
778                                 }
779                         }
780                 }
781         }
782
783         return (err != target);
784 }
785
786 /*
787  * Returns a set of divisors for the desired target clock with the given
788  * refclk, or FALSE.  The returned values represent the clock equation:
789  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
790  *
791  * Target and reference clocks are specified in kHz.
792  *
793  * If match_clock is provided, then best_clock P divider must match the P
794  * divider from @match_clock used for LVDS downclocking.
795  */
796 static bool
797 g4x_find_best_dpll(const struct intel_limit *limit,
798                    struct intel_crtc_state *crtc_state,
799                    int target, int refclk, struct dpll *match_clock,
800                    struct dpll *best_clock)
801 {
802         struct drm_device *dev = crtc_state->base.crtc->dev;
803         struct dpll clock;
804         int max_n;
805         bool found = false;
806         /* approximately equals target * 0.00585 */
807         int err_most = (target >> 8) + (target >> 9);
808
809         memset(best_clock, 0, sizeof(*best_clock));
810
811         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
812
813         max_n = limit->n.max;
814         /* based on hardware requirement, prefer smaller n to precision */
815         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
816                 /* based on hardware requirement, prefere larger m1,m2 */
817                 for (clock.m1 = limit->m1.max;
818                      clock.m1 >= limit->m1.min; clock.m1--) {
819                         for (clock.m2 = limit->m2.max;
820                              clock.m2 >= limit->m2.min; clock.m2--) {
821                                 for (clock.p1 = limit->p1.max;
822                                      clock.p1 >= limit->p1.min; clock.p1--) {
823                                         int this_err;
824
825                                         i9xx_calc_dpll_params(refclk, &clock);
826                                         if (!intel_PLL_is_valid(to_i915(dev),
827                                                                 limit,
828                                                                 &clock))
829                                                 continue;
830
831                                         this_err = abs(clock.dot - target);
832                                         if (this_err < err_most) {
833                                                 *best_clock = clock;
834                                                 err_most = this_err;
835                                                 max_n = clock.n;
836                                                 found = true;
837                                         }
838                                 }
839                         }
840                 }
841         }
842         return found;
843 }
844
845 /*
846  * Check if the calculated PLL configuration is more optimal compared to the
847  * best configuration and error found so far. Return the calculated error.
848  */
849 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
850                                const struct dpll *calculated_clock,
851                                const struct dpll *best_clock,
852                                unsigned int best_error_ppm,
853                                unsigned int *error_ppm)
854 {
855         /*
856          * For CHV ignore the error and consider only the P value.
857          * Prefer a bigger P value based on HW requirements.
858          */
859         if (IS_CHERRYVIEW(to_i915(dev))) {
860                 *error_ppm = 0;
861
862                 return calculated_clock->p > best_clock->p;
863         }
864
865         if (WARN_ON_ONCE(!target_freq))
866                 return false;
867
868         *error_ppm = div_u64(1000000ULL *
869                                 abs(target_freq - calculated_clock->dot),
870                              target_freq);
871         /*
872          * Prefer a better P value over a better (smaller) error if the error
873          * is small. Ensure this preference for future configurations too by
874          * setting the error to 0.
875          */
876         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
877                 *error_ppm = 0;
878
879                 return true;
880         }
881
882         return *error_ppm + 10 < best_error_ppm;
883 }
884
885 /*
886  * Returns a set of divisors for the desired target clock with the given
887  * refclk, or FALSE.  The returned values represent the clock equation:
888  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
889  */
890 static bool
891 vlv_find_best_dpll(const struct intel_limit *limit,
892                    struct intel_crtc_state *crtc_state,
893                    int target, int refclk, struct dpll *match_clock,
894                    struct dpll *best_clock)
895 {
896         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
897         struct drm_device *dev = crtc->base.dev;
898         struct dpll clock;
899         unsigned int bestppm = 1000000;
900         /* min update 19.2 MHz */
901         int max_n = min(limit->n.max, refclk / 19200);
902         bool found = false;
903
904         target *= 5; /* fast clock */
905
906         memset(best_clock, 0, sizeof(*best_clock));
907
908         /* based on hardware requirement, prefer smaller n to precision */
909         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
910                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
911                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
912                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
913                                 clock.p = clock.p1 * clock.p2;
914                                 /* based on hardware requirement, prefer bigger m1,m2 values */
915                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
916                                         unsigned int ppm;
917
918                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
919                                                                      refclk * clock.m1);
920
921                                         vlv_calc_dpll_params(refclk, &clock);
922
923                                         if (!intel_PLL_is_valid(to_i915(dev),
924                                                                 limit,
925                                                                 &clock))
926                                                 continue;
927
928                                         if (!vlv_PLL_is_optimal(dev, target,
929                                                                 &clock,
930                                                                 best_clock,
931                                                                 bestppm, &ppm))
932                                                 continue;
933
934                                         *best_clock = clock;
935                                         bestppm = ppm;
936                                         found = true;
937                                 }
938                         }
939                 }
940         }
941
942         return found;
943 }
944
945 /*
946  * Returns a set of divisors for the desired target clock with the given
947  * refclk, or FALSE.  The returned values represent the clock equation:
948  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
949  */
950 static bool
951 chv_find_best_dpll(const struct intel_limit *limit,
952                    struct intel_crtc_state *crtc_state,
953                    int target, int refclk, struct dpll *match_clock,
954                    struct dpll *best_clock)
955 {
956         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
957         struct drm_device *dev = crtc->base.dev;
958         unsigned int best_error_ppm;
959         struct dpll clock;
960         uint64_t m2;
961         int found = false;
962
963         memset(best_clock, 0, sizeof(*best_clock));
964         best_error_ppm = 1000000;
965
966         /*
967          * Based on hardware doc, the n always set to 1, and m1 always
968          * set to 2.  If requires to support 200Mhz refclk, we need to
969          * revisit this because n may not 1 anymore.
970          */
971         clock.n = 1, clock.m1 = 2;
972         target *= 5;    /* fast clock */
973
974         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
975                 for (clock.p2 = limit->p2.p2_fast;
976                                 clock.p2 >= limit->p2.p2_slow;
977                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
978                         unsigned int error_ppm;
979
980                         clock.p = clock.p1 * clock.p2;
981
982                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
983                                         clock.n) << 22, refclk * clock.m1);
984
985                         if (m2 > INT_MAX/clock.m1)
986                                 continue;
987
988                         clock.m2 = m2;
989
990                         chv_calc_dpll_params(refclk, &clock);
991
992                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
993                                 continue;
994
995                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
996                                                 best_error_ppm, &error_ppm))
997                                 continue;
998
999                         *best_clock = clock;
1000                         best_error_ppm = error_ppm;
1001                         found = true;
1002                 }
1003         }
1004
1005         return found;
1006 }
1007
1008 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1009                         struct dpll *best_clock)
1010 {
1011         int refclk = 100000;
1012         const struct intel_limit *limit = &intel_limits_bxt;
1013
1014         return chv_find_best_dpll(limit, crtc_state,
1015                                   target_clock, refclk, NULL, best_clock);
1016 }
1017
1018 bool intel_crtc_active(struct intel_crtc *crtc)
1019 {
1020         /* Be paranoid as we can arrive here with only partial
1021          * state retrieved from the hardware during setup.
1022          *
1023          * We can ditch the adjusted_mode.crtc_clock check as soon
1024          * as Haswell has gained clock readout/fastboot support.
1025          *
1026          * We can ditch the crtc->primary->state->fb check as soon as we can
1027          * properly reconstruct framebuffers.
1028          *
1029          * FIXME: The intel_crtc->active here should be switched to
1030          * crtc->state->active once we have proper CRTC states wired up
1031          * for atomic.
1032          */
1033         return crtc->active && crtc->base.primary->state->fb &&
1034                 crtc->config->base.adjusted_mode.crtc_clock;
1035 }
1036
1037 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1038                                              enum pipe pipe)
1039 {
1040         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1041
1042         return crtc->config->cpu_transcoder;
1043 }
1044
1045 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1046                                     enum pipe pipe)
1047 {
1048         i915_reg_t reg = PIPEDSL(pipe);
1049         u32 line1, line2;
1050         u32 line_mask;
1051
1052         if (IS_GEN2(dev_priv))
1053                 line_mask = DSL_LINEMASK_GEN2;
1054         else
1055                 line_mask = DSL_LINEMASK_GEN3;
1056
1057         line1 = I915_READ(reg) & line_mask;
1058         msleep(5);
1059         line2 = I915_READ(reg) & line_mask;
1060
1061         return line1 != line2;
1062 }
1063
1064 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1065 {
1066         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067         enum pipe pipe = crtc->pipe;
1068
1069         /* Wait for the display line to settle/start moving */
1070         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1071                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1072                           pipe_name(pipe), onoff(state));
1073 }
1074
1075 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1076 {
1077         wait_for_pipe_scanline_moving(crtc, false);
1078 }
1079
1080 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1081 {
1082         wait_for_pipe_scanline_moving(crtc, true);
1083 }
1084
1085 static void
1086 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1087 {
1088         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1089         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1090
1091         if (INTEL_GEN(dev_priv) >= 4) {
1092                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1093                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1094
1095                 /* Wait for the Pipe State to go off */
1096                 if (intel_wait_for_register(dev_priv,
1097                                             reg, I965_PIPECONF_ACTIVE, 0,
1098                                             100))
1099                         WARN(1, "pipe_off wait timed out\n");
1100         } else {
1101                 intel_wait_for_pipe_scanline_stopped(crtc);
1102         }
1103 }
1104
1105 /* Only for pre-ILK configs */
1106 void assert_pll(struct drm_i915_private *dev_priv,
1107                 enum pipe pipe, bool state)
1108 {
1109         u32 val;
1110         bool cur_state;
1111
1112         val = I915_READ(DPLL(pipe));
1113         cur_state = !!(val & DPLL_VCO_ENABLE);
1114         I915_STATE_WARN(cur_state != state,
1115              "PLL state assertion failure (expected %s, current %s)\n",
1116                         onoff(state), onoff(cur_state));
1117 }
1118
1119 /* XXX: the dsi pll is shared between MIPI DSI ports */
1120 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1121 {
1122         u32 val;
1123         bool cur_state;
1124
1125         mutex_lock(&dev_priv->sb_lock);
1126         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1127         mutex_unlock(&dev_priv->sb_lock);
1128
1129         cur_state = val & DSI_PLL_VCO_EN;
1130         I915_STATE_WARN(cur_state != state,
1131              "DSI PLL state assertion failure (expected %s, current %s)\n",
1132                         onoff(state), onoff(cur_state));
1133 }
1134
1135 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1136                           enum pipe pipe, bool state)
1137 {
1138         bool cur_state;
1139         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1140                                                                       pipe);
1141
1142         if (HAS_DDI(dev_priv)) {
1143                 /* DDI does not have a specific FDI_TX register */
1144                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1145                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1146         } else {
1147                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1148                 cur_state = !!(val & FDI_TX_ENABLE);
1149         }
1150         I915_STATE_WARN(cur_state != state,
1151              "FDI TX state assertion failure (expected %s, current %s)\n",
1152                         onoff(state), onoff(cur_state));
1153 }
1154 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1155 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1156
1157 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1158                           enum pipe pipe, bool state)
1159 {
1160         u32 val;
1161         bool cur_state;
1162
1163         val = I915_READ(FDI_RX_CTL(pipe));
1164         cur_state = !!(val & FDI_RX_ENABLE);
1165         I915_STATE_WARN(cur_state != state,
1166              "FDI RX state assertion failure (expected %s, current %s)\n",
1167                         onoff(state), onoff(cur_state));
1168 }
1169 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1170 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1171
1172 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1173                                       enum pipe pipe)
1174 {
1175         u32 val;
1176
1177         /* ILK FDI PLL is always enabled */
1178         if (IS_GEN5(dev_priv))
1179                 return;
1180
1181         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1182         if (HAS_DDI(dev_priv))
1183                 return;
1184
1185         val = I915_READ(FDI_TX_CTL(pipe));
1186         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1187 }
1188
1189 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1190                        enum pipe pipe, bool state)
1191 {
1192         u32 val;
1193         bool cur_state;
1194
1195         val = I915_READ(FDI_RX_CTL(pipe));
1196         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1197         I915_STATE_WARN(cur_state != state,
1198              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1199                         onoff(state), onoff(cur_state));
1200 }
1201
1202 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1203 {
1204         i915_reg_t pp_reg;
1205         u32 val;
1206         enum pipe panel_pipe = INVALID_PIPE;
1207         bool locked = true;
1208
1209         if (WARN_ON(HAS_DDI(dev_priv)))
1210                 return;
1211
1212         if (HAS_PCH_SPLIT(dev_priv)) {
1213                 u32 port_sel;
1214
1215                 pp_reg = PP_CONTROL(0);
1216                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1217
1218                 switch (port_sel) {
1219                 case PANEL_PORT_SELECT_LVDS:
1220                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1221                         break;
1222                 case PANEL_PORT_SELECT_DPA:
1223                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1224                         break;
1225                 case PANEL_PORT_SELECT_DPC:
1226                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1227                         break;
1228                 case PANEL_PORT_SELECT_DPD:
1229                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1230                         break;
1231                 default:
1232                         MISSING_CASE(port_sel);
1233                         break;
1234                 }
1235         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1236                 /* presumably write lock depends on pipe, not port select */
1237                 pp_reg = PP_CONTROL(pipe);
1238                 panel_pipe = pipe;
1239         } else {
1240                 u32 port_sel;
1241
1242                 pp_reg = PP_CONTROL(0);
1243                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1244
1245                 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1246                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1247         }
1248
1249         val = I915_READ(pp_reg);
1250         if (!(val & PANEL_POWER_ON) ||
1251             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1252                 locked = false;
1253
1254         I915_STATE_WARN(panel_pipe == pipe && locked,
1255              "panel assertion failure, pipe %c regs locked\n",
1256              pipe_name(pipe));
1257 }
1258
1259 void assert_pipe(struct drm_i915_private *dev_priv,
1260                  enum pipe pipe, bool state)
1261 {
1262         bool cur_state;
1263         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1264                                                                       pipe);
1265         enum intel_display_power_domain power_domain;
1266
1267         /* we keep both pipes enabled on 830 */
1268         if (IS_I830(dev_priv))
1269                 state = true;
1270
1271         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1272         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1273                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1274                 cur_state = !!(val & PIPECONF_ENABLE);
1275
1276                 intel_display_power_put(dev_priv, power_domain);
1277         } else {
1278                 cur_state = false;
1279         }
1280
1281         I915_STATE_WARN(cur_state != state,
1282              "pipe %c assertion failure (expected %s, current %s)\n",
1283                         pipe_name(pipe), onoff(state), onoff(cur_state));
1284 }
1285
1286 static void assert_plane(struct intel_plane *plane, bool state)
1287 {
1288         enum pipe pipe;
1289         bool cur_state;
1290
1291         cur_state = plane->get_hw_state(plane, &pipe);
1292
1293         I915_STATE_WARN(cur_state != state,
1294                         "%s assertion failure (expected %s, current %s)\n",
1295                         plane->base.name, onoff(state), onoff(cur_state));
1296 }
1297
1298 #define assert_plane_enabled(p) assert_plane(p, true)
1299 #define assert_plane_disabled(p) assert_plane(p, false)
1300
1301 static void assert_planes_disabled(struct intel_crtc *crtc)
1302 {
1303         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1304         struct intel_plane *plane;
1305
1306         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1307                 assert_plane_disabled(plane);
1308 }
1309
1310 static void assert_vblank_disabled(struct drm_crtc *crtc)
1311 {
1312         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1313                 drm_crtc_vblank_put(crtc);
1314 }
1315
1316 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                     enum pipe pipe)
1318 {
1319         u32 val;
1320         bool enabled;
1321
1322         val = I915_READ(PCH_TRANSCONF(pipe));
1323         enabled = !!(val & TRANS_ENABLE);
1324         I915_STATE_WARN(enabled,
1325              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326              pipe_name(pipe));
1327 }
1328
1329 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1330                                    enum pipe pipe, enum port port,
1331                                    i915_reg_t dp_reg)
1332 {
1333         enum pipe port_pipe;
1334         bool state;
1335
1336         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1337
1338         I915_STATE_WARN(state && port_pipe == pipe,
1339                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1340                         port_name(port), pipe_name(pipe));
1341
1342         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1343                         "IBX PCH DP %c still using transcoder B\n",
1344                         port_name(port));
1345 }
1346
1347 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1348                                      enum pipe pipe, enum port port,
1349                                      i915_reg_t hdmi_reg)
1350 {
1351         enum pipe port_pipe;
1352         bool state;
1353
1354         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1355
1356         I915_STATE_WARN(state && port_pipe == pipe,
1357                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1358                         port_name(port), pipe_name(pipe));
1359
1360         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1361                         "IBX PCH HDMI %c still using transcoder B\n",
1362                         port_name(port));
1363 }
1364
1365 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1366                                       enum pipe pipe)
1367 {
1368         enum pipe port_pipe;
1369
1370         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1371         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1372         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1373
1374         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1375                         port_pipe == pipe,
1376                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1377                         pipe_name(pipe));
1378
1379         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1380                         port_pipe == pipe,
1381                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1382                         pipe_name(pipe));
1383
1384         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1385         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1386         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1387 }
1388
1389 static void _vlv_enable_pll(struct intel_crtc *crtc,
1390                             const struct intel_crtc_state *pipe_config)
1391 {
1392         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1393         enum pipe pipe = crtc->pipe;
1394
1395         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1396         POSTING_READ(DPLL(pipe));
1397         udelay(150);
1398
1399         if (intel_wait_for_register(dev_priv,
1400                                     DPLL(pipe),
1401                                     DPLL_LOCK_VLV,
1402                                     DPLL_LOCK_VLV,
1403                                     1))
1404                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1405 }
1406
1407 static void vlv_enable_pll(struct intel_crtc *crtc,
1408                            const struct intel_crtc_state *pipe_config)
1409 {
1410         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1411         enum pipe pipe = crtc->pipe;
1412
1413         assert_pipe_disabled(dev_priv, pipe);
1414
1415         /* PLL is protected by panel, make sure we can write it */
1416         assert_panel_unlocked(dev_priv, pipe);
1417
1418         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1419                 _vlv_enable_pll(crtc, pipe_config);
1420
1421         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1422         POSTING_READ(DPLL_MD(pipe));
1423 }
1424
1425
1426 static void _chv_enable_pll(struct intel_crtc *crtc,
1427                             const struct intel_crtc_state *pipe_config)
1428 {
1429         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1430         enum pipe pipe = crtc->pipe;
1431         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1432         u32 tmp;
1433
1434         mutex_lock(&dev_priv->sb_lock);
1435
1436         /* Enable back the 10bit clock to display controller */
1437         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1438         tmp |= DPIO_DCLKP_EN;
1439         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1440
1441         mutex_unlock(&dev_priv->sb_lock);
1442
1443         /*
1444          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1445          */
1446         udelay(1);
1447
1448         /* Enable PLL */
1449         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1450
1451         /* Check PLL is locked */
1452         if (intel_wait_for_register(dev_priv,
1453                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1454                                     1))
1455                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1456 }
1457
1458 static void chv_enable_pll(struct intel_crtc *crtc,
1459                            const struct intel_crtc_state *pipe_config)
1460 {
1461         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1462         enum pipe pipe = crtc->pipe;
1463
1464         assert_pipe_disabled(dev_priv, pipe);
1465
1466         /* PLL is protected by panel, make sure we can write it */
1467         assert_panel_unlocked(dev_priv, pipe);
1468
1469         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1470                 _chv_enable_pll(crtc, pipe_config);
1471
1472         if (pipe != PIPE_A) {
1473                 /*
1474                  * WaPixelRepeatModeFixForC0:chv
1475                  *
1476                  * DPLLCMD is AWOL. Use chicken bits to propagate
1477                  * the value from DPLLBMD to either pipe B or C.
1478                  */
1479                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1480                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1481                 I915_WRITE(CBR4_VLV, 0);
1482                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1483
1484                 /*
1485                  * DPLLB VGA mode also seems to cause problems.
1486                  * We should always have it disabled.
1487                  */
1488                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1489         } else {
1490                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1491                 POSTING_READ(DPLL_MD(pipe));
1492         }
1493 }
1494
1495 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1496 {
1497         struct intel_crtc *crtc;
1498         int count = 0;
1499
1500         for_each_intel_crtc(&dev_priv->drm, crtc) {
1501                 count += crtc->base.state->active &&
1502                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1503         }
1504
1505         return count;
1506 }
1507
1508 static void i9xx_enable_pll(struct intel_crtc *crtc,
1509                             const struct intel_crtc_state *crtc_state)
1510 {
1511         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1512         i915_reg_t reg = DPLL(crtc->pipe);
1513         u32 dpll = crtc_state->dpll_hw_state.dpll;
1514         int i;
1515
1516         assert_pipe_disabled(dev_priv, crtc->pipe);
1517
1518         /* PLL is protected by panel, make sure we can write it */
1519         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1520                 assert_panel_unlocked(dev_priv, crtc->pipe);
1521
1522         /* Enable DVO 2x clock on both PLLs if necessary */
1523         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1524                 /*
1525                  * It appears to be important that we don't enable this
1526                  * for the current pipe before otherwise configuring the
1527                  * PLL. No idea how this should be handled if multiple
1528                  * DVO outputs are enabled simultaneosly.
1529                  */
1530                 dpll |= DPLL_DVO_2X_MODE;
1531                 I915_WRITE(DPLL(!crtc->pipe),
1532                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1533         }
1534
1535         /*
1536          * Apparently we need to have VGA mode enabled prior to changing
1537          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1538          * dividers, even though the register value does change.
1539          */
1540         I915_WRITE(reg, 0);
1541
1542         I915_WRITE(reg, dpll);
1543
1544         /* Wait for the clocks to stabilize. */
1545         POSTING_READ(reg);
1546         udelay(150);
1547
1548         if (INTEL_GEN(dev_priv) >= 4) {
1549                 I915_WRITE(DPLL_MD(crtc->pipe),
1550                            crtc_state->dpll_hw_state.dpll_md);
1551         } else {
1552                 /* The pixel multiplier can only be updated once the
1553                  * DPLL is enabled and the clocks are stable.
1554                  *
1555                  * So write it again.
1556                  */
1557                 I915_WRITE(reg, dpll);
1558         }
1559
1560         /* We do this three times for luck */
1561         for (i = 0; i < 3; i++) {
1562                 I915_WRITE(reg, dpll);
1563                 POSTING_READ(reg);
1564                 udelay(150); /* wait for warmup */
1565         }
1566 }
1567
1568 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1569 {
1570         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1571         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1572         enum pipe pipe = crtc->pipe;
1573
1574         /* Disable DVO 2x clock on both PLLs if necessary */
1575         if (IS_I830(dev_priv) &&
1576             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO) &&
1577             !intel_num_dvo_pipes(dev_priv)) {
1578                 I915_WRITE(DPLL(PIPE_B),
1579                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1580                 I915_WRITE(DPLL(PIPE_A),
1581                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1582         }
1583
1584         /* Don't disable pipe or pipe PLLs if needed */
1585         if (IS_I830(dev_priv))
1586                 return;
1587
1588         /* Make sure the pipe isn't still relying on us */
1589         assert_pipe_disabled(dev_priv, pipe);
1590
1591         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1592         POSTING_READ(DPLL(pipe));
1593 }
1594
1595 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1596 {
1597         u32 val;
1598
1599         /* Make sure the pipe isn't still relying on us */
1600         assert_pipe_disabled(dev_priv, pipe);
1601
1602         val = DPLL_INTEGRATED_REF_CLK_VLV |
1603                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1604         if (pipe != PIPE_A)
1605                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1606
1607         I915_WRITE(DPLL(pipe), val);
1608         POSTING_READ(DPLL(pipe));
1609 }
1610
1611 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1612 {
1613         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1614         u32 val;
1615
1616         /* Make sure the pipe isn't still relying on us */
1617         assert_pipe_disabled(dev_priv, pipe);
1618
1619         val = DPLL_SSC_REF_CLK_CHV |
1620                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1621         if (pipe != PIPE_A)
1622                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1623
1624         I915_WRITE(DPLL(pipe), val);
1625         POSTING_READ(DPLL(pipe));
1626
1627         mutex_lock(&dev_priv->sb_lock);
1628
1629         /* Disable 10bit clock to display controller */
1630         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1631         val &= ~DPIO_DCLKP_EN;
1632         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1633
1634         mutex_unlock(&dev_priv->sb_lock);
1635 }
1636
1637 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1638                          struct intel_digital_port *dport,
1639                          unsigned int expected_mask)
1640 {
1641         u32 port_mask;
1642         i915_reg_t dpll_reg;
1643
1644         switch (dport->base.port) {
1645         case PORT_B:
1646                 port_mask = DPLL_PORTB_READY_MASK;
1647                 dpll_reg = DPLL(0);
1648                 break;
1649         case PORT_C:
1650                 port_mask = DPLL_PORTC_READY_MASK;
1651                 dpll_reg = DPLL(0);
1652                 expected_mask <<= 4;
1653                 break;
1654         case PORT_D:
1655                 port_mask = DPLL_PORTD_READY_MASK;
1656                 dpll_reg = DPIO_PHY_STATUS;
1657                 break;
1658         default:
1659                 BUG();
1660         }
1661
1662         if (intel_wait_for_register(dev_priv,
1663                                     dpll_reg, port_mask, expected_mask,
1664                                     1000))
1665                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1666                      port_name(dport->base.port),
1667                      I915_READ(dpll_reg) & port_mask, expected_mask);
1668 }
1669
1670 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1671 {
1672         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1673         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1674         enum pipe pipe = crtc->pipe;
1675         i915_reg_t reg;
1676         uint32_t val, pipeconf_val;
1677
1678         /* Make sure PCH DPLL is enabled */
1679         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1680
1681         /* FDI must be feeding us bits for PCH ports */
1682         assert_fdi_tx_enabled(dev_priv, pipe);
1683         assert_fdi_rx_enabled(dev_priv, pipe);
1684
1685         if (HAS_PCH_CPT(dev_priv)) {
1686                 /* Workaround: Set the timing override bit before enabling the
1687                  * pch transcoder. */
1688                 reg = TRANS_CHICKEN2(pipe);
1689                 val = I915_READ(reg);
1690                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1691                 I915_WRITE(reg, val);
1692         }
1693
1694         reg = PCH_TRANSCONF(pipe);
1695         val = I915_READ(reg);
1696         pipeconf_val = I915_READ(PIPECONF(pipe));
1697
1698         if (HAS_PCH_IBX(dev_priv)) {
1699                 /*
1700                  * Make the BPC in transcoder be consistent with
1701                  * that in pipeconf reg. For HDMI we must use 8bpc
1702                  * here for both 8bpc and 12bpc.
1703                  */
1704                 val &= ~PIPECONF_BPC_MASK;
1705                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1706                         val |= PIPECONF_8BPC;
1707                 else
1708                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1709         }
1710
1711         val &= ~TRANS_INTERLACE_MASK;
1712         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1713                 if (HAS_PCH_IBX(dev_priv) &&
1714                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1715                         val |= TRANS_LEGACY_INTERLACED_ILK;
1716                 else
1717                         val |= TRANS_INTERLACED;
1718         else
1719                 val |= TRANS_PROGRESSIVE;
1720
1721         I915_WRITE(reg, val | TRANS_ENABLE);
1722         if (intel_wait_for_register(dev_priv,
1723                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1724                                     100))
1725                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1726 }
1727
1728 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1729                                       enum transcoder cpu_transcoder)
1730 {
1731         u32 val, pipeconf_val;
1732
1733         /* FDI must be feeding us bits for PCH ports */
1734         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1735         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1736
1737         /* Workaround: set timing override bit. */
1738         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1739         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1741
1742         val = TRANS_ENABLE;
1743         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1744
1745         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1746             PIPECONF_INTERLACED_ILK)
1747                 val |= TRANS_INTERLACED;
1748         else
1749                 val |= TRANS_PROGRESSIVE;
1750
1751         I915_WRITE(LPT_TRANSCONF, val);
1752         if (intel_wait_for_register(dev_priv,
1753                                     LPT_TRANSCONF,
1754                                     TRANS_STATE_ENABLE,
1755                                     TRANS_STATE_ENABLE,
1756                                     100))
1757                 DRM_ERROR("Failed to enable PCH transcoder\n");
1758 }
1759
1760 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1761                                             enum pipe pipe)
1762 {
1763         i915_reg_t reg;
1764         uint32_t val;
1765
1766         /* FDI relies on the transcoder */
1767         assert_fdi_tx_disabled(dev_priv, pipe);
1768         assert_fdi_rx_disabled(dev_priv, pipe);
1769
1770         /* Ports must be off as well */
1771         assert_pch_ports_disabled(dev_priv, pipe);
1772
1773         reg = PCH_TRANSCONF(pipe);
1774         val = I915_READ(reg);
1775         val &= ~TRANS_ENABLE;
1776         I915_WRITE(reg, val);
1777         /* wait for PCH transcoder off, transcoder state */
1778         if (intel_wait_for_register(dev_priv,
1779                                     reg, TRANS_STATE_ENABLE, 0,
1780                                     50))
1781                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1782
1783         if (HAS_PCH_CPT(dev_priv)) {
1784                 /* Workaround: Clear the timing override chicken bit again. */
1785                 reg = TRANS_CHICKEN2(pipe);
1786                 val = I915_READ(reg);
1787                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1788                 I915_WRITE(reg, val);
1789         }
1790 }
1791
1792 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1793 {
1794         u32 val;
1795
1796         val = I915_READ(LPT_TRANSCONF);
1797         val &= ~TRANS_ENABLE;
1798         I915_WRITE(LPT_TRANSCONF, val);
1799         /* wait for PCH transcoder off, transcoder state */
1800         if (intel_wait_for_register(dev_priv,
1801                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1802                                     50))
1803                 DRM_ERROR("Failed to disable PCH transcoder\n");
1804
1805         /* Workaround: clear timing override bit. */
1806         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1807         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1808         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1809 }
1810
1811 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1812 {
1813         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1814
1815         if (HAS_PCH_LPT(dev_priv))
1816                 return PIPE_A;
1817         else
1818                 return crtc->pipe;
1819 }
1820
1821 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1822 {
1823         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1824         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1825         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1826         enum pipe pipe = crtc->pipe;
1827         i915_reg_t reg;
1828         u32 val;
1829
1830         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1831
1832         assert_planes_disabled(crtc);
1833
1834         /*
1835          * A pipe without a PLL won't actually be able to drive bits from
1836          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1837          * need the check.
1838          */
1839         if (HAS_GMCH_DISPLAY(dev_priv)) {
1840                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1841                         assert_dsi_pll_enabled(dev_priv);
1842                 else
1843                         assert_pll_enabled(dev_priv, pipe);
1844         } else {
1845                 if (new_crtc_state->has_pch_encoder) {
1846                         /* if driving the PCH, we need FDI enabled */
1847                         assert_fdi_rx_pll_enabled(dev_priv,
1848                                                   intel_crtc_pch_transcoder(crtc));
1849                         assert_fdi_tx_pll_enabled(dev_priv,
1850                                                   (enum pipe) cpu_transcoder);
1851                 }
1852                 /* FIXME: assert CPU port conditions for SNB+ */
1853         }
1854
1855         reg = PIPECONF(cpu_transcoder);
1856         val = I915_READ(reg);
1857         if (val & PIPECONF_ENABLE) {
1858                 /* we keep both pipes enabled on 830 */
1859                 WARN_ON(!IS_I830(dev_priv));
1860                 return;
1861         }
1862
1863         I915_WRITE(reg, val | PIPECONF_ENABLE);
1864         POSTING_READ(reg);
1865
1866         /*
1867          * Until the pipe starts PIPEDSL reads will return a stale value,
1868          * which causes an apparent vblank timestamp jump when PIPEDSL
1869          * resets to its proper value. That also messes up the frame count
1870          * when it's derived from the timestamps. So let's wait for the
1871          * pipe to start properly before we call drm_crtc_vblank_on()
1872          */
1873         if (dev_priv->drm.max_vblank_count == 0)
1874                 intel_wait_for_pipe_scanline_moving(crtc);
1875 }
1876
1877 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1878 {
1879         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1880         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1881         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1882         enum pipe pipe = crtc->pipe;
1883         i915_reg_t reg;
1884         u32 val;
1885
1886         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1887
1888         /*
1889          * Make sure planes won't keep trying to pump pixels to us,
1890          * or we might hang the display.
1891          */
1892         assert_planes_disabled(crtc);
1893
1894         reg = PIPECONF(cpu_transcoder);
1895         val = I915_READ(reg);
1896         if ((val & PIPECONF_ENABLE) == 0)
1897                 return;
1898
1899         /*
1900          * Double wide has implications for planes
1901          * so best keep it disabled when not needed.
1902          */
1903         if (old_crtc_state->double_wide)
1904                 val &= ~PIPECONF_DOUBLE_WIDE;
1905
1906         /* Don't disable pipe or pipe PLLs if needed */
1907         if (!IS_I830(dev_priv))
1908                 val &= ~PIPECONF_ENABLE;
1909
1910         I915_WRITE(reg, val);
1911         if ((val & PIPECONF_ENABLE) == 0)
1912                 intel_wait_for_pipe_off(old_crtc_state);
1913 }
1914
1915 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1916 {
1917         return IS_GEN2(dev_priv) ? 2048 : 4096;
1918 }
1919
1920 static unsigned int
1921 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1922 {
1923         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1924         unsigned int cpp = fb->format->cpp[color_plane];
1925
1926         switch (fb->modifier) {
1927         case DRM_FORMAT_MOD_LINEAR:
1928                 return cpp;
1929         case I915_FORMAT_MOD_X_TILED:
1930                 if (IS_GEN2(dev_priv))
1931                         return 128;
1932                 else
1933                         return 512;
1934         case I915_FORMAT_MOD_Y_TILED_CCS:
1935                 if (color_plane == 1)
1936                         return 128;
1937                 /* fall through */
1938         case I915_FORMAT_MOD_Y_TILED:
1939                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
1940                         return 128;
1941                 else
1942                         return 512;
1943         case I915_FORMAT_MOD_Yf_TILED_CCS:
1944                 if (color_plane == 1)
1945                         return 128;
1946                 /* fall through */
1947         case I915_FORMAT_MOD_Yf_TILED:
1948                 switch (cpp) {
1949                 case 1:
1950                         return 64;
1951                 case 2:
1952                 case 4:
1953                         return 128;
1954                 case 8:
1955                 case 16:
1956                         return 256;
1957                 default:
1958                         MISSING_CASE(cpp);
1959                         return cpp;
1960                 }
1961                 break;
1962         default:
1963                 MISSING_CASE(fb->modifier);
1964                 return cpp;
1965         }
1966 }
1967
1968 static unsigned int
1969 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
1970 {
1971         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1972                 return 1;
1973         else
1974                 return intel_tile_size(to_i915(fb->dev)) /
1975                         intel_tile_width_bytes(fb, color_plane);
1976 }
1977
1978 /* Return the tile dimensions in pixel units */
1979 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
1980                             unsigned int *tile_width,
1981                             unsigned int *tile_height)
1982 {
1983         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
1984         unsigned int cpp = fb->format->cpp[color_plane];
1985
1986         *tile_width = tile_width_bytes / cpp;
1987         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1988 }
1989
1990 unsigned int
1991 intel_fb_align_height(const struct drm_framebuffer *fb,
1992                       int color_plane, unsigned int height)
1993 {
1994         unsigned int tile_height = intel_tile_height(fb, color_plane);
1995
1996         return ALIGN(height, tile_height);
1997 }
1998
1999 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2000 {
2001         unsigned int size = 0;
2002         int i;
2003
2004         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2005                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2006
2007         return size;
2008 }
2009
2010 static void
2011 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2012                         const struct drm_framebuffer *fb,
2013                         unsigned int rotation)
2014 {
2015         view->type = I915_GGTT_VIEW_NORMAL;
2016         if (drm_rotation_90_or_270(rotation)) {
2017                 view->type = I915_GGTT_VIEW_ROTATED;
2018                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2019         }
2020 }
2021
2022 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2023 {
2024         if (IS_I830(dev_priv))
2025                 return 16 * 1024;
2026         else if (IS_I85X(dev_priv))
2027                 return 256;
2028         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2029                 return 32;
2030         else
2031                 return 4 * 1024;
2032 }
2033
2034 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2035 {
2036         if (INTEL_GEN(dev_priv) >= 9)
2037                 return 256 * 1024;
2038         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2039                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2040                 return 128 * 1024;
2041         else if (INTEL_GEN(dev_priv) >= 4)
2042                 return 4 * 1024;
2043         else
2044                 return 0;
2045 }
2046
2047 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2048                                          int color_plane)
2049 {
2050         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2051
2052         /* AUX_DIST needs only 4K alignment */
2053         if (color_plane == 1)
2054                 return 4096;
2055
2056         switch (fb->modifier) {
2057         case DRM_FORMAT_MOD_LINEAR:
2058                 return intel_linear_alignment(dev_priv);
2059         case I915_FORMAT_MOD_X_TILED:
2060                 if (INTEL_GEN(dev_priv) >= 9)
2061                         return 256 * 1024;
2062                 return 0;
2063         case I915_FORMAT_MOD_Y_TILED_CCS:
2064         case I915_FORMAT_MOD_Yf_TILED_CCS:
2065         case I915_FORMAT_MOD_Y_TILED:
2066         case I915_FORMAT_MOD_Yf_TILED:
2067                 return 1 * 1024 * 1024;
2068         default:
2069                 MISSING_CASE(fb->modifier);
2070                 return 0;
2071         }
2072 }
2073
2074 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2075 {
2076         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2077         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2078
2079         return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2080 }
2081
2082 struct i915_vma *
2083 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2084                            const struct i915_ggtt_view *view,
2085                            bool uses_fence,
2086                            unsigned long *out_flags)
2087 {
2088         struct drm_device *dev = fb->dev;
2089         struct drm_i915_private *dev_priv = to_i915(dev);
2090         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2091         struct i915_vma *vma;
2092         unsigned int pinctl;
2093         u32 alignment;
2094
2095         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2096
2097         alignment = intel_surf_alignment(fb, 0);
2098
2099         /* Note that the w/a also requires 64 PTE of padding following the
2100          * bo. We currently fill all unused PTE with the shadow page and so
2101          * we should always have valid PTE following the scanout preventing
2102          * the VT-d warning.
2103          */
2104         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2105                 alignment = 256 * 1024;
2106
2107         /*
2108          * Global gtt pte registers are special registers which actually forward
2109          * writes to a chunk of system memory. Which means that there is no risk
2110          * that the register values disappear as soon as we call
2111          * intel_runtime_pm_put(), so it is correct to wrap only the
2112          * pin/unpin/fence and not more.
2113          */
2114         intel_runtime_pm_get(dev_priv);
2115
2116         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2117
2118         pinctl = 0;
2119
2120         /* Valleyview is definitely limited to scanning out the first
2121          * 512MiB. Lets presume this behaviour was inherited from the
2122          * g4x display engine and that all earlier gen are similarly
2123          * limited. Testing suggests that it is a little more
2124          * complicated than this. For example, Cherryview appears quite
2125          * happy to scanout from anywhere within its global aperture.
2126          */
2127         if (HAS_GMCH_DISPLAY(dev_priv))
2128                 pinctl |= PIN_MAPPABLE;
2129
2130         vma = i915_gem_object_pin_to_display_plane(obj,
2131                                                    alignment, view, pinctl);
2132         if (IS_ERR(vma))
2133                 goto err;
2134
2135         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2136                 int ret;
2137
2138                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2139                  * fence, whereas 965+ only requires a fence if using
2140                  * framebuffer compression.  For simplicity, we always, when
2141                  * possible, install a fence as the cost is not that onerous.
2142                  *
2143                  * If we fail to fence the tiled scanout, then either the
2144                  * modeset will reject the change (which is highly unlikely as
2145                  * the affected systems, all but one, do not have unmappable
2146                  * space) or we will not be able to enable full powersaving
2147                  * techniques (also likely not to apply due to various limits
2148                  * FBC and the like impose on the size of the buffer, which
2149                  * presumably we violated anyway with this unmappable buffer).
2150                  * Anyway, it is presumably better to stumble onwards with
2151                  * something and try to run the system in a "less than optimal"
2152                  * mode that matches the user configuration.
2153                  */
2154                 ret = i915_vma_pin_fence(vma);
2155                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2156                         i915_gem_object_unpin_from_display_plane(vma);
2157                         vma = ERR_PTR(ret);
2158                         goto err;
2159                 }
2160
2161                 if (ret == 0 && vma->fence)
2162                         *out_flags |= PLANE_HAS_FENCE;
2163         }
2164
2165         i915_vma_get(vma);
2166 err:
2167         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2168
2169         intel_runtime_pm_put(dev_priv);
2170         return vma;
2171 }
2172
2173 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2174 {
2175         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2176
2177         if (flags & PLANE_HAS_FENCE)
2178                 i915_vma_unpin_fence(vma);
2179         i915_gem_object_unpin_from_display_plane(vma);
2180         i915_vma_put(vma);
2181 }
2182
2183 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2184                           unsigned int rotation)
2185 {
2186         if (drm_rotation_90_or_270(rotation))
2187                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2188         else
2189                 return fb->pitches[color_plane];
2190 }
2191
2192 /*
2193  * Convert the x/y offsets into a linear offset.
2194  * Only valid with 0/180 degree rotation, which is fine since linear
2195  * offset is only used with linear buffers on pre-hsw and tiled buffers
2196  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2197  */
2198 u32 intel_fb_xy_to_linear(int x, int y,
2199                           const struct intel_plane_state *state,
2200                           int color_plane)
2201 {
2202         const struct drm_framebuffer *fb = state->base.fb;
2203         unsigned int cpp = fb->format->cpp[color_plane];
2204         unsigned int pitch = state->color_plane[color_plane].stride;
2205
2206         return y * pitch + x * cpp;
2207 }
2208
2209 /*
2210  * Add the x/y offsets derived from fb->offsets[] to the user
2211  * specified plane src x/y offsets. The resulting x/y offsets
2212  * specify the start of scanout from the beginning of the gtt mapping.
2213  */
2214 void intel_add_fb_offsets(int *x, int *y,
2215                           const struct intel_plane_state *state,
2216                           int color_plane)
2217
2218 {
2219         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2220         unsigned int rotation = state->base.rotation;
2221
2222         if (drm_rotation_90_or_270(rotation)) {
2223                 *x += intel_fb->rotated[color_plane].x;
2224                 *y += intel_fb->rotated[color_plane].y;
2225         } else {
2226                 *x += intel_fb->normal[color_plane].x;
2227                 *y += intel_fb->normal[color_plane].y;
2228         }
2229 }
2230
2231 static u32 intel_adjust_tile_offset(int *x, int *y,
2232                                     unsigned int tile_width,
2233                                     unsigned int tile_height,
2234                                     unsigned int tile_size,
2235                                     unsigned int pitch_tiles,
2236                                     u32 old_offset,
2237                                     u32 new_offset)
2238 {
2239         unsigned int pitch_pixels = pitch_tiles * tile_width;
2240         unsigned int tiles;
2241
2242         WARN_ON(old_offset & (tile_size - 1));
2243         WARN_ON(new_offset & (tile_size - 1));
2244         WARN_ON(new_offset > old_offset);
2245
2246         tiles = (old_offset - new_offset) / tile_size;
2247
2248         *y += tiles / pitch_tiles * tile_height;
2249         *x += tiles % pitch_tiles * tile_width;
2250
2251         /* minimize x in case it got needlessly big */
2252         *y += *x / pitch_pixels * tile_height;
2253         *x %= pitch_pixels;
2254
2255         return new_offset;
2256 }
2257
2258 static u32 intel_adjust_aligned_offset(int *x, int *y,
2259                                        const struct drm_framebuffer *fb,
2260                                        int color_plane,
2261                                        unsigned int rotation,
2262                                        unsigned int pitch,
2263                                        u32 old_offset, u32 new_offset)
2264 {
2265         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2266         unsigned int cpp = fb->format->cpp[color_plane];
2267
2268         WARN_ON(new_offset > old_offset);
2269
2270         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2271                 unsigned int tile_size, tile_width, tile_height;
2272                 unsigned int pitch_tiles;
2273
2274                 tile_size = intel_tile_size(dev_priv);
2275                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2276
2277                 if (drm_rotation_90_or_270(rotation)) {
2278                         pitch_tiles = pitch / tile_height;
2279                         swap(tile_width, tile_height);
2280                 } else {
2281                         pitch_tiles = pitch / (tile_width * cpp);
2282                 }
2283
2284                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2285                                          tile_size, pitch_tiles,
2286                                          old_offset, new_offset);
2287         } else {
2288                 old_offset += *y * pitch + *x * cpp;
2289
2290                 *y = (old_offset - new_offset) / pitch;
2291                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2292         }
2293
2294         return new_offset;
2295 }
2296
2297 /*
2298  * Adjust the tile offset by moving the difference into
2299  * the x/y offsets.
2300  */
2301 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2302                                              const struct intel_plane_state *state,
2303                                              int color_plane,
2304                                              u32 old_offset, u32 new_offset)
2305 {
2306         return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
2307                                            state->base.rotation,
2308                                            state->color_plane[color_plane].stride,
2309                                            old_offset, new_offset);
2310 }
2311
2312 /*
2313  * Computes the aligned offset to the base tile and adjusts
2314  * x, y. bytes per pixel is assumed to be a power-of-two.
2315  *
2316  * In the 90/270 rotated case, x and y are assumed
2317  * to be already rotated to match the rotated GTT view, and
2318  * pitch is the tile_height aligned framebuffer height.
2319  *
2320  * This function is used when computing the derived information
2321  * under intel_framebuffer, so using any of that information
2322  * here is not allowed. Anything under drm_framebuffer can be
2323  * used. This is why the user has to pass in the pitch since it
2324  * is specified in the rotated orientation.
2325  */
2326 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2327                                         int *x, int *y,
2328                                         const struct drm_framebuffer *fb,
2329                                         int color_plane,
2330                                         unsigned int pitch,
2331                                         unsigned int rotation,
2332                                         u32 alignment)
2333 {
2334         uint64_t fb_modifier = fb->modifier;
2335         unsigned int cpp = fb->format->cpp[color_plane];
2336         u32 offset, offset_aligned;
2337
2338         if (alignment)
2339                 alignment--;
2340
2341         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2342                 unsigned int tile_size, tile_width, tile_height;
2343                 unsigned int tile_rows, tiles, pitch_tiles;
2344
2345                 tile_size = intel_tile_size(dev_priv);
2346                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2347
2348                 if (drm_rotation_90_or_270(rotation)) {
2349                         pitch_tiles = pitch / tile_height;
2350                         swap(tile_width, tile_height);
2351                 } else {
2352                         pitch_tiles = pitch / (tile_width * cpp);
2353                 }
2354
2355                 tile_rows = *y / tile_height;
2356                 *y %= tile_height;
2357
2358                 tiles = *x / tile_width;
2359                 *x %= tile_width;
2360
2361                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2362                 offset_aligned = offset & ~alignment;
2363
2364                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2365                                          tile_size, pitch_tiles,
2366                                          offset, offset_aligned);
2367         } else {
2368                 offset = *y * pitch + *x * cpp;
2369                 offset_aligned = offset & ~alignment;
2370
2371                 *y = (offset & alignment) / pitch;
2372                 *x = ((offset & alignment) - *y * pitch) / cpp;
2373         }
2374
2375         return offset_aligned;
2376 }
2377
2378 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2379                                               const struct intel_plane_state *state,
2380                                               int color_plane)
2381 {
2382         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2383         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2384         const struct drm_framebuffer *fb = state->base.fb;
2385         unsigned int rotation = state->base.rotation;
2386         int pitch = state->color_plane[color_plane].stride;
2387         u32 alignment;
2388
2389         if (intel_plane->id == PLANE_CURSOR)
2390                 alignment = intel_cursor_alignment(dev_priv);
2391         else
2392                 alignment = intel_surf_alignment(fb, color_plane);
2393
2394         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2395                                             pitch, rotation, alignment);
2396 }
2397
2398 /* Convert the fb->offset[] into x/y offsets */
2399 static int intel_fb_offset_to_xy(int *x, int *y,
2400                                  const struct drm_framebuffer *fb,
2401                                  int color_plane)
2402 {
2403         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2404
2405         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2406             fb->offsets[color_plane] % intel_tile_size(dev_priv))
2407                 return -EINVAL;
2408
2409         *x = 0;
2410         *y = 0;
2411
2412         intel_adjust_aligned_offset(x, y,
2413                                     fb, color_plane, DRM_MODE_ROTATE_0,
2414                                     fb->pitches[color_plane],
2415                                     fb->offsets[color_plane], 0);
2416
2417         return 0;
2418 }
2419
2420 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2421 {
2422         switch (fb_modifier) {
2423         case I915_FORMAT_MOD_X_TILED:
2424                 return I915_TILING_X;
2425         case I915_FORMAT_MOD_Y_TILED:
2426         case I915_FORMAT_MOD_Y_TILED_CCS:
2427                 return I915_TILING_Y;
2428         default:
2429                 return I915_TILING_NONE;
2430         }
2431 }
2432
2433 /*
2434  * From the Sky Lake PRM:
2435  * "The Color Control Surface (CCS) contains the compression status of
2436  *  the cache-line pairs. The compression state of the cache-line pair
2437  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2438  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2439  *  cache-line-pairs. CCS is always Y tiled."
2440  *
2441  * Since cache line pairs refers to horizontally adjacent cache lines,
2442  * each cache line in the CCS corresponds to an area of 32x16 cache
2443  * lines on the main surface. Since each pixel is 4 bytes, this gives
2444  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2445  * main surface.
2446  */
2447 static const struct drm_format_info ccs_formats[] = {
2448         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2449         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2450         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2451         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2452 };
2453
2454 static const struct drm_format_info *
2455 lookup_format_info(const struct drm_format_info formats[],
2456                    int num_formats, u32 format)
2457 {
2458         int i;
2459
2460         for (i = 0; i < num_formats; i++) {
2461                 if (formats[i].format == format)
2462                         return &formats[i];
2463         }
2464
2465         return NULL;
2466 }
2467
2468 static const struct drm_format_info *
2469 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2470 {
2471         switch (cmd->modifier[0]) {
2472         case I915_FORMAT_MOD_Y_TILED_CCS:
2473         case I915_FORMAT_MOD_Yf_TILED_CCS:
2474                 return lookup_format_info(ccs_formats,
2475                                           ARRAY_SIZE(ccs_formats),
2476                                           cmd->pixel_format);
2477         default:
2478                 return NULL;
2479         }
2480 }
2481
2482 bool is_ccs_modifier(u64 modifier)
2483 {
2484         return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2485                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2486 }
2487
2488 static int
2489 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2490                    struct drm_framebuffer *fb)
2491 {
2492         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2493         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2494         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2495         u32 gtt_offset_rotated = 0;
2496         unsigned int max_size = 0;
2497         int i, num_planes = fb->format->num_planes;
2498         unsigned int tile_size = intel_tile_size(dev_priv);
2499
2500         for (i = 0; i < num_planes; i++) {
2501                 unsigned int width, height;
2502                 unsigned int cpp, size;
2503                 u32 offset;
2504                 int x, y;
2505                 int ret;
2506
2507                 cpp = fb->format->cpp[i];
2508                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2509                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2510
2511                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2512                 if (ret) {
2513                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2514                                       i, fb->offsets[i]);
2515                         return ret;
2516                 }
2517
2518                 if (is_ccs_modifier(fb->modifier) && i == 1) {
2519                         int hsub = fb->format->hsub;
2520                         int vsub = fb->format->vsub;
2521                         int tile_width, tile_height;
2522                         int main_x, main_y;
2523                         int ccs_x, ccs_y;
2524
2525                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2526                         tile_width *= hsub;
2527                         tile_height *= vsub;
2528
2529                         ccs_x = (x * hsub) % tile_width;
2530                         ccs_y = (y * vsub) % tile_height;
2531                         main_x = intel_fb->normal[0].x % tile_width;
2532                         main_y = intel_fb->normal[0].y % tile_height;
2533
2534                         /*
2535                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2536                          * x/y offsets must match between CCS and the main surface.
2537                          */
2538                         if (main_x != ccs_x || main_y != ccs_y) {
2539                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2540                                               main_x, main_y,
2541                                               ccs_x, ccs_y,
2542                                               intel_fb->normal[0].x,
2543                                               intel_fb->normal[0].y,
2544                                               x, y);
2545                                 return -EINVAL;
2546                         }
2547                 }
2548
2549                 /*
2550                  * The fence (if used) is aligned to the start of the object
2551                  * so having the framebuffer wrap around across the edge of the
2552                  * fenced region doesn't really work. We have no API to configure
2553                  * the fence start offset within the object (nor could we probably
2554                  * on gen2/3). So it's just easier if we just require that the
2555                  * fb layout agrees with the fence layout. We already check that the
2556                  * fb stride matches the fence stride elsewhere.
2557                  */
2558                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2559                     (x + width) * cpp > fb->pitches[i]) {
2560                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2561                                       i, fb->offsets[i]);
2562                         return -EINVAL;
2563                 }
2564
2565                 /*
2566                  * First pixel of the framebuffer from
2567                  * the start of the normal gtt mapping.
2568                  */
2569                 intel_fb->normal[i].x = x;
2570                 intel_fb->normal[i].y = y;
2571
2572                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2573                                                       fb->pitches[i],
2574                                                       DRM_MODE_ROTATE_0,
2575                                                       tile_size);
2576                 offset /= tile_size;
2577
2578                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2579                         unsigned int tile_width, tile_height;
2580                         unsigned int pitch_tiles;
2581                         struct drm_rect r;
2582
2583                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2584
2585                         rot_info->plane[i].offset = offset;
2586                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2587                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2588                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2589
2590                         intel_fb->rotated[i].pitch =
2591                                 rot_info->plane[i].height * tile_height;
2592
2593                         /* how many tiles does this plane need */
2594                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2595                         /*
2596                          * If the plane isn't horizontally tile aligned,
2597                          * we need one more tile.
2598                          */
2599                         if (x != 0)
2600                                 size++;
2601
2602                         /* rotate the x/y offsets to match the GTT view */
2603                         r.x1 = x;
2604                         r.y1 = y;
2605                         r.x2 = x + width;
2606                         r.y2 = y + height;
2607                         drm_rect_rotate(&r,
2608                                         rot_info->plane[i].width * tile_width,
2609                                         rot_info->plane[i].height * tile_height,
2610                                         DRM_MODE_ROTATE_270);
2611                         x = r.x1;
2612                         y = r.y1;
2613
2614                         /* rotate the tile dimensions to match the GTT view */
2615                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2616                         swap(tile_width, tile_height);
2617
2618                         /*
2619                          * We only keep the x/y offsets, so push all of the
2620                          * gtt offset into the x/y offsets.
2621                          */
2622                         intel_adjust_tile_offset(&x, &y,
2623                                                  tile_width, tile_height,
2624                                                  tile_size, pitch_tiles,
2625                                                  gtt_offset_rotated * tile_size, 0);
2626
2627                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2628
2629                         /*
2630                          * First pixel of the framebuffer from
2631                          * the start of the rotated gtt mapping.
2632                          */
2633                         intel_fb->rotated[i].x = x;
2634                         intel_fb->rotated[i].y = y;
2635                 } else {
2636                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2637                                             x * cpp, tile_size);
2638                 }
2639
2640                 /* how many tiles in total needed in the bo */
2641                 max_size = max(max_size, offset + size);
2642         }
2643
2644         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2645                 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2646                               mul_u32_u32(max_size, tile_size), obj->base.size);
2647                 return -EINVAL;
2648         }
2649
2650         return 0;
2651 }
2652
2653 static int i9xx_format_to_fourcc(int format)
2654 {
2655         switch (format) {
2656         case DISPPLANE_8BPP:
2657                 return DRM_FORMAT_C8;
2658         case DISPPLANE_BGRX555:
2659                 return DRM_FORMAT_XRGB1555;
2660         case DISPPLANE_BGRX565:
2661                 return DRM_FORMAT_RGB565;
2662         default:
2663         case DISPPLANE_BGRX888:
2664                 return DRM_FORMAT_XRGB8888;
2665         case DISPPLANE_RGBX888:
2666                 return DRM_FORMAT_XBGR8888;
2667         case DISPPLANE_BGRX101010:
2668                 return DRM_FORMAT_XRGB2101010;
2669         case DISPPLANE_RGBX101010:
2670                 return DRM_FORMAT_XBGR2101010;
2671         }
2672 }
2673
2674 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2675 {
2676         switch (format) {
2677         case PLANE_CTL_FORMAT_RGB_565:
2678                 return DRM_FORMAT_RGB565;
2679         case PLANE_CTL_FORMAT_NV12:
2680                 return DRM_FORMAT_NV12;
2681         default:
2682         case PLANE_CTL_FORMAT_XRGB_8888:
2683                 if (rgb_order) {
2684                         if (alpha)
2685                                 return DRM_FORMAT_ABGR8888;
2686                         else
2687                                 return DRM_FORMAT_XBGR8888;
2688                 } else {
2689                         if (alpha)
2690                                 return DRM_FORMAT_ARGB8888;
2691                         else
2692                                 return DRM_FORMAT_XRGB8888;
2693                 }
2694         case PLANE_CTL_FORMAT_XRGB_2101010:
2695                 if (rgb_order)
2696                         return DRM_FORMAT_XBGR2101010;
2697                 else
2698                         return DRM_FORMAT_XRGB2101010;
2699         }
2700 }
2701
2702 static bool
2703 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2704                               struct intel_initial_plane_config *plane_config)
2705 {
2706         struct drm_device *dev = crtc->base.dev;
2707         struct drm_i915_private *dev_priv = to_i915(dev);
2708         struct drm_i915_gem_object *obj = NULL;
2709         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2710         struct drm_framebuffer *fb = &plane_config->fb->base;
2711         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2712         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2713                                     PAGE_SIZE);
2714
2715         size_aligned -= base_aligned;
2716
2717         if (plane_config->size == 0)
2718                 return false;
2719
2720         /* If the FB is too big, just don't use it since fbdev is not very
2721          * important and we should probably use that space with FBC or other
2722          * features. */
2723         if (size_aligned * 2 > dev_priv->stolen_usable_size)
2724                 return false;
2725
2726         mutex_lock(&dev->struct_mutex);
2727         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2728                                                              base_aligned,
2729                                                              base_aligned,
2730                                                              size_aligned);
2731         mutex_unlock(&dev->struct_mutex);
2732         if (!obj)
2733                 return false;
2734
2735         if (plane_config->tiling == I915_TILING_X)
2736                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2737
2738         mode_cmd.pixel_format = fb->format->format;
2739         mode_cmd.width = fb->width;
2740         mode_cmd.height = fb->height;
2741         mode_cmd.pitches[0] = fb->pitches[0];
2742         mode_cmd.modifier[0] = fb->modifier;
2743         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2744
2745         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2746                 DRM_DEBUG_KMS("intel fb init failed\n");
2747                 goto out_unref_obj;
2748         }
2749
2750
2751         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2752         return true;
2753
2754 out_unref_obj:
2755         i915_gem_object_put(obj);
2756         return false;
2757 }
2758
2759 static void
2760 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2761                         struct intel_plane_state *plane_state,
2762                         bool visible)
2763 {
2764         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2765
2766         plane_state->base.visible = visible;
2767
2768         if (visible)
2769                 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2770         else
2771                 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2772 }
2773
2774 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
2775 {
2776         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2777         struct drm_plane *plane;
2778
2779         /*
2780          * Active_planes aliases if multiple "primary" or cursor planes
2781          * have been used on the same (or wrong) pipe. plane_mask uses
2782          * unique ids, hence we can use that to reconstruct active_planes.
2783          */
2784         crtc_state->active_planes = 0;
2785
2786         drm_for_each_plane_mask(plane, &dev_priv->drm,
2787                                 crtc_state->base.plane_mask)
2788                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
2789 }
2790
2791 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2792                                          struct intel_plane *plane)
2793 {
2794         struct intel_crtc_state *crtc_state =
2795                 to_intel_crtc_state(crtc->base.state);
2796         struct intel_plane_state *plane_state =
2797                 to_intel_plane_state(plane->base.state);
2798
2799         DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
2800                       plane->base.base.id, plane->base.name,
2801                       crtc->base.base.id, crtc->base.name);
2802
2803         intel_set_plane_visible(crtc_state, plane_state, false);
2804         fixup_active_planes(crtc_state);
2805
2806         if (plane->id == PLANE_PRIMARY)
2807                 intel_pre_disable_primary_noatomic(&crtc->base);
2808
2809         trace_intel_disable_plane(&plane->base, crtc);
2810         plane->disable_plane(plane, crtc);
2811 }
2812
2813 static void
2814 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2815                              struct intel_initial_plane_config *plane_config)
2816 {
2817         struct drm_device *dev = intel_crtc->base.dev;
2818         struct drm_i915_private *dev_priv = to_i915(dev);
2819         struct drm_crtc *c;
2820         struct drm_i915_gem_object *obj;
2821         struct drm_plane *primary = intel_crtc->base.primary;
2822         struct drm_plane_state *plane_state = primary->state;
2823         struct intel_plane *intel_plane = to_intel_plane(primary);
2824         struct intel_plane_state *intel_state =
2825                 to_intel_plane_state(plane_state);
2826         struct drm_framebuffer *fb;
2827
2828         if (!plane_config->fb)
2829                 return;
2830
2831         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2832                 fb = &plane_config->fb->base;
2833                 goto valid_fb;
2834         }
2835
2836         kfree(plane_config->fb);
2837
2838         /*
2839          * Failed to alloc the obj, check to see if we should share
2840          * an fb with another CRTC instead
2841          */
2842         for_each_crtc(dev, c) {
2843                 struct intel_plane_state *state;
2844
2845                 if (c == &intel_crtc->base)
2846                         continue;
2847
2848                 if (!to_intel_crtc(c)->active)
2849                         continue;
2850
2851                 state = to_intel_plane_state(c->primary->state);
2852                 if (!state->vma)
2853                         continue;
2854
2855                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2856                         fb = state->base.fb;
2857                         drm_framebuffer_get(fb);
2858                         goto valid_fb;
2859                 }
2860         }
2861
2862         /*
2863          * We've failed to reconstruct the BIOS FB.  Current display state
2864          * indicates that the primary plane is visible, but has a NULL FB,
2865          * which will lead to problems later if we don't fix it up.  The
2866          * simplest solution is to just disable the primary plane now and
2867          * pretend the BIOS never had it enabled.
2868          */
2869         intel_plane_disable_noatomic(intel_crtc, intel_plane);
2870
2871         return;
2872
2873 valid_fb:
2874         intel_fill_fb_ggtt_view(&intel_state->view, fb,
2875                                 intel_state->base.rotation);
2876         intel_state->color_plane[0].stride =
2877                 intel_fb_pitch(fb, 0, intel_state->base.rotation);
2878
2879         mutex_lock(&dev->struct_mutex);
2880         intel_state->vma =
2881                 intel_pin_and_fence_fb_obj(fb,
2882                                            &intel_state->view,
2883                                            intel_plane_uses_fence(intel_state),
2884                                            &intel_state->flags);
2885         mutex_unlock(&dev->struct_mutex);
2886         if (IS_ERR(intel_state->vma)) {
2887                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2888                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2889
2890                 intel_state->vma = NULL;
2891                 drm_framebuffer_put(fb);
2892                 return;
2893         }
2894
2895         obj = intel_fb_obj(fb);
2896         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2897
2898         plane_state->src_x = 0;
2899         plane_state->src_y = 0;
2900         plane_state->src_w = fb->width << 16;
2901         plane_state->src_h = fb->height << 16;
2902
2903         plane_state->crtc_x = 0;
2904         plane_state->crtc_y = 0;
2905         plane_state->crtc_w = fb->width;
2906         plane_state->crtc_h = fb->height;
2907
2908         intel_state->base.src = drm_plane_state_src(plane_state);
2909         intel_state->base.dst = drm_plane_state_dest(plane_state);
2910
2911         if (i915_gem_object_is_tiled(obj))
2912                 dev_priv->preserve_bios_swizzle = true;
2913
2914         plane_state->fb = fb;
2915         plane_state->crtc = &intel_crtc->base;
2916
2917         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2918                   &obj->frontbuffer_bits);
2919 }
2920
2921 static int skl_max_plane_width(const struct drm_framebuffer *fb,
2922                                int color_plane,
2923                                unsigned int rotation)
2924 {
2925         int cpp = fb->format->cpp[color_plane];
2926
2927         switch (fb->modifier) {
2928         case DRM_FORMAT_MOD_LINEAR:
2929         case I915_FORMAT_MOD_X_TILED:
2930                 switch (cpp) {
2931                 case 8:
2932                         return 4096;
2933                 case 4:
2934                 case 2:
2935                 case 1:
2936                         return 8192;
2937                 default:
2938                         MISSING_CASE(cpp);
2939                         break;
2940                 }
2941                 break;
2942         case I915_FORMAT_MOD_Y_TILED_CCS:
2943         case I915_FORMAT_MOD_Yf_TILED_CCS:
2944                 /* FIXME AUX plane? */
2945         case I915_FORMAT_MOD_Y_TILED:
2946         case I915_FORMAT_MOD_Yf_TILED:
2947                 switch (cpp) {
2948                 case 8:
2949                         return 2048;
2950                 case 4:
2951                         return 4096;
2952                 case 2:
2953                 case 1:
2954                         return 8192;
2955                 default:
2956                         MISSING_CASE(cpp);
2957                         break;
2958                 }
2959                 break;
2960         default:
2961                 MISSING_CASE(fb->modifier);
2962         }
2963
2964         return 2048;
2965 }
2966
2967 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2968                                            int main_x, int main_y, u32 main_offset)
2969 {
2970         const struct drm_framebuffer *fb = plane_state->base.fb;
2971         int hsub = fb->format->hsub;
2972         int vsub = fb->format->vsub;
2973         int aux_x = plane_state->color_plane[1].x;
2974         int aux_y = plane_state->color_plane[1].y;
2975         u32 aux_offset = plane_state->color_plane[1].offset;
2976         u32 alignment = intel_surf_alignment(fb, 1);
2977
2978         while (aux_offset >= main_offset && aux_y <= main_y) {
2979                 int x, y;
2980
2981                 if (aux_x == main_x && aux_y == main_y)
2982                         break;
2983
2984                 if (aux_offset == 0)
2985                         break;
2986
2987                 x = aux_x / hsub;
2988                 y = aux_y / vsub;
2989                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
2990                                                                aux_offset, aux_offset - alignment);
2991                 aux_x = x * hsub + aux_x % hsub;
2992                 aux_y = y * vsub + aux_y % vsub;
2993         }
2994
2995         if (aux_x != main_x || aux_y != main_y)
2996                 return false;
2997
2998         plane_state->color_plane[1].offset = aux_offset;
2999         plane_state->color_plane[1].x = aux_x;
3000         plane_state->color_plane[1].y = aux_y;
3001
3002         return true;
3003 }
3004
3005 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3006 {
3007         const struct drm_framebuffer *fb = plane_state->base.fb;
3008         unsigned int rotation = plane_state->base.rotation;
3009         int x = plane_state->base.src.x1 >> 16;
3010         int y = plane_state->base.src.y1 >> 16;
3011         int w = drm_rect_width(&plane_state->base.src) >> 16;
3012         int h = drm_rect_height(&plane_state->base.src) >> 16;
3013         int max_width = skl_max_plane_width(fb, 0, rotation);
3014         int max_height = 4096;
3015         u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3016
3017         if (w > max_width || h > max_height) {
3018                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3019                               w, h, max_width, max_height);
3020                 return -EINVAL;
3021         }
3022
3023         intel_add_fb_offsets(&x, &y, plane_state, 0);
3024         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);