drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include "drmP.h"
  29 #include "intel_drv.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32
  33 #include "drm_crtc_helper.h"
  34
  35 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  36
  37 typedef struct {
  38     /* given values */
  39     int n;
  40     int m1, m2;
  41     int p1, p2;
  42     /* derived values */
  43     int dot;
  44     int vco;
  45     int m;
  46     int p;
  47 } intel_clock_t;
  48
  49 typedef struct {
  50     int min, max;
  51 } intel_range_t;
  52
  53 typedef struct {
  54     int dot_limit;
  55     int p2_slow, p2_fast;
  56 } intel_p2_t;
  57
  58 #define INTEL_P2_NUM                  2
  59 typedef struct intel_limit intel_limit_t;
  60 struct intel_limit {
  61     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  62     intel_p2_t      p2;
  63     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  64                       int, int, intel_clock_t *);
  65 };
  66
  67 #define I8XX_DOT_MIN              25000
  68 #define I8XX_DOT_MAX             350000
  69 #define I8XX_VCO_MIN             930000
  70 #define I8XX_VCO_MAX            1400000
  71 #define I8XX_N_MIN                    3
  72 #define I8XX_N_MAX                   16
  73 #define I8XX_M_MIN                   96
  74 #define I8XX_M_MAX                  140
  75 #define I8XX_M1_MIN                  18
  76 #define I8XX_M1_MAX                  26
  77 #define I8XX_M2_MIN                   6
  78 #define I8XX_M2_MAX                  16
  79 #define I8XX_P_MIN                    4
  80 #define I8XX_P_MAX                  128
  81 #define I8XX_P1_MIN                   2
  82 #define I8XX_P1_MAX                  33
  83 #define I8XX_P1_LVDS_MIN              1
  84 #define I8XX_P1_LVDS_MAX              6
  85 #define I8XX_P2_SLOW                  4
  86 #define I8XX_P2_FAST                  2
  87 #define I8XX_P2_LVDS_SLOW             14
  88 #define I8XX_P2_LVDS_FAST             14 /* No fast option */
  89 #define I8XX_P2_SLOW_LIMIT       165000
  90
  91 #define I9XX_DOT_MIN              20000
  92 #define I9XX_DOT_MAX             400000
  93 #define I9XX_VCO_MIN            1400000
  94 #define I9XX_VCO_MAX            2800000
  95 #define IGD_VCO_MIN             1700000
  96 #define IGD_VCO_MAX             3500000
  97 #define I9XX_N_MIN                    1
  98 #define I9XX_N_MAX                    6
  99 /* IGD's Ncounter is a ring counter */
 100 #define IGD_N_MIN                     3
 101 #define IGD_N_MAX                     6
 102 #define I9XX_M_MIN                   70
 103 #define I9XX_M_MAX                  120
 104 #define IGD_M_MIN                     2
 105 #define IGD_M_MAX                   256
 106 #define I9XX_M1_MIN                  10
 107 #define I9XX_M1_MAX                  22
 108 #define I9XX_M2_MIN                   5
 109 #define I9XX_M2_MAX                   9
 110 /* IGD M1 is reserved, and must be 0 */
 111 #define IGD_M1_MIN                    0
 112 #define IGD_M1_MAX                    0
 113 #define IGD_M2_MIN                    0
 114 #define IGD_M2_MAX                    254
 115 #define I9XX_P_SDVO_DAC_MIN           5
 116 #define I9XX_P_SDVO_DAC_MAX          80
 117 #define I9XX_P_LVDS_MIN               7
 118 #define I9XX_P_LVDS_MAX              98
 119 #define IGD_P_LVDS_MIN                7
 120 #define IGD_P_LVDS_MAX               112
 121 #define I9XX_P1_MIN                   1
 122 #define I9XX_P1_MAX                   8
 123 #define I9XX_P2_SDVO_DAC_SLOW                10
 124 #define I9XX_P2_SDVO_DAC_FAST                 5
 125 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 126 #define I9XX_P2_LVDS_SLOW                    14
 127 #define I9XX_P2_LVDS_FAST                     7
 128 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 129
 130 #define INTEL_LIMIT_I8XX_DVO_DAC    0
 131 #define INTEL_LIMIT_I8XX_LVDS       1
 132 #define INTEL_LIMIT_I9XX_SDVO_DAC   2
 133 #define INTEL_LIMIT_I9XX_LVDS       3
 134 #define INTEL_LIMIT_G4X_SDVO        4
 135 #define INTEL_LIMIT_G4X_HDMI_DAC   5
 136 #define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS   6
 137 #define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS   7
 138 #define INTEL_LIMIT_IGD_SDVO_DAC    8
 139 #define INTEL_LIMIT_IGD_LVDS        9
 140
 141 /*The parameter is for SDVO on G4x platform*/
 142 #define G4X_DOT_SDVO_MIN           25000
 143 #define G4X_DOT_SDVO_MAX           270000
 144 #define G4X_VCO_MIN                1750000
 145 #define G4X_VCO_MAX                3500000
 146 #define G4X_N_SDVO_MIN             1
 147 #define G4X_N_SDVO_MAX             4
 148 #define G4X_M_SDVO_MIN             104
 149 #define G4X_M_SDVO_MAX             138
 150 #define G4X_M1_SDVO_MIN            17
 151 #define G4X_M1_SDVO_MAX            23
 152 #define G4X_M2_SDVO_MIN            5
 153 #define G4X_M2_SDVO_MAX            11
 154 #define G4X_P_SDVO_MIN             10
 155 #define G4X_P_SDVO_MAX             30
 156 #define G4X_P1_SDVO_MIN            1
 157 #define G4X_P1_SDVO_MAX            3
 158 #define G4X_P2_SDVO_SLOW           10
 159 #define G4X_P2_SDVO_FAST           10
 160 #define G4X_P2_SDVO_LIMIT          270000
 161
 162 /*The parameter is for HDMI_DAC on G4x platform*/
 163 #define G4X_DOT_HDMI_DAC_MIN           22000
 164 #define G4X_DOT_HDMI_DAC_MAX           400000
 165 #define G4X_N_HDMI_DAC_MIN             1
 166 #define G4X_N_HDMI_DAC_MAX             4
 167 #define G4X_M_HDMI_DAC_MIN             104
 168 #define G4X_M_HDMI_DAC_MAX             138
 169 #define G4X_M1_HDMI_DAC_MIN            16
 170 #define G4X_M1_HDMI_DAC_MAX            23
 171 #define G4X_M2_HDMI_DAC_MIN            5
 172 #define G4X_M2_HDMI_DAC_MAX            11
 173 #define G4X_P_HDMI_DAC_MIN             5
 174 #define G4X_P_HDMI_DAC_MAX             80
 175 #define G4X_P1_HDMI_DAC_MIN            1
 176 #define G4X_P1_HDMI_DAC_MAX            8
 177 #define G4X_P2_HDMI_DAC_SLOW           10
 178 #define G4X_P2_HDMI_DAC_FAST           5
 179 #define G4X_P2_HDMI_DAC_LIMIT          165000
 180
 181 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 199
 200 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 218
 219 static bool
 220 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 221                     int target, int refclk, intel_clock_t *best_clock);
 222 static bool
 223 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 224                         int target, int refclk, intel_clock_t *best_clock);
 225
 226 static const intel_limit_t intel_limits[] = {
 227     { /* INTEL_LIMIT_I8XX_DVO_DAC */
 228         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 229         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 230         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 231         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 232         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 233         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 234         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 235         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 236         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 237                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 238         .find_pll = intel_find_best_PLL,
 239     },
 240     { /* INTEL_LIMIT_I8XX_LVDS */
 241         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 242         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 243         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 244         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 245         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 246         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 247         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 248         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 249         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 250                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 251         .find_pll = intel_find_best_PLL,
 252     },
 253     { /* INTEL_LIMIT_I9XX_SDVO_DAC */
 254         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 255         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 256         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 257         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 258         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 259         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 260         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 261         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 262         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 263                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 264         .find_pll = intel_find_best_PLL,
 265     },
 266     { /* INTEL_LIMIT_I9XX_LVDS */
 267         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 268         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 269         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 270         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 271         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 272         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 273         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 274         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 275         /* The single-channel range is 25-112Mhz, and dual-channel
 276          * is 80-224Mhz.  Prefer single channel as much as possible.
 277          */
 278         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 279                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 280         .find_pll = intel_find_best_PLL,
 281     },
 282     /* below parameter and function is for G4X Chipset Family*/
 283     { /* INTEL_LIMIT_G4X_SDVO */
 284         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 285         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 286         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 287         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 288         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 289         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 290         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 291         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 292         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 293                  .p2_slow = G4X_P2_SDVO_SLOW,
 294                  .p2_fast = G4X_P2_SDVO_FAST
 295         },
 296         .find_pll = intel_g4x_find_best_PLL,
 297     },
 298     { /* INTEL_LIMIT_G4X_HDMI_DAC */
 299         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 300         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 301         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 302         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 303         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 304         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 305         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 306         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 307         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 308                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 309                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 310         },
 311         .find_pll = intel_g4x_find_best_PLL,
 312     },
 313     { /* INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS */
 314         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 315                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 316         .vco = { .min = G4X_VCO_MIN,
 317                  .max = G4X_VCO_MAX },
 318         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 319                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 320         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 321                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 322         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 323                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 324         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 325                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 326         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 327                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 328         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 329                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 330         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 331                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 332                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 333         },
 334         .find_pll = intel_g4x_find_best_PLL,
 335     },
 336     { /* INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS */
 337         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 338                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 339         .vco = { .min = G4X_VCO_MIN,
 340                  .max = G4X_VCO_MAX },
 341         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 342                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 343         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 344                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 345         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 346                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 347         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 348                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 349         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 350                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 351         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 352                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 353         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 354                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 355                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 356         },
 357         .find_pll = intel_g4x_find_best_PLL,
 358     },
 359     { /* INTEL_LIMIT_IGD_SDVO */
 360         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 361         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 362         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 363         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 364         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 365         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 366         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 367         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 368         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 369                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 370         .find_pll = intel_find_best_PLL,
 371     },
 372     { /* INTEL_LIMIT_IGD_LVDS */
 373         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 374         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 375         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 376         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 377         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 378         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 379         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 380         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 381         /* IGD only supports single-channel mode. */
 382         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 383                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 384         .find_pll = intel_find_best_PLL,
 385     },
 386
 387 };
 388
 389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 390 {
 391         struct drm_device *dev = crtc->dev;
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         const intel_limit_t *limit;
 394
 395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 396                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 397                     LVDS_CLKB_POWER_UP)
 398                         /* LVDS with dual channel */
 399                         limit = &intel_limits
 400                                         [INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS];
 401                 else
 402                         /* LVDS with dual channel */
 403                         limit = &intel_limits
 404                                         [INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS];
 405         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 406                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 407                 limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC];
 408         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 409                 limit = &intel_limits[INTEL_LIMIT_G4X_SDVO];
 410         } else /* The option is for other outputs */
 411                 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
 412
 413         return limit;
 414 }
 415
 416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 417 {
 418         struct drm_device *dev = crtc->dev;
 419         const intel_limit_t *limit;
 420
 421         if (IS_G4X(dev)) {
 422                 limit = intel_g4x_limit(crtc);
 423         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 424                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 425                         limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
 426                 else
 427                         limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
 428         } else if (IS_IGD(dev)) {
 429                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 430                         limit = &intel_limits[INTEL_LIMIT_IGD_LVDS];
 431                 else
 432                         limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC];
 433         } else {
 434                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 435                         limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
 436                 else
 437                         limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
 438         }
 439         return limit;
 440 }
 441
 442 /* m1 is reserved as 0 in IGD, n is a ring counter */
 443 static void igd_clock(int refclk, intel_clock_t *clock)
 444 {
 445         clock->m = clock->m2 + 2;
 446         clock->p = clock->p1 * clock->p2;
 447         clock->vco = refclk * clock->m / clock->n;
 448         clock->dot = clock->vco / clock->p;
 449 }
 450
 451 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 452 {
 453         if (IS_IGD(dev)) {
 454                 igd_clock(refclk, clock);
 455                 return;
 456         }
 457         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 458         clock->p = clock->p1 * clock->p2;
 459         clock->vco = refclk * clock->m / (clock->n + 2);
 460         clock->dot = clock->vco / clock->p;
 461 }
 462
 463 /**
 464  * Returns whether any output on the specified pipe is of the specified type
 465  */
 466 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 467 {
 468     struct drm_device *dev = crtc->dev;
 469     struct drm_mode_config *mode_config = &dev->mode_config;
 470     struct drm_connector *l_entry;
 471
 472     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 473             if (l_entry->encoder &&
 474                 l_entry->encoder->crtc == crtc) {
 475                     struct intel_output *intel_output = to_intel_output(l_entry);
 476                     if (intel_output->type == type)
 477                             return true;
 478             }
 479     }
 480     return false;
 481 }
 482
 483 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 484 /**
 485  * Returns whether the given set of divisors are valid for a given refclk with
 486  * the given connectors.
 487  */
 488
 489 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 490 {
 491         const intel_limit_t *limit = intel_limit (crtc);
 492         struct drm_device *dev = crtc->dev;
 493
 494         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 495                 INTELPllInvalid ("p1 out of range\n");
 496         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 497                 INTELPllInvalid ("p out of range\n");
 498         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 499                 INTELPllInvalid ("m2 out of range\n");
 500         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 501                 INTELPllInvalid ("m1 out of range\n");
 502         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 503                 INTELPllInvalid ("m1 <= m2\n");
 504         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 505                 INTELPllInvalid ("m out of range\n");
 506         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 507                 INTELPllInvalid ("n out of range\n");
 508         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 509                 INTELPllInvalid ("vco out of range\n");
 510         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 511          * connector, etc., rather than just a single range.
 512          */
 513         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 514                 INTELPllInvalid ("dot out of range\n");
 515
 516         return true;
 517 }
 518
 519 static bool
 520 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 521                     int target, int refclk, intel_clock_t *best_clock)
 522
 523 {
 524         struct drm_device *dev = crtc->dev;
 525         struct drm_i915_private *dev_priv = dev->dev_private;
 526         intel_clock_t clock;
 527         int err = target;
 528
 529         if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 530             (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
 531                 /*
 532                  * For LVDS, if the panel is on, just rely on its current
 533                  * settings for dual-channel.  We haven't figured out how to
 534                  * reliably set up different single/dual channel state, if we
 535                  * even can.
 536                  */
 537                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 538                     LVDS_CLKB_POWER_UP)
 539                         clock.p2 = limit->p2.p2_fast;
 540                 else
 541                         clock.p2 = limit->p2.p2_slow;
 542         } else {
 543                 if (target < limit->p2.dot_limit)
 544                         clock.p2 = limit->p2.p2_slow;
 545                 else
 546                         clock.p2 = limit->p2.p2_fast;
 547         }
 548
 549         memset (best_clock, 0, sizeof (*best_clock));
 550
 551         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 552                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 553                         /* m1 is always 0 in IGD */
 554                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 555                                 break;
 556                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 557                              clock.n++) {
 558                                 for (clock.p1 = limit->p1.min;
 559                                      clock.p1 <= limit->p1.max; clock.p1++) {
 560                                         int this_err;
 561
 562                                         intel_clock(dev, refclk, &clock);
 563
 564                                         if (!intel_PLL_is_valid(crtc, &clock))
 565                                                 continue;
 566
 567                                         this_err = abs(clock.dot - target);
 568                                         if (this_err < err) {
 569                                                 *best_clock = clock;
 570                                                 err = this_err;
 571                                         }
 572                                 }
 573                         }
 574                 }
 575         }
 576
 577         return (err != target);
 578 }
 579
 580 static bool
 581 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 582                         int target, int refclk, intel_clock_t *best_clock)
 583 {
 584         struct drm_device *dev = crtc->dev;
 585         struct drm_i915_private *dev_priv = dev->dev_private;
 586         intel_clock_t clock;
 587         int max_n;
 588         bool found;
 589         /* approximately equals target * 0.00488 */
 590         int err_most = (target >> 8) + (target >> 10);
 591         found = false;
 592
 593         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 594                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 595                     LVDS_CLKB_POWER_UP)
 596                         clock.p2 = limit->p2.p2_fast;
 597                 else
 598                         clock.p2 = limit->p2.p2_slow;
 599         } else {
 600                 if (target < limit->p2.dot_limit)
 601                         clock.p2 = limit->p2.p2_slow;
 602                 else
 603                         clock.p2 = limit->p2.p2_fast;
 604         }
 605
 606         memset(best_clock, 0, sizeof(*best_clock));
 607         max_n = limit->n.max;
 608         /* based on hardware requriment prefer smaller n to precision */
 609         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 610                 /* based on hardware requirment prefere larger m1,m2, p1 */
 611                 for (clock.m1 = limit->m1.max;
 612                      clock.m1 >= limit->m1.min; clock.m1--) {
 613                         for (clock.m2 = limit->m2.max;
 614                              clock.m2 >= limit->m2.min; clock.m2--) {
 615                                 for (clock.p1 = limit->p1.max;
 616                                      clock.p1 >= limit->p1.min; clock.p1--) {
 617                                         int this_err;
 618
 619                                         intel_clock(dev, refclk, &clock);
 620                                         if (!intel_PLL_is_valid(crtc, &clock))
 621                                                 continue;
 622                                         this_err = abs(clock.dot - target) ;
 623                                         if (this_err < err_most) {
 624                                                 *best_clock = clock;
 625                                                 err_most = this_err;
 626                                                 max_n = clock.n;
 627                                                 found = true;
 628                                         }
 629                                 }
 630                         }
 631                 }
 632         }
 633
 634         return found;
 635 }
 636
 637 void
 638 intel_wait_for_vblank(struct drm_device *dev)
 639 {
 640         /* Wait for 20ms, i.e. one cycle at 50hz. */
 641         mdelay(20);
 642 }
 643
 644 static int
 645 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 646                     struct drm_framebuffer *old_fb)
 647 {
 648         struct drm_device *dev = crtc->dev;
 649         struct drm_i915_private *dev_priv = dev->dev_private;
 650         struct drm_i915_master_private *master_priv;
 651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 652         struct intel_framebuffer *intel_fb;
 653         struct drm_i915_gem_object *obj_priv;
 654         struct drm_gem_object *obj;
 655         int pipe = intel_crtc->pipe;
 656         unsigned long Start, Offset;
 657         int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
 658         int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
 659         int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
 660         int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
 661         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 662         u32 dspcntr, alignment;
 663         int ret;
 664
 665         /* no fb bound */
 666         if (!crtc->fb) {
 667                 DRM_DEBUG("No FB bound\n");
 668                 return 0;
 669         }
 670
 671         switch (pipe) {
 672         case 0:
 673         case 1:
 674                 break;
 675         default:
 676                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 677                 return -EINVAL;
 678         }
 679
 680         intel_fb = to_intel_framebuffer(crtc->fb);
 681         obj = intel_fb->obj;
 682         obj_priv = obj->driver_private;
 683
 684         switch (obj_priv->tiling_mode) {
 685         case I915_TILING_NONE:
 686                 alignment = 64 * 1024;
 687                 break;
 688         case I915_TILING_X:
 689                 /* pin() will align the object as required by fence */
 690                 alignment = 0;
 691                 break;
 692         case I915_TILING_Y:
 693                 /* FIXME: Is this true? */
 694                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
 695                 return -EINVAL;
 696         default:
 697                 BUG();
 698         }
 699
 700         mutex_lock(&dev->struct_mutex);
 701         ret = i915_gem_object_pin(intel_fb->obj, alignment);
 702         if (ret != 0) {
 703                 mutex_unlock(&dev->struct_mutex);
 704                 return ret;
 705         }
 706
 707         ret = i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1);
 708         if (ret != 0) {
 709                 i915_gem_object_unpin(intel_fb->obj);
 710                 mutex_unlock(&dev->struct_mutex);
 711                 return ret;
 712         }
 713
 714         dspcntr = I915_READ(dspcntr_reg);
 715         /* Mask out pixel format bits in case we change it */
 716         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 717         switch (crtc->fb->bits_per_pixel) {
 718         case 8:
 719                 dspcntr |= DISPPLANE_8BPP;
 720                 break;
 721         case 16:
 722                 if (crtc->fb->depth == 15)
 723                         dspcntr |= DISPPLANE_15_16BPP;
 724                 else
 725                         dspcntr |= DISPPLANE_16BPP;
 726                 break;
 727         case 24:
 728         case 32:
 729                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 730                 break;
 731         default:
 732                 DRM_ERROR("Unknown color depth\n");
 733                 i915_gem_object_unpin(intel_fb->obj);
 734                 mutex_unlock(&dev->struct_mutex);
 735                 return -EINVAL;
 736         }
 737         if (IS_I965G(dev)) {
 738                 if (obj_priv->tiling_mode != I915_TILING_NONE)
 739                         dspcntr |= DISPPLANE_TILED;
 740                 else
 741                         dspcntr &= ~DISPPLANE_TILED;
 742         }
 743
 744         I915_WRITE(dspcntr_reg, dspcntr);
 745
 746         Start = obj_priv->gtt_offset;
 747         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
 748
 749         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
 750         I915_WRITE(dspstride, crtc->fb->pitch);
 751         if (IS_I965G(dev)) {
 752                 I915_WRITE(dspbase, Offset);
 753                 I915_READ(dspbase);
 754                 I915_WRITE(dspsurf, Start);
 755                 I915_READ(dspsurf);
 756                 I915_WRITE(dsptileoff, (y << 16) | x);
 757         } else {
 758                 I915_WRITE(dspbase, Start + Offset);
 759                 I915_READ(dspbase);
 760         }
 761
 762         intel_wait_for_vblank(dev);
 763
 764         if (old_fb) {
 765                 intel_fb = to_intel_framebuffer(old_fb);
 766                 i915_gem_object_unpin(intel_fb->obj);
 767         }
 768         mutex_unlock(&dev->struct_mutex);
 769
 770         if (!dev->primary->master)
 771                 return 0;
 772
 773         master_priv = dev->primary->master->driver_priv;
 774         if (!master_priv->sarea_priv)
 775                 return 0;
 776
 777         if (pipe) {
 778                 master_priv->sarea_priv->pipeB_x = x;
 779                 master_priv->sarea_priv->pipeB_y = y;
 780         } else {
 781                 master_priv->sarea_priv->pipeA_x = x;
 782                 master_priv->sarea_priv->pipeA_y = y;
 783         }
 784
 785         return 0;
 786 }
 787
 788
 789
 790 /**
 791  * Sets the power management mode of the pipe and plane.
 792  *
 793  * This code should probably grow support for turning the cursor off and back
 794  * on appropriately at the same time as we're turning the pipe off/on.
 795  */
 796 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
 797 {
 798         struct drm_device *dev = crtc->dev;
 799         struct drm_i915_master_private *master_priv;
 800         struct drm_i915_private *dev_priv = dev->dev_private;
 801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 802         int pipe = intel_crtc->pipe;
 803         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
 804         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 805         int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
 806         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 807         u32 temp;
 808         bool enabled;
 809
 810         /* XXX: When our outputs are all unaware of DPMS modes other than off
 811          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 812          */
 813         switch (mode) {
 814         case DRM_MODE_DPMS_ON:
 815         case DRM_MODE_DPMS_STANDBY:
 816         case DRM_MODE_DPMS_SUSPEND:
 817                 /* Enable the DPLL */
 818                 temp = I915_READ(dpll_reg);
 819                 if ((temp & DPLL_VCO_ENABLE) == 0) {
 820                         I915_WRITE(dpll_reg, temp);
 821                         I915_READ(dpll_reg);
 822                         /* Wait for the clocks to stabilize. */
 823                         udelay(150);
 824                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
 825                         I915_READ(dpll_reg);
 826                         /* Wait for the clocks to stabilize. */
 827                         udelay(150);
 828                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
 829                         I915_READ(dpll_reg);
 830                         /* Wait for the clocks to stabilize. */
 831                         udelay(150);
 832                 }
 833
 834                 /* Enable the pipe */
 835                 temp = I915_READ(pipeconf_reg);
 836                 if ((temp & PIPEACONF_ENABLE) == 0)
 837                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
 838
 839                 /* Enable the plane */
 840                 temp = I915_READ(dspcntr_reg);
 841                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
 842                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
 843                         /* Flush the plane changes */
 844                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
 845                 }
 846
 847                 intel_crtc_load_lut(crtc);
 848
 849                 /* Give the overlay scaler a chance to enable if it's on this pipe */
 850                 //intel_crtc_dpms_video(crtc, true); TODO
 851         break;
 852         case DRM_MODE_DPMS_OFF:
 853                 /* Give the overlay scaler a chance to disable if it's on this pipe */
 854                 //intel_crtc_dpms_video(crtc, FALSE); TODO
 855
 856                 /* Disable the VGA plane that we never use */
 857                 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
 858
 859                 /* Disable display plane */
 860                 temp = I915_READ(dspcntr_reg);
 861                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
 862                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
 863                         /* Flush the plane changes */
 864                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
 865                         I915_READ(dspbase_reg);
 866                 }
 867
 868                 if (!IS_I9XX(dev)) {
 869                         /* Wait for vblank for the disable to take effect */
 870                         intel_wait_for_vblank(dev);
 871                 }
 872
 873                 /* Next, disable display pipes */
 874                 temp = I915_READ(pipeconf_reg);
 875                 if ((temp & PIPEACONF_ENABLE) != 0) {
 876                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
 877                         I915_READ(pipeconf_reg);
 878                 }
 879
 880                 /* Wait for vblank for the disable to take effect. */
 881                 intel_wait_for_vblank(dev);
 882
 883                 temp = I915_READ(dpll_reg);
 884                 if ((temp & DPLL_VCO_ENABLE) != 0) {
 885                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
 886                         I915_READ(dpll_reg);
 887                 }
 888
 889                 /* Wait for the clocks to turn off. */
 890                 udelay(150);
 891                 break;
 892         }
 893
 894         if (!dev->primary->master)
 895                 return;
 896
 897         master_priv = dev->primary->master->driver_priv;
 898         if (!master_priv->sarea_priv)
 899                 return;
 900
 901         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
 902
 903         switch (pipe) {
 904         case 0:
 905                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
 906                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
 907                 break;
 908         case 1:
 909                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
 910                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
 911                 break;
 912         default:
 913                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 914                 break;
 915         }
 916
 917         intel_crtc->dpms_mode = mode;
 918 }
 919
 920 static void intel_crtc_prepare (struct drm_crtc *crtc)
 921 {
 922         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 923         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 924 }
 925
 926 static void intel_crtc_commit (struct drm_crtc *crtc)
 927 {
 928         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 929         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
 930 }
 931
 932 void intel_encoder_prepare (struct drm_encoder *encoder)
 933 {
 934         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 935         /* lvds has its own version of prepare see intel_lvds_prepare */
 936         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
 937 }
 938
 939 void intel_encoder_commit (struct drm_encoder *encoder)
 940 {
 941         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 942         /* lvds has its own version of commit see intel_lvds_commit */
 943         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
 944 }
 945
 946 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
 947                                   struct drm_display_mode *mode,
 948                                   struct drm_display_mode *adjusted_mode)
 949 {
 950         return true;
 951 }
 952
 953
 954 /** Returns the core display clock speed for i830 - i945 */
 955 static int intel_get_core_clock_speed(struct drm_device *dev)
 956 {
 957
 958         /* Core clock values taken from the published datasheets.
 959          * The 830 may go up to 166 Mhz, which we should check.
 960          */
 961         if (IS_I945G(dev))
 962                 return 400000;
 963         else if (IS_I915G(dev))
 964                 return 333000;
 965         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
 966                 return 200000;
 967         else if (IS_I915GM(dev)) {
 968                 u16 gcfgc = 0;
 969
 970                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
 971
 972                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
 973                         return 133000;
 974                 else {
 975                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 976                         case GC_DISPLAY_CLOCK_333_MHZ:
 977                                 return 333000;
 978                         default:
 979                         case GC_DISPLAY_CLOCK_190_200_MHZ:
 980                                 return 190000;
 981                         }
 982                 }
 983         } else if (IS_I865G(dev))
 984                 return 266000;
 985         else if (IS_I855(dev)) {
 986                 u16 hpllcc = 0;
 987                 /* Assume that the hardware is in the high speed state.  This
 988                  * should be the default.
 989                  */
 990                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 991                 case GC_CLOCK_133_200:
 992                 case GC_CLOCK_100_200:
 993                         return 200000;
 994                 case GC_CLOCK_166_250:
 995                         return 250000;
 996                 case GC_CLOCK_100_133:
 997                         return 133000;
 998                 }
 999         } else /* 852, 830 */
1000                 return 133000;
1001
1002         return 0; /* Silence gcc warning */
1003 }
1004
1005
1006 /**
1007  * Return the pipe currently connected to the panel fitter,
1008  * or -1 if the panel fitter is not present or not in use
1009  */
1010 static int intel_panel_fitter_pipe (struct drm_device *dev)
1011 {
1012         struct drm_i915_private *dev_priv = dev->dev_private;
1013         u32  pfit_control;
1014
1015         /* i830 doesn't have a panel fitter */
1016         if (IS_I830(dev))
1017                 return -1;
1018
1019         pfit_control = I915_READ(PFIT_CONTROL);
1020
1021         /* See if the panel fitter is in use */
1022         if ((pfit_control & PFIT_ENABLE) == 0)
1023                 return -1;
1024
1025         /* 965 can place panel fitter on either pipe */
1026         if (IS_I965G(dev))
1027                 return (pfit_control >> 29) & 0x3;
1028
1029         /* older chips can only use pipe 1 */
1030         return 1;
1031 }
1032
1033 static int intel_crtc_mode_set(struct drm_crtc *crtc,
1034                                struct drm_display_mode *mode,
1035                                struct drm_display_mode *adjusted_mode,
1036                                int x, int y,
1037                                struct drm_framebuffer *old_fb)
1038 {
1039         struct drm_device *dev = crtc->dev;
1040         struct drm_i915_private *dev_priv = dev->dev_private;
1041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1042         int pipe = intel_crtc->pipe;
1043         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
1044         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1045         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
1046         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1047         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1048         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1049         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1050         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1051         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1052         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1053         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1054         int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
1055         int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
1056         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
1057         int refclk, num_outputs = 0;
1058         intel_clock_t clock;
1059         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
1060         bool ok, is_sdvo = false, is_dvo = false;
1061         bool is_crt = false, is_lvds = false, is_tv = false;
1062         struct drm_mode_config *mode_config = &dev->mode_config;
1063         struct drm_connector *connector;
1064         const intel_limit_t *limit;
1065         int ret;
1066
1067         drm_vblank_pre_modeset(dev, pipe);
1068
1069         list_for_each_entry(connector, &mode_config->connector_list, head) {
1070                 struct intel_output *intel_output = to_intel_output(connector);
1071
1072                 if (!connector->encoder || connector->encoder->crtc != crtc)
1073                         continue;
1074
1075                 switch (intel_output->type) {
1076                 case INTEL_OUTPUT_LVDS:
1077                         is_lvds = true;
1078                         break;
1079                 case INTEL_OUTPUT_SDVO:
1080                 case INTEL_OUTPUT_HDMI:
1081                         is_sdvo = true;
1082                         if (intel_output->needs_tv_clock)
1083                                 is_tv = true;
1084                         break;
1085                 case INTEL_OUTPUT_DVO:
1086                         is_dvo = true;
1087                         break;
1088                 case INTEL_OUTPUT_TVOUT:
1089                         is_tv = true;
1090                         break;
1091                 case INTEL_OUTPUT_ANALOG:
1092                         is_crt = true;
1093                         break;
1094                 }
1095
1096                 num_outputs++;
1097         }
1098
1099         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
1100                 refclk = dev_priv->lvds_ssc_freq * 1000;
1101                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
1102         } else if (IS_I9XX(dev)) {
1103                 refclk = 96000;
1104         } else {
1105                 refclk = 48000;
1106         }
1107
1108         /*
1109          * Returns a set of divisors for the desired target clock with the given
1110          * refclk, or FALSE.  The returned values represent the clock equation:
1111          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
1112          */
1113         limit = intel_limit(crtc);
1114         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
1115         if (!ok) {
1116                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
1117                 return -EINVAL;
1118         }
1119
1120         /* SDVO TV has fixed PLL values depend on its clock range,
1121            this mirrors vbios setting. */
1122         if (is_sdvo && is_tv) {
1123                 if (adjusted_mode->clock >= 100000
1124                                 && adjusted_mode->clock < 140500) {
1125                         clock.p1 = 2;
1126                         clock.p2 = 10;
1127                         clock.n = 3;
1128                         clock.m1 = 16;
1129                         clock.m2 = 8;
1130                 } else if (adjusted_mode->clock >= 140500
1131                                 && adjusted_mode->clock <= 200000) {
1132                         clock.p1 = 1;
1133                         clock.p2 = 10;
1134                         clock.n = 6;
1135                         clock.m1 = 12;
1136                         clock.m2 = 8;
1137                 }
1138         }
1139
1140         if (IS_IGD(dev))
1141                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
1142         else
1143                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
1144
1145         dpll = DPLL_VGA_MODE_DIS;
1146         if (IS_I9XX(dev)) {
1147                 if (is_lvds)
1148                         dpll |= DPLLB_MODE_LVDS;
1149                 else
1150                         dpll |= DPLLB_MODE_DAC_SERIAL;
1151                 if (is_sdvo) {
1152                         dpll |= DPLL_DVO_HIGH_SPEED;
1153                         if (IS_I945G(dev) || IS_I945GM(dev)) {
1154                                 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1155                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
1156                         }
1157                 }
1158
1159                 /* compute bitmask from p1 value */
1160                 if (IS_IGD(dev))
1161                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
1162                 else
1163                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1164                 switch (clock.p2) {
1165                 case 5:
1166                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1167                         break;
1168                 case 7:
1169                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1170                         break;
1171                 case 10:
1172                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1173                         break;
1174                 case 14:
1175                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1176                         break;
1177                 }
1178                 if (IS_I965G(dev))
1179                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
1180         } else {
1181                 if (is_lvds) {
1182                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1183                 } else {
1184                         if (clock.p1 == 2)
1185                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
1186                         else
1187                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1188                         if (clock.p2 == 4)
1189                                 dpll |= PLL_P2_DIVIDE_BY_4;
1190                 }
1191         }
1192
1193         if (is_sdvo && is_tv)
1194                 dpll |= PLL_REF_INPUT_TVCLKINBC;
1195         else if (is_tv)
1196                 /* XXX: just matching BIOS for now */
1197                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
1198                 dpll |= 3;
1199         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
1200                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1201         else
1202                 dpll |= PLL_REF_INPUT_DREFCLK;
1203
1204         /* setup pipeconf */
1205         pipeconf = I915_READ(pipeconf_reg);
1206
1207         /* Set up the display plane register */
1208         dspcntr = DISPPLANE_GAMMA_ENABLE;
1209
1210         if (pipe == 0)
1211                 dspcntr |= DISPPLANE_SEL_PIPE_A;
1212         else
1213                 dspcntr |= DISPPLANE_SEL_PIPE_B;
1214
1215         if (pipe == 0 && !IS_I965G(dev)) {
1216                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
1217                  * core speed.
1218                  *
1219                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
1220                  * pipe == 0 check?
1221                  */
1222                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
1223                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
1224                 else
1225                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
1226         }
1227
1228         dspcntr |= DISPLAY_PLANE_ENABLE;
1229         pipeconf |= PIPEACONF_ENABLE;
1230         dpll |= DPLL_VCO_ENABLE;
1231
1232
1233         /* Disable the panel fitter if it was on our pipe */
1234         if (intel_panel_fitter_pipe(dev) == pipe)
1235                 I915_WRITE(PFIT_CONTROL, 0);
1236
1237         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
1238         drm_mode_debug_printmodeline(mode);
1239
1240
1241         if (dpll & DPLL_VCO_ENABLE) {
1242                 I915_WRITE(fp_reg, fp);
1243                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
1244                 I915_READ(dpll_reg);
1245                 udelay(150);
1246         }
1247
1248         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
1249          * This is an exception to the general rule that mode_set doesn't turn
1250          * things on.
1251          */
1252         if (is_lvds) {
1253                 u32 lvds = I915_READ(LVDS);
1254
1255                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
1256                 /* Set the B0-B3 data pairs corresponding to whether we're going to
1257                  * set the DPLLs for dual-channel mode or not.
1258                  */
1259                 if (clock.p2 == 7)
1260                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
1261                 else
1262                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
1263
1264                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
1265                  * appropriately here, but we need to look more thoroughly into how
1266                  * panels behave in the two modes.
1267                  */
1268
1269                 I915_WRITE(LVDS, lvds);
1270                 I915_READ(LVDS);
1271         }
1272
1273         I915_WRITE(fp_reg, fp);
1274         I915_WRITE(dpll_reg, dpll);
1275         I915_READ(dpll_reg);
1276         /* Wait for the clocks to stabilize. */
1277         udelay(150);
1278
1279         if (IS_I965G(dev)) {
1280                 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1281                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
1282                            ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
1283         } else {
1284                 /* write it again -- the BIOS does, after all */
1285                 I915_WRITE(dpll_reg, dpll);
1286         }
1287         I915_READ(dpll_reg);
1288         /* Wait for the clocks to stabilize. */
1289         udelay(150);
1290
1291         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
1292                    ((adjusted_mode->crtc_htotal - 1) << 16));
1293         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
1294                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
1295         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
1296                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
1297         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
1298                    ((adjusted_mode->crtc_vtotal - 1) << 16));
1299         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
1300                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
1301         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
1302                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
1303         /* pipesrc and dspsize control the size that is scaled from, which should
1304          * always be the user's requested size.
1305          */
1306         I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
1307         I915_WRITE(dsppos_reg, 0);
1308         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
1309         I915_WRITE(pipeconf_reg, pipeconf);
1310         I915_READ(pipeconf_reg);
1311
1312         intel_wait_for_vblank(dev);
1313
1314         I915_WRITE(dspcntr_reg, dspcntr);
1315
1316         /* Flush the plane changes */
1317         ret = intel_pipe_set_base(crtc, x, y, old_fb);
1318         if (ret != 0)
1319             return ret;
1320
1321         drm_vblank_post_modeset(dev, pipe);
1322
1323         return 0;
1324 }
1325
1326 /** Loads the palette/gamma unit for the CRTC with the prepared values */
1327 void intel_crtc_load_lut(struct drm_crtc *crtc)
1328 {
1329         struct drm_device *dev = crtc->dev;
1330         struct drm_i915_private *dev_priv = dev->dev_private;
1331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1332         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
1333         int i;
1334
1335         /* The clocks have to be on to load the palette. */
1336         if (!crtc->enabled)
1337                 return;
1338
1339         for (i = 0; i < 256; i++) {
1340                 I915_WRITE(palreg + 4 * i,
1341                            (intel_crtc->lut_r[i] << 16) |
1342                            (intel_crtc->lut_g[i] << 8) |
1343                            intel_crtc->lut_b[i]);
1344         }
1345 }
1346
1347 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
1348                                  struct drm_file *file_priv,
1349                                  uint32_t handle,
1350                                  uint32_t width, uint32_t height)
1351 {
1352         struct drm_device *dev = crtc->dev;
1353         struct drm_i915_private *dev_priv = dev->dev_private;
1354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1355         struct drm_gem_object *bo;
1356         struct drm_i915_gem_object *obj_priv;
1357         int pipe = intel_crtc->pipe;
1358         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1359         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1360         uint32_t temp;
1361         size_t addr;
1362         int ret;
1363
1364         DRM_DEBUG("\n");
1365
1366         /* if we want to turn off the cursor ignore width and height */
1367         if (!handle) {
1368                 DRM_DEBUG("cursor off\n");
1369                 temp = CURSOR_MODE_DISABLE;
1370                 addr = 0;
1371                 bo = NULL;
1372                 mutex_lock(&dev->struct_mutex);
1373                 goto finish;
1374         }
1375
1376         /* Currently we only support 64x64 cursors */
1377         if (width != 64 || height != 64) {
1378                 DRM_ERROR("we currently only support 64x64 cursors\n");
1379                 return -EINVAL;
1380         }
1381
1382         bo = drm_gem_object_lookup(dev, file_priv, handle);
1383         if (!bo)
1384                 return -ENOENT;
1385
1386         obj_priv = bo->driver_private;
1387
1388         if (bo->size < width * height * 4) {
1389                 DRM_ERROR("buffer is to small\n");
1390                 ret = -ENOMEM;
1391                 goto fail;
1392         }
1393
1394         /* we only need to pin inside GTT if cursor is non-phy */
1395         mutex_lock(&dev->struct_mutex);
1396         if (!dev_priv->cursor_needs_physical) {
1397                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
1398                 if (ret) {
1399                         DRM_ERROR("failed to pin cursor bo\n");
1400                         goto fail_locked;
1401                 }
1402                 addr = obj_priv->gtt_offset;
1403         } else {
1404                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
1405                 if (ret) {
1406                         DRM_ERROR("failed to attach phys object\n");
1407                         goto fail_locked;
1408                 }
1409                 addr = obj_priv->phys_obj->handle->busaddr;
1410         }
1411
1412         temp = 0;
1413         /* set the pipe for the cursor */
1414         temp |= (pipe << 28);
1415         temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1416
1417  finish:
1418         I915_WRITE(control, temp);
1419         I915_WRITE(base, addr);
1420
1421         if (intel_crtc->cursor_bo) {
1422                 if (dev_priv->cursor_needs_physical) {
1423                         if (intel_crtc->cursor_bo != bo)
1424                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
1425                 } else
1426                         i915_gem_object_unpin(intel_crtc->cursor_bo);
1427                 drm_gem_object_unreference(intel_crtc->cursor_bo);
1428         }
1429         mutex_unlock(&dev->struct_mutex);
1430
1431         intel_crtc->cursor_addr = addr;
1432         intel_crtc->cursor_bo = bo;
1433
1434         return 0;
1435 fail:
1436         mutex_lock(&dev->struct_mutex);
1437 fail_locked:
1438         drm_gem_object_unreference(bo);
1439         mutex_unlock(&dev->struct_mutex);
1440         return ret;
1441 }
1442
1443 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1444 {
1445         struct drm_device *dev = crtc->dev;
1446         struct drm_i915_private *dev_priv = dev->dev_private;
1447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1448         int pipe = intel_crtc->pipe;
1449         uint32_t temp = 0;
1450         uint32_t adder;
1451
1452         if (x < 0) {
1453                 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1454                 x = -x;
1455         }
1456         if (y < 0) {
1457                 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1458                 y = -y;
1459         }
1460
1461         temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1462         temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1463
1464         adder = intel_crtc->cursor_addr;
1465         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1466         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1467
1468         return 0;
1469 }
1470
1471 /** Sets the color ramps on behalf of RandR */
1472 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1473                                  u16 blue, int regno)
1474 {
1475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1476
1477         intel_crtc->lut_r[regno] = red >> 8;
1478         intel_crtc->lut_g[regno] = green >> 8;
1479         intel_crtc->lut_b[regno] = blue >> 8;
1480 }
1481
1482 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1483                                  u16 *blue, uint32_t size)
1484 {
1485         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1486         int i;
1487
1488         if (size != 256)
1489                 return;
1490
1491         for (i = 0; i < 256; i++) {
1492                 intel_crtc->lut_r[i] = red[i] >> 8;
1493                 intel_crtc->lut_g[i] = green[i] >> 8;
1494                 intel_crtc->lut_b[i] = blue[i] >> 8;
1495         }
1496
1497         intel_crtc_load_lut(crtc);
1498 }
1499
1500 /**
1501  * Get a pipe with a simple mode set on it for doing load-based monitor
1502  * detection.
1503  *
1504  * It will be up to the load-detect code to adjust the pipe as appropriate for
1505  * its requirements.  The pipe will be connected to no other outputs.
1506  *
1507  * Currently this code will only succeed if there is a pipe with no outputs
1508  * configured for it.  In the future, it could choose to temporarily disable
1509  * some outputs to free up a pipe for its use.
1510  *
1511  * \return crtc, or NULL if no pipes are available.
1512  */
1513
1514 /* VESA 640x480x72Hz mode to set on the pipe */
1515 static struct drm_display_mode load_detect_mode = {
1516         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
1517                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1518 };
1519
1520 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
1521                                             struct drm_display_mode *mode,
1522                                             int *dpms_mode)
1523 {
1524         struct intel_crtc *intel_crtc;
1525         struct drm_crtc *possible_crtc;
1526         struct drm_crtc *supported_crtc =NULL;
1527         struct drm_encoder *encoder = &intel_output->enc;
1528         struct drm_crtc *crtc = NULL;
1529         struct drm_device *dev = encoder->dev;
1530         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1531         struct drm_crtc_helper_funcs *crtc_funcs;
1532         int i = -1;
1533
1534         /*
1535          * Algorithm gets a little messy:
1536          *   - if the connector already has an assigned crtc, use it (but make
1537          *     sure it's on first)
1538          *   - try to find the first unused crtc that can drive this connector,
1539          *     and use that if we find one
1540          *   - if there are no unused crtcs available, try to use the first
1541          *     one we found that supports the connector
1542          */
1543
1544         /* See if we already have a CRTC for this connector */
1545         if (encoder->crtc) {
1546                 crtc = encoder->crtc;
1547                 /* Make sure the crtc and connector are running */
1548                 intel_crtc = to_intel_crtc(crtc);
1549                 *dpms_mode = intel_crtc->dpms_mode;
1550                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1551                         crtc_funcs = crtc->helper_private;
1552                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1553                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1554                 }
1555                 return crtc;
1556         }
1557
1558         /* Find an unused one (if possible) */
1559         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
1560                 i++;
1561                 if (!(encoder->possible_crtcs & (1 << i)))
1562                         continue;
1563                 if (!possible_crtc->enabled) {
1564                         crtc = possible_crtc;
1565                         break;
1566                 }
1567                 if (!supported_crtc)
1568                         supported_crtc = possible_crtc;
1569         }
1570
1571         /*
1572          * If we didn't find an unused CRTC, don't use any.
1573          */
1574         if (!crtc) {
1575                 return NULL;
1576         }
1577
1578         encoder->crtc = crtc;
1579         intel_output->load_detect_temp = true;
1580
1581         intel_crtc = to_intel_crtc(crtc);
1582         *dpms_mode = intel_crtc->dpms_mode;
1583
1584         if (!crtc->enabled) {
1585                 if (!mode)
1586                         mode = &load_detect_mode;
1587                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
1588         } else {
1589                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1590                         crtc_funcs = crtc->helper_private;
1591                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1592                 }
1593
1594                 /* Add this connector to the crtc */
1595                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
1596                 encoder_funcs->commit(encoder);
1597         }
1598         /* let the connector get through one full cycle before testing */
1599         intel_wait_for_vblank(dev);
1600
1601         return crtc;
1602 }
1603
1604 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
1605 {
1606         struct drm_encoder *encoder = &intel_output->enc;
1607         struct drm_device *dev = encoder->dev;
1608         struct drm_crtc *crtc = encoder->crtc;
1609         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1610         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1611
1612         if (intel_output->load_detect_temp) {
1613                 encoder->crtc = NULL;
1614                 intel_output->load_detect_temp = false;
1615                 crtc->enabled = drm_helper_crtc_in_use(crtc);
1616                 drm_helper_disable_unused_functions(dev);
1617         }
1618
1619         /* Switch crtc and output back off if necessary */
1620         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
1621                 if (encoder->crtc == crtc)
1622                         encoder_funcs->dpms(encoder, dpms_mode);
1623                 crtc_funcs->dpms(crtc, dpms_mode);
1624         }
1625 }
1626
1627 /* Returns the clock of the currently programmed mode of the given pipe. */
1628 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
1629 {
1630         struct drm_i915_private *dev_priv = dev->dev_private;
1631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1632         int pipe = intel_crtc->pipe;
1633         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
1634         u32 fp;
1635         intel_clock_t clock;
1636
1637         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1638                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
1639         else
1640                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
1641
1642         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1643         if (IS_IGD(dev)) {
1644                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
1645                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
1646         } else {
1647                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1648                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1649         }
1650
1651         if (IS_I9XX(dev)) {
1652                 if (IS_IGD(dev))
1653                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
1654                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
1655                 else
1656                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
1657                                DPLL_FPA01_P1_POST_DIV_SHIFT);
1658
1659                 switch (dpll & DPLL_MODE_MASK) {
1660                 case DPLLB_MODE_DAC_SERIAL:
1661                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
1662                                 5 : 10;
1663                         break;
1664                 case DPLLB_MODE_LVDS:
1665                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
1666                                 7 : 14;
1667                         break;
1668                 default:
1669                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
1670                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
1671                         return 0;
1672                 }
1673
1674                 /* XXX: Handle the 100Mhz refclk */
1675                 intel_clock(dev, 96000, &clock);
1676         } else {
1677                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
1678
1679                 if (is_lvds) {
1680                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1681                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
1682                         clock.p2 = 14;
1683
1684                         if ((dpll & PLL_REF_INPUT_MASK) ==
1685                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1686                                 /* XXX: might not be 66MHz */
1687                                 intel_clock(dev, 66000, &clock);
1688                         } else
1689                                 intel_clock(dev, 48000, &clock);
1690                 } else {
1691                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
1692                                 clock.p1 = 2;
1693                         else {
1694                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1695                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1696                         }
1697                         if (dpll & PLL_P2_DIVIDE_BY_4)
1698                                 clock.p2 = 4;
1699                         else
1700                                 clock.p2 = 2;
1701
1702                         intel_clock(dev, 48000, &clock);
1703                 }
1704         }
1705
1706         /* XXX: It would be nice to validate the clocks, but we can't reuse
1707          * i830PllIsValid() because it relies on the xf86_config connector
1708          * configuration being accurate, which it isn't necessarily.
1709          */
1710
1711         return clock.dot;
1712 }
1713
1714 /** Returns the currently programmed mode of the given pipe. */
1715 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1716                                              struct drm_crtc *crtc)
1717 {
1718         struct drm_i915_private *dev_priv = dev->dev_private;
1719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1720         int pipe = intel_crtc->pipe;
1721         struct drm_display_mode *mode;
1722         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
1723         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
1724         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
1725         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1726
1727         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1728         if (!mode)
1729                 return NULL;
1730
1731         mode->clock = intel_crtc_clock_get(dev, crtc);
1732         mode->hdisplay = (htot & 0xffff) + 1;
1733         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1734         mode->hsync_start = (hsync & 0xffff) + 1;
1735         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1736         mode->vdisplay = (vtot & 0xffff) + 1;
1737         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1738         mode->vsync_start = (vsync & 0xffff) + 1;
1739         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1740
1741         drm_mode_set_name(mode);
1742         drm_mode_set_crtcinfo(mode, 0);
1743
1744         return mode;
1745 }
1746
1747 static void intel_crtc_destroy(struct drm_crtc *crtc)
1748 {
1749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1750
1751         drm_crtc_cleanup(crtc);
1752         kfree(intel_crtc);
1753 }
1754
1755 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
1756         .dpms = intel_crtc_dpms,
1757         .mode_fixup = intel_crtc_mode_fixup,
1758         .mode_set = intel_crtc_mode_set,
1759         .mode_set_base = intel_pipe_set_base,
1760         .prepare = intel_crtc_prepare,
1761         .commit = intel_crtc_commit,
1762 };
1763
1764 static const struct drm_crtc_funcs intel_crtc_funcs = {
1765         .cursor_set = intel_crtc_cursor_set,
1766         .cursor_move = intel_crtc_cursor_move,
1767         .gamma_set = intel_crtc_gamma_set,
1768         .set_config = drm_crtc_helper_set_config,
1769         .destroy = intel_crtc_destroy,
1770 };
1771
1772
1773 static void intel_crtc_init(struct drm_device *dev, int pipe)
1774 {
1775         struct intel_crtc *intel_crtc;
1776         int i;
1777
1778         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
1779         if (intel_crtc == NULL)
1780                 return;
1781
1782         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
1783
1784         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
1785         intel_crtc->pipe = pipe;
1786         for (i = 0; i < 256; i++) {
1787                 intel_crtc->lut_r[i] = i;
1788                 intel_crtc->lut_g[i] = i;
1789                 intel_crtc->lut_b[i] = i;
1790         }
1791
1792         intel_crtc->cursor_addr = 0;
1793         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
1794         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
1795
1796         intel_crtc->mode_set.crtc = &intel_crtc->base;
1797         intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
1798         intel_crtc->mode_set.num_connectors = 0;
1799
1800         if (i915_fbpercrtc) {
1801
1802
1803
1804         }
1805 }
1806
1807 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
1808 {
1809         struct drm_crtc *crtc = NULL;
1810
1811         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1812                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1813                 if (intel_crtc->pipe == pipe)
1814                         break;
1815         }
1816         return crtc;
1817 }
1818
1819 static int intel_connector_clones(struct drm_device *dev, int type_mask)
1820 {
1821         int index_mask = 0;
1822         struct drm_connector *connector;
1823         int entry = 0;
1824
1825         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1826                 struct intel_output *intel_output = to_intel_output(connector);
1827                 if (type_mask & (1 << intel_output->type))
1828                         index_mask |= (1 << entry);
1829                 entry++;
1830         }
1831         return index_mask;
1832 }
1833
1834
1835 static void intel_setup_outputs(struct drm_device *dev)
1836 {
1837         struct drm_i915_private *dev_priv = dev->dev_private;
1838         struct drm_connector *connector;
1839
1840         intel_crt_init(dev);
1841
1842         /* Set up integrated LVDS */
1843         if (IS_MOBILE(dev) && !IS_I830(dev))
1844                 intel_lvds_init(dev);
1845
1846         if (IS_I9XX(dev)) {
1847                 int found;
1848                 u32 reg;
1849
1850                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
1851                         found = intel_sdvo_init(dev, SDVOB);
1852                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1853                                 intel_hdmi_init(dev, SDVOB);
1854                 }
1855
1856                 /* Before G4X SDVOC doesn't have its own detect register */
1857                 if (IS_G4X(dev))
1858                         reg = SDVOC;
1859                 else
1860                         reg = SDVOB;
1861
1862                 if (I915_READ(reg) & SDVO_DETECTED) {
1863                         found = intel_sdvo_init(dev, SDVOC);
1864                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1865                                 intel_hdmi_init(dev, SDVOC);
1866                 }
1867         } else
1868                 intel_dvo_init(dev);
1869
1870         if (IS_I9XX(dev) && IS_MOBILE(dev))
1871                 intel_tv_init(dev);
1872
1873         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1874                 struct intel_output *intel_output = to_intel_output(connector);
1875                 struct drm_encoder *encoder = &intel_output->enc;
1876                 int crtc_mask = 0, clone_mask = 0;
1877
1878                 /* valid crtcs */
1879                 switch(intel_output->type) {
1880                 case INTEL_OUTPUT_HDMI:
1881                         crtc_mask = ((1 << 0)|
1882                                      (1 << 1));
1883                         clone_mask = ((1 << INTEL_OUTPUT_HDMI));
1884                         break;
1885                 case INTEL_OUTPUT_DVO:
1886                 case INTEL_OUTPUT_SDVO:
1887                         crtc_mask = ((1 << 0)|
1888                                      (1 << 1));
1889                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1890                                       (1 << INTEL_OUTPUT_DVO) |
1891                                       (1 << INTEL_OUTPUT_SDVO));
1892                         break;
1893                 case INTEL_OUTPUT_ANALOG:
1894                         crtc_mask = ((1 << 0)|
1895                                      (1 << 1));
1896                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1897                                       (1 << INTEL_OUTPUT_DVO) |
1898                                       (1 << INTEL_OUTPUT_SDVO));
1899                         break;
1900                 case INTEL_OUTPUT_LVDS:
1901                         crtc_mask = (1 << 1);
1902                         clone_mask = (1 << INTEL_OUTPUT_LVDS);
1903                         break;
1904                 case INTEL_OUTPUT_TVOUT:
1905                         crtc_mask = ((1 << 0) |
1906                                      (1 << 1));
1907                         clone_mask = (1 << INTEL_OUTPUT_TVOUT);
1908                         break;
1909                 }
1910                 encoder->possible_crtcs = crtc_mask;
1911                 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
1912         }
1913 }
1914
1915 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
1916 {
1917         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1918         struct drm_device *dev = fb->dev;
1919
1920         if (fb->fbdev)
1921                 intelfb_remove(dev, fb);
1922
1923         drm_framebuffer_cleanup(fb);
1924         mutex_lock(&dev->struct_mutex);
1925         drm_gem_object_unreference(intel_fb->obj);
1926         mutex_unlock(&dev->struct_mutex);
1927
1928         kfree(intel_fb);
1929 }
1930
1931 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1932                                                 struct drm_file *file_priv,
1933                                                 unsigned int *handle)
1934 {
1935         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1936         struct drm_gem_object *object = intel_fb->obj;
1937
1938         return drm_gem_handle_create(file_priv, object, handle);
1939 }
1940
1941 static const struct drm_framebuffer_funcs intel_fb_funcs = {
1942         .destroy = intel_user_framebuffer_destroy,
1943         .create_handle = intel_user_framebuffer_create_handle,
1944 };
1945
1946 int intel_framebuffer_create(struct drm_device *dev,
1947                              struct drm_mode_fb_cmd *mode_cmd,
1948                              struct drm_framebuffer **fb,
1949                              struct drm_gem_object *obj)
1950 {
1951         struct intel_framebuffer *intel_fb;
1952         int ret;
1953
1954         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1955         if (!intel_fb)
1956                 return -ENOMEM;
1957
1958         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
1959         if (ret) {
1960                 DRM_ERROR("framebuffer init failed %d\n", ret);
1961                 return ret;
1962         }
1963
1964         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
1965
1966         intel_fb->obj = obj;
1967
1968         *fb = &intel_fb->base;
1969
1970         return 0;
1971 }
1972
1973
1974 static struct drm_framebuffer *
1975 intel_user_framebuffer_create(struct drm_device *dev,
1976                               struct drm_file *filp,
1977                               struct drm_mode_fb_cmd *mode_cmd)
1978 {
1979         struct drm_gem_object *obj;
1980         struct drm_framebuffer *fb;
1981         int ret;
1982
1983         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
1984         if (!obj)
1985                 return NULL;
1986
1987         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
1988         if (ret) {
1989                 mutex_lock(&dev->struct_mutex);
1990                 drm_gem_object_unreference(obj);
1991                 mutex_unlock(&dev->struct_mutex);
1992                 return NULL;
1993         }
1994
1995         return fb;
1996 }
1997
1998 static const struct drm_mode_config_funcs intel_mode_funcs = {
1999         .fb_create = intel_user_framebuffer_create,
2000         .fb_changed = intelfb_probe,
2001 };
2002
2003 void intel_modeset_init(struct drm_device *dev)
2004 {
2005         int num_pipe;
2006         int i;
2007
2008         drm_mode_config_init(dev);
2009
2010         dev->mode_config.min_width = 0;
2011         dev->mode_config.min_height = 0;
2012
2013         dev->mode_config.funcs = (void *)&intel_mode_funcs;
2014
2015         if (IS_I965G(dev)) {
2016                 dev->mode_config.max_width = 8192;
2017                 dev->mode_config.max_height = 8192;
2018         } else {
2019                 dev->mode_config.max_width = 2048;
2020                 dev->mode_config.max_height = 2048;
2021         }
2022
2023         /* set memory base */
2024         if (IS_I9XX(dev))
2025                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
2026         else
2027                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
2028
2029         if (IS_MOBILE(dev) || IS_I9XX(dev))
2030                 num_pipe = 2;
2031         else
2032                 num_pipe = 1;
2033         DRM_DEBUG("%d display pipe%s available.\n",
2034                   num_pipe, num_pipe > 1 ? "s" : "");
2035
2036         for (i = 0; i < num_pipe; i++) {
2037                 intel_crtc_init(dev, i);
2038         }
2039
2040         intel_setup_outputs(dev);
2041 }
2042
2043 void intel_modeset_cleanup(struct drm_device *dev)
2044 {
2045         drm_mode_config_cleanup(dev);
2046 }
2047
2048
2049 /* current intel driver doesn't take advantage of encoders
2050    always give back the encoder for the connector
2051 */
2052 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
2053 {
2054         struct intel_output *intel_output = to_intel_output(connector);
2055
2056         return &intel_output->enc;
2057 }