Merge tag 'topic/drm-misc-2016-08-12' of git://anongit.freedesktop.org/drm-intel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_gem_dmabuf.h"
40 #include "intel_dsi.h"
41 #include "i915_trace.h"
42 #include <drm/drm_atomic.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_plane_helper.h>
47 #include <drm/drm_rect.h>
48 #include <linux/dma_remapping.h>
49 #include <linux/reservation.h>
50
51 static bool is_mmio_work(struct intel_flip_work *work)
52 {
53         return work->mmio_work.func;
54 }
55
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats[] = {
58         DRM_FORMAT_C8,
59         DRM_FORMAT_RGB565,
60         DRM_FORMAT_XRGB1555,
61         DRM_FORMAT_XRGB8888,
62 };
63
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats[] = {
66         DRM_FORMAT_C8,
67         DRM_FORMAT_RGB565,
68         DRM_FORMAT_XRGB8888,
69         DRM_FORMAT_XBGR8888,
70         DRM_FORMAT_XRGB2101010,
71         DRM_FORMAT_XBGR2101010,
72 };
73
74 static const uint32_t skl_primary_formats[] = {
75         DRM_FORMAT_C8,
76         DRM_FORMAT_RGB565,
77         DRM_FORMAT_XRGB8888,
78         DRM_FORMAT_XBGR8888,
79         DRM_FORMAT_ARGB8888,
80         DRM_FORMAT_ABGR8888,
81         DRM_FORMAT_XRGB2101010,
82         DRM_FORMAT_XBGR2101010,
83         DRM_FORMAT_YUYV,
84         DRM_FORMAT_YVYU,
85         DRM_FORMAT_UYVY,
86         DRM_FORMAT_VYUY,
87 };
88
89 /* Cursor formats */
90 static const uint32_t intel_cursor_formats[] = {
91         DRM_FORMAT_ARGB8888,
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95                                 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97                                    struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct drm_device *dev,
100                                   struct intel_framebuffer *ifb,
101                                   struct drm_mode_fb_cmd2 *mode_cmd,
102                                   struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107                                          struct intel_link_m_n *m_n,
108                                          struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113                             const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115                             const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
119         struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
126 static int bxt_calc_cdclk(int max_pixclk);
127
128 struct intel_limit {
129         struct {
130                 int min, max;
131         } dot, vco, n, m, m1, m2, p, p1;
132
133         struct {
134                 int dot_limit;
135                 int p2_slow, p2_fast;
136         } p2;
137 };
138
139 /* returns HPLL frequency in kHz */
140 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
141 {
142         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
143
144         /* Obtain SKU information */
145         mutex_lock(&dev_priv->sb_lock);
146         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
147                 CCK_FUSE_HPLL_FREQ_MASK;
148         mutex_unlock(&dev_priv->sb_lock);
149
150         return vco_freq[hpll_freq] * 1000;
151 }
152
153 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
154                       const char *name, u32 reg, int ref_freq)
155 {
156         u32 val;
157         int divider;
158
159         mutex_lock(&dev_priv->sb_lock);
160         val = vlv_cck_read(dev_priv, reg);
161         mutex_unlock(&dev_priv->sb_lock);
162
163         divider = val & CCK_FREQUENCY_VALUES;
164
165         WARN((val & CCK_FREQUENCY_STATUS) !=
166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
167              "%s change in progress\n", name);
168
169         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
170 }
171
172 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
173                                   const char *name, u32 reg)
174 {
175         if (dev_priv->hpll_freq == 0)
176                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
177
178         return vlv_get_cck_clock(dev_priv, name, reg,
179                                  dev_priv->hpll_freq);
180 }
181
182 static int
183 intel_pch_rawclk(struct drm_i915_private *dev_priv)
184 {
185         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
186 }
187
188 static int
189 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
190 {
191         /* RAWCLK_FREQ_VLV register updated from power well code */
192         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
193                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
194 }
195
196 static int
197 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
198 {
199         uint32_t clkcfg;
200
201         /* hrawclock is 1/4 the FSB frequency */
202         clkcfg = I915_READ(CLKCFG);
203         switch (clkcfg & CLKCFG_FSB_MASK) {
204         case CLKCFG_FSB_400:
205                 return 100000;
206         case CLKCFG_FSB_533:
207                 return 133333;
208         case CLKCFG_FSB_667:
209                 return 166667;
210         case CLKCFG_FSB_800:
211                 return 200000;
212         case CLKCFG_FSB_1067:
213                 return 266667;
214         case CLKCFG_FSB_1333:
215                 return 333333;
216         /* these two are just a guess; one of them might be right */
217         case CLKCFG_FSB_1600:
218         case CLKCFG_FSB_1600_ALT:
219                 return 400000;
220         default:
221                 return 133333;
222         }
223 }
224
225 void intel_update_rawclk(struct drm_i915_private *dev_priv)
226 {
227         if (HAS_PCH_SPLIT(dev_priv))
228                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
229         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
230                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
231         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
232                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
233         else
234                 return; /* no rawclk on other platforms, or no need to know it */
235
236         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
237 }
238
239 static void intel_update_czclk(struct drm_i915_private *dev_priv)
240 {
241         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
242                 return;
243
244         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
245                                                       CCK_CZ_CLOCK_CONTROL);
246
247         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
248 }
249
250 static inline u32 /* units of 100MHz */
251 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
252                     const struct intel_crtc_state *pipe_config)
253 {
254         if (HAS_DDI(dev_priv))
255                 return pipe_config->port_clock; /* SPLL */
256         else if (IS_GEN5(dev_priv))
257                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
258         else
259                 return 270000;
260 }
261
262 static const struct intel_limit intel_limits_i8xx_dac = {
263         .dot = { .min = 25000, .max = 350000 },
264         .vco = { .min = 908000, .max = 1512000 },
265         .n = { .min = 2, .max = 16 },
266         .m = { .min = 96, .max = 140 },
267         .m1 = { .min = 18, .max = 26 },
268         .m2 = { .min = 6, .max = 16 },
269         .p = { .min = 4, .max = 128 },
270         .p1 = { .min = 2, .max = 33 },
271         .p2 = { .dot_limit = 165000,
272                 .p2_slow = 4, .p2_fast = 2 },
273 };
274
275 static const struct intel_limit intel_limits_i8xx_dvo = {
276         .dot = { .min = 25000, .max = 350000 },
277         .vco = { .min = 908000, .max = 1512000 },
278         .n = { .min = 2, .max = 16 },
279         .m = { .min = 96, .max = 140 },
280         .m1 = { .min = 18, .max = 26 },
281         .m2 = { .min = 6, .max = 16 },
282         .p = { .min = 4, .max = 128 },
283         .p1 = { .min = 2, .max = 33 },
284         .p2 = { .dot_limit = 165000,
285                 .p2_slow = 4, .p2_fast = 4 },
286 };
287
288 static const struct intel_limit intel_limits_i8xx_lvds = {
289         .dot = { .min = 25000, .max = 350000 },
290         .vco = { .min = 908000, .max = 1512000 },
291         .n = { .min = 2, .max = 16 },
292         .m = { .min = 96, .max = 140 },
293         .m1 = { .min = 18, .max = 26 },
294         .m2 = { .min = 6, .max = 16 },
295         .p = { .min = 4, .max = 128 },
296         .p1 = { .min = 1, .max = 6 },
297         .p2 = { .dot_limit = 165000,
298                 .p2_slow = 14, .p2_fast = 7 },
299 };
300
301 static const struct intel_limit intel_limits_i9xx_sdvo = {
302         .dot = { .min = 20000, .max = 400000 },
303         .vco = { .min = 1400000, .max = 2800000 },
304         .n = { .min = 1, .max = 6 },
305         .m = { .min = 70, .max = 120 },
306         .m1 = { .min = 8, .max = 18 },
307         .m2 = { .min = 3, .max = 7 },
308         .p = { .min = 5, .max = 80 },
309         .p1 = { .min = 1, .max = 8 },
310         .p2 = { .dot_limit = 200000,
311                 .p2_slow = 10, .p2_fast = 5 },
312 };
313
314 static const struct intel_limit intel_limits_i9xx_lvds = {
315         .dot = { .min = 20000, .max = 400000 },
316         .vco = { .min = 1400000, .max = 2800000 },
317         .n = { .min = 1, .max = 6 },
318         .m = { .min = 70, .max = 120 },
319         .m1 = { .min = 8, .max = 18 },
320         .m2 = { .min = 3, .max = 7 },
321         .p = { .min = 7, .max = 98 },
322         .p1 = { .min = 1, .max = 8 },
323         .p2 = { .dot_limit = 112000,
324                 .p2_slow = 14, .p2_fast = 7 },
325 };
326
327
328 static const struct intel_limit intel_limits_g4x_sdvo = {
329         .dot = { .min = 25000, .max = 270000 },
330         .vco = { .min = 1750000, .max = 3500000},
331         .n = { .min = 1, .max = 4 },
332         .m = { .min = 104, .max = 138 },
333         .m1 = { .min = 17, .max = 23 },
334         .m2 = { .min = 5, .max = 11 },
335         .p = { .min = 10, .max = 30 },
336         .p1 = { .min = 1, .max = 3},
337         .p2 = { .dot_limit = 270000,
338                 .p2_slow = 10,
339                 .p2_fast = 10
340         },
341 };
342
343 static const struct intel_limit intel_limits_g4x_hdmi = {
344         .dot = { .min = 22000, .max = 400000 },
345         .vco = { .min = 1750000, .max = 3500000},
346         .n = { .min = 1, .max = 4 },
347         .m = { .min = 104, .max = 138 },
348         .m1 = { .min = 16, .max = 23 },
349         .m2 = { .min = 5, .max = 11 },
350         .p = { .min = 5, .max = 80 },
351         .p1 = { .min = 1, .max = 8},
352         .p2 = { .dot_limit = 165000,
353                 .p2_slow = 10, .p2_fast = 5 },
354 };
355
356 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
357         .dot = { .min = 20000, .max = 115000 },
358         .vco = { .min = 1750000, .max = 3500000 },
359         .n = { .min = 1, .max = 3 },
360         .m = { .min = 104, .max = 138 },
361         .m1 = { .min = 17, .max = 23 },
362         .m2 = { .min = 5, .max = 11 },
363         .p = { .min = 28, .max = 112 },
364         .p1 = { .min = 2, .max = 8 },
365         .p2 = { .dot_limit = 0,
366                 .p2_slow = 14, .p2_fast = 14
367         },
368 };
369
370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
371         .dot = { .min = 80000, .max = 224000 },
372         .vco = { .min = 1750000, .max = 3500000 },
373         .n = { .min = 1, .max = 3 },
374         .m = { .min = 104, .max = 138 },
375         .m1 = { .min = 17, .max = 23 },
376         .m2 = { .min = 5, .max = 11 },
377         .p = { .min = 14, .max = 42 },
378         .p1 = { .min = 2, .max = 6 },
379         .p2 = { .dot_limit = 0,
380                 .p2_slow = 7, .p2_fast = 7
381         },
382 };
383
384 static const struct intel_limit intel_limits_pineview_sdvo = {
385         .dot = { .min = 20000, .max = 400000},
386         .vco = { .min = 1700000, .max = 3500000 },
387         /* Pineview's Ncounter is a ring counter */
388         .n = { .min = 3, .max = 6 },
389         .m = { .min = 2, .max = 256 },
390         /* Pineview only has one combined m divider, which we treat as m2. */
391         .m1 = { .min = 0, .max = 0 },
392         .m2 = { .min = 0, .max = 254 },
393         .p = { .min = 5, .max = 80 },
394         .p1 = { .min = 1, .max = 8 },
395         .p2 = { .dot_limit = 200000,
396                 .p2_slow = 10, .p2_fast = 5 },
397 };
398
399 static const struct intel_limit intel_limits_pineview_lvds = {
400         .dot = { .min = 20000, .max = 400000 },
401         .vco = { .min = 1700000, .max = 3500000 },
402         .n = { .min = 3, .max = 6 },
403         .m = { .min = 2, .max = 256 },
404         .m1 = { .min = 0, .max = 0 },
405         .m2 = { .min = 0, .max = 254 },
406         .p = { .min = 7, .max = 112 },
407         .p1 = { .min = 1, .max = 8 },
408         .p2 = { .dot_limit = 112000,
409                 .p2_slow = 14, .p2_fast = 14 },
410 };
411
412 /* Ironlake / Sandybridge
413  *
414  * We calculate clock using (register_value + 2) for N/M1/M2, so here
415  * the range value for them is (actual_value - 2).
416  */
417 static const struct intel_limit intel_limits_ironlake_dac = {
418         .dot = { .min = 25000, .max = 350000 },
419         .vco = { .min = 1760000, .max = 3510000 },
420         .n = { .min = 1, .max = 5 },
421         .m = { .min = 79, .max = 127 },
422         .m1 = { .min = 12, .max = 22 },
423         .m2 = { .min = 5, .max = 9 },
424         .p = { .min = 5, .max = 80 },
425         .p1 = { .min = 1, .max = 8 },
426         .p2 = { .dot_limit = 225000,
427                 .p2_slow = 10, .p2_fast = 5 },
428 };
429
430 static const struct intel_limit intel_limits_ironlake_single_lvds = {
431         .dot = { .min = 25000, .max = 350000 },
432         .vco = { .min = 1760000, .max = 3510000 },
433         .n = { .min = 1, .max = 3 },
434         .m = { .min = 79, .max = 118 },
435         .m1 = { .min = 12, .max = 22 },
436         .m2 = { .min = 5, .max = 9 },
437         .p = { .min = 28, .max = 112 },
438         .p1 = { .min = 2, .max = 8 },
439         .p2 = { .dot_limit = 225000,
440                 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
444         .dot = { .min = 25000, .max = 350000 },
445         .vco = { .min = 1760000, .max = 3510000 },
446         .n = { .min = 1, .max = 3 },
447         .m = { .min = 79, .max = 127 },
448         .m1 = { .min = 12, .max = 22 },
449         .m2 = { .min = 5, .max = 9 },
450         .p = { .min = 14, .max = 56 },
451         .p1 = { .min = 2, .max = 8 },
452         .p2 = { .dot_limit = 225000,
453                 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 /* LVDS 100mhz refclk limits. */
457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
458         .dot = { .min = 25000, .max = 350000 },
459         .vco = { .min = 1760000, .max = 3510000 },
460         .n = { .min = 1, .max = 2 },
461         .m = { .min = 79, .max = 126 },
462         .m1 = { .min = 12, .max = 22 },
463         .m2 = { .min = 5, .max = 9 },
464         .p = { .min = 28, .max = 112 },
465         .p1 = { .min = 2, .max = 8 },
466         .p2 = { .dot_limit = 225000,
467                 .p2_slow = 14, .p2_fast = 14 },
468 };
469
470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
471         .dot = { .min = 25000, .max = 350000 },
472         .vco = { .min = 1760000, .max = 3510000 },
473         .n = { .min = 1, .max = 3 },
474         .m = { .min = 79, .max = 126 },
475         .m1 = { .min = 12, .max = 22 },
476         .m2 = { .min = 5, .max = 9 },
477         .p = { .min = 14, .max = 42 },
478         .p1 = { .min = 2, .max = 6 },
479         .p2 = { .dot_limit = 225000,
480                 .p2_slow = 7, .p2_fast = 7 },
481 };
482
483 static const struct intel_limit intel_limits_vlv = {
484          /*
485           * These are the data rate limits (measured in fast clocks)
486           * since those are the strictest limits we have. The fast
487           * clock and actual rate limits are more relaxed, so checking
488           * them would make no difference.
489           */
490         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
491         .vco = { .min = 4000000, .max = 6000000 },
492         .n = { .min = 1, .max = 7 },
493         .m1 = { .min = 2, .max = 3 },
494         .m2 = { .min = 11, .max = 156 },
495         .p1 = { .min = 2, .max = 3 },
496         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
497 };
498
499 static const struct intel_limit intel_limits_chv = {
500         /*
501          * These are the data rate limits (measured in fast clocks)
502          * since those are the strictest limits we have.  The fast
503          * clock and actual rate limits are more relaxed, so checking
504          * them would make no difference.
505          */
506         .dot = { .min = 25000 * 5, .max = 540000 * 5},
507         .vco = { .min = 4800000, .max = 6480000 },
508         .n = { .min = 1, .max = 1 },
509         .m1 = { .min = 2, .max = 2 },
510         .m2 = { .min = 24 << 22, .max = 175 << 22 },
511         .p1 = { .min = 2, .max = 4 },
512         .p2 = { .p2_slow = 1, .p2_fast = 14 },
513 };
514
515 static const struct intel_limit intel_limits_bxt = {
516         /* FIXME: find real dot limits */
517         .dot = { .min = 0, .max = INT_MAX },
518         .vco = { .min = 4800000, .max = 6700000 },
519         .n = { .min = 1, .max = 1 },
520         .m1 = { .min = 2, .max = 2 },
521         /* FIXME: find real m2 limits */
522         .m2 = { .min = 2 << 22, .max = 255 << 22 },
523         .p1 = { .min = 2, .max = 4 },
524         .p2 = { .p2_slow = 1, .p2_fast = 20 },
525 };
526
527 static bool
528 needs_modeset(struct drm_crtc_state *state)
529 {
530         return drm_atomic_crtc_needs_modeset(state);
531 }
532
533 /*
534  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
535  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
536  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
537  * The helpers' return value is the rate of the clock that is fed to the
538  * display engine's pipe which can be the above fast dot clock rate or a
539  * divided-down version of it.
540  */
541 /* m1 is reserved as 0 in Pineview, n is a ring counter */
542 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
543 {
544         clock->m = clock->m2 + 2;
545         clock->p = clock->p1 * clock->p2;
546         if (WARN_ON(clock->n == 0 || clock->p == 0))
547                 return 0;
548         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
549         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
550
551         return clock->dot;
552 }
553
554 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
555 {
556         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
557 }
558
559 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
560 {
561         clock->m = i9xx_dpll_compute_m(clock);
562         clock->p = clock->p1 * clock->p2;
563         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
564                 return 0;
565         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
566         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
567
568         return clock->dot;
569 }
570
571 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
572 {
573         clock->m = clock->m1 * clock->m2;
574         clock->p = clock->p1 * clock->p2;
575         if (WARN_ON(clock->n == 0 || clock->p == 0))
576                 return 0;
577         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
578         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
579
580         return clock->dot / 5;
581 }
582
583 int chv_calc_dpll_params(int refclk, struct dpll *clock)
584 {
585         clock->m = clock->m1 * clock->m2;
586         clock->p = clock->p1 * clock->p2;
587         if (WARN_ON(clock->n == 0 || clock->p == 0))
588                 return 0;
589         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
590                         clock->n << 22);
591         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
592
593         return clock->dot / 5;
594 }
595
596 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
597 /**
598  * Returns whether the given set of divisors are valid for a given refclk with
599  * the given connectors.
600  */
601
602 static bool intel_PLL_is_valid(struct drm_device *dev,
603                                const struct intel_limit *limit,
604                                const struct dpll *clock)
605 {
606         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
607                 INTELPllInvalid("n out of range\n");
608         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
609                 INTELPllInvalid("p1 out of range\n");
610         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
611                 INTELPllInvalid("m2 out of range\n");
612         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
613                 INTELPllInvalid("m1 out of range\n");
614
615         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
616             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
617                 if (clock->m1 <= clock->m2)
618                         INTELPllInvalid("m1 <= m2\n");
619
620         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
621                 if (clock->p < limit->p.min || limit->p.max < clock->p)
622                         INTELPllInvalid("p out of range\n");
623                 if (clock->m < limit->m.min || limit->m.max < clock->m)
624                         INTELPllInvalid("m out of range\n");
625         }
626
627         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
628                 INTELPllInvalid("vco out of range\n");
629         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630          * connector, etc., rather than just a single range.
631          */
632         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
633                 INTELPllInvalid("dot out of range\n");
634
635         return true;
636 }
637
638 static int
639 i9xx_select_p2_div(const struct intel_limit *limit,
640                    const struct intel_crtc_state *crtc_state,
641                    int target)
642 {
643         struct drm_device *dev = crtc_state->base.crtc->dev;
644
645         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
646                 /*
647                  * For LVDS just rely on its current settings for dual-channel.
648                  * We haven't figured out how to reliably set up different
649                  * single/dual channel state, if we even can.
650                  */
651                 if (intel_is_dual_link_lvds(dev))
652                         return limit->p2.p2_fast;
653                 else
654                         return limit->p2.p2_slow;
655         } else {
656                 if (target < limit->p2.dot_limit)
657                         return limit->p2.p2_slow;
658                 else
659                         return limit->p2.p2_fast;
660         }
661 }
662
663 /*
664  * Returns a set of divisors for the desired target clock with the given
665  * refclk, or FALSE.  The returned values represent the clock equation:
666  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
667  *
668  * Target and reference clocks are specified in kHz.
669  *
670  * If match_clock is provided, then best_clock P divider must match the P
671  * divider from @match_clock used for LVDS downclocking.
672  */
673 static bool
674 i9xx_find_best_dpll(const struct intel_limit *limit,
675                     struct intel_crtc_state *crtc_state,
676                     int target, int refclk, struct dpll *match_clock,
677                     struct dpll *best_clock)
678 {
679         struct drm_device *dev = crtc_state->base.crtc->dev;
680         struct dpll clock;
681         int err = target;
682
683         memset(best_clock, 0, sizeof(*best_clock));
684
685         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
686
687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688              clock.m1++) {
689                 for (clock.m2 = limit->m2.min;
690                      clock.m2 <= limit->m2.max; clock.m2++) {
691                         if (clock.m2 >= clock.m1)
692                                 break;
693                         for (clock.n = limit->n.min;
694                              clock.n <= limit->n.max; clock.n++) {
695                                 for (clock.p1 = limit->p1.min;
696                                         clock.p1 <= limit->p1.max; clock.p1++) {
697                                         int this_err;
698
699                                         i9xx_calc_dpll_params(refclk, &clock);
700                                         if (!intel_PLL_is_valid(dev, limit,
701                                                                 &clock))
702                                                 continue;
703                                         if (match_clock &&
704                                             clock.p != match_clock->p)
705                                                 continue;
706
707                                         this_err = abs(clock.dot - target);
708                                         if (this_err < err) {
709                                                 *best_clock = clock;
710                                                 err = this_err;
711                                         }
712                                 }
713                         }
714                 }
715         }
716
717         return (err != target);
718 }
719
720 /*
721  * Returns a set of divisors for the desired target clock with the given
722  * refclk, or FALSE.  The returned values represent the clock equation:
723  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
724  *
725  * Target and reference clocks are specified in kHz.
726  *
727  * If match_clock is provided, then best_clock P divider must match the P
728  * divider from @match_clock used for LVDS downclocking.
729  */
730 static bool
731 pnv_find_best_dpll(const struct intel_limit *limit,
732                    struct intel_crtc_state *crtc_state,
733                    int target, int refclk, struct dpll *match_clock,
734                    struct dpll *best_clock)
735 {
736         struct drm_device *dev = crtc_state->base.crtc->dev;
737         struct dpll clock;
738         int err = target;
739
740         memset(best_clock, 0, sizeof(*best_clock));
741
742         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
743
744         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
745              clock.m1++) {
746                 for (clock.m2 = limit->m2.min;
747                      clock.m2 <= limit->m2.max; clock.m2++) {
748                         for (clock.n = limit->n.min;
749                              clock.n <= limit->n.max; clock.n++) {
750                                 for (clock.p1 = limit->p1.min;
751                                         clock.p1 <= limit->p1.max; clock.p1++) {
752                                         int this_err;
753
754                                         pnv_calc_dpll_params(refclk, &clock);
755                                         if (!intel_PLL_is_valid(dev, limit,
756                                                                 &clock))
757                                                 continue;
758                                         if (match_clock &&
759                                             clock.p != match_clock->p)
760                                                 continue;
761
762                                         this_err = abs(clock.dot - target);
763                                         if (this_err < err) {
764                                                 *best_clock = clock;
765                                                 err = this_err;
766                                         }
767                                 }
768                         }
769                 }
770         }
771
772         return (err != target);
773 }
774
775 /*
776  * Returns a set of divisors for the desired target clock with the given
777  * refclk, or FALSE.  The returned values represent the clock equation:
778  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
779  *
780  * Target and reference clocks are specified in kHz.
781  *
782  * If match_clock is provided, then best_clock P divider must match the P
783  * divider from @match_clock used for LVDS downclocking.
784  */
785 static bool
786 g4x_find_best_dpll(const struct intel_limit *limit,
787                    struct intel_crtc_state *crtc_state,
788                    int target, int refclk, struct dpll *match_clock,
789                    struct dpll *best_clock)
790 {
791         struct drm_device *dev = crtc_state->base.crtc->dev;
792         struct dpll clock;
793         int max_n;
794         bool found = false;
795         /* approximately equals target * 0.00585 */
796         int err_most = (target >> 8) + (target >> 9);
797
798         memset(best_clock, 0, sizeof(*best_clock));
799
800         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
801
802         max_n = limit->n.max;
803         /* based on hardware requirement, prefer smaller n to precision */
804         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
805                 /* based on hardware requirement, prefere larger m1,m2 */
806                 for (clock.m1 = limit->m1.max;
807                      clock.m1 >= limit->m1.min; clock.m1--) {
808                         for (clock.m2 = limit->m2.max;
809                              clock.m2 >= limit->m2.min; clock.m2--) {
810                                 for (clock.p1 = limit->p1.max;
811                                      clock.p1 >= limit->p1.min; clock.p1--) {
812                                         int this_err;
813
814                                         i9xx_calc_dpll_params(refclk, &clock);
815                                         if (!intel_PLL_is_valid(dev, limit,
816                                                                 &clock))
817                                                 continue;
818
819                                         this_err = abs(clock.dot - target);
820                                         if (this_err < err_most) {
821                                                 *best_clock = clock;
822                                                 err_most = this_err;
823                                                 max_n = clock.n;
824                                                 found = true;
825                                         }
826                                 }
827                         }
828                 }
829         }
830         return found;
831 }
832
833 /*
834  * Check if the calculated PLL configuration is more optimal compared to the
835  * best configuration and error found so far. Return the calculated error.
836  */
837 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
838                                const struct dpll *calculated_clock,
839                                const struct dpll *best_clock,
840                                unsigned int best_error_ppm,
841                                unsigned int *error_ppm)
842 {
843         /*
844          * For CHV ignore the error and consider only the P value.
845          * Prefer a bigger P value based on HW requirements.
846          */
847         if (IS_CHERRYVIEW(dev)) {
848                 *error_ppm = 0;
849
850                 return calculated_clock->p > best_clock->p;
851         }
852
853         if (WARN_ON_ONCE(!target_freq))
854                 return false;
855
856         *error_ppm = div_u64(1000000ULL *
857                                 abs(target_freq - calculated_clock->dot),
858                              target_freq);
859         /*
860          * Prefer a better P value over a better (smaller) error if the error
861          * is small. Ensure this preference for future configurations too by
862          * setting the error to 0.
863          */
864         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
865                 *error_ppm = 0;
866
867                 return true;
868         }
869
870         return *error_ppm + 10 < best_error_ppm;
871 }
872
873 /*
874  * Returns a set of divisors for the desired target clock with the given
875  * refclk, or FALSE.  The returned values represent the clock equation:
876  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
877  */
878 static bool
879 vlv_find_best_dpll(const struct intel_limit *limit,
880                    struct intel_crtc_state *crtc_state,
881                    int target, int refclk, struct dpll *match_clock,
882                    struct dpll *best_clock)
883 {
884         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
885         struct drm_device *dev = crtc->base.dev;
886         struct dpll clock;
887         unsigned int bestppm = 1000000;
888         /* min update 19.2 MHz */
889         int max_n = min(limit->n.max, refclk / 19200);
890         bool found = false;
891
892         target *= 5; /* fast clock */
893
894         memset(best_clock, 0, sizeof(*best_clock));
895
896         /* based on hardware requirement, prefer smaller n to precision */
897         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
898                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
899                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
900                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
901                                 clock.p = clock.p1 * clock.p2;
902                                 /* based on hardware requirement, prefer bigger m1,m2 values */
903                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
904                                         unsigned int ppm;
905
906                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
907                                                                      refclk * clock.m1);
908
909                                         vlv_calc_dpll_params(refclk, &clock);
910
911                                         if (!intel_PLL_is_valid(dev, limit,
912                                                                 &clock))
913                                                 continue;
914
915                                         if (!vlv_PLL_is_optimal(dev, target,
916                                                                 &clock,
917                                                                 best_clock,
918                                                                 bestppm, &ppm))
919                                                 continue;
920
921                                         *best_clock = clock;
922                                         bestppm = ppm;
923                                         found = true;
924                                 }
925                         }
926                 }
927         }
928
929         return found;
930 }
931
932 /*
933  * Returns a set of divisors for the desired target clock with the given
934  * refclk, or FALSE.  The returned values represent the clock equation:
935  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
936  */
937 static bool
938 chv_find_best_dpll(const struct intel_limit *limit,
939                    struct intel_crtc_state *crtc_state,
940                    int target, int refclk, struct dpll *match_clock,
941                    struct dpll *best_clock)
942 {
943         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
944         struct drm_device *dev = crtc->base.dev;
945         unsigned int best_error_ppm;
946         struct dpll clock;
947         uint64_t m2;
948         int found = false;
949
950         memset(best_clock, 0, sizeof(*best_clock));
951         best_error_ppm = 1000000;
952
953         /*
954          * Based on hardware doc, the n always set to 1, and m1 always
955          * set to 2.  If requires to support 200Mhz refclk, we need to
956          * revisit this because n may not 1 anymore.
957          */
958         clock.n = 1, clock.m1 = 2;
959         target *= 5;    /* fast clock */
960
961         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
962                 for (clock.p2 = limit->p2.p2_fast;
963                                 clock.p2 >= limit->p2.p2_slow;
964                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
965                         unsigned int error_ppm;
966
967                         clock.p = clock.p1 * clock.p2;
968
969                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
970                                         clock.n) << 22, refclk * clock.m1);
971
972                         if (m2 > INT_MAX/clock.m1)
973                                 continue;
974
975                         clock.m2 = m2;
976
977                         chv_calc_dpll_params(refclk, &clock);
978
979                         if (!intel_PLL_is_valid(dev, limit, &clock))
980                                 continue;
981
982                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
983                                                 best_error_ppm, &error_ppm))
984                                 continue;
985
986                         *best_clock = clock;
987                         best_error_ppm = error_ppm;
988                         found = true;
989                 }
990         }
991
992         return found;
993 }
994
995 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
996                         struct dpll *best_clock)
997 {
998         int refclk = 100000;
999         const struct intel_limit *limit = &intel_limits_bxt;
1000
1001         return chv_find_best_dpll(limit, crtc_state,
1002                                   target_clock, refclk, NULL, best_clock);
1003 }
1004
1005 bool intel_crtc_active(struct drm_crtc *crtc)
1006 {
1007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1008
1009         /* Be paranoid as we can arrive here with only partial
1010          * state retrieved from the hardware during setup.
1011          *
1012          * We can ditch the adjusted_mode.crtc_clock check as soon
1013          * as Haswell has gained clock readout/fastboot support.
1014          *
1015          * We can ditch the crtc->primary->fb check as soon as we can
1016          * properly reconstruct framebuffers.
1017          *
1018          * FIXME: The intel_crtc->active here should be switched to
1019          * crtc->state->active once we have proper CRTC states wired up
1020          * for atomic.
1021          */
1022         return intel_crtc->active && crtc->primary->state->fb &&
1023                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1024 }
1025
1026 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1027                                              enum pipe pipe)
1028 {
1029         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1031
1032         return intel_crtc->config->cpu_transcoder;
1033 }
1034
1035 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1036 {
1037         struct drm_i915_private *dev_priv = to_i915(dev);
1038         i915_reg_t reg = PIPEDSL(pipe);
1039         u32 line1, line2;
1040         u32 line_mask;
1041
1042         if (IS_GEN2(dev))
1043                 line_mask = DSL_LINEMASK_GEN2;
1044         else
1045                 line_mask = DSL_LINEMASK_GEN3;
1046
1047         line1 = I915_READ(reg) & line_mask;
1048         msleep(5);
1049         line2 = I915_READ(reg) & line_mask;
1050
1051         return line1 == line2;
1052 }
1053
1054 /*
1055  * intel_wait_for_pipe_off - wait for pipe to turn off
1056  * @crtc: crtc whose pipe to wait for
1057  *
1058  * After disabling a pipe, we can't wait for vblank in the usual way,
1059  * spinning on the vblank interrupt status bit, since we won't actually
1060  * see an interrupt when the pipe is disabled.
1061  *
1062  * On Gen4 and above:
1063  *   wait for the pipe register state bit to turn off
1064  *
1065  * Otherwise:
1066  *   wait for the display line value to settle (it usually
1067  *   ends up stopping at the start of the next frame).
1068  *
1069  */
1070 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1071 {
1072         struct drm_device *dev = crtc->base.dev;
1073         struct drm_i915_private *dev_priv = to_i915(dev);
1074         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1075         enum pipe pipe = crtc->pipe;
1076
1077         if (INTEL_INFO(dev)->gen >= 4) {
1078                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1079
1080                 /* Wait for the Pipe State to go off */
1081                 if (intel_wait_for_register(dev_priv,
1082                                             reg, I965_PIPECONF_ACTIVE, 0,
1083                                             100))
1084                         WARN(1, "pipe_off wait timed out\n");
1085         } else {
1086                 /* Wait for the display line to settle */
1087                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1088                         WARN(1, "pipe_off wait timed out\n");
1089         }
1090 }
1091
1092 /* Only for pre-ILK configs */
1093 void assert_pll(struct drm_i915_private *dev_priv,
1094                 enum pipe pipe, bool state)
1095 {
1096         u32 val;
1097         bool cur_state;
1098
1099         val = I915_READ(DPLL(pipe));
1100         cur_state = !!(val & DPLL_VCO_ENABLE);
1101         I915_STATE_WARN(cur_state != state,
1102              "PLL state assertion failure (expected %s, current %s)\n",
1103                         onoff(state), onoff(cur_state));
1104 }
1105
1106 /* XXX: the dsi pll is shared between MIPI DSI ports */
1107 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1108 {
1109         u32 val;
1110         bool cur_state;
1111
1112         mutex_lock(&dev_priv->sb_lock);
1113         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1114         mutex_unlock(&dev_priv->sb_lock);
1115
1116         cur_state = val & DSI_PLL_VCO_EN;
1117         I915_STATE_WARN(cur_state != state,
1118              "DSI PLL state assertion failure (expected %s, current %s)\n",
1119                         onoff(state), onoff(cur_state));
1120 }
1121
1122 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1123                           enum pipe pipe, bool state)
1124 {
1125         bool cur_state;
1126         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1127                                                                       pipe);
1128
1129         if (HAS_DDI(dev_priv)) {
1130                 /* DDI does not have a specific FDI_TX register */
1131                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1132                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133         } else {
1134                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1135                 cur_state = !!(val & FDI_TX_ENABLE);
1136         }
1137         I915_STATE_WARN(cur_state != state,
1138              "FDI TX state assertion failure (expected %s, current %s)\n",
1139                         onoff(state), onoff(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145                           enum pipe pipe, bool state)
1146 {
1147         u32 val;
1148         bool cur_state;
1149
1150         val = I915_READ(FDI_RX_CTL(pipe));
1151         cur_state = !!(val & FDI_RX_ENABLE);
1152         I915_STATE_WARN(cur_state != state,
1153              "FDI RX state assertion failure (expected %s, current %s)\n",
1154                         onoff(state), onoff(cur_state));
1155 }
1156 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158
1159 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1160                                       enum pipe pipe)
1161 {
1162         u32 val;
1163
1164         /* ILK FDI PLL is always enabled */
1165         if (IS_GEN5(dev_priv))
1166                 return;
1167
1168         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169         if (HAS_DDI(dev_priv))
1170                 return;
1171
1172         val = I915_READ(FDI_TX_CTL(pipe));
1173         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1174 }
1175
1176 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1177                        enum pipe pipe, bool state)
1178 {
1179         u32 val;
1180         bool cur_state;
1181
1182         val = I915_READ(FDI_RX_CTL(pipe));
1183         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1184         I915_STATE_WARN(cur_state != state,
1185              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186                         onoff(state), onoff(cur_state));
1187 }
1188
1189 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1190                            enum pipe pipe)
1191 {
1192         struct drm_device *dev = &dev_priv->drm;
1193         i915_reg_t pp_reg;
1194         u32 val;
1195         enum pipe panel_pipe = PIPE_A;
1196         bool locked = true;
1197
1198         if (WARN_ON(HAS_DDI(dev)))
1199                 return;
1200
1201         if (HAS_PCH_SPLIT(dev)) {
1202                 u32 port_sel;
1203
1204                 pp_reg = PCH_PP_CONTROL;
1205                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1206
1207                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1208                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1209                         panel_pipe = PIPE_B;
1210                 /* XXX: else fix for eDP */
1211         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1212                 /* presumably write lock depends on pipe, not port select */
1213                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1214                 panel_pipe = pipe;
1215         } else {
1216                 pp_reg = PP_CONTROL;
1217                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1218                         panel_pipe = PIPE_B;
1219         }
1220
1221         val = I915_READ(pp_reg);
1222         if (!(val & PANEL_POWER_ON) ||
1223             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1224                 locked = false;
1225
1226         I915_STATE_WARN(panel_pipe == pipe && locked,
1227              "panel assertion failure, pipe %c regs locked\n",
1228              pipe_name(pipe));
1229 }
1230
1231 static void assert_cursor(struct drm_i915_private *dev_priv,
1232                           enum pipe pipe, bool state)
1233 {
1234         struct drm_device *dev = &dev_priv->drm;
1235         bool cur_state;
1236
1237         if (IS_845G(dev) || IS_I865G(dev))
1238                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1239         else
1240                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1241
1242         I915_STATE_WARN(cur_state != state,
1243              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1244                         pipe_name(pipe), onoff(state), onoff(cur_state));
1245 }
1246 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1247 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1248
1249 void assert_pipe(struct drm_i915_private *dev_priv,
1250                  enum pipe pipe, bool state)
1251 {
1252         bool cur_state;
1253         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1254                                                                       pipe);
1255         enum intel_display_power_domain power_domain;
1256
1257         /* if we need the pipe quirk it must be always on */
1258         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1259             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1260                 state = true;
1261
1262         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1263         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1264                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1265                 cur_state = !!(val & PIPECONF_ENABLE);
1266
1267                 intel_display_power_put(dev_priv, power_domain);
1268         } else {
1269                 cur_state = false;
1270         }
1271
1272         I915_STATE_WARN(cur_state != state,
1273              "pipe %c assertion failure (expected %s, current %s)\n",
1274                         pipe_name(pipe), onoff(state), onoff(cur_state));
1275 }
1276
1277 static void assert_plane(struct drm_i915_private *dev_priv,
1278                          enum plane plane, bool state)
1279 {
1280         u32 val;
1281         bool cur_state;
1282
1283         val = I915_READ(DSPCNTR(plane));
1284         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1285         I915_STATE_WARN(cur_state != state,
1286              "plane %c assertion failure (expected %s, current %s)\n",
1287                         plane_name(plane), onoff(state), onoff(cur_state));
1288 }
1289
1290 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1291 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1292
1293 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1294                                    enum pipe pipe)
1295 {
1296         struct drm_device *dev = &dev_priv->drm;
1297         int i;
1298
1299         /* Primary planes are fixed to pipes on gen4+ */
1300         if (INTEL_INFO(dev)->gen >= 4) {
1301                 u32 val = I915_READ(DSPCNTR(pipe));
1302                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1303                      "plane %c assertion failure, should be disabled but not\n",
1304                      plane_name(pipe));
1305                 return;
1306         }
1307
1308         /* Need to check both planes against the pipe */
1309         for_each_pipe(dev_priv, i) {
1310                 u32 val = I915_READ(DSPCNTR(i));
1311                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1312                         DISPPLANE_SEL_PIPE_SHIFT;
1313                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1314                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1315                      plane_name(i), pipe_name(pipe));
1316         }
1317 }
1318
1319 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1320                                     enum pipe pipe)
1321 {
1322         struct drm_device *dev = &dev_priv->drm;
1323         int sprite;
1324
1325         if (INTEL_INFO(dev)->gen >= 9) {
1326                 for_each_sprite(dev_priv, pipe, sprite) {
1327                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1328                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1329                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1330                              sprite, pipe_name(pipe));
1331                 }
1332         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1333                 for_each_sprite(dev_priv, pipe, sprite) {
1334                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1335                         I915_STATE_WARN(val & SP_ENABLE,
1336                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337                              sprite_name(pipe, sprite), pipe_name(pipe));
1338                 }
1339         } else if (INTEL_INFO(dev)->gen >= 7) {
1340                 u32 val = I915_READ(SPRCTL(pipe));
1341                 I915_STATE_WARN(val & SPRITE_ENABLE,
1342                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1343                      plane_name(pipe), pipe_name(pipe));
1344         } else if (INTEL_INFO(dev)->gen >= 5) {
1345                 u32 val = I915_READ(DVSCNTR(pipe));
1346                 I915_STATE_WARN(val & DVS_ENABLE,
1347                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1348                      plane_name(pipe), pipe_name(pipe));
1349         }
1350 }
1351
1352 static void assert_vblank_disabled(struct drm_crtc *crtc)
1353 {
1354         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1355                 drm_crtc_vblank_put(crtc);
1356 }
1357
1358 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1359                                     enum pipe pipe)
1360 {
1361         u32 val;
1362         bool enabled;
1363
1364         val = I915_READ(PCH_TRANSCONF(pipe));
1365         enabled = !!(val & TRANS_ENABLE);
1366         I915_STATE_WARN(enabled,
1367              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1368              pipe_name(pipe));
1369 }
1370
1371 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1372                             enum pipe pipe, u32 port_sel, u32 val)
1373 {
1374         if ((val & DP_PORT_EN) == 0)
1375                 return false;
1376
1377         if (HAS_PCH_CPT(dev_priv)) {
1378                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1379                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1380                         return false;
1381         } else if (IS_CHERRYVIEW(dev_priv)) {
1382                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1383                         return false;
1384         } else {
1385                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1386                         return false;
1387         }
1388         return true;
1389 }
1390
1391 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1392                               enum pipe pipe, u32 val)
1393 {
1394         if ((val & SDVO_ENABLE) == 0)
1395                 return false;
1396
1397         if (HAS_PCH_CPT(dev_priv)) {
1398                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1399                         return false;
1400         } else if (IS_CHERRYVIEW(dev_priv)) {
1401                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1402                         return false;
1403         } else {
1404                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1405                         return false;
1406         }
1407         return true;
1408 }
1409
1410 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1411                               enum pipe pipe, u32 val)
1412 {
1413         if ((val & LVDS_PORT_EN) == 0)
1414                 return false;
1415
1416         if (HAS_PCH_CPT(dev_priv)) {
1417                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1418                         return false;
1419         } else {
1420                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1421                         return false;
1422         }
1423         return true;
1424 }
1425
1426 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1427                               enum pipe pipe, u32 val)
1428 {
1429         if ((val & ADPA_DAC_ENABLE) == 0)
1430                 return false;
1431         if (HAS_PCH_CPT(dev_priv)) {
1432                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1433                         return false;
1434         } else {
1435                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1436                         return false;
1437         }
1438         return true;
1439 }
1440
1441 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1442                                    enum pipe pipe, i915_reg_t reg,
1443                                    u32 port_sel)
1444 {
1445         u32 val = I915_READ(reg);
1446         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1447              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1448              i915_mmio_reg_offset(reg), pipe_name(pipe));
1449
1450         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1451              && (val & DP_PIPEB_SELECT),
1452              "IBX PCH dp port still using transcoder B\n");
1453 }
1454
1455 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1456                                      enum pipe pipe, i915_reg_t reg)
1457 {
1458         u32 val = I915_READ(reg);
1459         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1460              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1461              i915_mmio_reg_offset(reg), pipe_name(pipe));
1462
1463         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1464              && (val & SDVO_PIPE_B_SELECT),
1465              "IBX PCH hdmi port still using transcoder B\n");
1466 }
1467
1468 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1469                                       enum pipe pipe)
1470 {
1471         u32 val;
1472
1473         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1476
1477         val = I915_READ(PCH_ADPA);
1478         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1479              "PCH VGA enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         val = I915_READ(PCH_LVDS);
1483         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1484              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1485              pipe_name(pipe));
1486
1487         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1490 }
1491
1492 static void _vlv_enable_pll(struct intel_crtc *crtc,
1493                             const struct intel_crtc_state *pipe_config)
1494 {
1495         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1496         enum pipe pipe = crtc->pipe;
1497
1498         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1499         POSTING_READ(DPLL(pipe));
1500         udelay(150);
1501
1502         if (intel_wait_for_register(dev_priv,
1503                                     DPLL(pipe),
1504                                     DPLL_LOCK_VLV,
1505                                     DPLL_LOCK_VLV,
1506                                     1))
1507                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511                            const struct intel_crtc_state *pipe_config)
1512 {
1513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1514         enum pipe pipe = crtc->pipe;
1515
1516         assert_pipe_disabled(dev_priv, pipe);
1517
1518         /* PLL is protected by panel, make sure we can write it */
1519         assert_panel_unlocked(dev_priv, pipe);
1520
1521         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1522                 _vlv_enable_pll(crtc, pipe_config);
1523
1524         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1525         POSTING_READ(DPLL_MD(pipe));
1526 }
1527
1528
1529 static void _chv_enable_pll(struct intel_crtc *crtc,
1530                             const struct intel_crtc_state *pipe_config)
1531 {
1532         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1533         enum pipe pipe = crtc->pipe;
1534         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1535         u32 tmp;
1536
1537         mutex_lock(&dev_priv->sb_lock);
1538
1539         /* Enable back the 10bit clock to display controller */
1540         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1541         tmp |= DPIO_DCLKP_EN;
1542         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1543
1544         mutex_unlock(&dev_priv->sb_lock);
1545
1546         /*
1547          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1548          */
1549         udelay(1);
1550
1551         /* Enable PLL */
1552         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1553
1554         /* Check PLL is locked */
1555         if (intel_wait_for_register(dev_priv,
1556                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1557                                     1))
1558                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1559 }
1560
1561 static void chv_enable_pll(struct intel_crtc *crtc,
1562                            const struct intel_crtc_state *pipe_config)
1563 {
1564         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1565         enum pipe pipe = crtc->pipe;
1566
1567         assert_pipe_disabled(dev_priv, pipe);
1568
1569         /* PLL is protected by panel, make sure we can write it */
1570         assert_panel_unlocked(dev_priv, pipe);
1571
1572         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1573                 _chv_enable_pll(crtc, pipe_config);
1574
1575         if (pipe != PIPE_A) {
1576                 /*
1577                  * WaPixelRepeatModeFixForC0:chv
1578                  *
1579                  * DPLLCMD is AWOL. Use chicken bits to propagate
1580                  * the value from DPLLBMD to either pipe B or C.
1581                  */
1582                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1583                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1584                 I915_WRITE(CBR4_VLV, 0);
1585                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1586
1587                 /*
1588                  * DPLLB VGA mode also seems to cause problems.
1589                  * We should always have it disabled.
1590                  */
1591                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1592         } else {
1593                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1594                 POSTING_READ(DPLL_MD(pipe));
1595         }
1596 }
1597
1598 static int intel_num_dvo_pipes(struct drm_device *dev)
1599 {
1600         struct intel_crtc *crtc;
1601         int count = 0;
1602
1603         for_each_intel_crtc(dev, crtc) {
1604                 count += crtc->base.state->active &&
1605                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1606         }
1607
1608         return count;
1609 }
1610
1611 static void i9xx_enable_pll(struct intel_crtc *crtc)
1612 {
1613         struct drm_device *dev = crtc->base.dev;
1614         struct drm_i915_private *dev_priv = to_i915(dev);
1615         i915_reg_t reg = DPLL(crtc->pipe);
1616         u32 dpll = crtc->config->dpll_hw_state.dpll;
1617
1618         assert_pipe_disabled(dev_priv, crtc->pipe);
1619
1620         /* PLL is protected by panel, make sure we can write it */
1621         if (IS_MOBILE(dev) && !IS_I830(dev))
1622                 assert_panel_unlocked(dev_priv, crtc->pipe);
1623
1624         /* Enable DVO 2x clock on both PLLs if necessary */
1625         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1626                 /*
1627                  * It appears to be important that we don't enable this
1628                  * for the current pipe before otherwise configuring the
1629                  * PLL. No idea how this should be handled if multiple
1630                  * DVO outputs are enabled simultaneosly.
1631                  */
1632                 dpll |= DPLL_DVO_2X_MODE;
1633                 I915_WRITE(DPLL(!crtc->pipe),
1634                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1635         }
1636
1637         /*
1638          * Apparently we need to have VGA mode enabled prior to changing
1639          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1640          * dividers, even though the register value does change.
1641          */
1642         I915_WRITE(reg, 0);
1643
1644         I915_WRITE(reg, dpll);
1645
1646         /* Wait for the clocks to stabilize. */
1647         POSTING_READ(reg);
1648         udelay(150);
1649
1650         if (INTEL_INFO(dev)->gen >= 4) {
1651                 I915_WRITE(DPLL_MD(crtc->pipe),
1652                            crtc->config->dpll_hw_state.dpll_md);
1653         } else {
1654                 /* The pixel multiplier can only be updated once the
1655                  * DPLL is enabled and the clocks are stable.
1656                  *
1657                  * So write it again.
1658                  */
1659                 I915_WRITE(reg, dpll);
1660         }
1661
1662         /* We do this three times for luck */
1663         I915_WRITE(reg, dpll);
1664         POSTING_READ(reg);
1665         udelay(150); /* wait for warmup */
1666         I915_WRITE(reg, dpll);
1667         POSTING_READ(reg);
1668         udelay(150); /* wait for warmup */
1669         I915_WRITE(reg, dpll);
1670         POSTING_READ(reg);
1671         udelay(150); /* wait for warmup */
1672 }
1673
1674 /**
1675  * i9xx_disable_pll - disable a PLL
1676  * @dev_priv: i915 private structure
1677  * @pipe: pipe PLL to disable
1678  *
1679  * Disable the PLL for @pipe, making sure the pipe is off first.
1680  *
1681  * Note!  This is for pre-ILK only.
1682  */
1683 static void i9xx_disable_pll(struct intel_crtc *crtc)
1684 {
1685         struct drm_device *dev = crtc->base.dev;
1686         struct drm_i915_private *dev_priv = to_i915(dev);
1687         enum pipe pipe = crtc->pipe;
1688
1689         /* Disable DVO 2x clock on both PLLs if necessary */
1690         if (IS_I830(dev) &&
1691             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1692             !intel_num_dvo_pipes(dev)) {
1693                 I915_WRITE(DPLL(PIPE_B),
1694                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1695                 I915_WRITE(DPLL(PIPE_A),
1696                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1697         }
1698
1699         /* Don't disable pipe or pipe PLLs if needed */
1700         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1701             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1702                 return;
1703
1704         /* Make sure the pipe isn't still relying on us */
1705         assert_pipe_disabled(dev_priv, pipe);
1706
1707         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1708         POSTING_READ(DPLL(pipe));
1709 }
1710
1711 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1712 {
1713         u32 val;
1714
1715         /* Make sure the pipe isn't still relying on us */
1716         assert_pipe_disabled(dev_priv, pipe);
1717
1718         val = DPLL_INTEGRATED_REF_CLK_VLV |
1719                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1720         if (pipe != PIPE_A)
1721                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1722
1723         I915_WRITE(DPLL(pipe), val);
1724         POSTING_READ(DPLL(pipe));
1725 }
1726
1727 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1728 {
1729         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1730         u32 val;
1731
1732         /* Make sure the pipe isn't still relying on us */
1733         assert_pipe_disabled(dev_priv, pipe);
1734
1735         val = DPLL_SSC_REF_CLK_CHV |
1736                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1737         if (pipe != PIPE_A)
1738                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1739
1740         I915_WRITE(DPLL(pipe), val);
1741         POSTING_READ(DPLL(pipe));
1742
1743         mutex_lock(&dev_priv->sb_lock);
1744
1745         /* Disable 10bit clock to display controller */
1746         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1747         val &= ~DPIO_DCLKP_EN;
1748         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1749
1750         mutex_unlock(&dev_priv->sb_lock);
1751 }
1752
1753 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1754                          struct intel_digital_port *dport,
1755                          unsigned int expected_mask)
1756 {
1757         u32 port_mask;
1758         i915_reg_t dpll_reg;
1759
1760         switch (dport->port) {
1761         case PORT_B:
1762                 port_mask = DPLL_PORTB_READY_MASK;
1763                 dpll_reg = DPLL(0);
1764                 break;
1765         case PORT_C:
1766                 port_mask = DPLL_PORTC_READY_MASK;
1767                 dpll_reg = DPLL(0);
1768                 expected_mask <<= 4;
1769                 break;
1770         case PORT_D:
1771                 port_mask = DPLL_PORTD_READY_MASK;
1772                 dpll_reg = DPIO_PHY_STATUS;
1773                 break;
1774         default:
1775                 BUG();
1776         }
1777
1778         if (intel_wait_for_register(dev_priv,
1779                                     dpll_reg, port_mask, expected_mask,
1780                                     1000))
1781                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1782                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1783 }
1784
1785 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1786                                            enum pipe pipe)
1787 {
1788         struct drm_device *dev = &dev_priv->drm;
1789         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1791         i915_reg_t reg;
1792         uint32_t val, pipeconf_val;
1793
1794         /* Make sure PCH DPLL is enabled */
1795         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1796
1797         /* FDI must be feeding us bits for PCH ports */
1798         assert_fdi_tx_enabled(dev_priv, pipe);
1799         assert_fdi_rx_enabled(dev_priv, pipe);
1800
1801         if (HAS_PCH_CPT(dev)) {
1802                 /* Workaround: Set the timing override bit before enabling the
1803                  * pch transcoder. */
1804                 reg = TRANS_CHICKEN2(pipe);
1805                 val = I915_READ(reg);
1806                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1807                 I915_WRITE(reg, val);
1808         }
1809
1810         reg = PCH_TRANSCONF(pipe);
1811         val = I915_READ(reg);
1812         pipeconf_val = I915_READ(PIPECONF(pipe));
1813
1814         if (HAS_PCH_IBX(dev_priv)) {
1815                 /*
1816                  * Make the BPC in transcoder be consistent with
1817                  * that in pipeconf reg. For HDMI we must use 8bpc
1818                  * here for both 8bpc and 12bpc.
1819                  */
1820                 val &= ~PIPECONF_BPC_MASK;
1821                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1822                         val |= PIPECONF_8BPC;
1823                 else
1824                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1825         }
1826
1827         val &= ~TRANS_INTERLACE_MASK;
1828         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1829                 if (HAS_PCH_IBX(dev_priv) &&
1830                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1831                         val |= TRANS_LEGACY_INTERLACED_ILK;
1832                 else
1833                         val |= TRANS_INTERLACED;
1834         else
1835                 val |= TRANS_PROGRESSIVE;
1836
1837         I915_WRITE(reg, val | TRANS_ENABLE);
1838         if (intel_wait_for_register(dev_priv,
1839                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1840                                     100))
1841                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1842 }
1843
1844 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1845                                       enum transcoder cpu_transcoder)
1846 {
1847         u32 val, pipeconf_val;
1848
1849         /* FDI must be feeding us bits for PCH ports */
1850         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1851         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1852
1853         /* Workaround: set timing override bit. */
1854         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1855         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1856         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1857
1858         val = TRANS_ENABLE;
1859         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1860
1861         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1862             PIPECONF_INTERLACED_ILK)
1863                 val |= TRANS_INTERLACED;
1864         else
1865                 val |= TRANS_PROGRESSIVE;
1866
1867         I915_WRITE(LPT_TRANSCONF, val);
1868         if (intel_wait_for_register(dev_priv,
1869                                     LPT_TRANSCONF,
1870                                     TRANS_STATE_ENABLE,
1871                                     TRANS_STATE_ENABLE,
1872                                     100))
1873                 DRM_ERROR("Failed to enable PCH transcoder\n");
1874 }
1875
1876 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1877                                             enum pipe pipe)
1878 {
1879         struct drm_device *dev = &dev_priv->drm;
1880         i915_reg_t reg;
1881         uint32_t val;
1882
1883         /* FDI relies on the transcoder */
1884         assert_fdi_tx_disabled(dev_priv, pipe);
1885         assert_fdi_rx_disabled(dev_priv, pipe);
1886
1887         /* Ports must be off as well */
1888         assert_pch_ports_disabled(dev_priv, pipe);
1889
1890         reg = PCH_TRANSCONF(pipe);
1891         val = I915_READ(reg);
1892         val &= ~TRANS_ENABLE;
1893         I915_WRITE(reg, val);
1894         /* wait for PCH transcoder off, transcoder state */
1895         if (intel_wait_for_register(dev_priv,
1896                                     reg, TRANS_STATE_ENABLE, 0,
1897                                     50))
1898                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1899
1900         if (HAS_PCH_CPT(dev)) {
1901                 /* Workaround: Clear the timing override chicken bit again. */
1902                 reg = TRANS_CHICKEN2(pipe);
1903                 val = I915_READ(reg);
1904                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1905                 I915_WRITE(reg, val);
1906         }
1907 }
1908
1909 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1910 {
1911         u32 val;
1912
1913         val = I915_READ(LPT_TRANSCONF);
1914         val &= ~TRANS_ENABLE;
1915         I915_WRITE(LPT_TRANSCONF, val);
1916         /* wait for PCH transcoder off, transcoder state */
1917         if (intel_wait_for_register(dev_priv,
1918                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1919                                     50))
1920                 DRM_ERROR("Failed to disable PCH transcoder\n");
1921
1922         /* Workaround: clear timing override bit. */
1923         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1924         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1925         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1926 }
1927
1928 /**
1929  * intel_enable_pipe - enable a pipe, asserting requirements
1930  * @crtc: crtc responsible for the pipe
1931  *
1932  * Enable @crtc's pipe, making sure that various hardware specific requirements
1933  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1934  */
1935 static void intel_enable_pipe(struct intel_crtc *crtc)
1936 {
1937         struct drm_device *dev = crtc->base.dev;
1938         struct drm_i915_private *dev_priv = to_i915(dev);
1939         enum pipe pipe = crtc->pipe;
1940         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1941         enum pipe pch_transcoder;
1942         i915_reg_t reg;
1943         u32 val;
1944
1945         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1946
1947         assert_planes_disabled(dev_priv, pipe);
1948         assert_cursor_disabled(dev_priv, pipe);
1949         assert_sprites_disabled(dev_priv, pipe);
1950
1951         if (HAS_PCH_LPT(dev_priv))
1952                 pch_transcoder = TRANSCODER_A;
1953         else
1954                 pch_transcoder = pipe;
1955
1956         /*
1957          * A pipe without a PLL won't actually be able to drive bits from
1958          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1959          * need the check.
1960          */
1961         if (HAS_GMCH_DISPLAY(dev_priv))
1962                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1963                         assert_dsi_pll_enabled(dev_priv);
1964                 else
1965                         assert_pll_enabled(dev_priv, pipe);
1966         else {
1967                 if (crtc->config->has_pch_encoder) {
1968                         /* if driving the PCH, we need FDI enabled */
1969                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1970                         assert_fdi_tx_pll_enabled(dev_priv,
1971                                                   (enum pipe) cpu_transcoder);
1972                 }
1973                 /* FIXME: assert CPU port conditions for SNB+ */
1974         }
1975
1976         reg = PIPECONF(cpu_transcoder);
1977         val = I915_READ(reg);
1978         if (val & PIPECONF_ENABLE) {
1979                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1980                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1981                 return;
1982         }
1983
1984         I915_WRITE(reg, val | PIPECONF_ENABLE);
1985         POSTING_READ(reg);
1986
1987         /*
1988          * Until the pipe starts DSL will read as 0, which would cause
1989          * an apparent vblank timestamp jump, which messes up also the
1990          * frame count when it's derived from the timestamps. So let's
1991          * wait for the pipe to start properly before we call
1992          * drm_crtc_vblank_on()
1993          */
1994         if (dev->max_vblank_count == 0 &&
1995             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1996                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1997 }
1998
1999 /**
2000  * intel_disable_pipe - disable a pipe, asserting requirements
2001  * @crtc: crtc whose pipes is to be disabled
2002  *
2003  * Disable the pipe of @crtc, making sure that various hardware
2004  * specific requirements are met, if applicable, e.g. plane
2005  * disabled, panel fitter off, etc.
2006  *
2007  * Will wait until the pipe has shut down before returning.
2008  */
2009 static void intel_disable_pipe(struct intel_crtc *crtc)
2010 {
2011         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2012         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2013         enum pipe pipe = crtc->pipe;
2014         i915_reg_t reg;
2015         u32 val;
2016
2017         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2018
2019         /*
2020          * Make sure planes won't keep trying to pump pixels to us,
2021          * or we might hang the display.
2022          */
2023         assert_planes_disabled(dev_priv, pipe);
2024         assert_cursor_disabled(dev_priv, pipe);
2025         assert_sprites_disabled(dev_priv, pipe);
2026
2027         reg = PIPECONF(cpu_transcoder);
2028         val = I915_READ(reg);
2029         if ((val & PIPECONF_ENABLE) == 0)
2030                 return;
2031
2032         /*
2033          * Double wide has implications for planes
2034          * so best keep it disabled when not needed.
2035          */
2036         if (crtc->config->double_wide)
2037                 val &= ~PIPECONF_DOUBLE_WIDE;
2038
2039         /* Don't disable pipe or pipe PLLs if needed */
2040         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2041             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2042                 val &= ~PIPECONF_ENABLE;
2043
2044         I915_WRITE(reg, val);
2045         if ((val & PIPECONF_ENABLE) == 0)
2046                 intel_wait_for_pipe_off(crtc);
2047 }
2048
2049 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2050 {
2051         return IS_GEN2(dev_priv) ? 2048 : 4096;
2052 }
2053
2054 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2055                                            uint64_t fb_modifier, unsigned int cpp)
2056 {
2057         switch (fb_modifier) {
2058         case DRM_FORMAT_MOD_NONE:
2059                 return cpp;
2060         case I915_FORMAT_MOD_X_TILED:
2061                 if (IS_GEN2(dev_priv))
2062                         return 128;
2063                 else
2064                         return 512;
2065         case I915_FORMAT_MOD_Y_TILED:
2066                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2067                         return 128;
2068                 else
2069                         return 512;
2070         case I915_FORMAT_MOD_Yf_TILED:
2071                 switch (cpp) {
2072                 case 1:
2073                         return 64;
2074                 case 2:
2075                 case 4:
2076                         return 128;
2077                 case 8:
2078                 case 16:
2079                         return 256;
2080                 default:
2081                         MISSING_CASE(cpp);
2082                         return cpp;
2083                 }
2084                 break;
2085         default:
2086                 MISSING_CASE(fb_modifier);
2087                 return cpp;
2088         }
2089 }
2090
2091 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2092                                uint64_t fb_modifier, unsigned int cpp)
2093 {
2094         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2095                 return 1;
2096         else
2097                 return intel_tile_size(dev_priv) /
2098                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2099 }
2100
2101 /* Return the tile dimensions in pixel units */
2102 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2103                             unsigned int *tile_width,
2104                             unsigned int *tile_height,
2105                             uint64_t fb_modifier,
2106                             unsigned int cpp)
2107 {
2108         unsigned int tile_width_bytes =
2109                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2110
2111         *tile_width = tile_width_bytes / cpp;
2112         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2113 }
2114
2115 unsigned int
2116 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2117                       uint32_t pixel_format, uint64_t fb_modifier)
2118 {
2119         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2120         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2121
2122         return ALIGN(height, tile_height);
2123 }
2124
2125 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2126 {
2127         unsigned int size = 0;
2128         int i;
2129
2130         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2131                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2132
2133         return size;
2134 }
2135
2136 static void
2137 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2138                         const struct drm_framebuffer *fb,
2139                         unsigned int rotation)
2140 {
2141         if (intel_rotation_90_or_270(rotation)) {
2142                 *view = i915_ggtt_view_rotated;
2143                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2144         } else {
2145                 *view = i915_ggtt_view_normal;
2146         }
2147 }
2148
2149 static void
2150 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2151                    struct drm_framebuffer *fb)
2152 {
2153         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2154         unsigned int tile_size, tile_width, tile_height, cpp;
2155
2156         tile_size = intel_tile_size(dev_priv);
2157
2158         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2159         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2160                         fb->modifier[0], cpp);
2161
2162         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2163         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2164
2165         if (info->pixel_format == DRM_FORMAT_NV12) {
2166                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2167                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2168                                 fb->modifier[1], cpp);
2169
2170                 info->uv_offset = fb->offsets[1];
2171                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2172                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2173         }
2174 }
2175
2176 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2177 {
2178         if (INTEL_INFO(dev_priv)->gen >= 9)
2179                 return 256 * 1024;
2180         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2181                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2182                 return 128 * 1024;
2183         else if (INTEL_INFO(dev_priv)->gen >= 4)
2184                 return 4 * 1024;
2185         else
2186                 return 0;
2187 }
2188
2189 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2190                                          uint64_t fb_modifier)
2191 {
2192         switch (fb_modifier) {
2193         case DRM_FORMAT_MOD_NONE:
2194                 return intel_linear_alignment(dev_priv);
2195         case I915_FORMAT_MOD_X_TILED:
2196                 if (INTEL_INFO(dev_priv)->gen >= 9)
2197                         return 256 * 1024;
2198                 return 0;
2199         case I915_FORMAT_MOD_Y_TILED:
2200         case I915_FORMAT_MOD_Yf_TILED:
2201                 return 1 * 1024 * 1024;
2202         default:
2203                 MISSING_CASE(fb_modifier);
2204                 return 0;
2205         }
2206 }
2207
2208 int
2209 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2210                            unsigned int rotation)
2211 {
2212         struct drm_device *dev = fb->dev;
2213         struct drm_i915_private *dev_priv = to_i915(dev);
2214         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2215         struct i915_ggtt_view view;
2216         u32 alignment;
2217         int ret;
2218
2219         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2220
2221         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2222
2223         intel_fill_fb_ggtt_view(&view, fb, rotation);
2224
2225         /* Note that the w/a also requires 64 PTE of padding following the
2226          * bo. We currently fill all unused PTE with the shadow page and so
2227          * we should always have valid PTE following the scanout preventing
2228          * the VT-d warning.
2229          */
2230         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2231                 alignment = 256 * 1024;
2232
2233         /*
2234          * Global gtt pte registers are special registers which actually forward
2235          * writes to a chunk of system memory. Which means that there is no risk
2236          * that the register values disappear as soon as we call
2237          * intel_runtime_pm_put(), so it is correct to wrap only the
2238          * pin/unpin/fence and not more.
2239          */
2240         intel_runtime_pm_get(dev_priv);
2241
2242         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2243                                                    &view);
2244         if (ret)
2245                 goto err_pm;
2246
2247         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2248          * fence, whereas 965+ only requires a fence if using
2249          * framebuffer compression.  For simplicity, we always install
2250          * a fence as the cost is not that onerous.
2251          */
2252         if (view.type == I915_GGTT_VIEW_NORMAL) {
2253                 ret = i915_gem_object_get_fence(obj);
2254                 if (ret == -EDEADLK) {
2255                         /*
2256                          * -EDEADLK means there are no free fences
2257                          * no pending flips.
2258                          *
2259                          * This is propagated to atomic, but it uses
2260                          * -EDEADLK to force a locking recovery, so
2261                          * change the returned error to -EBUSY.
2262                          */
2263                         ret = -EBUSY;
2264                         goto err_unpin;
2265                 } else if (ret)
2266                         goto err_unpin;
2267
2268                 i915_gem_object_pin_fence(obj);
2269         }
2270
2271         intel_runtime_pm_put(dev_priv);
2272         return 0;
2273
2274 err_unpin:
2275         i915_gem_object_unpin_from_display_plane(obj, &view);
2276 err_pm:
2277         intel_runtime_pm_put(dev_priv);
2278         return ret;
2279 }
2280
2281 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2282 {
2283         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2284         struct i915_ggtt_view view;
2285
2286         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2287
2288         intel_fill_fb_ggtt_view(&view, fb, rotation);
2289
2290         if (view.type == I915_GGTT_VIEW_NORMAL)
2291                 i915_gem_object_unpin_fence(obj);
2292
2293         i915_gem_object_unpin_from_display_plane(obj, &view);
2294 }
2295
2296 /*
2297  * Adjust the tile offset by moving the difference into
2298  * the x/y offsets.
2299  *
2300  * Input tile dimensions and pitch must already be
2301  * rotated to match x and y, and in pixel units.
2302  */
2303 static u32 intel_adjust_tile_offset(int *x, int *y,
2304                                     unsigned int tile_width,
2305                                     unsigned int tile_height,
2306                                     unsigned int tile_size,
2307                                     unsigned int pitch_tiles,
2308                                     u32 old_offset,
2309                                     u32 new_offset)
2310 {
2311         unsigned int tiles;
2312
2313         WARN_ON(old_offset & (tile_size - 1));
2314         WARN_ON(new_offset & (tile_size - 1));
2315         WARN_ON(new_offset > old_offset);
2316
2317         tiles = (old_offset - new_offset) / tile_size;
2318
2319         *y += tiles / pitch_tiles * tile_height;
2320         *x += tiles % pitch_tiles * tile_width;
2321
2322         return new_offset;
2323 }
2324
2325 /*
2326  * Computes the linear offset to the base tile and adjusts
2327  * x, y. bytes per pixel is assumed to be a power-of-two.
2328  *
2329  * In the 90/270 rotated case, x and y are assumed
2330  * to be already rotated to match the rotated GTT view, and
2331  * pitch is the tile_height aligned framebuffer height.
2332  */
2333 u32 intel_compute_tile_offset(int *x, int *y,
2334                               const struct drm_framebuffer *fb, int plane,
2335                               unsigned int pitch,
2336                               unsigned int rotation)
2337 {
2338         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2339         uint64_t fb_modifier = fb->modifier[plane];
2340         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2341         u32 offset, offset_aligned, alignment;
2342
2343         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2344         if (alignment)
2345                 alignment--;
2346
2347         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2348                 unsigned int tile_size, tile_width, tile_height;
2349                 unsigned int tile_rows, tiles, pitch_tiles;
2350
2351                 tile_size = intel_tile_size(dev_priv);
2352                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2353                                 fb_modifier, cpp);
2354
2355                 if (intel_rotation_90_or_270(rotation)) {
2356                         pitch_tiles = pitch / tile_height;
2357                         swap(tile_width, tile_height);
2358                 } else {
2359                         pitch_tiles = pitch / (tile_width * cpp);
2360                 }
2361
2362                 tile_rows = *y / tile_height;
2363                 *y %= tile_height;
2364
2365                 tiles = *x / tile_width;
2366                 *x %= tile_width;
2367
2368                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2369                 offset_aligned = offset & ~alignment;
2370
2371                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372                                          tile_size, pitch_tiles,
2373                                          offset, offset_aligned);
2374         } else {
2375                 offset = *y * pitch + *x * cpp;
2376                 offset_aligned = offset & ~alignment;
2377
2378                 *y = (offset & alignment) / pitch;
2379                 *x = ((offset & alignment) - *y * pitch) / cpp;
2380         }
2381
2382         return offset_aligned;
2383 }
2384
2385 static int i9xx_format_to_fourcc(int format)
2386 {
2387         switch (format) {
2388         case DISPPLANE_8BPP:
2389                 return DRM_FORMAT_C8;
2390         case DISPPLANE_BGRX555:
2391                 return DRM_FORMAT_XRGB1555;
2392         case DISPPLANE_BGRX565:
2393                 return DRM_FORMAT_RGB565;
2394         default:
2395         case DISPPLANE_BGRX888:
2396                 return DRM_FORMAT_XRGB8888;
2397         case DISPPLANE_RGBX888:
2398                 return DRM_FORMAT_XBGR8888;
2399         case DISPPLANE_BGRX101010:
2400                 return DRM_FORMAT_XRGB2101010;
2401         case DISPPLANE_RGBX101010:
2402                 return DRM_FORMAT_XBGR2101010;
2403         }
2404 }
2405
2406 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2407 {
2408         switch (format) {
2409         case PLANE_CTL_FORMAT_RGB_565:
2410                 return DRM_FORMAT_RGB565;
2411         default:
2412         case PLANE_CTL_FORMAT_XRGB_8888:
2413                 if (rgb_order) {
2414                         if (alpha)
2415                                 return DRM_FORMAT_ABGR8888;
2416                         else
2417                                 return DRM_FORMAT_XBGR8888;
2418                 } else {
2419                         if (alpha)
2420                                 return DRM_FORMAT_ARGB8888;
2421                         else
2422                                 return DRM_FORMAT_XRGB8888;
2423                 }
2424         case PLANE_CTL_FORMAT_XRGB_2101010:
2425                 if (rgb_order)
2426                         return DRM_FORMAT_XBGR2101010;
2427                 else
2428                         return DRM_FORMAT_XRGB2101010;
2429         }
2430 }
2431
2432 static bool
2433 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2434                               struct intel_initial_plane_config *plane_config)
2435 {
2436         struct drm_device *dev = crtc->base.dev;
2437         struct drm_i915_private *dev_priv = to_i915(dev);
2438         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2439         struct drm_i915_gem_object *obj = NULL;
2440         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2441         struct drm_framebuffer *fb = &plane_config->fb->base;
2442         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2443         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2444                                     PAGE_SIZE);
2445
2446         size_aligned -= base_aligned;
2447
2448         if (plane_config->size == 0)
2449                 return false;
2450
2451         /* If the FB is too big, just don't use it since fbdev is not very
2452          * important and we should probably use that space with FBC or other
2453          * features. */
2454         if (size_aligned * 2 > ggtt->stolen_usable_size)
2455                 return false;
2456
2457         mutex_lock(&dev->struct_mutex);
2458
2459         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2460                                                              base_aligned,
2461                                                              base_aligned,
2462                                                              size_aligned);
2463         if (!obj) {
2464                 mutex_unlock(&dev->struct_mutex);
2465                 return false;
2466         }
2467
2468         obj->tiling_mode = plane_config->tiling;
2469         if (obj->tiling_mode == I915_TILING_X)
2470                 obj->stride = fb->pitches[0];
2471
2472         mode_cmd.pixel_format = fb->pixel_format;
2473         mode_cmd.width = fb->width;
2474         mode_cmd.height = fb->height;
2475         mode_cmd.pitches[0] = fb->pitches[0];
2476         mode_cmd.modifier[0] = fb->modifier[0];
2477         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2478
2479         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2480                                    &mode_cmd, obj)) {
2481                 DRM_DEBUG_KMS("intel fb init failed\n");
2482                 goto out_unref_obj;
2483         }
2484
2485         mutex_unlock(&dev->struct_mutex);
2486
2487         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2488         return true;
2489
2490 out_unref_obj:
2491         drm_gem_object_unreference(&obj->base);
2492         mutex_unlock(&dev->struct_mutex);
2493         return false;
2494 }
2495
2496 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2497 static void
2498 update_state_fb(struct drm_plane *plane)
2499 {
2500         if (plane->fb == plane->state->fb)
2501                 return;
2502
2503         if (plane->state->fb)
2504                 drm_framebuffer_unreference(plane->state->fb);
2505         plane->state->fb = plane->fb;
2506         if (plane->state->fb)
2507                 drm_framebuffer_reference(plane->state->fb);
2508 }
2509
2510 static void
2511 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2512                              struct intel_initial_plane_config *plane_config)
2513 {
2514         struct drm_device *dev = intel_crtc->base.dev;
2515         struct drm_i915_private *dev_priv = to_i915(dev);
2516         struct drm_crtc *c;
2517         struct intel_crtc *i;
2518         struct drm_i915_gem_object *obj;
2519         struct drm_plane *primary = intel_crtc->base.primary;
2520         struct drm_plane_state *plane_state = primary->state;
2521         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2522         struct intel_plane *intel_plane = to_intel_plane(primary);
2523         struct intel_plane_state *intel_state =
2524                 to_intel_plane_state(plane_state);
2525         struct drm_framebuffer *fb;
2526
2527         if (!plane_config->fb)
2528                 return;
2529
2530         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2531                 fb = &plane_config->fb->base;
2532                 goto valid_fb;
2533         }
2534
2535         kfree(plane_config->fb);
2536
2537         /*
2538          * Failed to alloc the obj, check to see if we should share
2539          * an fb with another CRTC instead
2540          */
2541         for_each_crtc(dev, c) {
2542                 i = to_intel_crtc(c);
2543
2544                 if (c == &intel_crtc->base)
2545                         continue;
2546
2547                 if (!i->active)
2548                         continue;
2549
2550                 fb = c->primary->fb;
2551                 if (!fb)
2552                         continue;
2553
2554                 obj = intel_fb_obj(fb);
2555                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2556                         drm_framebuffer_reference(fb);
2557                         goto valid_fb;
2558                 }
2559         }
2560
2561         /*
2562          * We've failed to reconstruct the BIOS FB.  Current display state
2563          * indicates that the primary plane is visible, but has a NULL FB,
2564          * which will lead to problems later if we don't fix it up.  The
2565          * simplest solution is to just disable the primary plane now and
2566          * pretend the BIOS never had it enabled.
2567          */
2568         to_intel_plane_state(plane_state)->base.visible = false;
2569         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2570         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2571         intel_plane->disable_plane(primary, &intel_crtc->base);
2572
2573         return;
2574
2575 valid_fb:
2576         plane_state->src_x = 0;
2577         plane_state->src_y = 0;
2578         plane_state->src_w = fb->width << 16;
2579         plane_state->src_h = fb->height << 16;
2580
2581         plane_state->crtc_x = 0;
2582         plane_state->crtc_y = 0;
2583         plane_state->crtc_w = fb->width;
2584         plane_state->crtc_h = fb->height;
2585
2586         intel_state->base.src.x1 = plane_state->src_x;
2587         intel_state->base.src.y1 = plane_state->src_y;
2588         intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2589         intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2590         intel_state->base.dst.x1 = plane_state->crtc_x;
2591         intel_state->base.dst.y1 = plane_state->crtc_y;
2592         intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2593         intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2594
2595         obj = intel_fb_obj(fb);
2596         if (obj->tiling_mode != I915_TILING_NONE)
2597                 dev_priv->preserve_bios_swizzle = true;
2598
2599         drm_framebuffer_reference(fb);
2600         primary->fb = primary->state->fb = fb;
2601         primary->crtc = primary->state->crtc = &intel_crtc->base;
2602         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2603         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2604 }
2605
2606 static void i9xx_update_primary_plane(struct drm_plane *primary,
2607                                       const struct intel_crtc_state *crtc_state,
2608                                       const struct intel_plane_state *plane_state)
2609 {
2610         struct drm_device *dev = primary->dev;
2611         struct drm_i915_private *dev_priv = to_i915(dev);
2612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2613         struct drm_framebuffer *fb = plane_state->base.fb;
2614         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2615         int plane = intel_crtc->plane;
2616         u32 linear_offset;
2617         u32 dspcntr;
2618         i915_reg_t reg = DSPCNTR(plane);
2619         unsigned int rotation = plane_state->base.rotation;
2620         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2621         int x = plane_state->base.src.x1 >> 16;
2622         int y = plane_state->base.src.y1 >> 16;
2623
2624         dspcntr = DISPPLANE_GAMMA_ENABLE;
2625
2626         dspcntr |= DISPLAY_PLANE_ENABLE;
2627
2628         if (INTEL_INFO(dev)->gen < 4) {
2629                 if (intel_crtc->pipe == PIPE_B)
2630                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2631
2632                 /* pipesrc and dspsize control the size that is scaled from,
2633                  * which should always be the user's requested size.
2634                  */
2635                 I915_WRITE(DSPSIZE(plane),
2636                            ((crtc_state->pipe_src_h - 1) << 16) |
2637                            (crtc_state->pipe_src_w - 1));
2638                 I915_WRITE(DSPPOS(plane), 0);
2639         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2640                 I915_WRITE(PRIMSIZE(plane),
2641                            ((crtc_state->pipe_src_h - 1) << 16) |
2642                            (crtc_state->pipe_src_w - 1));
2643                 I915_WRITE(PRIMPOS(plane), 0);
2644                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2645         }
2646
2647         switch (fb->pixel_format) {
2648         case DRM_FORMAT_C8:
2649                 dspcntr |= DISPPLANE_8BPP;
2650                 break;
2651         case DRM_FORMAT_XRGB1555:
2652                 dspcntr |= DISPPLANE_BGRX555;
2653                 break;
2654         case DRM_FORMAT_RGB565:
2655                 dspcntr |= DISPPLANE_BGRX565;
2656                 break;
2657         case DRM_FORMAT_XRGB8888:
2658                 dspcntr |= DISPPLANE_BGRX888;
2659                 break;
2660         case DRM_FORMAT_XBGR8888:
2661                 dspcntr |= DISPPLANE_RGBX888;
2662                 break;
2663         case DRM_FORMAT_XRGB2101010:
2664                 dspcntr |= DISPPLANE_BGRX101010;
2665                 break;
2666         case DRM_FORMAT_XBGR2101010:
2667                 dspcntr |= DISPPLANE_RGBX101010;
2668                 break;
2669         default:
2670                 BUG();
2671         }
2672
2673         if (INTEL_INFO(dev)->gen >= 4 &&
2674             obj->tiling_mode != I915_TILING_NONE)
2675                 dspcntr |= DISPPLANE_TILED;
2676
2677         if (IS_G4X(dev))
2678                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2679
2680         linear_offset = y * fb->pitches[0] + x * cpp;
2681
2682         if (INTEL_INFO(dev)->gen >= 4) {
2683                 intel_crtc->dspaddr_offset =
2684                         intel_compute_tile_offset(&x, &y, fb, 0,
2685                                                   fb->pitches[0], rotation);
2686                 linear_offset -= intel_crtc->dspaddr_offset;
2687         } else {
2688                 intel_crtc->dspaddr_offset = linear_offset;
2689         }
2690
2691         if (rotation == DRM_ROTATE_180) {
2692                 dspcntr |= DISPPLANE_ROTATE_180;
2693
2694                 x += (crtc_state->pipe_src_w - 1);
2695                 y += (crtc_state->pipe_src_h - 1);
2696
2697                 /* Finding the last pixel of the last line of the display
2698                 data and adding to linear_offset*/
2699                 linear_offset +=
2700                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2701                         (crtc_state->pipe_src_w - 1) * cpp;
2702         }
2703
2704         intel_crtc->adjusted_x = x;
2705         intel_crtc->adjusted_y = y;
2706
2707         I915_WRITE(reg, dspcntr);
2708
2709         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2710         if (INTEL_INFO(dev)->gen >= 4) {
2711                 I915_WRITE(DSPSURF(plane),
2712                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2713                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2714                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2715         } else
2716                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2717         POSTING_READ(reg);
2718 }
2719
2720 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2721                                        struct drm_crtc *crtc)
2722 {
2723         struct drm_device *dev = crtc->dev;
2724         struct drm_i915_private *dev_priv = to_i915(dev);
2725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726         int plane = intel_crtc->plane;
2727
2728         I915_WRITE(DSPCNTR(plane), 0);
2729         if (INTEL_INFO(dev_priv)->gen >= 4)
2730                 I915_WRITE(DSPSURF(plane), 0);
2731         else
2732                 I915_WRITE(DSPADDR(plane), 0);
2733         POSTING_READ(DSPCNTR(plane));
2734 }
2735
2736 static void ironlake_update_primary_plane(struct drm_plane *primary,
2737                                           const struct intel_crtc_state *crtc_state,
2738                                           const struct intel_plane_state *plane_state)
2739 {
2740         struct drm_device *dev = primary->dev;
2741         struct drm_i915_private *dev_priv = to_i915(dev);
2742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2743         struct drm_framebuffer *fb = plane_state->base.fb;
2744         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2745         int plane = intel_crtc->plane;
2746         u32 linear_offset;
2747         u32 dspcntr;
2748         i915_reg_t reg = DSPCNTR(plane);
2749         unsigned int rotation = plane_state->base.rotation;
2750         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2751         int x = plane_state->base.src.x1 >> 16;
2752         int y = plane_state->base.src.y1 >> 16;
2753
2754         dspcntr = DISPPLANE_GAMMA_ENABLE;
2755         dspcntr |= DISPLAY_PLANE_ENABLE;
2756
2757         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2758                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2759
2760         switch (fb->pixel_format) {
2761         case DRM_FORMAT_C8:
2762                 dspcntr |= DISPPLANE_8BPP;
2763                 break;
2764         case DRM_FORMAT_RGB565:
2765                 dspcntr |= DISPPLANE_BGRX565;
2766                 break;
2767         case DRM_FORMAT_XRGB8888:
2768                 dspcntr |= DISPPLANE_BGRX888;
2769                 break;
2770         case DRM_FORMAT_XBGR8888:
2771                 dspcntr |= DISPPLANE_RGBX888;
2772                 break;
2773         case DRM_FORMAT_XRGB2101010:
2774                 dspcntr |= DISPPLANE_BGRX101010;
2775                 break;
2776         case DRM_FORMAT_XBGR2101010:
2777                 dspcntr |= DISPPLANE_RGBX101010;
2778                 break;
2779         default:
2780                 BUG();
2781         }
2782
2783         if (obj->tiling_mode != I915_TILING_NONE)
2784                 dspcntr |= DISPPLANE_TILED;
2785
2786         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2787                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2788
2789         linear_offset = y * fb->pitches[0] + x * cpp;
2790         intel_crtc->dspaddr_offset =
2791                 intel_compute_tile_offset(&x, &y, fb, 0,
2792                                           fb->pitches[0], rotation);
2793         linear_offset -= intel_crtc->dspaddr_offset;
2794         if (rotation == DRM_ROTATE_180) {
2795                 dspcntr |= DISPPLANE_ROTATE_180;
2796
2797                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2798                         x += (crtc_state->pipe_src_w - 1);
2799                         y += (crtc_state->pipe_src_h - 1);
2800
2801                         /* Finding the last pixel of the last line of the display
2802                         data and adding to linear_offset*/
2803                         linear_offset +=
2804                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2805                                 (crtc_state->pipe_src_w - 1) * cpp;
2806                 }
2807         }
2808
2809         intel_crtc->adjusted_x = x;
2810         intel_crtc->adjusted_y = y;
2811
2812         I915_WRITE(reg, dspcntr);
2813
2814         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2815         I915_WRITE(DSPSURF(plane),
2816                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2817         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2818                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2819         } else {
2820                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2821                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2822         }
2823         POSTING_READ(reg);
2824 }
2825
2826 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2827                               uint64_t fb_modifier, uint32_t pixel_format)
2828 {
2829         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2830                 return 64;
2831         } else {
2832                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2833
2834                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2835         }
2836 }
2837
2838 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2839                            struct drm_i915_gem_object *obj,
2840                            unsigned int plane)
2841 {
2842         struct i915_ggtt_view view;
2843         struct i915_vma *vma;
2844         u64 offset;
2845
2846         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2847                                 intel_plane->base.state->rotation);
2848
2849         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2850         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2851                 view.type))
2852                 return -1;
2853
2854         offset = vma->node.start;
2855
2856         if (plane == 1) {
2857                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2858                           PAGE_SIZE;
2859         }
2860
2861         WARN_ON(upper_32_bits(offset));
2862
2863         return lower_32_bits(offset);
2864 }
2865
2866 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2867 {
2868         struct drm_device *dev = intel_crtc->base.dev;
2869         struct drm_i915_private *dev_priv = to_i915(dev);
2870
2871         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2872         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2873         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2874 }
2875
2876 /*
2877  * This function detaches (aka. unbinds) unused scalers in hardware
2878  */
2879 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2880 {
2881         struct intel_crtc_scaler_state *scaler_state;
2882         int i;
2883
2884         scaler_state = &intel_crtc->config->scaler_state;
2885
2886         /* loop through and disable scalers that aren't in use */
2887         for (i = 0; i < intel_crtc->num_scalers; i++) {
2888                 if (!scaler_state->scalers[i].in_use)
2889                         skl_detach_scaler(intel_crtc, i);
2890         }
2891 }
2892
2893 u32 skl_plane_ctl_format(uint32_t pixel_format)
2894 {
2895         switch (pixel_format) {
2896         case DRM_FORMAT_C8:
2897                 return PLANE_CTL_FORMAT_INDEXED;
2898         case DRM_FORMAT_RGB565:
2899                 return PLANE_CTL_FORMAT_RGB_565;
2900         case DRM_FORMAT_XBGR8888:
2901                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2902         case DRM_FORMAT_XRGB8888:
2903                 return PLANE_CTL_FORMAT_XRGB_8888;
2904         /*
2905          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2906          * to be already pre-multiplied. We need to add a knob (or a different
2907          * DRM_FORMAT) for user-space to configure that.
2908          */
2909         case DRM_FORMAT_ABGR8888:
2910                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2911                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2912         case DRM_FORMAT_ARGB8888:
2913                 return PLANE_CTL_FORMAT_XRGB_8888 |
2914                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2915         case DRM_FORMAT_XRGB2101010:
2916                 return PLANE_CTL_FORMAT_XRGB_2101010;
2917         case DRM_FORMAT_XBGR2101010:
2918                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2919         case DRM_FORMAT_YUYV:
2920                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2921         case DRM_FORMAT_YVYU:
2922                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2923         case DRM_FORMAT_UYVY:
2924                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2925         case DRM_FORMAT_VYUY:
2926                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2927         default:
2928                 MISSING_CASE(pixel_format);
2929         }
2930
2931         return 0;
2932 }
2933
2934 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2935 {
2936         switch (fb_modifier) {
2937         case DRM_FORMAT_MOD_NONE:
2938                 break;
2939         case I915_FORMAT_MOD_X_TILED:
2940                 return PLANE_CTL_TILED_X;
2941         case I915_FORMAT_MOD_Y_TILED:
2942                 return PLANE_CTL_TILED_Y;
2943         case I915_FORMAT_MOD_Yf_TILED:
2944                 return PLANE_CTL_TILED_YF;
2945         default:
2946                 MISSING_CASE(fb_modifier);
2947         }
2948
2949         return 0;
2950 }
2951
2952 u32 skl_plane_ctl_rotation(unsigned int rotation)
2953 {
2954         switch (rotation) {
2955         case DRM_ROTATE_0:
2956                 break;
2957         /*
2958          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2959          * while i915 HW rotation is clockwise, thats why this swapping.
2960          */
2961         case DRM_ROTATE_90:
2962                 return PLANE_CTL_ROTATE_270;
2963         case DRM_ROTATE_180:
2964                 return PLANE_CTL_ROTATE_180;
2965         case DRM_ROTATE_270:
2966                 return PLANE_CTL_ROTATE_90;
2967         default:
2968                 MISSING_CASE(rotation);
2969         }
2970
2971         return 0;
2972 }
2973
2974 static void skylake_update_primary_plane(struct drm_plane *plane,
2975                                          const struct intel_crtc_state *crtc_state,
2976                                          const struct intel_plane_state *plane_state)
2977 {
2978         struct drm_device *dev = plane->dev;
2979         struct drm_i915_private *dev_priv = to_i915(dev);
2980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2981         struct drm_framebuffer *fb = plane_state->base.fb;
2982         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2983         int pipe = intel_crtc->pipe;
2984         u32 plane_ctl, stride_div, stride;
2985         u32 tile_height, plane_offset, plane_size;
2986         unsigned int rotation = plane_state->base.rotation;
2987         int x_offset, y_offset;
2988         u32 surf_addr;
2989         int scaler_id = plane_state->scaler_id;
2990         int src_x = plane_state->base.src.x1 >> 16;
2991         int src_y = plane_state->base.src.y1 >> 16;
2992         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
2993         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
2994         int dst_x = plane_state->base.dst.x1;
2995         int dst_y = plane_state->base.dst.y1;
2996         int dst_w = drm_rect_width(&plane_state->base.dst);
2997         int dst_h = drm_rect_height(&plane_state->base.dst);
2998
2999         plane_ctl = PLANE_CTL_ENABLE |
3000                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3001                     PLANE_CTL_PIPE_CSC_ENABLE;
3002
3003         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3004         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3005         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3006         plane_ctl |= skl_plane_ctl_rotation(rotation);
3007
3008         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3009                                                fb->pixel_format);
3010         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3011
3012         WARN_ON(drm_rect_width(&plane_state->base.src) == 0);
3013
3014         if (intel_rotation_90_or_270(rotation)) {
3015                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3016
3017                 /* stride = Surface height in tiles */
3018                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3019                 stride = DIV_ROUND_UP(fb->height, tile_height);
3020                 x_offset = stride * tile_height - src_y - src_h;
3021                 y_offset = src_x;
3022                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3023         } else {
3024                 stride = fb->pitches[0] / stride_div;
3025                 x_offset = src_x;
3026                 y_offset = src_y;
3027                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3028         }
3029         plane_offset = y_offset << 16 | x_offset;
3030
3031         intel_crtc->adjusted_x = x_offset;
3032         intel_crtc->adjusted_y = y_offset;
3033
3034         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3035         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3036         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3037         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3038
3039         if (scaler_id >= 0) {
3040                 uint32_t ps_ctrl = 0;
3041
3042                 WARN_ON(!dst_w || !dst_h);
3043                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3044                         crtc_state->scaler_state.scalers[scaler_id].mode;
3045                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3046                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3047                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3048                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3049                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3050         } else {
3051                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3052         }
3053
3054         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3055
3056         POSTING_READ(PLANE_SURF(pipe, 0));
3057 }
3058