drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/reservation.h>
  33 #include <linux/slab.h>
  34 #include <linux/vgaarb.h>
  35
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_atomic_uapi.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_probe_helper.h>
  44 #include <drm/drm_rect.h>
  45 #include <drm/i915_drm.h>
  46
  47 #include "i915_drv.h"
  48 #include "i915_gem_clflush.h"
  49 #include "i915_trace.h"
  50 #include "intel_drv.h"
  51 #include "intel_dsi.h"
  52 #include "intel_frontbuffer.h"
  53
  54 #include "intel_drv.h"
  55 #include "intel_dsi.h"
  56 #include "intel_frontbuffer.h"
  57
  58 #include "i915_drv.h"
  59 #include "i915_gem_clflush.h"
  60 #include "i915_reset.h"
  61 #include "i915_trace.h"
  62
  63 /* Primary plane formats for gen <= 3 */
  64 static const u32 i8xx_primary_formats[] = {
  65         DRM_FORMAT_C8,
  66         DRM_FORMAT_RGB565,
  67         DRM_FORMAT_XRGB1555,
  68         DRM_FORMAT_XRGB8888,
  69 };
  70
  71 /* Primary plane formats for gen >= 4 */
  72 static const u32 i965_primary_formats[] = {
  73         DRM_FORMAT_C8,
  74         DRM_FORMAT_RGB565,
  75         DRM_FORMAT_XRGB8888,
  76         DRM_FORMAT_XBGR8888,
  77         DRM_FORMAT_XRGB2101010,
  78         DRM_FORMAT_XBGR2101010,
  79 };
  80
  81 static const u64 i9xx_format_modifiers[] = {
  82         I915_FORMAT_MOD_X_TILED,
  83         DRM_FORMAT_MOD_LINEAR,
  84         DRM_FORMAT_MOD_INVALID
  85 };
  86
  87 /* Cursor formats */
  88 static const u32 intel_cursor_formats[] = {
  89         DRM_FORMAT_ARGB8888,
  90 };
  91
  92 static const u64 cursor_format_modifiers[] = {
  93         DRM_FORMAT_MOD_LINEAR,
  94         DRM_FORMAT_MOD_INVALID
  95 };
  96
  97 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  98                                 struct intel_crtc_state *pipe_config);
  99 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 100                                    struct intel_crtc_state *pipe_config);
 101
 102 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 103                                   struct drm_i915_gem_object *obj,
 104                                   struct drm_mode_fb_cmd2 *mode_cmd);
 105 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 106 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 107 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 108                                          const struct intel_link_m_n *m_n,
 109                                          const struct intel_link_m_n *m2_n2);
 110 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 111 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
 112 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
 113 static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state);
 114 static void vlv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void chv_prepare_pll(struct intel_crtc *crtc,
 117                             const struct intel_crtc_state *pipe_config);
 118 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 119 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 120 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 121                                     struct intel_crtc_state *crtc_state);
 122 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
 123 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 124 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
 125 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 126                                          struct drm_modeset_acquire_ctx *ctx);
 127 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                            const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 184 {
 185         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 186                 return;
 187
 188         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 189                                                       CCK_CZ_CLOCK_CONTROL);
 190
 191         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 192 }
 193
 194 static inline u32 /* units of 100MHz */
 195 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 196                     const struct intel_crtc_state *pipe_config)
 197 {
 198         if (HAS_DDI(dev_priv))
 199                 return pipe_config->port_clock; /* SPLL */
 200         else
 201                 return dev_priv->fdi_pll_freq;
 202 }
 203
 204 static const struct intel_limit intel_limits_i8xx_dac = {
 205         .dot = { .min = 25000, .max = 350000 },
 206         .vco = { .min = 908000, .max = 1512000 },
 207         .n = { .min = 2, .max = 16 },
 208         .m = { .min = 96, .max = 140 },
 209         .m1 = { .min = 18, .max = 26 },
 210         .m2 = { .min = 6, .max = 16 },
 211         .p = { .min = 4, .max = 128 },
 212         .p1 = { .min = 2, .max = 33 },
 213         .p2 = { .dot_limit = 165000,
 214                 .p2_slow = 4, .p2_fast = 2 },
 215 };
 216
 217 static const struct intel_limit intel_limits_i8xx_dvo = {
 218         .dot = { .min = 25000, .max = 350000 },
 219         .vco = { .min = 908000, .max = 1512000 },
 220         .n = { .min = 2, .max = 16 },
 221         .m = { .min = 96, .max = 140 },
 222         .m1 = { .min = 18, .max = 26 },
 223         .m2 = { .min = 6, .max = 16 },
 224         .p = { .min = 4, .max = 128 },
 225         .p1 = { .min = 2, .max = 33 },
 226         .p2 = { .dot_limit = 165000,
 227                 .p2_slow = 4, .p2_fast = 4 },
 228 };
 229
 230 static const struct intel_limit intel_limits_i8xx_lvds = {
 231         .dot = { .min = 25000, .max = 350000 },
 232         .vco = { .min = 908000, .max = 1512000 },
 233         .n = { .min = 2, .max = 16 },
 234         .m = { .min = 96, .max = 140 },
 235         .m1 = { .min = 18, .max = 26 },
 236         .m2 = { .min = 6, .max = 16 },
 237         .p = { .min = 4, .max = 128 },
 238         .p1 = { .min = 1, .max = 6 },
 239         .p2 = { .dot_limit = 165000,
 240                 .p2_slow = 14, .p2_fast = 7 },
 241 };
 242
 243 static const struct intel_limit intel_limits_i9xx_sdvo = {
 244         .dot = { .min = 20000, .max = 400000 },
 245         .vco = { .min = 1400000, .max = 2800000 },
 246         .n = { .min = 1, .max = 6 },
 247         .m = { .min = 70, .max = 120 },
 248         .m1 = { .min = 8, .max = 18 },
 249         .m2 = { .min = 3, .max = 7 },
 250         .p = { .min = 5, .max = 80 },
 251         .p1 = { .min = 1, .max = 8 },
 252         .p2 = { .dot_limit = 200000,
 253                 .p2_slow = 10, .p2_fast = 5 },
 254 };
 255
 256 static const struct intel_limit intel_limits_i9xx_lvds = {
 257         .dot = { .min = 20000, .max = 400000 },
 258         .vco = { .min = 1400000, .max = 2800000 },
 259         .n = { .min = 1, .max = 6 },
 260         .m = { .min = 70, .max = 120 },
 261         .m1 = { .min = 8, .max = 18 },
 262         .m2 = { .min = 3, .max = 7 },
 263         .p = { .min = 7, .max = 98 },
 264         .p1 = { .min = 1, .max = 8 },
 265         .p2 = { .dot_limit = 112000,
 266                 .p2_slow = 14, .p2_fast = 7 },
 267 };
 268
 269
 270 static const struct intel_limit intel_limits_g4x_sdvo = {
 271         .dot = { .min = 25000, .max = 270000 },
 272         .vco = { .min = 1750000, .max = 3500000},
 273         .n = { .min = 1, .max = 4 },
 274         .m = { .min = 104, .max = 138 },
 275         .m1 = { .min = 17, .max = 23 },
 276         .m2 = { .min = 5, .max = 11 },
 277         .p = { .min = 10, .max = 30 },
 278         .p1 = { .min = 1, .max = 3},
 279         .p2 = { .dot_limit = 270000,
 280                 .p2_slow = 10,
 281                 .p2_fast = 10
 282         },
 283 };
 284
 285 static const struct intel_limit intel_limits_g4x_hdmi = {
 286         .dot = { .min = 22000, .max = 400000 },
 287         .vco = { .min = 1750000, .max = 3500000},
 288         .n = { .min = 1, .max = 4 },
 289         .m = { .min = 104, .max = 138 },
 290         .m1 = { .min = 16, .max = 23 },
 291         .m2 = { .min = 5, .max = 11 },
 292         .p = { .min = 5, .max = 80 },
 293         .p1 = { .min = 1, .max = 8},
 294         .p2 = { .dot_limit = 165000,
 295                 .p2_slow = 10, .p2_fast = 5 },
 296 };
 297
 298 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 299         .dot = { .min = 20000, .max = 115000 },
 300         .vco = { .min = 1750000, .max = 3500000 },
 301         .n = { .min = 1, .max = 3 },
 302         .m = { .min = 104, .max = 138 },
 303         .m1 = { .min = 17, .max = 23 },
 304         .m2 = { .min = 5, .max = 11 },
 305         .p = { .min = 28, .max = 112 },
 306         .p1 = { .min = 2, .max = 8 },
 307         .p2 = { .dot_limit = 0,
 308                 .p2_slow = 14, .p2_fast = 14
 309         },
 310 };
 311
 312 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 313         .dot = { .min = 80000, .max = 224000 },
 314         .vco = { .min = 1750000, .max = 3500000 },
 315         .n = { .min = 1, .max = 3 },
 316         .m = { .min = 104, .max = 138 },
 317         .m1 = { .min = 17, .max = 23 },
 318         .m2 = { .min = 5, .max = 11 },
 319         .p = { .min = 14, .max = 42 },
 320         .p1 = { .min = 2, .max = 6 },
 321         .p2 = { .dot_limit = 0,
 322                 .p2_slow = 7, .p2_fast = 7
 323         },
 324 };
 325
 326 static const struct intel_limit intel_limits_pineview_sdvo = {
 327         .dot = { .min = 20000, .max = 400000},
 328         .vco = { .min = 1700000, .max = 3500000 },
 329         /* Pineview's Ncounter is a ring counter */
 330         .n = { .min = 3, .max = 6 },
 331         .m = { .min = 2, .max = 256 },
 332         /* Pineview only has one combined m divider, which we treat as m2. */
 333         .m1 = { .min = 0, .max = 0 },
 334         .m2 = { .min = 0, .max = 254 },
 335         .p = { .min = 5, .max = 80 },
 336         .p1 = { .min = 1, .max = 8 },
 337         .p2 = { .dot_limit = 200000,
 338                 .p2_slow = 10, .p2_fast = 5 },
 339 };
 340
 341 static const struct intel_limit intel_limits_pineview_lvds = {
 342         .dot = { .min = 20000, .max = 400000 },
 343         .vco = { .min = 1700000, .max = 3500000 },
 344         .n = { .min = 3, .max = 6 },
 345         .m = { .min = 2, .max = 256 },
 346         .m1 = { .min = 0, .max = 0 },
 347         .m2 = { .min = 0, .max = 254 },
 348         .p = { .min = 7, .max = 112 },
 349         .p1 = { .min = 1, .max = 8 },
 350         .p2 = { .dot_limit = 112000,
 351                 .p2_slow = 14, .p2_fast = 14 },
 352 };
 353
 354 /* Ironlake / Sandybridge
 355  *
 356  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 357  * the range value for them is (actual_value - 2).
 358  */
 359 static const struct intel_limit intel_limits_ironlake_dac = {
 360         .dot = { .min = 25000, .max = 350000 },
 361         .vco = { .min = 1760000, .max = 3510000 },
 362         .n = { .min = 1, .max = 5 },
 363         .m = { .min = 79, .max = 127 },
 364         .m1 = { .min = 12, .max = 22 },
 365         .m2 = { .min = 5, .max = 9 },
 366         .p = { .min = 5, .max = 80 },
 367         .p1 = { .min = 1, .max = 8 },
 368         .p2 = { .dot_limit = 225000,
 369                 .p2_slow = 10, .p2_fast = 5 },
 370 };
 371
 372 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 373         .dot = { .min = 25000, .max = 350000 },
 374         .vco = { .min = 1760000, .max = 3510000 },
 375         .n = { .min = 1, .max = 3 },
 376         .m = { .min = 79, .max = 118 },
 377         .m1 = { .min = 12, .max = 22 },
 378         .m2 = { .min = 5, .max = 9 },
 379         .p = { .min = 28, .max = 112 },
 380         .p1 = { .min = 2, .max = 8 },
 381         .p2 = { .dot_limit = 225000,
 382                 .p2_slow = 14, .p2_fast = 14 },
 383 };
 384
 385 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 386         .dot = { .min = 25000, .max = 350000 },
 387         .vco = { .min = 1760000, .max = 3510000 },
 388         .n = { .min = 1, .max = 3 },
 389         .m = { .min = 79, .max = 127 },
 390         .m1 = { .min = 12, .max = 22 },
 391         .m2 = { .min = 5, .max = 9 },
 392         .p = { .min = 14, .max = 56 },
 393         .p1 = { .min = 2, .max = 8 },
 394         .p2 = { .dot_limit = 225000,
 395                 .p2_slow = 7, .p2_fast = 7 },
 396 };
 397
 398 /* LVDS 100mhz refclk limits. */
 399 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 400         .dot = { .min = 25000, .max = 350000 },
 401         .vco = { .min = 1760000, .max = 3510000 },
 402         .n = { .min = 1, .max = 2 },
 403         .m = { .min = 79, .max = 126 },
 404         .m1 = { .min = 12, .max = 22 },
 405         .m2 = { .min = 5, .max = 9 },
 406         .p = { .min = 28, .max = 112 },
 407         .p1 = { .min = 2, .max = 8 },
 408         .p2 = { .dot_limit = 225000,
 409                 .p2_slow = 14, .p2_fast = 14 },
 410 };
 411
 412 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 413         .dot = { .min = 25000, .max = 350000 },
 414         .vco = { .min = 1760000, .max = 3510000 },
 415         .n = { .min = 1, .max = 3 },
 416         .m = { .min = 79, .max = 126 },
 417         .m1 = { .min = 12, .max = 22 },
 418         .m2 = { .min = 5, .max = 9 },
 419         .p = { .min = 14, .max = 42 },
 420         .p1 = { .min = 2, .max = 6 },
 421         .p2 = { .dot_limit = 225000,
 422                 .p2_slow = 7, .p2_fast = 7 },
 423 };
 424
 425 static const struct intel_limit intel_limits_vlv = {
 426          /*
 427           * These are the data rate limits (measured in fast clocks)
 428           * since those are the strictest limits we have. The fast
 429           * clock and actual rate limits are more relaxed, so checking
 430           * them would make no difference.
 431           */
 432         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 433         .vco = { .min = 4000000, .max = 6000000 },
 434         .n = { .min = 1, .max = 7 },
 435         .m1 = { .min = 2, .max = 3 },
 436         .m2 = { .min = 11, .max = 156 },
 437         .p1 = { .min = 2, .max = 3 },
 438         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 439 };
 440
 441 static const struct intel_limit intel_limits_chv = {
 442         /*
 443          * These are the data rate limits (measured in fast clocks)
 444          * since those are the strictest limits we have.  The fast
 445          * clock and actual rate limits are more relaxed, so checking
 446          * them would make no difference.
 447          */
 448         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 449         .vco = { .min = 4800000, .max = 6480000 },
 450         .n = { .min = 1, .max = 1 },
 451         .m1 = { .min = 2, .max = 2 },
 452         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 453         .p1 = { .min = 2, .max = 4 },
 454         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 455 };
 456
 457 static const struct intel_limit intel_limits_bxt = {
 458         /* FIXME: find real dot limits */
 459         .dot = { .min = 0, .max = INT_MAX },
 460         .vco = { .min = 4800000, .max = 6700000 },
 461         .n = { .min = 1, .max = 1 },
 462         .m1 = { .min = 2, .max = 2 },
 463         /* FIXME: find real m2 limits */
 464         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 465         .p1 = { .min = 2, .max = 4 },
 466         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 467 };
 468
 469 static void
 470 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
 471 {
 472         if (enable)
 473                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 474                            DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 475         else
 476                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 477                            I915_READ(CLKGATE_DIS_PSL(pipe)) &
 478                            ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 479 }
 480
 481 static bool
 482 needs_modeset(const struct drm_crtc_state *state)
 483 {
 484         return drm_atomic_crtc_needs_modeset(state);
 485 }
 486
 487 /*
 488  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 489  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 490  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 491  * The helpers' return value is the rate of the clock that is fed to the
 492  * display engine's pipe which can be the above fast dot clock rate or a
 493  * divided-down version of it.
 494  */
 495 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 496 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 497 {
 498         clock->m = clock->m2 + 2;
 499         clock->p = clock->p1 * clock->p2;
 500         if (WARN_ON(clock->n == 0 || clock->p == 0))
 501                 return 0;
 502         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 503         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 504
 505         return clock->dot;
 506 }
 507
 508 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 509 {
 510         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 511 }
 512
 513 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 514 {
 515         clock->m = i9xx_dpll_compute_m(clock);
 516         clock->p = clock->p1 * clock->p2;
 517         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 518                 return 0;
 519         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 520         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 521
 522         return clock->dot;
 523 }
 524
 525 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 526 {
 527         clock->m = clock->m1 * clock->m2;
 528         clock->p = clock->p1 * clock->p2;
 529         if (WARN_ON(clock->n == 0 || clock->p == 0))
 530                 return 0;
 531         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 533
 534         return clock->dot / 5;
 535 }
 536
 537 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 538 {
 539         clock->m = clock->m1 * clock->m2;
 540         clock->p = clock->p1 * clock->p2;
 541         if (WARN_ON(clock->n == 0 || clock->p == 0))
 542                 return 0;
 543         clock->vco = DIV_ROUND_CLOSEST_ULL((u64)refclk * clock->m,
 544                                            clock->n << 22);
 545         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 546
 547         return clock->dot / 5;
 548 }
 549
 550 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 551
 552 /*
 553  * Returns whether the given set of divisors are valid for a given refclk with
 554  * the given connectors.
 555  */
 556 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 557                                const struct intel_limit *limit,
 558                                const struct dpll *clock)
 559 {
 560         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 561                 INTELPllInvalid("n out of range\n");
 562         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 563                 INTELPllInvalid("p1 out of range\n");
 564         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 565                 INTELPllInvalid("m2 out of range\n");
 566         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 567                 INTELPllInvalid("m1 out of range\n");
 568
 569         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 570             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 571                 if (clock->m1 <= clock->m2)
 572                         INTELPllInvalid("m1 <= m2\n");
 573
 574         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 575             !IS_GEN9_LP(dev_priv)) {
 576                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 577                         INTELPllInvalid("p out of range\n");
 578                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 579                         INTELPllInvalid("m out of range\n");
 580         }
 581
 582         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 583                 INTELPllInvalid("vco out of range\n");
 584         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 585          * connector, etc., rather than just a single range.
 586          */
 587         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 588                 INTELPllInvalid("dot out of range\n");
 589
 590         return true;
 591 }
 592
 593 static int
 594 i9xx_select_p2_div(const struct intel_limit *limit,
 595                    const struct intel_crtc_state *crtc_state,
 596                    int target)
 597 {
 598         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 599
 600         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 601                 /*
 602                  * For LVDS just rely on its current settings for dual-channel.
 603                  * We haven't figured out how to reliably set up different
 604                  * single/dual channel state, if we even can.
 605                  */
 606                 if (intel_is_dual_link_lvds(dev_priv))
 607                         return limit->p2.p2_fast;
 608                 else
 609                         return limit->p2.p2_slow;
 610         } else {
 611                 if (target < limit->p2.dot_limit)
 612                         return limit->p2.p2_slow;
 613                 else
 614                         return limit->p2.p2_fast;
 615         }
 616 }
 617
 618 /*
 619  * Returns a set of divisors for the desired target clock with the given
 620  * refclk, or FALSE.  The returned values represent the clock equation:
 621  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 622  *
 623  * Target and reference clocks are specified in kHz.
 624  *
 625  * If match_clock is provided, then best_clock P divider must match the P
 626  * divider from @match_clock used for LVDS downclocking.
 627  */
 628 static bool
 629 i9xx_find_best_dpll(const struct intel_limit *limit,
 630                     struct intel_crtc_state *crtc_state,
 631                     int target, int refclk, struct dpll *match_clock,
 632                     struct dpll *best_clock)
 633 {
 634         struct drm_device *dev = crtc_state->base.crtc->dev;
 635         struct dpll clock;
 636         int err = target;
 637
 638         memset(best_clock, 0, sizeof(*best_clock));
 639
 640         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 641
 642         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 643              clock.m1++) {
 644                 for (clock.m2 = limit->m2.min;
 645                      clock.m2 <= limit->m2.max; clock.m2++) {
 646                         if (clock.m2 >= clock.m1)
 647                                 break;
 648                         for (clock.n = limit->n.min;
 649                              clock.n <= limit->n.max; clock.n++) {
 650                                 for (clock.p1 = limit->p1.min;
 651                                         clock.p1 <= limit->p1.max; clock.p1++) {
 652                                         int this_err;
 653
 654                                         i9xx_calc_dpll_params(refclk, &clock);
 655                                         if (!intel_PLL_is_valid(to_i915(dev),
 656                                                                 limit,
 657                                                                 &clock))
 658                                                 continue;
 659                                         if (match_clock &&
 660                                             clock.p != match_clock->p)
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err) {
 665                                                 *best_clock = clock;
 666                                                 err = this_err;
 667                                         }
 668                                 }
 669                         }
 670                 }
 671         }
 672
 673         return (err != target);
 674 }
 675
 676 /*
 677  * Returns a set of divisors for the desired target clock with the given
 678  * refclk, or FALSE.  The returned values represent the clock equation:
 679  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 680  *
 681  * Target and reference clocks are specified in kHz.
 682  *
 683  * If match_clock is provided, then best_clock P divider must match the P
 684  * divider from @match_clock used for LVDS downclocking.
 685  */
 686 static bool
 687 pnv_find_best_dpll(const struct intel_limit *limit,
 688                    struct intel_crtc_state *crtc_state,
 689                    int target, int refclk, struct dpll *match_clock,
 690                    struct dpll *best_clock)
 691 {
 692         struct drm_device *dev = crtc_state->base.crtc->dev;
 693         struct dpll clock;
 694         int err = target;
 695
 696         memset(best_clock, 0, sizeof(*best_clock));
 697
 698         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 699
 700         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 701              clock.m1++) {
 702                 for (clock.m2 = limit->m2.min;
 703                      clock.m2 <= limit->m2.max; clock.m2++) {
 704                         for (clock.n = limit->n.min;
 705                              clock.n <= limit->n.max; clock.n++) {
 706                                 for (clock.p1 = limit->p1.min;
 707                                         clock.p1 <= limit->p1.max; clock.p1++) {
 708                                         int this_err;
 709
 710                                         pnv_calc_dpll_params(refclk, &clock);
 711                                         if (!intel_PLL_is_valid(to_i915(dev),
 712                                                                 limit,
 713                                                                 &clock))
 714                                                 continue;
 715                                         if (match_clock &&
 716                                             clock.p != match_clock->p)
 717                                                 continue;
 718
 719                                         this_err = abs(clock.dot - target);
 720                                         if (this_err < err) {
 721                                                 *best_clock = clock;
 722                                                 err = this_err;
 723                                         }
 724                                 }
 725                         }
 726                 }
 727         }
 728
 729         return (err != target);
 730 }
 731
 732 /*
 733  * Returns a set of divisors for the desired target clock with the given
 734  * refclk, or FALSE.  The returned values represent the clock equation:
 735  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 736  *
 737  * Target and reference clocks are specified in kHz.
 738  *
 739  * If match_clock is provided, then best_clock P divider must match the P
 740  * divider from @match_clock used for LVDS downclocking.
 741  */
 742 static bool
 743 g4x_find_best_dpll(const struct intel_limit *limit,
 744                    struct intel_crtc_state *crtc_state,
 745                    int target, int refclk, struct dpll *match_clock,
 746                    struct dpll *best_clock)
 747 {
 748         struct drm_device *dev = crtc_state->base.crtc->dev;
 749         struct dpll clock;
 750         int max_n;
 751         bool found = false;
 752         /* approximately equals target * 0.00585 */
 753         int err_most = (target >> 8) + (target >> 9);
 754
 755         memset(best_clock, 0, sizeof(*best_clock));
 756
 757         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 758
 759         max_n = limit->n.max;
 760         /* based on hardware requirement, prefer smaller n to precision */
 761         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 762                 /* based on hardware requirement, prefere larger m1,m2 */
 763                 for (clock.m1 = limit->m1.max;
 764                      clock.m1 >= limit->m1.min; clock.m1--) {
 765                         for (clock.m2 = limit->m2.max;
 766                              clock.m2 >= limit->m2.min; clock.m2--) {
 767                                 for (clock.p1 = limit->p1.max;
 768                                      clock.p1 >= limit->p1.min; clock.p1--) {
 769                                         int this_err;
 770
 771                                         i9xx_calc_dpll_params(refclk, &clock);
 772                                         if (!intel_PLL_is_valid(to_i915(dev),
 773                                                                 limit,
 774                                                                 &clock))
 775                                                 continue;
 776
 777                                         this_err = abs(clock.dot - target);
 778                                         if (this_err < err_most) {
 779                                                 *best_clock = clock;
 780                                                 err_most = this_err;
 781                                                 max_n = clock.n;
 782                                                 found = true;
 783                                         }
 784                                 }
 785                         }
 786                 }
 787         }
 788         return found;
 789 }
 790
 791 /*
 792  * Check if the calculated PLL configuration is more optimal compared to the
 793  * best configuration and error found so far. Return the calculated error.
 794  */
 795 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 796                                const struct dpll *calculated_clock,
 797                                const struct dpll *best_clock,
 798                                unsigned int best_error_ppm,
 799                                unsigned int *error_ppm)
 800 {
 801         /*
 802          * For CHV ignore the error and consider only the P value.
 803          * Prefer a bigger P value based on HW requirements.
 804          */
 805         if (IS_CHERRYVIEW(to_i915(dev))) {
 806                 *error_ppm = 0;
 807
 808                 return calculated_clock->p > best_clock->p;
 809         }
 810
 811         if (WARN_ON_ONCE(!target_freq))
 812                 return false;
 813
 814         *error_ppm = div_u64(1000000ULL *
 815                                 abs(target_freq - calculated_clock->dot),
 816                              target_freq);
 817         /*
 818          * Prefer a better P value over a better (smaller) error if the error
 819          * is small. Ensure this preference for future configurations too by
 820          * setting the error to 0.
 821          */
 822         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 823                 *error_ppm = 0;
 824
 825                 return true;
 826         }
 827
 828         return *error_ppm + 10 < best_error_ppm;
 829 }
 830
 831 /*
 832  * Returns a set of divisors for the desired target clock with the given
 833  * refclk, or FALSE.  The returned values represent the clock equation:
 834  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 835  */
 836 static bool
 837 vlv_find_best_dpll(const struct intel_limit *limit,
 838                    struct intel_crtc_state *crtc_state,
 839                    int target, int refclk, struct dpll *match_clock,
 840                    struct dpll *best_clock)
 841 {
 842         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 843         struct drm_device *dev = crtc->base.dev;
 844         struct dpll clock;
 845         unsigned int bestppm = 1000000;
 846         /* min update 19.2 MHz */
 847         int max_n = min(limit->n.max, refclk / 19200);
 848         bool found = false;
 849
 850         target *= 5; /* fast clock */
 851
 852         memset(best_clock, 0, sizeof(*best_clock));
 853
 854         /* based on hardware requirement, prefer smaller n to precision */
 855         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 856                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 857                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 858                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 859                                 clock.p = clock.p1 * clock.p2;
 860                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 861                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 862                                         unsigned int ppm;
 863
 864                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 865                                                                      refclk * clock.m1);
 866
 867                                         vlv_calc_dpll_params(refclk, &clock);
 868
 869                                         if (!intel_PLL_is_valid(to_i915(dev),
 870                                                                 limit,
 871                                                                 &clock))
 872                                                 continue;
 873
 874                                         if (!vlv_PLL_is_optimal(dev, target,
 875                                                                 &clock,
 876                                                                 best_clock,
 877                                                                 bestppm, &ppm))
 878                                                 continue;
 879
 880                                         *best_clock = clock;
 881                                         bestppm = ppm;
 882                                         found = true;
 883                                 }
 884                         }
 885                 }
 886         }
 887
 888         return found;
 889 }
 890
 891 /*
 892  * Returns a set of divisors for the desired target clock with the given
 893  * refclk, or FALSE.  The returned values represent the clock equation:
 894  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 895  */
 896 static bool
 897 chv_find_best_dpll(const struct intel_limit *limit,
 898                    struct intel_crtc_state *crtc_state,
 899                    int target, int refclk, struct dpll *match_clock,
 900                    struct dpll *best_clock)
 901 {
 902         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 903         struct drm_device *dev = crtc->base.dev;
 904         unsigned int best_error_ppm;
 905         struct dpll clock;
 906         u64 m2;
 907         int found = false;
 908
 909         memset(best_clock, 0, sizeof(*best_clock));
 910         best_error_ppm = 1000000;
 911
 912         /*
 913          * Based on hardware doc, the n always set to 1, and m1 always
 914          * set to 2.  If requires to support 200Mhz refclk, we need to
 915          * revisit this because n may not 1 anymore.
 916          */
 917         clock.n = 1, clock.m1 = 2;
 918         target *= 5;    /* fast clock */
 919
 920         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 921                 for (clock.p2 = limit->p2.p2_fast;
 922                                 clock.p2 >= limit->p2.p2_slow;
 923                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 924                         unsigned int error_ppm;
 925
 926                         clock.p = clock.p1 * clock.p2;
 927
 928                         m2 = DIV_ROUND_CLOSEST_ULL(((u64)target * clock.p *
 929                                         clock.n) << 22, refclk * clock.m1);
 930
 931                         if (m2 > INT_MAX/clock.m1)
 932                                 continue;
 933
 934                         clock.m2 = m2;
 935
 936                         chv_calc_dpll_params(refclk, &clock);
 937
 938                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 939                                 continue;
 940
 941                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 942                                                 best_error_ppm, &error_ppm))
 943                                 continue;
 944
 945                         *best_clock = clock;
 946                         best_error_ppm = error_ppm;
 947                         found = true;
 948                 }
 949         }
 950
 951         return found;
 952 }
 953
 954 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
 955                         struct dpll *best_clock)
 956 {
 957         int refclk = 100000;
 958         const struct intel_limit *limit = &intel_limits_bxt;
 959
 960         return chv_find_best_dpll(limit, crtc_state,
 961                                   crtc_state->port_clock, refclk,
 962                                   NULL, best_clock);
 963 }
 964
 965 bool intel_crtc_active(struct intel_crtc *crtc)
 966 {
 967         /* Be paranoid as we can arrive here with only partial
 968          * state retrieved from the hardware during setup.
 969          *
 970          * We can ditch the adjusted_mode.crtc_clock check as soon
 971          * as Haswell has gained clock readout/fastboot support.
 972          *
 973          * We can ditch the crtc->primary->state->fb check as soon as we can
 974          * properly reconstruct framebuffers.
 975          *
 976          * FIXME: The intel_crtc->active here should be switched to
 977          * crtc->state->active once we have proper CRTC states wired up
 978          * for atomic.
 979          */
 980         return crtc->active && crtc->base.primary->state->fb &&
 981                 crtc->config->base.adjusted_mode.crtc_clock;
 982 }
 983
 984 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 985                                              enum pipe pipe)
 986 {
 987         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 988
 989         return crtc->config->cpu_transcoder;
 990 }
 991
 992 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
 993                                     enum pipe pipe)
 994 {
 995         i915_reg_t reg = PIPEDSL(pipe);
 996         u32 line1, line2;
 997         u32 line_mask;
 998
 999         if (IS_GEN(dev_priv, 2))
1000                 line_mask = DSL_LINEMASK_GEN2;
1001         else
1002                 line_mask = DSL_LINEMASK_GEN3;
1003
1004         line1 = I915_READ(reg) & line_mask;
1005         msleep(5);
1006         line2 = I915_READ(reg) & line_mask;
1007
1008         return line1 != line2;
1009 }
1010
1011 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1012 {
1013         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1014         enum pipe pipe = crtc->pipe;
1015
1016         /* Wait for the display line to settle/start moving */
1017         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1018                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1019                           pipe_name(pipe), onoff(state));
1020 }
1021
1022 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1023 {
1024         wait_for_pipe_scanline_moving(crtc, false);
1025 }
1026
1027 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1028 {
1029         wait_for_pipe_scanline_moving(crtc, true);
1030 }
1031
1032 static void
1033 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1034 {
1035         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1036         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1037
1038         if (INTEL_GEN(dev_priv) >= 4) {
1039                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1040                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1041
1042                 /* Wait for the Pipe State to go off */
1043                 if (intel_wait_for_register(&dev_priv->uncore,
1044                                             reg, I965_PIPECONF_ACTIVE, 0,
1045                                             100))
1046                         WARN(1, "pipe_off wait timed out\n");
1047         } else {
1048                 intel_wait_for_pipe_scanline_stopped(crtc);
1049         }
1050 }
1051
1052 /* Only for pre-ILK configs */
1053 void assert_pll(struct drm_i915_private *dev_priv,
1054                 enum pipe pipe, bool state)
1055 {
1056         u32 val;
1057         bool cur_state;
1058
1059         val = I915_READ(DPLL(pipe));
1060         cur_state = !!(val & DPLL_VCO_ENABLE);
1061         I915_STATE_WARN(cur_state != state,
1062              "PLL state assertion failure (expected %s, current %s)\n",
1063                         onoff(state), onoff(cur_state));
1064 }
1065
1066 /* XXX: the dsi pll is shared between MIPI DSI ports */
1067 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1068 {
1069         u32 val;
1070         bool cur_state;
1071
1072         mutex_lock(&dev_priv->sb_lock);
1073         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1074         mutex_unlock(&dev_priv->sb_lock);
1075
1076         cur_state = val & DSI_PLL_VCO_EN;
1077         I915_STATE_WARN(cur_state != state,
1078              "DSI PLL state assertion failure (expected %s, current %s)\n",
1079                         onoff(state), onoff(cur_state));
1080 }
1081
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083                           enum pipe pipe, bool state)
1084 {
1085         bool cur_state;
1086         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1087                                                                       pipe);
1088
1089         if (HAS_DDI(dev_priv)) {
1090                 /* DDI does not have a specific FDI_TX register */
1091                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1095                 cur_state = !!(val & FDI_TX_ENABLE);
1096         }
1097         I915_STATE_WARN(cur_state != state,
1098              "FDI TX state assertion failure (expected %s, current %s)\n",
1099                         onoff(state), onoff(cur_state));
1100 }
1101 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1102 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1103
1104 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1105                           enum pipe pipe, bool state)
1106 {
1107         u32 val;
1108         bool cur_state;
1109
1110         val = I915_READ(FDI_RX_CTL(pipe));
1111         cur_state = !!(val & FDI_RX_ENABLE);
1112         I915_STATE_WARN(cur_state != state,
1113              "FDI RX state assertion failure (expected %s, current %s)\n",
1114                         onoff(state), onoff(cur_state));
1115 }
1116 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1117 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1118
1119 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1120                                       enum pipe pipe)
1121 {
1122         u32 val;
1123
1124         /* ILK FDI PLL is always enabled */
1125         if (IS_GEN(dev_priv, 5))
1126                 return;
1127
1128         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1129         if (HAS_DDI(dev_priv))
1130                 return;
1131
1132         val = I915_READ(FDI_TX_CTL(pipe));
1133         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1134 }
1135
1136 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1137                        enum pipe pipe, bool state)
1138 {
1139         u32 val;
1140         bool cur_state;
1141
1142         val = I915_READ(FDI_RX_CTL(pipe));
1143         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1144         I915_STATE_WARN(cur_state != state,
1145              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1146                         onoff(state), onoff(cur_state));
1147 }
1148
1149 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1150 {
1151         i915_reg_t pp_reg;
1152         u32 val;
1153         enum pipe panel_pipe = INVALID_PIPE;
1154         bool locked = true;
1155
1156         if (WARN_ON(HAS_DDI(dev_priv)))
1157                 return;
1158
1159         if (HAS_PCH_SPLIT(dev_priv)) {
1160                 u32 port_sel;
1161
1162                 pp_reg = PP_CONTROL(0);
1163                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1164
1165                 switch (port_sel) {
1166                 case PANEL_PORT_SELECT_LVDS:
1167                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1168                         break;
1169                 case PANEL_PORT_SELECT_DPA:
1170                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1171                         break;
1172                 case PANEL_PORT_SELECT_DPC:
1173                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1174                         break;
1175                 case PANEL_PORT_SELECT_DPD:
1176                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1177                         break;
1178                 default:
1179                         MISSING_CASE(port_sel);
1180                         break;
1181                 }
1182         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1183                 /* presumably write lock depends on pipe, not port select */
1184                 pp_reg = PP_CONTROL(pipe);
1185                 panel_pipe = pipe;
1186         } else {
1187                 u32 port_sel;
1188
1189                 pp_reg = PP_CONTROL(0);
1190                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1191
1192                 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1193                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1194         }
1195
1196         val = I915_READ(pp_reg);
1197         if (!(val & PANEL_POWER_ON) ||
1198             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1199                 locked = false;
1200
1201         I915_STATE_WARN(panel_pipe == pipe && locked,
1202              "panel assertion failure, pipe %c regs locked\n",
1203              pipe_name(pipe));
1204 }
1205
1206 void assert_pipe(struct drm_i915_private *dev_priv,
1207                  enum pipe pipe, bool state)
1208 {
1209         bool cur_state;
1210         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211                                                                       pipe);
1212         enum intel_display_power_domain power_domain;
1213         intel_wakeref_t wakeref;
1214
1215         /* we keep both pipes enabled on 830 */
1216         if (IS_I830(dev_priv))
1217                 state = true;
1218
1219         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1220         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1221         if (wakeref) {
1222                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1223                 cur_state = !!(val & PIPECONF_ENABLE);
1224
1225                 intel_display_power_put(dev_priv, power_domain, wakeref);
1226         } else {
1227                 cur_state = false;
1228         }
1229
1230         I915_STATE_WARN(cur_state != state,
1231              "pipe %c assertion failure (expected %s, current %s)\n",
1232                         pipe_name(pipe), onoff(state), onoff(cur_state));
1233 }
1234
1235 static void assert_plane(struct intel_plane *plane, bool state)
1236 {
1237         enum pipe pipe;
1238         bool cur_state;
1239
1240         cur_state = plane->get_hw_state(plane, &pipe);
1241
1242         I915_STATE_WARN(cur_state != state,
1243                         "%s assertion failure (expected %s, current %s)\n",
1244                         plane->base.name, onoff(state), onoff(cur_state));
1245 }
1246
1247 #define assert_plane_enabled(p) assert_plane(p, true)
1248 #define assert_plane_disabled(p) assert_plane(p, false)
1249
1250 static void assert_planes_disabled(struct intel_crtc *crtc)
1251 {
1252         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1253         struct intel_plane *plane;
1254
1255         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1256                 assert_plane_disabled(plane);
1257 }
1258
1259 static void assert_vblank_disabled(struct drm_crtc *crtc)
1260 {
1261         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1262                 drm_crtc_vblank_put(crtc);
1263 }
1264
1265 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1266                                     enum pipe pipe)
1267 {
1268         u32 val;
1269         bool enabled;
1270
1271         val = I915_READ(PCH_TRANSCONF(pipe));
1272         enabled = !!(val & TRANS_ENABLE);
1273         I915_STATE_WARN(enabled,
1274              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1275              pipe_name(pipe));
1276 }
1277
1278 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1279                                    enum pipe pipe, enum port port,
1280                                    i915_reg_t dp_reg)
1281 {
1282         enum pipe port_pipe;
1283         bool state;
1284
1285         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1286
1287         I915_STATE_WARN(state && port_pipe == pipe,
1288                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1289                         port_name(port), pipe_name(pipe));
1290
1291         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1292                         "IBX PCH DP %c still using transcoder B\n",
1293                         port_name(port));
1294 }
1295
1296 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1297                                      enum pipe pipe, enum port port,
1298                                      i915_reg_t hdmi_reg)
1299 {
1300         enum pipe port_pipe;
1301         bool state;
1302
1303         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1304
1305         I915_STATE_WARN(state && port_pipe == pipe,
1306                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1307                         port_name(port), pipe_name(pipe));
1308
1309         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1310                         "IBX PCH HDMI %c still using transcoder B\n",
1311                         port_name(port));
1312 }
1313
1314 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1315                                       enum pipe pipe)
1316 {
1317         enum pipe port_pipe;
1318
1319         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1320         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1321         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1322
1323         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1324                         port_pipe == pipe,
1325                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1326                         pipe_name(pipe));
1327
1328         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1329                         port_pipe == pipe,
1330                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1331                         pipe_name(pipe));
1332
1333         /* PCH SDVOB multiplex with HDMIB */
1334         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1335         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1336         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1337 }
1338
1339 static void _vlv_enable_pll(struct intel_crtc *crtc,
1340                             const struct intel_crtc_state *pipe_config)
1341 {
1342         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1343         enum pipe pipe = crtc->pipe;
1344
1345         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1346         POSTING_READ(DPLL(pipe));
1347         udelay(150);
1348
1349         if (intel_wait_for_register(&dev_priv->uncore,
1350                                     DPLL(pipe),
1351                                     DPLL_LOCK_VLV,
1352                                     DPLL_LOCK_VLV,
1353                                     1))
1354                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1355 }
1356
1357 static void vlv_enable_pll(struct intel_crtc *crtc,
1358                            const struct intel_crtc_state *pipe_config)
1359 {
1360         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1361         enum pipe pipe = crtc->pipe;
1362
1363         assert_pipe_disabled(dev_priv, pipe);
1364
1365         /* PLL is protected by panel, make sure we can write it */
1366         assert_panel_unlocked(dev_priv, pipe);
1367
1368         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1369                 _vlv_enable_pll(crtc, pipe_config);
1370
1371         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1372         POSTING_READ(DPLL_MD(pipe));
1373 }
1374
1375
1376 static void _chv_enable_pll(struct intel_crtc *crtc,
1377                             const struct intel_crtc_state *pipe_config)
1378 {
1379         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1380         enum pipe pipe = crtc->pipe;
1381         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1382         u32 tmp;
1383
1384         mutex_lock(&dev_priv->sb_lock);
1385
1386         /* Enable back the 10bit clock to display controller */
1387         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1388         tmp |= DPIO_DCLKP_EN;
1389         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1390
1391         mutex_unlock(&dev_priv->sb_lock);
1392
1393         /*
1394          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1395          */
1396         udelay(1);
1397
1398         /* Enable PLL */
1399         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1400
1401         /* Check PLL is locked */
1402         if (intel_wait_for_register(&dev_priv->uncore,
1403                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1404                                     1))
1405                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1406 }
1407
1408 static void chv_enable_pll(struct intel_crtc *crtc,
1409                            const struct intel_crtc_state *pipe_config)
1410 {
1411         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1412         enum pipe pipe = crtc->pipe;
1413
1414         assert_pipe_disabled(dev_priv, pipe);
1415
1416         /* PLL is protected by panel, make sure we can write it */
1417         assert_panel_unlocked(dev_priv, pipe);
1418
1419         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1420                 _chv_enable_pll(crtc, pipe_config);
1421
1422         if (pipe != PIPE_A) {
1423                 /*
1424                  * WaPixelRepeatModeFixForC0:chv
1425                  *
1426                  * DPLLCMD is AWOL. Use chicken bits to propagate
1427                  * the value from DPLLBMD to either pipe B or C.
1428                  */
1429                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1430                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1431                 I915_WRITE(CBR4_VLV, 0);
1432                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1433
1434                 /*
1435                  * DPLLB VGA mode also seems to cause problems.
1436                  * We should always have it disabled.
1437                  */
1438                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1439         } else {
1440                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1441                 POSTING_READ(DPLL_MD(pipe));
1442         }
1443 }
1444
1445 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1446 {
1447         if (IS_I830(dev_priv))
1448                 return false;
1449
1450         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1451 }
1452
1453 static void i9xx_enable_pll(struct intel_crtc *crtc,
1454                             const struct intel_crtc_state *crtc_state)
1455 {
1456         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1457         i915_reg_t reg = DPLL(crtc->pipe);
1458         u32 dpll = crtc_state->dpll_hw_state.dpll;
1459         int i;
1460
1461         assert_pipe_disabled(dev_priv, crtc->pipe);
1462
1463         /* PLL is protected by panel, make sure we can write it */
1464         if (i9xx_has_pps(dev_priv))
1465                 assert_panel_unlocked(dev_priv, crtc->pipe);
1466
1467         /*
1468          * Apparently we need to have VGA mode enabled prior to changing
1469          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1470          * dividers, even though the register value does change.
1471          */
1472         I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1473         I915_WRITE(reg, dpll);
1474
1475         /* Wait for the clocks to stabilize. */
1476         POSTING_READ(reg);
1477         udelay(150);
1478
1479         if (INTEL_GEN(dev_priv) >= 4) {
1480                 I915_WRITE(DPLL_MD(crtc->pipe),
1481                            crtc_state->dpll_hw_state.dpll_md);
1482         } else {
1483                 /* The pixel multiplier can only be updated once the
1484                  * DPLL is enabled and the clocks are stable.
1485                  *
1486                  * So write it again.
1487                  */
1488                 I915_WRITE(reg, dpll);
1489         }
1490
1491         /* We do this three times for luck */
1492         for (i = 0; i < 3; i++) {
1493                 I915_WRITE(reg, dpll);
1494                 POSTING_READ(reg);
1495                 udelay(150); /* wait for warmup */
1496         }
1497 }
1498
1499 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1500 {
1501         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1502         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1503         enum pipe pipe = crtc->pipe;
1504
1505         /* Don't disable pipe or pipe PLLs if needed */
1506         if (IS_I830(dev_priv))
1507                 return;
1508
1509         /* Make sure the pipe isn't still relying on us */
1510         assert_pipe_disabled(dev_priv, pipe);
1511
1512         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1513         POSTING_READ(DPLL(pipe));
1514 }
1515
1516 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1517 {
1518         u32 val;
1519
1520         /* Make sure the pipe isn't still relying on us */
1521         assert_pipe_disabled(dev_priv, pipe);
1522
1523         val = DPLL_INTEGRATED_REF_CLK_VLV |
1524                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1525         if (pipe != PIPE_A)
1526                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1527
1528         I915_WRITE(DPLL(pipe), val);
1529         POSTING_READ(DPLL(pipe));
1530 }
1531
1532 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1533 {
1534         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1535         u32 val;
1536
1537         /* Make sure the pipe isn't still relying on us */
1538         assert_pipe_disabled(dev_priv, pipe);
1539
1540         val = DPLL_SSC_REF_CLK_CHV |
1541                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1542         if (pipe != PIPE_A)
1543                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1544
1545         I915_WRITE(DPLL(pipe), val);
1546         POSTING_READ(DPLL(pipe));
1547
1548         mutex_lock(&dev_priv->sb_lock);
1549
1550         /* Disable 10bit clock to display controller */
1551         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1552         val &= ~DPIO_DCLKP_EN;
1553         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1554
1555         mutex_unlock(&dev_priv->sb_lock);
1556 }
1557
1558 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1559                          struct intel_digital_port *dport,
1560                          unsigned int expected_mask)
1561 {
1562         u32 port_mask;
1563         i915_reg_t dpll_reg;
1564
1565         switch (dport->base.port) {
1566         case PORT_B:
1567                 port_mask = DPLL_PORTB_READY_MASK;
1568                 dpll_reg = DPLL(0);
1569                 break;
1570         case PORT_C:
1571                 port_mask = DPLL_PORTC_READY_MASK;
1572                 dpll_reg = DPLL(0);
1573                 expected_mask <<= 4;
1574                 break;
1575         case PORT_D:
1576                 port_mask = DPLL_PORTD_READY_MASK;
1577                 dpll_reg = DPIO_PHY_STATUS;
1578                 break;
1579         default:
1580                 BUG();
1581         }
1582
1583         if (intel_wait_for_register(&dev_priv->uncore,
1584                                     dpll_reg, port_mask, expected_mask,
1585                                     1000))
1586                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1587                      port_name(dport->base.port),
1588                      I915_READ(dpll_reg) & port_mask, expected_mask);
1589 }
1590
1591 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1592 {
1593         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1594         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1595         enum pipe pipe = crtc->pipe;
1596         i915_reg_t reg;
1597         u32 val, pipeconf_val;
1598
1599         /* Make sure PCH DPLL is enabled */
1600         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1601
1602         /* FDI must be feeding us bits for PCH ports */
1603         assert_fdi_tx_enabled(dev_priv, pipe);
1604         assert_fdi_rx_enabled(dev_priv, pipe);
1605
1606         if (HAS_PCH_CPT(dev_priv)) {
1607                 /* Workaround: Set the timing override bit before enabling the
1608                  * pch transcoder. */
1609                 reg = TRANS_CHICKEN2(pipe);
1610                 val = I915_READ(reg);
1611                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1612                 I915_WRITE(reg, val);
1613         }
1614
1615         reg = PCH_TRANSCONF(pipe);
1616         val = I915_READ(reg);
1617         pipeconf_val = I915_READ(PIPECONF(pipe));
1618
1619         if (HAS_PCH_IBX(dev_priv)) {
1620                 /*
1621                  * Make the BPC in transcoder be consistent with
1622                  * that in pipeconf reg. For HDMI we must use 8bpc
1623                  * here for both 8bpc and 12bpc.
1624                  */
1625                 val &= ~PIPECONF_BPC_MASK;
1626                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1627                         val |= PIPECONF_8BPC;
1628                 else
1629                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1630         }
1631
1632         val &= ~TRANS_INTERLACE_MASK;
1633         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1634                 if (HAS_PCH_IBX(dev_priv) &&
1635                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1636                         val |= TRANS_LEGACY_INTERLACED_ILK;
1637                 else
1638                         val |= TRANS_INTERLACED;
1639         } else {
1640                 val |= TRANS_PROGRESSIVE;
1641         }
1642
1643         I915_WRITE(reg, val | TRANS_ENABLE);
1644         if (intel_wait_for_register(&dev_priv->uncore,
1645                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1646                                     100))
1647                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1648 }
1649
1650 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1651                                       enum transcoder cpu_transcoder)
1652 {
1653         u32 val, pipeconf_val;
1654
1655         /* FDI must be feeding us bits for PCH ports */
1656         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1657         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1658
1659         /* Workaround: set timing override bit. */
1660         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1661         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1662         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1663
1664         val = TRANS_ENABLE;
1665         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1666
1667         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1668             PIPECONF_INTERLACED_ILK)
1669                 val |= TRANS_INTERLACED;
1670         else
1671                 val |= TRANS_PROGRESSIVE;
1672
1673         I915_WRITE(LPT_TRANSCONF, val);
1674         if (intel_wait_for_register(&dev_priv->uncore,
1675                                     LPT_TRANSCONF,
1676                                     TRANS_STATE_ENABLE,
1677                                     TRANS_STATE_ENABLE,
1678                                     100))
1679                 DRM_ERROR("Failed to enable PCH transcoder\n");
1680 }
1681
1682 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1683                                             enum pipe pipe)
1684 {
1685         i915_reg_t reg;
1686         u32 val;
1687
1688         /* FDI relies on the transcoder */
1689         assert_fdi_tx_disabled(dev_priv, pipe);
1690         assert_fdi_rx_disabled(dev_priv, pipe);
1691
1692         /* Ports must be off as well */
1693         assert_pch_ports_disabled(dev_priv, pipe);
1694
1695         reg = PCH_TRANSCONF(pipe);
1696         val = I915_READ(reg);
1697         val &= ~TRANS_ENABLE;
1698         I915_WRITE(reg, val);
1699         /* wait for PCH transcoder off, transcoder state */
1700         if (intel_wait_for_register(&dev_priv->uncore,
1701                                     reg, TRANS_STATE_ENABLE, 0,
1702                                     50))
1703                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1704
1705         if (HAS_PCH_CPT(dev_priv)) {
1706                 /* Workaround: Clear the timing override chicken bit again. */
1707                 reg = TRANS_CHICKEN2(pipe);
1708                 val = I915_READ(reg);
1709                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1710                 I915_WRITE(reg, val);
1711         }
1712 }
1713
1714 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1715 {
1716         u32 val;
1717
1718         val = I915_READ(LPT_TRANSCONF);
1719         val &= ~TRANS_ENABLE;
1720         I915_WRITE(LPT_TRANSCONF, val);
1721         /* wait for PCH transcoder off, transcoder state */
1722         if (intel_wait_for_register(&dev_priv->uncore,
1723                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1724                                     50))
1725                 DRM_ERROR("Failed to disable PCH transcoder\n");
1726
1727         /* Workaround: clear timing override bit. */
1728         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1729         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1730         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1731 }
1732
1733 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1734 {
1735         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1736
1737         if (HAS_PCH_LPT(dev_priv))
1738                 return PIPE_A;
1739         else
1740                 return crtc->pipe;
1741 }
1742
1743 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1744 {
1745         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1746
1747         /*
1748          * On i965gm the hardware frame counter reads
1749          * zero when the TV encoder is enabled :(
1750          */
1751         if (IS_I965GM(dev_priv) &&
1752             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1753                 return 0;
1754
1755         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1756                 return 0xffffffff; /* full 32 bit counter */
1757         else if (INTEL_GEN(dev_priv) >= 3)
1758                 return 0xffffff; /* only 24 bits of frame count */
1759         else
1760                 return 0; /* Gen2 doesn't have a hardware frame counter */
1761 }
1762
1763 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1764 {
1765         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1766
1767         drm_crtc_set_max_vblank_count(&crtc->base,
1768                                       intel_crtc_max_vblank_count(crtc_state));
1769         drm_crtc_vblank_on(&crtc->base);
1770 }
1771
1772 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1773 {
1774         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1775         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1776         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1777         enum pipe pipe = crtc->pipe;
1778         i915_reg_t reg;
1779         u32 val;
1780
1781         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1782
1783         assert_planes_disabled(crtc);
1784
1785         /*
1786          * A pipe without a PLL won't actually be able to drive bits from
1787          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1788          * need the check.
1789          */
1790         if (HAS_GMCH(dev_priv)) {
1791                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1792                         assert_dsi_pll_enabled(dev_priv);
1793                 else
1794                         assert_pll_enabled(dev_priv, pipe);
1795         } else {
1796                 if (new_crtc_state->has_pch_encoder) {
1797                         /* if driving the PCH, we need FDI enabled */
1798                         assert_fdi_rx_pll_enabled(dev_priv,
1799                                                   intel_crtc_pch_transcoder(crtc));
1800                         assert_fdi_tx_pll_enabled(dev_priv,
1801                                                   (enum pipe) cpu_transcoder);
1802                 }
1803                 /* FIXME: assert CPU port conditions for SNB+ */
1804         }
1805
1806         trace_intel_pipe_enable(dev_priv, pipe);
1807
1808         reg = PIPECONF(cpu_transcoder);
1809         val = I915_READ(reg);
1810         if (val & PIPECONF_ENABLE) {
1811                 /* we keep both pipes enabled on 830 */
1812                 WARN_ON(!IS_I830(dev_priv));
1813                 return;
1814         }
1815
1816         I915_WRITE(reg, val | PIPECONF_ENABLE);
1817         POSTING_READ(reg);
1818
1819         /*
1820          * Until the pipe starts PIPEDSL reads will return a stale value,
1821          * which causes an apparent vblank timestamp jump when PIPEDSL
1822          * resets to its proper value. That also messes up the frame count
1823          * when it's derived from the timestamps. So let's wait for the
1824          * pipe to start properly before we call drm_crtc_vblank_on()
1825          */
1826         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1827                 intel_wait_for_pipe_scanline_moving(crtc);
1828 }
1829
1830 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1831 {
1832         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1833         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1834         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1835         enum pipe pipe = crtc->pipe;
1836         i915_reg_t reg;
1837         u32 val;
1838
1839         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1840
1841         /*
1842          * Make sure planes won't keep trying to pump pixels to us,
1843          * or we might hang the display.
1844          */
1845         assert_planes_disabled(crtc);
1846
1847         trace_intel_pipe_disable(dev_priv, pipe);
1848
1849         reg = PIPECONF(cpu_transcoder);
1850         val = I915_READ(reg);
1851         if ((val & PIPECONF_ENABLE) == 0)
1852                 return;
1853
1854         /*
1855          * Double wide has implications for planes
1856          * so best keep it disabled when not needed.
1857          */
1858         if (old_crtc_state->double_wide)
1859                 val &= ~PIPECONF_DOUBLE_WIDE;
1860
1861         /* Don't disable pipe or pipe PLLs if needed */
1862         if (!IS_I830(dev_priv))
1863                 val &= ~PIPECONF_ENABLE;
1864
1865         I915_WRITE(reg, val);
1866         if ((val & PIPECONF_ENABLE) == 0)
1867                 intel_wait_for_pipe_off(old_crtc_state);
1868 }
1869
1870 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1871 {
1872         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1873 }
1874
1875 static unsigned int
1876 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1877 {
1878         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1879         unsigned int cpp = fb->format->cpp[color_plane];
1880
1881         switch (fb->modifier) {
1882         case DRM_FORMAT_MOD_LINEAR:
1883                 return cpp;
1884         case I915_FORMAT_MOD_X_TILED:
1885                 if (IS_GEN(dev_priv, 2))
1886                         return 128;
1887                 else
1888                         return 512;
1889         case I915_FORMAT_MOD_Y_TILED_CCS:
1890                 if (color_plane == 1)
1891                         return 128;
1892                 /* fall through */
1893         case I915_FORMAT_MOD_Y_TILED:
1894                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1895                         return 128;
1896                 else
1897                         return 512;
1898         case I915_FORMAT_MOD_Yf_TILED_CCS:
1899                 if (color_plane == 1)
1900                         return 128;
1901                 /* fall through */
1902         case I915_FORMAT_MOD_Yf_TILED:
1903                 switch (cpp) {
1904                 case 1:
1905                         return 64;
1906                 case 2:
1907                 case 4:
1908                         return 128;
1909                 case 8:
1910                 case 16:
1911                         return 256;
1912                 default:
1913                         MISSING_CASE(cpp);
1914                         return cpp;
1915                 }
1916                 break;
1917         default:
1918                 MISSING_CASE(fb->modifier);
1919                 return cpp;
1920         }
1921 }
1922
1923 static unsigned int
1924 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
1925 {
1926         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1927                 return 1;
1928         else
1929                 return intel_tile_size(to_i915(fb->dev)) /
1930                         intel_tile_width_bytes(fb, color_plane);
1931 }
1932
1933 /* Return the tile dimensions in pixel units */
1934 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
1935                             unsigned int *tile_width,
1936                             unsigned int *tile_height)
1937 {
1938         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
1939         unsigned int cpp = fb->format->cpp[color_plane];
1940
1941         *tile_width = tile_width_bytes / cpp;
1942         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1943 }
1944
1945 unsigned int
1946 intel_fb_align_height(const struct drm_framebuffer *fb,
1947                       int color_plane, unsigned int height)
1948 {
1949         unsigned int tile_height = intel_tile_height(fb, color_plane);
1950
1951         return ALIGN(height, tile_height);
1952 }
1953
1954 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1955 {
1956         unsigned int size = 0;
1957         int i;
1958
1959         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
1960                 size += rot_info->plane[i].width * rot_info->plane[i].height;
1961
1962         return size;
1963 }
1964
1965 static void
1966 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
1967                         const struct drm_framebuffer *fb,
1968                         unsigned int rotation)
1969 {
1970         view->type = I915_GGTT_VIEW_NORMAL;
1971         if (drm_rotation_90_or_270(rotation)) {
1972                 view->type = I915_GGTT_VIEW_ROTATED;
1973                 view->rotated = to_intel_framebuffer(fb)->rot_info;
1974         }
1975 }
1976
1977 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
1978 {
1979         if (IS_I830(dev_priv))
1980                 return 16 * 1024;
1981         else if (IS_I85X(dev_priv))
1982                 return 256;
1983         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1984                 return 32;
1985         else
1986                 return 4 * 1024;
1987 }
1988
1989 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
1990 {
1991         if (INTEL_GEN(dev_priv) >= 9)
1992                 return 256 * 1024;
1993         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
1994                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1995                 return 128 * 1024;
1996         else if (INTEL_GEN(dev_priv) >= 4)
1997                 return 4 * 1024;
1998         else
1999                 return 0;
2000 }
2001
2002 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2003                                          int color_plane)
2004 {
2005         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2006
2007         /* AUX_DIST needs only 4K alignment */
2008         if (color_plane == 1)
2009                 return 4096;
2010
2011         switch (fb->modifier) {
2012         case DRM_FORMAT_MOD_LINEAR:
2013                 return intel_linear_alignment(dev_priv);
2014         case I915_FORMAT_MOD_X_TILED:
2015                 if (INTEL_GEN(dev_priv) >= 9)
2016                         return 256 * 1024;
2017                 return 0;
2018         case I915_FORMAT_MOD_Y_TILED_CCS:
2019         case I915_FORMAT_MOD_Yf_TILED_CCS:
2020         case I915_FORMAT_MOD_Y_TILED:
2021         case I915_FORMAT_MOD_Yf_TILED:
2022                 return 1 * 1024 * 1024;
2023         default:
2024                 MISSING_CASE(fb->modifier);
2025                 return 0;
2026         }
2027 }
2028
2029 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2030 {
2031         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2032         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2033
2034         return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2035 }
2036
2037 struct i915_vma *
2038 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2039                            const struct i915_ggtt_view *view,
2040                            bool uses_fence,
2041                            unsigned long *out_flags)
2042 {
2043         struct drm_device *dev = fb->dev;
2044         struct drm_i915_private *dev_priv = to_i915(dev);
2045         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2046         intel_wakeref_t wakeref;
2047         struct i915_vma *vma;
2048         unsigned int pinctl;
2049         u32 alignment;
2050
2051         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2052
2053         alignment = intel_surf_alignment(fb, 0);
2054
2055         /* Note that the w/a also requires 64 PTE of padding following the
2056          * bo. We currently fill all unused PTE with the shadow page and so
2057          * we should always have valid PTE following the scanout preventing
2058          * the VT-d warning.
2059          */
2060         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2061                 alignment = 256 * 1024;
2062
2063         /*
2064          * Global gtt pte registers are special registers which actually forward
2065          * writes to a chunk of system memory. Which means that there is no risk
2066          * that the register values disappear as soon as we call
2067          * intel_runtime_pm_put(), so it is correct to wrap only the
2068          * pin/unpin/fence and not more.
2069          */
2070         wakeref = intel_runtime_pm_get(dev_priv);
2071
2072         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2073
2074         pinctl = 0;
2075
2076         /* Valleyview is definitely limited to scanning out the first
2077          * 512MiB. Lets presume this behaviour was inherited from the
2078          * g4x display engine and that all earlier gen are similarly
2079          * limited. Testing suggests that it is a little more
2080          * complicated than this. For example, Cherryview appears quite
2081          * happy to scanout from anywhere within its global aperture.
2082          */
2083         if (HAS_GMCH(dev_priv))
2084                 pinctl |= PIN_MAPPABLE;
2085
2086         vma = i915_gem_object_pin_to_display_plane(obj,
2087                                                    alignment, view, pinctl);
2088         if (IS_ERR(vma))
2089                 goto err;
2090
2091         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2092                 int ret;
2093
2094                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2095                  * fence, whereas 965+ only requires a fence if using
2096                  * framebuffer compression.  For simplicity, we always, when
2097                  * possible, install a fence as the cost is not that onerous.
2098                  *
2099                  * If we fail to fence the tiled scanout, then either the
2100                  * modeset will reject the change (which is highly unlikely as
2101                  * the affected systems, all but one, do not have unmappable
2102                  * space) or we will not be able to enable full powersaving
2103                  * techniques (also likely not to apply due to various limits
2104                  * FBC and the like impose on the size of the buffer, which
2105                  * presumably we violated anyway with this unmappable buffer).
2106                  * Anyway, it is presumably better to stumble onwards with
2107                  * something and try to run the system in a "less than optimal"
2108                  * mode that matches the user configuration.
2109                  */
2110                 ret = i915_vma_pin_fence(vma);
2111                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2112                         i915_gem_object_unpin_from_display_plane(vma);
2113                         vma = ERR_PTR(ret);
2114                         goto err;
2115                 }
2116
2117                 if (ret == 0 && vma->fence)
2118                         *out_flags |= PLANE_HAS_FENCE;
2119         }
2120
2121         i915_vma_get(vma);
2122 err:
2123         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2124
2125         intel_runtime_pm_put(dev_priv, wakeref);
2126         return vma;
2127 }
2128
2129 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2130 {
2131         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2132
2133         if (flags & PLANE_HAS_FENCE)
2134                 i915_vma_unpin_fence(vma);
2135         i915_gem_object_unpin_from_display_plane(vma);
2136         i915_vma_put(vma);
2137 }
2138
2139 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2140                           unsigned int rotation)
2141 {
2142         if (drm_rotation_90_or_270(rotation))
2143                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2144         else
2145                 return fb->pitches[color_plane];
2146 }
2147
2148 /*
2149  * Convert the x/y offsets into a linear offset.
2150  * Only valid with 0/180 degree rotation, which is fine since linear
2151  * offset is only used with linear buffers on pre-hsw and tiled buffers
2152  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2153  */
2154 u32 intel_fb_xy_to_linear(int x, int y,
2155                           const struct intel_plane_state *state,
2156                           int color_plane)
2157 {
2158         const struct drm_framebuffer *fb = state->base.fb;
2159         unsigned int cpp = fb->format->cpp[color_plane];
2160         unsigned int pitch = state->color_plane[color_plane].stride;
2161
2162         return y * pitch + x * cpp;
2163 }
2164
2165 /*
2166  * Add the x/y offsets derived from fb->offsets[] to the user
2167  * specified plane src x/y offsets. The resulting x/y offsets
2168  * specify the start of scanout from the beginning of the gtt mapping.
2169  */
2170 void intel_add_fb_offsets(int *x, int *y,
2171                           const struct intel_plane_state *state,
2172                           int color_plane)
2173
2174 {
2175         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2176         unsigned int rotation = state->base.rotation;
2177
2178         if (drm_rotation_90_or_270(rotation)) {
2179                 *x += intel_fb->rotated[color_plane].x;
2180                 *y += intel_fb->rotated[color_plane].y;
2181         } else {
2182                 *x += intel_fb->normal[color_plane].x;
2183                 *y += intel_fb->normal[color_plane].y;
2184         }
2185 }
2186
2187 static u32 intel_adjust_tile_offset(int *x, int *y,
2188                                     unsigned int tile_width,
2189                                     unsigned int tile_height,
2190                                     unsigned int tile_size,
2191                                     unsigned int pitch_tiles,
2192                                     u32 old_offset,
2193                                     u32 new_offset)
2194 {
2195         unsigned int pitch_pixels = pitch_tiles * tile_width;
2196         unsigned int tiles;
2197
2198         WARN_ON(old_offset & (tile_size - 1));
2199         WARN_ON(new_offset & (tile_size - 1));
2200         WARN_ON(new_offset > old_offset);
2201
2202         tiles = (old_offset - new_offset) / tile_size;
2203
2204         *y += tiles / pitch_tiles * tile_height;
2205         *x += tiles % pitch_tiles * tile_width;
2206
2207         /* minimize x in case it got needlessly big */
2208         *y += *x / pitch_pixels * tile_height;
2209         *x %= pitch_pixels;
2210
2211         return new_offset;
2212 }
2213
2214 static bool is_surface_linear(u64 modifier, int color_plane)
2215 {
2216         return modifier == DRM_FORMAT_MOD_LINEAR;
2217 }
2218
2219 static u32 intel_adjust_aligned_offset(int *x, int *y,
2220                                        const struct drm_framebuffer *fb,
2221                                        int color_plane,
2222                                        unsigned int rotation,
2223                                        unsigned int pitch,
2224                                        u32 old_offset, u32 new_offset)
2225 {
2226         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2227         unsigned int cpp = fb->format->cpp[color_plane];
2228
2229         WARN_ON(new_offset > old_offset);
2230
2231         if (!is_surface_linear(fb->modifier, color_plane)) {
2232                 unsigned int tile_size, tile_width, tile_height;
2233                 unsigned int pitch_tiles;
2234
2235                 tile_size = intel_tile_size(dev_priv);
2236                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2237
2238                 if (drm_rotation_90_or_270(rotation)) {
2239                         pitch_tiles = pitch / tile_height;
2240                         swap(tile_width, tile_height);
2241                 } else {
2242                         pitch_tiles = pitch / (tile_width * cpp);
2243                 }
2244
2245                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2246                                          tile_size, pitch_tiles,
2247                                          old_offset, new_offset);
2248         } else {
2249                 old_offset += *y * pitch + *x * cpp;
2250
2251                 *y = (old_offset - new_offset) / pitch;
2252                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2253         }
2254
2255         return new_offset;
2256 }
2257
2258 /*
2259  * Adjust the tile offset by moving the difference into
2260  * the x/y offsets.
2261  */
2262 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2263                                              const struct intel_plane_state *state,
2264                                              int color_plane,
2265                                              u32 old_offset, u32 new_offset)
2266 {
2267         return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
2268                                            state->base.rotation,
2269                                            state->color_plane[color_plane].stride,
2270                                            old_offset, new_offset);
2271 }
2272
2273 /*
2274  * Computes the aligned offset to the base tile and adjusts
2275  * x, y. bytes per pixel is assumed to be a power-of-two.
2276  *
2277  * In the 90/270 rotated case, x and y are assumed
2278  * to be already rotated to match the rotated GTT view, and
2279  * pitch is the tile_height aligned framebuffer height.
2280  *
2281  * This function is used when computing the derived information
2282  * under intel_framebuffer, so using any of that information
2283  * here is not allowed. Anything under drm_framebuffer can be
2284  * used. This is why the user has to pass in the pitch since it
2285  * is specified in the rotated orientation.
2286  */
2287 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2288                                         int *x, int *y,
2289                                         const struct drm_framebuffer *fb,
2290                                         int color_plane,
2291                                         unsigned int pitch,
2292                                         unsigned int rotation,
2293                                         u32 alignment)
2294 {
2295         unsigned int cpp = fb->format->cpp[color_plane];
2296         u32 offset, offset_aligned;
2297
2298         if (alignment)
2299                 alignment--;
2300
2301         if (!is_surface_linear(fb->modifier, color_plane)) {
2302                 unsigned int tile_size, tile_width, tile_height;
2303                 unsigned int tile_rows, tiles, pitch_tiles;
2304
2305                 tile_size = intel_tile_size(dev_priv);
2306                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2307
2308                 if (drm_rotation_90_or_270(rotation)) {
2309                         pitch_tiles = pitch / tile_height;
2310                         swap(tile_width, tile_height);
2311                 } else {
2312                         pitch_tiles = pitch / (tile_width * cpp);
2313                 }
2314
2315                 tile_rows = *y / tile_height;
2316                 *y %= tile_height;
2317
2318                 tiles = *x / tile_width;
2319                 *x %= tile_width;
2320
2321                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2322                 offset_aligned = offset & ~alignment;
2323
2324                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2325                                          tile_size, pitch_tiles,
2326                                          offset, offset_aligned);
2327         } else {
2328                 offset = *y * pitch + *x * cpp;
2329                 offset_aligned = offset & ~alignment;
2330
2331                 *y = (offset & alignment) / pitch;
2332                 *x = ((offset & alignment) - *y * pitch) / cpp;
2333         }
2334
2335         return offset_aligned;
2336 }
2337
2338 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2339                                               const struct intel_plane_state *state,
2340                                               int color_plane)
2341 {
2342         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2343         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2344         const struct drm_framebuffer *fb = state->base.fb;
2345         unsigned int rotation = state->base.rotation;
2346         int pitch = state->color_plane[color_plane].stride;
2347         u32 alignment;
2348
2349         if (intel_plane->id == PLANE_CURSOR)
2350                 alignment = intel_cursor_alignment(dev_priv);
2351         else
2352                 alignment = intel_surf_alignment(fb, color_plane);
2353
2354         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2355                                             pitch, rotation, alignment);
2356 }
2357
2358 /* Convert the fb->offset[] into x/y offsets */
2359 static int intel_fb_offset_to_xy(int *x, int *y,
2360                                  const struct drm_framebuffer *fb,
2361                                  int color_plane)
2362 {
2363         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2364         unsigned int height;
2365
2366         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2367             fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2368                 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2369                               fb->offsets[color_plane], color_plane);
2370                 return -EINVAL;
2371         }
2372
2373         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2374         height = ALIGN(height, intel_tile_height(fb, color_plane));
2375
2376         /* Catch potential overflows early */
2377         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2378                             fb->offsets[color_plane])) {
2379                 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2380                               fb->offsets[color_plane], fb->pitches[color_plane],
2381                               color_plane);
2382                 return -ERANGE;
2383         }
2384
2385         *x = 0;
2386         *y = 0;
2387
2388         intel_adjust_aligned_offset(x, y,
2389                                     fb, color_plane, DRM_MODE_ROTATE_0,
2390                                     fb->pitches[color_plane],
2391                                     fb->offsets[color_plane], 0);
2392
2393         return 0;
2394 }
2395
2396 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2397 {
2398         switch (fb_modifier) {
2399         case I915_FORMAT_MOD_X_TILED:
2400                 return I915_TILING_X;
2401         case I915_FORMAT_MOD_Y_TILED:
2402         case I915_FORMAT_MOD_Y_TILED_CCS:
2403                 return I915_TILING_Y;
2404         default:
2405                 return I915_TILING_NONE;
2406         }
2407 }
2408
2409 /*
2410  * From the Sky Lake PRM:
2411  * "The Color Control Surface (CCS) contains the compression status of
2412  *  the cache-line pairs. The compression state of the cache-line pair
2413  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2414  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2415  *  cache-line-pairs. CCS is always Y tiled."
2416  *
2417  * Since cache line pairs refers to horizontally adjacent cache lines,
2418  * each cache line in the CCS corresponds to an area of 32x16 cache
2419  * lines on the main surface. Since each pixel is 4 bytes, this gives
2420  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2421  * main surface.
2422  */
2423 static const struct drm_format_info ccs_formats[] = {
2424         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2425         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2426         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2427         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2428 };
2429
2430 static const struct drm_format_info *
2431 lookup_format_info(const struct drm_format_info formats[],
2432                    int num_formats, u32 format)
2433 {
2434         int i;
2435
2436         for (i = 0; i < num_formats; i++) {
2437                 if (formats[i].format == format)
2438                         return &formats[i];
2439         }
2440
2441         return NULL;
2442 }
2443
2444 static const struct drm_format_info *
2445 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2446 {
2447         switch (cmd->modifier[0]) {
2448         case I915_FORMAT_MOD_Y_TILED_CCS:
2449         case I915_FORMAT_MOD_Yf_TILED_CCS:
2450                 return lookup_format_info(ccs_formats,
2451                                           ARRAY_SIZE(ccs_formats),
2452                                           cmd->pixel_format);
2453         default:
2454                 return NULL;
2455         }
2456 }
2457
2458 bool is_ccs_modifier(u64 modifier)
2459 {
2460         return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2461                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2462 }
2463
2464 static int
2465 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2466                    struct drm_framebuffer *fb)
2467 {
2468         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2469         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2470         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2471         u32 gtt_offset_rotated = 0;
2472         unsigned int max_size = 0;
2473         int i, num_planes = fb->format->num_planes;
2474         unsigned int tile_size = intel_tile_size(dev_priv);
2475
2476         for (i = 0; i < num_planes; i++) {
2477                 unsigned int width, height;
2478                 unsigned int cpp, size;
2479                 u32 offset;
2480                 int x, y;
2481                 int ret;
2482
2483                 cpp = fb->format->cpp[i];
2484                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2485                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2486
2487                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2488                 if (ret) {
2489                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2490                                       i, fb->offsets[i]);
2491                         return ret;
2492                 }
2493
2494                 if (is_ccs_modifier(fb->modifier) && i == 1) {
2495                         int hsub = fb->format->hsub;
2496                         int vsub = fb->format->vsub;
2497                         int tile_width, tile_height;
2498                         int main_x, main_y;
2499                         int ccs_x, ccs_y;
2500
2501                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2502                         tile_width *= hsub;
2503                         tile_height *= vsub;
2504
2505                         ccs_x = (x * hsub) % tile_width;
2506                         ccs_y = (y * vsub) % tile_height;
2507                         main_x = intel_fb->normal[0].x % tile_width;
2508                         main_y = intel_fb->normal[0].y % tile_height;
2509
2510                         /*
2511                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2512                          * x/y offsets must match between CCS and the main surface.
2513                          */
2514                         if (main_x != ccs_x || main_y != ccs_y) {
2515                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2516                                               main_x, main_y,
2517                                               ccs_x, ccs_y,
2518                                               intel_fb->normal[0].x,
2519                                               intel_fb->normal[0].y,
2520                                               x, y);
2521                                 return -EINVAL;
2522                         }
2523                 }
2524
2525                 /*
2526                  * The fence (if used) is aligned to the start of the object
2527                  * so having the framebuffer wrap around across the edge of the
2528                  * fenced region doesn't really work. We have no API to configure
2529                  * the fence start offset within the object (nor could we probably
2530                  * on gen2/3). So it's just easier if we just require that the
2531                  * fb layout agrees with the fence layout. We already check that the
2532                  * fb stride matches the fence stride elsewhere.
2533                  */
2534                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2535                     (x + width) * cpp > fb->pitches[i]) {
2536                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2537                                       i, fb->offsets[i]);
2538                         return -EINVAL;
2539                 }
2540
2541                 /*
2542                  * First pixel of the framebuffer from
2543                  * the start of the normal gtt mapping.
2544                  */
2545                 intel_fb->normal[i].x = x;
2546                 intel_fb->normal[i].y = y;
2547
2548                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2549                                                       fb->pitches[i],
2550                                                       DRM_MODE_ROTATE_0,
2551                                                       tile_size);
2552                 offset /= tile_size;
2553
2554                 if (!is_surface_linear(fb->modifier, i)) {
2555                         unsigned int tile_width, tile_height;
2556                         unsigned int pitch_tiles;
2557                         struct drm_rect r;
2558
2559                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2560
2561                         rot_info->plane[i].offset = offset;
2562                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2563                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2564                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2565
2566                         intel_fb->rotated[i].pitch =
2567                                 rot_info->plane[i].height * tile_height;
2568
2569                         /* how many tiles does this plane need */
2570                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2571                         /*
2572                          * If the plane isn't horizontally tile aligned,
2573                          * we need one more tile.
2574                          */
2575                         if (x != 0)
2576                                 size++;
2577
2578                         /* rotate the x/y offsets to match the GTT view */
2579                         r.x1 = x;
2580                         r.y1 = y;
2581                         r.x2 = x + width;
2582                         r.y2 = y + height;
2583                         drm_rect_rotate(&r,
2584                                         rot_info->plane[i].width * tile_width,
2585                                         rot_info->plane[i].height * tile_height,
2586                                         DRM_MODE_ROTATE_270);
2587                         x = r.x1;
2588                         y = r.y1;
2589
2590                         /* rotate the tile dimensions to match the GTT view */
2591                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2592                         swap(tile_width, tile_height);
2593
2594                         /*
2595                          * We only keep the x/y offsets, so push all of the
2596                          * gtt offset into the x/y offsets.
2597                          */
2598                         intel_adjust_tile_offset(&x, &y,
2599                                                  tile_width, tile_height,
2600                                                  tile_size, pitch_tiles,
2601                                                  gtt_offset_rotated * tile_size, 0);
2602
2603                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2604
2605                         /*
2606                          * First pixel of the framebuffer from
2607                          * the start of the rotated gtt mapping.
2608                          */
2609                         intel_fb->rotated[i].x = x;
2610                         intel_fb->rotated[i].y = y;
2611                 } else {
2612                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2613                                             x * cpp, tile_size);
2614                 }
2615
2616                 /* how many tiles in total needed in the bo */
2617                 max_size = max(max_size, offset + size);
2618         }
2619
2620         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2621                 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2622                               mul_u32_u32(max_size, tile_size), obj->base.size);
2623                 return -EINVAL;
2624         }
2625
2626         return 0;
2627 }
2628
2629 static int i9xx_format_to_fourcc(int format)
2630 {
2631         switch (format) {
2632         case DISPPLANE_8BPP:
2633                 return DRM_FORMAT_C8;
2634         case DISPPLANE_BGRX555:
2635                 return DRM_FORMAT_XRGB1555;
2636         case DISPPLANE_BGRX565:
2637                 return DRM_FORMAT_RGB565;
2638         default:
2639         case DISPPLANE_BGRX888:
2640                 return DRM_FORMAT_XRGB8888;
2641         case DISPPLANE_RGBX888:
2642                 return DRM_FORMAT_XBGR8888;
2643         case DISPPLANE_BGRX101010:
2644                 return DRM_FORMAT_XRGB2101010;
2645         case DISPPLANE_RGBX101010:
2646                 return DRM_FORMAT_XBGR2101010;
2647         }
2648 }
2649
2650 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2651 {
2652         switch (format) {
2653         case PLANE_CTL_FORMAT_RGB_565:
2654                 return DRM_FORMAT_RGB565;
2655         case PLANE_CTL_FORMAT_NV12:
2656                 return DRM_FORMAT_NV12;
2657         case PLANE_CTL_FORMAT_P010:
2658                 return DRM_FORMAT_P010;
2659         case PLANE_CTL_FORMAT_P012:
2660                 return DRM_FORMAT_P012;
2661         case PLANE_CTL_FORMAT_P016:
2662                 return DRM_FORMAT_P016;
2663         case PLANE_CTL_FORMAT_Y210:
2664                 return DRM_FORMAT_Y210;
2665         case PLANE_CTL_FORMAT_Y212:
2666                 return DRM_FORMAT_Y212;
2667         case PLANE_CTL_FORMAT_Y216:
2668                 return DRM_FORMAT_Y216;
2669         case PLANE_CTL_FORMAT_Y410:
2670                 return DRM_FORMAT_XVYU2101010;
2671         case PLANE_CTL_FORMAT_Y412:
2672                 return DRM_FORMAT_XVYU12_16161616;
2673         case PLANE_CTL_FORMAT_Y416:
2674                 return DRM_FORMAT_XVYU16161616;
2675         default:
2676         case PLANE_CTL_FORMAT_XRGB_8888:
2677                 if (rgb_order) {
2678                         if (alpha)
2679                                 return DRM_FORMAT_ABGR8888;
2680                         else
2681                                 return DRM_FORMAT_XBGR8888;
2682                 } else {
2683                         if (alpha)
2684                                 return DRM_FORMAT_ARGB8888;
2685                         else
2686                                 return DRM_FORMAT_XRGB8888;
2687                 }
2688         case PLANE_CTL_FORMAT_XRGB_2101010:
2689                 if (rgb_order)
2690                         return DRM_FORMAT_XBGR2101010;
2691                 else
2692                         return DRM_FORMAT_XRGB2101010;
2693         case PLANE_CTL_FORMAT_XRGB_16161616F:
2694                 if (rgb_order) {
2695                         if (alpha)
2696                                 return DRM_FORMAT_ABGR16161616F;
2697                         else
2698                                 return DRM_FORMAT_XBGR16161616F;
2699                 } else {
2700                         if (alpha)
2701                                 return DRM_FORMAT_ARGB16161616F;
2702                         else
2703                                 return DRM_FORMAT_XRGB16161616F;
2704                 }
2705         }
2706 }
2707
2708 static bool
2709 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2710                               struct intel_initial_plane_config *plane_config)
2711 {
2712         struct drm_device *dev = crtc->base.dev;
2713         struct drm_i915_private *dev_priv = to_i915(dev);
2714         struct drm_i915_gem_object *obj = NULL;
2715         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2716         struct drm_framebuffer *fb = &plane_config->fb->base;
2717         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2718         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2719                                     PAGE_SIZE);
2720
2721         size_aligned -= base_aligned;
2722
2723         if (plane_config->size == 0)
2724                 return false;
2725
2726         /* If the FB is too big, just don't use it since fbdev is not very
2727          * important and we should probably use that space with FBC or other
2728          * features. */
2729         if (size_aligned * 2 > dev_priv->stolen_usable_size)
2730                 return false;
2731
2732         switch (fb->modifier) {
2733         case DRM_FORMAT_MOD_LINEAR:
2734         case I915_FORMAT_MOD_X_TILED:
2735         case I915_FORMAT_MOD_Y_TILED:
2736                 break;
2737         default:
2738                 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
2739                                  fb->modifier);
2740                 return false;
2741         }
2742
2743         mutex_lock(&dev->struct_mutex);
2744         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2745                                                              base_aligned,
2746                                                              base_aligned,
2747                                                              size_aligned);
2748         mutex_unlock(&dev->struct_mutex);
2749         if (!obj)
2750                 return false;
2751
2752         switch (plane_config->tiling) {
2753         case I915_TILING_NONE:
2754                 break;
2755         case I915_TILING_X:
2756         case I915_TILING_Y:
2757                 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
2758                 break;
2759         default:
2760                 MISSING_CASE(plane_config->tiling);
2761                 return false;
2762         }
2763
2764         mode_cmd.pixel_format = fb->format->format;
2765         mode_cmd.width = fb->width;
2766         mode_cmd.height = fb->height;
2767         mode_cmd.pitches[0] = fb->pitches[0];
2768         mode_cmd.modifier[0] = fb->modifier;
2769         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2770
2771         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2772                 DRM_DEBUG_KMS("intel fb init failed\n");
2773                 goto out_unref_obj;
2774         }
2775
2776
2777         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2778         return true;
2779
2780 out_unref_obj:
2781         i915_gem_object_put(obj);
2782         return false;
2783 }
2784
2785 static void
2786 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2787                         struct intel_plane_state *plane_state,
2788                         bool visible)
2789 {
2790         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2791
2792         plane_state->base.visible = visible;
2793
2794         if (visible)
2795                 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2796         else
2797                 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2798 }
2799
2800 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
2801 {
2802         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2803         struct drm_plane *plane;
2804
2805         /*
2806          * Active_planes aliases if multiple "primary" or cursor planes
2807          * have been used on the same (or wrong) pipe. plane_mask uses
2808          * unique ids, hence we can use that to reconstruct active_planes.
2809          */
2810         crtc_state->active_planes = 0;
2811
2812         drm_for_each_plane_mask(plane, &dev_priv->drm,
2813                                 crtc_state->base.plane_mask)
2814                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
2815 }
2816
2817 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2818                                          struct intel_plane *plane)
2819 {
2820         struct intel_crtc_state *crtc_state =
2821                 to_intel_crtc_state(crtc->base.state);
2822         struct intel_plane_state *plane_state =
2823                 to_intel_plane_state(plane->base.state);
2824
2825         DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
2826                       plane->base.base.id, plane->base.name,
2827                       crtc->base.base.id, crtc->base.name);
2828
2829         intel_set_plane_visible(crtc_state, plane_state, false);
2830         fixup_active_planes(crtc_state);
2831
2832         if (plane->id == PLANE_PRIMARY)
2833                 intel_pre_disable_primary_noatomic(&crtc->base);
2834
2835         intel_disable_plane(plane, crtc_state);
2836 }
2837
2838 static void
2839 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2840                              struct intel_initial_plane_config *plane_config)
2841 {
2842         struct drm_device *dev = intel_crtc->base.dev;
2843         struct drm_i915_private *dev_priv = to_i915(dev);
2844         struct drm_crtc *c;
2845         struct drm_i915_gem_object *obj;
2846         struct drm_plane *primary = intel_crtc->base.primary;
2847         struct drm_plane_state *plane_state = primary->state;
2848         struct intel_plane *intel_plane = to_intel_plane(primary);
2849         struct intel_plane_state *intel_state =
2850                 to_intel_plane_state(plane_state);
2851         struct drm_framebuffer *fb;
2852
2853         if (!plane_config->fb)
2854                 return;
2855
2856         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2857                 fb = &plane_config->fb->base;
2858                 goto valid_fb;
2859         }
2860
2861         kfree(plane_config->fb);
2862
2863         /*
2864          * Failed to alloc the obj, check to see if we should share
2865          * an fb with another CRTC instead
2866          */
2867         for_each_crtc(dev, c) {
2868                 struct intel_plane_state *state;
2869
2870                 if (c == &intel_crtc->base)
2871                         continue;
2872
2873                 if (!to_intel_crtc(c)->active)
2874                         continue;
2875
2876                 state = to_intel_plane_state(c->primary->state);
2877                 if (!state->vma)
2878                         continue;
2879
2880                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2881                         fb = state->base.fb;
2882                         drm_framebuffer_get(fb);
2883                         goto valid_fb;
2884                 }
2885         }
2886
2887         /*
2888          * We've failed to reconstruct the BIOS FB.  Current display state
2889          * indicates that the primary plane is visible, but has a NULL FB,
2890          * which will lead to problems later if we don't fix it up.  The
2891          * simplest solution is to just disable the primary plane now and
2892          * pretend the BIOS never had it enabled.
2893          */
2894         intel_plane_disable_noatomic(intel_crtc, intel_plane);
2895
2896         return;
2897
2898 valid_fb:
2899         intel_state->base.rotation = plane_config->rotation;
2900         intel_fill_fb_ggtt_view(&intel_state->view, fb,
2901                                 intel_state->base.rotation);
2902         intel_state->color_plane[0].stride =
2903                 intel_fb_pitch(fb, 0, intel_state->base.rotation);
2904
2905         mutex_lock(&dev->struct_mutex);
2906         intel_state->vma =
2907                 intel_pin_and_fence_fb_obj(fb,
2908                                            &intel_state->view,
2909                                            intel_plane_uses_fence(intel_state),
2910                                            &intel_state->flags);
2911         mutex_unlock(&dev->struct_mutex);
2912         if (IS_ERR(intel_state->vma)) {
2913                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2914                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2915
2916                 intel_state->vma = NULL;
2917                 drm_framebuffer_put(fb);
2918                 return;
2919         }
2920
2921         obj = intel_fb_obj(fb);
2922         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2923
2924         plane_state->src_x = 0;
2925         plane_state->src_y = 0;
2926         plane_state->src_w = fb->width << 16;
2927         plane_state->src_h = fb->height << 16;
2928
2929         plane_state->crtc_x = 0;
2930         plane_state->crtc_y = 0;
2931         plane_state->crtc_w = fb->width;
2932         plane_state->crtc_h = fb->height;
2933
2934         intel_state->base.src = drm_plane_state_src(plane_state);
2935         intel_state->base.dst = drm_plane_state_dest(plane_state);
2936
2937         if (i915_gem_object_is_tiled(obj))
2938                 dev_priv->preserve_bios_swizzle = true;
2939
2940         plane_state->fb = fb;
2941         plane_state->crtc = &intel_crtc->base;
2942
2943         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2944                   &obj->frontbuffer_bits);
2945 }
2946
2947 static int skl_max_plane_width(const struct drm_framebuffer *fb,
2948                                int color_plane,
2949                                unsigned int rotation)
2950 {
2951         int cpp = fb->format->cpp[color_plane];
2952
2953         switch (fb->modifier) {
2954         case DRM_FORMAT_MOD_LINEAR:
2955         case I915_FORMAT_MOD_X_TILED:
2956                 switch (cpp) {
2957                 case 8:
2958                         return 4096;
2959                 case 4:
2960                 case 2:
2961                 case 1:
2962                         return 8192;
2963                 default:
2964                         MISSING_CASE(cpp);
2965                         break;
2966                 }
2967                 break;
2968         case I915_FORMAT_MOD_Y_TILED_CCS:
2969         case I915_FORMAT_MOD_Yf_TILED_CCS:
2970                 /* FIXME AUX plane? */
2971         case I915_FORMAT_MOD_Y_TILED:
2972         case I915_FORMAT_MOD_Yf_TILED:
2973                 switch (cpp) {
2974                 case 8:
2975                         return 2048;
2976                 case 4:
2977                         return 4096;
2978                 case 2:
2979                 case 1:
2980                         return 8192;
2981                 default:
2982                         MISSING_CASE(cpp);
2983                         break;
2984                 }
2985                 break;
2986         default:
2987                 MISSING_CASE(fb->modifier);
2988         }
2989
2990         return 2048;
2991 }
2992
2993 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2994                                            int main_x, int main_y, u32 main_offset)
2995 {
2996         const struct drm_framebuffer *fb = plane_state->base.fb;
2997         int hsub = fb->format->hsub;
2998         int vsub = fb->format->vsub;
2999         int aux_x = plane_state->color_plane[1].x;
3000         int aux_y = plane_state->color_plane[1].y;
3001         u32 aux_offset = plane_state->color_plane[1].offset;
3002         u32 alignment = intel_surf_alignment(fb, 1);
3003
3004         while (aux_offset >= main_offset && aux_y <= main_y) {
3005                 int x, y;
3006
3007                 if (aux_x == main_x && aux_y == main_y)
3008                         break;
3009
3010                 if (aux_offset == 0)
3011                         break;
3012
3013                 x = aux_x / hsub;
3014                 y = aux_y / vsub;
3015                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3016                                                                aux_offset, aux_offset - alignment);
3017                 aux_x = x * hsub + aux_x % hsub;
3018                 aux_y = y * vsub + aux_y % vsub;
3019         }
3020
3021         if (aux_x != main_x || aux_y != main_y)
3022                 return false;
3023
3024         plane_state->color_plane[1].offset = aux_offset;
3025         plane_state->color_plane[1].x = aux_x;
3026         plane_state->color_plane[1].y = aux_y;
3027
3028         return true;
3029 }
3030
3031 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3032 {
3033         const struct drm_framebuffer *fb = plane_state->base.fb;
3034         unsigned int rotation = plane_state->base.rotation;
3035         int x = plane_state->base.src.x1 >> 16;
3036         int y = plane_state->base.src.y1 >> 16;
3037         int w = drm_rect_width(&plane_state->base.src) >> 16;
3038         int h = drm_rect_height(&plane_state->base.src) >> 16;
3039         int max_width = skl_max_plane_width(fb, 0, rotation);
3040         int max_height = 4096;
3041         u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3042
3043         if (w > max_width || h > max_height) {
3044                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3045                               w, h, max_width, max_height);
3046                 return -EINVAL;
3047         }
3048
3049         intel_add_fb_offsets(&x, &y, plane_state, 0);
3050         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3051         alignment = intel_surf_alignment(fb, 0);
3052
3053         /*
3054          * AUX surface offset is specified as the distance from the
3055          * main surface offset, and it must be non-negative. Make
3056          * sure that is what we will get.
3057          */
3058         if (offset > aux_offset)
3059                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3060                                                            offset, aux_offset & ~(alignment - 1));
3061
3062         /*
3063          * When using an X-tiled surface, the plane blows up
3064          * if the x offset + width exceed the stride.
3065          *
3066          * TODO: linear and Y-tiled seem fine, Yf untested,
3067          */
3068         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3069                 int cpp = fb->format->cpp[0];
3070
3071                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3072                         if (offset == 0) {
3073                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3074                                 return -EINVAL;
3075                         }
3076
3077                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3078                                                                    offset, offset - alignment);
3079                 }
3080         }
3081
3082         /*
3083          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3084          * they match with the main surface x/y offsets.
3085          */
3086         if (is_ccs_modifier(fb->modifier)) {
3087                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3088                         if (offset == 0)
3089                                 break;
3090
3091                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3092                                                                    offset, offset - alignment);
3093                 }
3094
3095                 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3096                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3097                         return -EINVAL;
3098                 }
3099         }
3100
3101         plane_state->color_plane[0].offset = offset;
3102         plane_state->color_plane[0].x = x;
3103         plane_state->color_plane[0].y = y;
3104
3105         return 0;
3106 }
3107
3108 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3109 {
3110         const struct drm_framebuffer *fb = plane_state->base.fb;
3111         unsigned int rotation = plane_state->base.rotation;
3112         int max_width = skl_max_plane_width(fb, 1, rotation);
3113         int max_height = 4096;
3114         int x = plane_state->base.src.x1 >> 17;
3115         int y = plane_state->base.src.y1 >> 17;
3116         int w = drm_rect_width(&plane_state->base.src) >> 17;
3117         int h = drm_rect_height(&plane_state->base.src) >> 17;
3118         u32 offset;
3119
3120         intel_add_fb_offsets(&x, &y, plane_state, 1);
3121         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3122
3123         /* FIXME not quite sure how/if these apply to the chroma plane */
3124         if (w > max_width || h > max_height) {
3125                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3126                               w, h, max_width, max_height);
3127                 return -EINVAL;
3128         }
3129
3130         plane_state->color_plane[1].offset = offset;
3131         plane_state->color_plane[1].x = x;
3132         plane_state->color_plane[1].y = y;
3133
3134         return 0;
3135 }
3136
3137 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3138 {
3139         const struct drm_framebuffer *fb = plane_state->base.fb;
3140         int src_x = plane_state->base.src.x1 >> 16;
3141         int src_y = plane_state->base.src.y1 >> 16;
3142         int hsub = fb->format->hsub;
3143         int vsub = fb->format->vsub;
3144         int x = src_x / hsub;
3145         int y = src_y / vsub;
3146         u32 offset;
3147
3148         intel_add_fb_offsets(&x, &y, plane_state, 1);
3149         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3150
3151         plane_state->color_plane[1].offset = offset;
3152         plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3153         plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3154
3155         return 0;
3156 }
3157
3158 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3159 {
3160         const struct drm_framebuffer *fb = plane_state->base.fb;
3161         unsigned int rotation = plane_state->base.rotation;
3162         int ret;
3163
3164         intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
3165         plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
3166         plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
3167
3168         ret = intel_plane_check_stride(plane_state);
3169         if (ret)
3170                 return ret;
3171
3172         if (!plane_state->base.visible)
3173                 return 0;
3174
3175         /* Rotate src coordinates to match rotated GTT view */
3176         if (drm_rotation_90_or_270(rotation))
3177                 drm_rect_rotate(&plane_state->base.src,
3178                                 fb->width << 16, fb->height << 16,
3179                                 DRM_MODE_ROTATE_270);
3180
3181         /*
3182          * Handle the AUX surface first since
3183          * the main surface setup depends on it.
3184          */
3185         if (is_planar_yuv_format(fb->format->format)) {
3186                 ret = skl_check_nv12_aux_surface(plane_state);
3187                 if (ret)
3188                         return ret;
3189         } else if (is_ccs_modifier(fb->modifier)) {
3190                 ret = skl_check_ccs_aux_surface(plane_state);
3191                 if (ret)
3192                         return ret;
3193         } else {
3194                 plane_state->color_plane[1].offset = ~0xfff;
3195                 plane_state->color_plane[1].x = 0;
3196                 plane_state->color_plane[1].y = 0;
3197         }
3198
3199         ret = skl_check_main_surface(plane_state);
3200         if (ret)
3201                 return ret;
3202
3203         return 0;
3204 }
3205
3206 unsigned int
3207 i9xx_plane_max_stride(struct intel_plane *plane,
3208                       u32 pixel_format, u64 modifier,
3209                       unsigned int rotation)
3210 {
3211         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3212
3213         if (!HAS_GMCH(dev_priv)) {
3214                 return 32*1024;
3215         } else if (INTEL_GEN(dev_priv) >= 4) {
3216                 if (modifier == I915_FORMAT_MOD_X_TILED)
3217                         return 16*1024;
3218                 else
3219                         return 32*1024;
3220         } else if (INTEL_GEN(dev_priv) >= 3) {
3221                 if (modifier == I915_FORMAT_MOD_X_TILED)
3222                         return 8*1024;
3223                 else
3224                         return 16*1024;
3225         } else {
3226                 if (plane->i9xx_plane == PLANE_C)
3227                         return 4*1024;
3228                 else
3229                         return 8*1024;
3230         }
3231 }
3232
3233 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3234 {
3235         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3236         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3237         u32 dspcntr = 0;
3238
3239         if (crtc_state->gamma_enable)
3240                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3241
3242         if (crtc_state->csc_enable)
3243                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3244
3245         if (INTEL_GEN(dev_priv) < 5)
3246                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3247
3248         return dspcntr;
3249 }
3250
3251 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3252                           const struct intel_plane_state *plane_state)
3253 {
3254         struct drm_i915_private *dev_priv =
3255                 to_i915(plane_state->base.plane->dev);
3256         const struct drm_framebuffer *fb = plane_state->base.fb;
3257         unsigned int rotation = plane_state->base.rotation;
3258         u32 dspcntr;
3259
3260         dspcntr = DISPLAY_PLANE_ENABLE;
3261
3262         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3263             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3264                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3265
3266         switch (fb->format->format) {
3267         case DRM_FORMAT_C8:
3268                 dspcntr |= DISPPLANE_8BPP;
3269                 break;
3270         case DRM_FORMAT_XRGB1555:
3271                 dspcntr |= DISPPLANE_BGRX555;
3272                 break;
3273         case DRM_FORMAT_RGB565:
3274                 dspcntr |= DISPPLANE_BGRX565;
3275                 break;
3276         case DRM_FORMAT_XRGB8888:
3277                 dspcntr |= DISPPLANE_BGRX888;
3278                 break;
3279         case DRM_FORMAT_XBGR8888:
3280                 dspcntr |= DISPPLANE_RGBX888;
3281                 break;
3282         case DRM_FORMAT_XRGB2101010:
3283                 dspcntr |= DISPPLANE_BGRX101010;
3284                 break;
3285         case DRM_FORMAT_XBGR2101010:
3286                 dspcntr |= DISPPLANE_RGBX101010;
3287                 break;
3288         default:
3289                 MISSING_CASE(fb->format->format);
3290                 return 0;
3291         }
3292
3293         if (INTEL_GEN(dev_priv) >= 4 &&
3294             fb->modifier == I915_FORMAT_MOD_X_TILED)
3295                 dspcntr |= DISPPLANE_TILED;
3296
3297         if (rotation & DRM_MODE_ROTATE_180)
3298                 dspcntr |= DISPPLANE_ROTATE_180;
3299
3300         if (rotation & DRM_MODE_REFLECT_X)
3301                 dspcntr |= DISPPLANE_MIRROR;
3302
3303         return dspcntr;
3304 }
3305
3306 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3307 {
3308         struct drm_i915_private *dev_priv =
3309                 to_i915(plane_state->base.plane->dev);
3310         const struct drm_framebuffer *fb = plane_state->base.fb;
3311         unsigned int rotation = plane_state->base.rotation;
3312         int src_x = plane_state->base.src.x1 >> 16;
3313         int src_y = plane_state->base.src.y1 >> 16;
3314         u32 offset;
3315         int ret;
3316
3317         intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
3318         plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
3319
3320         ret = intel_plane_check_stride(plane_state);
3321         if (ret)
3322                 return ret;
3323
3324         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3325
3326         if (INTEL_GEN(dev_priv) >= 4)
3327                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3328                                                             plane_state, 0);
3329         else
3330                 offset = 0;
3331
3332         /* HSW/BDW do this automagically in hardware */
3333         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3334                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3335                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3336
3337                 if (rotation & DRM_MODE_ROTATE_180) {
3338                         src_x += src_w - 1;
3339                         src_y += src_h - 1;
3340                 } else if (rotation & DRM_MODE_REFLECT_X) {
3341                         src_x += src_w - 1;
3342                 }
3343         }
3344
3345         plane_state->color_plane[0].offset = offset;
3346         plane_state->color_plane[0].x = src_x;
3347         plane_state->color_plane[0].y = src_y;
3348
3349         return 0;
3350 }
3351
3352 static int
3353 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3354                  struct intel_plane_state *plane_state)
3355 {
3356         int ret;
3357
3358         ret = chv_plane_check_rotation(plane_state);
3359         if (ret)
3360                 return ret;
3361
3362         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
3363                                                   &crtc_state->base,
3364                                                   DRM_PLANE_HELPER_NO_SCALING,
3365                                                   DRM_PLANE_HELPER_NO_SCALING,
3366                                                   false, true);
3367         if (ret)
3368                 return ret;
3369
3370         if (!plane_state->base.visible)
3371                 return 0;
3372
3373         ret = intel_plane_check_src_coordinates(plane_state);
3374         if (ret)
3375                 return ret;
3376
3377         ret = i9xx_check_plane_surface(plane_state);
3378         if (ret)
3379                 return ret;
3380
3381         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3382
3383         return 0;
3384 }
3385
3386 static void i9xx_update_plane(struct intel_plane *plane,
3387                               const struct intel_crtc_state *crtc_state,
3388                               const struct intel_plane_state *plane_state)
3389 {
3390         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3391         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3392         u32 linear_offset;
3393         int x = plane_state->color_plane[0].x;
3394         int y = plane_state->color_plane[0].y;
3395         unsigned long irqflags;
3396         u32 dspaddr_offset;
3397         u32 dspcntr;
3398
3399         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3400
3401         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3402
3403         if (INTEL_GEN(dev_priv) >= 4)
3404                 dspaddr_offset = plane_state->color_plane[0].offset;
3405         else
3406                 dspaddr_offset = linear_offset;
3407
3408         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3409
3410         I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3411
3412         if (INTEL_GEN(dev_priv) < 4) {
3413                 /* pipesrc and dspsize control the size that is scaled from,
3414                  * which should always be the user's requested size.
3415                  */
3416                 I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
3417                 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3418                               ((crtc_state->pipe_src_h - 1) << 16) |
3419                               (crtc_state->pipe_src_w - 1));
3420         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3421                 I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
3422                 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3423                               ((crtc_state->pipe_src_h - 1) << 16) |
3424                               (crtc_state->pipe_src_w - 1));
3425                 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3426         }
3427
3428         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3429                 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3430         } else if (INTEL_GEN(dev_priv) >= 4) {
3431                 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3432                 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3433         }
3434
3435         /*
3436          * The control register self-arms if the plane was previously
3437          * disabled. Try to make the plane enable atomic by writing
3438          * the control register just before the surface register.
3439          */
3440         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3441         if (INTEL_GEN(dev_priv) >= 4)
3442                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3443                               intel_plane_ggtt_offset(plane_state) +
3444                               dspaddr_offset);
3445         else
3446                 I915_WRITE_FW(DSPADDR(i9xx_plane),
3447                               intel_plane_ggtt_offset(plane_state) +
3448                               dspaddr_offset);
3449
3450         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3451 }
3452
3453 static void i9xx_disable_plane(struct intel_plane *plane,
3454                                const struct intel_crtc_state *crtc_state)
3455 {
3456         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3457         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3458         unsigned long irqflags;
3459         u32 dspcntr;
3460
3461         /*
3462          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
3463          * enable on ilk+ affect the pipe bottom color as
3464          * well, so we must configure them even if the plane
3465          * is disabled.
3466          *
3467          * On pre-g4x there is no way to gamma correct the
3468          * pipe bottom color but we'll keep on doing this
3469          * anyway so that the crtc state readout works correctly.
3470          */
3471         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
3472
3473         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3474
3475         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3476         if (INTEL_GEN(dev_priv) >= 4)
3477                 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3478         else
3479                 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3480
3481         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3482 }
3483
3484 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
3485                                     enum pipe *pipe)
3486 {
3487         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3488         enum intel_display_power_domain power_domain;
3489         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3490         intel_wakeref_t wakeref;
3491         bool ret;
3492         u32 val;
3493
3494         /*
3495          * Not 100% correct for planes that can move between pipes,
3496          * but that's only the case for gen2-4 which don't have any
3497          * display power wells.
3498          */
3499         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
3500         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3501         if (!wakeref)
3502                 return false;
3503
3504         val = I915_READ(DSPCNTR(i9xx_plane));
3505
3506         ret = val & DISPLAY_PLANE_ENABLE;
3507
3508         if (INTEL_GEN(dev_priv) >= 5)
3509                 *pipe = plane->pipe;
3510         else
3511                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
3512                         DISPPLANE_SEL_PIPE_SHIFT;
3513
3514         intel_display_power_put(dev_priv, power_domain, wakeref);
3515
3516         return ret;
3517 }
3518
3519 static u32
3520 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
3521 {
3522         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3523                 return 64;
3524         else
3525                 return intel_tile_width_bytes(fb, color_plane);
3526 }
3527
3528 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3529 {
3530         struct drm_device *dev = intel_crtc->base.dev;
3531         struct drm_i915_private *dev_priv = to_i915(dev);
3532
3533         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3534         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3535         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3536 }
3537
3538 /*
3539  * This function detaches (aka. unbinds) unused scalers in hardware
3540  */
3541 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
3542 {
3543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3544         const struct intel_crtc_scaler_state *scaler_state =
3545                 &crtc_state->scaler_state;
3546         int i;
3547
3548         /* loop through and disable scalers that aren't in use */
3549         for (i = 0; i < intel_crtc->num_scalers; i++) {
3550                 if (!scaler_state->scalers[i].in_use)
3551                         skl_detach_scaler(intel_crtc, i);
3552         }
3553 }
3554
3555 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
3556                                           int color_plane, unsigned int rotation)
3557 {
3558         /*
3559          * The stride is either expressed as a multiple of 64 bytes chunks for
3560          * linear buffers or in number of tiles for tiled buffers.
3561          */
3562         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3563                 return 64;
3564         else if (drm_rotation_90_or_270(rotation))
3565                 return intel_tile_height(fb, color_plane);
3566         else
3567                 return intel_tile_width_bytes(fb, color_plane);
3568 }
3569
3570 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
3571                      int color_plane)
3572 {
3573         const struct drm_framebuffer *fb = plane_state->base.fb;
3574         unsigned int rotation = plane_state->base.rotation;
3575         u32 stride = plane_state->color_plane[color_plane].stride;
3576
3577         if (color_plane >= fb->format->num_planes)
3578                 return 0;
3579
3580         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
3581 }
3582
3583 static u32 skl_plane_ctl_format(u32 pixel_format)
3584 {
3585         switch (pixel_format) {
3586         case DRM_FORMAT_C8:
3587                 return PLANE_CTL_FORMAT_INDEXED;
3588         case DRM_FORMAT_RGB565:
3589                 return PLANE_CTL_FORMAT_RGB_565;
3590         case DRM_FORMAT_XBGR8888:
3591         case DRM_FORMAT_ABGR8888:
3592                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3593         case DRM_FORMAT_XRGB8888:
3594         case DRM_FORMAT_ARGB8888:
3595                 return PLANE_CTL_FORMAT_XRGB_8888;
3596         case DRM_FORMAT_XRGB2101010:
3597                 return PLANE_CTL_FORMAT_XRGB_2101010;
3598         case DRM_FORMAT_XBGR2101010:
3599                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3600         case DRM_FORMAT_XBGR16161616F:
3601         case DRM_FORMAT_ABGR16161616F:
3602                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
3603         case DRM_FORMAT_XRGB16161616F:
3604         case DRM_FORMAT_ARGB16161616F:
3605                 return PLANE_CTL_FORMAT_XRGB_16161616F;
3606         case DRM_FORMAT_YUYV:
3607                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3608         case DRM_FORMAT_YVYU:
3609                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3610         case DRM_FORMAT_UYVY:
3611                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3612         case DRM_FORMAT_VYUY:
3613                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3614         case DRM_FORMAT_NV12:
3615                 return PLANE_CTL_FORMAT_NV12;
3616         case DRM_FORMAT_P010:
3617                 return PLANE_CTL_FORMAT_P010;
3618         case DRM_FORMAT_P012:
3619                 return PLANE_CTL_FORMAT_P012;
3620         case DRM_FORMAT_P016:
3621                 return PLANE_CTL_FORMAT_P016;
3622         case DRM_FORMAT_Y210:
3623                 return PLANE_CTL_FORMAT_Y210;
3624         case DRM_FORMAT_Y212:
3625                 return PLANE_CTL_FORMAT_Y212;
3626         case DRM_FORMAT_Y216:
3627                 return PLANE_CTL_FORMAT_Y216;
3628         case DRM_FORMAT_XVYU2101010:
3629                 return PLANE_CTL_FORMAT_Y410;
3630         case DRM_FORMAT_XVYU12_16161616:
3631                 return PLANE_CTL_FORMAT_Y412;
3632         case DRM_FORMAT_XVYU16161616:
3633                 return PLANE_CTL_FORMAT_Y416;
3634         default:
3635                 MISSING_CASE(pixel_format);
3636         }
3637
3638         return 0;
3639 }
3640
3641 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
3642 {
3643         if (!plane_state->base.fb->format->has_alpha)
3644                 return PLANE_CTL_ALPHA_DISABLE;
3645
3646         switch (plane_state->base.pixel_blend_mode) {
3647         case DRM_MODE_BLEND_PIXEL_NONE:
3648                 return PLANE_CTL_ALPHA_DISABLE;
3649         case DRM_MODE_BLEND_PREMULTI:
3650                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3651         case DRM_MODE_BLEND_COVERAGE:
3652                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
3653         default:
3654                 MISSING_CASE(plane_state->base.pixel_blend_mode);
3655                 return PLANE_CTL_ALPHA_DISABLE;
3656         }
3657 }
3658
3659 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
3660 {
3661         if (!plane_state->base.fb->format->has_alpha)
3662                 return PLANE_COLOR_ALPHA_DISABLE;
3663
3664         switch (plane_state->base.pixel_blend_mode) {
3665         case DRM_MODE_BLEND_PIXEL_NONE:
3666                 return PLANE_COLOR_ALPHA_DISABLE;
3667         case DRM_MODE_BLEND_PREMULTI:
3668                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3669         case DRM_MODE_BLEND_COVERAGE:
3670                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
3671         default:
3672                 MISSING_CASE(plane_state->base.pixel_blend_mode);
3673                 return PLANE_COLOR_ALPHA_DISABLE;
3674         }
3675 }
3676
3677 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
3678 {
3679         switch (fb_modifier) {
3680         case DRM_FORMAT_MOD_LINEAR:
3681                 break;
3682         case I915_FORMAT_MOD_X_TILED:
3683                 return PLANE_CTL_TILED_X;
3684         case I915_FORMAT_MOD_Y_TILED:
3685                 return PLANE_CTL_TILED_Y;
3686         case I915_FORMAT_MOD_Y_TILED_CCS:
3687                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3688         case I915_FORMAT_MOD_Yf_TILED:
3689                 return PLANE_CTL_TILED_YF;
3690         case I915_FORMAT_MOD_Yf_TILED_CCS:
3691                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3692         default:
3693                 MISSING_CASE(fb_modifier);
3694         }
3695
3696         return 0;
3697 }
3698
3699 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3700 {
3701         switch (rotate) {
3702         case DRM_MODE_ROTATE_0:
3703                 break;
3704         /*
3705          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3706          * while i915 HW rotation is clockwise, thats why this swapping.
3707          */
3708         case DRM_MODE_ROTATE_90:
3709                 return PLANE_CTL_ROTATE_270;
3710         case DRM_MODE_ROTATE_180:
3711                 return PLANE_CTL_ROTATE_180;
3712         case DRM_MODE_ROTATE_270:
3713                 return PLANE_CTL_ROTATE_90;
3714         default:
3715                 MISSING_CASE(rotate);
3716         }
3717
3718         return 0;
3719 }
3720
3721 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3722 {
3723         switch (reflect) {
3724         case 0:
3725                 break;
3726         case DRM_MODE_REFLECT_X:
3727                 return PLANE_CTL_FLIP_HORIZONTAL;
3728         case DRM_MODE_REFLECT_Y:
3729         default:
3730                 MISSING_CASE(reflect);
3731         }
3732
3733         return 0;
3734 }
3735
3736 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3737 {
3738         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3739         u32 plane_ctl = 0;
3740
3741         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3742                 return plane_ctl;
3743
3744         if (crtc_state->gamma_enable)
3745                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
3746
3747         if (crtc_state->csc_enable)
3748                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
3749
3750         return plane_ctl;
3751 }
3752
3753 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3754                   const struct intel_plane_state *plane_state)
3755 {
3756         struct drm_i915_private *dev_priv =
3757                 to_i915(plane_state->base.plane->dev);
3758         const struct drm_framebuffer *fb = plane_state->base.fb;
3759         unsigned int rotation = plane_state->base.rotation;
3760         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3761         u32 plane_ctl;
3762
3763         plane_ctl = PLANE_CTL_ENABLE;
3764
3765         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3766                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
3767                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3768
3769                 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3770                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3771
3772                 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3773                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3774         }
3775
3776         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3777         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3778         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3779
3780         if (INTEL_GEN(dev_priv) >= 10)
3781                 plane_ctl |= cnl_plane_ctl_flip(rotation &
3782                                                 DRM_MODE_REFLECT_MASK);
3783
3784         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3785                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3786         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3787                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3788
3789         return plane_ctl;
3790 }
3791
3792 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
3793 {
3794         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3795         u32 plane_color_ctl = 0;
3796
3797         if (INTEL_GEN(dev_priv) >= 11)
3798                 return plane_color_ctl;
3799
3800         if (crtc_state->gamma_enable)
3801                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3802
3803         if (crtc_state->csc_enable)
3804                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3805
3806         return plane_color_ctl;
3807 }
3808
3809 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3810                         const struct intel_plane_state *plane_state)
3811 {
3812         struct drm_i915_private *dev_priv =
3813                 to_i915(plane_state->base.plane->dev);
3814         const struct drm_framebuffer *fb = plane_state->base.fb;
3815         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3816         u32 plane_color_ctl = 0;
3817
3818         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3819         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
3820
3821         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
3822                 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3823                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3824                 else
3825                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
3826
3827                 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3828                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3829         } else if (fb->format->is_yuv) {
3830                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
3831         }
3832
3833         return plane_color_ctl;
3834 }
3835
3836 static int
3837 __intel_display_resume(struct drm_device *dev,
3838                        struct drm_atomic_state *state,
3839                        struct drm_modeset_acquire_ctx *ctx)
3840 {
3841         struct drm_crtc_state *crtc_state;
3842         struct drm_crtc *crtc;
3843         int i, ret;
3844
3845         intel_modeset_setup_hw_state(dev, ctx);
3846         i915_redisable_vga(to_i915(dev));
3847
3848         if (!state)
3849                 return 0;
3850
3851         /*
3852          * We've duplicated the state, pointers to the old state are invalid.
3853          *
3854          * Don't attempt to use the old state until we commit the duplicated state.
3855          */
3856         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3857                 /*
3858                  * Force recalculation even if we restore
3859                  * current state. With fast modeset this may not result
3860                  * in a modeset when the state is compatible.
3861                  */
3862                 crtc_state->mode_changed = true;
3863         }
3864
3865         /* ignore any reset values/BIOS leftovers in the WM registers */
3866         if (!HAS_GMCH(to_i915(dev)))
3867                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3868
3869         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3870
3871         WARN_ON(ret == -EDEADLK);
3872         return ret;
3873 }
3874
3875 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3876 {
3877         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
3878                 intel_has_gpu_reset(dev_priv));
3879 }
3880
3881 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3882 {
3883         struct drm_device *dev = &dev_priv->drm;
3884         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3885         struct drm_atomic_state *state;
3886         int ret;
3887
3888         /* reset doesn't touch the display */
3889         if (!i915_modparams.force_reset_modeset_test &&
3890             !gpu_reset_clobbers_display(dev_priv))
3891                 return;
3892
3893         /* We have a modeset vs reset deadlock, defensively unbreak it. */
3894         set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3895         wake_up_all(&dev_priv->gpu_error.wait_queue);
3896
3897         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3898                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3899                 i915_gem_set_wedged(dev_priv);
3900         }
3901
3902         /*
3903          * Need mode_config.mutex so that we don't
3904          * trample ongoing ->detect() and whatnot.
3905          */
3906         mutex_lock(&dev->mode_config.mutex);
3907         drm_modeset_acquire_init(ctx, 0);
3908         while (1) {
3909                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3910                 if (ret != -EDEADLK)
3911                         break;
3912
3913                 drm_modeset_backoff(ctx);
3914         }
3915         /*
3916          * Disabling the crtcs gracefully seems nicer. Also the
3917          * g33 docs say we should at least disable all the planes.
3918          */
3919         state = drm_atomic_helper_duplicate_state(dev, ctx);
3920         if (IS_ERR(state)) {
3921                 ret = PTR_ERR(state);
3922                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3923                 return;
3924         }
3925
3926         ret = drm_atomic_helper_disable_all(dev, ctx);
3927         if (ret) {
3928                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3929                 drm_atomic_state_put(state);
3930                 return;
3931         }
3932
3933         dev_priv->modeset_restore_state = state;
3934         state->acquire_ctx = ctx;
3935 }
3936
3937 void intel_finish_reset(struct drm_i915_private *dev_priv)
3938 {
3939         struct drm_device *dev = &dev_priv->drm;
3940         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3941         struct drm_atomic_state *state;
3942         int ret;
3943
3944         /* reset doesn't touch the display */
3945         if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
3946                 return;
3947
3948         state = fetch_and_zero(&dev_priv->modeset_restore_state);
3949         if (!state)
3950                 goto unlock;
3951
3952         /* reset doesn't touch the display */
3953         if (!gpu_reset_clobbers_display(dev_priv)) {
3954                 /* for testing only restore the display */
3955                 ret = __intel_display_resume(dev, state, ctx);
3956                 if (ret)
3957                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3958         } else {
3959                 /*
3960                  * The display has been reset as well,
3961                  * so need a full re-initialization.
3962                  */
3963                 intel_pps_unlock_regs_wa(dev_priv);
3964                 intel_modeset_init_hw(dev);
3965                 intel_init_clock_gating(dev_priv);
3966
3967                 spin_lock_irq(&dev_priv->irq_lock);
3968                 if (dev_priv->display.hpd_irq_setup)
3969                         dev_priv->display.hpd_irq_setup(dev_priv);
3970                 spin_unlock_irq(&dev_priv->irq_lock);
3971
3972                 ret = __intel_display_resume(dev, state, ctx);
3973                 if (ret)
3974                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3975
3976                 intel_hpd_init(dev_priv);
3977         }
3978
3979         drm_atomic_state_put(state);
3980 unlock:
3981         drm_modeset_drop_locks(ctx);
3982         drm_modeset_acquire_fini(ctx);
3983         mutex_unlock(&dev->mode_config.mutex);
3984
3985         clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3986 }
3987
3988 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
3989 {
3990         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3991         enum pipe pipe = crtc->pipe;
3992         u32 tmp;
3993
3994         tmp = I915_READ(PIPE_CHICKEN(pipe));
3995
3996         /*
3997          * Display WA #1153: icl
3998          * enable hardware to bypass the alpha math
3999          * and rounding for per-pixel values 00 and 0xff
4000          */
4001         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4002         /*
4003          * Display WA # 1605353570: icl
4004          * Set the pixel rounding bit to 1 for allowing
4005          * passthrough of Frame buffer pixels unmodified
4006          * across pipe
4007          */
4008         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4009         I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4010 }
4011
4012 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
4013                                      const struct intel_crtc_state *new_crtc_state)
4014 {
4015         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
4016         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4017
4018         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
4019         crtc->base.mode = new_crtc_state->base.mode;
4020
4021         /*
4022          * Update pipe size and adjust fitter if needed: the reason for this is
4023          * that in compute_mode_changes we check the native mode (not the pfit
4024          * mode) to see if we can flip rather than do a full mode set. In the
4025          * fastboot case, we'll flip, but if we don't update the pipesrc and
4026          * pfit state, we'll end up with a big fb scanned out into the wrong
4027          * sized surface.
4028          */
4029
4030         I915_WRITE(PIPESRC(crtc->pipe),
4031                    ((new_crtc_state->pipe_src_w - 1) << 16) |
4032                    (new_crtc_state->pipe_src_h - 1));
4033
4034         /* on skylake this is done by detaching scalers */
4035         if (INTEL_GEN(dev_priv) >= 9) {
4036                 skl_detach_scalers(new_crtc_state);
4037
4038                 if (new_crtc_state->pch_pfit.enabled)
4039                         skylake_pfit_enable(new_crtc_state);
4040         } else if (HAS_PCH_SPLIT(dev_priv)) {
4041                 if (new_crtc_state->pch_pfit.enabled)
4042                         ironlake_pfit_enable(new_crtc_state);
4043                 else if (old_crtc_state->pch_pfit.enabled)
4044                         ironlake_pfit_disable(old_crtc_state);
4045         }
4046
4047         if (INTEL_GEN(dev_priv) >= 11)
4048                 icl_set_pipe_chicken(crtc);
4049 }
4050
4051 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4052 {
4053         struct drm_device *dev = crtc->base.dev;
4054         struct drm_i915_private *dev_priv = to_i915(dev);
4055         int pipe = crtc->pipe;
4056         i915_reg_t reg;
4057         u32 temp;
4058
4059         /* enable normal train */
4060         reg = FDI_TX_CTL(pipe);
4061         temp = I915_READ(reg);
4062         if (IS_IVYBRIDGE(dev_priv)) {
4063                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4064                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4065         } else {
4066                 temp &= ~FDI_LINK_TRAIN_NONE;
4067                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4068         }
4069         I915_WRITE(reg, temp);
4070
4071         reg = FDI_RX_CTL(pipe);
4072         temp = I915_READ(reg);
4073         if (HAS_PCH_CPT(dev_priv)) {
4074                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4075                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4076         } else {
4077                 temp &= ~FDI_LINK_TRAIN_NONE;
4078                 temp |= FDI_LINK_TRAIN_NONE;
4079         }
4080         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4081
4082         /* wait one idle pattern time */
4083         POSTING_READ(reg);
4084         udelay(1000);
4085
4086         /* IVB wants error correction enabled */
4087         if (IS_IVYBRIDGE(dev_priv))
4088                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4089                            FDI_FE_ERRC_ENABLE);
4090 }
4091
4092 /* The FDI link training functions for ILK/Ibexpeak. */
4093 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4094                                     const struct intel_crtc_state *crtc_state)
4095 {
4096         struct drm_device *dev = crtc->base.dev;
4097         struct drm_i915_private *dev_priv = to_i915(dev);
4098         int pipe = crtc->pipe;
4099         i915_reg_t reg;
4100         u32 temp, tries;
4101
4102         /* FDI needs bits from pipe first */
4103         assert_pipe_enabled(dev_priv, pipe);
4104
4105         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4106            for train result */
4107         reg = FDI_RX_IMR(pipe);
4108         temp = I915_READ(reg);
4109         temp &= ~FDI_RX_SYMBOL_LOCK;
4110         temp &= ~FDI_RX_BIT_LOCK;
4111         I915_WRITE(reg, temp);
4112         I915_READ(reg);
4113         udelay(150);
4114
4115         /* enable CPU FDI TX and PCH FDI RX */
4116         reg = FDI_TX_CTL(pipe);
4117         temp = I915_READ(reg);
4118         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4119         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4120         temp &= ~FDI_LINK_TRAIN_NONE;
4121         temp |= FDI_LINK_TRAIN_PATTERN_1;
4122         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4123
4124         reg = FDI_RX_CTL(pipe);
4125         temp = I915_READ(reg);
4126         temp &= ~FDI_LINK_TRAIN_NONE;
4127         temp |= FDI_LINK_TRAIN_PATTERN_1;
4128         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4129
4130         POSTING_READ(reg);
4131         udelay(150);
4132
4133         /* Ironlake workaround, enable clock pointer after FDI enable*/
4134         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4135         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4136                    FDI_RX_PHASE_SYNC_POINTER_EN);
4137
4138         reg = FDI_RX_IIR(pipe);
4139         for (tries = 0; tries < 5; tries++) {
4140                 temp = I915_READ(reg);
4141                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4142
4143                 if ((temp & FDI_RX_BIT_LOCK)) {
4144                         DRM_DEBUG_KMS("FDI train 1 done.\n");
4145                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4146                         break;
4147                 }
4148         }
4149         if (tries == 5)
4150                 DRM_ERROR("FDI train 1 fail!\n");
4151
4152         /* Train 2 */
4153         reg = FDI_TX_CTL(pipe);
4154         temp = I915_READ(reg);
4155         temp &= ~FDI_LINK_TRAIN_NONE;
4156         temp |= FDI_LINK_TRAIN_PATTERN_2;
4157         I915_WRITE(reg, temp);
4158
4159         reg = FDI_RX_CTL(pipe);
4160         temp = I915_READ(reg);
4161         temp &= ~FDI_LINK_TRAIN_NONE;
4162         temp |= FDI_LINK_TRAIN_PATTERN_2;
4163         I915_WRITE(reg, temp);
4164
4165         POSTING_READ(reg);
4166         udelay(150);
4167
4168         reg = FDI_RX_IIR(pipe);
4169         for (tries = 0; tries < 5; tries++) {
4170                 temp = I915_READ(reg);
4171                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4172
4173                 if (temp & FDI_RX_SYMBOL_LOCK) {
4174                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4175                         DRM_DEBUG_KMS("FDI train 2 done.\n");
4176                         break;
4177                 }
4178         }
4179         if (tries == 5)
4180                 DRM_ERROR("FDI train 2 fail!\n");
4181
4182         DRM_DEBUG_KMS("FDI train done\n");
4183
4184 }
4185
4186 static const int snb_b_fdi_train_param[] = {
4187         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4188         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4189         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4190         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4191 };
4192
4193 /* The FDI link training functions for SNB/Cougarpoint. */
4194 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4195                                 const struct intel_crtc_state *crtc_state)
4196 {
4197         struct drm_device *dev = crtc->base.dev;
4198         struct drm_i915_private *dev_priv = to_i915(dev);
4199         int pipe = crtc->pipe;
4200         i915_reg_t reg;
4201         u32 temp, i, retry;
4202
4203         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4204            for train result */
4205         reg = FDI_RX_IMR(pipe);
4206         temp = I915_READ(reg);
4207         temp &= ~FDI_RX_SYMBOL_LOCK;
4208         temp &= ~FDI_RX_BIT_LOCK;
4209         I915_WRITE(reg, temp);
4210
4211         POSTING_READ(reg);
4212         udelay(150);
4213
4214         /* enable CPU FDI TX and PCH FDI RX */
4215         reg = FDI_TX_CTL(pipe);
4216         temp = I915_READ(reg);
4217         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4218         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4219         temp &= ~FDI_LINK_TRAIN_NONE;
4220         temp |= FDI_LINK_TRAIN_PATTERN_1;
4221         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4222         /* SNB-B */
4223         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4224         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4225
4226         I915_WRITE(FDI_RX_MISC(pipe),
4227                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4228
4229         reg = FDI_RX_CTL(pipe);
4230         temp = I915_READ(reg);
4231         if (HAS_PCH_CPT(dev_priv)) {
4232                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4233                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4234         } else {
4235                 temp &= ~FDI_LINK_TRAIN_NONE;
4236                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4237         }
4238         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4239
4240         POSTING_READ(reg);
4241         udelay(150);
4242
4243         for (i = 0; i < 4; i++) {
4244                 reg = FDI_TX_CTL(pipe);
4245                 temp = I915_READ(reg);
4246                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4247                 temp |= snb_b_fdi_train_param[i];
4248                 I915_WRITE(reg, temp);
4249
4250                 POSTING_READ(reg);
4251                 udelay(500);
4252
4253                 for (retry = 0; retry < 5; retry++) {
4254                         reg = FDI_RX_IIR(pipe);
4255                         temp = I915_READ(reg);
4256                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4257                         if (temp & FDI_RX_BIT_LOCK) {
4258                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4259                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
4260                                 break;
4261                         }
4262                         udelay(50);
4263                 }
4264                 if (retry < 5)
4265                         break;
4266         }
4267         if (i == 4)
4268                 DRM_ERROR("FDI train 1 fail!\n");
4269
4270         /* Train 2 */
4271         reg = FDI_TX_CTL(pipe);
4272         temp = I915_READ(reg);
4273         temp &= ~FDI_LINK_TRAIN_NONE;
4274         temp |= FDI_LINK_TRAIN_PATTERN_2;
4275         if (IS_GEN(dev_priv, 6)) {
4276                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4277                 /* SNB-B */
4278                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4279         }
4280         I915_WRITE(reg, temp);
4281
4282         reg = FDI_RX_CTL(pipe);
4283         temp = I915_READ(reg);
4284         if (HAS_PCH_CPT(dev_priv)) {
4285                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4286                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4287         } else {
4288                 temp &= ~FDI_LINK_TRAIN_NONE;
4289                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4290         }
4291         I915_WRITE(reg, temp);
4292
4293         POSTING_READ(reg);
4294         udelay(150);
4295
4296         for (i = 0; i < 4; i++) {
4297                 reg = FDI_TX_CTL(pipe);
4298                 temp = I915_READ(reg);
4299                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4300                 temp |= snb_b_fdi_train_param[i];
4301                 I915_WRITE(reg, temp);
4302
4303                 POSTING_READ(reg);
4304                 udelay(500);
4305
4306                 for (retry = 0; retry < 5; retry++) {
4307                         reg = FDI_RX_IIR(pipe);
4308                         temp = I915_READ(reg);
4309                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4310                         if (temp & FDI_RX_SYMBOL_LOCK) {
4311                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4312                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4313                                 break;
4314                         }
4315                         udelay(50);
4316                 }
4317                 if (retry < 5)
4318                         break;
4319         }
4320         if (i == 4)
4321                 DRM_ERROR("FDI train 2 fail!\n");
4322
4323         DRM_DEBUG_KMS("FDI train done.\n");
4324 }
4325
4326 /* Manual link training for Ivy Bridge A0 parts */
4327 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4328                                       const struct intel_crtc_state *crtc_state)
4329 {
4330         struct drm_device *dev = crtc->base.dev;
4331         struct drm_i915_private *dev_priv = to_i915(dev);
4332         int pipe = crtc->pipe;
4333         i915_reg_t reg;
4334         u32 temp, i, j;
4335
4336         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4337            for train result */
4338         reg = FDI_RX_IMR(pipe);
4339         temp = I915_READ(reg);
4340         temp &= ~FDI_RX_SYMBOL_LOCK;
4341         temp &= ~FDI_RX_BIT_LOCK;
4342         I915_WRITE(reg, temp);
4343
4344         POSTING_READ(reg);
4345         udelay(150);
4346
4347         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4348                       I915_READ(FDI_RX_IIR(pipe)));
4349
4350         /* Try each vswing and preemphasis setting twice before moving on */
4351         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4352                 /* disable first in case we need to retry */
4353                 reg = FDI_TX_CTL(pipe);
4354                 temp = I915_READ(reg);
4355                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4356                 temp &= ~FDI_TX_ENABLE;
4357                 I915_WRITE(reg, temp);
4358
4359                 reg = FDI_RX_CTL(pipe);
4360                 temp = I915_READ(reg);
4361                 temp &= ~FDI_LINK_TRAIN_AUTO;
4362                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4363                 temp &= ~FDI_RX_ENABLE;
4364                 I915_WRITE(reg, temp);
4365
4366                 /* enable CPU FDI TX and PCH FDI RX */
4367                 reg = FDI_TX_CTL(pipe);
4368                 temp = I915_READ(reg);
4369                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4370                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4371                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4372                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4373                 temp |= snb_b_fdi_train_param[j/2];
4374                 temp |= FDI_COMPOSITE_SYNC;
4375                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4376
4377                 I915_WRITE(FDI_RX_MISC(pipe),
4378                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4379
4380                 reg = FDI_RX_CTL(pipe);
4381                 temp = I915_READ(reg);
4382                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4383                 temp |= FDI_COMPOSITE_SYNC;
4384                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4385
4386                 POSTING_READ(reg);
4387                 udelay(1); /* should be 0.5us */
4388
4389                 for (i = 0; i < 4; i++) {
4390                         reg = FDI_RX_IIR(pipe);
4391                         temp = I915_READ(reg);
4392                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4393
4394                         if (temp & FDI_RX_BIT_LOCK ||
4395                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4396                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4397                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4398                                               i);
4399                                 break;
4400                         }
4401                         udelay(1); /* should be 0.5us */
4402                 }
4403                 if (i == 4) {
4404                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4405                         continue;
4406                 }
4407
4408                 /* Train 2 */
4409                 reg = FDI_TX_CTL(pipe);
4410                 temp = I915_READ(reg);
4411                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4412                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4413                 I915_WRITE(reg, temp);
4414
4415                 reg = FDI_RX_CTL(pipe);
4416                 temp = I915_READ(reg);
4417                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4418                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4419                 I915_WRITE(reg, temp);
4420
4421                 POSTING_READ(reg);
4422                 udelay(2); /* should be 1.5us */
4423
4424                 for (i = 0; i < 4; i++) {
4425                         reg = FDI_RX_IIR(pipe);
4426                         temp = I915_READ(reg);
4427                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4428
4429                         if (temp & FDI_RX_SYMBOL_LOCK ||
4430                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4431                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4432                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4433                                               i);
4434                                 goto train_done;
4435                         }
4436                         udelay(2); /* should be 1.5us */
4437                 }
4438                 if (i == 4)
4439                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4440         }
4441
4442 train_done:
4443         DRM_DEBUG_KMS("FDI train done.\n");
4444 }
4445
4446 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4447 {
4448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4449         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4450         int pipe = intel_crtc->pipe;
4451         i915_reg_t reg;
4452         u32 temp;
4453
4454         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4455         reg = FDI_RX_CTL(pipe);
4456         temp = I915_READ(reg);
4457         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4458         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4459         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4460         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4461
4462         POSTING_READ(reg);
4463         udelay(200);
4464
4465         /* Switch from Rawclk to PCDclk */
4466         temp = I915_READ(reg);
4467         I915_WRITE(reg, temp | FDI_PCDCLK);
4468
4469         POSTING_READ(reg);
4470         udelay(200);
4471
4472         /* Enable CPU FDI TX PLL, always on for Ironlake */
4473         reg = FDI_TX_CTL(pipe);
4474         temp = I915_READ(reg);
4475         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4476                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4477
4478                 POSTING_READ(reg);
4479                 udelay(100);
4480         }
4481 }
4482
4483 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4484 {
4485         struct drm_device *dev = intel_crtc->base.dev;
4486         struct drm_i915_private *dev_priv = to_i915(dev);
4487         int pipe = intel_crtc->pipe;
4488         i915_reg_t reg;
4489         u32 temp;
4490
4491         /* Switch from PCDclk to Rawclk */
4492         reg = FDI_RX_CTL(pipe);
4493         temp = I915_READ(reg);
4494         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4495
4496         /* Disable CPU FDI TX PLL */
4497         reg = FDI_TX_CTL(pipe);
4498         temp = I915_READ(reg);
4499         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4500
4501         POSTING_READ(reg);
4502         udelay(100);
4503
4504         reg = FDI_RX_CTL(pipe);
4505         temp = I915_READ(reg);
4506         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4507
4508         /* Wait for the clocks to turn off. */
4509         POSTING_READ(reg);
4510         udelay(100);
4511 }
4512
4513 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4514 {
4515         struct drm_device *dev = crtc->dev;
4516         struct drm_i915_private *dev_priv = to_i915(dev);
4517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4518         int pipe = intel_crtc->pipe;
4519         i915_reg_t reg;
4520         u32 temp;
4521
4522         /* disable CPU FDI tx and PCH FDI rx */
4523         reg = FDI_TX_CTL(pipe);
4524         temp = I915_READ(reg);
4525         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4526         POSTING_READ(reg);
4527
4528         reg = FDI_RX_CTL(pipe);
4529         temp = I915_READ(reg);
4530         temp &= ~(0x7 << 16);
4531         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4532         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4533
4534         POSTING_READ(reg);
4535         udelay(100);
4536
4537         /* Ironlake workaround, disable clock pointer after downing FDI */
4538         if (HAS_PCH_IBX(dev_priv))
4539                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4540
4541         /* still set train pattern 1 */
4542         reg = FDI_TX_CTL(pipe);
4543         temp = I915_READ(reg);
4544         temp &= ~FDI_LINK_TRAIN_NONE;
4545         temp |= FDI_LINK_TRAIN_PATTERN_1;
4546         I915_WRITE(reg, temp);
4547
4548         reg = FDI_RX_CTL(pipe);
4549         temp = I915_READ(reg);
4550         if (HAS_PCH_CPT(dev_priv)) {
4551                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4552                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4553         } else {
4554                 temp &= ~FDI_LINK_TRAIN_NONE;
4555                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4556         }
4557         /* BPC in FDI rx is consistent with that in PIPECONF */
4558         temp &= ~(0x07 << 16);
4559         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4560         I915_WRITE(reg, temp);
4561
4562         POSTING_READ(reg);
4563         udelay(100);
4564 }
4565
4566 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4567 {
4568         struct drm_crtc *crtc;
4569         bool cleanup_done;
4570
4571         drm_for_each_crtc(crtc, &dev_priv->drm) {
4572                 struct drm_crtc_commit *commit;
4573                 spin_lock(&crtc->commit_lock);
4574                 commit = list_first_entry_or_null(&crtc->commit_list,
4575                                                   struct drm_crtc_commit, commit_entry);
4576                 cleanup_done = commit ?
4577                         try_wait_for_completion(&commit->cleanup_done) : true;
4578                 spin_unlock(&crtc->commit_lock);
4579
4580                 if (cleanup_done)
4581                         continue;
4582
4583                 drm_crtc_wait_one_vblank(crtc);
4584
4585                 return true;
4586         }
4587
4588         return false;
4589 }
4590
4591 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4592 {
4593         u32 temp;
4594
4595         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4596
4597         mutex_lock(&dev_priv->sb_lock);
4598
4599         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4600         temp |= SBI_SSCCTL_DISABLE;
4601         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4602
4603         mutex_unlock(&dev_priv->sb_lock);
4604 }
4605
4606 /* Program iCLKIP clock to the desired frequency */
4607 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
4608 {
4609         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4610         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4611         int clock = crtc_state->base.adjusted_mode.crtc_clock;
4612         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4613         u32 temp;
4614
4615         lpt_disable_iclkip(dev_priv);
4616
4617         /* The iCLK virtual clock root frequency is in MHz,
4618          * but the adjusted_mode->crtc_clock in in KHz. To get the
4619          * divisors, it is necessary to divide one by another, so we
4620          * convert the virtual clock precision to KHz here for higher
4621          * precision.
4622          */
4623         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4624                 u32 iclk_virtual_root_freq = 172800 * 1000;
4625                 u32 iclk_pi_range = 64;
4626                 u32 desired_divisor;
4627
4628                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4629                                                     clock << auxdiv);
4630                 divsel = (desired_divisor / iclk_pi_range) - 2;
4631                 phaseinc = desired_divisor % iclk_pi_range;
4632
4633                 /*
4634                  * Near 20MHz is a corner case which is
4635                  * out of range for the 7-bit divisor
4636                  */
4637                 if (divsel <= 0x7f)
4638                         break;
4639         }
4640
4641         /* This should not happen with any sane values */
4642         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4643                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4644         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4645                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4646
4647         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4648                         clock,
4649                         auxdiv,
4650                         divsel,
4651                         phasedir,
4652                         phaseinc);
4653
4654         mutex_lock(&dev_priv->sb_lock);
4655
4656         /* Program SSCDIVINTPHASE6 */
4657         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4658         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4659         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4660         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4661         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4662         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4663         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4664         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4665
4666         /* Program SSCAUXDIV */
4667         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4668         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4669         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4670         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4671
4672         /* Enable modulator and associated divider */
4673         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4674         temp &= ~SBI_SSCCTL_DISABLE;
4675         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4676
4677         mutex_unlock(&dev_priv->sb_lock);
4678
4679         /* Wait for initialization time */
4680         udelay(24);
4681
4682         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4683 }
4684
4685 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4686 {
4687         u32 divsel, phaseinc, auxdiv;
4688         u32 iclk_virtual_root_freq = 172800 * 1000;
4689         u32 iclk_pi_range = 64;
4690         u32 desired_divisor;
4691         u32 temp;
4692
4693         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4694                 return 0;
4695
4696         mutex_lock(&dev_priv->sb_lock);
4697
4698         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4699         if (temp & SBI_SSCCTL_DISABLE) {
4700                 mutex_unlock(&dev_priv->sb_lock);
4701                 return 0;
4702         }
4703
4704         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4705         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4706                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4707         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4708                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4709
4710         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4711         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4712                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4713
4714         mutex_unlock(&dev_priv->sb_lock);
4715
4716         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4717
4718         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4719                                  desired_divisor << auxdiv);
4720 }
4721
4722 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
4723                                                 enum pipe pch_transcoder)
4724 {
4725         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4726         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4727         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4728
4729         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4730                    I915_READ(HTOTAL(cpu_transcoder)));
4731         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4732                    I915_READ(HBLANK(cpu_transcoder)));
4733         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4734                    I915_READ(HSYNC(cpu_transcoder)));
4735
4736         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4737                    I915_READ(VTOTAL(cpu_transcoder)));
4738         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4739                    I915_READ(VBLANK(cpu_transcoder)));
4740         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4741                    I915_READ(VSYNC(cpu_transcoder)));
4742         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4743                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4744 }
4745
4746 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
4747 {
4748         u32 temp;
4749
4750         temp = I915_READ(SOUTH_CHICKEN1);
4751         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4752                 return;
4753
4754         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4755         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4756
4757         temp &= ~FDI_BC_BIFURCATION_SELECT;
4758         if (enable)
4759                 temp |= FDI_BC_BIFURCATION_SELECT;
4760
4761         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4762         I915_WRITE(SOUTH_CHICKEN1, temp);
4763         POSTING_READ(SOUTH_CHICKEN1);
4764 }
4765
4766 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
4767 {
4768         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4769         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4770
4771         switch (crtc->pipe) {
4772         case PIPE_A:
4773                 break;
4774         case PIPE_B:
4775                 if (crtc_state->fdi_lanes > 2)
4776                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
4777                 else
4778                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
4779
4780                 break;
4781         case PIPE_C:
4782                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
4783
4784                 break;
4785         default:
4786                 BUG();
4787         }
4788 }
4789
4790 /*
4791  * Finds the encoder associated with the given CRTC. This can only be
4792  * used when we know that the CRTC isn't feeding multiple encoders!
4793  */
4794 static struct intel_encoder *
4795 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
4796                            const struct intel_crtc_state *crtc_state)
4797 {
4798         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4799         const struct drm_connector_state *connector_state;
4800         const struct drm_connector *connector;
4801         struct intel_encoder *encoder = NULL;
4802         int num_encoders = 0;
4803         int i;
4804
4805         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4806                 if (connector_state->crtc != &crtc->base)
4807                         continue;
4808
4809                 encoder = to_intel_encoder(connector_state->best_encoder);
4810                 num_encoders++;
4811         }
4812
4813         WARN(num_encoders != 1, "%d encoders for pipe %c\n",
4814              num_encoders, pipe_name(crtc->pipe));
4815
4816         return encoder;
4817 }
4818
4819 /*
4820  * Enable PCH resources required for PCH ports:
4821  *   - PCH PLLs
4822  *   - FDI training & RX/TX
4823  *   - update transcoder timings
4824  *   - DP transcoding bits
4825  *   - transcoder
4826  */
4827 static void ironlake_pch_enable(const struct intel_atomic_state *state,
4828                                 const struct intel_crtc_state *crtc_state)
4829 {
4830         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4831         struct drm_device *dev = crtc->base.dev;
4832         struct drm_i915_private *dev_priv = to_i915(dev);
4833         int pipe = crtc->pipe;
4834         u32 temp;
4835
4836         assert_pch_transcoder_disabled(dev_priv, pipe);
4837
4838         if (IS_IVYBRIDGE(dev_priv))
4839                 ivybridge_update_fdi_bc_bifurcation(crtc_state);
4840
4841         /* Write the TU size bits before fdi link training, so that error
4842          * detection works. */
4843         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4844                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4845
4846         /* For PCH output, training FDI link */
4847         dev_priv->display.fdi_link_train(crtc, crtc_state);
4848
4849         /* We need to program the right clock selection before writing the pixel
4850          * mutliplier into the DPLL. */
4851         if (HAS_PCH_CPT(dev_priv)) {
4852                 u32 sel;
4853
4854                 temp = I915_READ(PCH_DPLL_SEL);
4855                 temp |= TRANS_DPLL_ENABLE(pipe);
4856                 sel = TRANS_DPLLB_SEL(pipe);
4857                 if (crtc_state->shared_dpll ==
4858                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4859                         temp |= sel;
4860                 else
4861                         temp &= ~sel;
4862                 I915_WRITE(PCH_DPLL_SEL, temp);
4863         }
4864
4865         /* XXX: pch pll's can be enabled any time before we enable the PCH
4866          * transcoder, and we actually should do this to not upset any PCH
4867          * transcoder that already use the clock when we share it.
4868          *
4869          * Note that enable_shared_dpll tries to do the right thing, but
4870          * get_shared_dpll unconditionally resets the pll - we need that to have
4871          * the right LVDS enable sequence. */
4872         intel_enable_shared_dpll(crtc_state);
4873
4874         /* set transcoder timing, panel must allow it */
4875         assert_panel_unlocked(dev_priv, pipe);
4876         ironlake_pch_transcoder_set_timings(crtc_state, pipe);
4877
4878         intel_fdi_normal_train(crtc);
4879
4880         /* For PCH DP, enable TRANS_DP_CTL */
4881         if (HAS_PCH_CPT(dev_priv) &&
4882             intel_crtc_has_dp_encoder(crtc_state)) {
4883                 const struct drm_display_mode *adjusted_mode =
4884                         &crtc_state->base.adjusted_mode;
4885                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4886                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4887                 enum port port;
4888
4889                 temp = I915_READ(reg);
4890                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4891                           TRANS_DP_SYNC_MASK |
4892                           TRANS_DP_BPC_MASK);
4893                 temp |= TRANS_DP_OUTPUT_ENABLE;
4894                 temp |= bpc << 9; /* same format but at 11:9 */
4895
4896                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4897                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4898                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4899                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4900
4901                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
4902                 WARN_ON(port < PORT_B || port > PORT_D);
4903                 temp |= TRANS_DP_PORT_SEL(port);
4904
4905                 I915_WRITE(reg, temp);
4906         }
4907
4908         ironlake_enable_pch_transcoder(crtc_state);
4909 }
4910
4911 static void lpt_pch_enable(const struct intel_atomic_state *state,
4912                            const struct intel_crtc_state *crtc_state)
4913 {
4914         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4915         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4916         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4917
4918         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4919
4920         lpt_program_iclkip(crtc_state);
4921
4922         /* Set transcoder timing. */
4923         ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
4924
4925         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4926 }
4927
4928 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4929 {
4930         struct drm_i915_private *dev_priv = to_i915(dev);
4931         i915_reg_t dslreg = PIPEDSL(pipe);
4932         u32 temp;
4933
4934         temp = I915_READ(dslreg);
4935         udelay(500);
4936         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4937                 if (wait_for(I915_READ(dslreg) != temp, 5))
4938                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4939         }
4940 }
4941
4942 /*
4943  * The hardware phase 0.0 refers to the center of the pixel.
4944  * We want to start from the top/left edge which is phase
4945  * -0.5. That matches how the hardware calculates the scaling
4946  * factors (from top-left of the first pixel to bottom-right
4947  * of the last pixel, as opposed to the pixel centers).
4948  *
4949  * For 4:2:0 subsampled chroma planes we obviously have to
4950  * adjust that so that the chroma sample position lands in
4951  * the right spot.
4952  *
4953  * Note that for packed YCbCr 4:2:2 formats there is no way to
4954  * control chroma siting. The hardware simply replicates the
4955  * chroma samples for both of the luma samples, and thus we don't
4956  * actually get the expected MPEG2 chroma siting convention :(
4957  * The same behaviour is observed on pre-SKL platforms as well.
4958  *
4959  * Theory behind the formula (note that we ignore sub-pixel
4960  * source coordinates):
4961  * s = source sample position
4962  * d = destination sample position
4963  *
4964  * Downscaling 4:1:
4965  * -0.5
4966  * | 0.0
4967  * | |     1.5 (initial phase)
4968  * | |     |
4969  * v v     v
4970  * | s | s | s | s |
4971  * |       d       |
4972  *
4973  * Upscaling 1:4:
4974  * -0.5
4975  * | -0.375 (initial phase)
4976  * | |     0.0
4977  * | |     |
4978  * v v     v
4979  * |       s       |
4980  * | d | d | d | d |
4981  */
4982 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
4983 {
4984         int phase = -0x8000;
4985         u16 trip = 0;
4986
4987         if (chroma_cosited)
4988                 phase += (sub - 1) * 0x8000 / sub;
4989
4990         phase += scale / (2 * sub);
4991
4992         /*
4993          * Hardware initial phase limited to [-0.5:1.5].
4994          * Since the max hardware scale factor is 3.0, we
4995          * should never actually excdeed 1.0 here.
4996          */
4997         WARN_ON(phase < -0x8000 || phase > 0x18000);
4998
4999         if (phase < 0)
5000                 phase = 0x10000 + phase;
5001         else
5002                 trip = PS_PHASE_TRIP;
5003
5004         return ((phase >> 2) & PS_PHASE_MASK) | trip;
5005 }
5006
5007 static int
5008 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5009                   unsigned int scaler_user, int *scaler_id,
5010                   int src_w, int src_h, int dst_w, int dst_h,
5011                   const struct drm_format_info *format, bool need_scaler)
5012 {
5013         struct intel_crtc_scaler_state *scaler_state =
5014                 &crtc_state->scaler_state;
5015         struct intel_crtc *intel_crtc =
5016                 to_intel_crtc(crtc_state->base.crtc);
5017         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5018         const struct drm_display_mode *adjusted_mode =
5019                 &crtc_state->base.adjusted_mode;
5020
5021         /*
5022          * Src coordinates are already rotated by 270 degrees for
5023          * the 90/270 degree plane rotation cases (to match the
5024          * GTT mapping), hence no need to account for rotation here.
5025          */
5026         if (src_w != dst_w || src_h != dst_h)
5027                 need_scaler = true;
5028
5029         /*
5030          * Scaling/fitting not supported in IF-ID mode in GEN9+
5031          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5032          * Once NV12 is enabled, handle it here while allocating scaler
5033          * for NV12.
5034          */
5035         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
5036             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5037                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5038                 return -EINVAL;
5039         }
5040
5041         /*
5042          * if plane is being disabled or scaler is no more required or force detach
5043          *  - free scaler binded to this plane/crtc
5044          *  - in order to do this, update crtc->scaler_usage
5045          *
5046          * Here scaler state in crtc_state is set free so that
5047          * scaler can be assigned to other user. Actual register
5048          * update to free the scaler is done in plane/panel-fit programming.
5049          * For this purpose crtc/plane_state->scaler_id isn't reset here.
5050          */
5051         if (force_detach || !need_scaler) {
5052                 if (*scaler_id >= 0) {
5053                         scaler_state->scaler_users &= ~(1 << scaler_user);
5054                         scaler_state->scalers[*scaler_id].in_use = 0;
5055
5056                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5057                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5058                                 intel_crtc->pipe, scaler_user, *scaler_id,
5059                                 scaler_state->scaler_users);
5060                         *scaler_id = -1;
5061                 }
5062                 return 0;
5063         }
5064
5065         if (format && is_planar_yuv_format(format->format) &&
5066             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5067                 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5068                 return -EINVAL;
5069         }
5070
5071         /* range checks */
5072         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5073             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5074             (INTEL_GEN(dev_priv) >= 11 &&
5075              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5076               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5077             (INTEL_GEN(dev_priv) < 11 &&
5078              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5079               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5080                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5081                         "size is out of scaler range\n",
5082                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5083                 return -EINVAL;
5084         }
5085
5086         /* mark this plane as a scaler user in crtc_state */
5087         scaler_state->scaler_users |= (1 << scaler_user);
5088         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5089                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5090                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5091                 scaler_state->scaler_users);
5092
5093         return 0;
5094 }
5095
5096 /**
5097  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5098  *
5099  * @state: crtc's scaler state
5100  *
5101  * Return
5102  *     0 - scaler_usage updated successfully
5103  *    error - requested scaling cannot be supported or other error condition
5104  */
5105 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5106 {
5107         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
5108         bool need_scaler = false;
5109
5110         if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5111                 need_scaler = true;
5112
5113         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
5114                                  &state->scaler_state.scaler_id,
5115                                  state->pipe_src_w, state->pipe_src_h,
5116                                  adjusted_mode->crtc_hdisplay,
5117                                  adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5118 }
5119
5120 /**
5121  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5122  * @crtc_state: crtc's scaler state
5123  * @plane_state: atomic plane state to update
5124  *
5125  * Return
5126  *     0 - scaler_usage updated successfully
5127  *    error - requested scaling cannot be supported or other error condition
5128  */
5129 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5130                                    struct intel_plane_state *plane_state)
5131 {
5132         struct intel_plane *intel_plane =
5133                 to_intel_plane(plane_state->base.plane);
5134         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5135         struct drm_framebuffer *fb = plane_state->base.fb;
5136         int ret;
5137         bool force_detach = !fb || !plane_state->base.visible;
5138         bool need_scaler = false;
5139
5140         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5141         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5142             fb && is_planar_yuv_format(fb->format->format))
5143                 need_scaler = true;
5144
5145         ret = skl_update_scaler(crtc_state, force_detach,
5146                                 drm_plane_index(&intel_plane->base),
5147                                 &plane_state->scaler_id,
5148                                 drm_rect_width(&plane_state->base.src) >> 16,
5149                                 drm_rect_height(&plane_state->base.src) >> 16,
5150                                 drm_rect_width(&plane_state->base.dst),
5151                                 drm_rect_height(&plane_state->base.dst),
5152                                 fb ? fb->format : NULL, need_scaler);
5153
5154         if (ret || plane_state->scaler_id < 0)
5155                 return ret;
5156
5157         /* check colorkey */
5158         if (plane_state->ckey.flags) {
5159                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5160                               intel_plane->base.base.id,
5161                               intel_plane->base.name);
5162                 return -EINVAL;
5163         }
5164
5165         /* Check src format */
5166         switch (fb->format->format) {
5167         case DRM_FORMAT_RGB565:
5168         case DRM_FORMAT_XBGR8888:
5169         case DRM_FORMAT_XRGB8888:
5170         case DRM_FORMAT_ABGR8888:
5171         case DRM_FORMAT_ARGB8888:
5172         case DRM_FORMAT_XRGB2101010:
5173         case DRM_FORMAT_XBGR2101010:
5174         case DRM_FORMAT_XBGR16161616F:
5175         case DRM_FORMAT_ABGR16161616F:
5176         case DRM_FORMAT_XRGB16161616F:
5177         case DRM_FORMAT_ARGB16161616F:
5178         case DRM_FORMAT_YUYV:
5179         case DRM_FORMAT_YVYU:
5180         case DRM_FORMAT_UYVY:
5181         case DRM_FORMAT_VYUY:
5182         case DRM_FORMAT_NV12:
5183         case DRM_FORMAT_P010:
5184         case DRM_FORMAT_P012:
5185         case DRM_FORMAT_P016:
5186         case DRM_FORMAT_Y210:
5187         case DRM_FORMAT_Y212:
5188         case DRM_FORMAT_Y216:
5189         case DRM_FORMAT_XVYU2101010:
5190         case DRM_FORMAT_XVYU12_16161616:
5191         case DRM_FORMAT_XVYU16161616:
5192                 break;
5193         default:
5194                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5195                               intel_plane->base.base.id, intel_plane->base.name,
5196                               fb->base.id, fb->format->format);
5197                 return -EINVAL;
5198         }
5199
5200         return 0;
5201 }
5202
5203 static void skylake_scaler_disable(struct intel_crtc *crtc)
5204 {
5205         int i;
5206
5207         for (i = 0; i < crtc->num_scalers; i++)
5208                 skl_detach_scaler(crtc, i);
5209 }
5210
5211 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5212 {
5213         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5214         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5215         enum pipe pipe = crtc->pipe;
5216         const struct intel_crtc_scaler_state *scaler_state =
5217                 &crtc_state->scaler_state;
5218
5219         if (crtc_state->pch_pfit.enabled) {
5220                 u16 uv_rgb_hphase, uv_rgb_vphase;
5221                 int pfit_w, pfit_h, hscale, vscale;
5222                 int id;
5223
5224                 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5225                         return;
5226
5227                 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5228                 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5229
5230                 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5231                 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5232
5233                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5234                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5235
5236                 id = scaler_state->scaler_id;
5237                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5238                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5239                 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5240                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5241                 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5242                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5243                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5244                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5245         }
5246 }
5247
5248 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5249 {
5250         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5251         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5252         int pipe = crtc->pipe;
5253
5254         if (crtc_state->pch_pfit.enabled) {
5255                 /* Force use of hard-coded filter coefficients
5256                  * as some pre-programmed values are broken,
5257                  * e.g. x201.
5258                  */
5259                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5260                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5261                                                  PF_PIPE_SEL_IVB(pipe));
5262                 else
5263                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5264                 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5265                 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5266         }
5267 }
5268
5269 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5270 {
5271         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5272         struct drm_device *dev = crtc->base.dev;
5273         struct drm_i915_private *dev_priv = to_i915(dev);
5274
5275         if (!crtc_state->ips_enabled)
5276                 return;
5277
5278         /*
5279          * We can only enable IPS after we enable a plane and wait for a vblank
5280          * This function is called from post_plane_update, which is run after
5281          * a vblank wait.
5282          */
5283         WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5284
5285         if (IS_BROADWELL(dev_priv)) {
5286                 mutex_lock(&dev_priv->pcu_lock);
5287                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5288                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
5289                 mutex_unlock(&dev_priv->pcu_lock);
5290                 /* Quoting Art Runyan: "its not safe to expect any particular
5291                  * value in IPS_CTL bit 31 after enabling IPS through the
5292                  * mailbox." Moreover, the mailbox may return a bogus state,
5293                  * so we need to just enable it and continue on.
5294                  */
5295         } else {
5296                 I915_WRITE(IPS_CTL, IPS_ENABLE);
5297                 /* The bit only becomes 1 in the next vblank, so this wait here
5298                  * is essentially intel_wait_for_vblank. If we don't have this
5299                  * and don't wait for vblanks until the end of crtc_enable, then
5300                  * the HW state readout code will complain that the expected
5301                  * IPS_CTL value is not the one we read. */
5302                 if (intel_wait_for_register(&dev_priv->uncore,
5303                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
5304                                             50))
5305                         DRM_ERROR("Timed out waiting for IPS enable\n");
5306         }
5307 }
5308
5309 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5310 {
5311         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5312         struct drm_device *dev = crtc->base.dev;
5313         struct drm_i915_private *dev_priv = to_i915(dev);
5314
5315         if (!crtc_state->ips_enabled)
5316                 return;
5317
5318         if (IS_BROADWELL(dev_priv)) {
5319                 mutex_lock(&dev_priv->pcu_lock);
5320                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5321                 mutex_unlock(&dev_priv->pcu_lock);
5322                 /*
5323                  * Wait for PCODE to finish disabling IPS. The BSpec specified
5324                  * 42ms timeout value leads to occasional timeouts so use 100ms
5325                  * instead.
5326                  */
5327                 if (intel_wait_for_register(&dev_priv->uncore,
5328                                             IPS_CTL, IPS_ENABLE, 0,
5329                                             100))
5330                         DRM_ERROR("Timed out waiting for IPS disable\n");
5331         } else {
5332                 I915_WRITE(IPS_CTL, 0);
5333                 POSTING_READ(IPS_CTL);
5334         }
5335
5336         /* We need to wait for a vblank before we can disable the plane. */
5337         intel_wait_for_vblank(dev_priv, crtc->pipe);
5338 }
5339
5340 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5341 {
5342         if (intel_crtc->overlay) {
5343                 struct drm_device *dev = intel_crtc->base.dev;
5344
5345                 mutex_lock(&dev->struct_mutex);
5346                 (void) intel_overlay_switch_off(intel_crtc->overlay);
5347                 mutex_unlock(&dev->struct_mutex);
5348         }
5349
5350         /* Let userspace switch the overlay on again. In most cases userspace
5351          * has to recompute where to put it anyway.
5352          */
5353 }
5354
5355 /**
5356  * intel_post_enable_primary - Perform operations after enabling primary plane
5357  * @crtc: the CRTC whose primary plane was just enabled
5358  * @new_crtc_state: the enabling state
5359  *
5360  * Performs potentially sleeping operations that must be done after the primary
5361  * plane is enabled, such as updating FBC and IPS.  Note that this may be
5362  * called due to an explicit primary plane update, or due to an implicit
5363  * re-enable that is caused when a sprite plane is updated to no longer
5364  * completely hide the primary plane.
5365  */
5366 static void
5367 intel_post_enable_primary(struct drm_crtc *crtc,
5368                           const struct intel_crtc_state *new_crtc_state)
5369 {
5370         struct drm_device *dev = crtc->dev;
5371         struct drm_i915_private *dev_priv = to_i915(dev);
5372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5373         int pipe = intel_crtc->pipe;
5374
5375         /*
5376          * Gen2 reports pipe underruns whenever all planes are disabled.
5377          * So don't enable underrun reporting before at least some planes
5378          * are enabled.
5379          * FIXME: Need to fix the logic to work when we turn off all planes
5380          * but leave the pipe running.
5381          */
5382         if (IS_GEN(dev_priv, 2))
5383                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5384
5385         /* Underruns don't always raise interrupts, so check manually. */
5386         intel_check_cpu_fifo_underruns(dev_priv);
5387         intel_check_pch_fifo_underruns(dev_priv);
5388 }
5389
5390 /* FIXME get rid of this and use pre_plane_update */
5391 static void
5392 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5393 {
5394         struct drm_device *dev = crtc->dev;
5395         struct drm_i915_private *dev_priv = to_i915(dev);
5396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5397         int pipe = intel_crtc->pipe;
5398
5399         /*
5400          * Gen2 reports pipe underruns whenever all planes are disabled.
5401          * So disable underrun reporting before all the planes get disabled.
5402          */
5403         if (IS_GEN(dev_priv, 2))
5404                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5405
5406         hsw_disable_ips(to_intel_crtc_state(crtc->state));
5407
5408         /*
5409          * Vblank time updates from the shadow to live plane control register
5410          * are blocked if the memory self-refresh mode is active at that
5411          * moment. So to make sure the plane gets truly disabled, disable
5412          * first the self-refresh mode. The self-refresh enable bit in turn
5413          * will be checked/applied by the HW only at the next frame start
5414          * event which is after the vblank start event, so we need to have a
5415          * wait-for-vblank between disabling the plane and the pipe.
5416          */
5417         if (HAS_GMCH(dev_priv) &&
5418             intel_set_memory_cxsr(dev_priv, false))
5419                 intel_wait_for_vblank(dev_priv, pipe);
5420 }
5421
5422 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5423                                        const struct intel_crtc_state *new_crtc_state)
5424 {
5425         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5426         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5427
5428         if (!old_crtc_state->ips_enabled)
5429                 return false;
5430
5431         if (needs_modeset(&new_crtc_state->base))
5432                 return true;
5433
5434         /*
5435          * Workaround : Do not read or write the pipe palette/gamma data while
5436          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5437          *
5438          * Disable IPS before we program the LUT.
5439          */
5440         if (IS_HASWELL(dev_priv) &&
5441             (new_crtc_state->base.color_mgmt_changed ||
5442              new_crtc_state->update_pipe) &&
5443             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5444                 return true;
5445
5446         return !new_crtc_state->ips_enabled;
5447 }
5448
5449 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5450                                        const struct intel_crtc_state *new_crtc_state)
5451 {
5452         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5453         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5454
5455         if (!new_crtc_state->ips_enabled)
5456                 return false;
5457
5458         if (needs_modeset(&new_crtc_state->base))
5459                 return true;
5460
5461         /*
5462          * Workaround : Do not read or write the pipe palette/gamma data while
5463          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5464          *
5465          * Re-enable IPS after the LUT has been programmed.
5466          */
5467         if (IS_HASWELL(dev_priv) &&
5468             (new_crtc_state->base.color_mgmt_changed ||
5469              new_crtc_state->update_pipe) &&
5470             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5471                 return true;
5472
5473         /*
5474          * We can't read out IPS on broadwell, assume the worst and
5475          * forcibly enable IPS on the first fastset.
5476          */
5477         if (new_crtc_state->update_pipe &&
5478             old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5479                 return true;
5480
5481         return !old_crtc_state->ips_enabled;
5482 }
5483
5484 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5485                           const struct intel_crtc_state *crtc_state)
5486 {
5487         if (!crtc_state->nv12_planes)
5488                 return false;
5489
5490         /* WA Display #0827: Gen9:all */
5491         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
5492                 return true;
5493
5494         return false;
5495 }
5496
5497 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5498 {
5499         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5500         struct drm_device *dev = crtc->base.dev;
5501         struct drm_i915_private *dev_priv = to_i915(dev);
5502         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5503         struct intel_crtc_state *pipe_config =
5504                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5505                                                 crtc);
5506         struct drm_plane *primary = crtc->base.primary;
5507         struct drm_plane_state *old_primary_state =
5508                 drm_atomic_get_old_plane_state(old_state, primary);
5509
5510         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5511
5512         if (pipe_config->update_wm_post && pipe_config->base.active)
5513                 intel_update_watermarks(crtc);
5514
5515         if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5516                 hsw_enable_ips(pipe_config);
5517
5518         if (old_primary_state) {
5519                 struct drm_plane_state *new_primary_state =
5520                         drm_atomic_get_new_plane_state(old_state, primary);
5521
5522                 intel_fbc_post_update(crtc);
5523
5524                 if (new_primary_state->visible &&
5525                     (needs_modeset(&pipe_config->base) ||
5526                      !old_primary_state->visible))
5527                         intel_post_enable_primary(&crtc->base, pipe_config);
5528         }
5529
5530         /* Display WA 827 */
5531         if (needs_nv12_wa(dev_priv, old_crtc_state) &&
5532             !needs_nv12_wa(dev_priv, pipe_config)) {
5533                 skl_wa_clkgate(dev_priv, crtc->pipe, false);
5534         }
5535 }
5536
5537 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5538                                    struct intel_crtc_state *pipe_config)
5539 {
5540         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5541         struct drm_device *dev = crtc->base.dev;
5542         struct drm_i915_private *dev_priv = to_i915(dev);
5543         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5544         struct drm_plane *primary = crtc->base.primary;
5545         struct drm_plane_state *old_primary_state =
5546                 drm_atomic_get_old_plane_state(old_state, primary);
5547         bool modeset = needs_modeset(&pipe_config->base);
5548         struct intel_atomic_state *old_intel_state =
5549                 to_intel_atomic_state(old_state);
5550
5551         if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5552                 hsw_disable_ips(old_crtc_state);
5553
5554         if (old_primary_state) {
5555                 struct intel_plane_state *new_primary_state =
5556                         intel_atomic_get_new_plane_state(old_intel_state,
5557                                                          to_intel_plane(primary));
5558
5559                 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
5560                 /*
5561                  * Gen2 reports pipe underruns whenever all planes are disabled.
5562                  * So disable underrun reporting before all the planes get disabled.
5563                  */
5564                 if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
5565                     (modeset || !new_primary_state->base.visible))
5566                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5567         }
5568
5569         /* Display WA 827 */
5570         if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
5571             needs_nv12_wa(dev_priv, pipe_config)) {
5572                 skl_wa_clkgate(dev_priv, crtc->pipe, true);
5573         }
5574
5575         /*
5576          * Vblank time updates from the shadow to live plane control register
5577          * are blocked if the memory self-refresh mode is active at that
5578          * moment. So to make sure the plane gets truly disabled, disable
5579          * first the self-refresh mode. The self-refresh enable bit in turn
5580          * will be checked/applied by the HW only at the next frame start
5581          * event which is after the vblank start event, so we need to have a
5582          * wait-for-vblank between disabling the plane and the pipe.
5583          */
5584         if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
5585             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5586                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5587
5588         /*
5589          * IVB workaround: must disable low power watermarks for at least
5590          * one frame before enabling scaling.  LP watermarks can be re-enabled
5591          * when scaling is disabled.
5592          *
5593          * WaCxSRDisabledForSpriteScaling:ivb
5594          */
5595         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
5596             old_crtc_state->base.active)
5597                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5598
5599         /*
5600          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5601          * watermark programming here.
5602          */
5603         if (needs_modeset(&pipe_config->base))
5604                 return;
5605
5606         /*
5607          * For platforms that support atomic watermarks, program the
5608          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5609          * will be the intermediate values that are safe for both pre- and
5610          * post- vblank; when vblank happens, the 'active' values will be set
5611          * to the final 'target' values and we'll do this again to get the
5612          * optimal watermarks.  For gen9+ platforms, the values we program here
5613          * will be the final target values which will get automatically latched
5614          * at vblank time; no further programming will be necessary.
5615          *
5616          * If a platform hasn't been transitioned to atomic watermarks yet,
5617          * we'll continue to update watermarks the old way, if flags tell
5618          * us to.
5619          */
5620         if (dev_priv->display.initial_watermarks != NULL)
5621                 dev_priv->display.initial_watermarks(old_intel_state,
5622                                                      pipe_config);
5623         else if (pipe_config->update_wm_pre)
5624                 intel_update_watermarks(crtc);
5625 }
5626
5627 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
5628                                       struct intel_crtc *crtc)
5629 {
5630         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5631         const struct intel_crtc_state *new_crtc_state =
5632                 intel_atomic_get_new_crtc_state(state, crtc);
5633         unsigned int update_mask = new_crtc_state->update_planes;
5634         const struct intel_plane_state *old_plane_state;
5635         struct intel_plane *plane;
5636         unsigned fb_bits = 0;
5637         int i;
5638
5639         intel_crtc_dpms_overlay_disable(crtc);
5640
5641         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
5642                 if (crtc->pipe != plane->pipe ||
5643                     !(update_mask & BIT(plane->id)))
5644                         continue;
5645
5646                 intel_disable_plane(plane, new_crtc_state);
5647
5648                 if (old_plane_state->base.visible)
5649                         fb_bits |= plane->frontbuffer_bit;
5650         }
5651
5652         intel_frontbuffer_flip(dev_priv, fb_bits);
5653 }
5654
5655 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5656                                           struct intel_crtc_state *crtc_state,
5657                                           struct drm_atomic_state *old_state)
5658 {
5659         struct drm_connector_state *conn_state;
5660         struct drm_connector *conn;
5661         int i;
5662
5663         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5664                 struct intel_encoder *encoder =
5665                         to_intel_encoder(conn_state->best_encoder);
5666
5667                 if (conn_state->crtc != crtc)
5668                         continue;
5669
5670                 if (encoder->pre_pll_enable)
5671                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5672         }
5673 }
5674
5675 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5676                                       struct intel_crtc_state *crtc_state,
5677                                       struct drm_atomic_state *old_state)
5678 {
5679         struct drm_connector_state *conn_state;
5680         struct drm_connector *conn;
5681         int i;
5682
5683         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5684                 struct intel_encoder *encoder =
5685                         to_intel_encoder(conn_state->best_encoder);
5686
5687                 if (conn_state->crtc != crtc)
5688                         continue;
5689
5690                 if (encoder->pre_enable)
5691                         encoder->pre_enable(encoder, crtc_state, conn_state);
5692         }
5693 }
5694
5695 static void intel_encoders_enable(struct drm_crtc *crtc,
5696                                   struct intel_crtc_state *crtc_state,
5697                                   struct drm_atomic_state *old_state)
5698 {
5699         struct drm_connector_state *conn_state;
5700         struct drm_connector *conn;
5701         int i;
5702
5703         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5704                 struct intel_encoder *encoder =
5705                         to_intel_encoder(conn_state->best_encoder);
5706
5707                 if (conn_state->crtc != crtc)
5708                         continue;
5709
5710                 if (encoder->enable)
5711                         encoder->enable(encoder, crtc_state, conn_state);
5712                 intel_opregion_notify_encoder(encoder, true);
5713         }
5714 }
5715
5716 static void intel_encoders_disable(struct drm_crtc *crtc,
5717                                    struct intel_crtc_state *old_crtc_state,
5718                                    struct drm_atomic_state *old_state)
5719 {
5720         struct drm_connector_state *old_conn_state;
5721         struct drm_connector *conn;
5722         int i;
5723
5724         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5725                 struct intel_encoder *encoder =
5726                         to_intel_encoder(old_conn_state->best_encoder);
5727
5728                 if (old_conn_state->crtc != crtc)
5729                         continue;
5730
5731                 intel_opregion_notify_encoder(encoder, false);
5732                 if (encoder->disable)
5733                         encoder->disable(encoder, old_crtc_state, old_conn_state);
5734         }
5735 }
5736
5737 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5738                                         struct intel_crtc_state *old_crtc_state,
5739                                         struct drm_atomic_state *old_state)
5740 {
5741         struct drm_connector_state *old_conn_state;
5742         struct drm_connector *conn;
5743         int i;
5744
5745         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5746                 struct intel_encoder *encoder =
5747                         to_intel_encoder(old_conn_state->best_encoder);
5748
5749                 if (old_conn_state->crtc != crtc)
5750                         continue;
5751
5752                 if (encoder->post_disable)
5753                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5754         }
5755 }
5756
5757 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5758                                             struct intel_crtc_state *old_crtc_state,
5759                                             struct drm_atomic_state *old_state)
5760 {
5761         struct drm_connector_state *old_conn_state;
5762         struct drm_connector *conn;
5763         int i;
5764
5765         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5766                 struct intel_encoder *encoder =
5767                         to_intel_encoder(old_conn_state->best_encoder);
5768
5769                 if (old_conn_state->crtc != crtc)
5770                         continue;
5771
5772                 if (encoder->post_pll_disable)
5773                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5774         }
5775 }
5776
5777 static void intel_encoders_update_pipe(struct drm_crtc *crtc,
5778                                        struct intel_crtc_state *crtc_state,
5779                                        struct drm_atomic_state *old_state)
5780 {
5781         struct drm_connector_state *conn_state;
5782         struct drm_connector *conn;
5783         int i;
5784
5785         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5786                 struct intel_encoder *encoder =
5787                         to_intel_encoder(conn_state->best_encoder);
5788
5789                 if (conn_state->crtc != crtc)
5790                         continue;
5791
5792                 if (encoder->update_pipe)
5793                         encoder->update_pipe(encoder, crtc_state, conn_state);
5794         }
5795 }
5796
5797 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
5798 {
5799         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5800         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
5801
5802         plane->disable_plane(plane, crtc_state);
5803 }
5804
5805 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5806                                  struct drm_atomic_state *old_state)
5807 {
5808         struct drm_crtc *crtc = pipe_config->base.crtc;
5809         struct drm_device *dev = crtc->dev;
5810         struct drm_i915_private *dev_priv = to_i915(dev);
5811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5812         int pipe = intel_crtc->pipe;
5813         struct intel_atomic_state *old_intel_state =
5814                 to_intel_atomic_state(old_state);
5815
5816         if (WARN_ON(intel_crtc->active))
5817                 return;
5818
5819         /*
5820          * Sometimes spurious CPU pipe underruns happen during FDI
5821          * training, at least with VGA+HDMI cloning. Suppress them.
5822          *
5823          * On ILK we get an occasional spurious CPU pipe underruns
5824          * between eDP port A enable and vdd enable. Also PCH port
5825          * enable seems to result in the occasional CPU pipe underrun.
5826          *
5827          * Spurious PCH underruns also occur during PCH enabling.
5828          */
5829         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5830         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5831
5832         if (pipe_config->has_pch_encoder)
5833                 intel_prepare_shared_dpll(pipe_config);
5834
5835         if (intel_crtc_has_dp_encoder(pipe_config))
5836                 intel_dp_set_m_n(pipe_config, M1_N1);
5837
5838         intel_set_pipe_timings(pipe_config);
5839         intel_set_pipe_src_size(pipe_config);
5840
5841         if (pipe_config->has_pch_encoder) {
5842                 intel_cpu_transcoder_set_m_n(pipe_config,
5843                                              &pipe_config->fdi_m_n, NULL);
5844         }
5845
5846         ironlake_set_pipeconf(pipe_config);
5847
5848         intel_crtc->active = true;
5849
5850         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5851
5852         if (pipe_config->has_pch_encoder) {
5853                 /* Note: FDI PLL enabling _must_ be done before we enable the
5854                  * cpu pipes, hence this is separate from all the other fdi/pch
5855                  * enabling. */
5856                 ironlake_fdi_pll_enable(pipe_config);
5857         } else {
5858                 assert_fdi_tx_disabled(dev_priv, pipe);
5859                 assert_fdi_rx_disabled(dev_priv, pipe);
5860         }
5861
5862         ironlake_pfit_enable(pipe_config);
5863
5864         /*
5865          * On ILK+ LUT must be loaded before the pipe is running but with
5866          * clocks enabled
5867          */
5868         intel_color_load_luts(pipe_config);
5869         intel_color_commit(pipe_config);
5870         /* update DSPCNTR to configure gamma for pipe bottom color */
5871         intel_disable_primary_plane(pipe_config);
5872
5873         if (dev_priv->display.initial_watermarks != NULL)
5874                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5875         intel_enable_pipe(pipe_config);
5876
5877         if (pipe_config->has_pch_encoder)
5878                 ironlake_pch_enable(old_intel_state, pipe_config);
5879
5880         assert_vblank_disabled(crtc);
5881         intel_crtc_vblank_on(pipe_config);
5882
5883         intel_encoders_enable(crtc, pipe_config, old_state);
5884
5885         if (HAS_PCH_CPT(dev_priv))
5886                 cpt_verify_modeset(dev, intel_crtc->pipe);
5887
5888         /*
5889          * Must wait for vblank to avoid spurious PCH FIFO underruns.
5890          * And a second vblank wait is needed at least on ILK with
5891          * some interlaced HDMI modes. Let's do the double wait always
5892          * in case there are more corner cases we don't know about.
5893          */
5894         if (pipe_config->has_pch_encoder) {
5895                 intel_wait_for_vblank(dev_priv, pipe);
5896                 intel_wait_for_vblank(dev_priv, pipe);
5897         }
5898         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5899         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5900 }
5901
5902 /* IPS only exists on ULT machines and is tied to pipe A. */
5903 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5904 {
5905         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5906 }
5907
5908 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5909                                             enum pipe pipe, bool apply)
5910 {
5911         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5912         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5913
5914         if (apply)
5915                 val |= mask;
5916         else
5917                 val &= ~mask;
5918
5919         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5920 }
5921
5922 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5923 {
5924         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5925         enum pipe pipe = crtc->pipe;
5926         u32 val;
5927
5928         val = MBUS_DBOX_A_CREDIT(2);
5929         val |= MBUS_DBOX_BW_CREDIT(1);
5930         val |= MBUS_DBOX_B_CREDIT(8);
5931
5932         I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
5933 }
5934
5935 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5936                                 struct drm_atomic_state *old_state)
5937 {
5938         struct drm_crtc *crtc = pipe_config->base.crtc;
5939         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5940         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5941         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5942         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5943         struct intel_atomic_state *old_intel_state =
5944                 to_intel_atomic_state(old_state);
5945         bool psl_clkgate_wa;
5946
5947         if (WARN_ON(intel_crtc->active))
5948                 return;
5949
5950         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5951
5952         if (pipe_config->shared_dpll)
5953                 intel_enable_shared_dpll(pipe_config);
5954
5955         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5956
5957         if (intel_crtc_has_dp_encoder(pipe_config))
5958                 intel_dp_set_m_n(pipe_config, M1_N1);
5959
5960         if (!transcoder_is_dsi(cpu_transcoder))
5961                 intel_set_pipe_timings(pipe_config);
5962
5963         intel_set_pipe_src_size(pipe_config);
5964
5965         if (cpu_transcoder != TRANSCODER_EDP &&
5966             !transcoder_is_dsi(cpu_transcoder)) {
5967                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5968                            pipe_config->pixel_multiplier - 1);
5969         }
5970
5971         if (pipe_config->has_pch_encoder) {
5972                 intel_cpu_transcoder_set_m_n(pipe_config,
5973                                              &pipe_config->fdi_m_n, NULL);
5974         }
5975
5976         if (!transcoder_is_dsi(cpu_transcoder))
5977                 haswell_set_pipeconf(pipe_config);
5978
5979         haswell_set_pipemisc(pipe_config);
5980
5981         intel_crtc->active = true;
5982
5983         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5984         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5985                          pipe_config->pch_pfit.enabled;
5986         if (psl_clkgate_wa)
5987                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5988
5989         if (INTEL_GEN(dev_priv) >= 9)
5990                 skylake_pfit_enable(pipe_config);
5991         else
5992                 ironlake_pfit_enable(pipe_config);
5993
5994         /*
5995          * On ILK+ LUT must be loaded before the pipe is running but with
5996          * clocks enabled
5997          */
5998         intel_color_load_luts(pipe_config);
5999         intel_color_commit(pipe_config);
6000         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6001         if (INTEL_GEN(dev_priv) < 9)
6002                 intel_disable_primary_plane(pipe_config);
6003
6004         if (INTEL_GEN(dev_priv) >= 11)
6005                 icl_set_pipe_chicken(intel_crtc);
6006
6007         intel_ddi_set_pipe_settings(pipe_config);
6008         if (!transcoder_is_dsi(cpu_transcoder))
6009                 intel_ddi_enable_transcoder_func(pipe_config);
6010
6011         if (dev_priv->display.initial_watermarks != NULL)
6012                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
6013
6014         if (INTEL_GEN(dev_priv) >= 11)
6015                 icl_pipe_mbus_enable(intel_crtc);
6016
6017         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6018         if (!transcoder_is_dsi(cpu_transcoder))
6019                 intel_enable_pipe(pipe_config);
6020
6021         if (pipe_config->has_pch_encoder)
6022                 lpt_pch_enable(old_intel_state, pipe_config);
6023
6024         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
6025                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
6026
6027         assert_vblank_disabled(crtc);
6028         intel_crtc_vblank_on(pipe_config);
6029
6030         intel_encoders_enable(crtc, pipe_config, old_state);
6031
6032         if (psl_clkgate_wa) {
6033                 intel_wait_for_vblank(dev_priv, pipe);
6034                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6035         }
6036
6037         /* If we change the relative order between pipe/planes enabling, we need
6038          * to change the workaround. */
6039         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
6040         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6041                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6042                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6043         }
6044 }
6045
6046 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6047 {
6048         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6049         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6050         enum pipe pipe = crtc->pipe;
6051
6052         /* To avoid upsetting the power well on haswell only disable the pfit if
6053          * it's in use. The hw state code will make sure we get this right. */
6054         if (old_crtc_state->pch_pfit.enabled) {
6055                 I915_WRITE(PF_CTL(pipe), 0);
6056                 I915_WRITE(PF_WIN_POS(pipe), 0);
6057                 I915_WRITE(PF_WIN_SZ(pipe), 0);
6058         }
6059 }
6060
6061 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
6062                                   struct drm_atomic_state *old_state)
6063 {
6064         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6065         struct drm_device *dev = crtc->dev;
6066         struct drm_i915_private *dev_priv = to_i915(dev);
6067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6068         int pipe = intel_crtc->pipe;
6069
6070         /*
6071          * Sometimes spurious CPU pipe underruns happen when the
6072          * pipe is already disabled, but FDI RX/TX is still enabled.
6073          * Happens at least with VGA+HDMI cloning. Suppress them.
6074          */
6075         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6076         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6077
6078         intel_encoders_disable(crtc, old_crtc_state, old_state);
6079
6080         drm_crtc_vblank_off(crtc);
6081         assert_vblank_disabled(crtc);
6082
6083         intel_disable_pipe(old_crtc_state);
6084
6085         ironlake_pfit_disable(old_crtc_state);
6086
6087         if (old_crtc_state->has_pch_encoder)
6088                 ironlake_fdi_disable(crtc);
6089
6090         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6091
6092         if (old_crtc_state->has_pch_encoder) {
6093                 ironlake_disable_pch_transcoder(dev_priv, pipe);
6094
6095                 if (HAS_PCH_CPT(dev_priv)) {
6096                         i915_reg_t reg;
6097                         u32 temp;
6098
6099                         /* disable TRANS_DP_CTL */
6100                         reg = TRANS_DP_CTL(pipe);
6101                         temp = I915_READ(reg);
6102                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6103                                   TRANS_DP_PORT_SEL_MASK);
6104                         temp |= TRANS_DP_PORT_SEL_NONE;
6105                         I915_WRITE(reg, temp);
6106
6107                         /* disable DPLL_SEL */
6108                         temp = I915_READ(PCH_DPLL_SEL);
6109                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6110                         I915_WRITE(PCH_DPLL_SEL, temp);
6111                 }
6112
6113                 ironlake_fdi_pll_disable(intel_crtc);
6114         }
6115
6116         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6117         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6118 }
6119
6120 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
6121                                  struct drm_atomic_state *old_state)
6122 {
6123         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6124         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6126         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6127
6128         intel_encoders_disable(crtc, old_crtc_state, old_state);
6129
6130         drm_crtc_vblank_off(crtc);
6131         assert_vblank_disabled(crtc);
6132
6133         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6134         if (!transcoder_is_dsi(cpu_transcoder))
6135                 intel_disable_pipe(old_crtc_state);
6136
6137         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
6138                 intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
6139
6140         if (!transcoder_is_dsi(cpu_transcoder))
6141                 intel_ddi_disable_transcoder_func(old_crtc_state);
6142
6143         intel_dsc_disable(old_crtc_state);
6144
6145         if (INTEL_GEN(dev_priv) >= 9)
6146                 skylake_scaler_disable(intel_crtc);
6147         else
6148                 ironlake_pfit_disable(old_crtc_state);
6149
6150         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6151
6152         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6153 }
6154
6155 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6156 {
6157         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6158         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6159
6160         if (!crtc_state->gmch_pfit.control)
6161                 return;
6162
6163         /*
6164          * The panel fitter should only be adjusted whilst the pipe is disabled,
6165          * according to register description and PRM.
6166          */
6167         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6168         assert_pipe_disabled(dev_priv, crtc->pipe);
6169
6170         I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6171         I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6172
6173         /* Border color in case we don't scale up to the full screen. Black by
6174          * default, change to something else for debugging. */
6175         I915_WRITE(BCLRPAT(crtc->pipe), 0);
6176 }
6177
6178 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
6179 {
6180         if (port == PORT_NONE)
6181                 return false;
6182
6183         if (INTEL_GEN(dev_priv) >= 11)
6184                 return port <= PORT_B;
6185
6186         return false;
6187 }
6188
6189 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
6190 {
6191         if (INTEL_GEN(dev_priv) >= 11)
6192                 return port >= PORT_C && port <= PORT_F;
6193
6194         return false;
6195 }
6196
6197 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6198 {
6199         if (!intel_port_is_tc(dev_priv, port))
6200                 return PORT_TC_NONE;
6201
6202         return port - PORT_C;
6203 }
6204
6205 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6206 {
6207         switch (port) {
6208         case PORT_A:
6209                 return POWER_DOMAIN_PORT_DDI_A_LANES;
6210         case PORT_B:
6211                 return POWER_DOMAIN_PORT_DDI_B_LANES;
6212         case PORT_C:
6213                 return POWER_DOMAIN_PORT_DDI_C_LANES;
6214         case PORT_D:
6215                 return POWER_DOMAIN_PORT_DDI_D_LANES;
6216         case PORT_E:
6217                 return POWER_DOMAIN_PORT_DDI_E_LANES;
6218         case PORT_F:
6219                 return POWER_DOMAIN_PORT_DDI_F_LANES;
6220         default:
6221                 MISSING_CASE(port);
6222                 return POWER_DOMAIN_PORT_OTHER;
6223         }
6224 }
6225
6226 enum intel_display_power_domain
6227 intel_aux_power_domain(struct intel_digital_port *dig_port)
6228 {
6229         switch (dig_port->aux_ch) {
6230         case AUX_CH_A:
6231                 return POWER_DOMAIN_AUX_A;
6232         case AUX_CH_B:
6233                 return POWER_DOMAIN_AUX_B;
6234         case AUX_CH_C:
6235                 return POWER_DOMAIN_AUX_C;
6236         case AUX_CH_D:
6237                 return POWER_DOMAIN_AUX_D;
6238         case AUX_CH_E:
6239                 return POWER_DOMAIN_AUX_E;
6240         case AUX_CH_F:
6241                 return POWER_DOMAIN_AUX_F;
6242         default:
6243                 MISSING_CASE(dig_port->aux_ch);
6244                 return POWER_DOMAIN_AUX_A;
6245         }
6246 }
6247
6248 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
6249                                   struct intel_crtc_state *crtc_state)
6250 {
6251         struct drm_device *dev = crtc->dev;
6252         struct drm_i915_private *dev_priv = to_i915(dev);
6253         struct drm_encoder *encoder;
6254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6255         enum pipe pipe = intel_crtc->pipe;
6256         u64 mask;
6257         enum transcoder transcoder = crtc_state->cpu_transcoder;
6258
6259         if (!crtc_state->base.active)
6260                 return 0;
6261
6262         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6263         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6264         if (crtc_state->pch_pfit.enabled ||
6265             crtc_state->pch_pfit.force_thru)
6266                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6267
6268         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
6269                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6270
6271                 mask |= BIT_ULL(intel_encoder->power_domain);
6272         }
6273
6274         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6275                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6276
6277         if (crtc_state->shared_dpll)
6278                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
6279
6280         return mask;
6281 }
6282
6283 static u64
6284 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
6285                                struct intel_crtc_state *crtc_state)
6286 {
6287         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6289         enum intel_display_power_domain domain;
6290         u64 domains, new_domains, old_domains;
6291
6292         old_domains = intel_crtc->enabled_power_domains;
6293         intel_crtc->enabled_power_domains = new_domains =
6294                 get_crtc_power_domains(crtc, crtc_state);
6295
6296         domains = new_domains & ~old_domains;
6297
6298         for_each_power_domain(domain, domains)
6299                 intel_display_power_get(dev_priv, domain);
6300
6301         return old_domains & ~new_domains;
6302 }
6303
6304 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
6305                                       u64 domains)
6306 {
6307         enum intel_display_power_domain domain;
6308
6309         for_each_power_domain(domain, domains)
6310                 intel_display_power_put_unchecked(dev_priv, domain);
6311 }
6312
6313 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6314                                    struct drm_atomic_state *old_state)
6315 {
6316         struct intel_atomic_state *old_intel_state =
6317                 to_intel_atomic_state(old_state);
6318         struct drm_crtc *crtc = pipe_config->base.crtc;
6319         struct drm_device *dev = crtc->dev;
6320         struct drm_i915_private *dev_priv = to_i915(dev);
6321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6322         int pipe = intel_crtc->pipe;
6323
6324         if (WARN_ON(intel_crtc->active))
6325                 return;
6326
6327         if (intel_crtc_has_dp_encoder(pipe_config))
6328                 intel_dp_set_m_n(pipe_config, M1_N1);
6329
6330         intel_set_pipe_timings(pipe_config);
6331         intel_set_pipe_src_size(pipe_config);
6332
6333         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6334                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6335                 I915_WRITE(CHV_CANVAS(pipe), 0);
6336         }
6337
6338         i9xx_set_pipeconf(pipe_config);
6339
6340         intel_crtc->active = true;
6341
6342         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6343
6344         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6345
6346         if (IS_CHERRYVIEW(dev_priv)) {
6347                 chv_prepare_pll(intel_crtc, pipe_config);
6348                 chv_enable_pll(intel_crtc, pipe_config);
6349         } else {
6350                 vlv_prepare_pll(intel_crtc, pipe_config);
6351                 vlv_enable_pll(intel_crtc, pipe_config);
6352         }
6353
6354         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6355
6356         i9xx_pfit_enable(pipe_config);
6357
6358         intel_color_load_luts(pipe_config);
6359         intel_color_commit(pipe_config);
6360         /* update DSPCNTR to configure gamma for pipe bottom color */
6361         intel_disable_primary_plane(pipe_config);
6362
6363         dev_priv->display.initial_watermarks(old_intel_state,
6364                                              pipe_config);
6365         intel_enable_pipe(pipe_config);
6366
6367         assert_vblank_disabled(crtc);
6368         intel_crtc_vblank_on(pipe_config);
6369
6370         intel_encoders_enable(crtc, pipe_config, old_state);
6371 }
6372
6373 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
6374 {
6375         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6376         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6377
6378         I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
6379         I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
6380 }
6381
6382 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6383                              struct drm_atomic_state *old_state)
6384 {
6385         struct intel_atomic_state *old_intel_state =
6386                 to_intel_atomic_state(old_state);
6387         struct drm_crtc *crtc = pipe_config->base.crtc;
6388         struct drm_device *dev = crtc->dev;
6389         struct drm_i915_private *dev_priv = to_i915(dev);
6390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6391         enum pipe pipe = intel_crtc->pipe;
6392
6393         if (WARN_ON(intel_crtc->active))
6394                 return;
6395
6396         i9xx_set_pll_dividers(pipe_config);
6397
6398         if (intel_crtc_has_dp_encoder(pipe_config))
6399                 intel_dp_set_m_n(pipe_config, M1_N1);
6400
6401         intel_set_pipe_timings(pipe_config);
6402         intel_set_pipe_src_size(pipe_config);
6403
6404         i9xx_set_pipeconf(pipe_config);
6405
6406         intel_crtc->active = true;
6407
6408         if (!IS_GEN(dev_priv, 2))
6409                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6410
6411         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6412
6413         i9xx_enable_pll(intel_crtc, pipe_config);
6414
6415         i9xx_pfit_enable(pipe_config);
6416
6417         intel_color_load_luts(pipe_config);
6418         intel_color_commit(pipe_config);
6419         /* update DSPCNTR to configure gamma for pipe bottom color */
6420         intel_disable_primary_plane(pipe_config);
6421
6422         if (dev_priv->display.initial_watermarks != NULL)
6423                 dev_priv->display.initial_watermarks(old_intel_state,
6424                                                      pipe_config);
6425         else
6426                 intel_update_watermarks(intel_crtc);
6427         intel_enable_pipe(pipe_config);
6428
6429         assert_vblank_disabled(crtc);
6430         intel_crtc_vblank_on(pipe_config);
6431
6432         intel_encoders_enable(crtc, pipe_config, old_state);
6433 }
6434
6435 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6436 {
6437         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6438         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6439
6440         if (!old_crtc_state->gmch_pfit.control)
6441                 return;
6442
6443         assert_pipe_disabled(dev_priv, crtc->pipe);
6444
6445         DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
6446                       I915_READ(PFIT_CONTROL));
6447         I915_WRITE(PFIT_CONTROL, 0);
6448 }
6449
6450 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6451                               struct drm_atomic_state *old_state)
6452 {
6453         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6454         struct drm_device *dev = crtc->dev;
6455         struct drm_i915_private *dev_priv = to_i915(dev);
6456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6457         int pipe = intel_crtc->pipe;
6458
6459         /*
6460          * On gen2 planes are double buffered but the pipe isn't, so we must
6461          * wait for planes to fully turn off before disabling the pipe.
6462          */
6463         if (IS_GEN(dev_priv, 2))
6464                 intel_wait_for_vblank(dev_priv, pipe);
6465
6466         intel_encoders_disable(crtc, old_crtc_state, old_state);
6467
6468         drm_crtc_vblank_off(crtc);
6469         assert_vblank_disabled(crtc);
6470
6471         intel_disable_pipe(old_crtc_state);
6472
6473         i9xx_pfit_disable(old_crtc_state);
6474
6475         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6476
6477         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
6478                 if (IS_CHERRYVIEW(dev_priv))
6479                         chv_disable_pll(dev_priv, pipe);
6480                 else if (IS_VALLEYVIEW(dev_priv))
6481                         vlv_disable_pll(dev_priv, pipe);
6482                 else
6483                         i9xx_disable_pll(old_crtc_state);
6484         }
6485
6486         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6487
6488         if (!IS_GEN(dev_priv, 2))
6489                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6490
6491         if (!dev_priv->display.initial_watermarks)
6492                 intel_update_watermarks(intel_crtc);
6493
6494         /* clock the pipe down to 640x480@60 to potentially save power */
6495         if (IS_I830(dev_priv))
6496                 i830_enable_pipe(dev_priv, pipe);
6497 }
6498
6499 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6500                                         struct drm_modeset_acquire_ctx *ctx)
6501 {
6502         struct intel_encoder *encoder;
6503         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6504         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6505         enum intel_display_power_domain domain;
6506         struct intel_plane *plane;
6507         u64 domains;
6508         struct drm_atomic_state *state;
6509         struct intel_crtc_state *crtc_state;
6510         int ret;
6511
6512         if (!intel_crtc->active)
6513                 return;
6514
6515         for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
6516                 const struct intel_plane_state *plane_state =
6517                         to_intel_plane_state(plane->base.state);
6518
6519                 if (plane_state->base.visible)
6520                         intel_plane_disable_noatomic(intel_crtc, plane);
6521         }
6522
6523         state = drm_atomic_state_alloc(crtc->dev);
6524         if (!state) {
6525                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6526                               crtc->base.id, crtc->name);
6527                 return;
6528         }
6529
6530         state->acquire_ctx = ctx;
6531
6532         /* Everything's already locked, -EDEADLK can't happen. */
6533         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6534         ret = drm_atomic_add_affected_connectors(state, crtc);
6535
6536         WARN_ON(IS_ERR(crtc_state) || ret);
6537
6538         dev_priv->display.crtc_disable(crtc_state, state);
6539
6540         drm_atomic_state_put(state);
6541
6542         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6543                       crtc->base.id, crtc->name);
6544
6545         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6546         crtc->state->active = false;
6547         intel_crtc->active = false;
6548         crtc->enabled = false;
6549         crtc->state->connector_mask = 0;
6550         crtc->state->encoder_mask = 0;
6551
6552         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6553                 encoder->base.crtc = NULL;
6554
6555         intel_fbc_disable(intel_crtc);
6556         intel_update_watermarks(intel_crtc);
6557         intel_disable_shared_dpll(to_intel_crtc_state(crtc->state));
6558
6559         domains = intel_crtc->enabled_power_domains;
6560         for_each_power_domain(domain, domains)
6561                 intel_display_power_put_unchecked(dev_priv, domain);
6562         intel_crtc->enabled_power_domains = 0;
6563
6564         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6565         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6566         dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
6567 }
6568
6569 /*
6570  * turn all crtc's off, but do not adjust state
6571  * This has to be paired with a call to intel_modeset_setup_hw_state.
6572  */
6573 int intel_display_suspend(struct drm_device *dev)
6574 {
6575         struct drm_i915_private *dev_priv = to_i915(dev);
6576         struct drm_atomic_state *state;
6577         int ret;
6578
6579         state = drm_atomic_helper_suspend(dev);
6580         ret = PTR_ERR_OR_ZERO(state);
6581         if (ret)
6582                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6583         else
6584                 dev_priv->modeset_restore_state = state;
6585         return ret;
6586 }
6587
6588 void intel_encoder_destroy(struct drm_encoder *encoder)
6589 {
6590         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6591
6592         drm_encoder_cleanup(encoder);
6593         kfree(intel_encoder);
6594 }
6595
6596 /* Cross check the actual hw state with our own modeset state tracking (and it's
6597  * internal consistency). */
6598 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6599                                          struct drm_connector_state *conn_state)
6600 {
6601         struct intel_connector *connector = to_intel_connector(conn_state->connector);
6602
6603         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6604                       connector->base.base.id,
6605                       connector->base.name);
6606
6607         if (connector->get_hw_state(connector)) {
6608                 struct intel_encoder *encoder = connector->encoder;
6609
6610                 I915_STATE_WARN(!crtc_state,
6611                          "connector enabled without attached crtc\n");
6612
6613                 if (!crtc_state)
6614                         return;
6615
6616                 I915_STATE_WARN(!crtc_state->active,
6617                       "connector is active, but attached crtc isn't\n");
6618
6619                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6620                         return;
6621
6622                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6623                         "atomic encoder doesn't match attached encoder\n");
6624
6625                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6626                         "attached encoder crtc differs from connector crtc\n");
6627         } else {
6628                 I915_STATE_WARN(crtc_state && crtc_state->active,
6629                         "attached crtc is active, but connector isn't\n");
6630                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6631                         "best encoder set without crtc!\n");
6632         }
6633 }
6634
6635 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6636 {
6637         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6638                 return crtc_state->fdi_lanes;
6639
6640         return 0;
6641 }
6642
6643 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6644                                      struct intel_crtc_state *pipe_config)
6645 {
6646         struct drm_i915_private *dev_priv = to_i915(dev);
6647         struct drm_atomic_state *state = pipe_config->base.state;
6648         struct intel_crtc *other_crtc;
6649         struct intel_crtc_state *other_crtc_state;
6650
6651         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6652                       pipe_name(pipe), pipe_config->fdi_lanes);
6653         if (pipe_config->fdi_lanes > 4) {
6654                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6655                               pipe_name(pipe), pipe_config->fdi_lanes);
6656                 return -EINVAL;
6657         }
6658
6659         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6660                 if (pipe_config->fdi_lanes > 2) {
6661                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6662                                       pipe_config->fdi_lanes);
6663                         return -EINVAL;
6664                 } else {
6665                         return 0;
6666                 }
6667         }
6668
6669         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6670                 return 0;
6671
6672         /* Ivybridge 3 pipe is really complicated */
6673         switch (pipe) {
6674         case PIPE_A:
6675                 return 0;
6676         case PIPE_B:
6677                 if (pipe_config->fdi_lanes <= 2)
6678                         return 0;
6679
6680                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6681                 other_crtc_state =
6682                         intel_atomic_get_crtc_state(state, other_crtc);
6683                 if (IS_ERR(other_crtc_state))
6684                         return PTR_ERR(other_crtc_state);
6685
6686                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6687                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6688                                       pipe_name(pipe), pipe_config->fdi_lanes);
6689                         return -EINVAL;
6690                 }
6691                 return 0;
6692         case PIPE_C:
6693                 if (pipe_config->fdi_lanes > 2) {
6694                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6695                                       pipe_name(pipe), pipe_config->fdi_lanes);
6696                         return -EINVAL;
6697                 }
6698
6699                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6700                 other_crtc_state =
6701                         intel_atomic_get_crtc_state(state, other_crtc);
6702                 if (IS_ERR(other_crtc_state))
6703                         return PTR_ERR(other_crtc_state);
6704
6705                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6706                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6707                         return -EINVAL;
6708                 }
6709                 return 0;
6710         default:
6711                 BUG();
6712         }
6713 }
6714
6715 #define RETRY 1
6716 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6717                                        struct intel_crtc_state *pipe_config)
6718 {
6719         struct drm_device *dev = intel_crtc->base.dev;
6720         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6721         int lane, link_bw, fdi_dotclock, ret;
6722         bool needs_recompute = false;
6723
6724 retry:
6725         /* FDI is a binary signal running at ~2.7GHz, encoding
6726          * each output octet as 10 bits. The actual frequency
6727          * is stored as a divider into a 100MHz clock, and the
6728          * mode pixel clock is stored in units of 1KHz.
6729          * Hence the bw of each lane in terms of the mode signal
6730          * is:
6731          */
6732         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6733
6734         fdi_dotclock = adjusted_mode->crtc_clock;
6735
6736         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6737                                            pipe_config->pipe_bpp);
6738
6739         pipe_config->fdi_lanes = lane;
6740
6741         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6742                                link_bw, &pipe_config->fdi_m_n, false);
6743
6744         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6745         if (ret == -EDEADLK)
6746                 return ret;
6747
6748         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6749                 pipe_config->pipe_bpp -= 2*3;
6750                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6751                               pipe_config->pipe_bpp);
6752                 needs_recompute = true;
6753                 pipe_config->bw_constrained = true;
6754
6755                 goto retry;
6756         }
6757
6758         if (needs_recompute)
6759                 return RETRY;
6760
6761         return ret;
6762 }
6763
6764 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6765 {
6766         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6767         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6768
6769         /* IPS only exists on ULT machines and is tied to pipe A. */
6770         if (!hsw_crtc_supports_ips(crtc))
6771                 return false;
6772
6773         if (!i915_modparams.enable_ips)
6774                 return false;
6775
6776         if (crtc_state->pipe_bpp > 24)
6777                 return false;
6778
6779         /*
6780          * We compare against max which means we must take
6781          * the increased cdclk requirement into account when
6782          * calculating the new cdclk.
6783          *
6784          * Should measure whether using a lower cdclk w/o IPS
6785          */
6786         if (IS_BROADWELL(dev_priv) &&
6787             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6788                 return false;
6789
6790         return true;
6791 }
6792
6793 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6794 {
6795         struct drm_i915_private *dev_priv =
6796                 to_i915(crtc_state->base.crtc->dev);
6797         struct intel_atomic_state *intel_state =
6798                 to_intel_atomic_state(crtc_state->base.state);
6799
6800         if (!hsw_crtc_state_ips_capable(crtc_state))
6801                 return false;
6802
6803         /*
6804          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
6805          * enabled and disabled dynamically based on package C states,
6806          * user space can't make reliable use of the CRCs, so let's just
6807          * completely disable it.
6808          */
6809         if (crtc_state->crc_enabled)
6810                 return false;
6811
6812         /* IPS should be fine as long as at least one plane is enabled. */
6813         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6814                 return false;
6815
6816         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6817         if (IS_BROADWELL(dev_priv) &&
6818             crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
6819                 return false;
6820
6821         return true;
6822 }
6823
6824 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6825 {
6826         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6827
6828         /* GDG double wide on either pipe, otherwise pipe A only */
6829         return INTEL_GEN(dev_priv) < 4 &&
6830                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6831 }
6832
6833 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6834 {
6835         u32 pixel_rate;
6836
6837         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6838
6839         /*
6840          * We only use IF-ID interlacing. If we ever use
6841          * PF-ID we'll need to adjust the pixel_rate here.
6842          */
6843
6844         if (pipe_config->pch_pfit.enabled) {
6845                 u64 pipe_w, pipe_h, pfit_w, pfit_h;
6846                 u32 pfit_size = pipe_config->pch_pfit.size;
6847
6848                 pipe_w = pipe_config->pipe_src_w;
6849                 pipe_h = pipe_config->pipe_src_h;
6850
6851                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6852                 pfit_h = pfit_size & 0xFFFF;
6853                 if (pipe_w < pfit_w)
6854                         pipe_w = pfit_w;
6855                 if (pipe_h < pfit_h)
6856                         pipe_h = pfit_h;
6857
6858                 if (WARN_ON(!pfit_w || !pfit_h))
6859                         return pixel_rate;
6860
6861                 pixel_rate = div_u64((u64)pixel_rate * pipe_w * pipe_h,
6862                                      pfit_w * pfit_h);
6863         }
6864
6865         return pixel_rate;
6866 }
6867
6868 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6869 {
6870         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6871
6872         if (HAS_GMCH(dev_priv))
6873                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6874                 crtc_state->pixel_rate =
6875                         crtc_state->base.adjusted_mode.crtc_clock;
6876         else
6877                 crtc_state->pixel_rate =
6878                         ilk_pipe_pixel_rate(crtc_state);
6879 }
6880
6881 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6882                                      struct intel_crtc_state *pipe_config)
6883 {
6884         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6885         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6886         int clock_limit = dev_priv->max_dotclk_freq;
6887
6888         if (INTEL_GEN(dev_priv) < 4) {
6889                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6890
6891                 /*
6892                  * Enable double wide mode when the dot clock
6893                  * is > 90% of the (display) core speed.
6894                  */
6895                 if (intel_crtc_supports_double_wide(crtc) &&
6896                     adjusted_mode->crtc_clock > clock_limit) {
6897                         clock_limit = dev_priv->max_dotclk_freq;
6898                         pipe_config->double_wide = true;
6899                 }
6900         }
6901
6902         if (adjusted_mode->crtc_clock > clock_limit) {
6903                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6904                               adjusted_mode->crtc_clock, clock_limit,
6905                               yesno(pipe_config->double_wide));
6906                 return -EINVAL;
6907         }
6908
6909         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
6910              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
6911              pipe_config->base.ctm) {
6912                 /*
6913                  * There is only one pipe CSC unit per pipe, and we need that
6914                  * for output conversion from RGB->YCBCR. So if CTM is already
6915                  * applied we can't support YCBCR420 output.
6916                  */
6917                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6918                 return -EINVAL;
6919         }
6920
6921         /*
6922          * Pipe horizontal size must be even in:
6923          * - DVO ganged mode
6924          * - LVDS dual channel mode
6925          * - Double wide pipe
6926          */
6927         if (pipe_config->pipe_src_w & 1) {
6928                 if (pipe_config->double_wide) {
6929                         DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
6930                         return -EINVAL;
6931                 }
6932
6933                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6934                     intel_is_dual_link_lvds(dev_priv)) {
6935                         DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
6936                         return -EINVAL;
6937                 }
6938         }
6939
6940         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6941          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6942          */
6943         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6944                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6945                 return -EINVAL;
6946
6947         intel_crtc_compute_pixel_rate(pipe_config);
6948
6949         if (pipe_config->has_pch_encoder)
6950                 return ironlake_fdi_compute_config(crtc, pipe_config);
6951
6952         return 0;
6953 }
6954
6955 static void
6956 intel_reduce_m_n_ratio(u32 *num, u32 *den)
6957 {
6958         while (*num > DATA_LINK_M_N_MASK ||
6959                *den > DATA_LINK_M_N_MASK) {
6960                 *num >>= 1;
6961                 *den >>= 1;
6962         }
6963 }
6964
6965 static void compute_m_n(unsigned int m, unsigned int n,
6966                         u32 *ret_m, u32 *ret_n,
6967                         bool constant_n)
6968 {
6969         /*
6970          * Several DP dongles in particular seem to be fussy about
6971          * too large link M/N values. Give N value as 0x8000 that
6972          * should be acceptable by specific devices. 0x8000 is the
6973          * specified fixed N value for asynchronous clock mode,
6974          * which the devices expect also in synchronous clock mode.
6975          */
6976         if (constant_n)
6977                 *ret_n = 0x8000;
6978         else
6979                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6980
6981         *ret_m = div_u64((u64)m * *ret_n, n);
6982         intel_reduce_m_n_ratio(ret_m, ret_n);
6983 }
6984
6985 void
6986 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
6987                        int pixel_clock, int link_clock,
6988                        struct intel_link_m_n *m_n,
6989                        bool constant_n)
6990 {
6991         m_n->tu = 64;
6992
6993         compute_m_n(bits_per_pixel * pixel_clock,
6994                     link_clock * nlanes * 8,
6995                     &m_n->gmch_m, &m_n->gmch_n,
6996                     constant_n);
6997
6998         compute_m_n(pixel_clock, link_clock,
6999                     &m_n->link_m, &m_n->link_n,
7000                     constant_n);
7001 }
7002
7003 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7004 {
7005         if (i915_modparams.panel_use_ssc >= 0)
7006                 return i915_modparams.panel_use_ssc != 0;
7007         return dev_priv->vbt.lvds_use_ssc
7008                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7009 }
7010
7011 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7012 {
7013         return (1 << dpll->n) << 16 | dpll->m2;
7014 }
7015
7016 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7017 {
7018         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7019 }
7020
7021 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7022                                      struct intel_crtc_state *crtc_state,
7023                                      struct dpll *reduced_clock)
7024 {
7025         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7026         u32 fp, fp2 = 0;
7027
7028         if (IS_PINEVIEW(dev_priv)) {
7029                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7030                 if (reduced_clock)
7031                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7032         } else {
7033                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7034                 if (reduced_clock)
7035                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7036         }
7037
7038         crtc_state->dpll_hw_state.fp0 = fp;
7039
7040         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7041             reduced_clock) {
7042                 crtc_state->dpll_hw_state.fp1 = fp2;
7043         } else {
7044                 crtc_state->dpll_hw_state.fp1 = fp;
7045         }
7046 }
7047
7048 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7049                 pipe)
7050 {
7051         u32 reg_val;
7052
7053         /*
7054          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7055          * and set it to a reasonable value instead.
7056          */
7057         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7058         reg_val &= 0xffffff00;
7059         reg_val |= 0x00000030;
7060         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7061
7062         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7063         reg_val &= 0x00ffffff;
7064         reg_val |= 0x8c000000;
7065         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7066
7067         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7068         reg_val &= 0xffffff00;
7069         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7070
7071         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7072         reg_val &= 0x00ffffff;
7073         reg_val |= 0xb0000000;
7074         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7075 }
7076
7077 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7078                                          const struct intel_link_m_n *m_n)
7079 {
7080         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7081         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7082         enum pipe pipe = crtc->pipe;
7083
7084         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7085         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7086         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7087         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7088 }
7089
7090 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7091                                  enum transcoder transcoder)
7092 {
7093         if (IS_HASWELL(dev_priv))
7094                 return transcoder == TRANSCODER_EDP;
7095
7096         /*
7097          * Strictly speaking some registers are available before
7098          * gen7, but we only support DRRS on gen7+
7099          */
7100         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7101 }
7102
7103 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7104                                          const struct intel_link_m_n *m_n,
7105                                          const struct intel_link_m_n *m2_n2)
7106 {
7107         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7108         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7109         enum pipe pipe = crtc->pipe;
7110         enum transcoder transcoder = crtc_state->cpu_transcoder;
7111
7112         if (INTEL_GEN(dev_priv) >= 5) {
7113                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7114                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7115                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7116                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7117                 /*
7118                  *  M2_N2 registers are set only if DRRS is supported
7119                  * (to make sure the registers are not unnecessarily accessed).
7120                  */
7121                 if (m2_n2 && crtc_state->has_drrs &&
7122                     transcoder_has_m2_n2(dev_priv, transcoder)) {
7123                         I915_WRITE(PIPE_DATA_M2(transcoder),
7124                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7125                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7126                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7127                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7128                 }
7129         } else {
7130                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7131                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7132                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7133                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7134         }
7135 }
7136
7137 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7138 {
7139         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7140
7141         if (m_n == M1_N1) {
7142                 dp_m_n = &crtc_state->dp_m_n;
7143                 dp_m2_n2 = &crtc_state->dp_m2_n2;
7144         } else if (m_n == M2_N2) {
7145
7146                 /*
7147                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7148                  * needs to be programmed into M1_N1.
7149                  */
7150                 dp_m_n = &crtc_state->dp_m2_n2;
7151         } else {
7152                 DRM_ERROR("Unsupported divider value\n");
7153                 return;
7154         }
7155
7156         if (crtc_state->has_pch_encoder)
7157                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7158         else
7159                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7160 }
7161
7162 static void vlv_compute_dpll(struct intel_crtc *crtc,
7163                              struct intel_crtc_state *pipe_config)
7164 {
7165         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7166                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7167         if (crtc->pipe != PIPE_A)
7168                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7169
7170         /* DPLL not used with DSI, but still need the rest set up */
7171         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7172                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7173                         DPLL_EXT_BUFFER_ENABLE_VLV;
7174
7175         pipe_config->dpll_hw_state.dpll_md =
7176                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7177 }
7178
7179 static void chv_compute_dpll(struct intel_crtc *crtc,
7180                              struct intel_crtc_state *pipe_config)
7181 {
7182         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7183                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7184         if (crtc->pipe != PIPE_A)
7185                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7186
7187         /* DPLL not used with DSI, but still need the rest set up */
7188         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7189                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7190
7191         pipe_config->dpll_hw_state.dpll_md =
7192                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7193 }
7194
7195 static void vlv_prepare_pll(struct intel_crtc *crtc,
7196                             const struct intel_crtc_state *pipe_config)
7197 {
7198         struct drm_device *dev = crtc->base.dev;
7199         struct drm_i915_private *dev_priv = to_i915(dev);
7200         enum pipe pipe = crtc->pipe;
7201         u32 mdiv;
7202         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7203         u32 coreclk, reg_val;
7204
7205         /* Enable Refclk */
7206         I915_WRITE(DPLL(pipe),
7207                    pipe_config->dpll_hw_state.dpll &
7208                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7209
7210         /* No need to actually set up the DPLL with DSI */
7211         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7212                 return;
7213
7214         mutex_lock(&dev_priv->sb_lock);
7215
7216         bestn = pipe_config->dpll.n;
7217         bestm1 = pipe_config->dpll.m1;
7218         bestm2 = pipe_config->dpll.m2;
7219         bestp1 = pipe_config->dpll.p1;
7220         bestp2 = pipe_config->dpll.p2;
7221
7222         /* See eDP HDMI DPIO driver vbios notes doc */
7223
7224         /* PLL B needs special handling */
7225         if (pipe == PIPE_B)
7226                 vlv_pllb_recal_opamp(dev_priv, pipe);
7227
7228         /* Set up Tx target for periodic Rcomp update */
7229         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7230
7231         /* Disable target IRef on PLL */
7232         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7233         reg_val &= 0x00ffffff;
7234         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7235
7236         /* Disable fast lock */
7237         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7238
7239         /* Set idtafcrecal before PLL is enabled */
7240         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7241         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7242         mdiv |= ((bestn << DPIO_N_SHIFT));
7243         mdiv |= (1 << DPIO_K_SHIFT);
7244
7245         /*
7246          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7247          * but we don't support that).
7248          * Note: don't use the DAC post divider as it seems unstable.
7249          */
7250         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7251         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7252
7253         mdiv |= DPIO_ENABLE_CALIBRATION;
7254         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7255
7256         /* Set HBR and RBR LPF coefficients */
7257         if (pipe_config->port_clock == 162000 ||
7258             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
7259             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
7260                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7261                                  0x009f0003);
7262         else
7263                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7264                                  0x00d0000f);
7265
7266         if (intel_crtc_has_dp_encoder(pipe_config)) {
7267                 /* Use SSC source */
7268                 if (pipe == PIPE_A)
7269                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7270                                          0x0df40000);
7271                 else
7272                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7273                                          0x0df70000);
7274         } else { /* HDMI or VGA */
7275                 /* Use bend source */
7276                 if (pipe == PIPE_A)
7277                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7278                                          0x0df70000);
7279                 else
7280                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7281                                          0x0df40000);
7282         }
7283
7284         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7285         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7286         if (intel_crtc_has_dp_encoder(pipe_config))
7287                 coreclk |= 0x01000000;
7288         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7289
7290         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7291         mutex_unlock(&dev_priv->sb_lock);
7292 }
7293
7294 static void chv_prepare_pll(struct intel_crtc *crtc,
7295                             const struct intel_crtc_state *pipe_config)
7296 {
7297         struct drm_device *dev = crtc->base.dev;
7298         struct drm_i915_private *dev_priv = to_i915(dev);
7299         enum pipe pipe = crtc->pipe;
7300         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7301         u32 loopfilter, tribuf_calcntr;
7302         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7303         u32 dpio_val;
7304         int vco;
7305
7306         /* Enable Refclk and SSC */
7307         I915_WRITE(DPLL(pipe),
7308                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7309
7310         /* No need to actually set up the DPLL with DSI */
7311         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7312                 return;
7313
7314         bestn = pipe_config->dpll.n;
7315         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7316         bestm1 = pipe_config->dpll.m1;
7317         bestm2 = pipe_config->dpll.m2 >> 22;
7318         bestp1 = pipe_config->dpll.p1;
7319         bestp2 = pipe_config->dpll.p2;
7320         vco = pipe_config->dpll.vco;
7321         dpio_val = 0;
7322         loopfilter = 0;
7323
7324         mutex_lock(&dev_priv->sb_lock);
7325
7326         /* p1 and p2 divider */
7327         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7328                         5 << DPIO_CHV_S1_DIV_SHIFT |
7329                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7330                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7331                         1 << DPIO_CHV_K_DIV_SHIFT);
7332
7333         /* Feedback post-divider - m2 */
7334         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7335
7336         /* Feedback refclk divider - n and m1 */
7337         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7338                         DPIO_CHV_M1_DIV_BY_2 |
7339                         1 << DPIO_CHV_N_DIV_SHIFT);
7340
7341         /* M2 fraction division */
7342         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7343
7344         /* M2 fraction division enable */
7345         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7346         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7347         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7348         if (bestm2_frac)
7349                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7350         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7351
7352         /* Program digital lock detect threshold */
7353         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7354         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7355                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7356         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7357         if (!bestm2_frac)
7358                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7359         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7360
7361         /* Loop filter */
7362         if (vco == 5400000) {
7363                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7364                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7365                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7366                 tribuf_calcntr = 0x9;
7367         } else if (vco <= 6200000) {
7368                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7369                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7370                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7371                 tribuf_calcntr = 0x9;
7372         } else if (vco <= 6480000) {
7373                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7374                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7375                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7376                 tribuf_calcntr = 0x8;
7377         } else {
7378                 /* Not supported. Apply the same limits as in the max case */
7379                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7380                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7381                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7382                 tribuf_calcntr = 0;
7383         }
7384         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7385
7386         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7387         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7388         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7389         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7390
7391         /* AFC Recal */
7392         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7393                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7394                         DPIO_AFC_RECAL);
7395
7396         mutex_unlock(&dev_priv->sb_lock);
7397 }
7398
7399 /**
7400  * vlv_force_pll_on - forcibly enable just the PLL
7401  * @dev_priv: i915 private structure
7402  * @pipe: pipe PLL to enable
7403  * @dpll: PLL configuration
7404  *
7405  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7406  * in cases where we need the PLL enabled even when @pipe is not going to
7407  * be enabled.
7408  */
7409 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
7410                      const struct dpll *dpll)
7411 {
7412         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7413         struct intel_crtc_state *pipe_config;
7414
7415         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7416         if (!pipe_config)
7417                 return -ENOMEM;
7418
7419         pipe_config->base.crtc = &crtc->base;
7420         pipe_config->pixel_multiplier = 1;
7421         pipe_config->dpll = *dpll;
7422
7423         if (IS_CHERRYVIEW(dev_priv)) {
7424                 chv_compute_dpll(crtc, pipe_config);
7425                 chv_prepare_pll(crtc, pipe_config);
7426                 chv_enable_pll(crtc, pipe_config);
7427         } else {
7428                 vlv_compute_dpll(crtc, pipe_config);
7429                 vlv_prepare_pll(crtc, pipe_config);
7430                 vlv_enable_pll(crtc, pipe_config);
7431         }
7432
7433         kfree(pipe_config);
7434
7435         return 0;
7436 }
7437
7438 /**
7439  * vlv_force_pll_off - forcibly disable just the PLL
7440  * @dev_priv: i915 private structure
7441  * @pipe: pipe PLL to disable
7442  *
7443  * Disable the PLL for @pipe. To be used in cases where we need
7444  * the PLL enabled even when @pipe is not going to be enabled.
7445  */
7446 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
7447 {
7448         if (IS_CHERRYVIEW(dev_priv))
7449                 chv_disable_pll(dev_priv, pipe);
7450         else
7451                 vlv_disable_pll(dev_priv, pipe);
7452 }
7453
7454 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7455                               struct intel_crtc_state *crtc_state,
7456                               struct dpll *reduced_clock)
7457 {
7458         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7459         u32 dpll;
7460         struct dpll *clock = &crtc_state->dpll;
7461
7462         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7463
7464         dpll = DPLL_VGA_MODE_DIS;
7465
7466         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7467                 dpll |= DPLLB_MODE_LVDS;
7468         else
7469                 dpll |= DPLLB_MODE_DAC_SERIAL;
7470
7471         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7472             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7473                 dpll |= (crtc_state->pixel_multiplier - 1)
7474                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7475         }
7476
7477         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7478             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7479                 dpll |= DPLL_SDVO_HIGH_SPEED;
7480
7481         if (intel_crtc_has_dp_encoder(crtc_state))
7482                 dpll |= DPLL_SDVO_HIGH_SPEED;
7483
7484         /* compute bitmask from p1 value */
7485         if (IS_PINEVIEW(dev_priv))
7486                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7487         else {
7488                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7489                 if (IS_G4X(dev_priv) && reduced_clock)
7490                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7491         }
7492         switch (clock->p2) {
7493         case 5:
7494                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7495                 break;
7496         case 7:
7497                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7498                 break;
7499         case 10:
7500                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7501                 break;
7502         case 14:
7503                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7504                 break;
7505         }
7506         if (INTEL_GEN(dev_priv) >= 4)
7507                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7508
7509         if (crtc_state->sdvo_tv_clock)
7510                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7511         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7512                  intel_panel_use_ssc(dev_priv))
7513                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7514         else
7515                 dpll |= PLL_REF_INPUT_DREFCLK;
7516
7517         dpll |= DPLL_VCO_ENABLE;
7518         crtc_state->dpll_hw_state.dpll = dpll;
7519
7520         if (INTEL_GEN(dev_priv) >= 4) {
7521                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7522                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7523                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7524         }
7525 }
7526
7527 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7528                               struct intel_crtc_state *crtc_state,
7529                               struct dpll *reduced_clock)
7530 {
7531         struct drm_device *dev = crtc->base.dev;
7532         struct drm_i915_private *dev_priv = to_i915(dev);
7533         u32 dpll;
7534         struct dpll *clock = &crtc_state->dpll;
7535
7536         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7537
7538         dpll = DPLL_VGA_MODE_DIS;
7539
7540         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7541                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7542         } else {
7543                 if (clock->p1 == 2)
7544                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7545                 else
7546                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7547                 if (clock->p2 == 4)
7548                         dpll |= PLL_P2_DIVIDE_BY_4;
7549         }
7550
7551         /*
7552          * Bspec:
7553          * "[Almador Errata}: For the correct operation of the muxed DVO pins
7554          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
7555          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
7556          *  Enable) must be set to “1” in both the DPLL A Control Register
7557          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
7558          *
7559          * For simplicity We simply keep both bits always enabled in
7560          * both DPLLS. The spec says we should disable the DVO 2X clock
7561          * when not needed, but this seems to work fine in practice.
7562          */
7563         if (IS_I830(dev_priv) ||
7564             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7565                 dpll |= DPLL_DVO_2X_MODE;
7566
7567         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7568             intel_panel_use_ssc(dev_priv))
7569                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7570         else
7571                 dpll |= PLL_REF_INPUT_DREFCLK;
7572
7573         dpll |= DPLL_VCO_ENABLE;
7574         crtc_state->dpll_hw_state.dpll = dpll;
7575 }
7576
7577 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
7578 {
7579         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7580         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7581         enum pipe pipe = crtc->pipe;
7582         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
7583         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
7584         u32 crtc_vtotal, crtc_vblank_end;
7585         int vsyncshift = 0;
7586
7587         /* We need to be careful not to changed the adjusted mode, for otherwise
7588          * the hw state checker will get angry at the mismatch. */
7589         crtc_vtotal = adjusted_mode->crtc_vtotal;
7590         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7591
7592         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7593                 /* the chip adds 2 halflines automatically */
7594                 crtc_vtotal -= 1;
7595                 crtc_vblank_end -= 1;
7596
7597                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
7598                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7599                 else
7600                         vsyncshift = adjusted_mode->crtc_hsync_start -
7601                                 adjusted_mode->crtc_htotal / 2;
7602                 if (vsyncshift < 0)
7603                         vsyncshift += adjusted_mode->crtc_htotal;
7604         }
7605
7606         if (INTEL_GEN(dev_priv) > 3)
7607                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7608
7609         I915_WRITE(HTOTAL(cpu_transcoder),
7610                    (adjusted_mode->crtc_hdisplay - 1) |
7611                    ((adjusted_mode->crtc_htotal - 1) << 16));
7612         I915_WRITE(HBLANK(cpu_transcoder),
7613                    (adjusted_mode->crtc_hblank_start - 1) |
7614                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7615         I915_WRITE(HSYNC(cpu_transcoder),
7616                    (adjusted_mode->crtc_hsync_start - 1) |
7617                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7618
7619         I915_WRITE(VTOTAL(cpu_transcoder),
7620                    (adjusted_mode->crtc_vdisplay - 1) |
7621                    ((crtc_vtotal - 1) << 16));
7622         I915_WRITE(VBLANK(cpu_transcoder),
7623                    (adjusted_mode->crtc_vblank_start - 1) |
7624                    ((crtc_vblank_end - 1) << 16));
7625         I915_WRITE(VSYNC(cpu_transcoder),
7626                    (adjusted_mode->crtc_vsync_start - 1) |
7627                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7628
7629         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7630          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7631          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7632          * bits. */
7633         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7634             (pipe == PIPE_B || pipe == PIPE_C))
7635                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7636
7637 }
7638
7639 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
7640 {
7641         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7642         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7643         enum pipe pipe = crtc->pipe;
7644
7645         /* pipesrc controls the size that is scaled from, which should
7646          * always be the user's requested size.
7647          */
7648         I915_WRITE(PIPESRC(pipe),
7649                    ((crtc_state->pipe_src_w - 1) << 16) |
7650                    (crtc_state->pipe_src_h - 1));
7651 }
7652
7653 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7654                                    struct intel_crtc_state *pipe_config)
7655 {
7656         struct drm_device *dev = crtc->base.dev;
7657         struct drm_i915_private *dev_priv = to_i915(dev);
7658         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7659         u32 tmp;
7660
7661         tmp = I915_READ(HTOTAL(cpu_transcoder));
7662         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7663         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7664         tmp = I915_READ(HBLANK(cpu_transcoder));
7665         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7666         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7667         tmp = I915_READ(HSYNC(cpu_transcoder));
7668         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7669         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7670
7671         tmp = I915_READ(VTOTAL(cpu_transcoder));
7672         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7673         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7674         tmp = I915_READ(VBLANK(cpu_transcoder));
7675         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7676         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7677         tmp = I915_READ(VSYNC(cpu_transcoder));
7678         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7679         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7680
7681         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7682                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7683                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7684                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7685         }
7686 }
7687
7688 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7689                                     struct intel_crtc_state *pipe_config)
7690 {
7691         struct drm_device *dev = crtc->base.dev;
7692         struct drm_i915_private *dev_priv = to_i915(dev);
7693         u32 tmp;
7694
7695         tmp = I915_READ(PIPESRC(crtc->pipe));
7696         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7697         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7698
7699         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7700         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7701 }
7702
7703 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7704                                  struct intel_crtc_state *pipe_config)
7705 {
7706         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7707         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7708         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7709         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7710
7711         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7712         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7713         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7714         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7715
7716         mode->flags = pipe_config->base.adjusted_mode.flags;
7717         mode->type = DRM_MODE_TYPE_DRIVER;
7718
7719         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7720
7721         mode->hsync = drm_mode_hsync(mode);
7722         mode->vrefresh = drm_mode_vrefresh(mode);
7723         drm_mode_set_name(mode);
7724 }
7725
7726 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
7727 {
7728         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7729         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7730         u32 pipeconf;
7731
7732         pipeconf = 0;
7733
7734         /* we keep both pipes enabled on 830 */
7735         if (IS_I830(dev_priv))
7736                 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
7737
7738         if (crtc_state->double_wide)
7739                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7740
7741         /* only g4x and later have fancy bpc/dither controls */
7742         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7743             IS_CHERRYVIEW(dev_priv)) {
7744                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7745                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
7746                         pipeconf |= PIPECONF_DITHER_EN |
7747                                     PIPECONF_DITHER_TYPE_SP;
7748
7749                 switch (crtc_state->pipe_bpp) {
7750                 case 18:
7751                         pipeconf |= PIPECONF_6BPC;
7752                         break;
7753                 case 24:
7754                         pipeconf |= PIPECONF_8BPC;
7755                         break;
7756                 case 30:
7757                         pipeconf |= PIPECONF_10BPC;
7758                         break;
7759                 default:
7760                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7761                         BUG();
7762                 }
7763         }
7764
7765         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7766                 if (INTEL_GEN(dev_priv) < 4 ||
7767                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
7768                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7769                 else
7770                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7771         } else {
7772                 pipeconf |= PIPECONF_PROGRESSIVE;
7773         }
7774
7775         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7776              crtc_state->limited_color_range)
7777                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7778
7779         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
7780
7781         I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
7782         POSTING_READ(PIPECONF(crtc->pipe));
7783 }
7784
7785 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7786                                    struct intel_crtc_state *crtc_state)
7787 {
7788         struct drm_device *dev = crtc->base.dev;
7789         struct drm_i915_private *dev_priv = to_i915(dev);
7790         const struct intel_limit *limit;
7791         int refclk = 48000;
7792
7793         memset(&crtc_state->dpll_hw_state, 0,
7794                sizeof(crtc_state->dpll_hw_state));
7795
7796         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7797                 if (intel_panel_use_ssc(dev_priv)) {
7798                         refclk = dev_priv->vbt.lvds_ssc_freq;
7799                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7800                 }
7801
7802                 limit = &intel_limits_i8xx_lvds;
7803         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7804                 limit = &intel_limits_i8xx_dvo;
7805         } else {
7806                 limit = &intel_limits_i8xx_dac;
7807         }
7808
7809         if (!crtc_state->clock_set &&
7810             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7811                                  refclk, NULL, &crtc_state->dpll)) {
7812                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7813                 return -EINVAL;
7814         }
7815
7816         i8xx_compute_dpll(crtc, crtc_state, NULL);
7817
7818         return 0;
7819 }
7820
7821 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7822                                   struct intel_crtc_state *crtc_state)
7823 {
7824         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7825         const struct intel_limit *limit;
7826         int refclk = 96000;
7827
7828         memset(&crtc_state->dpll_hw_state, 0,
7829                sizeof(crtc_state->dpll_hw_state));
7830
7831         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7832                 if (intel_panel_use_ssc(dev_priv)) {
7833                         refclk = dev_priv->vbt.lvds_ssc_freq;
7834                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7835                 }
7836
7837                 if (intel_is_dual_link_lvds(dev_priv))
7838                         limit = &intel_limits_g4x_dual_channel_lvds;
7839                 else
7840                         limit = &intel_limits_g4x_single_channel_lvds;
7841         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7842                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7843                 limit = &intel_limits_g4x_hdmi;
7844         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7845                 limit = &intel_limits_g4x_sdvo;
7846         } else {
7847                 /* The option is for other outputs */
7848                 limit = &intel_limits_i9xx_sdvo;
7849         }
7850
7851         if (!crtc_state->clock_set &&
7852             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7853                                 refclk, NULL, &crtc_state->dpll)) {
7854                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7855                 return -EINVAL;
7856         }
7857
7858         i9xx_compute_dpll(crtc, crtc_state, NULL);
7859
7860         return 0;
7861 }
7862
7863 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7864                                   struct intel_crtc_state *crtc_state)
7865 {
7866         struct drm_device *dev = crtc->base.dev;
7867         struct drm_i915_private *dev_priv = to_i915(dev);
7868         const struct intel_limit *limit;
7869         int refclk = 96000;
7870
7871         memset(&crtc_state->dpll_hw_state, 0,
7872                sizeof(crtc_state->dpll_hw_state));
7873
7874         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7875                 if (intel_panel_use_ssc(dev_priv)) {
7876                         refclk = dev_priv->vbt.lvds_ssc_freq;
7877                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7878                 }
7879
7880                 limit = &intel_limits_pineview_lvds;
7881         } else {
7882                 limit = &intel_limits_pineview_sdvo;
7883         }
7884
7885         if (!crtc_state->clock_set &&
7886             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7887                                 refclk, NULL, &crtc_state->dpll)) {
7888                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7889                 return -EINVAL;
7890         }
7891
7892         i9xx_compute_dpll(crtc, crtc_state, NULL);
7893
7894         return 0;
7895 }
7896
7897 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7898                                    struct intel_crtc_state *crtc_state)
7899 {
7900         struct drm_device *dev = crtc->base.dev;
7901         struct drm_i915_private *dev_priv = to_i915(dev);
7902         const struct intel_limit *limit;
7903         int refclk = 96000;
7904
7905         memset(&crtc_state->dpll_hw_state, 0,
7906                sizeof(crtc_state->dpll_hw_state));
7907
7908         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7909                 if (intel_panel_use_ssc(dev_priv)) {
7910                         refclk = dev_priv->vbt.lvds_ssc_freq;
7911                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7912                 }
7913
7914                 limit = &intel_limits_i9xx_lvds;
7915         } else {
7916                 limit = &intel_limits_i9xx_sdvo;
7917         }
7918
7919         if (!crtc_state->clock_set &&
7920             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7921                                  refclk, NULL, &crtc_state->dpll)) {
7922                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7923                 return -EINVAL;
7924         }
7925
7926         i9xx_compute_dpll(crtc, crtc_state, NULL);
7927
7928         return 0;
7929 }
7930
7931 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7932                                   struct intel_crtc_state *crtc_state)
7933 {
7934         int refclk = 100000;
7935         const struct intel_limit *limit = &intel_limits_chv;
7936
7937         memset(&crtc_state->dpll_hw_state, 0,
7938                sizeof(crtc_state->dpll_hw_state));
7939
7940         if (!crtc_state->clock_set &&
7941             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7942                                 refclk, NULL, &crtc_state->dpll)) {
7943                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7944                 return -EINVAL;
7945         }
7946
7947         chv_compute_dpll(crtc, crtc_state);
7948
7949         return 0;
7950 }
7951
7952 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7953                                   struct intel_crtc_state *crtc_state)
7954 {
7955         int refclk = 100000;
7956         const struct intel_limit *limit = &intel_limits_vlv;
7957
7958         memset(&crtc_state->dpll_hw_state, 0,
7959                sizeof(crtc_state->dpll_hw_state));
7960
7961         if (!crtc_state->clock_set &&
7962             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7963                                 refclk, NULL, &crtc_state->dpll)) {
7964                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7965                 return -EINVAL;
7966         }
7967
7968         vlv_compute_dpll(crtc, crtc_state);
7969
7970         return 0;
7971 }
7972
7973 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
7974 {
7975         if (IS_I830(dev_priv))
7976                 return false;
7977
7978         return INTEL_GEN(dev_priv) >= 4 ||
7979                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
7980 }
7981
7982 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7983                                  struct intel_crtc_state *pipe_config)
7984 {
7985         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7986         u32 tmp;
7987
7988         if (!i9xx_has_pfit(dev_priv))
7989                 return;
7990
7991         tmp = I915_READ(PFIT_CONTROL);
7992         if (!(tmp & PFIT_ENABLE))
7993                 return;
7994
7995         /* Check whether the pfit is attached to our pipe. */
7996         if (INTEL_GEN(dev_priv) < 4) {
7997                 if (crtc->pipe != PIPE_B)
7998                         return;
7999         } else {
8000                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8001                         return;
8002         }
8003
8004         pipe_config->gmch_pfit.control = tmp;
8005         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8006 }
8007
8008 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8009                                struct intel_crtc_state *pipe_config)
8010 {
8011         struct drm_device *dev = crtc->base.dev;
8012         struct drm_i915_private *dev_priv = to_i915(dev);
8013         int pipe = pipe_config->cpu_transcoder;
8014         struct dpll clock;
8015         u32 mdiv;
8016         int refclk = 100000;
8017
8018         /* In case of DSI, DPLL will not be used */
8019         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8020                 return;
8021
8022         mutex_lock(&dev_priv->sb_lock);
8023         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8024         mutex_unlock(&dev_priv->sb_lock);
8025
8026         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8027         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8028         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8029         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8030         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8031
8032         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8033 }
8034
8035 static void
8036 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8037                               struct intel_initial_plane_config *plane_config)
8038 {
8039         struct drm_device *dev = crtc->base.dev;
8040         struct drm_i915_private *dev_priv = to_i915(dev);
8041         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8042         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8043         enum pipe pipe;
8044         u32 val, base, offset;
8045         int fourcc, pixel_format;
8046         unsigned int aligned_height;
8047         struct drm_framebuffer *fb;
8048         struct intel_framebuffer *intel_fb;
8049
8050         if (!plane->get_hw_state(plane, &pipe))
8051                 return;
8052
8053         WARN_ON(pipe != crtc->pipe);
8054
8055         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8056         if (!intel_fb) {
8057                 DRM_DEBUG_KMS("failed to alloc fb\n");
8058                 return;
8059         }
8060
8061         fb = &intel_fb->base;
8062
8063         fb->dev = dev;
8064
8065         val = I915_READ(DSPCNTR(i9xx_plane));
8066
8067         if (INTEL_GEN(dev_priv) >= 4) {
8068                 if (val & DISPPLANE_TILED) {
8069                         plane_config->tiling = I915_TILING_X;
8070                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8071                 }
8072
8073                 if (val & DISPPLANE_ROTATE_180)
8074                         plane_config->rotation = DRM_MODE_ROTATE_180;
8075         }
8076
8077         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8078             val & DISPPLANE_MIRROR)
8079                 plane_config->rotation |= DRM_MODE_REFLECT_X;
8080
8081         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8082         fourcc = i9xx_format_to_fourcc(pixel_format);
8083         fb->format = drm_format_info(fourcc);
8084
8085         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8086                 offset = I915_READ(DSPOFFSET(i9xx_plane));
8087                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8088         } else if (INTEL_GEN(dev_priv) >= 4) {
8089                 if (plane_config->tiling)
8090                         offset = I915_READ(DSPTILEOFF(i9xx_plane));
8091                 else
8092                         offset = I915_READ(DSPLINOFF(i9xx_plane));
8093                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8094         } else {
8095                 base = I915_READ(DSPADDR(i9xx_plane));
8096         }
8097         plane_config->base = base;
8098
8099         val = I915_READ(PIPESRC(pipe));
8100         fb->width = ((val >> 16) & 0xfff) + 1;
8101         fb->height = ((val >> 0) & 0xfff) + 1;
8102
8103         val = I915_READ(DSPSTRIDE(i9xx_plane));
8104         fb->pitches[0] = val & 0xffffffc0;
8105
8106         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8107
8108         plane_config->size = fb->pitches[0] * aligned_height;
8109
8110         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8111                       crtc->base.name, plane->base.name, fb->width, fb->height,
8112                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8113                       plane_config->size);
8114
8115         plane_config->fb = intel_fb;
8116 }
8117
8118 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8119                                struct intel_crtc_state *pipe_config)
8120 {
8121         struct drm_device *dev = crtc->base.dev;
8122         struct drm_i915_private *dev_priv = to_i915(dev);
8123         int pipe = pipe_config->cpu_transcoder;
8124         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8125         struct dpll clock;
8126         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8127         int refclk = 100000;
8128
8129         /* In case of DSI, DPLL will not be used */
8130         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8131                 return;
8132
8133         mutex_lock(&dev_priv->sb_lock);
8134         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8135         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8136         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8137         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8138         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8139         mutex_unlock(&dev_priv->sb_lock);
8140
8141         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8142         clock.m2 = (pll_dw0 & 0xff) << 22;
8143         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8144                 clock.m2 |= pll_dw2 & 0x3fffff;
8145         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8146         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8147         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8148
8149         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8150 }
8151
8152 static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
8153                                         struct intel_crtc_state *pipe_config)
8154 {
8155         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8156         enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
8157
8158         pipe_config->lspcon_downsampling = false;
8159
8160         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8161                 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
8162
8163                 if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8164                         bool ycbcr420_enabled = tmp & PIPEMISC_YUV420_ENABLE;
8165                         bool blend = tmp & PIPEMISC_YUV420_MODE_FULL_BLEND;
8166
8167                         if (ycbcr420_enabled) {
8168                                 /* We support 4:2:0 in full blend mode only */
8169                                 if (!blend)
8170                                         output = INTEL_OUTPUT_FORMAT_INVALID;
8171                                 else if (!(IS_GEMINILAKE(dev_priv) ||
8172                                            INTEL_GEN(dev_priv) >= 10))
8173                                         output = INTEL_OUTPUT_FORMAT_INVALID;
8174                                 else
8175                                         output = INTEL_OUTPUT_FORMAT_YCBCR420;
8176                         } else {
8177                                 /*
8178                                  * Currently there is no interface defined to
8179                                  * check user preference between RGB/YCBCR444
8180                                  * or YCBCR420. So the only possible case for
8181                                  * YCBCR444 usage is driving YCBCR420 output
8182                                  * with LSPCON, when pipe is configured for
8183                                  * YCBCR444 output and LSPCON takes care of
8184                                  * downsampling it.
8185                                  */
8186                                 pipe_config->lspcon_downsampling = true;
8187                                 output = INTEL_OUTPUT_FORMAT_YCBCR444;
8188                         }
8189                 }
8190         }
8191
8192         pipe_config->output_format = output;
8193 }
8194
8195 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8196 {
8197         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8198         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8199         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8200         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8201         u32 tmp;
8202
8203         tmp = I915_READ(DSPCNTR(i9xx_plane));
8204
8205         if (tmp & DISPPLANE_GAMMA_ENABLE)
8206                 crtc_state->gamma_enable = true;
8207
8208         if (!HAS_GMCH(dev_priv) &&
8209             tmp & DISPPLANE_PIPE_CSC_ENABLE)
8210                 crtc_state->csc_enable = true;
8211 }
8212
8213 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8214                                  struct intel_crtc_state *pipe_config)
8215 {
8216         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8217         enum intel_display_power_domain power_domain;
8218         intel_wakeref_t wakeref;
8219         u32 tmp;
8220         bool ret;
8221
8222         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8223         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8224         if (!wakeref)
8225                 return false;
8226
8227         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8228         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8229         pipe_config->shared_dpll = NULL;
8230
8231         ret = false;
8232
8233         tmp = I915_READ(PIPECONF(crtc->pipe));
8234         if (!(tmp & PIPECONF_ENABLE))
8235                 goto out;
8236
8237         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8238             IS_CHERRYVIEW(dev_priv)) {
8239                 switch (tmp & PIPECONF_BPC_MASK) {
8240                 case PIPECONF_6BPC:
8241                         pipe_config->pipe_bpp = 18;
8242                         break;
8243                 case PIPECONF_8BPC:
8244                         pipe_config->pipe_bpp = 24;
8245                         break;
8246                 case PIPECONF_10BPC:
8247                         pipe_config->pipe_bpp = 30;
8248                         break;
8249                 default:
8250                         break;
8251                 }
8252         }
8253
8254         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8255             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8256                 pipe_config->limited_color_range = true;
8257
8258         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
8259                 PIPECONF_GAMMA_MODE_SHIFT;
8260
8261         if (IS_CHERRYVIEW(dev_priv))
8262                 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
8263
8264         i9xx_get_pipe_color_config(pipe_config);
8265
8266         if (INTEL_GEN(dev_priv) < 4)
8267                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8268
8269         intel_get_pipe_timings(crtc, pipe_config);
8270         intel_get_pipe_src_size(crtc, pipe_config);
8271
8272         i9xx_get_pfit_config(crtc, pipe_config);
8273
8274         if (INTEL_GEN(dev_priv) >= 4) {
8275                 /* No way to read it out on pipes B and C */
8276                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8277                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8278                 else
8279                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8280                 pipe_config->pixel_multiplier =
8281                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8282                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8283                 pipe_config->dpll_hw_state.dpll_md = tmp;
8284         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8285                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8286                 tmp = I915_READ(DPLL(crtc->pipe));
8287                 pipe_config->pixel_multiplier =
8288                         ((tmp & SDVO_MULTIPLIER_MASK)
8289                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8290         } else {
8291                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8292                  * port and will be fixed up in the encoder->get_config
8293                  * function. */
8294                 pipe_config->pixel_multiplier = 1;
8295         }
8296         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8297         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8298                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8299                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8300         } else {
8301                 /* Mask out read-only status bits. */
8302                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8303                                                      DPLL_PORTC_READY_MASK |
8304                                                      DPLL_PORTB_READY_MASK);
8305         }
8306
8307         if (IS_CHERRYVIEW(dev_priv))
8308                 chv_crtc_clock_get(crtc, pipe_config);
8309         else if (IS_VALLEYVIEW(dev_priv))
8310                 vlv_crtc_clock_get(crtc, pipe_config);
8311         else
8312                 i9xx_crtc_clock_get(crtc, pipe_config);
8313
8314         /*
8315          * Normally the dotclock is filled in by the encoder .get_config()
8316          * but in case the pipe is enabled w/o any ports we need a sane
8317          * default.
8318          */
8319         pipe_config->base.adjusted_mode.crtc_clock =
8320                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8321
8322         ret = true;
8323
8324 out:
8325         intel_display_power_put(dev_priv, power_domain, wakeref);
8326
8327         return ret;
8328 }
8329
8330 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
8331 {
8332         struct intel_encoder *encoder;
8333         int i;
8334         u32 val, final;
8335         bool has_lvds = false;
8336         bool has_cpu_edp = false;
8337         bool has_panel = false;
8338         bool has_ck505 = false;
8339         bool can_ssc = false;
8340         bool using_ssc_source = false;
8341
8342         /* We need to take the global config into account */
8343         for_each_intel_encoder(&dev_priv->drm, encoder) {
8344                 switch (encoder->type) {
8345                 case INTEL_OUTPUT_LVDS:
8346                         has_panel = true;
8347                         has_lvds = true;
8348                         break;
8349                 case INTEL_OUTPUT_EDP:
8350                         has_panel = true;
8351                         if (encoder->port == PORT_A)
8352                                 has_cpu_edp = true;
8353                         break;
8354                 default:
8355                         break;
8356                 }
8357         }
8358
8359         if (HAS_PCH_IBX(dev_priv)) {
8360                 has_ck505 = dev_priv->vbt.display_clock_mode;
8361                 can_ssc = has_ck505;
8362         } else {
8363                 has_ck505 = false;
8364                 can_ssc = true;
8365         }
8366
8367         /* Check if any DPLLs are using the SSC source */
8368         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8369                 u32 temp = I915_READ(PCH_DPLL(i));
8370
8371                 if (!(temp & DPLL_VCO_ENABLE))
8372                         continue;
8373
8374                 if ((temp & PLL_REF_INPUT_MASK) ==
8375                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8376                         using_ssc_source = true;
8377                         break;
8378                 }
8379         }
8380
8381         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8382                       has_panel, has_lvds, has_ck505, using_ssc_source);
8383
8384         /* Ironlake: try to setup display ref clock before DPLL
8385          * enabling. This is only under driver's control after
8386          * PCH B stepping, previous chipset stepping should be
8387          * ignoring this setting.
8388          */
8389         val = I915_READ(PCH_DREF_CONTROL);
8390
8391         /* As we must carefully and slowly disable/enable each source in turn,
8392          * compute the final state we want first and check if we need to
8393          * make any changes at all.
8394          */
8395         final = val;
8396         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8397         if (has_ck505)
8398                 final |= DREF_NONSPREAD_CK505_ENABLE;
8399         else
8400                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8401
8402         final &= ~DREF_SSC_SOURCE_MASK;
8403         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8404         final &= ~DREF_SSC1_ENABLE;
8405
8406         if (has_panel) {
8407                 final |= DREF_SSC_SOURCE_ENABLE;
8408
8409                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8410                         final |= DREF_SSC1_ENABLE;
8411
8412                 if (has_cpu_edp) {
8413                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8414                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8415                         else
8416                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8417                 } else
8418                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8419         } else if (using_ssc_source) {
8420                 final |= DREF_SSC_SOURCE_ENABLE;
8421                 final |= DREF_SSC1_ENABLE;
8422         }
8423
8424         if (final == val)
8425                 return;
8426
8427         /* Always enable nonspread source */
8428         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8429
8430         if (has_ck505)
8431                 val |= DREF_NONSPREAD_CK505_ENABLE;
8432         else
8433                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8434
8435         if (has_panel) {
8436                 val &= ~DREF_SSC_SOURCE_MASK;
8437                 val |= DREF_SSC_SOURCE_ENABLE;
8438
8439                 /* SSC must be turned on before enabling the CPU output  */
8440                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8441                         DRM_DEBUG_KMS("Using SSC on panel\n");
8442                         val |= DREF_SSC1_ENABLE;
8443                 } else
8444                         val &= ~DREF_SSC1_ENABLE;
8445
8446                 /* Get SSC going before enabling the outputs */
8447                 I915_WRITE(PCH_DREF_CONTROL, val);
8448                 POSTING_READ(PCH_DREF_CONTROL);
8449                 udelay(200);
8450
8451                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8452
8453                 /* Enable CPU source on CPU attached eDP */
8454                 if (has_cpu_edp) {
8455                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8456                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8457                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8458                         } else
8459                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8460                 } else
8461                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8462
8463                 I915_WRITE(PCH_DREF_CONTROL, val);
8464                 POSTING_READ(PCH_DREF_CONTROL);
8465                 udelay(200);
8466         } else {
8467                 DRM_DEBUG_KMS("Disabling CPU source output\n");
8468
8469                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8470
8471                 /* Turn off CPU output */
8472                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8473
8474                 I915_WRITE(PCH_DREF_CONTROL, val);
8475                 POSTING_READ(PCH_DREF_CONTROL);
8476                 udelay(200);
8477
8478                 if (!using_ssc_source) {
8479                         DRM_DEBUG_KMS("Disabling SSC source\n");
8480
8481                         /* Turn off the SSC source */
8482                         val &= ~DREF_SSC_SOURCE_MASK;
8483                         val |= DREF_SSC_SOURCE_DISABLE;
8484
8485                         /* Turn off SSC1 */
8486                         val &= ~DREF_SSC1_ENABLE;
8487
8488                         I915_WRITE(PCH_DREF_CONTROL, val);
8489                         POSTING_READ(PCH_DREF_CONTROL);
8490                         udelay(200);
8491                 }
8492         }
8493
8494         BUG_ON(val != final);
8495 }
8496
8497 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8498 {
8499         u32 tmp;
8500
8501         tmp = I915_READ(SOUTH_CHICKEN2);
8502         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8503         I915_WRITE(SOUTH_CHICKEN2, tmp);
8504
8505         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8506                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8507                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8508
8509         tmp = I915_READ(SOUTH_CHICKEN2);
8510         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8511         I915_WRITE(SOUTH_CHICKEN2, tmp);
8512
8513         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8514                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8515                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8516 }
8517
8518 /* WaMPhyProgramming:hsw */
8519 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8520 {
8521         u32 tmp;
8522
8523         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8524         tmp &= ~(0xFF << 24);
8525         tmp |= (0x12 << 24);
8526         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8527
8528         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8529         tmp |= (1 << 11);
8530         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8531
8532         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8533         tmp |= (1 << 11);
8534         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8535
8536         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8537         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8538         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8539
8540         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8541         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8542         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8543
8544         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8545         tmp &= ~(7 << 13);
8546         tmp |= (5 << 13);
8547         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8548
8549         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8550         tmp &= ~(7 << 13);
8551         tmp |= (5 << 13);
8552         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8553
8554         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8555         tmp &= ~0xFF;
8556         tmp |= 0x1C;
8557         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8558
8559         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8560         tmp &= ~0xFF;
8561         tmp |= 0x1C;
8562         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8563
8564         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8565         tmp &= ~(0xFF << 16);
8566         tmp |= (0x1C << 16);
8567         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8568
8569         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8570         tmp &= ~(0xFF << 16);
8571         tmp |= (0x1C << 16);
8572         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8573
8574         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8575         tmp |= (1 << 27);
8576         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8577
8578         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8579         tmp |= (1 << 27);
8580         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8581
8582         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8583         tmp &= ~(0xF << 28);
8584         tmp |= (4 << 28);
8585         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8586
8587         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8588         tmp &= ~(0xF << 28);
8589         tmp |= (4 << 28);
8590         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8591 }
8592
8593 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8594  * Programming" based on the parameters passed:
8595  * - Sequence to enable CLKOUT_DP
8596  * - Sequence to enable CLKOUT_DP without spread
8597  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8598  */
8599 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
8600                                  bool with_spread, bool with_fdi)
8601 {
8602         u32 reg, tmp;
8603
8604         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8605                 with_spread = true;
8606         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
8607             with_fdi, "LP PCH doesn't have FDI\n"))
8608                 with_fdi = false;
8609
8610         mutex_lock(&dev_priv->sb_lock);
8611
8612         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8613         tmp &= ~SBI_SSCCTL_DISABLE;
8614         tmp |= SBI_SSCCTL_PATHALT;
8615         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8616
8617         udelay(24);
8618
8619         if (with_spread) {
8620                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8621                 tmp &= ~SBI_SSCCTL_PATHALT;
8622                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8623
8624                 if (with_fdi) {
8625                         lpt_reset_fdi_mphy(dev_priv);
8626                         lpt_program_fdi_mphy(dev_priv);
8627                 }
8628         }
8629
8630         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8631         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8632         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8633         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8634
8635         mutex_unlock(&dev_priv->sb_lock);
8636 }
8637
8638 /* Sequence to disable CLKOUT_DP */
8639 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8640 {
8641         u32 reg, tmp;
8642
8643         mutex_lock(&dev_priv->sb_lock);
8644
8645         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8646         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8647         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8648         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8649
8650         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8651         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8652                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8653                         tmp |= SBI_SSCCTL_PATHALT;
8654                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8655                         udelay(32);
8656                 }
8657                 tmp |= SBI_SSCCTL_DISABLE;
8658                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8659         }
8660
8661         mutex_unlock(&dev_priv->sb_lock);
8662 }
8663
8664 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8665
8666 static const u16 sscdivintphase[] = {
8667         [BEND_IDX( 50)] = 0x3B23,
8668         [BEND_IDX( 45)] = 0x3B23,
8669         [BEND_IDX( 40)] = 0x3C23,
8670         [BEND_IDX( 35)] = 0x3C23,
8671         [BEND_IDX( 30)] = 0x3D23,
8672         [BEND_IDX( 25)] = 0x3D23,
8673         [BEND_IDX( 20)] = 0x3E23,
8674         [BEND_IDX( 15)] = 0x3E23,
8675         [BEND_IDX( 10)] = 0x3F23,
8676         [BEND_IDX(  5)] = 0x3F23,
8677         [BEND_IDX(  0)] = 0x0025,
8678         [BEND_IDX( -5)] = 0x0025,
8679         [BEND_IDX(-10)] = 0x0125,
8680         [BEND_IDX(-15)] = 0x0125,
8681         [BEND_IDX(-20)] = 0x0225,
8682         [BEND_IDX(-25)] = 0x0225,
8683         [BEND_IDX(-30)] = 0x0325,
8684         [BEND_IDX(-35)] = 0x0325,
8685         [BEND_IDX(-40)] = 0x0425,
8686         [BEND_IDX(-45)] = 0x0425,
8687         [BEND_IDX(-50)] = 0x0525,
8688 };
8689
8690 /*
8691  * Bend CLKOUT_DP
8692  * steps -50 to 50 inclusive, in steps of 5
8693  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8694  * change in clock period = -(steps / 10) * 5.787 ps
8695  */
8696 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8697 {
8698         u32 tmp;
8699         int idx = BEND_IDX(steps);
8700
8701         if (WARN_ON(steps % 5 != 0))
8702                 return;
8703
8704         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8705                 return;
8706
8707         mutex_lock(&dev_priv->sb_lock);
8708
8709         if (steps % 10 != 0)
8710                 tmp = 0xAAAAAAAB;
8711         else
8712                 tmp = 0x00000000;
8713         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8714
8715         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8716         tmp &= 0xffff0000;
8717         tmp |= sscdivintphase[idx];
8718         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8719
8720         mutex_unlock(&dev_priv->sb_lock);
8721 }
8722
8723 #undef BEND_IDX
8724
8725 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8726 {
8727         struct intel_encoder *encoder;
8728         bool has_vga = false;
8729
8730         for_each_intel_encoder(&dev_priv->drm, encoder) {
8731                 switch (encoder->type) {
8732                 case INTEL_OUTPUT_ANALOG:
8733                         has_vga = true;
8734                         break;
8735                 default:
8736                         break;
8737                 }
8738         }
8739
8740         if (has_vga) {
8741                 lpt_bend_clkout_dp(dev_priv, 0);
8742                 lpt_enable_clkout_dp(dev_priv, true, true);
8743         } else {
8744                 lpt_disable_clkout_dp(dev_priv);
8745         }
8746 }
8747
8748 /*
8749  * Initialize reference clocks when the driver loads
8750  */
8751 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8752 {
8753         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8754                 ironlake_init_pch_refclk(dev_priv);
8755         else if (HAS_PCH_LPT(dev_priv))
8756                 lpt_init_pch_refclk(dev_priv);
8757 }
8758
8759 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
8760 {
8761         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8762         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8763         enum pipe pipe = crtc->pipe;
8764         u32 val;
8765
8766         val = 0;
8767
8768         switch (crtc_state->pipe_bpp) {
8769         case 18:
8770                 val |= PIPECONF_6BPC;
8771                 break;
8772         case 24:
8773                 val |= PIPECONF_8BPC;
8774                 break;
8775         case 30:
8776                 val |= PIPECONF_10BPC;
8777                 break;
8778         case 36:
8779                 val |= PIPECONF_12BPC;
8780                 break;
8781         default:
8782                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8783                 BUG();
8784         }
8785
8786         if (crtc_state->dither)
8787                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8788
8789         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8790                 val |= PIPECONF_INTERLACED_ILK;
8791         else
8792                 val |= PIPECONF_PROGRESSIVE;
8793
8794         if (crtc_state->limited_color_range)
8795                 val |= PIPECONF_COLOR_RANGE_SELECT;
8796
8797         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8798
8799         I915_WRITE(PIPECONF(pipe), val);
8800         POSTING_READ(PIPECONF(pipe));
8801 }
8802
8803 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
8804 {
8805         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8806         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8807         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8808         u32 val = 0;
8809
8810         if (IS_HASWELL(dev_priv) && crtc_state->dither)
8811                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8812
8813         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8814                 val |= PIPECONF_INTERLACED_ILK;
8815         else
8816                 val |= PIPECONF_PROGRESSIVE;
8817
8818         I915_WRITE(PIPECONF(cpu_transcoder), val);
8819         POSTING_READ(PIPECONF(cpu_transcoder));
8820 }
8821
8822 static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state)
8823 {
8824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
8825         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8826
8827         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8828                 u32 val = 0;
8829
8830                 switch (crtc_state->pipe_bpp) {
8831                 case 18:
8832                         val |= PIPEMISC_DITHER_6_BPC;
8833                         break;
8834                 case 24:
8835                         val |= PIPEMISC_DITHER_8_BPC;
8836                         break;
8837                 case 30:
8838                         val |= PIPEMISC_DITHER_10_BPC;
8839                         break;
8840                 case 36:
8841                         val |= PIPEMISC_DITHER_12_BPC;
8842                         break;
8843                 default:
8844                         /* Case prevented by pipe_config_set_bpp. */
8845                         BUG();
8846                 }
8847
8848                 if (crtc_state->dither)
8849                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8850
8851                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8852                     crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
8853                         val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
8854
8855                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
8856                         val |= PIPEMISC_YUV420_ENABLE |
8857                                 PIPEMISC_YUV420_MODE_FULL_BLEND;
8858
8859                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8860         }
8861 }
8862
8863 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8864 {
8865         /*
8866          * Account for spread spectrum to avoid
8867          * oversubscribing the link. Max center spread
8868          * is 2.5%; use 5% for safety's sake.
8869          */
8870         u32 bps = target_clock * bpp * 21 / 20;
8871         return DIV_ROUND_UP(bps, link_bw * 8);
8872 }
8873
8874 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8875 {
8876         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8877 }
8878
8879 static void ironlake_compute_dpll(struct intel_crtc *crtc,
8880                                   struct intel_crtc_state *crtc_state,
8881                                   struct dpll *reduced_clock)
8882 {
8883         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8884         u32 dpll, fp, fp2;
8885         int factor;
8886
8887         /* Enable autotuning of the PLL clock (if permissible) */
8888         factor = 21;
8889         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8890                 if ((intel_panel_use_ssc(dev_priv) &&
8891                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8892                     (HAS_PCH_IBX(dev_priv) &&
8893                      intel_is_dual_link_lvds(dev_priv)))
8894                         factor = 25;
8895         } else if (crtc_state->sdvo_tv_clock) {
8896                 factor = 20;
8897         }
8898
8899         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8900
8901         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8902                 fp |= FP_CB_TUNE;
8903
8904         if (reduced_clock) {
8905                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8906
8907                 if (reduced_clock->m < factor * reduced_clock->n)
8908                         fp2 |= FP_CB_TUNE;
8909         } else {
8910                 fp2 = fp;
8911         }
8912
8913         dpll = 0;
8914
8915         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8916                 dpll |= DPLLB_MODE_LVDS;
8917         else
8918                 dpll |= DPLLB_MODE_DAC_SERIAL;
8919
8920         dpll |= (crtc_state->pixel_multiplier - 1)
8921                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8922
8923         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8924             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8925                 dpll |= DPLL_SDVO_HIGH_SPEED;
8926
8927         if (intel_crtc_has_dp_encoder(crtc_state))
8928                 dpll |= DPLL_SDVO_HIGH_SPEED;
8929
8930         /*
8931          * The high speed IO clock is only really required for
8932          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8933          * possible to share the DPLL between CRT and HDMI. Enabling
8934          * the clock needlessly does no real harm, except use up a
8935          * bit of power potentially.
8936          *
8937          * We'll limit this to IVB with 3 pipes, since it has only two
8938          * DPLLs and so DPLL sharing is the only way to get three pipes
8939          * driving PCH ports at the same time. On SNB we could do this,
8940          * and potentially avoid enabling the second DPLL, but it's not
8941          * clear if it''s a win or loss power wise. No point in doing
8942          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8943          */
8944         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8945             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8946                 dpll |= DPLL_SDVO_HIGH_SPEED;
8947
8948         /* compute bitmask from p1 value */
8949         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8950         /* also FPA1 */
8951         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8952
8953         switch (crtc_state->dpll.p2) {
8954         case 5:
8955                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8956                 break;
8957         case 7:
8958                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8959                 break;
8960         case 10:
8961                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8962                 break;
8963         case 14:
8964                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8965                 break;
8966         }
8967
8968         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8969             intel_panel_use_ssc(dev_priv))
8970                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8971         else
8972                 dpll |= PLL_REF_INPUT_DREFCLK;
8973
8974         dpll |= DPLL_VCO_ENABLE;
8975
8976         crtc_state->dpll_hw_state.dpll = dpll;
8977         crtc_state->dpll_hw_state.fp0 = fp;
8978         crtc_state->dpll_hw_state.fp1 = fp2;
8979 }
8980
8981 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8982                                        struct intel_crtc_state *crtc_state)
8983 {
8984         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8985         const struct intel_limit *limit;
8986         int refclk = 120000;
8987
8988         memset(&crtc_state->dpll_hw_state, 0,
8989                sizeof(crtc_state->dpll_hw_state));
8990
8991         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8992         if (!crtc_state->has_pch_encoder)
8993                 return 0;
8994
8995         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8996                 if (intel_panel_use_ssc(dev_priv)) {
8997                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8998                                       dev_priv->vbt.lvds_ssc_freq);
8999                         refclk = dev_priv->vbt.lvds_ssc_freq;
9000                 }
9001
9002                 if (intel_is_dual_link_lvds(dev_priv)) {
9003                         if (refclk == 100000)
9004                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9005                         else
9006                                 limit = &intel_limits_ironlake_dual_lvds;
9007                 } else {
9008                         if (refclk == 100000)
9009                                 limit = &intel_limits_ironlake_single_lvds_100m;
9010                         else
9011                                 limit = &intel_limits_ironlake_single_lvds;
9012                 }
9013         } else {
9014                 limit = &intel_limits_ironlake_dac;
9015         }
9016
9017         if (!crtc_state->clock_set &&
9018             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9019                                 refclk, NULL, &crtc_state->dpll)) {
9020                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9021                 return -EINVAL;
9022         }
9023
9024         ironlake_compute_dpll(crtc, crtc_state, NULL);
9025
9026         if (!intel_get_shared_dpll(crtc_state, NULL)) {
9027                 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9028                               pipe_name(crtc->pipe));
9029                 return -EINVAL;
9030         }
9031
9032         return 0;
9033 }
9034
9035 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9036                                          struct intel_link_m_n *m_n)
9037 {
9038         struct drm_device *dev = crtc->base.dev;
9039         struct drm_i915_private *dev_priv = to_i915(dev);
9040         enum pipe pipe = crtc->pipe;
9041
9042         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9043         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9044         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9045                 & ~TU_SIZE_MASK;
9046         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9047         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9048                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9049 }
9050
9051 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9052                                          enum transcoder transcoder,
9053                                          struct intel_link_m_n *m_n,
9054                                          struct intel_link_m_n *m2_n2)
9055 {
9056         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9057         enum pipe pipe = crtc->pipe;
9058
9059         if (INTEL_GEN(dev_priv) >= 5) {
9060                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9061                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9062                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9063                         & ~TU_SIZE_MASK;
9064                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9065                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9066                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9067
9068                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9069                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9070                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9071                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9072                                         & ~TU_SIZE_MASK;
9073                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9074                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9075                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9076                 }
9077         } else {
9078                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9079                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9080                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9081                         & ~TU_SIZE_MASK;
9082                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9083                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9084                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9085         }
9086 }
9087
9088 void intel_dp_get_m_n(struct intel_crtc *crtc,
9089                       struct intel_crtc_state *pipe_config)
9090 {
9091         if (pipe_config->has_pch_encoder)
9092                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9093         else
9094                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9095                                              &pipe_config->dp_m_n,
9096                                              &pipe_config->dp_m2_n2);
9097 }
9098
9099 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9100                                         struct intel_crtc_state *pipe_config)
9101 {
9102         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9103                                      &pipe_config->fdi_m_n, NULL);
9104 }
9105
9106 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9107                                     struct intel_crtc_state *pipe_config)
9108 {
9109         struct drm_device *dev = crtc->base.dev;
9110         struct drm_i915_private *dev_priv = to_i915(dev);
9111         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9112         u32 ps_ctrl = 0;
9113         int id = -1;
9114         int i;
9115
9116         /* find scaler attached to this pipe */
9117         for (i = 0; i < crtc->num_scalers; i++) {
9118                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9119                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9120                         id = i;
9121                         pipe_config->pch_pfit.enabled = true;
9122                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9123                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9124                         scaler_state->scalers[i].in_use = true;
9125                         break;
9126                 }
9127         }
9128
9129         scaler_state->scaler_id = id;
9130         if (id >= 0) {
9131                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9132         } else {
9133                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9134         }
9135 }
9136
9137 static void
9138 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9139                                  struct intel_initial_plane_config *plane_config)
9140 {
9141         struct drm_device *dev = crtc->base.dev;
9142         struct drm_i915_private *dev_priv = to_i915(dev);
9143         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9144         enum plane_id plane_id = plane->id;
9145         enum pipe pipe;
9146         u32 val, base, offset, stride_mult, tiling, alpha;
9147         int fourcc, pixel_format;
9148         unsigned int aligned_height;
9149         struct drm_framebuffer *fb;
9150         struct intel_framebuffer *intel_fb;
9151
9152         if (!plane->get_hw_state(plane, &pipe))
9153                 return;
9154
9155         WARN_ON(pipe != crtc->pipe);
9156
9157         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9158         if (!intel_fb) {
9159                 DRM_DEBUG_KMS("failed to alloc fb\n");
9160                 return;
9161         }
9162
9163         fb = &intel_fb->base;
9164
9165         fb->dev = dev;
9166
9167         val = I915_READ(PLANE_CTL(pipe, plane_id));
9168
9169         if (INTEL_GEN(dev_priv) >= 11)
9170                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
9171         else
9172                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9173
9174         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
9175                 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
9176                 alpha &= PLANE_COLOR_ALPHA_MASK;
9177         } else {
9178                 alpha = val & PLANE_CTL_ALPHA_MASK;
9179         }
9180
9181         fourcc = skl_format_to_fourcc(pixel_format,
9182                                       val & PLANE_CTL_ORDER_RGBX, alpha);
9183         fb->format = drm_format_info(fourcc);
9184
9185         tiling = val & PLANE_CTL_TILED_MASK;
9186         switch (tiling) {
9187         case PLANE_CTL_TILED_LINEAR:
9188                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
9189                 break;
9190         case PLANE_CTL_TILED_X:
9191                 plane_config->tiling = I915_TILING_X;
9192                 fb->modifier = I915_FORMAT_MOD_X_TILED;
9193                 break;
9194         case PLANE_CTL_TILED_Y:
9195                 plane_config->tiling = I915_TILING_Y;
9196                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9197                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
9198                 else
9199                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
9200                 break;
9201         case PLANE_CTL_TILED_YF:
9202                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9203                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
9204                 else
9205                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9206                 break;
9207         default:
9208                 MISSING_CASE(tiling);
9209                 goto error;
9210         }
9211
9212         /*
9213          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
9214          * while i915 HW rotation is clockwise, thats why this swapping.
9215          */
9216         switch (val & PLANE_CTL_ROTATE_MASK) {
9217         case PLANE_CTL_ROTATE_0:
9218                 plane_config->rotation = DRM_MODE_ROTATE_0;
9219                 break;
9220         case PLANE_CTL_ROTATE_90:
9221                 plane_config->rotation = DRM_MODE_ROTATE_270;
9222                 break;
9223         case PLANE_CTL_ROTATE_180:
9224                 plane_config->rotation = DRM_MODE_ROTATE_180;
9225                 break;
9226         case PLANE_CTL_ROTATE_270:
9227                 plane_config->rotation = DRM_MODE_ROTATE_90;
9228                 break;
9229         }
9230
9231         if (INTEL_GEN(dev_priv) >= 10 &&
9232             val & PLANE_CTL_FLIP_HORIZONTAL)
9233                 plane_config->rotation |= DRM_MODE_REFLECT_X;
9234
9235         base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
9236         plane_config->base = base;
9237
9238         offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
9239
9240         val = I915_READ(PLANE_SIZE(pipe, plane_id));
9241         fb->height = ((val >> 16) & 0xfff) + 1;
9242         fb->width = ((val >> 0) & 0x1fff) + 1;
9243
9244         val = I915_READ(PLANE_STRIDE(pipe, plane_id));
9245         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
9246         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9247
9248         aligned_height = intel_fb_align_height(fb, 0, fb->height);
9249
9250         plane_config->size = fb->pitches[0] * aligned_height;
9251
9252         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9253                       crtc->base.name, plane->base.name, fb->width, fb->height,
9254                       fb->format->cpp[0] * 8, base, fb->pitches[0],
9255                       plane_config->size);
9256
9257         plane_config->fb = intel_fb;
9258         return;
9259
9260 error:
9261         kfree(intel_fb);
9262 }
9263
9264 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9265                                      struct intel_crtc_state *pipe_config)
9266 {
9267         struct drm_device *dev = crtc->base.dev;
9268         struct drm_i915_private *dev_priv = to_i915(dev);
9269         u32 tmp;
9270
9271         tmp = I915_READ(PF_CTL(crtc->pipe));
9272
9273         if (tmp & PF_ENABLE) {
9274                 pipe_config->pch_pfit.enabled = true;
9275                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9276                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9277
9278                 /* We currently do not free assignements of panel fitters on
9279                  * ivb/hsw (since we don't use the higher upscaling modes which
9280                  * differentiates them) so just WARN about this case for now. */
9281                 if (IS_GEN(dev_priv, 7)) {
9282                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9283                                 PF_PIPE_SEL_IVB(crtc->pipe));
9284                 }
9285         }
9286 }
9287
9288 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9289                                      struct intel_crtc_state *pipe_config)
9290 {
9291         struct drm_device *dev = crtc->base.dev;
9292         struct drm_i915_private *dev_priv = to_i915(dev);
9293         enum intel_display_power_domain power_domain;
9294         intel_wakeref_t wakeref;
9295         u32 tmp;
9296         bool ret;
9297
9298         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9299         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9300         if (!wakeref)
9301                 return false;
9302
9303         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9304         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9305         pipe_config->shared_dpll = NULL;
9306
9307         ret = false;
9308         tmp = I915_READ(PIPECONF(crtc->pipe));
9309         if (!(tmp & PIPECONF_ENABLE))
9310                 goto out;
9311
9312         switch (tmp & PIPECONF_BPC_MASK) {
9313         case PIPECONF_6BPC:
9314                 pipe_config->pipe_bpp = 18;
9315                 break;
9316         case PIPECONF_8BPC:
9317                 pipe_config->pipe_bpp = 24;
9318                 break;
9319         case PIPECONF_10BPC:
9320                 pipe_config->pipe_bpp = 30;
9321                 break;
9322         case PIPECONF_12BPC:
9323                 pipe_config->pipe_bpp = 36;
9324                 break;
9325         default:
9326                 break;
9327         }
9328
9329         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9330                 pipe_config->limited_color_range = true;
9331
9332         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
9333                 PIPECONF_GAMMA_MODE_SHIFT;
9334
9335         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
9336
9337         i9xx_get_pipe_color_config(pipe_config);
9338
9339         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9340                 struct intel_shared_dpll *pll;
9341                 enum intel_dpll_id pll_id;
9342
9343                 pipe_config->has_pch_encoder = true;
9344
9345                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9346                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9347                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9348
9349                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9350
9351                 if (HAS_PCH_IBX(dev_priv)) {
9352                         /*
9353                          * The pipe->pch transcoder and pch transcoder->pll
9354                          * mapping is fixed.
9355                          */
9356                         pll_id = (enum intel_dpll_id) crtc->pipe;
9357                 } else {
9358                         tmp = I915_READ(PCH_DPLL_SEL);
9359                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9360                                 pll_id = DPLL_ID_PCH_PLL_B;
9361                         else
9362                                 pll_id= DPLL_ID_PCH_PLL_A;
9363                 }
9364
9365                 pipe_config->shared_dpll =
9366                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9367                 pll = pipe_config->shared_dpll;
9368
9369                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9370                                                 &pipe_config->dpll_hw_state));
9371
9372                 tmp = pipe_config->dpll_hw_state.dpll;
9373                 pipe_config->pixel_multiplier =
9374                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9375                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9376
9377                 ironlake_pch_clock_get(crtc, pipe_config);
9378         } else {
9379                 pipe_config->pixel_multiplier = 1;
9380         }
9381
9382         intel_get_pipe_timings(crtc, pipe_config);
9383         intel_get_pipe_src_size(crtc, pipe_config);
9384
9385         ironlake_get_pfit_config(crtc, pipe_config);
9386
9387         ret = true;
9388
9389 out:
9390         intel_display_power_put(dev_priv, power_domain, wakeref);
9391
9392         return ret;
9393 }
9394
9395 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9396 {
9397         struct drm_device *dev = &dev_priv->drm;
9398         struct intel_crtc *crtc;
9399
9400         for_each_intel_crtc(dev, crtc)
9401                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9402                      pipe_name(crtc->pipe));
9403
9404         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
9405                         "Display power well on\n");
9406         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9407         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9408         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9409         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
9410         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9411              "CPU PWM1 enabled\n");
9412         if (IS_HASWELL(dev_priv))
9413                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9414                      "CPU PWM2 enabled\n");
9415         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9416              "PCH PWM1 enabled\n");
9417         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9418              "Utility pin enabled\n");
9419         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9420
9421         /*
9422          * In theory we can still leave IRQs enabled, as long as only the HPD
9423          * interrupts remain enabled. We used to check for that, but since it's
9424          * gen-specific and since we only disable LCPLL after we fully disable
9425          * the interrupts, the check below should be enough.
9426          */
9427         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9428 }
9429
9430 static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
9431 {
9432         if (IS_HASWELL(dev_priv))
9433                 return I915_READ(D_COMP_HSW);
9434         else
9435                 return I915_READ(D_COMP_BDW);
9436 }
9437
9438 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
9439 {
9440         if (IS_HASWELL(dev_priv)) {
9441                 mutex_lock(&dev_priv->pcu_lock);
9442                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9443                                             val))
9444                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
9445                 mutex_unlock(&dev_priv->pcu_lock);
9446         } else {
9447                 I915_WRITE(D_COMP_BDW, val);
9448                 POSTING_READ(D_COMP_BDW);
9449         }
9450 }
9451
9452 /*
9453  * This function implements pieces of two sequences from BSpec:
9454  * - Sequence for display software to disable LCPLL
9455  * - Sequence for display software to allow package C8+
9456  * The steps implemented here are just the steps that actually touch the LCPLL
9457  * register. Callers should take care of disabling all the display engine
9458  * functions, doing the mode unset, fixing interrupts, etc.
9459  */
9460 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9461                               bool switch_to_fclk, bool allow_power_down)
9462 {
9463         u32 val;
9464
9465         assert_can_disable_lcpll(dev_priv);
9466
9467         val = I915_READ(LCPLL_CTL);
9468
9469         if (switch_to_fclk) {
9470                 val |= LCPLL_CD_SOURCE_FCLK;
9471                 I915_WRITE(LCPLL_CTL, val);
9472
9473                 if (wait_for_us(I915_READ(LCPLL_CTL) &
9474                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9475                         DRM_ERROR("Switching to FCLK failed\n");
9476
9477                 val = I915_READ(LCPLL_CTL);
9478         }
9479
9480         val |= LCPLL_PLL_DISABLE;
9481         I915_WRITE(LCPLL_CTL, val);
9482         POSTING_READ(LCPLL_CTL);
9483
9484         if (intel_wait_for_register(&dev_priv->uncore,
9485                                     LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9486                 DRM_ERROR("LCPLL still locked\n");
9487
9488         val = hsw_read_dcomp(dev_priv);
9489         val |= D_COMP_COMP_DISABLE;
9490         hsw_write_dcomp(dev_priv, val);
9491         ndelay(100);
9492
9493         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9494                      1))
9495                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9496
9497         if (allow_power_down) {
9498                 val = I915_READ(LCPLL_CTL);
9499                 val |= LCPLL_POWER_DOWN_ALLOW;
9500                 I915_WRITE(LCPLL_CTL, val);
9501                 POSTING_READ(LCPLL_CTL);
9502         }
9503 }
9504
9505 /*
9506  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9507  * source.
9508  */
9509 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9510 {
9511         u32 val;
9512
9513         val = I915_READ(LCPLL_CTL);
9514
9515         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9516                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9517                 return;
9518
9519         /*
9520          * Make sure we're not on PC8 state before disabling PC8, otherwise
9521          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9522          */
9523         intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
9524
9525         if (val & LCPLL_POWER_DOWN_ALLOW) {
9526                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9527                 I915_WRITE(LCPLL_CTL, val);
9528                 POSTING_READ(LCPLL_CTL);
9529         }
9530
9531         val = hsw_read_dcomp(dev_priv);
9532         val |= D_COMP_COMP_FORCE;
9533         val &= ~D_COMP_COMP_DISABLE;
9534         hsw_write_dcomp(dev_priv, val);
9535
9536         val = I915_READ(LCPLL_CTL);
9537         val &= ~LCPLL_PLL_DISABLE;
9538         I915_WRITE(LCPLL_CTL, val);
9539
9540         if (intel_wait_for_register(&dev_priv->uncore,
9541                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9542                                     5))
9543                 DRM_ERROR("LCPLL not locked yet\n");
9544
9545         if (val & LCPLL_CD_SOURCE_FCLK) {
9546                 val = I915_READ(LCPLL_CTL);
9547                 val &= ~LCPLL_CD_SOURCE_FCLK;
9548                 I915_WRITE(LCPLL_CTL, val);
9549
9550                 if (wait_for_us((I915_READ(LCPLL_CTL) &
9551                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9552                         DRM_ERROR("Switching back to LCPLL failed\n");
9553         }
9554
9555         intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
9556
9557         intel_update_cdclk(dev_priv);
9558         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
9559 }
9560
9561 /*
9562  * Package states C8 and deeper are really deep PC states that can only be
9563  * reached when all the devices on the system allow it, so even if the graphics
9564  * device allows PC8+, it doesn't mean the system will actually get to these
9565  * states. Our driver only allows PC8+ when going into runtime PM.
9566  *
9567  * The requirements for PC8+ are that all the outputs are disabled, the power
9568  * well is disabled and most interrupts are disabled, and these are also
9569  * requirements for runtime PM. When these conditions are met, we manually do
9570  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9571  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9572  * hang the machine.
9573  *
9574  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9575  * the state of some registers, so when we come back from PC8+ we need to
9576  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9577  * need to take care of the registers kept by RC6. Notice that this happens even
9578  * if we don't put the device in PCI D3 state (which is what currently happens
9579  * because of the runtime PM support).
9580  *
9581  * For more, read "Display Sequences for Package C8" on the hardware
9582  * documentation.
9583  */
9584 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9585 {
9586         u32 val;
9587
9588         DRM_DEBUG_KMS("Enabling package C8+\n");
9589
9590         if (HAS_PCH_LPT_LP(dev_priv)) {
9591                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9592                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9593                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9594         }
9595
9596         lpt_disable_clkout_dp(dev_priv);
9597         hsw_disable_lcpll(dev_priv, true, true);
9598 }
9599
9600 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9601 {
9602         u32 val;
9603
9604         DRM_DEBUG_KMS("Disabling package C8+\n");
9605
9606         hsw_restore_lcpll(dev_priv);
9607         lpt_init_pch_refclk(dev_priv);
9608
9609         if (HAS_PCH_LPT_LP(dev_priv)) {
9610                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9611                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9612                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9613         }
9614 }
9615
9616 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9617                                       struct intel_crtc_state *crtc_state)
9618 {
9619         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9620         struct intel_atomic_state *state =
9621                 to_intel_atomic_state(crtc_state->base.state);
9622
9623         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
9624             INTEL_GEN(dev_priv) >= 11) {
9625                 struct intel_encoder *encoder =
9626                         intel_get_crtc_new_encoder(state, crtc_state);
9627
9628                 if (!intel_get_shared_dpll(crtc_state, encoder)) {
9629                         DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9630                                       pipe_name(crtc->pipe));
9631                         return -EINVAL;
9632                 }
9633         }
9634
9635         return 0;
9636 }
9637
9638 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9639                                    enum port port,
9640                                    struct intel_crtc_state *pipe_config)
9641 {
9642         enum intel_dpll_id id;
9643         u32 temp;
9644
9645         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9646         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9647
9648         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9649                 return;
9650
9651         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9652 }
9653
9654 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
9655                                 enum port port,
9656                                 struct intel_crtc_state *pipe_config)
9657 {
9658         enum intel_dpll_id id;
9659         u32 temp;
9660
9661         /* TODO: TBT pll not implemented. */
9662         if (intel_port_is_combophy(dev_priv, port)) {
9663                 temp = I915_READ(DPCLKA_CFGCR0_ICL) &
9664                        DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9665                 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9666         } else if (intel_port_is_tc(dev_priv, port)) {
9667                 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
9668         } else {
9669                 WARN(1, "Invalid port %x\n", port);
9670                 return;
9671         }
9672
9673         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9674 }
9675
9676 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9677                                 enum port port,
9678                                 struct intel_crtc_state *pipe_config)
9679 {
9680         enum intel_dpll_id id;
9681
9682         switch (port) {
9683         case PORT_A:
9684                 id = DPLL_ID_SKL_DPLL0;
9685                 break;
9686         case PORT_B:
9687                 id = DPLL_ID_SKL_DPLL1;
9688                 break;
9689         case PORT_C:
9690                 id = DPLL_ID_SKL_DPLL2;
9691                 break;
9692         default:
9693                 DRM_ERROR("Incorrect port type\n");
9694                 return;
9695         }
9696
9697         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9698 }
9699
9700 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9701                                 enum port port,
9702                                 struct intel_crtc_state *pipe_config)
9703 {
9704         enum intel_dpll_id id;
9705         u32 temp;
9706
9707         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9708         id = temp >> (port * 3 + 1);
9709
9710         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9711                 return;
9712
9713         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9714 }
9715
9716 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9717                                 enum port port,
9718                                 struct intel_crtc_state *pipe_config)
9719 {
9720         enum intel_dpll_id id;
9721         u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9722
9723         switch (ddi_pll_sel) {
9724         case PORT_CLK_SEL_WRPLL1:
9725                 id = DPLL_ID_WRPLL1;
9726                 break;
9727         case PORT_CLK_SEL_WRPLL2:
9728                 id = DPLL_ID_WRPLL2;
9729                 break;
9730         case PORT_CLK_SEL_SPLL:
9731                 id = DPLL_ID_SPLL;
9732                 break;
9733         case PORT_CLK_SEL_LCPLL_810:
9734                 id = DPLL_ID_LCPLL_810;
9735                 break;
9736         case PORT_CLK_SEL_LCPLL_1350:
9737                 id = DPLL_ID_LCPLL_1350;
9738                 break;
9739         case PORT_CLK_SEL_LCPLL_2700:
9740                 id = DPLL_ID_LCPLL_2700;
9741                 break;
9742         default:
9743                 MISSING_CASE(ddi_pll_sel);
9744                 /* fall through */
9745         case PORT_CLK_SEL_NONE:
9746                 return;
9747         }
9748
9749         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9750 }
9751
9752 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9753                                      struct intel_crtc_state *pipe_config,
9754                                      u64 *power_domain_mask)
9755 {
9756         struct drm_device *dev = crtc->base.dev;
9757         struct drm_i915_private *dev_priv = to_i915(dev);
9758         enum intel_display_power_domain power_domain;
9759         unsigned long panel_transcoder_mask = 0;
9760         unsigned long enabled_panel_transcoders = 0;
9761         enum transcoder panel_transcoder;
9762         u32 tmp;
9763
9764         if (INTEL_GEN(dev_priv) >= 11)
9765                 panel_transcoder_mask |=
9766                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
9767
9768         if (HAS_TRANSCODER_EDP(dev_priv))
9769                 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
9770
9771         /*
9772          * The pipe->transcoder mapping is fixed with the exception of the eDP
9773          * and DSI transcoders handled below.
9774          */
9775         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9776
9777         /*
9778          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9779          * consistency and less surprising code; it's in always on power).
9780          */
9781         for_each_set_bit(panel_transcoder,
9782                          &panel_transcoder_mask,
9783                          ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
9784                 enum pipe trans_pipe;
9785
9786                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
9787                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
9788                         continue;
9789
9790                 /*
9791                  * Log all enabled ones, only use the first one.
9792                  *
9793                  * FIXME: This won't work for two separate DSI displays.
9794                  */
9795                 enabled_panel_transcoders |= BIT(panel_transcoder);
9796                 if (enabled_panel_transcoders != BIT(panel_transcoder))
9797                         continue;
9798
9799                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9800                 default:
9801                         WARN(1, "unknown pipe linked to transcoder %s\n",
9802                              transcoder_name(panel_transcoder));
9803                         /* fall through */
9804                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9805                 case TRANS_DDI_EDP_INPUT_A_ON:
9806                         trans_pipe = PIPE_A;
9807                         break;
9808                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9809                         trans_pipe = PIPE_B;
9810                         break;
9811                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9812                         trans_pipe = PIPE_C;
9813                         break;
9814                 }
9815
9816                 if (trans_pipe == crtc->pipe)
9817                         pipe_config->cpu_transcoder = panel_transcoder;
9818         }
9819
9820         /*
9821          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
9822          */
9823         WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
9824                 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
9825
9826         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9827         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9828                 return false;
9829
9830         WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
9831         *power_domain_mask |= BIT_ULL(power_domain);
9832
9833         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9834
9835         return tmp & PIPECONF_ENABLE;
9836 }
9837
9838 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9839                                          struct intel_crtc_state *pipe_config,
9840                                          u64 *power_domain_mask)
9841 {
9842         struct drm_device *dev = crtc->base.dev;
9843         struct drm_i915_private *dev_priv = to_i915(dev);
9844         enum intel_display_power_domain power_domain;
9845         enum port port;
9846         enum transcoder cpu_transcoder;
9847         u32 tmp;
9848
9849         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9850                 if (port == PORT_A)
9851                         cpu_transcoder = TRANSCODER_DSI_A;
9852                 else
9853                         cpu_transcoder = TRANSCODER_DSI_C;
9854
9855                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9856                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9857                         continue;
9858
9859                 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
9860                 *power_domain_mask |= BIT_ULL(power_domain);
9861
9862                 /*
9863                  * The PLL needs to be enabled with a valid divider
9864                  * configuration, otherwise accessing DSI registers will hang
9865                  * the machine. See BSpec North Display Engine
9866                  * registers/MIPI[BXT]. We can break out here early, since we
9867                  * need the same DSI PLL to be enabled for both DSI ports.
9868                  */
9869                 if (!bxt_dsi_pll_is_enabled(dev_priv))
9870                         break;
9871
9872                 /* XXX: this works for video mode only */
9873                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9874                 if (!(tmp & DPI_ENABLE))
9875                         continue;
9876
9877                 tmp = I915_READ(MIPI_CTRL(port));
9878                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9879                         continue;
9880
9881                 pipe_config->cpu_transcoder = cpu_transcoder;
9882                 break;
9883         }
9884
9885         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9886 }
9887
9888 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9889                                        struct intel_crtc_state *pipe_config)
9890 {
9891         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9892         struct intel_shared_dpll *pll;
9893         enum port port;
9894         u32 tmp;
9895
9896         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9897
9898         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9899
9900         if (INTEL_GEN(dev_priv) >= 11)
9901                 icelake_get_ddi_pll(dev_priv, port, pipe_config);
9902         else if (IS_CANNONLAKE(dev_priv))
9903                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9904         else if (IS_GEN9_BC(dev_priv))
9905                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9906         else if (IS_GEN9_LP(dev_priv))
9907                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9908         else
9909                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9910
9911         pll = pipe_config->shared_dpll;
9912         if (pll) {
9913                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9914                                                 &pipe_config->dpll_hw_state));
9915         }
9916
9917         /*
9918          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9919          * DDI E. So just check whether this pipe is wired to DDI E and whether
9920          * the PCH transcoder is on.
9921          */
9922         if (INTEL_GEN(dev_priv) < 9 &&
9923             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9924                 pipe_config->has_pch_encoder = true;
9925
9926                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9927                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9928                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9929
9930                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9931         }
9932 }
9933
9934 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9935                                     struct intel_crtc_state *pipe_config)
9936 {
9937         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9938         enum intel_display_power_domain power_domain;
9939         u64 power_domain_mask;
9940         bool active;
9941
9942         intel_crtc_init_scalers(crtc, pipe_config);
9943
9944         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9945         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9946                 return false;
9947         power_domain_mask = BIT_ULL(power_domain);
9948
9949         pipe_config->shared_dpll = NULL;
9950
9951         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9952
9953         if (IS_GEN9_LP(dev_priv) &&
9954             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9955                 WARN_ON(active);
9956                 active = true;
9957         }
9958
9959         if (!active)
9960                 goto out;
9961
9962         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
9963             INTEL_GEN(dev_priv) >= 11) {
9964                 haswell_get_ddi_port_state(crtc, pipe_config);
9965                 intel_get_pipe_timings(crtc, pipe_config);
9966         }
9967
9968         intel_get_pipe_src_size(crtc, pipe_config);
9969         intel_get_crtc_ycbcr_config(crtc, pipe_config);
9970
9971         pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
9972
9973         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
9974
9975         if (INTEL_GEN(dev_priv) >= 9) {
9976                 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
9977
9978                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
9979                         pipe_config->gamma_enable = true;
9980
9981                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
9982                         pipe_config->csc_enable = true;
9983         } else {
9984                 i9xx_get_pipe_color_config(pipe_config);
9985         }
9986
9987         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9988         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9989                 WARN_ON(power_domain_mask & BIT_ULL(power_domain));
9990                 power_domain_mask |= BIT_ULL(power_domain);
9991
9992                 if (INTEL_GEN(dev_priv) >= 9)
9993                         skylake_get_pfit_config(crtc, pipe_config);
9994                 else
9995                         ironlake_get_pfit_config(crtc, pipe_config);
9996         }
9997
9998         if (hsw_crtc_supports_ips(crtc)) {
9999                 if (IS_HASWELL(dev_priv))
10000                         pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
10001                 else {
10002                         /*
10003                          * We cannot readout IPS state on broadwell, set to
10004                          * true so we can set it to a defined state on first
10005                          * commit.
10006                          */
10007                         pipe_config->ips_enabled = true;
10008                 }
10009         }
10010
10011         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10012             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10013                 pipe_config->pixel_multiplier =
10014                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10015         } else {
10016                 pipe_config->pixel_multiplier = 1;
10017         }
10018
10019 out:
10020         for_each_power_domain(power_domain, power_domain_mask)
10021                 intel_display_power_put_unchecked(dev_priv, power_domain);
10022
10023         return active;
10024 }
10025
10026 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
10027 {
10028         struct drm_i915_private *dev_priv =
10029                 to_i915(plane_state->base.plane->dev);
10030         const struct drm_framebuffer *fb = plane_state->base.fb;
10031         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10032         u32 base;
10033
10034         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
10035                 base = obj->phys_handle->busaddr;
10036         else
10037                 base = intel_plane_ggtt_offset(plane_state);
10038
10039         base += plane_state->color_plane[0].offset;
10040
10041         /* ILK+ do this automagically */
10042         if (HAS_GMCH(dev_priv) &&
10043             plane_state->base.rotation & DRM_MODE_ROTATE_180)
10044                 base += (plane_state->base.crtc_h *
10045                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
10046
10047         return base;
10048 }
10049
10050 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
10051 {
10052         int x = plane_state->base.crtc_x;
10053         int y = plane_state->base.crtc_y;
10054         u32 pos = 0;
10055
10056         if (x < 0) {
10057                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10058                 x = -x;
10059         }
10060         pos |= x << CURSOR_X_SHIFT;
10061
10062         if (y < 0) {
10063                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10064                 y = -y;
10065         }
10066         pos |= y << CURSOR_Y_SHIFT;
10067
10068         return pos;
10069 }
10070
10071 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
10072 {
10073         const struct drm_mode_config *config =
10074                 &plane_state->base.plane->dev->mode_config;
10075         int width = plane_state->base.crtc_w;
10076         int height = plane_state->base.crtc_h;
10077
10078         return width > 0 && width <= config->cursor_width &&
10079                 height > 0 && height <= config->cursor_height;
10080 }
10081
10082 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10083 {
10084         const struct drm_framebuffer *fb = plane_state->base.fb;
10085         unsigned int rotation = plane_state->base.rotation;
10086         int src_x, src_y;
10087         u32 offset;
10088         int ret;
10089
10090         intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
10091         plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
10092
10093         ret = intel_plane_check_stride(plane_state);
10094         if (ret)
10095                 return ret;
10096
10097         src_x = plane_state->base.src_x >> 16;
10098         src_y = plane_state->base.src_y >> 16;
10099
10100         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10101         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10102                                                     plane_state, 0);
10103
10104         if (src_x != 0 || src_y != 0) {
10105                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10106                 return -EINVAL;
10107         }
10108
10109         plane_state->color_plane[0].offset = offset;
10110
10111         return 0;
10112 }
10113
10114 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10115                               struct intel_plane_state *plane_state)
10116 {
10117         const struct drm_framebuffer *fb = plane_state->base.fb;
10118         int ret;
10119
10120         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10121                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10122                 return -EINVAL;
10123         }
10124
10125         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
10126                                                   &crtc_state->base,
10127                                                   DRM_PLANE_HELPER_NO_SCALING,
10128                                                   DRM_PLANE_HELPER_NO_SCALING,
10129                                                   true, true);
10130         if (ret)
10131                 return ret;
10132
10133         if (!plane_state->base.visible)
10134                 return 0;
10135
10136         ret = intel_plane_check_src_coordinates(plane_state);
10137         if (ret)
10138                 return ret;
10139
10140         ret = intel_cursor_check_surface(plane_state);
10141         if (ret)
10142                 return ret;
10143
10144         return 0;
10145 }
10146
10147 static unsigned int
10148 i845_cursor_max_stride(struct intel_plane *plane,
10149                        u32 pixel_format, u64 modifier,
10150                        unsigned int rotation)
10151 {
10152         return 2048;
10153 }
10154
10155 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10156 {
10157         u32 cntl = 0;
10158
10159         if (crtc_state->gamma_enable)
10160                 cntl |= CURSOR_GAMMA_ENABLE;
10161
10162         return cntl;
10163 }
10164
10165 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10166                            const struct intel_plane_state *plane_state)
10167 {
10168         return CURSOR_ENABLE |
10169                 CURSOR_FORMAT_ARGB |
10170                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10171 }
10172
10173 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10174 {
10175         int width = plane_state->base.crtc_w;
10176
10177         /*
10178          * 845g/865g are only limited by the width of their cursors,
10179          * the height is arbitrary up to the precision of the register.
10180          */
10181         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10182 }
10183
10184 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10185                              struct intel_plane_state *plane_state)
10186 {
10187         const struct drm_framebuffer *fb = plane_state->base.fb;
10188         int ret;
10189
10190         ret = intel_check_cursor(crtc_state, plane_state);
10191         if (ret)
10192                 return ret;
10193
10194         /* if we want to turn off the cursor ignore width and height */
10195         if (!fb)
10196                 return 0;
10197
10198         /* Check for which cursor types we support */
10199         if (!i845_cursor_size_ok(plane_state)) {
10200                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10201                           plane_state->base.crtc_w,
10202                           plane_state->base.crtc_h);
10203                 return -EINVAL;
10204         }
10205
10206         WARN_ON(plane_state->base.visible &&
10207                 plane_state->color_plane[0].stride != fb->pitches[0]);
10208
10209         switch (fb->pitches[0]) {
10210         case 256:
10211         case 512:
10212         case 1024:
10213         case 2048:
10214                 break;
10215         default:
10216                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10217                               fb->pitches[0]);
10218                 return -EINVAL;
10219         }
10220
10221         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
10222
10223         return 0;
10224 }
10225
10226 static void i845_update_cursor(struct intel_plane *plane,
10227                                const struct intel_crtc_state *crtc_state,
10228                                const struct intel_plane_state *plane_state)
10229 {
10230         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10231         u32 cntl = 0, base = 0, pos = 0, size = 0;
10232         unsigned long irqflags;
10233
10234         if (plane_state && plane_state->base.visible) {
10235                 unsigned int width = plane_state->base.crtc_w;
10236                 unsigned int height = plane_state->base.crtc_h;
10237
10238                 cntl = plane_state->ctl |
10239                         i845_cursor_ctl_crtc(crtc_state);
10240
10241                 size = (height << 12) | width;
10242
10243                 base = intel_cursor_base(plane_state);
10244                 pos = intel_cursor_position(plane_state);
10245         }
10246
10247         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10248
10249         /* On these chipsets we can only modify the base/size/stride
10250          * whilst the cursor is disabled.
10251          */
10252         if (plane->cursor.base != base ||
10253             plane->cursor.size != size ||
10254             plane->cursor.cntl != cntl) {
10255                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
10256                 I915_WRITE_FW(CURBASE(PIPE_A), base);
10257                 I915_WRITE_FW(CURSIZE, size);
10258                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10259                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
10260
10261                 plane->cursor.base = base;
10262                 plane->cursor.size = size;
10263                 plane->cursor.cntl = cntl;
10264         } else {
10265                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10266         }
10267
10268         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10269 }
10270
10271 static void i845_disable_cursor(struct intel_plane *plane,
10272                                 const struct intel_crtc_state *crtc_state)
10273 {
10274         i845_update_cursor(plane, crtc_state, NULL);
10275 }
10276
10277 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
10278                                      enum pipe *pipe)
10279 {
10280         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10281         enum intel_display_power_domain power_domain;
10282         intel_wakeref_t wakeref;
10283         bool ret;
10284
10285         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
10286         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10287         if (!wakeref)
10288                 return false;
10289
10290         ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
10291
10292         *pipe = PIPE_A;
10293
10294         intel_display_power_put(dev_priv, power_domain, wakeref);
10295
10296         return ret;
10297 }
10298
10299 static unsigned int
10300 i9xx_cursor_max_stride(struct intel_plane *plane,
10301                        u32 pixel_format, u64 modifier,
10302                        unsigned int rotation)
10303 {
10304         return plane->base.dev->mode_config.cursor_width * 4;
10305 }
10306
10307 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10308 {
10309         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
10310         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10311         u32 cntl = 0;
10312
10313         if (INTEL_GEN(dev_priv) >= 11)
10314                 return cntl;
10315
10316         if (crtc_state->gamma_enable)
10317                 cntl = MCURSOR_GAMMA_ENABLE;
10318
10319         if (crtc_state->csc_enable)
10320                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
10321
10322         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10323                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
10324
10325         return cntl;
10326 }
10327
10328 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
10329                            const struct intel_plane_state *plane_state)
10330 {
10331         struct drm_i915_private *dev_priv =
10332                 to_i915(plane_state->base.plane->dev);
10333         u32 cntl = 0;
10334
10335         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
10336                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
10337
10338         switch (plane_state->base.crtc_w) {
10339         case 64:
10340                 cntl |= MCURSOR_MODE_64_ARGB_AX;
10341                 break;
10342         case 128:
10343                 cntl |= MCURSOR_MODE_128_ARGB_AX;
10344                 break;
10345         case 256:
10346                 cntl |= MCURSOR_MODE_256_ARGB_AX;
10347                 break;
10348         default:
10349                 MISSING_CASE(plane_state->base.crtc_w);
10350                 return 0;
10351         }
10352
10353         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
10354                 cntl |= MCURSOR_ROTATE_180;
10355
10356         return cntl;
10357 }
10358
10359 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
10360 {
10361         struct drm_i915_private *dev_priv =
10362                 to_i915(plane_state->base.plane->dev);
10363         int width = plane_state->base.crtc_w;
10364         int height = plane_state->base.crtc_h;
10365
10366         if (!intel_cursor_size_ok(plane_state))
10367                 return false;
10368
10369         /* Cursor width is limited to a few power-of-two sizes */
10370         switch (width) {
10371         case 256:
10372         case 128:
10373         case 64:
10374                 break;
10375         default:
10376                 return false;
10377         }
10378
10379         /*
10380          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
10381          * height from 8 lines up to the cursor width, when the
10382          * cursor is not rotated. Everything else requires square
10383          * cursors.
10384          */
10385         if (HAS_CUR_FBC(dev_priv) &&
10386             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
10387                 if (height < 8 || height > width)
10388                         return false;
10389         } else {
10390                 if (height != width)
10391                         return false;
10392         }
10393
10394         return true;
10395 }
10396
10397 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
10398                              struct intel_plane_state *plane_state)
10399 {
10400         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
10401         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10402         const struct drm_framebuffer *fb = plane_state->base.fb;
10403         enum pipe pipe = plane->pipe;
10404         int ret;
10405
10406         ret = intel_check_cursor(crtc_state, plane_state);
10407         if (ret)
10408                 return ret;
10409
10410         /* if we want to turn off the cursor ignore width and height */
10411         if (!fb)
10412                 return 0;
10413
10414         /* Check for which cursor types we support */
10415         if (!i9xx_cursor_size_ok(plane_state)) {
10416                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10417                           plane_state->base.crtc_w,
10418                           plane_state->base.crtc_h);
10419                 return -EINVAL;
10420         }
10421
10422         WARN_ON(plane_state->base.visible &&
10423                 plane_state->color_plane[0].stride != fb->pitches[0]);
10424
10425         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
10426                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
10427                               fb->pitches[0], plane_state->base.crtc_w);
10428                 return -EINVAL;
10429         }
10430
10431         /*
10432          * There's something wrong with the cursor on CHV pipe C.
10433          * If it straddles the left edge of the screen then
10434          * moving it away from the edge or disabling it often
10435          * results in a pipe underrun, and often that can lead to
10436          * dead pipe (constant underrun reported, and it scans
10437          * out just a solid color). To recover from that, the
10438          * display power well must be turned off and on again.
10439          * Refuse the put the cursor into that compromised position.
10440          */
10441         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
10442             plane_state->base.visible && plane_state->base.crtc_x < 0) {
10443                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
10444                 return -EINVAL;
10445         }
10446
10447         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
10448
10449         return 0;
10450 }
10451
10452 static void i9xx_update_cursor(struct intel_plane *plane,
10453                                const struct intel_crtc_state *crtc_state,
10454                                const struct intel_plane_state *plane_state)
10455 {
10456         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10457         enum pipe pipe = plane->pipe;
10458         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
10459         unsigned long irqflags;
10460
10461         if (plane_state && plane_state->base.visible) {
10462                 cntl = plane_state->ctl |
10463                         i9xx_cursor_ctl_crtc(crtc_state);
10464
10465                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
10466                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
10467
10468                 base = intel_cursor_base(plane_state);
10469                 pos = intel_cursor_position(plane_state);
10470         }
10471
10472         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10473
10474         /*
10475          * On some platforms writing CURCNTR first will also
10476          * cause CURPOS to be armed by the CURBASE write.
10477          * Without the CURCNTR write the CURPOS write would
10478          * arm itself. Thus we always update CURCNTR before
10479          * CURPOS.
10480          *
10481          * On other platforms CURPOS always requires the
10482          * CURBASE write to arm the update. Additonally
10483          * a write to any of the cursor register will cancel
10484          * an already armed cursor update. Thus leaving out
10485          * the CURBASE write after CURPOS could lead to a
10486          * cursor that doesn't appear to move, or even change
10487          * shape. Thus we always write CURBASE.
10488          *
10489          * The other registers are armed by by the CURBASE write
10490          * except when the plane is getting enabled at which time
10491          * the CURCNTR write arms the update.
10492          */
10493
10494         if (INTEL_GEN(dev_priv) >= 9)
10495                 skl_write_cursor_wm(plane, crtc_state);
10496
10497         if (plane->cursor.base != base ||
10498             plane->cursor.size != fbc_ctl ||
10499             plane->cursor.cntl != cntl) {
10500                 if (HAS_CUR_FBC(dev_priv))
10501                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
10502                 I915_WRITE_FW(CURCNTR(pipe), cntl);
10503                 I915_WRITE_FW(CURPOS(pipe), pos);
10504                 I915_WRITE_FW(CURBASE(pipe), base);
10505
10506                 plane->cursor.base = base;
10507                 plane->cursor.size = fbc_ctl;
10508                 plane->cursor.cntl = cntl;
10509         } else {
10510                 I915_WRITE_FW(CURPOS(pipe), pos);
10511                 I915_WRITE_FW(CURBASE(pipe), base);
10512         }
10513
10514         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10515 }
10516
10517 static void i9xx_disable_cursor(struct intel_plane *plane,
10518                                 const struct intel_crtc_state *crtc_state)
10519 {
10520         i9xx_update_cursor(plane, crtc_state, NULL);
10521 }
10522
10523 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
10524                                      enum pipe *pipe)
10525 {
10526         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10527         enum intel_display_power_domain power_domain;
10528         intel_wakeref_t wakeref;
10529         bool ret;
10530         u32 val;
10531
10532         /*
10533          * Not 100% correct for planes that can move between pipes,
10534          * but that's only the case for gen2-3 which don't have any
10535          * display power wells.
10536          */
10537         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
10538         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10539         if (!wakeref)
10540                 return false;
10541
10542         val = I915_READ(CURCNTR(plane->pipe));
10543
10544         ret = val & MCURSOR_MODE;
10545
10546         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10547                 *pipe = plane->pipe;
10548         else
10549                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
10550                         MCURSOR_PIPE_SELECT_SHIFT;
10551
10552         intel_display_power_put(dev_priv, power_domain, wakeref);
10553
10554         return ret;
10555 }
10556
10557 /* VESA 640x480x72Hz mode to set on the pipe */
10558 static const struct drm_display_mode load_detect_mode = {
10559         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10560                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10561 };
10562
10563 struct drm_framebuffer *
10564 intel_framebuffer_create(struct drm_i915_gem_object *obj,
10565                          struct drm_mode_fb_cmd2 *mode_cmd)
10566 {
10567         struct intel_framebuffer *intel_fb;
10568         int ret;
10569
10570         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10571         if (!intel_fb)
10572                 return ERR_PTR(-ENOMEM);
10573
10574         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
10575         if (ret)
10576                 goto err;
10577
10578         return &intel_fb->base;
10579
10580 err:
10581         kfree(intel_fb);
10582         return ERR_PTR(ret);
10583 }
10584
10585 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
10586                                         struct drm_crtc *crtc)
10587 {
10588         struct drm_plane *plane;
10589         struct drm_plane_state *plane_state;
10590         int ret, i;
10591
10592         ret = drm_atomic_add_affected_planes(state, crtc);
10593         if (ret)
10594                 return ret;
10595
10596         for_each_new_plane_in_state(state, plane, plane_state, i) {
10597                 if (plane_state->crtc != crtc)
10598                         continue;
10599
10600                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
10601                 if (ret)
10602                         return ret;
10603
10604                 drm_atomic_set_fb_for_plane(plane_state, NULL);
10605         }
10606
10607         return 0;
10608 }
10609
10610 int intel_get_load_detect_pipe(struct drm_connector *connector,
10611                                const struct drm_display_mode *mode,
10612                                struct intel_load_detect_pipe *old,
10613                                struct drm_modeset_acquire_ctx *ctx)
10614 {
10615         struct intel_crtc *intel_crtc;
10616         struct intel_encoder *intel_encoder =
10617                 intel_attached_encoder(connector);
10618         struct drm_crtc *possible_crtc;
10619         struct drm_encoder *encoder = &intel_encoder->base;
10620         struct drm_crtc *crtc = NULL;
10621         struct drm_device *dev = encoder->dev;
10622         struct drm_i915_private *dev_priv = to_i915(dev);
10623         struct drm_mode_config *config = &dev->mode_config;
10624         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10625         struct drm_connector_state *connector_state;
10626         struct intel_crtc_state *crtc_state;
10627         int ret, i = -1;
10628
10629         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10630                       connector->base.id, connector->name,
10631                       encoder->base.id, encoder->name);
10632
10633         old->restore_state = NULL;
10634
10635         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
10636
10637         /*
10638          * Algorithm gets a little messy:
10639          *
10640          *   - if the connector already has an assigned crtc, use it (but make
10641          *     sure it's on first)
10642          *
10643          *   - try to find the first unused crtc that can drive this connector,
10644          *     and use that if we find one
10645          */
10646
10647         /* See if we already have a CRTC for this connector */
10648         if (connector->state->crtc) {
10649                 crtc = connector->state->crtc;
10650
10651                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10652                 if (ret)
10653                         goto fail;
10654
10655                 /* Make sure the crtc and connector are running */
10656                 goto found;
10657         }
10658
10659         /* Find an unused one (if possible) */
10660         for_each_crtc(dev, possible_crtc) {
10661                 i++;
10662                 if (!(encoder->possible_crtcs & (1 << i)))
10663                         continue;
10664
10665                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10666                 if (ret)
10667                         goto fail;
10668
10669                 if (possible_crtc->state->enable) {
10670                         drm_modeset_unlock(&possible_crtc->mutex);
10671                         continue;
10672                 }
10673
10674                 crtc = possible_crtc;
10675                 break;
10676         }
10677
10678         /*
10679          * If we didn't find an unused CRTC, don't use any.
10680          */
10681         if (!crtc) {
10682                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10683                 ret = -ENODEV;
10684                 goto fail;
10685         }
10686
10687 found:
10688         intel_crtc = to_intel_crtc(crtc);
10689
10690         state = drm_atomic_state_alloc(dev);
10691         restore_state = drm_atomic_state_alloc(dev);
10692         if (!state || !restore_state) {
10693                 ret = -ENOMEM;
10694                 goto fail;
10695         }
10696
10697         state->acquire_ctx = ctx;
10698         restore_state->acquire_ctx = ctx;
10699
10700         connector_state = drm_atomic_get_connector_state(state, connector);
10701         if (IS_ERR(connector_state)) {
10702                 ret = PTR_ERR(connector_state);
10703                 goto fail;
10704         }
10705
10706         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10707         if (ret)
10708                 goto fail;
10709
10710         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10711         if (IS_ERR(crtc_state)) {
10712                 ret = PTR_ERR(crtc_state);
10713                 goto fail;
10714         }
10715
10716         crtc_state->base.active = crtc_state->base.enable = true;
10717
10718         if (!mode)
10719                 mode = &load_detect_mode;
10720
10721         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10722         if (ret)
10723                 goto fail;
10724
10725         ret = intel_modeset_disable_planes(state, crtc);
10726         if (ret)
10727                 goto fail;
10728
10729         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10730         if (!ret)
10731                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10732         if (!ret)
10733                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
10734         if (ret) {
10735                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10736                 goto fail;
10737         }
10738
10739         ret = drm_atomic_commit(state);
10740         if (ret) {
10741                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10742                 goto fail;
10743         }
10744
10745         old->restore_state = restore_state;
10746         drm_atomic_state_put(state);
10747
10748         /* let the connector get through one full cycle before testing */
10749         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10750         return true;
10751
10752 fail:
10753         if (state) {
10754                 drm_atomic_state_put(state);
10755                 state = NULL;
10756         }
10757         if (restore_state) {
10758                 drm_atomic_state_put(restore_state);
10759                 restore_state = NULL;
10760         }
10761
10762         if (ret == -EDEADLK)
10763                 return ret;
10764
10765         return false;
10766 }
10767
10768 void intel_release_load_detect_pipe(struct drm_connector *connector,
10769                                     struct intel_load_detect_pipe *old,
10770                                     struct drm_modeset_acquire_ctx *ctx)
10771 {
10772         struct intel_encoder *intel_encoder =
10773                 intel_attached_encoder(connector);
10774         struct drm_encoder *encoder = &intel_encoder->base;
10775         struct drm_atomic_state *state = old->restore_state;
10776         int ret;
10777
10778         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10779                       connector->base.id, connector->name,
10780                       encoder->base.id, encoder->name);
10781
10782         if (!state)
10783                 return;
10784
10785         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10786         if (ret)
10787                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10788         drm_atomic_state_put(state);
10789 }
10790
10791 static int i9xx_pll_refclk(struct drm_device *dev,
10792                            const struct intel_crtc_state *pipe_config)
10793 {
10794         struct drm_i915_private *dev_priv = to_i915(dev);
10795         u32 dpll = pipe_config->dpll_hw_state.dpll;
10796
10797         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10798                 return dev_priv->vbt.lvds_ssc_freq;
10799         else if (HAS_PCH_SPLIT(dev_priv))
10800                 return 120000;
10801         else if (!IS_GEN(dev_priv, 2))
10802                 return 96000;
10803         else
10804                 return 48000;
10805 }
10806
10807 /* Returns the clock of the currently programmed mode of the given pipe. */
10808 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10809                                 struct intel_crtc_state *pipe_config)
10810 {
10811         struct drm_device *dev = crtc->base.dev;
10812         struct drm_i915_private *dev_priv = to_i915(dev);
10813         int pipe = pipe_config->cpu_transcoder;
10814         u32 dpll = pipe_config->dpll_hw_state.dpll;
10815         u32 fp;
10816         struct dpll clock;
10817         int port_clock;
10818         int refclk = i9xx_pll_refclk(dev, pipe_config);
10819
10820         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10821                 fp = pipe_config->dpll_hw_state.fp0;
10822         else
10823                 fp = pipe_config->dpll_hw_state.fp1;
10824
10825         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10826         if (IS_PINEVIEW(dev_priv)) {
10827                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10828                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10829         } else {
10830                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10831                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10832         }
10833
10834         if (!IS_GEN(dev_priv, 2)) {
10835                 if (IS_PINEVIEW(dev_priv))
10836                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10837                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10838                 else
10839                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10840                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10841
10842                 switch (dpll & DPLL_MODE_MASK) {
10843                 case DPLLB_MODE_DAC_SERIAL:
10844                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10845                                 5 : 10;
10846                         break;
10847                 case DPLLB_MODE_LVDS:
10848                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10849                                 7 : 14;
10850                         break;
10851                 default:
10852                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10853                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10854                         return;
10855                 }
10856
10857                 if (IS_PINEVIEW(dev_priv))
10858                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10859                 else
10860                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10861         } else {
10862                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10863                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10864
10865                 if (is_lvds) {
10866                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10867                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10868
10869                         if (lvds & LVDS_CLKB_POWER_UP)
10870                                 clock.p2 = 7;
10871                         else
10872                                 clock.p2 = 14;
10873                 } else {
10874                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10875                                 clock.p1 = 2;
10876                         else {
10877                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10878                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10879                         }
10880                         if (dpll & PLL_P2_DIVIDE_BY_4)
10881                                 clock.p2 = 4;
10882                         else
10883                                 clock.p2 = 2;
10884                 }
10885
10886                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10887         }
10888
10889         /*
10890          * This value includes pixel_multiplier. We will use
10891          * port_clock to compute adjusted_mode.crtc_clock in the
10892          * encoder's get_config() function.
10893          */
10894         pipe_config->port_clock = port_clock;
10895 }
10896
10897 int intel_dotclock_calculate(int link_freq,
10898                              const struct intel_link_m_n *m_n)
10899 {
10900         /*
10901          * The calculation for the data clock is:
10902          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10903          * But we want to avoid losing precison if possible, so:
10904          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10905          *
10906          * and the link clock is simpler:
10907          * link_clock = (m * link_clock) / n
10908          */
10909
10910         if (!m_n->link_n)
10911                 return 0;
10912
10913         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10914 }
10915
10916 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10917                                    struct intel_crtc_state *pipe_config)
10918 {
10919         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10920
10921         /* read out port_clock from the DPLL */
10922         i9xx_crtc_clock_get(crtc, pipe_config);
10923
10924         /*
10925          * In case there is an active pipe without active ports,
10926          * we may need some idea for the dotclock anyway.
10927          * Calculate one based on the FDI configuration.
10928          */
10929         pipe_config->base.adjusted_mode.crtc_clock =
10930                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10931                                          &pipe_config->fdi_m_n);
10932 }
10933
10934 /* Returns the currently programmed mode of the given encoder. */
10935 struct drm_display_mode *
10936 intel_encoder_current_mode(struct intel_encoder *encoder)
10937 {
10938         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10939         struct intel_crtc_state *crtc_state;
10940         struct drm_display_mode *mode;
10941         struct intel_crtc *crtc;
10942         enum pipe pipe;
10943
10944         if (!encoder->get_hw_state(encoder, &pipe))
10945                 return NULL;
10946
10947         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10948
10949         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10950         if (!mode)
10951                 return NULL;
10952
10953         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10954         if (!crtc_state) {
10955                 kfree(mode);
10956                 return NULL;
10957         }
10958
10959         crtc_state->base.crtc = &crtc->base;
10960
10961         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10962                 kfree(crtc_state);
10963                 kfree(mode);
10964                 return NULL;
10965         }
10966
10967         encoder->get_config(encoder, crtc_state);
10968
10969         intel_mode_from_pipe_config(mode, crtc_state);
10970
10971         kfree(crtc_state);
10972
10973         return mode;
10974 }
10975
10976 static void intel_crtc_destroy(struct drm_crtc *crtc)
10977 {
10978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10979
10980         drm_crtc_cleanup(crtc);
10981         kfree(intel_crtc);
10982 }
10983
10984 /**
10985  * intel_wm_need_update - Check whether watermarks need updating
10986  * @cur: current plane state
10987  * @new: new plane state
10988  *
10989  * Check current plane state versus the new one to determine whether
10990  * watermarks need to be recalculated.
10991  *
10992  * Returns true or false.
10993  */
10994 static bool intel_wm_need_update(struct intel_plane_state *cur,
10995                                  struct intel_plane_state *new)
10996 {
10997         /* Update watermarks on tiling or size changes. */
10998         if (new->base.visible != cur->base.visible)
10999                 return true;
11000
11001         if (!cur->base.fb || !new->base.fb)
11002                 return false;
11003
11004         if (cur->base.fb->modifier != new->base.fb->modifier ||
11005             cur->base.rotation != new->base.rotation ||
11006             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
11007             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
11008             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
11009             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
11010                 return true;
11011
11012         return false;
11013 }
11014
11015 static bool needs_scaling(const struct intel_plane_state *state)
11016 {
11017         int src_w = drm_rect_width(&state->base.src) >> 16;
11018         int src_h = drm_rect_height(&state->base.src) >> 16;
11019         int dst_w = drm_rect_width(&state->base.dst);
11020         int dst_h = drm_rect_height(&state->base.dst);
11021
11022         return (src_w != dst_w || src_h != dst_h);
11023 }
11024
11025 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11026                                     struct drm_crtc_state *crtc_state,
11027                                     const struct intel_plane_state *old_plane_state,
11028                                     struct drm_plane_state *plane_state)
11029 {
11030         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11031         struct drm_crtc *crtc = crtc_state->crtc;
11032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11033         struct intel_plane *plane = to_intel_plane(plane_state->plane);
11034         struct drm_device *dev = crtc->dev;
11035         struct drm_i915_private *dev_priv = to_i915(dev);
11036         bool mode_changed = needs_modeset(crtc_state);
11037         bool was_crtc_enabled = old_crtc_state->base.active;
11038         bool is_crtc_enabled = crtc_state->active;
11039         bool turn_off, turn_on, visible, was_visible;
11040         struct drm_framebuffer *fb = plane_state->fb;
11041         int ret;
11042
11043         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11044                 ret = skl_update_scaler_plane(
11045                         to_intel_crtc_state(crtc_state),
11046                         to_intel_plane_state(plane_state));
11047                 if (ret)
11048                         return ret;
11049         }
11050
11051         was_visible = old_plane_state->base.visible;
11052         visible = plane_state->visible;
11053
11054         if (!was_crtc_enabled && WARN_ON(was_visible))
11055                 was_visible = false;
11056
11057         /*
11058          * Visibility is calculated as if the crtc was on, but
11059          * after scaler setup everything depends on it being off
11060          * when the crtc isn't active.
11061          *
11062          * FIXME this is wrong for watermarks. Watermarks should also
11063          * be computed as if the pipe would be active. Perhaps move
11064          * per-plane wm computation to the .check_plane() hook, and
11065          * only combine the results from all planes in the current place?
11066          */
11067         if (!is_crtc_enabled) {
11068                 plane_state->visible = visible = false;
11069                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
11070         }
11071
11072         if (!was_visible && !visible)
11073                 return 0;
11074
11075         if (fb != old_plane_state->base.fb)
11076                 pipe_config->fb_changed = true;
11077
11078         turn_off = was_visible && (!visible || mode_changed);
11079         turn_on = visible && (!was_visible || mode_changed);
11080
11081         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11082                          intel_crtc->base.base.id, intel_crtc->base.name,
11083                          plane->base.base.id, plane->base.name,
11084                          fb ? fb->base.id : -1);
11085
11086         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11087                          plane->base.base.id, plane->base.name,
11088                          was_visible, visible,
11089                          turn_off, turn_on, mode_changed);
11090
11091         if (turn_on) {
11092                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11093                         pipe_config->update_wm_pre = true;
11094
11095                 /* must disable cxsr around plane enable/disable */
11096                 if (plane->id != PLANE_CURSOR)
11097                         pipe_config->disable_cxsr = true;
11098         } else if (turn_off) {
11099                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11100                         pipe_config->update_wm_post = true;
11101
11102                 /* must disable cxsr around plane enable/disable */
11103                 if (plane->id != PLANE_CURSOR)
11104                         pipe_config->disable_cxsr = true;
11105         } else if (intel_wm_need_update(to_intel_plane_state(plane->base.state),
11106                                         to_intel_plane_state(plane_state))) {
11107                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11108                         /* FIXME bollocks */
11109                         pipe_config->update_wm_pre = true;
11110                         pipe_config->update_wm_post = true;
11111                 }
11112         }
11113
11114         if (visible || was_visible)
11115                 pipe_config->fb_bits |= plane->frontbuffer_bit;
11116
11117         /*
11118          * ILK/SNB DVSACNTR/Sprite Enable
11119          * IVB SPR_CTL/Sprite Enable
11120          * "When in Self Refresh Big FIFO mode, a write to enable the
11121          *  plane will be internally buffered and delayed while Big FIFO
11122          *  mode is exiting."
11123          *
11124          * Which means that enabling the sprite can take an extra frame
11125          * when we start in big FIFO mode (LP1+). Thus we need to drop
11126          * down to LP0 and wait for vblank in order to make sure the
11127          * sprite gets enabled on the next vblank after the register write.
11128          * Doing otherwise would risk enabling the sprite one frame after
11129          * we've already signalled flip completion. We can resume LP1+
11130          * once the sprite has been enabled.
11131          *
11132          *
11133          * WaCxSRDisabledForSpriteScaling:ivb
11134          * IVB SPR_SCALE/Scaling Enable
11135          * "Low Power watermarks must be disabled for at least one
11136          *  frame before enabling sprite scaling, and kept disabled
11137          *  until sprite scaling is disabled."
11138          *
11139          * ILK/SNB DVSASCALE/Scaling Enable
11140          * "When in Self Refresh Big FIFO mode, scaling enable will be
11141          *  masked off while Big FIFO mode is exiting."
11142          *
11143          * Despite the w/a only being listed for IVB we assume that
11144          * the ILK/SNB note has similar ramifications, hence we apply
11145          * the w/a on all three platforms.
11146          *
11147          * With experimental results seems this is needed also for primary
11148          * plane, not only sprite plane.
11149          */
11150         if (plane->id != PLANE_CURSOR &&
11151             (IS_GEN_RANGE(dev_priv, 5, 6) ||
11152              IS_IVYBRIDGE(dev_priv)) &&
11153             (turn_on || (!needs_scaling(old_plane_state) &&
11154                          needs_scaling(to_intel_plane_state(plane_state)))))
11155                 pipe_config->disable_lp_wm = true;
11156
11157         return 0;
11158 }
11159
11160 static bool encoders_cloneable(const struct intel_encoder *a,
11161                                const struct intel_encoder *b)
11162 {
11163         /* masks could be asymmetric, so check both ways */
11164         return a == b || (a->cloneable & (1 << b->type) &&
11165                           b->cloneable & (1 << a->type));
11166 }
11167
11168 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11169                                          struct intel_crtc *crtc,
11170                                          struct intel_encoder *encoder)
11171 {
11172         struct intel_encoder *source_encoder;
11173         struct drm_connector *connector;
11174         struct drm_connector_state *connector_state;
11175         int i;
11176
11177         for_each_new_connector_in_state(state, connector, connector_state, i) {
11178                 if (connector_state->crtc != &crtc->base)
11179                         continue;
11180
11181                 source_encoder =
11182                         to_intel_encoder(connector_state->best_encoder);
11183                 if (!encoders_cloneable(encoder, source_encoder))
11184                         return false;
11185         }
11186
11187         return true;
11188 }
11189
11190 static int icl_add_linked_planes(struct intel_atomic_state *state)
11191 {
11192         struct intel_plane *plane, *linked;
11193         struct intel_plane_state *plane_state, *linked_plane_state;
11194         int i;
11195
11196         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11197                 linked = plane_state->linked_plane;
11198
11199                 if (!linked)
11200                         continue;
11201
11202                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11203                 if (IS_ERR(linked_plane_state))
11204                         return PTR_ERR(linked_plane_state);
11205
11206                 WARN_ON(linked_plane_state->linked_plane != plane);
11207                 WARN_ON(linked_plane_state->slave == plane_state->slave);
11208         }
11209
11210         return 0;
11211 }
11212
11213 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
11214 {
11215         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
11216         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11217         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
11218         struct intel_plane *plane, *linked;
11219         struct intel_plane_state *plane_state;
11220         int i;
11221
11222         if (INTEL_GEN(dev_priv) < 11)
11223                 return 0;
11224
11225         /*
11226          * Destroy all old plane links and make the slave plane invisible
11227          * in the crtc_state->active_planes mask.
11228          */
11229         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11230                 if (plane->pipe != crtc->pipe || !plane_state->linked_plane)
11231                         continue;
11232
11233                 plane_state->linked_plane = NULL;
11234                 if (plane_state->slave && !plane_state->base.visible) {
11235                         crtc_state->active_planes &= ~BIT(plane->id);
11236                         crtc_state->update_planes |= BIT(plane->id);
11237                 }
11238
11239                 plane_state->slave = false;
11240         }
11241
11242         if (!crtc_state->nv12_planes)
11243                 return 0;
11244
11245         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11246                 struct intel_plane_state *linked_state = NULL;
11247
11248                 if (plane->pipe != crtc->pipe ||
11249                     !(crtc_state->nv12_planes & BIT(plane->id)))
11250                         continue;
11251
11252                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
11253                         if (!icl_is_nv12_y_plane(linked->id))
11254                                 continue;
11255
11256                         if (crtc_state->active_planes & BIT(linked->id))
11257                                 continue;
11258
11259                         linked_state = intel_atomic_get_plane_state(state, linked);
11260                         if (IS_ERR(linked_state))
11261                                 return PTR_ERR(linked_state);
11262
11263                         break;
11264                 }
11265
11266                 if (!linked_state) {
11267                         DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
11268                                       hweight8(crtc_state->nv12_planes));
11269
11270                         return -EINVAL;
11271                 }
11272
11273                 plane_state->linked_plane = linked;
11274
11275                 linked_state->slave = true;
11276                 linked_state->linked_plane = plane;
11277                 crtc_state->active_planes |= BIT(linked->id);
11278                 crtc_state->update_planes |= BIT(linked->id);
11279                 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
11280         }
11281
11282         return 0;
11283 }
11284
11285 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11286                                    struct drm_crtc_state *crtc_state)
11287 {
11288         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11290         struct intel_crtc_state *pipe_config =
11291                 to_intel_crtc_state(crtc_state);
11292         int ret;
11293         bool mode_changed = needs_modeset(crtc_state);
11294
11295         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
11296             mode_changed && !crtc_state->active)
11297                 pipe_config->update_wm_post = true;
11298
11299         if (mode_changed && crtc_state->enable &&
11300             dev_priv->display.crtc_compute_clock &&
11301             !WARN_ON(pipe_config->shared_dpll)) {
11302                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11303                                                            pipe_config);
11304                 if (ret)
11305                         return ret;
11306         }
11307
11308         if (mode_changed || pipe_config->update_pipe ||
11309             crtc_state->color_mgmt_changed) {
11310                 ret = intel_color_check(pipe_config);
11311                 if (ret)
11312                         return ret;
11313         }
11314
11315         ret = 0;
11316         if (dev_priv->display.compute_pipe_wm) {
11317                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11318                 if (ret) {
11319                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11320                         return ret;
11321                 }
11322         }
11323
11324         if (dev_priv->display.compute_intermediate_wm) {
11325                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11326                         return 0;
11327
11328                 /*
11329                  * Calculate 'intermediate' watermarks that satisfy both the
11330                  * old state and the new state.  We can program these
11331                  * immediately.
11332                  */
11333                 ret = dev_priv->display.compute_intermediate_wm(pipe_config);
11334                 if (ret) {
11335                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11336                         return ret;
11337                 }
11338         }
11339
11340         if (INTEL_GEN(dev_priv) >= 9) {
11341                 if (mode_changed || pipe_config->update_pipe)
11342                         ret = skl_update_scaler_crtc(pipe_config);
11343
11344                 if (!ret)
11345                         ret = icl_check_nv12_planes(pipe_config);
11346                 if (!ret)
11347                         ret = skl_check_pipe_max_pixel_rate(intel_crtc,
11348                                                             pipe_config);
11349                 if (!ret)
11350                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11351                                                          pipe_config);
11352         }
11353
11354         if (HAS_IPS(dev_priv))
11355                 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
11356
11357         return ret;
11358 }
11359
11360 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11361         .atomic_check = intel_crtc_atomic_check,
11362 };
11363
11364 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11365 {
11366         struct intel_connector *connector;
11367         struct drm_connector_list_iter conn_iter;
11368
11369         drm_connector_list_iter_begin(dev, &conn_iter);
11370         for_each_intel_connector_iter(connector, &conn_iter) {
11371                 if (connector->base.state->crtc)
11372                         drm_connector_put(&connector->base);
11373
11374                 if (connector->base.encoder) {
11375                         connector->base.state->best_encoder =
11376                                 connector->base.encoder;
11377                         connector->base.state->crtc =
11378                                 connector->base.encoder->crtc;
11379
11380                         drm_connector_get(&connector->base);
11381                 } else {
11382                         connector->base.state->best_encoder = NULL;
11383                         connector->base.state->crtc = NULL;
11384                 }
11385         }
11386         drm_connector_list_iter_end(&conn_iter);
11387 }
11388
11389 static int
11390 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
11391                       struct intel_crtc_state *pipe_config)
11392 {
11393         struct drm_connector *connector = conn_state->connector;
11394         const struct drm_display_info *info = &connector->display_info;
11395         int bpp;
11396
11397         switch (conn_state->max_bpc) {
11398         case 6 ... 7:
11399                 bpp = 6 * 3;
11400                 break;
11401         case 8 ... 9:
11402                 bpp = 8 * 3;
11403                 break;
11404         case 10 ... 11:
11405                 bpp = 10 * 3;
11406                 break;
11407         case 12:
11408                 bpp = 12 * 3;
11409                 break;
11410         default:
11411                 return -EINVAL;
11412         }
11413
11414         if (bpp < pipe_config->pipe_bpp) {
11415                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
11416                               "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
11417                               connector->base.id, connector->name,
11418                               bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
11419                               pipe_config->pipe_bpp);
11420
11421                 pipe_config->pipe_bpp = bpp;
11422         }
11423
11424         return 0;
11425 }
11426
11427 static int
11428 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11429                           struct intel_crtc_state *pipe_config)
11430 {
11431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11432         struct drm_atomic_state *state = pipe_config->base.state;
11433         struct drm_connector *connector;
11434         struct drm_connector_state *connector_state;
11435         int bpp, i;
11436
11437         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11438             IS_CHERRYVIEW(dev_priv)))
11439                 bpp = 10*3;
11440         else if (INTEL_GEN(dev_priv) >= 5)
11441                 bpp = 12*3;
11442         else
11443                 bpp = 8*3;
11444
11445         pipe_config->pipe_bpp = bpp;
11446
11447         /* Clamp display bpp to connector max bpp */
11448         for_each_new_connector_in_state(state, connector, connector_state, i) {
11449                 int ret;
11450
11451                 if (connector_state->crtc != &crtc->base)
11452                         continue;
11453
11454                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
11455                 if (ret)
11456                         return ret;
11457         }
11458
11459         return 0;
11460 }
11461
11462 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11463 {
11464         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11465                         "type: 0x%x flags: 0x%x\n",
11466                 mode->crtc_clock,
11467                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11468                 mode->crtc_hsync_end, mode->crtc_htotal,
11469                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11470                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11471 }
11472
11473 static inline void
11474 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11475                       unsigned int lane_count, struct intel_link_m_n *m_n)
11476 {
11477         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11478                       id, lane_count,
11479                       m_n->gmch_m, m_n->gmch_n,
11480                       m_n->link_m, m_n->link_n, m_n->tu);
11481 }
11482
11483 static void
11484 intel_dump_infoframe(struct drm_i915_private *dev_priv,
11485                      const union hdmi_infoframe *frame)
11486 {
11487         if ((drm_debug & DRM_UT_KMS) == 0)
11488                 return;
11489
11490         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
11491 }
11492
11493 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
11494
11495 static const char * const output_type_str[] = {
11496         OUTPUT_TYPE(UNUSED),
11497         OUTPUT_TYPE(ANALOG),
11498         OUTPUT_TYPE(DVO),
11499         OUTPUT_TYPE(SDVO),
11500         OUTPUT_TYPE(LVDS),
11501         OUTPUT_TYPE(TVOUT),
11502         OUTPUT_TYPE(HDMI),
11503         OUTPUT_TYPE(DP),
11504         OUTPUT_TYPE(EDP),
11505         OUTPUT_TYPE(DSI),
11506         OUTPUT_TYPE(DDI),
11507         OUTPUT_TYPE(DP_MST),
11508 };
11509
11510 #undef OUTPUT_TYPE
11511
11512 static void snprintf_output_types(char *buf, size_t len,
11513                                   unsigned int output_types)
11514 {
11515         char *str = buf;
11516         int i;
11517
11518         str[0] = '\0';
11519
11520         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
11521                 int r;
11522
11523                 if ((output_types & BIT(i)) == 0)
11524                         continue;
11525
11526                 r = snprintf(str, len, "%s%s",
11527                              str != buf ? "," : "", output_type_str[i]);
11528                 if (r >= len)
11529                         break;
11530                 str += r;
11531                 len -= r;
11532
11533                 output_types &= ~BIT(i);
11534         }
11535
11536         WARN_ON_ONCE(output_types != 0);
11537 }
11538
11539 static const char * const output_format_str[] = {
11540         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
11541         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
11542         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
11543         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
11544 };
11545
11546 static const char *output_formats(enum intel_output_format format)
11547 {
11548         if (format >= ARRAY_SIZE(output_format_str))
11549                 format = INTEL_OUTPUT_FORMAT_INVALID;
11550         return output_format_str[format];
11551 }
11552
11553 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11554                                    struct intel_crtc_state *pipe_config,
11555                                    const char *context)
11556 {
11557         struct drm_device *dev = crtc->base.dev;
11558         struct drm_i915_private *dev_priv = to_i915(dev);
11559         struct drm_plane *plane;
11560         struct intel_plane *intel_plane;
11561         struct intel_plane_state *state;
11562         struct drm_framebuffer *fb;
11563         char buf[64];
11564
11565         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11566                       crtc->base.base.id, crtc->base.name, context);
11567
11568         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
11569         DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
11570                       buf, pipe_config->output_types);
11571
11572         DRM_DEBUG_KMS("output format: %s\n",
11573                       output_formats(pipe_config->output_format));
11574
11575         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11576                       transcoder_name(pipe_config->cpu_transcoder),
11577                       pipe_config->pipe_bpp, pipe_config->dither);
11578
11579         if (pipe_config->has_pch_encoder)
11580                 intel_dump_m_n_config(pipe_config, "fdi",
11581                                       pipe_config->fdi_lanes,
11582                                       &pipe_config->fdi_m_n);
11583
11584         if (intel_crtc_has_dp_encoder(pipe_config)) {
11585                 intel_dump_m_n_config(pipe_config, "dp m_n",
11586                                 pipe_config->lane_count, &pipe_config->dp_m_n);
11587                 if (pipe_config->has_drrs)
11588                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
11589                                               pipe_config->lane_count,
11590                                               &pipe_config->dp_m2_n2);
11591         }
11592
11593         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11594                       pipe_config->has_audio, pipe_config->has_infoframe);
11595
11596         DRM_DEBUG_KMS("infoframes enabled: 0x%x\n",
11597                       pipe_config->infoframes.enable);
11598
11599         if (pipe_config->infoframes.enable &
11600             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
11601                 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
11602         if (pipe_config->infoframes.enable &
11603             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
11604                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
11605         if (pipe_config->infoframes.enable &
11606             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
11607                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
11608         if (pipe_config->infoframes.enable &
11609             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
11610                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
11611
11612         DRM_DEBUG_KMS("requested mode:\n");
11613         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11614         DRM_DEBUG_KMS("adjusted mode:\n");
11615         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11616         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11617         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11618                       pipe_config->port_clock,
11619                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11620                       pipe_config->pixel_rate);
11621
11622         if (INTEL_GEN(dev_priv) >= 9)
11623                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11624                               crtc->num_scalers,
11625                               pipe_config->scaler_state.scaler_users,
11626                               pipe_config->scaler_state.scaler_id);
11627
11628         if (HAS_GMCH(dev_priv))
11629                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11630                               pipe_config->gmch_pfit.control,
11631                               pipe_config->gmch_pfit.pgm_ratios,
11632                               pipe_config->gmch_pfit.lvds_border_bits);
11633         else
11634                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11635                               pipe_config->pch_pfit.pos,
11636                               pipe_config->pch_pfit.size,
11637                               enableddisabled(pipe_config->pch_pfit.enabled));
11638
11639         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11640                       pipe_config->ips_enabled, pipe_config->double_wide);
11641
11642         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11643
11644         DRM_DEBUG_KMS("planes on this crtc\n");
11645         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11646                 struct drm_format_name_buf format_name;
11647                 intel_plane = to_intel_plane(plane);
11648                 if (intel_plane->pipe != crtc->pipe)
11649                         continue;
11650
11651                 state = to_intel_plane_state(plane->state);
11652                 fb = state->base.fb;
11653                 if (!fb) {
11654                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11655                                       plane->base.id, plane->name, state->scaler_id);
11656                         continue;
11657                 }
11658
11659                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11660                               plane->base.id, plane->name,
11661                               fb->base.id, fb->width, fb->height,
11662                               drm_get_format_name(fb->format->format, &format_name));
11663                 if (INTEL_GEN(dev_priv) >= 9)
11664                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11665                                       state->scaler_id,
11666                                       state->base.src.x1 >> 16,
11667                                       state->base.src.y1 >> 16,
11668                                       drm_rect_width(&state->base.src) >> 16,
11669                                       drm_rect_height(&state->base.src) >> 16,
11670                                       state->base.dst.x1, state->base.dst.y1,
11671                                       drm_rect_width(&state->base.dst),
11672                                       drm_rect_height(&state->base.dst));
11673         }
11674 }
11675
11676 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11677 {
11678         struct drm_device *dev = state->dev;
11679         struct drm_connector *connector;
11680         struct drm_connector_list_iter conn_iter;
11681         unsigned int used_ports = 0;
11682         unsigned int used_mst_ports = 0;
11683         bool ret = true;
11684
11685         /*
11686          * Walk the connector list instead of the encoder
11687          * list to detect the problem on ddi platforms
11688          * where there's just one encoder per digital port.
11689          */
11690         drm_connector_list_iter_begin(dev, &conn_iter);
11691         drm_for_each_connector_iter(connector, &conn_iter) {
11692                 struct drm_connector_state *connector_state;
11693                 struct intel_encoder *encoder;
11694
11695                 connector_state = drm_atomic_get_new_connector_state(state, connector);
11696                 if (!connector_state)
11697                         connector_state = connector->state;
11698
11699                 if (!connector_state->best_encoder)
11700                         continue;
11701
11702                 encoder = to_intel_encoder(connector_state->best_encoder);
11703
11704                 WARN_ON(!connector_state->crtc);
11705
11706                 switch (encoder->type) {
11707                         unsigned int port_mask;
11708                 case INTEL_OUTPUT_DDI:
11709                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
11710                                 break;
11711                         /* else: fall through */
11712                 case INTEL_OUTPUT_DP:
11713                 case INTEL_OUTPUT_HDMI:
11714                 case INTEL_OUTPUT_EDP:
11715                         port_mask = 1 << encoder->port;
11716
11717                         /* the same port mustn't appear more than once */
11718                         if (used_ports & port_mask)
11719                                 ret = false;
11720
11721                         used_ports |= port_mask;
11722                         break;
11723                 case INTEL_OUTPUT_DP_MST:
11724                         used_mst_ports |=
11725                                 1 << encoder->port;
11726                         break;
11727                 default:
11728                         break;
11729                 }
11730         }
11731         drm_connector_list_iter_end(&conn_iter);
11732
11733         /* can't mix MST and SST/HDMI on the same port */
11734         if (used_ports & used_mst_ports)
11735                 return false;
11736
11737         return ret;
11738 }
11739
11740 static int
11741 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11742 {
11743         struct drm_i915_private *dev_priv =
11744                 to_i915(crtc_state->base.crtc->dev);
11745         struct intel_crtc_state *saved_state;
11746
11747         saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
11748         if (!saved_state)
11749                 return -ENOMEM;
11750
11751         /* FIXME: before the switch to atomic started, a new pipe_config was
11752          * kzalloc'd. Code that depends on any field being zero should be
11753          * fixed, so that the crtc_state can be safely duplicated. For now,
11754          * only fields that are know to not cause problems are preserved. */
11755
11756         saved_state->scaler_state = crtc_state->scaler_state;
11757         saved_state->shared_dpll = crtc_state->shared_dpll;
11758         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
11759         saved_state->pch_pfit.force_thru = crtc_state->pch_pfit.force_thru;
11760         saved_state->crc_enabled = crtc_state->crc_enabled;
11761         if (IS_G4X(dev_priv) ||
11762             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11763                 saved_state->wm = crtc_state->wm;
11764
11765         /* Keep base drm_crtc_state intact, only clear our extended struct */
11766         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11767         memcpy(&crtc_state->base + 1, &saved_state->base + 1,
11768                sizeof(*crtc_state) - sizeof(crtc_state->base));
11769
11770         kfree(saved_state);
11771         return 0;
11772 }
11773
11774 static int
11775 intel_modeset_pipe_config(struct drm_crtc *crtc,
11776                           struct intel_crtc_state *pipe_config)
11777 {
11778         struct drm_atomic_state *state = pipe_config->base.state;
11779         struct intel_encoder *encoder;
11780         struct drm_connector *connector;
11781         struct drm_connector_state *connector_state;
11782         int base_bpp, ret;
11783         int i;
11784         bool retry = true;
11785
11786         ret = clear_intel_crtc_state(pipe_config);
11787         if (ret)
11788                 return ret;
11789
11790         pipe_config->cpu_transcoder =
11791                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11792
11793         /*
11794          * Sanitize sync polarity flags based on requested ones. If neither
11795          * positive or negative polarity is requested, treat this as meaning
11796          * negative polarity.
11797          */
11798         if (!(pipe_config->base.adjusted_mode.flags &
11799               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11800                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11801
11802         if (!(pipe_config->base.adjusted_mode.flags &
11803               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11804                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11805
11806         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11807                                         pipe_config);
11808         if (ret)
11809                 return ret;
11810
11811         base_bpp = pipe_config->pipe_bpp;
11812
11813         /*
11814          * Determine the real pipe dimensions. Note that stereo modes can
11815          * increase the actual pipe size due to the frame doubling and
11816          * insertion of additional space for blanks between the frame. This
11817          * is stored in the crtc timings. We use the requested mode to do this
11818          * computation to clearly distinguish it from the adjusted mode, which
11819          * can be changed by the connectors in the below retry loop.
11820          */
11821         drm_mode_get_hv_timing(&pipe_config->base.mode,
11822                                &pipe_config->pipe_src_w,
11823                                &pipe_config->pipe_src_h);
11824
11825         for_each_new_connector_in_state(state, connector, connector_state, i) {
11826                 if (connector_state->crtc != crtc)
11827                         continue;
11828
11829                 encoder = to_intel_encoder(connector_state->best_encoder);
11830
11831                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11832                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11833                         return -EINVAL;
11834                 }
11835
11836                 /*
11837                  * Determine output_types before calling the .compute_config()
11838                  * hooks so that the hooks can use this information safely.
11839                  */
11840                 if (encoder->compute_output_type)
11841                         pipe_config->output_types |=
11842                                 BIT(encoder->compute_output_type(encoder, pipe_config,
11843                                                                  connector_state));
11844                 else
11845                         pipe_config->output_types |= BIT(encoder->type);
11846         }
11847
11848 encoder_retry:
11849         /* Ensure the port clock defaults are reset when retrying. */
11850         pipe_config->port_clock = 0;
11851         pipe_config->pixel_multiplier = 1;
11852
11853         /* Fill in default crtc timings, allow encoders to overwrite them. */
11854         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11855                               CRTC_STEREO_DOUBLE);
11856
11857         /* Pass our mode to the connectors and the CRTC to give them a chance to
11858          * adjust it according to limitations or connector properties, and also
11859          * a chance to reject the mode entirely.
11860          */
11861         for_each_new_connector_in_state(state, connector, connector_state, i) {
11862                 if (connector_state->crtc != crtc)
11863                         continue;
11864
11865                 encoder = to_intel_encoder(connector_state->best_encoder);
11866                 ret = encoder->compute_config(encoder, pipe_config,
11867                                               connector_state);
11868                 if (ret < 0) {
11869                         if (ret != -EDEADLK)
11870                                 DRM_DEBUG_KMS("Encoder config failure: %d\n",
11871                                               ret);
11872                         return ret;
11873                 }
11874         }
11875
11876         /* Set default port clock if not overwritten by the encoder. Needs to be
11877          * done afterwards in case the encoder adjusts the mode. */
11878         if (!pipe_config->port_clock)
11879                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11880                         * pipe_config->pixel_multiplier;
11881
11882         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11883         if (ret == -EDEADLK)
11884                 return ret;
11885         if (ret < 0) {
11886                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11887                 return ret;
11888         }
11889
11890         if (ret == RETRY) {
11891                 if (WARN(!retry, "loop in pipe configuration computation\n"))
11892                         return -EINVAL;
11893
11894                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11895                 retry = false;
11896                 goto encoder_retry;
11897         }
11898
11899         /* Dithering seems to not pass-through bits correctly when it should, so
11900          * only enable it on 6bpc panels and when its not a compliance
11901          * test requesting 6bpc video pattern.
11902          */
11903         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11904                 !pipe_config->dither_force_disable;
11905         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11906                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11907
11908         return 0;
11909 }
11910
11911 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11912 {
11913         int diff;
11914
11915         if (clock1 == clock2)
11916                 return true;
11917
11918         if (!clock1 || !clock2)
11919                 return false;
11920
11921         diff = abs(clock1 - clock2);
11922
11923         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11924                 return true;
11925
11926         return false;
11927 }
11928
11929 static bool
11930 intel_compare_m_n(unsigned int m, unsigned int n,
11931                   unsigned int m2, unsigned int n2,
11932                   bool exact)
11933 {
11934         if (m == m2 && n == n2)
11935                 return true;
11936
11937         if (exact || !m || !n || !m2 || !n2)
11938                 return false;
11939
11940         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11941
11942         if (n > n2) {
11943                 while (n > n2) {
11944                         m2 <<= 1;
11945                         n2 <<= 1;
11946                 }
11947         } else if (n < n2) {
11948                 while (n < n2) {
11949                         m <<= 1;
11950                         n <<= 1;
11951                 }
11952         }
11953
11954         if (n != n2)
11955                 return false;
11956
11957         return intel_fuzzy_clock_check(m, m2);
11958 }
11959
11960 static bool
11961 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11962                        struct intel_link_m_n *m2_n2,
11963                        bool adjust)
11964 {
11965         if (m_n->tu == m2_n2->tu &&
11966             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11967                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11968             intel_compare_m_n(m_n->link_m, m_n->link_n,
11969                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11970                 if (adjust)
11971                         *m2_n2 = *m_n;
11972
11973                 return true;
11974         }
11975
11976         return false;
11977 }
11978
11979 static bool
11980 intel_compare_infoframe(const union hdmi_infoframe *a,
11981                         const union hdmi_infoframe *b)
11982 {
11983         return memcmp(a, b, sizeof(*a)) == 0;
11984 }
11985
11986 static void
11987 pipe_config_infoframe_err(struct drm_i915_private *dev_priv,
11988                           bool adjust, const char *name,
11989                           const union hdmi_infoframe *a,
11990                           const union hdmi_infoframe *b)
11991 {
11992         if (adjust) {
11993                 if ((drm_debug & DRM_UT_KMS) == 0)
11994                         return;
11995
11996                 drm_dbg(DRM_UT_KMS, "mismatch in %s infoframe", name);
11997                 drm_dbg(DRM_UT_KMS, "expected:");
11998                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
11999                 drm_dbg(DRM_UT_KMS, "found");
12000                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
12001         } else {
12002                 drm_err("mismatch in %s infoframe", name);
12003                 drm_err("expected:");
12004                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
12005                 drm_err("found");
12006                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
12007         }
12008 }
12009
12010 static void __printf(3, 4)
12011 pipe_config_err(bool adjust, const char *name, const char *format, ...)
12012 {
12013         struct va_format vaf;
12014         va_list args;
12015
12016         va_start(args, format);
12017         vaf.fmt = format;
12018         vaf.va = &args;
12019
12020         if (adjust)
12021                 drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
12022         else
12023                 drm_err("mismatch in %s %pV", name, &vaf);
12024
12025         va_end(args);
12026 }
12027
12028 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
12029 {
12030         if (i915_modparams.fastboot != -1)
12031                 return i915_modparams.fastboot;
12032
12033         /* Enable fastboot by default on Skylake and newer */
12034         if (INTEL_GEN(dev_priv) >= 9)
12035                 return true;
12036
12037         /* Enable fastboot by default on VLV and CHV */
12038         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12039                 return true;
12040
12041         /* Disabled by default on all others */
12042         return false;
12043 }
12044
12045 static bool
12046 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
12047                           struct intel_crtc_state *current_config,
12048                           struct intel_crtc_state *pipe_config,
12049                           bool adjust)
12050 {
12051         bool ret = true;
12052         bool fixup_inherited = adjust &&
12053                 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
12054                 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
12055
12056         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
12057                 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12058                 ret = false;
12059         }
12060
12061 #define PIPE_CONF_CHECK_X(name) do { \
12062         if (current_config->name != pipe_config->name) { \
12063                 pipe_config_err(adjust, __stringify(name), \
12064                           "(expected 0x%08x, found 0x%08x)\n", \
12065                           current_config->name, \
12066                           pipe_config->name); \
12067                 ret = false; \
12068         } \
12069 } while (0)
12070
12071 #define PIPE_CONF_CHECK_I(name) do { \
12072         if (current_config->name != pipe_config->name) { \
12073                 pipe_config_err(adjust, __stringify(name), \
12074                           "(expected %i, found %i)\n", \
12075                           current_config->name, \
12076                           pipe_config->name); \
12077                 ret = false; \
12078         } \
12079 } while (0)
12080
12081 #define PIPE_CONF_CHECK_BOOL(name) do { \
12082         if (current_config->name != pipe_config->name) { \
12083                 pipe_config_err(adjust, __stringify(name), \
12084                           "(expected %s, found %s)\n", \
12085                           yesno(current_config->name), \
12086                           yesno(pipe_config->name)); \
12087                 ret = false; \
12088         } \
12089 } while (0)
12090
12091 /*
12092  * Checks state where we only read out the enabling, but not the entire
12093  * state itself (like full infoframes or ELD for audio). These states
12094  * require a full modeset on bootup to fix up.
12095  */
12096 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
12097         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
12098                 PIPE_CONF_CHECK_BOOL(name); \
12099         } else { \
12100                 pipe_config_err(adjust, __stringify(name), \
12101                           "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
12102                           yesno(current_config->name), \
12103                           yesno(pipe_config->name)); \
12104                 ret = false; \
12105         } \
12106 } while (0)
12107
12108 #define PIPE_CONF_CHECK_P(name) do { \
12109         if (current_config->name != pipe_config->name) { \
12110                 pipe_config_err(adjust, __stringify(name), \
12111                           "(expected %p, found %p)\n", \
12112                           current_config->name, \
12113                           pipe_config->name); \
12114                 ret = false; \
12115         } \
12116 } while (0)
12117
12118 #define PIPE_CONF_CHECK_M_N(name) do { \
12119         if (!intel_compare_link_m_n(&current_config->name, \
12120                                     &pipe_config->name,\
12121                                     adjust)) { \
12122                 pipe_config_err(adjust, __stringify(name), \
12123                           "(expected tu %i gmch %i/%i link %i/%i, " \
12124                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12125                           current_config->name.tu, \
12126                           current_config->name.gmch_m, \
12127                           current_config->name.gmch_n, \
12128                           current_config->name.link_m, \
12129                           current_config->name.link_n, \
12130                           pipe_config->name.tu, \
12131                           pipe_config->name.gmch_m, \
12132                           pipe_config->name.gmch_n, \
12133                           pipe_config->name.link_m, \
12134                           pipe_config->name.link_n); \
12135                 ret = false; \
12136         } \
12137 } while (0)
12138
12139 /* This is required for BDW+ where there is only one set of registers for
12140  * switching between high and low RR.
12141  * This macro can be used whenever a comparison has to be made between one
12142  * hw state and multiple sw state variables.
12143  */
12144 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
12145         if (!intel_compare_link_m_n(&current_config->name, \
12146                                     &pipe_config->name, adjust) && \
12147             !intel_compare_link_m_n(&current_config->alt_name, \
12148                                     &pipe_config->name, adjust)) { \
12149                 pipe_config_err(adjust, __stringify(name), \
12150                           "(expected tu %i gmch %i/%i link %i/%i, " \
12151                           "or tu %i gmch %i/%i link %i/%i, " \
12152                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12153                           current_config->name.tu, \
12154                           current_config->name.gmch_m, \
12155                           current_config->name.gmch_n, \
12156                           current_config->name.link_m, \
12157                           current_config->name.link_n, \
12158                           current_config->alt_name.tu, \
12159                           current_config->alt_name.gmch_m, \
12160                           current_config->alt_name.gmch_n, \
12161                           current_config->alt_name.link_m, \
12162                           current_config->alt_name.link_n, \
12163                           pipe_config->name.tu, \
12164                           pipe_config->name.gmch_m, \
12165                           pipe_config->name.gmch_n, \
12166                           pipe_config->name.link_m, \
12167                           pipe_config->name.link_n); \
12168                 ret = false; \
12169         } \
12170 } while (0)
12171
12172 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
12173         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12174                 pipe_config_err(adjust, __stringify(name), \
12175                           "(%x) (expected %i, found %i)\n", \
12176                           (mask), \
12177                           current_config->name & (mask), \
12178                           pipe_config->name & (mask)); \
12179                 ret = false; \
12180         } \
12181 } while (0)
12182
12183 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
12184         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12185                 pipe_config_err(adjust, __stringify(name), \
12186                           "(expected %i, found %i)\n", \
12187                           current_config->name, \
12188                           pipe_config->name); \
12189                 ret = false; \
12190         } \
12191 } while (0)
12192
12193 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
12194         if (!intel_compare_infoframe(&current_config->infoframes.name, \
12195                                      &pipe_config->infoframes.name)) { \
12196                 pipe_config_infoframe_err(dev_priv, adjust, __stringify(name), \
12197                                           &current_config->infoframes.name, \
12198                                           &pipe_config->infoframes.name); \
12199                 ret = false; \
12200         } \
12201 } while (0)
12202
12203 #define PIPE_CONF_QUIRK(quirk) \
12204         ((current_config->quirks | pipe_config->quirks) & (quirk))
12205
12206         PIPE_CONF_CHECK_I(cpu_transcoder);
12207
12208         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
12209         PIPE_CONF_CHECK_I(fdi_lanes);
12210         PIPE_CONF_CHECK_M_N(fdi_m_n);
12211
12212         PIPE_CONF_CHECK_I(lane_count);
12213         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12214
12215         if (INTEL_GEN(dev_priv) < 8) {
12216                 PIPE_CONF_CHECK_M_N(dp_m_n);
12217
12218                 if (current_config->has_drrs)
12219                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12220         } else
12221                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12222
12223         PIPE_CONF_CHECK_X(output_types);
12224
12225         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12226         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12227         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12228         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12229         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12230         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12231
12232         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12233         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12234         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12235         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12236         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12237         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12238
12239         PIPE_CONF_CHECK_I(pixel_multiplier);
12240         PIPE_CONF_CHECK_I(output_format);
12241         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
12242         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
12243             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12244                 PIPE_CONF_CHECK_BOOL(limited_color_range);
12245
12246         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
12247         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
12248         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
12249
12250         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
12251
12252         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12253                               DRM_MODE_FLAG_INTERLACE);
12254
12255         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12256                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12257                                       DRM_MODE_FLAG_PHSYNC);
12258                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12259                                       DRM_MODE_FLAG_NHSYNC);
12260                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12261                                       DRM_MODE_FLAG_PVSYNC);
12262                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12263                                       DRM_MODE_FLAG_NVSYNC);
12264         }
12265
12266         PIPE_CONF_CHECK_X(gmch_pfit.control);
12267         /* pfit ratios are autocomputed by the hw on gen4+ */
12268         if (INTEL_GEN(dev_priv) < 4)
12269                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12270         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12271
12272         if (!adjust) {
12273                 PIPE_CONF_CHECK_I(pipe_src_w);
12274                 PIPE_CONF_CHECK_I(pipe_src_h);
12275
12276                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
12277                 if (current_config->pch_pfit.enabled) {
12278                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12279                         PIPE_CONF_CHECK_X(pch_pfit.size);
12280                 }
12281
12282                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12283                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
12284
12285                 PIPE_CONF_CHECK_X(gamma_mode);
12286                 if (IS_CHERRYVIEW(dev_priv))
12287                         PIPE_CONF_CHECK_X(cgm_mode);
12288                 else
12289                         PIPE_CONF_CHECK_X(csc_mode);
12290                 PIPE_CONF_CHECK_BOOL(gamma_enable);
12291                 PIPE_CONF_CHECK_BOOL(csc_enable);
12292         }
12293
12294         PIPE_CONF_CHECK_BOOL(double_wide);
12295
12296         PIPE_CONF_CHECK_P(shared_dpll);
12297         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12298         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12299         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12300         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12301         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12302         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12303         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12304         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12305         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12306         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
12307         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
12308         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
12309         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
12310         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
12311         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
12312         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
12313         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
12314         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
12315         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
12316         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
12317         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
12318         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
12319         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
12320         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
12321         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
12322         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
12323         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
12324         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
12325         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
12326         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
12327         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
12328
12329         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12330         PIPE_CONF_CHECK_X(dsi_pll.div);
12331
12332         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
12333                 PIPE_CONF_CHECK_I(pipe_bpp);
12334
12335         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12336         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12337
12338         PIPE_CONF_CHECK_I(min_voltage_level);
12339
12340         PIPE_CONF_CHECK_X(infoframes.enable);
12341         PIPE_CONF_CHECK_X(infoframes.gcp);
12342         PIPE_CONF_CHECK_INFOFRAME(avi);
12343         PIPE_CONF_CHECK_INFOFRAME(spd);
12344         PIPE_CONF_CHECK_INFOFRAME(hdmi);
12345
12346 #undef PIPE_CONF_CHECK_X
12347 #undef PIPE_CONF_CHECK_I
12348 #undef PIPE_CONF_CHECK_BOOL
12349 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
12350 #undef PIPE_CONF_CHECK_P
12351 #undef PIPE_CONF_CHECK_FLAGS
12352 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12353 #undef PIPE_CONF_QUIRK
12354
12355         return ret;
12356 }
12357
12358 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12359                                            const struct intel_crtc_state *pipe_config)
12360 {
12361         if (pipe_config->has_pch_encoder) {
12362                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12363                                                             &pipe_config->fdi_m_n);
12364                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12365
12366                 /*
12367                  * FDI already provided one idea for the dotclock.
12368                  * Yell if the encoder disagrees.
12369                  */
12370                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12371                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12372                      fdi_dotclock, dotclock);
12373         }
12374 }
12375
12376 static void verify_wm_state(struct drm_crtc *crtc,
12377                             struct drm_crtc_state *new_state)
12378 {
12379         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12380         struct skl_hw_state {
12381                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
12382                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
12383                 struct skl_ddb_allocation ddb;
12384                 struct skl_pipe_wm wm;
12385         } *hw;
12386         struct skl_ddb_allocation *sw_ddb;
12387         struct skl_pipe_wm *sw_wm;
12388         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
12389         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12390         const enum pipe pipe = intel_crtc->pipe;
12391         int plane, level, max_level = ilk_wm_max_level(dev_priv);
12392
12393         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
12394                 return;
12395
12396         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
12397         if (!hw)
12398                 return;
12399
12400         skl_pipe_wm_get_hw_state(intel_crtc, &hw->wm);
12401         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
12402
12403         skl_pipe_ddb_get_hw_state(intel_crtc, hw->ddb_y, hw->ddb_uv);
12404
12405         skl_ddb_get_hw_state(dev_priv, &hw->ddb);
12406         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12407
12408         if (INTEL_GEN(dev_priv) >= 11 &&
12409             hw->ddb.enabled_slices != sw_ddb->enabled_slices)
12410                 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
12411                           sw_ddb->enabled_slices,
12412                           hw->ddb.enabled_slices);
12413
12414         /* planes */
12415         for_each_universal_plane(dev_priv, pipe, plane) {
12416                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12417
12418                 hw_plane_wm = &hw->wm.planes[plane];
12419                 sw_plane_wm = &sw_wm->planes[plane];
12420
12421                 /* Watermarks */
12422                 for (level = 0; level <= max_level; level++) {
12423                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12424                                                 &sw_plane_wm->wm[level]))
12425                                 continue;
12426
12427                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12428                                   pipe_name(pipe), plane + 1, level,
12429                                   sw_plane_wm->wm[level].plane_en,
12430                                   sw_plane_wm->wm[level].plane_res_b,
12431                                   sw_plane_wm->wm[level].plane_res_l,
12432                                   hw_plane_wm->wm[level].plane_en,
12433                                   hw_plane_wm->wm[level].plane_res_b,
12434                                   hw_plane_wm->wm[level].plane_res_l);
12435                 }
12436
12437                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12438                                          &sw_plane_wm->trans_wm)) {
12439                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12440                                   pipe_name(pipe), plane + 1,
12441                                   sw_plane_wm->trans_wm.plane_en,
12442                                   sw_plane_wm->trans_wm.plane_res_b,
12443                                   sw_plane_wm->trans_wm.plane_res_l,
12444                                   hw_plane_wm->trans_wm.plane_en,
12445                                   hw_plane_wm->trans_wm.plane_res_b,
12446                                   hw_plane_wm->trans_wm.plane_res_l);
12447                 }
12448
12449                 /* DDB */
12450                 hw_ddb_entry = &hw->ddb_y[plane];
12451                 sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[plane];
12452
12453                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12454                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12455                                   pipe_name(pipe), plane + 1,
12456                                   sw_ddb_entry->start, sw_ddb_entry->end,
12457                                   hw_ddb_entry->start, hw_ddb_entry->end);
12458                 }
12459         }
12460
12461         /*
12462          * cursor
12463          * If the cursor plane isn't active, we may not have updated it's ddb
12464          * allocation. In that case since the ddb allocation will be updated
12465          * once the plane becomes visible, we can skip this check
12466          */
12467         if (1) {
12468                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12469
12470                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
12471                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
12472
12473                 /* Watermarks */
12474                 for (level = 0; level <= max_level; level++) {
12475                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12476                                                 &sw_plane_wm->wm[level]))
12477                                 continue;
12478
12479                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12480                                   pipe_name(pipe), level,
12481                                   sw_plane_wm->wm[level].plane_en,
12482                                   sw_plane_wm->wm[level].plane_res_b,
12483                                   sw_plane_wm->wm[level].plane_res_l,
12484                                   hw_plane_wm->wm[level].plane_en,
12485                                   hw_plane_wm->wm[level].plane_res_b,
12486                                   hw_plane_wm->wm[level].plane_res_l);
12487                 }
12488
12489                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12490                                          &sw_plane_wm->trans_wm)) {
12491                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12492                                   pipe_name(pipe),
12493                                   sw_plane_wm->trans_wm.plane_en,
12494                                   sw_plane_wm->trans_wm.plane_res_b,
12495                                   sw_plane_wm->trans_wm.plane_res_l,
12496                                   hw_plane_wm->trans_wm.plane_en,
12497                                   hw_plane_wm->trans_wm.plane_res_b,
12498                                   hw_plane_wm->trans_wm.plane_res_l);
12499                 }
12500
12501                 /* DDB */
12502                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
12503                 sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[PLANE_CURSOR];
12504
12505                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12506                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12507                                   pipe_name(pipe),
12508                                   sw_ddb_entry->start, sw_ddb_entry->end,
12509                                   hw_ddb_entry->start, hw_ddb_entry->end);
12510                 }
12511         }
12512
12513         kfree(hw);
12514 }
12515
12516 static void
12517 verify_connector_state(struct drm_device *dev,
12518                        struct drm_atomic_state *state,
12519                        struct drm_crtc *crtc)
12520 {
12521         struct drm_connector *connector;
12522         struct drm_connector_state *new_conn_state;
12523         int i;
12524
12525         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
12526                 struct drm_encoder *encoder = connector->encoder;
12527                 struct drm_crtc_state *crtc_state = NULL;
12528
12529                 if (new_conn_state->crtc != crtc)
12530                         continue;
12531
12532                 if (crtc)
12533                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
12534
12535                 intel_connector_verify_state(crtc_state, new_conn_state);
12536
12537                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
12538                      "connector's atomic encoder doesn't match legacy encoder\n");
12539         }
12540 }
12541
12542 static void
12543 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
12544 {
12545         struct intel_encoder *encoder;
12546         struct drm_connector *connector;
12547         struct drm_connector_state *old_conn_state, *new_conn_state;
12548         int i;
12549
12550         for_each_intel_encoder(dev, encoder) {
12551                 bool enabled = false, found = false;
12552                 enum pipe pipe;
12553
12554                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12555                               encoder->base.base.id,
12556                               encoder->base.name);
12557
12558                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
12559                                                    new_conn_state, i) {
12560                         if (old_conn_state->best_encoder == &encoder->base)
12561                                 found = true;
12562
12563                         if (new_conn_state->best_encoder != &encoder->base)
12564                                 continue;
12565                         found = enabled = true;
12566
12567                         I915_STATE_WARN(new_conn_state->crtc !=
12568                                         encoder->base.crtc,
12569                              "connector's crtc doesn't match encoder crtc\n");
12570                 }
12571
12572                 if (!found)
12573                         continue;
12574
12575                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12576                      "encoder's enabled state mismatch "
12577                      "(expected %i, found %i)\n",
12578                      !!encoder->base.crtc, enabled);
12579
12580                 if (!encoder->base.crtc) {
12581                         bool active;
12582
12583                         active = encoder->get_hw_state(encoder, &pipe);
12584                         I915_STATE_WARN(active,
12585                              "encoder detached but still enabled on pipe %c.\n",
12586                              pipe_name(pipe));
12587                 }
12588         }
12589 }
12590
12591 static void
12592 verify_crtc_state(struct drm_crtc *crtc,
12593                   struct drm_crtc_state *old_crtc_state,
12594                   struct drm_crtc_state *new_crtc_state)
12595 {
12596         struct drm_device *dev = crtc->dev;
12597         struct drm_i915_private *dev_priv = to_i915(dev);
12598         struct intel_encoder *encoder;
12599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12600         struct intel_crtc_state *pipe_config, *sw_config;
12601         struct drm_atomic_state *old_state;
12602         bool active;
12603
12604         old_state = old_crtc_state->state;
12605         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12606         pipe_config = to_intel_crtc_state(old_crtc_state);
12607         memset(pipe_config, 0, sizeof(*pipe_config));
12608         pipe_config->base.crtc = crtc;
12609         pipe_config->base.state = old_state;
12610
12611         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12612
12613         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12614
12615         /* we keep both pipes enabled on 830 */
12616         if (IS_I830(dev_priv))
12617                 active = new_crtc_state->active;
12618
12619         I915_STATE_WARN(new_crtc_state->active != active,
12620              "crtc active state doesn't match with hw state "
12621              "(expected %i, found %i)\n", new_crtc_state->active, active);
12622
12623         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12624              "transitional active state does not match atomic hw state "
12625              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12626
12627         for_each_encoder_on_crtc(dev, crtc, encoder) {
12628                 enum pipe pipe;
12629
12630                 active = encoder->get_hw_state(encoder, &pipe);
12631                 I915_STATE_WARN(active != new_crtc_state->active,
12632                         "[ENCODER:%i] active %i with crtc active %i\n",
12633                         encoder->base.base.id, active, new_crtc_state->active);
12634
12635                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12636                                 "Encoder connected to wrong pipe %c\n",
12637                                 pipe_name(pipe));
12638
12639                 if (active)
12640                         encoder->get_config(encoder, pipe_config);
12641         }
12642
12643         intel_crtc_compute_pixel_rate(pipe_config);
12644
12645         if (!new_crtc_state->active)
12646                 return;
12647
12648         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12649
12650         sw_config = to_intel_crtc_state(new_crtc_state);
12651         if (!intel_pipe_config_compare(dev_priv, sw_config,
12652                                        pipe_config, false)) {
12653                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12654                 intel_dump_pipe_config(intel_crtc, pipe_config,
12655                                        "[hw state]");
12656                 intel_dump_pipe_config(intel_crtc, sw_config,
12657                                        "[sw state]");
12658         }
12659 }
12660
12661 static void
12662 intel_verify_planes(struct intel_atomic_state *state)
12663 {
12664         struct intel_plane *plane;
12665         const struct intel_plane_state *plane_state;
12666         int i;
12667
12668         for_each_new_intel_plane_in_state(state, plane,
12669                                           plane_state, i)
12670                 assert_plane(plane, plane_state->slave ||
12671                              plane_state->base.visible);
12672 }
12673
12674 static void
12675 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12676                          struct intel_shared_dpll *pll,
12677                          struct drm_crtc *crtc,
12678                          struct drm_crtc_state *new_state)
12679 {
12680         struct intel_dpll_hw_state dpll_hw_state;
12681         unsigned int crtc_mask;
12682         bool active;
12683
12684         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12685
12686         DRM_DEBUG_KMS("%s\n", pll->info->name);
12687
12688         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
12689
12690         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
12691                 I915_STATE_WARN(!pll->on && pll->active_mask,
12692                      "pll in active use but not on in sw tracking\n");
12693                 I915_STATE_WARN(pll->on && !pll->active_mask,
12694                      "pll is on but not used by any active crtc\n");
12695                 I915_STATE_WARN(pll->on != active,
12696                      "pll on state mismatch (expected %i, found %i)\n",
12697                      pll->on, active);
12698         }
12699
12700         if (!crtc) {
12701                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12702                                 "more active pll users than references: %x vs %x\n",
12703                                 pll->active_mask, pll->state.crtc_mask);
12704
12705                 return;
12706         }
12707
12708         crtc_mask = drm_crtc_mask(crtc);
12709
12710         if (new_state->active)
12711                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12712                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12713                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12714         else
12715                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12716                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12717                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12718
12719         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12720                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12721                         crtc_mask, pll->state.crtc_mask);
12722
12723         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12724                                           &dpll_hw_state,
12725                                           sizeof(dpll_hw_state)),
12726                         "pll hw state mismatch\n");
12727 }
12728
12729 static void
12730 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12731                          struct drm_crtc_state *old_crtc_state,
12732                          struct drm_crtc_state *new_crtc_state)
12733 {
12734         struct drm_i915_private *dev_priv = to_i915(dev);
12735         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12736         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12737
12738         if (new_state->shared_dpll)
12739                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12740
12741         if (old_state->shared_dpll &&
12742             old_state->shared_dpll != new_state->shared_dpll) {
12743                 unsigned int crtc_mask = drm_crtc_mask(crtc);
12744                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12745
12746                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12747                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12748                                 pipe_name(drm_crtc_index(crtc)));
12749                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12750                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12751                                 pipe_name(drm_crtc_index(crtc)));
12752         }
12753 }
12754
12755 static void
12756 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12757                           struct drm_atomic_state *state,
12758                           struct drm_crtc_state *old_state,
12759                           struct drm_crtc_state *new_state)
12760 {
12761         if (!needs_modeset(new_state) &&
12762             !to_intel_crtc_state(new_state)->update_pipe)
12763                 return;
12764
12765         verify_wm_state(crtc, new_state);
12766         verify_connector_state(crtc->dev, state, crtc);
12767         verify_crtc_state(crtc, old_state, new_state);
12768         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12769 }
12770
12771 static void
12772 verify_disabled_dpll_state(struct drm_device *dev)
12773 {
12774         struct drm_i915_private *dev_priv = to_i915(dev);
12775         int i;
12776
12777         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12778                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12779 }
12780
12781 static void
12782 intel_modeset_verify_disabled(struct drm_device *dev,
12783                               struct drm_atomic_state *state)
12784 {
12785         verify_encoder_state(dev, state);
12786         verify_connector_state(dev, state, NULL);
12787         verify_disabled_dpll_state(dev);
12788 }
12789
12790 static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
12791 {
12792         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
12793         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12794
12795         /*
12796          * The scanline counter increments at the leading edge of hsync.
12797          *
12798          * On most platforms it starts counting from vtotal-1 on the
12799          * first active line. That means the scanline counter value is
12800          * always one less than what we would expect. Ie. just after
12801          * start of vblank, which also occurs at start of hsync (on the
12802          * last active line), the scanline counter will read vblank_start-1.
12803          *
12804          * On gen2 the scanline counter starts counting from 1 instead
12805          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12806          * to keep the value positive), instead of adding one.
12807          *
12808          * On HSW+ the behaviour of the scanline counter depends on the output
12809          * type. For DP ports it behaves like most other platforms, but on HDMI
12810          * there's an extra 1 line difference. So we need to add two instead of
12811          * one to the value.
12812          *
12813          * On VLV/CHV DSI the scanline counter would appear to increment
12814          * approx. 1/3 of a scanline before start of vblank. Unfortunately
12815          * that means we can't tell whether we're in vblank or not while
12816          * we're on that particular line. We must still set scanline_offset
12817          * to 1 so that the vblank timestamps come out correct when we query
12818          * the scanline counter from within the vblank interrupt handler.
12819          * However if queried just before the start of vblank we'll get an
12820          * answer that's slightly in the future.
12821          */
12822         if (IS_GEN(dev_priv, 2)) {
12823                 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
12824                 int vtotal;
12825
12826                 vtotal = adjusted_mode->crtc_vtotal;
12827                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12828                         vtotal /= 2;
12829
12830                 crtc->scanline_offset = vtotal - 1;
12831         } else if (HAS_DDI(dev_priv) &&
12832                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
12833                 crtc->scanline_offset = 2;
12834         } else
12835                 crtc->scanline_offset = 1;
12836 }
12837
12838 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12839 {
12840         struct drm_device *dev = state->dev;
12841         struct drm_i915_private *dev_priv = to_i915(dev);
12842         struct drm_crtc *crtc;
12843         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12844         int i;
12845
12846         if (!dev_priv->display.crtc_compute_clock)
12847                 return;
12848
12849         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12850                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12851                 struct intel_shared_dpll *old_dpll =
12852                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
12853
12854                 if (!needs_modeset(new_crtc_state))
12855                         continue;
12856
12857                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12858
12859                 if (!old_dpll)
12860                         continue;
12861
12862                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12863         }
12864 }
12865
12866 /*
12867  * This implements the workaround described in the "notes" section of the mode
12868  * set sequence documentation. When going from no pipes or single pipe to
12869  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12870  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12871  */
12872 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12873 {
12874         struct drm_crtc_state *crtc_state;
12875         struct intel_crtc *intel_crtc;
12876         struct drm_crtc *crtc;
12877         struct intel_crtc_state *first_crtc_state = NULL;
12878         struct intel_crtc_state *other_crtc_state = NULL;
12879         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12880         int i;
12881
12882         /* look at all crtc's that are going to be enabled in during modeset */
12883         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12884                 intel_crtc = to_intel_crtc(crtc);
12885
12886                 if (!crtc_state->active || !needs_modeset(crtc_state))
12887                         continue;
12888
12889                 if (first_crtc_state) {
12890                         other_crtc_state = to_intel_crtc_state(crtc_state);
12891                         break;
12892                 } else {
12893                         first_crtc_state = to_intel_crtc_state(crtc_state);
12894                         first_pipe = intel_crtc->pipe;
12895                 }
12896         }
12897
12898         /* No workaround needed? */
12899         if (!first_crtc_state)
12900                 return 0;
12901
12902         /* w/a possibly needed, check how many crtc's are already enabled. */
12903         for_each_intel_crtc(state->dev, intel_crtc) {
12904                 struct intel_crtc_state *pipe_config;
12905
12906                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12907                 if (IS_ERR(pipe_config))
12908                         return PTR_ERR(pipe_config);
12909
12910                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12911
12912                 if (!pipe_config->base.active ||
12913                     needs_modeset(&pipe_config->base))
12914                         continue;
12915
12916                 /* 2 or more enabled crtcs means no need for w/a */
12917                 if (enabled_pipe != INVALID_PIPE)
12918                         return 0;
12919
12920                 enabled_pipe = intel_crtc->pipe;
12921         }
12922
12923         if (enabled_pipe != INVALID_PIPE)
12924                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12925         else if (other_crtc_state)
12926                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12927
12928         return 0;
12929 }
12930
12931 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12932 {
12933         struct drm_crtc *crtc;
12934
12935         /* Add all pipes to the state */
12936         for_each_crtc(state->dev, crtc) {
12937                 struct drm_crtc_state *crtc_state;
12938
12939                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12940                 if (IS_ERR(crtc_state))
12941                         return PTR_ERR(crtc_state);
12942         }
12943
12944         return 0;
12945 }
12946
12947 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12948 {
12949         struct drm_crtc *crtc;
12950
12951         /*
12952          * Add all pipes to the state, and force
12953          * a modeset on all the active ones.
12954          */
12955         for_each_crtc(state->dev, crtc) {
12956                 struct drm_crtc_state *crtc_state;
12957                 int ret;
12958
12959                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12960                 if (IS_ERR(crtc_state))
12961                         return PTR_ERR(crtc_state);
12962
12963                 if (!crtc_state->active || needs_modeset(crtc_state))
12964                         continue;
12965
12966                 crtc_state->mode_changed = true;
12967
12968                 ret = drm_atomic_add_affected_connectors(state, crtc);
12969                 if (ret)
12970                         return ret;
12971
12972                 ret = drm_atomic_add_affected_planes(state, crtc);
12973                 if (ret)
12974                         return ret;
12975         }
12976
12977         return 0;
12978 }
12979
12980 static int intel_modeset_checks(struct drm_atomic_state *state)
12981 {
12982         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12983         struct drm_i915_private *dev_priv = to_i915(state->dev);
12984         struct drm_crtc *crtc;
12985         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12986         int ret = 0, i;
12987
12988         if (!check_digital_port_conflicts(state)) {
12989                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12990                 return -EINVAL;
12991         }
12992
12993         intel_state->modeset = true;
12994         intel_state->active_crtcs = dev_priv->active_crtcs;
12995         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12996         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12997
12998         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12999                 if (new_crtc_state->active)
13000                         intel_state->active_crtcs |= 1 << i;
13001                 else
13002                         intel_state->active_crtcs &= ~(1 << i);
13003
13004                 if (old_crtc_state->active != new_crtc_state->active)
13005                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13006         }
13007
13008         /*
13009          * See if the config requires any additional preparation, e.g.
13010          * to adjust global state with pipes off.  We need to do this
13011          * here so we can get the modeset_pipe updated config for the new
13012          * mode set on this crtc.  For other crtcs we need to use the
13013          * adjusted_mode bits in the crtc directly.
13014          */
13015         if (dev_priv->display.modeset_calc_cdclk) {
13016                 ret = dev_priv->display.modeset_calc_cdclk(state);
13017                 if (ret < 0)
13018                         return ret;
13019
13020                 /*
13021                  * Writes to dev_priv->cdclk.logical must protected by
13022                  * holding all the crtc locks, even if we don't end up
13023                  * touching the hardware
13024                  */
13025                 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
13026                                         &intel_state->cdclk.logical)) {
13027                         ret = intel_lock_all_pipes(state);
13028                         if (ret < 0)
13029                                 return ret;
13030                 }
13031
13032                 /* All pipes must be switched off while we change the cdclk. */
13033                 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
13034                                               &intel_state->cdclk.actual)) {
13035                         ret = intel_modeset_all_pipes(state);
13036                         if (ret < 0)
13037                                 return ret;
13038                 }
13039
13040                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
13041                               intel_state->cdclk.logical.cdclk,
13042                               intel_state->cdclk.actual.cdclk);
13043                 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
13044                               intel_state->cdclk.logical.voltage_level,
13045                               intel_state->cdclk.actual.voltage_level);
13046         } else {
13047                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
13048         }
13049
13050         intel_modeset_clear_plls(state);
13051
13052         if (IS_HASWELL(dev_priv))
13053                 return haswell_mode_set_planes_workaround(state);
13054
13055         return 0;
13056 }
13057
13058 /*
13059  * Handle calculation of various watermark data at the end of the atomic check
13060  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13061  * handlers to ensure that all derived state has been updated.
13062  */
13063 static int calc_watermark_data(struct intel_atomic_state *state)
13064 {
13065         struct drm_device *dev = state->base.dev;
13066         struct drm_i915_private *dev_priv = to_i915(dev);
13067
13068         /* Is there platform-specific watermark information to calculate? */
13069         if (dev_priv->display.compute_global_watermarks)
13070                 return dev_priv->display.compute_global_watermarks(state);
13071
13072         return 0;
13073 }
13074
13075 /**
13076  * intel_atomic_check - validate state object
13077  * @dev: drm device
13078  * @state: state to validate
13079  */
13080 static int intel_atomic_check(struct drm_device *dev,
13081                               struct drm_atomic_state *state)
13082 {
13083         struct drm_i915_private *dev_priv = to_i915(dev);
13084         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13085         struct drm_crtc *crtc;
13086         struct drm_crtc_state *old_crtc_state, *crtc_state;
13087         int ret, i;
13088         bool any_ms = false;
13089
13090         /* Catch I915_MODE_FLAG_INHERITED */
13091         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
13092                                       crtc_state, i) {
13093                 if (crtc_state->mode.private_flags !=
13094                     old_crtc_state->mode.private_flags)
13095                         crtc_state->mode_changed = true;
13096         }
13097
13098         ret = drm_atomic_helper_check_modeset(dev, state);
13099         if (ret)
13100                 return ret;
13101
13102         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
13103                 struct intel_crtc_state *pipe_config =
13104                         to_intel_crtc_state(crtc_state);
13105
13106                 if (!needs_modeset(crtc_state))
13107                         continue;
13108
13109                 if (!crtc_state->enable) {
13110                         any_ms = true;
13111                         continue;
13112                 }
13113
13114                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13115                 if (ret == -EDEADLK)
13116                         return ret;
13117                 if (ret) {
13118                         intel_dump_pipe_config(to_intel_crtc(crtc),
13119                                                pipe_config, "[failed]");
13120                         return ret;
13121                 }
13122
13123                 if (intel_pipe_config_compare(dev_priv,
13124                                         to_intel_crtc_state(old_crtc_state),
13125                                         pipe_config, true)) {
13126                         crtc_state->mode_changed = false;
13127                         pipe_config->update_pipe = true;
13128                 }
13129
13130                 if (needs_modeset(crtc_state))
13131                         any_ms = true;
13132
13133                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13134                                        needs_modeset(crtc_state) ?
13135                                        "[modeset]" : "[fastset]");
13136         }
13137
13138         ret = drm_dp_mst_atomic_check(state);
13139         if (ret)
13140                 return ret;
13141
13142         if (any_ms) {
13143                 ret = intel_modeset_checks(state);
13144
13145                 if (ret)
13146                         return ret;
13147         } else {
13148                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
13149         }
13150
13151         ret = icl_add_linked_planes(intel_state);
13152         if (ret)
13153                 return ret;
13154
13155         ret = drm_atomic_helper_check_planes(dev, state);
13156         if (ret)
13157                 return ret;
13158
13159         intel_fbc_choose_crtc(dev_priv, intel_state);
13160         return calc_watermark_data(intel_state);
13161 }
13162
13163 static int intel_atomic_prepare_commit(struct drm_device *dev,
13164                                        struct drm_atomic_state *state)
13165 {
13166         return drm_atomic_helper_prepare_planes(dev, state);
13167 }
13168
13169 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13170 {
13171         struct drm_device *dev = crtc->base.dev;
13172         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
13173
13174         if (!vblank->max_vblank_count)
13175                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
13176
13177         return dev->driver->get_vblank_counter(dev, crtc->pipe);
13178 }
13179
13180 static void intel_update_crtc(struct drm_crtc *crtc,
13181                               struct drm_atomic_state *state,
13182                               struct drm_crtc_state *old_crtc_state,
13183                               struct drm_crtc_state *new_crtc_state)
13184 {
13185         struct drm_device *dev = crtc->dev;
13186         struct drm_i915_private *dev_priv = to_i915(dev);
13187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13188         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
13189         bool modeset = needs_modeset(new_crtc_state);
13190         struct intel_plane_state *new_plane_state =
13191                 intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
13192                                                  to_intel_plane(crtc->primary));
13193
13194         if (modeset) {
13195                 update_scanline_offset(pipe_config);
13196                 dev_priv->display.crtc_enable(pipe_config, state);
13197
13198                 /* vblanks work again, re-enable pipe CRC. */
13199                 intel_crtc_enable_pipe_crc(intel_crtc);
13200         } else {
13201                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
13202                                        pipe_config);
13203
13204                 if (pipe_config->update_pipe)
13205                         intel_encoders_update_pipe(crtc, pipe_config, state);
13206         }
13207
13208         if (pipe_config->update_pipe && !pipe_config->enable_fbc)
13209                 intel_fbc_disable(intel_crtc);
13210         else if (new_plane_state)
13211                 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
13212
13213         intel_begin_crtc_commit(crtc, old_crtc_state);
13214
13215         if (INTEL_GEN(dev_priv) >= 9)
13216                 skl_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
13217         else
13218                 i9xx_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
13219
13220         intel_finish_crtc_commit(crtc, old_crtc_state);
13221 }
13222
13223 static void intel_update_crtcs(struct drm_atomic_state *state)
13224 {
13225         struct drm_crtc *crtc;
13226         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13227         int i;
13228
13229         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13230                 if (!new_crtc_state->active)
13231                         continue;
13232
13233                 intel_update_crtc(crtc, state, old_crtc_state,
13234                                   new_crtc_state);
13235         }
13236 }
13237
13238 static void skl_update_crtcs(struct drm_atomic_state *state)
13239 {
13240         struct drm_i915_private *dev_priv = to_i915(state->dev);
13241         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13242         struct drm_crtc *crtc;
13243         struct intel_crtc *intel_crtc;
13244         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13245         struct intel_crtc_state *cstate;
13246         unsigned int updated = 0;
13247         bool progress;
13248         enum pipe pipe;
13249         int i;
13250         u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
13251         u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
13252         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
13253
13254         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
13255                 /* ignore allocations for crtc's that have been turned off. */
13256                 if (new_crtc_state->active)
13257                         entries[i] = to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
13258
13259         /* If 2nd DBuf slice required, enable it here */
13260         if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
13261                 icl_dbuf_slices_update(dev_priv, required_slices);
13262
13263         /*
13264          * Whenever the number of active pipes changes, we need to make sure we
13265          * update the pipes in the right order so that their ddb allocations
13266          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
13267          * cause pipe underruns and other bad stuff.
13268          */
13269         do {
13270                 progress = false;
13271
13272                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13273                         bool vbl_wait = false;
13274                         unsigned int cmask = drm_crtc_mask(crtc);
13275
13276                         intel_crtc = to_intel_crtc(crtc);
13277                         cstate = to_intel_crtc_state(new_crtc_state);
13278                         pipe = intel_crtc->pipe;
13279
13280                         if (updated & cmask || !cstate->base.active)
13281                                 continue;
13282
13283                         if (skl_ddb_allocation_overlaps(&cstate->wm.skl.ddb,
13284                                                         entries,
13285                                                         INTEL_INFO(dev_priv)->num_pipes, i))
13286                                 continue;
13287
13288                         updated |= cmask;
13289                         entries[i] = cstate->wm.skl.ddb;
13290
13291                         /*
13292                          * If this is an already active pipe, it's DDB changed,
13293                          * and this isn't the last pipe that needs updating
13294                          * then we need to wait for a vblank to pass for the
13295                          * new ddb allocation to take effect.
13296                          */
13297                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
13298                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
13299                             !new_crtc_state->active_changed &&
13300                             intel_state->wm_results.dirty_pipes != updated)
13301                                 vbl_wait = true;
13302
13303                         intel_update_crtc(crtc, state, old_crtc_state,
13304                                           new_crtc_state);
13305
13306                         if (vbl_wait)
13307                                 intel_wait_for_vblank(dev_priv, pipe);
13308
13309                         progress = true;
13310                 }
13311         } while (progress);
13312
13313         /* If 2nd DBuf slice is no more required disable it */
13314         if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
13315                 icl_dbuf_slices_update(dev_priv, required_slices);
13316 }
13317
13318 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
13319 {
13320         struct intel_atomic_state *state, *next;
13321         struct llist_node *freed;
13322
13323         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
13324         llist_for_each_entry_safe(state, next, freed, freed)
13325                 drm_atomic_state_put(&state->base);
13326 }
13327
13328 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
13329 {
13330         struct drm_i915_private *dev_priv =
13331                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
13332
13333         intel_atomic_helper_free_state(dev_priv);
13334 }
13335
13336 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
13337 {
13338         struct wait_queue_entry wait_fence, wait_reset;
13339         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
13340
13341         init_wait_entry(&wait_fence, 0);
13342         init_wait_entry(&wait_reset, 0);
13343         for (;;) {
13344                 prepare_to_wait(&intel_state->commit_ready.wait,
13345                                 &wait_fence, TASK_UNINTERRUPTIBLE);
13346                 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
13347                                 &wait_reset, TASK_UNINTERRUPTIBLE);
13348
13349
13350                 if (i915_sw_fence_done(&intel_state->commit_ready)
13351                     || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
13352                         break;
13353
13354                 schedule();
13355         }
13356         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
13357         finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
13358 }
13359
13360 static void intel_atomic_cleanup_work(struct work_struct *work)
13361 {
13362         struct drm_atomic_state *state =
13363                 container_of(work, struct drm_atomic_state, commit_work);
13364         struct drm_i915_private *i915 = to_i915(state->dev);
13365
13366         drm_atomic_helper_cleanup_planes(&i915->drm, state);
13367         drm_atomic_helper_commit_cleanup_done(state);
13368         drm_atomic_state_put(state);
13369
13370         intel_atomic_helper_free_state(i915);
13371 }
13372
13373 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13374 {
13375         struct drm_device *dev = state->dev;
13376         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13377         struct drm_i915_private *dev_priv = to_i915(dev);
13378         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13379         struct intel_crtc_state *new_intel_crtc_state, *old_intel_crtc_state;
13380         struct drm_crtc *crtc;
13381         struct intel_crtc *intel_crtc;
13382         u64 put_domains[I915_MAX_PIPES] = {};
13383         intel_wakeref_t wakeref = 0;
13384         int i;
13385
13386         intel_atomic_commit_fence_wait(intel_state);
13387
13388         drm_atomic_helper_wait_for_dependencies(state);
13389
13390         if (intel_state->modeset)
13391                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13392
13393         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13394                 old_intel_crtc_state = to_intel_crtc_state(old_crtc_state);
13395                 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13396                 intel_crtc = to_intel_crtc(crtc);
13397
13398                 if (needs_modeset(new_crtc_state) ||
13399                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
13400
13401                         put_domains[intel_crtc->pipe] =
13402                                 modeset_get_crtc_power_domains(crtc,
13403                                         new_intel_crtc_state);
13404                 }
13405
13406                 if (!needs_modeset(new_crtc_state))
13407                         continue;
13408
13409                 intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state);
13410
13411                 if (old_crtc_state->active) {
13412                         intel_crtc_disable_planes(intel_state, intel_crtc);
13413
13414                         /*
13415                          * We need to disable pipe CRC before disabling the pipe,
13416                          * or we race against vblank off.
13417                          */
13418                         intel_crtc_disable_pipe_crc(intel_crtc);
13419
13420                         dev_priv->display.crtc_disable(old_intel_crtc_state, state);
13421                         intel_crtc->active = false;
13422                         intel_fbc_disable(intel_crtc);
13423                         intel_disable_shared_dpll(old_intel_crtc_state);
13424
13425                         /*
13426                          * Underruns don't always raise
13427                          * interrupts, so check manually.
13428                          */
13429                         intel_check_cpu_fifo_underruns(dev_priv);
13430                         intel_check_pch_fifo_underruns(dev_priv);
13431
13432                         /* FIXME unify this for all platforms */
13433                         if (!new_crtc_state->active &&
13434                             !HAS_GMCH(dev_priv) &&
13435                             dev_priv->display.initial_watermarks)
13436                                 dev_priv->display.initial_watermarks(intel_state,
13437                                                                      new_intel_crtc_state);
13438                 }
13439         }
13440
13441         /* FIXME: Eventually get rid of our intel_crtc->config pointer */
13442         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
13443                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
13444
13445         if (intel_state->modeset) {
13446                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13447
13448                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
13449
13450                 /*
13451                  * SKL workaround: bspec recommends we disable the SAGV when we
13452                  * have more then one pipe enabled
13453                  */
13454                 if (!intel_can_enable_sagv(state))
13455                         intel_disable_sagv(dev_priv);
13456
13457                 intel_modeset_verify_disabled(dev, state);
13458         }
13459
13460         /* Complete the events for pipes that have now been disabled */
13461         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13462                 bool modeset = needs_modeset(new_crtc_state);
13463
13464                 /* Complete events for now disable pipes here. */
13465                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
13466                         spin_lock_irq(&dev->event_lock);
13467                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
13468                         spin_unlock_irq(&dev->event_lock);
13469
13470                         new_crtc_state->event = NULL;
13471                 }
13472         }
13473
13474         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13475         dev_priv->display.update_crtcs(state);
13476
13477         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13478          * already, but still need the state for the delayed optimization. To
13479          * fix this:
13480          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13481          * - schedule that vblank worker _before_ calling hw_done
13482          * - at the start of commit_tail, cancel it _synchrously
13483          * - switch over to the vblank wait helper in the core after that since
13484          *   we don't need out special handling any more.
13485          */
13486         drm_atomic_helper_wait_for_flip_done(dev, state);
13487
13488         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13489                 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13490
13491                 if (new_crtc_state->active &&
13492                     !needs_modeset(new_crtc_state) &&
13493                     (new_intel_crtc_state->base.color_mgmt_changed ||
13494                      new_intel_crtc_state->update_pipe))
13495                         intel_color_load_luts(new_intel_crtc_state);
13496         }
13497
13498         /*
13499          * Now that the vblank has passed, we can go ahead and program the
13500          * optimal watermarks on platforms that need two-step watermark
13501          * programming.
13502          *
13503          * TODO: Move this (and other cleanup) to an async worker eventually.
13504          */
13505         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13506                 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13507
13508                 if (dev_priv->display.optimize_watermarks)
13509                         dev_priv->display.optimize_watermarks(intel_state,
13510                                                               new_intel_crtc_state);
13511         }
13512
13513         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13514                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13515
13516                 if (put_domains[i])
13517                         modeset_put_power_domains(dev_priv, put_domains[i]);
13518
13519                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
13520         }
13521
13522         if (intel_state->modeset)
13523                 intel_verify_planes(intel_state);
13524
13525         if (intel_state->modeset && intel_can_enable_sagv(state))
13526                 intel_enable_sagv(dev_priv);
13527
13528         drm_atomic_helper_commit_hw_done(state);
13529
13530         if (intel_state->modeset) {
13531                 /* As one of the primary mmio accessors, KMS has a high
13532                  * likelihood of triggering bugs in unclaimed access. After we
13533                  * finish modesetting, see if an error has been flagged, and if
13534                  * so enable debugging for the next modeset - and hope we catch
13535                  * the culprit.
13536                  */
13537                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
13538                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
13539         }
13540
13541         /*
13542          * Defer the cleanup of the old state to a separate worker to not
13543          * impede the current task (userspace for blocking modesets) that
13544          * are executed inline. For out-of-line asynchronous modesets/flips,
13545          * deferring to a new worker seems overkill, but we would place a
13546          * schedule point (cond_resched()) here anyway to keep latencies
13547          * down.
13548          */
13549         INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);
13550         queue_work(system_highpri_wq, &state->commit_work);
13551 }
13552
13553 static void intel_atomic_commit_work(struct work_struct *work)
13554 {
13555         struct drm_atomic_state *state =
13556                 container_of(work, struct drm_atomic_state, commit_work);
13557
13558         intel_atomic_commit_tail(state);
13559 }
13560
13561 static int __i915_sw_fence_call
13562 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13563                           enum i915_sw_fence_notify notify)
13564 {
13565         struct intel_atomic_state *state =
13566                 container_of(fence, struct intel_atomic_state, commit_ready);
13567
13568         switch (notify) {
13569         case FENCE_COMPLETE:
13570                 /* we do blocking waits in the worker, nothing to do here */
13571                 break;
13572         case FENCE_FREE:
13573                 {
13574                         struct intel_atomic_helper *helper =
13575                                 &to_i915(state->base.dev)->atomic_helper;
13576
13577                         if (llist_add(&state->freed, &helper->free_list))
13578                                 schedule_work(&helper->free_work);
13579                         break;
13580                 }
13581         }
13582
13583         return NOTIFY_DONE;
13584 }
13585
13586 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13587 {
13588         struct drm_plane_state *old_plane_state, *new_plane_state;
13589         struct drm_plane *plane;
13590         int i;
13591
13592         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13593                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13594                                   intel_fb_obj(new_plane_state->fb),
13595                                   to_intel_plane(plane)->frontbuffer_bit);
13596 }
13597
13598 /**
13599  * intel_atomic_commit - commit validated state object
13600  * @dev: DRM device
13601  * @state: the top-level driver state object
13602  * @nonblock: nonblocking commit
13603  *
13604  * This function commits a top-level state object that has been validated
13605  * with drm_atomic_helper_check().
13606  *
13607  * RETURNS
13608  * Zero for success or -errno.
13609  */
13610 static int intel_atomic_commit(struct drm_device *dev,
13611                                struct drm_atomic_state *state,
13612                                bool nonblock)
13613 {
13614         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13615         struct drm_i915_private *dev_priv = to_i915(dev);
13616         int ret = 0;
13617
13618         drm_atomic_state_get(state);
13619         i915_sw_fence_init(&intel_state->commit_ready,
13620                            intel_atomic_commit_ready);
13621
13622         /*
13623          * The intel_legacy_cursor_update() fast path takes care
13624          * of avoiding the vblank waits for simple cursor
13625          * movement and flips. For cursor on/off and size changes,
13626          * we want to perform the vblank waits so that watermark
13627          * updates happen during the correct frames. Gen9+ have
13628          * double buffered watermarks and so shouldn't need this.
13629          *
13630          * Unset state->legacy_cursor_update before the call to
13631          * drm_atomic_helper_setup_commit() because otherwise
13632          * drm_atomic_helper_wait_for_flip_done() is a noop and
13633          * we get FIFO underruns because we didn't wait
13634          * for vblank.
13635          *
13636          * FIXME doing watermarks and fb cleanup from a vblank worker
13637          * (assuming we had any) would solve these problems.
13638          */
13639         if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
13640                 struct intel_crtc_state *new_crtc_state;
13641                 struct intel_crtc *crtc;
13642                 int i;
13643
13644                 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
13645                         if (new_crtc_state->wm.need_postvbl_update ||
13646                             new_crtc_state->update_wm_post)
13647                                 state->legacy_cursor_update = false;
13648         }
13649
13650         ret = intel_atomic_prepare_commit(dev, state);
13651         if (ret) {
13652                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13653                 i915_sw_fence_commit(&intel_state->commit_ready);
13654                 return ret;
13655         }
13656
13657         ret = drm_atomic_helper_setup_commit(state, nonblock);
13658         if (!ret)
13659                 ret = drm_atomic_helper_swap_state(state, true);
13660
13661         if (ret) {
13662                 i915_sw_fence_commit(&intel_state->commit_ready);
13663
13664                 drm_atomic_helper_cleanup_planes(dev, state);
13665                 return ret;
13666         }
13667         dev_priv->wm.distrust_bios_wm = false;
13668         intel_shared_dpll_swap_state(state);
13669         intel_atomic_track_fbs(state);
13670
13671         if (intel_state->modeset) {
13672                 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
13673                        sizeof(intel_state->min_cdclk));
13674                 memcpy(dev_priv->min_voltage_level,
13675                        intel_state->min_voltage_level,
13676                        sizeof(intel_state->min_voltage_level));
13677                 dev_priv->active_crtcs = intel_state->active_crtcs;
13678                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13679                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13680         }
13681
13682         drm_atomic_state_get(state);
13683         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13684
13685         i915_sw_fence_commit(&intel_state->commit_ready);
13686         if (nonblock && intel_state->modeset) {
13687                 queue_work(dev_priv->modeset_wq, &state->commit_work);
13688         } else if (nonblock) {
13689                 queue_work(system_unbound_wq, &state->commit_work);
13690         } else {
13691                 if (intel_state->modeset)
13692                         flush_workqueue(dev_priv->modeset_wq);
13693                 intel_atomic_commit_tail(state);
13694         }
13695
13696         return 0;
13697 }
13698
13699 static const struct drm_crtc_funcs intel_crtc_funcs = {
13700         .gamma_set = drm_atomic_helper_legacy_gamma_set,
13701         .set_config = drm_atomic_helper_set_config,
13702         .destroy = intel_crtc_destroy,
13703         .page_flip = drm_atomic_helper_page_flip,
13704         .atomic_duplicate_state = intel_crtc_duplicate_state,
13705         .atomic_destroy_state = intel_crtc_destroy_state,
13706         .set_crc_source = intel_crtc_set_crc_source,
13707         .verify_crc_source = intel_crtc_verify_crc_source,
13708         .get_crc_sources = intel_crtc_get_crc_sources,
13709 };
13710
13711 struct wait_rps_boost {
13712         struct wait_queue_entry wait;
13713
13714         struct drm_crtc *crtc;
13715         struct i915_request *request;
13716 };
13717
13718 static int do_rps_boost(struct wait_queue_entry *_wait,
13719                         unsigned mode, int sync, void *key)
13720 {
13721         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
13722         struct i915_request *rq = wait->request;
13723
13724         /*
13725          * If we missed the vblank, but the request is already running it
13726          * is reasonable to assume that it will complete before the next
13727          * vblank without our intervention, so leave RPS alone.
13728          */
13729         if (!i915_request_started(rq))
13730                 gen6_rps_boost(rq);
13731         i915_request_put(rq);
13732
13733         drm_crtc_vblank_put(wait->crtc);
13734
13735         list_del(&wait->wait.entry);
13736         kfree(wait);
13737         return 1;
13738 }
13739
13740 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
13741                                        struct dma_fence *fence)
13742 {
13743         struct wait_rps_boost *wait;
13744
13745         if (!dma_fence_is_i915(fence))
13746                 return;
13747
13748         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
13749                 return;
13750
13751         if (drm_crtc_vblank_get(crtc))
13752                 return;
13753
13754         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
13755         if (!wait) {
13756                 drm_crtc_vblank_put(crtc);
13757                 return;
13758         }
13759
13760         wait->request = to_request(dma_fence_get(fence));
13761         wait->crtc = crtc;
13762
13763         wait->wait.func = do_rps_boost;
13764         wait->wait.flags = 0;
13765
13766         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
13767 }
13768
13769 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
13770 {
13771         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
13772         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13773         struct drm_framebuffer *fb = plane_state->base.fb;
13774         struct i915_vma *vma;
13775
13776         if (plane->id == PLANE_CURSOR &&
13777             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
13778                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13779                 const int align = intel_cursor_alignment(dev_priv);
13780                 int err;
13781
13782                 err = i915_gem_object_attach_phys(obj, align);
13783                 if (err)
13784                         return err;
13785         }
13786
13787         vma = intel_pin_and_fence_fb_obj(fb,
13788                                          &plane_state->view,
13789                                          intel_plane_uses_fence(plane_state),
13790                                          &plane_state->flags);
13791         if (IS_ERR(vma))
13792                 return PTR_ERR(vma);
13793
13794         plane_state->vma = vma;
13795
13796         return 0;
13797 }
13798
13799 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
13800 {
13801         struct i915_vma *vma;
13802
13803         vma = fetch_and_zero(&old_plane_state->vma);
13804         if (vma)
13805                 intel_unpin_fb_vma(vma, old_plane_state->flags);
13806 }
13807
13808 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
13809 {
13810         struct i915_sched_attr attr = {
13811                 .priority = I915_PRIORITY_DISPLAY,
13812         };
13813
13814         i915_gem_object_wait_priority(obj, 0, &attr);
13815 }
13816
13817 /**
13818  * intel_prepare_plane_fb - Prepare fb for usage on plane
13819  * @plane: drm plane to prepare for
13820  * @new_state: the plane state being prepared
13821  *
13822  * Prepares a framebuffer for usage on a display plane.  Generally this
13823  * involves pinning the underlying object and updating the frontbuffer tracking
13824  * bits.  Some older platforms need special physical address handling for
13825  * cursor planes.
13826  *
13827  * Must be called with struct_mutex held.
13828  *
13829  * Returns 0 on success, negative error code on failure.
13830  */
13831 int
13832 intel_prepare_plane_fb(struct drm_plane *plane,
13833                        struct drm_plane_state *new_state)
13834 {
13835         struct intel_atomic_state *intel_state =
13836                 to_intel_atomic_state(new_state->state);
13837         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13838         struct drm_framebuffer *fb = new_state->fb;
13839         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13840         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13841         int ret;
13842
13843         if (old_obj) {
13844                 struct drm_crtc_state *crtc_state =
13845                         drm_atomic_get_new_crtc_state(new_state->state,
13846                                                       plane->state->crtc);
13847
13848                 /* Big Hammer, we also need to ensure that any pending
13849                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13850                  * current scanout is retired before unpinning the old
13851                  * framebuffer. Note that we rely on userspace rendering
13852                  * into the buffer attached to the pipe they are waiting
13853                  * on. If not, userspace generates a GPU hang with IPEHR
13854                  * point to the MI_WAIT_FOR_EVENT.
13855                  *
13856                  * This should only fail upon a hung GPU, in which case we
13857                  * can safely continue.
13858                  */
13859                 if (needs_modeset(crtc_state)) {
13860                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13861                                                               old_obj->resv, NULL,
13862                                                               false, 0,
13863                                                               GFP_KERNEL);
13864                         if (ret < 0)
13865                                 return ret;
13866                 }
13867         }
13868
13869         if (new_state->fence) { /* explicit fencing */
13870                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13871                                                     new_state->fence,
13872                                                     I915_FENCE_TIMEOUT,
13873                                                     GFP_KERNEL);
13874                 if (ret < 0)
13875                         return ret;
13876         }
13877
13878         if (!obj)
13879                 return 0;
13880
13881         ret = i915_gem_object_pin_pages(obj);
13882         if (ret)
13883                 return ret;
13884
13885         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13886         if (ret) {
13887                 i915_gem_object_unpin_pages(obj);
13888                 return ret;
13889         }
13890
13891         ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
13892
13893         mutex_unlock(&dev_priv->drm.struct_mutex);
13894         i915_gem_object_unpin_pages(obj);
13895         if (ret)
13896                 return ret;
13897
13898         fb_obj_bump_render_priority(obj);
13899         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13900
13901         if (!new_state->fence) { /* implicit fencing */
13902                 struct dma_fence *fence;
13903
13904                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13905                                                       obj->resv, NULL,
13906                                                       false, I915_FENCE_TIMEOUT,
13907                                                       GFP_KERNEL);
13908                 if (ret < 0)
13909                         return ret;
13910
13911                 fence = reservation_object_get_excl_rcu(obj->resv);
13912                 if (fence) {
13913                         add_rps_boost_after_vblank(new_state->crtc, fence);
13914                         dma_fence_put(fence);
13915                 }
13916         } else {
13917                 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
13918         }
13919
13920         /*
13921          * We declare pageflips to be interactive and so merit a small bias
13922          * towards upclocking to deliver the frame on time. By only changing
13923          * the RPS thresholds to sample more regularly and aim for higher
13924          * clocks we can hopefully deliver low power workloads (like kodi)
13925          * that are not quite steady state without resorting to forcing
13926          * maximum clocks following a vblank miss (see do_rps_boost()).
13927          */
13928         if (!intel_state->rps_interactive) {
13929                 intel_rps_mark_interactive(dev_priv, true);
13930                 intel_state->rps_interactive = true;
13931         }
13932
13933         return 0;
13934 }
13935
13936 /**
13937  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13938  * @plane: drm plane to clean up for
13939  * @old_state: the state from the previous modeset
13940  *
13941  * Cleans up a framebuffer that has just been removed from a plane.
13942  *
13943  * Must be called with struct_mutex held.
13944  */
13945 void
13946 intel_cleanup_plane_fb(struct drm_plane *plane,
13947                        struct drm_plane_state *old_state)
13948 {
13949         struct intel_atomic_state *intel_state =
13950                 to_intel_atomic_state(old_state->state);
13951         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13952
13953         if (intel_state->rps_interactive) {
13954                 intel_rps_mark_interactive(dev_priv, false);
13955                 intel_state->rps_interactive = false;
13956         }
13957
13958         /* Should only be called after a successful intel_prepare_plane_fb()! */
13959         mutex_lock(&dev_priv->drm.struct_mutex);
13960         intel_plane_unpin_fb(to_intel_plane_state(old_state));
13961         mutex_unlock(&dev_priv->drm.struct_mutex);
13962 }
13963
13964 int
13965 skl_max_scale(const struct intel_crtc_state *crtc_state,
13966               u32 pixel_format)
13967 {
13968         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
13969         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13970         int max_scale, mult;
13971         int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
13972
13973         if (!crtc_state->base.enable)
13974                 return DRM_PLANE_HELPER_NO_SCALING;
13975
13976         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13977         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13978
13979         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
13980                 max_dotclk *= 2;
13981
13982         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13983                 return DRM_PLANE_HELPER_NO_SCALING;
13984
13985         /*
13986          * skl max scale is lower of:
13987          *    close to 3 but not 3, -1 is for that purpose
13988          *            or
13989          *    cdclk/crtc_clock
13990          */
13991         mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
13992         tmpclk1 = (1 << 16) * mult - 1;
13993         tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
13994         max_scale = min(tmpclk1, tmpclk2);
13995
13996         return max_scale;
13997 }
13998
13999 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14000                                     struct drm_crtc_state *old_crtc_state)
14001 {
14002         struct drm_device *dev = crtc->dev;
14003         struct drm_i915_private *dev_priv = to_i915(dev);
14004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14005         struct intel_crtc_state *old_intel_cstate =
14006                 to_intel_crtc_state(old_crtc_state);
14007         struct intel_atomic_state *old_intel_state =
14008                 to_intel_atomic_state(old_crtc_state->state);
14009         struct intel_crtc_state *intel_cstate =
14010                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
14011         bool modeset = needs_modeset(&intel_cstate->base);
14012
14013         /* Perform vblank evasion around commit operation */
14014         intel_pipe_update_start(intel_cstate);
14015
14016         if (modeset)
14017                 goto out;
14018
14019         if (intel_cstate->base.color_mgmt_changed ||
14020             intel_cstate->update_pipe)
14021                 intel_color_commit(intel_cstate);
14022
14023         if (intel_cstate->update_pipe)
14024                 intel_update_pipe_config(old_intel_cstate, intel_cstate);
14025         else if (INTEL_GEN(dev_priv) >= 9)
14026                 skl_detach_scalers(intel_cstate);
14027
14028 out:
14029         if (dev_priv->display.atomic_update_watermarks)
14030                 dev_priv->display.atomic_update_watermarks(old_intel_state,
14031                                                            intel_cstate);
14032 }
14033
14034 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14035                                   struct intel_crtc_state *crtc_state)
14036 {
14037         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14038
14039         if (!IS_GEN(dev_priv, 2))
14040                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14041
14042         if (crtc_state->has_pch_encoder) {
14043                 enum pipe pch_transcoder =
14044                         intel_crtc_pch_transcoder(crtc);
14045
14046                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14047         }
14048 }
14049
14050 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14051                                      struct drm_crtc_state *old_crtc_state)
14052 {
14053         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14054         struct intel_atomic_state *old_intel_state =
14055                 to_intel_atomic_state(old_crtc_state->state);
14056         struct intel_crtc_state *new_crtc_state =
14057                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
14058
14059         intel_pipe_update_end(new_crtc_state);
14060
14061         if (new_crtc_state->update_pipe &&
14062             !needs_modeset(&new_crtc_state->base) &&
14063             old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED)
14064                 intel_crtc_arm_fifo_underrun(intel_crtc, new_crtc_state);
14065 }
14066
14067 /**
14068  * intel_plane_destroy - destroy a plane
14069  * @plane: plane to destroy
14070  *
14071  * Common destruction function for all types of planes (primary, cursor,
14072  * sprite).
14073  */
14074 void intel_plane_destroy(struct drm_plane *plane)
14075 {
14076         drm_plane_cleanup(plane);
14077         kfree(to_intel_plane(plane));
14078 }
14079
14080 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
14081                                             u32 format, u64 modifier)
14082 {
14083         switch (modifier) {
14084         case DRM_FORMAT_MOD_LINEAR:
14085         case I915_FORMAT_MOD_X_TILED:
14086                 break;
14087         default:
14088                 return false;
14089         }
14090
14091         switch (format) {
14092         case DRM_FORMAT_C8:
14093         case DRM_FORMAT_RGB565:
14094         case DRM_FORMAT_XRGB1555:
14095         case DRM_FORMAT_XRGB8888:
14096                 return modifier == DRM_FORMAT_MOD_LINEAR ||
14097                         modifier == I915_FORMAT_MOD_X_TILED;
14098         default:
14099                 return false;
14100         }
14101 }
14102
14103 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
14104                                             u32 format, u64 modifier)
14105 {
14106         switch (modifier) {
14107         case DRM_FORMAT_MOD_LINEAR:
14108         case I915_FORMAT_MOD_X_TILED:
14109                 break;
14110         default:
14111                 return false;
14112         }
14113
14114         switch (format) {
14115         case DRM_FORMAT_C8:
14116         case DRM_FORMAT_RGB565:
14117         case DRM_FORMAT_XRGB8888:
14118         case DRM_FORMAT_XBGR8888:
14119         case DRM_FORMAT_XRGB2101010:
14120         case DRM_FORMAT_XBGR2101010:
14121                 return modifier == DRM_FORMAT_MOD_LINEAR ||
14122                         modifier == I915_FORMAT_MOD_X_TILED;
14123         default:
14124                 return false;
14125         }
14126 }
14127
14128 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
14129                                               u32 format, u64 modifier)
14130 {
14131         return modifier == DRM_FORMAT_MOD_LINEAR &&
14132                 format == DRM_FORMAT_ARGB8888;
14133 }
14134
14135 static const struct drm_plane_funcs i965_plane_funcs = {
14136         .update_plane = drm_atomic_helper_update_plane,
14137         .disable_plane = drm_atomic_helper_disable_plane,
14138         .destroy = intel_plane_destroy,
14139         .atomic_get_property = intel_plane_atomic_get_property,
14140         .atomic_set_property = intel_plane_atomic_set_property,
14141         .atomic_duplicate_state = intel_plane_duplicate_state,
14142         .atomic_destroy_state = intel_plane_destroy_state,
14143         .format_mod_supported = i965_plane_format_mod_supported,
14144 };
14145
14146 static const struct drm_plane_funcs i8xx_plane_funcs = {
14147         .update_plane = drm_atomic_helper_update_plane,
14148         .disable_plane = drm_atomic_helper_disable_plane,
14149         .destroy = intel_plane_destroy,
14150         .atomic_get_property = intel_plane_atomic_get_property,
14151         .atomic_set_property = intel_plane_atomic_set_property,
14152         .atomic_duplicate_state = intel_plane_duplicate_state,
14153         .atomic_destroy_state = intel_plane_destroy_state,
14154         .format_mod_supported = i8xx_plane_format_mod_supported,
14155 };
14156
14157 static int
14158 intel_legacy_cursor_update(struct drm_plane *plane,
14159                            struct drm_crtc *crtc,
14160                            struct drm_framebuffer *fb,
14161                            int crtc_x, int crtc_y,
14162                            unsigned int crtc_w, unsigned int crtc_h,
14163                            u32 src_x, u32 src_y,
14164                            u32 src_w, u32 src_h,
14165                            struct drm_modeset_acquire_ctx *ctx)
14166 {
14167         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
14168         int ret;
14169         struct drm_plane_state *old_plane_state, *new_plane_state;
14170         struct intel_plane *intel_plane = to_intel_plane(plane);
14171         struct drm_framebuffer *old_fb;
14172         struct intel_crtc_state *crtc_state =
14173                 to_intel_crtc_state(crtc->state);
14174         struct intel_crtc_state *new_crtc_state;
14175
14176         /*
14177          * When crtc is inactive or there is a modeset pending,
14178          * wait for it to complete in the slowpath
14179          */
14180         if (!crtc_state->base.active || needs_modeset(&crtc_state->base) ||
14181             crtc_state->update_pipe)
14182                 goto slow;
14183
14184         old_plane_state = plane->state;
14185         /*
14186          * Don't do an async update if there is an outstanding commit modifying
14187          * the plane.  This prevents our async update's changes from getting
14188          * overridden by a previous synchronous update's state.
14189          */
14190         if (old_plane_state->commit &&
14191             !try_wait_for_completion(&old_plane_state->commit->hw_done))
14192                 goto slow;
14193
14194         /*
14195          * If any parameters change that may affect watermarks,
14196          * take the slowpath. Only changing fb or position should be
14197          * in the fastpath.
14198          */
14199         if (old_plane_state->crtc != crtc ||
14200             old_plane_state->src_w != src_w ||
14201             old_plane_state->src_h != src_h ||
14202             old_plane_state->crtc_w != crtc_w ||
14203             old_plane_state->crtc_h != crtc_h ||
14204             !old_plane_state->fb != !fb)
14205                 goto slow;
14206
14207         new_plane_state = intel_plane_duplicate_state(plane);
14208         if (!new_plane_state)
14209                 return -ENOMEM;
14210
14211         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(crtc));
14212         if (!new_crtc_state) {
14213                 ret = -ENOMEM;
14214                 goto out_free;
14215         }
14216
14217         drm_atomic_set_fb_for_plane(new_plane_state, fb);
14218
14219         new_plane_state->src_x = src_x;
14220         new_plane_state->src_y = src_y;
14221         new_plane_state->src_w = src_w;
14222         new_plane_state->src_h = src_h;
14223         new_plane_state->crtc_x = crtc_x;
14224         new_plane_state->crtc_y = crtc_y;
14225         new_plane_state->crtc_w = crtc_w;
14226         new_plane_state->crtc_h = crtc_h;
14227
14228         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
14229                                                   to_intel_plane_state(old_plane_state),
14230                                                   to_intel_plane_state(new_plane_state));
14231         if (ret)
14232                 goto out_free;
14233
14234         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
14235         if (ret)
14236                 goto out_free;
14237
14238         ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
14239         if (ret)
14240                 goto out_unlock;
14241
14242         intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP);
14243
14244         old_fb = old_plane_state->fb;
14245         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
14246                           intel_plane->frontbuffer_bit);
14247
14248         /* Swap plane state */
14249         plane->state = new_plane_state;
14250
14251         /*
14252          * We cannot swap crtc_state as it may be in use by an atomic commit or
14253          * page flip that's running simultaneously. If we swap crtc_state and
14254          * destroy the old state, we will cause a use-after-free there.
14255          *
14256          * Only update active_planes, which is needed for our internal
14257          * bookkeeping. Either value will do the right thing when updating
14258          * planes atomically. If the cursor was part of the atomic update then
14259          * we would have taken the slowpath.
14260          */
14261         crtc_state->active_planes = new_crtc_state->active_planes;
14262
14263         if (plane->state->visible)
14264                 intel_update_plane(intel_plane, crtc_state,
14265                                    to_intel_plane_state(plane->state));
14266         else
14267                 intel_disable_plane(intel_plane, crtc_state);
14268
14269         intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
14270
14271 out_unlock:
14272         mutex_unlock(&dev_priv->drm.struct_mutex);
14273 out_free:
14274         if (new_crtc_state)
14275                 intel_crtc_destroy_state(crtc, &new_crtc_state->base);
14276         if (ret)
14277                 intel_plane_destroy_state(plane, new_plane_state);
14278         else
14279                 intel_plane_destroy_state(plane, old_plane_state);
14280         return ret;
14281
14282 slow:
14283         return drm_atomic_helper_update_plane(plane, crtc, fb,
14284                                               crtc_x, crtc_y, crtc_w, crtc_h,
14285                                               src_x, src_y, src_w, src_h, ctx);
14286 }
14287
14288 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
14289         .update_plane = intel_legacy_cursor_update,
14290         .disable_plane = drm_atomic_helper_disable_plane,
14291         .destroy = intel_plane_destroy,
14292         .atomic_get_property = intel_plane_atomic_get_property,
14293         .atomic_set_property = intel_plane_atomic_set_property,
14294         .atomic_duplicate_state = intel_plane_duplicate_state,
14295         .atomic_destroy_state = intel_plane_destroy_state,
14296         .format_mod_supported = intel_cursor_format_mod_supported,
14297 };
14298
14299 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
14300                                enum i9xx_plane_id i9xx_plane)
14301 {
14302         if (!HAS_FBC(dev_priv))
14303                 return false;
14304
14305         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
14306                 return i9xx_plane == PLANE_A; /* tied to pipe A */
14307         else if (IS_IVYBRIDGE(dev_priv))
14308                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
14309                         i9xx_plane == PLANE_C;
14310         else if (INTEL_GEN(dev_priv) >= 4)
14311                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
14312         else
14313                 return i9xx_plane == PLANE_A;
14314 }
14315
14316 static struct intel_plane *
14317 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
14318 {
14319         struct intel_plane *plane;
14320         const struct drm_plane_funcs *plane_funcs;
14321         unsigned int supported_rotations;
14322         unsigned int possible_crtcs;
14323         const u64 *modifiers;
14324         const u32 *formats;
14325         int num_formats;
14326         int ret;
14327
14328         if (INTEL_GEN(dev_priv) >= 9)
14329                 return skl_universal_plane_create(dev_priv, pipe,
14330                                                   PLANE_PRIMARY);
14331
14332         plane = intel_plane_alloc();
14333         if (IS_ERR(plane))
14334                 return plane;
14335
14336         plane->pipe = pipe;
14337         /*
14338          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14339          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14340          */
14341         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
14342                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
14343         else
14344                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
14345         plane->id = PLANE_PRIMARY;
14346         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
14347
14348         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
14349         if (plane->has_fbc) {
14350                 struct intel_fbc *fbc = &dev_priv->fbc;
14351
14352                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
14353         }
14354
14355         if (INTEL_GEN(dev_priv) >= 4) {
14356                 formats = i965_primary_formats;
14357                 num_formats = ARRAY_SIZE(i965_primary_formats);
14358                 modifiers = i9xx_format_modifiers;
14359
14360                 plane->max_stride = i9xx_plane_max_stride;
14361                 plane->update_plane = i9xx_update_plane;
14362                 plane->disable_plane = i9xx_disable_plane;
14363                 plane->get_hw_state = i9xx_plane_get_hw_state;
14364                 plane->check_plane = i9xx_plane_check;
14365
14366                 plane_funcs = &i965_plane_funcs;
14367         } else {
14368                 formats = i8xx_primary_formats;
14369                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14370                 modifiers = i9xx_format_modifiers;
14371
14372                 plane->max_stride = i9xx_plane_max_stride;
14373                 plane->update_plane = i9xx_update_plane;
14374                 plane->disable_plane = i9xx_disable_plane;
14375                 plane->get_hw_state = i9xx_plane_get_hw_state;
14376                 plane->check_plane = i9xx_plane_check;
14377
14378                 plane_funcs = &i8xx_plane_funcs;
14379         }
14380
14381         possible_crtcs = BIT(pipe);
14382
14383         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
14384                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
14385                                                possible_crtcs, plane_funcs,
14386                                                formats, num_formats, modifiers,
14387                                                DRM_PLANE_TYPE_PRIMARY,
14388                                                "primary %c", pipe_name(pipe));
14389         else
14390                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
14391                                                possible_crtcs, plane_funcs,
14392                                                formats, num_formats, modifiers,
14393                                                DRM_PLANE_TYPE_PRIMARY,
14394                                                "plane %c",
14395                                                plane_name(plane->i9xx_plane));
14396         if (ret)
14397                 goto fail;
14398
14399         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
14400                 supported_rotations =
14401                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
14402                         DRM_MODE_REFLECT_X;
14403         } else if (INTEL_GEN(dev_priv) >= 4) {
14404                 supported_rotations =
14405                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
14406         } else {
14407                 supported_rotations = DRM_MODE_ROTATE_0;
14408         }
14409
14410         if (INTEL_GEN(dev_priv) >= 4)
14411                 drm_plane_create_rotation_property(&plane->base,
14412                                                    DRM_MODE_ROTATE_0,
14413                                                    supported_rotations);
14414
14415         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
14416
14417         return plane;
14418
14419 fail:
14420         intel_plane_free(plane);
14421
14422         return ERR_PTR(ret);
14423 }
14424
14425 static struct intel_plane *
14426 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
14427                           enum pipe pipe)
14428 {
14429         unsigned int possible_crtcs;
14430         struct intel_plane *cursor;
14431         int ret;
14432
14433         cursor = intel_plane_alloc();
14434         if (IS_ERR(cursor))
14435                 return cursor;
14436
14437         cursor->pipe = pipe;
14438         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
14439         cursor->id = PLANE_CURSOR;
14440         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
14441
14442         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14443                 cursor->max_stride = i845_cursor_max_stride;
14444                 cursor->update_plane = i845_update_cursor;
14445                 cursor->disable_plane = i845_disable_cursor;
14446                 cursor->get_hw_state = i845_cursor_get_hw_state;
14447                 cursor->check_plane = i845_check_cursor;
14448         } else {
14449                 cursor->max_stride = i9xx_cursor_max_stride;
14450                 cursor->update_plane = i9xx_update_cursor;
14451                 cursor->disable_plane = i9xx_disable_cursor;
14452                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
14453                 cursor->check_plane = i9xx_check_cursor;
14454         }
14455
14456         cursor->cursor.base = ~0;
14457         cursor->cursor.cntl = ~0;
14458
14459         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
14460                 cursor->cursor.size = ~0;
14461
14462         possible_crtcs = BIT(pipe);
14463
14464         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
14465                                        possible_crtcs, &intel_cursor_plane_funcs,
14466                                        intel_cursor_formats,
14467                                        ARRAY_SIZE(intel_cursor_formats),
14468                                        cursor_format_modifiers,
14469                                        DRM_PLANE_TYPE_CURSOR,
14470                                        "cursor %c", pipe_name(pipe));
14471         if (ret)
14472                 goto fail;
14473
14474         if (INTEL_GEN(dev_priv) >= 4)
14475                 drm_plane_create_rotation_property(&cursor->base,
14476                                                    DRM_MODE_ROTATE_0,
14477                                                    DRM_MODE_ROTATE_0 |
14478                                                    DRM_MODE_ROTATE_180);
14479
14480         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14481
14482         return cursor;
14483
14484 fail:
14485         intel_plane_free(cursor);
14486
14487         return ERR_PTR(ret);
14488 }
14489
14490 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
14491                                     struct intel_crtc_state *crtc_state)
14492 {
14493         struct intel_crtc_scaler_state *scaler_state =
14494                 &crtc_state->scaler_state;
14495         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14496         int i;
14497
14498         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
14499         if (!crtc->num_scalers)
14500                 return;
14501
14502         for (i = 0; i < crtc->num_scalers; i++) {
14503                 struct intel_scaler *scaler = &scaler_state->scalers[i];
14504
14505                 scaler->in_use = 0;
14506                 scaler->mode = 0;
14507         }
14508
14509         scaler_state->scaler_id = -1;
14510 }
14511
14512 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
14513 {
14514         struct intel_crtc *intel_crtc;
14515         struct intel_crtc_state *crtc_state = NULL;
14516         struct intel_plane *primary = NULL;
14517         struct intel_plane *cursor = NULL;
14518         int sprite, ret;
14519
14520         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14521         if (!intel_crtc)
14522                 return -ENOMEM;
14523
14524         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14525         if (!crtc_state) {
14526                 ret = -ENOMEM;
14527                 goto fail;
14528         }
14529         intel_crtc->config = crtc_state;
14530         intel_crtc->base.state = &crtc_state->base;
14531         crtc_state->base.crtc = &intel_crtc->base;
14532
14533         primary = intel_primary_plane_create(dev_priv, pipe);
14534         if (IS_ERR(primary)) {
14535                 ret = PTR_ERR(primary);
14536                 goto fail;
14537         }
14538         intel_crtc->plane_ids_mask |= BIT(primary->id);
14539
14540         for_each_sprite(dev_priv, pipe, sprite) {
14541                 struct intel_plane *plane;
14542
14543                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
14544                 if (IS_ERR(plane)) {
14545                         ret = PTR_ERR(plane);
14546                         goto fail;
14547                 }
14548                 intel_crtc->plane_ids_mask |= BIT(plane->id);
14549         }
14550
14551         cursor = intel_cursor_plane_create(dev_priv, pipe);
14552         if (IS_ERR(cursor)) {
14553                 ret = PTR_ERR(cursor);
14554                 goto fail;
14555         }
14556         intel_crtc->plane_ids_mask |= BIT(cursor->id);
14557
14558         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
14559                                         &primary->base, &cursor->base,
14560                                         &intel_crtc_funcs,
14561                                         "pipe %c", pipe_name(pipe));
14562         if (ret)
14563                 goto fail;
14564
14565         intel_crtc->pipe = pipe;
14566
14567         /* initialize shared scalers */
14568         intel_crtc_init_scalers(intel_crtc, crtc_state);
14569
14570         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
14571                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
14572         dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
14573
14574         if (INTEL_GEN(dev_priv) < 9) {
14575                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
14576
14577                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14578                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
14579                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
14580         }
14581
14582         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14583
14584         intel_color_init(intel_crtc);
14585
14586         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14587
14588         return 0;
14589
14590 fail:
14591         /*
14592          * drm_mode_config_cleanup() will free up any
14593          * crtcs/planes already initialized.
14594          */
14595         kfree(crtc_state);
14596         kfree(intel_crtc);
14597
14598         return ret;
14599 }
14600
14601 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
14602                                       struct drm_file *file)
14603 {
14604         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14605         struct drm_crtc *drmmode_crtc;
14606         struct intel_crtc *crtc;
14607
14608         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
14609         if (!drmmode_crtc)
14610                 return -ENOENT;
14611
14612         crtc = to_intel_crtc(drmmode_crtc);
14613         pipe_from_crtc_id->pipe = crtc->pipe;
14614
14615         return 0;
14616 }
14617
14618 static int intel_encoder_clones(struct intel_encoder *encoder)
14619 {
14620         struct drm_device *dev = encoder->base.dev;
14621         struct intel_encoder *source_encoder;
14622         int index_mask = 0;
14623         int entry = 0;
14624
14625         for_each_intel_encoder(dev, source_encoder) {
14626                 if (encoders_cloneable(encoder, source_encoder))
14627                         index_mask |= (1 << entry);
14628
14629                 entry++;
14630         }
14631
14632         return index_mask;
14633 }
14634
14635 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
14636 {
14637         if (!IS_MOBILE(dev_priv))
14638                 return false;
14639
14640         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14641                 return false;
14642
14643         if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14644                 return false;
14645
14646         return true;
14647 }
14648
14649 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
14650 {
14651         if (INTEL_GEN(dev_priv) >= 9)
14652                 return false;
14653
14654         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14655                 return false;
14656
14657         if (HAS_PCH_LPT_H(dev_priv) &&
14658             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14659                 return false;
14660
14661         /* DDI E can't be used if DDI A requires 4 lanes */
14662         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14663                 return false;
14664
14665         if (!dev_priv->vbt.int_crt_support)
14666                 return false;
14667
14668         return true;
14669 }
14670
14671 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14672 {
14673         int pps_num;
14674         int pps_idx;
14675
14676         if (HAS_DDI(dev_priv))
14677                 return;
14678         /*
14679          * This w/a is needed at least on CPT/PPT, but to be sure apply it
14680          * everywhere where registers can be write protected.
14681          */
14682         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14683                 pps_num = 2;
14684         else
14685                 pps_num = 1;
14686
14687         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14688                 u32 val = I915_READ(PP_CONTROL(pps_idx));
14689
14690                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14691                 I915_WRITE(PP_CONTROL(pps_idx), val);
14692         }
14693 }
14694
14695 static void intel_pps_init(struct drm_i915_private *dev_priv)
14696 {
14697         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14698                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14699         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14700                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14701         else
14702                 dev_priv->pps_mmio_base = PPS_BASE;
14703
14704         intel_pps_unlock_regs_wa(dev_priv);
14705 }
14706
14707 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14708 {
14709         struct intel_encoder *encoder;
14710         bool dpd_is_edp = false;
14711
14712         intel_pps_init(dev_priv);
14713
14714         if (!HAS_DISPLAY(dev_priv))
14715                 return;
14716
14717         if (IS_ELKHARTLAKE(dev_priv)) {
14718                 intel_ddi_init(dev_priv, PORT_A);
14719                 intel_ddi_init(dev_priv, PORT_B);
14720                 intel_ddi_init(dev_priv, PORT_C);
14721                 icl_dsi_init(dev_priv);
14722         } else if (INTEL_GEN(dev_priv) >= 11) {
14723                 intel_ddi_init(dev_priv, PORT_A);
14724                 intel_ddi_init(dev_priv, PORT_B);
14725                 intel_ddi_init(dev_priv, PORT_C);
14726                 intel_ddi_init(dev_priv, PORT_D);
14727                 intel_ddi_init(dev_priv, PORT_E);
14728                 /*
14729                  * On some ICL SKUs port F is not present. No strap bits for
14730                  * this, so rely on VBT.
14731                  * Work around broken VBTs on SKUs known to have no port F.
14732                  */
14733                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
14734                     intel_bios_is_port_present(dev_priv, PORT_F))
14735                         intel_ddi_init(dev_priv, PORT_F);
14736
14737                 icl_dsi_init(dev_priv);
14738         } else if (IS_GEN9_LP(dev_priv)) {
14739                 /*
14740                  * FIXME: Broxton doesn't support port detection via the
14741                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14742                  * detect the ports.
14743                  */
14744                 intel_ddi_init(dev_priv, PORT_A);
14745                 intel_ddi_init(dev_priv, PORT_B);
14746                 intel_ddi_init(dev_priv, PORT_C);
14747
14748                 vlv_dsi_init(dev_priv);
14749         } else if (HAS_DDI(dev_priv)) {
14750                 int found;
14751
14752                 if (intel_ddi_crt_present(dev_priv))
14753                         intel_crt_init(dev_priv);
14754
14755                 /*
14756                  * Haswell uses DDI functions to detect digital outputs.
14757                  * On SKL pre-D0 the strap isn't connected, so we assume
14758                  * it's there.
14759                  */
14760                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14761                 /* WaIgnoreDDIAStrap: skl */
14762                 if (found || IS_GEN9_BC(dev_priv))
14763                         intel_ddi_init(dev_priv, PORT_A);
14764
14765                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
14766                  * register */
14767                 found = I915_READ(SFUSE_STRAP);
14768
14769                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14770                         intel_ddi_init(dev_priv, PORT_B);
14771                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14772                         intel_ddi_init(dev_priv, PORT_C);
14773                 if (found & SFUSE_STRAP_DDID_DETECTED)
14774                         intel_ddi_init(dev_priv, PORT_D);
14775                 if (found & SFUSE_STRAP_DDIF_DETECTED)
14776                         intel_ddi_init(dev_priv, PORT_F);
14777                 /*
14778                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14779                  */
14780                 if (IS_GEN9_BC(dev_priv) &&
14781                     intel_bios_is_port_present(dev_priv, PORT_E))
14782                         intel_ddi_init(dev_priv, PORT_E);
14783
14784         } else if (HAS_PCH_SPLIT(dev_priv)) {
14785                 int found;
14786
14787                 /*
14788                  * intel_edp_init_connector() depends on this completing first,
14789                  * to prevent the registration of both eDP and LVDS and the
14790                  * incorrect sharing of the PPS.
14791                  */
14792                 intel_lvds_init(dev_priv);
14793                 intel_crt_init(dev_priv);
14794
14795                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
14796
14797                 if (ilk_has_edp_a(dev_priv))
14798                         intel_dp_init(dev_priv, DP_A, PORT_A);
14799
14800                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14801                         /* PCH SDVOB multiplex with HDMIB */
14802                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14803                         if (!found)
14804                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14805                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14806                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14807                 }
14808
14809                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14810                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14811
14812                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14813                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14814
14815                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14816                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14817
14818                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14819                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14820         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14821                 bool has_edp, has_port;
14822
14823                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
14824                         intel_crt_init(dev_priv);
14825
14826                 /*
14827                  * The DP_DETECTED bit is the latched state of the DDC
14828                  * SDA pin at boot. However since eDP doesn't require DDC
14829                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14830                  * eDP ports may have been muxed to an alternate function.
14831                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14832                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14833                  * detect eDP ports.
14834                  *
14835                  * Sadly the straps seem to be missing sometimes even for HDMI
14836                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14837                  * and VBT for the presence of the port. Additionally we can't
14838                  * trust the port type the VBT declares as we've seen at least
14839                  * HDMI ports that the VBT claim are DP or eDP.
14840                  */
14841                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
14842                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14843                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14844                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14845                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14846                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14847
14848                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
14849                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14850                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14851                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14852                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14853                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14854
14855                 if (IS_CHERRYVIEW(dev_priv)) {
14856                         /*
14857                          * eDP not supported on port D,
14858                          * so no need to worry about it
14859                          */
14860                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14861                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14862                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14863                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14864                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14865                 }
14866
14867                 vlv_dsi_init(dev_priv);
14868         } else if (IS_PINEVIEW(dev_priv)) {
14869                 intel_lvds_init(dev_priv);
14870                 intel_crt_init(dev_priv);
14871         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
14872                 bool found = false;
14873
14874                 if (IS_MOBILE(dev_priv))
14875                         intel_lvds_init(dev_priv);
14876
14877                 intel_crt_init(dev_priv);
14878
14879                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14880                         DRM_DEBUG_KMS("probing SDVOB\n");
14881                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14882                         if (!found && IS_G4X(dev_priv)) {
14883                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14884                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14885                         }
14886
14887                         if (!found && IS_G4X(dev_priv))
14888                                 intel_dp_init(dev_priv, DP_B, PORT_B);
14889                 }
14890
14891                 /* Before G4X SDVOC doesn't have its own detect register */
14892
14893                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14894                         DRM_DEBUG_KMS("probing SDVOC\n");
14895                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14896                 }
14897
14898                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14899
14900                         if (IS_G4X(dev_priv)) {
14901                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14902                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14903                         }
14904                         if (IS_G4X(dev_priv))
14905                                 intel_dp_init(dev_priv, DP_C, PORT_C);
14906                 }
14907
14908                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14909                         intel_dp_init(dev_priv, DP_D, PORT_D);
14910
14911                 if (SUPPORTS_TV(dev_priv))
14912                         intel_tv_init(dev_priv);
14913         } else if (IS_GEN(dev_priv, 2)) {
14914                 if (IS_I85X(dev_priv))
14915                         intel_lvds_init(dev_priv);
14916
14917                 intel_crt_init(dev_priv);
14918                 intel_dvo_init(dev_priv);
14919         }
14920
14921         intel_psr_init(dev_priv);
14922
14923         for_each_intel_encoder(&dev_priv->drm, encoder) {
14924                 encoder->base.possible_crtcs = encoder->crtc_mask;
14925                 encoder->base.possible_clones =
14926                         intel_encoder_clones(encoder);
14927         }
14928
14929         intel_init_pch_refclk(dev_priv);
14930
14931         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14932 }
14933
14934 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14935 {
14936         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14937         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14938
14939         drm_framebuffer_cleanup(fb);
14940
14941         i915_gem_object_lock(obj);
14942         WARN_ON(!obj->framebuffer_references--);
14943         i915_gem_object_unlock(obj);
14944
14945         i915_gem_object_put(obj);
14946
14947         kfree(intel_fb);
14948 }
14949
14950 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14951                                                 struct drm_file *file,
14952                                                 unsigned int *handle)
14953 {
14954         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14955
14956         if (obj->userptr.mm) {
14957                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14958                 return -EINVAL;
14959         }
14960
14961         return drm_gem_handle_create(file, &obj->base, handle);
14962 }
14963
14964 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14965                                         struct drm_file *file,
14966                                         unsigned flags, unsigned color,
14967                                         struct drm_clip_rect *clips,
14968                                         unsigned num_clips)
14969 {
14970         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14971
14972         i915_gem_object_flush_if_display(obj);
14973         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14974
14975         return 0;
14976 }
14977
14978 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14979         .destroy = intel_user_framebuffer_destroy,
14980         .create_handle = intel_user_framebuffer_create_handle,
14981         .dirty = intel_user_framebuffer_dirty,
14982 };
14983
14984 static
14985 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14986                          u32 pixel_format, u64 fb_modifier)
14987 {
14988         struct intel_crtc *crtc;
14989         struct intel_plane *plane;
14990
14991         /*
14992          * We assume the primary plane for pipe A has
14993          * the highest stride limits of them all.
14994          */
14995         crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
14996         plane = to_intel_plane(crtc->base.primary);
14997
14998         return plane->max_stride(plane, pixel_format, fb_modifier,
14999                                  DRM_MODE_ROTATE_0);
15000 }
15001
15002 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
15003                                   struct drm_i915_gem_object *obj,
15004                                   struct drm_mode_fb_cmd2 *mode_cmd)
15005 {
15006         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
15007         struct drm_framebuffer *fb = &intel_fb->base;
15008         u32 pitch_limit;
15009         unsigned int tiling, stride;
15010         int ret = -EINVAL;
15011         int i;
15012
15013         i915_gem_object_lock(obj);
15014         obj->framebuffer_references++;
15015         tiling = i915_gem_object_get_tiling(obj);
15016         stride = i915_gem_object_get_stride(obj);
15017         i915_gem_object_unlock(obj);
15018
15019         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15020                 /*
15021                  * If there's a fence, enforce that
15022                  * the fb modifier and tiling mode match.
15023                  */
15024                 if (tiling != I915_TILING_NONE &&
15025                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15026                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
15027                         goto err;
15028                 }
15029         } else {
15030                 if (tiling == I915_TILING_X) {
15031                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15032                 } else if (tiling == I915_TILING_Y) {
15033                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
15034                         goto err;
15035                 }
15036         }
15037
15038         if (!drm_any_plane_has_format(&dev_priv->drm,
15039                                       mode_cmd->pixel_format,
15040                                       mode_cmd->modifier[0])) {
15041                 struct drm_format_name_buf format_name;
15042
15043                 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
15044                               drm_get_format_name(mode_cmd->pixel_format,
15045                                                   &format_name),
15046                               mode_cmd->modifier[0]);
15047                 goto err;
15048         }
15049
15050         /*
15051          * gen2/3 display engine uses the fence if present,
15052          * so the tiling mode must match the fb modifier exactly.
15053          */
15054         if (INTEL_GEN(dev_priv) < 4 &&
15055             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15056                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
15057                 goto err;
15058         }
15059
15060         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->pixel_format,
15061                                            mode_cmd->modifier[0]);
15062         if (mode_cmd->pitches[0] > pitch_limit) {
15063                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
15064                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
15065                               "tiled" : "linear",
15066                               mode_cmd->pitches[0], pitch_limit);
15067                 goto err;
15068         }
15069
15070         /*
15071          * If there's a fence, enforce that
15072          * the fb pitch and fence stride match.
15073          */
15074         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
15075                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
15076                               mode_cmd->pitches[0], stride);
15077                 goto err;
15078         }
15079
15080         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15081         if (mode_cmd->offsets[0] != 0)
15082                 goto err;
15083
15084         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
15085
15086         for (i = 0; i < fb->format->num_planes; i++) {
15087                 u32 stride_alignment;
15088
15089                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
15090                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
15091                         goto err;
15092                 }
15093
15094                 stride_alignment = intel_fb_stride_alignment(fb, i);
15095
15096                 /*
15097                  * Display WA #0531: skl,bxt,kbl,glk
15098                  *
15099                  * Render decompression and plane width > 3840
15100                  * combined with horizontal panning requires the
15101                  * plane stride to be a multiple of 4. We'll just
15102                  * require the entire fb to accommodate that to avoid
15103                  * potential runtime errors at plane configuration time.
15104                  */
15105                 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
15106                     is_ccs_modifier(fb->modifier))
15107                         stride_alignment *= 4;
15108
15109                 if (fb->pitches[i] & (stride_alignment - 1)) {
15110                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
15111                                       i, fb->pitches[i], stride_alignment);
15112                         goto err;
15113                 }
15114
15115                 fb->obj[i] = &obj->base;
15116         }
15117
15118         ret = intel_fill_fb_info(dev_priv, fb);
15119         if (ret)
15120                 goto err;
15121
15122         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
15123         if (ret) {
15124                 DRM_ERROR("framebuffer init failed %d\n", ret);
15125                 goto err;
15126         }
15127
15128         return 0;
15129
15130 err:
15131         i915_gem_object_lock(obj);
15132         obj->framebuffer_references--;
15133         i915_gem_object_unlock(obj);
15134         return ret;
15135 }
15136
15137 static struct drm_framebuffer *
15138 intel_user_framebuffer_create(struct drm_device *dev,
15139                               struct drm_file *filp,
15140                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15141 {
15142         struct drm_framebuffer *fb;
15143         struct drm_i915_gem_object *obj;
15144         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15145
15146         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15147         if (!obj)
15148                 return ERR_PTR(-ENOENT);
15149
15150         fb = intel_framebuffer_create(obj, &mode_cmd);
15151         if (IS_ERR(fb))
15152                 i915_gem_object_put(obj);
15153
15154         return fb;
15155 }
15156
15157 static void intel_atomic_state_free(struct drm_atomic_state *state)
15158 {
15159         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
15160
15161         drm_atomic_state_default_release(state);
15162
15163         i915_sw_fence_fini(&intel_state->commit_ready);
15164
15165         kfree(state);
15166 }
15167
15168 static enum drm_mode_status
15169 intel_mode_valid(struct drm_device *dev,
15170                  const struct drm_display_mode *mode)
15171 {
15172         struct drm_i915_private *dev_priv = to_i915(dev);
15173         int hdisplay_max, htotal_max;
15174         int vdisplay_max, vtotal_max;
15175
15176         /*
15177          * Can't reject DBLSCAN here because Xorg ddxen can add piles
15178          * of DBLSCAN modes to the output's mode list when they detect
15179          * the scaling mode property on the connector. And they don't
15180          * ask the kernel to validate those modes in any way until
15181          * modeset time at which point the client gets a protocol error.
15182          * So in order to not upset those clients we silently ignore the
15183          * DBLSCAN flag on such connectors. For other connectors we will
15184          * reject modes with the DBLSCAN flag in encoder->compute_config().
15185          * And we always reject DBLSCAN modes in connector->mode_valid()
15186          * as we never want such modes on the connector's mode list.
15187          */
15188
15189         if (mode->vscan > 1)
15190                 return MODE_NO_VSCAN;
15191
15192         if (mode->flags & DRM_MODE_FLAG_HSKEW)
15193                 return MODE_H_ILLEGAL;
15194
15195         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
15196                            DRM_MODE_FLAG_NCSYNC |
15197                            DRM_MODE_FLAG_PCSYNC))
15198                 return MODE_HSYNC;
15199
15200         if (mode->flags & (DRM_MODE_FLAG_BCAST |
15201                            DRM_MODE_FLAG_PIXMUX |
15202                            DRM_MODE_FLAG_CLKDIV2))
15203                 return MODE_BAD;
15204
15205         if (INTEL_GEN(dev_priv) >= 9 ||
15206             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
15207                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
15208                 vdisplay_max = 4096;
15209                 htotal_max = 8192;
15210                 vtotal_max = 8192;
15211         } else if (INTEL_GEN(dev_priv) >= 3) {
15212                 hdisplay_max = 4096;
15213                 vdisplay_max = 4096;
15214                 htotal_max = 8192;
15215                 vtotal_max = 8192;
15216         } else {
15217                 hdisplay_max = 2048;
15218                 vdisplay_max = 2048;
15219                 htotal_max = 4096;
15220                 vtotal_max = 4096;
15221         }
15222
15223         if (mode->hdisplay > hdisplay_max ||
15224             mode->hsync_start > htotal_max ||
15225             mode->hsync_end > htotal_max ||
15226             mode->htotal > htotal_max)
15227                 return MODE_H_ILLEGAL;
15228
15229         if (mode->vdisplay > vdisplay_max ||
15230             mode->vsync_start > vtotal_max ||
15231             mode->vsync_end > vtotal_max ||
15232             mode->vtotal > vtotal_max)
15233                 return MODE_V_ILLEGAL;
15234
15235         return MODE_OK;
15236 }
15237
15238 static const struct drm_mode_config_funcs intel_mode_funcs = {
15239         .fb_create = intel_user_framebuffer_create,
15240         .get_format_info = intel_get_format_info,
15241         .output_poll_changed = intel_fbdev_output_poll_changed,
15242         .mode_valid = intel_mode_valid,
15243         .atomic_check = intel_atomic_check,
15244         .atomic_commit = intel_atomic_commit,
15245         .atomic_state_alloc = intel_atomic_state_alloc,
15246         .atomic_state_clear = intel_atomic_state_clear,
15247         .atomic_state_free = intel_atomic_state_free,
15248 };
15249
15250 /**
15251  * intel_init_display_hooks - initialize the display modesetting hooks
15252  * @dev_priv: device private
15253  */
15254 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15255 {
15256         intel_init_cdclk_hooks(dev_priv);
15257
15258         if (INTEL_GEN(dev_priv) >= 9) {
15259                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15260                 dev_priv->display.get_initial_plane_config =
15261                         skylake_get_initial_plane_config;
15262                 dev_priv->display.crtc_compute_clock =
15263                         haswell_crtc_compute_clock;
15264                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15265                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15266         } else if (HAS_DDI(dev_priv)) {
15267                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15268                 dev_priv->display.get_initial_plane_config =
15269                         i9xx_get_initial_plane_config;
15270                 dev_priv->display.crtc_compute_clock =
15271                         haswell_crtc_compute_clock;
15272                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15273                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15274         } else if (HAS_PCH_SPLIT(dev_priv)) {
15275                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15276                 dev_priv->display.get_initial_plane_config =
15277                         i9xx_get_initial_plane_config;
15278                 dev_priv->display.crtc_compute_clock =
15279                         ironlake_crtc_compute_clock;
15280                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15281                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15282         } else if (IS_CHERRYVIEW(dev_priv)) {
15283                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15284                 dev_priv->display.get_initial_plane_config =
15285                         i9xx_get_initial_plane_config;
15286                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15287                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15288                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15289         } else if (IS_VALLEYVIEW(dev_priv)) {
15290                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15291                 dev_priv->display.get_initial_plane_config =
15292                         i9xx_get_initial_plane_config;
15293                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15294                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15295                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15296         } else if (IS_G4X(dev_priv)) {
15297                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15298                 dev_priv->display.get_initial_plane_config =
15299                         i9xx_get_initial_plane_config;
15300                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15301                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15302                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15303         } else if (IS_PINEVIEW(dev_priv)) {
15304                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15305                 dev_priv->display.get_initial_plane_config =
15306                         i9xx_get_initial_plane_config;
15307                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15308                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15309                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15310         } else if (!IS_GEN(dev_priv, 2)) {
15311                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15312                 dev_priv->display.get_initial_plane_config =
15313                         i9xx_get_initial_plane_config;
15314                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15315                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15316                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15317         } else {
15318                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15319                 dev_priv->display.get_initial_plane_config =
15320                         i9xx_get_initial_plane_config;
15321                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15322                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15323                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15324         }
15325
15326         if (IS_GEN(dev_priv, 5)) {
15327                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15328         } else if (IS_GEN(dev_priv, 6)) {
15329                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15330         } else if (IS_IVYBRIDGE(dev_priv)) {
15331                 /* FIXME: detect B0+ stepping and use auto training */
15332                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15333         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15334                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15335         }
15336
15337         if (INTEL_GEN(dev_priv) >= 9)
15338                 dev_priv->display.update_crtcs = skl_update_crtcs;
15339         else
15340                 dev_priv->display.update_crtcs = intel_update_crtcs;
15341 }
15342
15343 /* Disable the VGA plane that we never use */
15344 static void i915_disable_vga(struct drm_i915_private *dev_priv)
15345 {
15346         struct pci_dev *pdev = dev_priv->drm.pdev;
15347         u8 sr1;
15348         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15349
15350         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15351         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
15352         outb(SR01, VGA_SR_INDEX);
15353         sr1 = inb(VGA_SR_DATA);
15354         outb(sr1 | 1<<5, VGA_SR_DATA);
15355         vga_put(pdev, VGA_RSRC_LEGACY_IO);
15356         udelay(300);
15357
15358         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15359         POSTING_READ(vga_reg);
15360 }
15361
15362 void intel_modeset_init_hw(struct drm_device *dev)
15363 {
15364         struct drm_i915_private *dev_priv = to_i915(dev);
15365
15366         intel_update_cdclk(dev_priv);
15367         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
15368         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
15369 }
15370
15371 /*
15372  * Calculate what we think the watermarks should be for the state we've read
15373  * out of the hardware and then immediately program those watermarks so that
15374  * we ensure the hardware settings match our internal state.
15375  *
15376  * We can calculate what we think WM's should be by creating a duplicate of the
15377  * current state (which was constructed during hardware readout) and running it
15378  * through the atomic check code to calculate new watermark values in the
15379  * state object.
15380  */
15381 static void sanitize_watermarks(struct drm_device *dev)
15382 {
15383         struct drm_i915_private *dev_priv = to_i915(dev);
15384         struct drm_atomic_state *state;
15385         struct intel_atomic_state *intel_state;
15386         struct drm_crtc *crtc;
15387         struct drm_crtc_state *cstate;
15388         struct drm_modeset_acquire_ctx ctx;
15389         int ret;
15390         int i;
15391
15392         /* Only supported on platforms that use atomic watermark design */
15393         if (!dev_priv->display.optimize_watermarks)
15394                 return;
15395
15396         /*
15397          * We need to hold connection_mutex before calling duplicate_state so
15398          * that the connector loop is protected.
15399          */
15400         drm_modeset_acquire_init(&ctx, 0);
15401 retry:
15402         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15403         if (ret == -EDEADLK) {
15404                 drm_modeset_backoff(&ctx);
15405                 goto retry;
15406         } else if (WARN_ON(ret)) {
15407                 goto fail;
15408         }
15409
15410         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15411         if (WARN_ON(IS_ERR(state)))
15412                 goto fail;
15413
15414         intel_state = to_intel_atomic_state(state);
15415
15416         /*
15417          * Hardware readout is the only time we don't want to calculate
15418          * intermediate watermarks (since we don't trust the current
15419          * watermarks).
15420          */
15421         if (!HAS_GMCH(dev_priv))
15422                 intel_state->skip_intermediate_wm = true;
15423
15424         ret = intel_atomic_check(dev, state);
15425         if (ret) {
15426                 /*
15427                  * If we fail here, it means that the hardware appears to be
15428                  * programmed in a way that shouldn't be possible, given our
15429                  * understanding of watermark requirements.  This might mean a
15430                  * mistake in the hardware readout code or a mistake in the
15431                  * watermark calculations for a given platform.  Raise a WARN
15432                  * so that this is noticeable.
15433                  *
15434                  * If this actually happens, we'll have to just leave the
15435                  * BIOS-programmed watermarks untouched and hope for the best.
15436                  */
15437                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15438                 goto put_state;
15439         }
15440
15441         /* Write calculated watermark values back */
15442         for_each_new_crtc_in_state(state, crtc, cstate, i) {
15443                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15444
15445                 cs->wm.need_postvbl_update = true;
15446                 dev_priv->display.optimize_watermarks(intel_state, cs);
15447
15448                 to_intel_crtc_state(crtc->state)->wm = cs->wm;
15449         }
15450
15451 put_state:
15452         drm_atomic_state_put(state);
15453 fail:
15454         drm_modeset_drop_locks(&ctx);
15455         drm_modeset_acquire_fini(&ctx);
15456 }
15457
15458 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
15459 {
15460         if (IS_GEN(dev_priv, 5)) {
15461                 u32 fdi_pll_clk =
15462                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
15463
15464                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
15465         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
15466                 dev_priv->fdi_pll_freq = 270000;
15467         } else {
15468                 return;
15469         }
15470
15471         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
15472 }
15473
15474 static int intel_initial_commit(struct drm_device *dev)
15475 {
15476         struct drm_atomic_state *state = NULL;
15477         struct drm_modeset_acquire_ctx ctx;
15478         struct drm_crtc *crtc;
15479         struct drm_crtc_state *crtc_state;
15480         int ret = 0;
15481
15482         state = drm_atomic_state_alloc(dev);
15483         if (!state)
15484                 return -ENOMEM;
15485
15486         drm_modeset_acquire_init(&ctx, 0);
15487
15488 retry:
15489         state->acquire_ctx = &ctx;
15490
15491         drm_for_each_crtc(crtc, dev) {
15492                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
15493                 if (IS_ERR(crtc_state)) {
15494                         ret = PTR_ERR(crtc_state);
15495                         goto out;
15496                 }
15497
15498                 if (crtc_state->active) {
15499                         ret = drm_atomic_add_affected_planes(state, crtc);
15500                         if (ret)
15501                                 goto out;
15502
15503                         /*
15504                          * FIXME hack to force a LUT update to avoid the
15505                          * plane update forcing the pipe gamma on without
15506                          * having a proper LUT loaded. Remove once we
15507                          * have readout for pipe gamma enable.
15508                          */
15509                         crtc_state->color_mgmt_changed = true;
15510                 }
15511         }
15512
15513         ret = drm_atomic_commit(state);
15514
15515 out:
15516         if (ret == -EDEADLK) {
15517                 drm_atomic_state_clear(state);
15518                 drm_modeset_backoff(&ctx);
15519                 goto retry;
15520         }
15521
15522         drm_atomic_state_put(state);
15523
15524         drm_modeset_drop_locks(&ctx);
15525         drm_modeset_acquire_fini(&ctx);
15526
15527         return ret;
15528 }
15529
15530 int intel_modeset_init(struct drm_device *dev)
15531 {
15532         struct drm_i915_private *dev_priv = to_i915(dev);
15533         struct i915_ggtt *ggtt = &dev_priv->ggtt;
15534         enum pipe pipe;
15535         struct intel_crtc *crtc;
15536         int ret;
15537
15538         dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
15539
15540         drm_mode_config_init(dev);
15541
15542         dev->mode_config.min_width = 0;
15543         dev->mode_config.min_height = 0;
15544
15545         dev->mode_config.preferred_depth = 24;
15546         dev->mode_config.prefer_shadow = 1;
15547
15548         dev->mode_config.allow_fb_modifiers = true;
15549
15550         dev->mode_config.funcs = &intel_mode_funcs;
15551
15552         init_llist_head(&dev_priv->atomic_helper.free_list);
15553         INIT_WORK(&dev_priv->atomic_helper.free_work,
15554                   intel_atomic_helper_free_state_worker);
15555
15556         intel_init_quirks(dev_priv);
15557
15558         intel_fbc_init(dev_priv);
15559
15560         intel_init_pm(dev_priv);
15561
15562         /*
15563          * There may be no VBT; and if the BIOS enabled SSC we can
15564          * just keep using it to avoid unnecessary flicker.  Whereas if the
15565          * BIOS isn't using it, don't assume it will work even if the VBT
15566          * indicates as much.
15567          */
15568         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15569                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15570                                             DREF_SSC1_ENABLE);
15571
15572                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15573                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15574                                      bios_lvds_use_ssc ? "en" : "dis",
15575                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15576                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15577                 }
15578         }
15579
15580         /* maximum framebuffer dimensions */
15581         if (IS_GEN(dev_priv, 2)) {
15582                 dev->mode_config.max_width = 2048;
15583                 dev->mode_config.max_height = 2048;
15584         } else if (IS_GEN(dev_priv, 3)) {
15585                 dev->mode_config.max_width = 4096;
15586                 dev->mode_config.max_height = 4096;
15587         } else {
15588                 dev->mode_config.max_width = 8192;
15589                 dev->mode_config.max_height = 8192;
15590         }
15591
15592         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15593                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15594                 dev->mode_config.cursor_height = 1023;
15595         } else if (IS_GEN(dev_priv, 2)) {
15596                 dev->mode_config.cursor_width = 64;
15597                 dev->mode_config.cursor_height = 64;
15598         } else {
15599                 dev->mode_config.cursor_width = 256;
15600                 dev->mode_config.cursor_height = 256;
15601         }
15602
15603         dev->mode_config.fb_base = ggtt->gmadr.start;
15604
15605         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15606                       INTEL_INFO(dev_priv)->num_pipes,
15607                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15608
15609         for_each_pipe(dev_priv, pipe) {
15610                 ret = intel_crtc_init(dev_priv, pipe);
15611                 if (ret) {
15612                         drm_mode_config_cleanup(dev);
15613                         return ret;
15614                 }
15615         }
15616
15617         intel_shared_dpll_init(dev);
15618         intel_update_fdi_pll_freq(dev_priv);
15619
15620         intel_update_czclk(dev_priv);
15621         intel_modeset_init_hw(dev);
15622
15623         intel_hdcp_component_init(dev_priv);
15624
15625         if (dev_priv->max_cdclk_freq == 0)
15626                 intel_update_max_cdclk(dev_priv);
15627
15628         /* Just disable it once at startup */
15629         i915_disable_vga(dev_priv);
15630         intel_setup_outputs(dev_priv);
15631
15632         drm_modeset_lock_all(dev);
15633         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15634         drm_modeset_unlock_all(dev);
15635
15636         for_each_intel_crtc(dev, crtc) {
15637                 struct intel_initial_plane_config plane_config = {};
15638
15639                 if (!crtc->active)
15640                         continue;
15641
15642                 /*
15643                  * Note that reserving the BIOS fb up front prevents us
15644                  * from stuffing other stolen allocations like the ring
15645                  * on top.  This prevents some ugliness at boot time, and
15646                  * can even allow for smooth boot transitions if the BIOS
15647                  * fb is large enough for the active pipe configuration.
15648                  */
15649                 dev_priv->display.get_initial_plane_config(crtc,
15650                                                            &plane_config);
15651
15652                 /*
15653                  * If the fb is shared between multiple heads, we'll
15654                  * just get the first one.
15655                  */
15656                 intel_find_initial_plane_obj(crtc, &plane_config);
15657         }
15658
15659         /*
15660          * Make sure hardware watermarks really match the state we read out.
15661          * Note that we need to do this after reconstructing the BIOS fb's
15662          * since the watermark calculation done here will use pstate->fb.
15663          */
15664         if (!HAS_GMCH(dev_priv))
15665                 sanitize_watermarks(dev);
15666
15667         /*
15668          * Force all active planes to recompute their states. So that on
15669          * mode_setcrtc after probe, all the intel_plane_state variables
15670          * are already calculated and there is no assert_plane warnings
15671          * during bootup.
15672          */
15673         ret = intel_initial_commit(dev);
15674         if (ret)
15675                 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
15676
15677         return 0;
15678 }
15679
15680 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15681 {
15682         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15683         /* 640x480@60Hz, ~25175 kHz */
15684         struct dpll clock = {
15685                 .m1 = 18,
15686                 .m2 = 7,
15687                 .p1 = 13,
15688                 .p2 = 4,
15689                 .n = 2,
15690         };
15691         u32 dpll, fp;
15692         int i;
15693
15694         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15695
15696         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15697                       pipe_name(pipe), clock.vco, clock.dot);
15698
15699         fp = i9xx_dpll_compute_fp(&clock);
15700         dpll = DPLL_DVO_2X_MODE |
15701                 DPLL_VGA_MODE_DIS |
15702                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15703                 PLL_P2_DIVIDE_BY_4 |
15704                 PLL_REF_INPUT_DREFCLK |
15705                 DPLL_VCO_ENABLE;
15706
15707         I915_WRITE(FP0(pipe), fp);
15708         I915_WRITE(FP1(pipe), fp);
15709
15710         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15711         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15712         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15713         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15714         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15715         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15716         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15717
15718         /*
15719          * Apparently we need to have VGA mode enabled prior to changing
15720          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15721          * dividers, even though the register value does change.
15722          */
15723         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15724         I915_WRITE(DPLL(pipe), dpll);
15725
15726         /* Wait for the clocks to stabilize. */
15727         POSTING_READ(DPLL(pipe));
15728         udelay(150);
15729
15730         /* The pixel multiplier can only be updated once the
15731          * DPLL is enabled and the clocks are stable.
15732          *
15733          * So write it again.
15734          */
15735         I915_WRITE(DPLL(pipe), dpll);
15736
15737         /* We do this three times for luck */
15738         for (i = 0; i < 3 ; i++) {
15739                 I915_WRITE(DPLL(pipe), dpll);
15740                 POSTING_READ(DPLL(pipe));
15741                 udelay(150); /* wait for warmup */
15742         }
15743
15744         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15745         POSTING_READ(PIPECONF(pipe));
15746
15747         intel_wait_for_pipe_scanline_moving(crtc);
15748 }
15749
15750 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15751 {
15752         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15753
15754         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15755                       pipe_name(pipe));
15756
15757         WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
15758         WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
15759         WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
15760         WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
15761         WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
15762
15763         I915_WRITE(PIPECONF(pipe), 0);
15764         POSTING_READ(PIPECONF(pipe));
15765
15766         intel_wait_for_pipe_scanline_stopped(crtc);
15767
15768         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15769         POSTING_READ(DPLL(pipe));
15770 }
15771
15772 static void
15773 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15774 {
15775         struct intel_crtc *crtc;
15776
15777         if (INTEL_GEN(dev_priv) >= 4)
15778                 return;
15779
15780         for_each_intel_crtc(&dev_priv->drm, crtc) {
15781                 struct intel_plane *plane =
15782                         to_intel_plane(crtc->base.primary);
15783                 struct intel_crtc *plane_crtc;
15784                 enum pipe pipe;
15785
15786                 if (!plane->get_hw_state(plane, &pipe))
15787                         continue;
15788
15789                 if (pipe == crtc->pipe)
15790                         continue;
15791
15792                 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
15793                               plane->base.base.id, plane->base.name);
15794
15795                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15796                 intel_plane_disable_noatomic(plane_crtc, plane);
15797         }
15798 }
15799
15800 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15801 {
15802         struct drm_device *dev = crtc->base.dev;
15803         struct intel_encoder *encoder;
15804
15805         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15806                 return true;
15807
15808         return false;
15809 }
15810
15811 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15812 {
15813         struct drm_device *dev = encoder->base.dev;
15814         struct intel_connector *connector;
15815
15816         for_each_connector_on_encoder(dev, &encoder->base, connector)
15817                 return connector;
15818
15819         return NULL;
15820 }
15821
15822 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15823                               enum pipe pch_transcoder)
15824 {
15825         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15826                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
15827 }
15828
15829 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15830                                 struct drm_modeset_acquire_ctx *ctx)
15831 {
15832         struct drm_device *dev = crtc->base.dev;
15833         struct drm_i915_private *dev_priv = to_i915(dev);
15834         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
15835         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
15836
15837         /* Clear any frame start delays used for debugging left by the BIOS */
15838         if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
15839                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15840
15841                 I915_WRITE(reg,
15842                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15843         }
15844
15845         if (crtc_state->base.active) {
15846                 struct intel_plane *plane;
15847
15848                 /* Disable everything but the primary plane */
15849                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15850                         const struct intel_plane_state *plane_state =
15851                                 to_intel_plane_state(plane->base.state);
15852
15853                         if (plane_state->base.visible &&
15854                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
15855                                 intel_plane_disable_noatomic(crtc, plane);
15856                 }
15857
15858                 /*
15859                  * Disable any background color set by the BIOS, but enable the
15860                  * gamma and CSC to match how we program our planes.
15861                  */
15862                 if (INTEL_GEN(dev_priv) >= 9)
15863                         I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
15864                                    SKL_BOTTOM_COLOR_GAMMA_ENABLE |
15865                                    SKL_BOTTOM_COLOR_CSC_ENABLE);
15866         }
15867
15868         /* Adjust the state of the output pipe according to whether we
15869          * have active connectors/encoders. */
15870         if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
15871                 intel_crtc_disable_noatomic(&crtc->base, ctx);
15872
15873         if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
15874                 /*
15875                  * We start out with underrun reporting disabled to avoid races.
15876                  * For correct bookkeeping mark this on active crtcs.
15877                  *
15878                  * Also on gmch platforms we dont have any hardware bits to
15879                  * disable the underrun reporting. Which means we need to start
15880                  * out with underrun reporting disabled also on inactive pipes,
15881                  * since otherwise we'll complain about the garbage we read when
15882                  * e.g. coming up after runtime pm.
15883                  *
15884                  * No protection against concurrent access is required - at
15885                  * worst a fifo underrun happens which also sets this to false.
15886                  */
15887                 crtc->cpu_fifo_underrun_disabled = true;
15888                 /*
15889                  * We track the PCH trancoder underrun reporting state
15890                  * within the crtc. With crtc for pipe A housing the underrun
15891                  * reporting state for PCH transcoder A, crtc for pipe B housing
15892                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15893                  * and marking underrun reporting as disabled for the non-existing
15894                  * PCH transcoders B and C would prevent enabling the south
15895                  * error interrupt (see cpt_can_enable_serr_int()).
15896                  */
15897                 if (has_pch_trancoder(dev_priv, crtc->pipe))
15898                         crtc->pch_fifo_underrun_disabled = true;
15899         }
15900 }
15901
15902 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
15903 {
15904         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
15905
15906         /*
15907          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
15908          * the hardware when a high res displays plugged in. DPLL P
15909          * divider is zero, and the pipe timings are bonkers. We'll
15910          * try to disable everything in that case.
15911          *
15912          * FIXME would be nice to be able to sanitize this state
15913          * without several WARNs, but for now let's take the easy
15914          * road.
15915          */
15916         return IS_GEN(dev_priv, 6) &&
15917                 crtc_state->base.active &&
15918                 crtc_state->shared_dpll &&
15919                 crtc_state->port_clock == 0;
15920 }
15921
15922 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15923 {
15924         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
15925         struct intel_connector *connector;
15926         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
15927         struct intel_crtc_state *crtc_state = crtc ?
15928                 to_intel_crtc_state(crtc->base.state) : NULL;
15929
15930         /* We need to check both for a crtc link (meaning that the
15931          * encoder is active and trying to read from a pipe) and the
15932          * pipe itself being active. */
15933         bool has_active_crtc = crtc_state &&
15934                 crtc_state->base.active;
15935
15936         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
15937                 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
15938                               pipe_name(crtc->pipe));
15939                 has_active_crtc = false;
15940         }
15941
15942         connector = intel_encoder_find_connector(encoder);
15943         if (connector && !has_active_crtc) {
15944                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15945                               encoder->base.base.id,
15946                               encoder->base.name);
15947
15948                 /* Connector is active, but has no active pipe. This is
15949                  * fallout from our resume register restoring. Disable
15950                  * the encoder manually again. */
15951                 if (crtc_state) {
15952                         struct drm_encoder *best_encoder;
15953
15954                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15955                                       encoder->base.base.id,
15956                                       encoder->base.name);
15957
15958                         /* avoid oopsing in case the hooks consult best_encoder */
15959                         best_encoder = connector->base.state->best_encoder;
15960                         connector->base.state->best_encoder = &encoder->base;
15961
15962                         if (encoder->disable)
15963                                 encoder->disable(encoder, crtc_state,
15964                                                  connector->base.state);
15965                         if (encoder->post_disable)
15966                                 encoder->post_disable(encoder, crtc_state,
15967                                                       connector->base.state);
15968
15969                         connector->base.state->best_encoder = best_encoder;
15970                 }
15971                 encoder->base.crtc = NULL;
15972
15973                 /* Inconsistent output/port/pipe state happens presumably due to
15974                  * a bug in one of the get_hw_state functions. Or someplace else
15975                  * in our code, like the register restore mess on resume. Clamp
15976                  * things to off as a safer default. */
15977
15978                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15979                 connector->base.encoder = NULL;
15980         }
15981
15982         /* notify opregion of the sanitized encoder state */
15983         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
15984
15985         if (INTEL_GEN(dev_priv) >= 11)
15986                 icl_sanitize_encoder_pll_mapping(encoder);
15987 }
15988
15989 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15990 {
15991         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15992
15993         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15994                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15995                 i915_disable_vga(dev_priv);
15996         }
15997 }
15998
15999 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16000 {
16001         intel_wakeref_t wakeref;
16002
16003         /*
16004          * This function can be called both from intel_modeset_setup_hw_state or
16005          * at a very early point in our resume sequence, where the power well
16006          * structures are not yet restored. Since this function is at a very
16007          * paranoid "someone might have enabled VGA while we were not looking"
16008          * level, just check if the power well is enabled instead of trying to
16009          * follow the "don't touch the power well if we don't need it" policy
16010          * the rest of the driver uses.
16011          */
16012         wakeref = intel_display_power_get_if_enabled(dev_priv,
16013                                                      POWER_DOMAIN_VGA);
16014         if (!wakeref)
16015                 return;
16016
16017         i915_redisable_vga_power_on(dev_priv);
16018
16019         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA, wakeref);
16020 }
16021
16022 /* FIXME read out full plane state for all planes */
16023 static void readout_plane_state(struct drm_i915_private *dev_priv)
16024 {
16025         struct intel_plane *plane;
16026         struct intel_crtc *crtc;
16027
16028         for_each_intel_plane(&dev_priv->drm, plane) {
16029                 struct intel_plane_state *plane_state =
16030                         to_intel_plane_state(plane->base.state);
16031                 struct intel_crtc_state *crtc_state;
16032                 enum pipe pipe = PIPE_A;
16033                 bool visible;
16034
16035                 visible = plane->get_hw_state(plane, &pipe);
16036
16037                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16038                 crtc_state = to_intel_crtc_state(crtc->base.state);
16039
16040                 intel_set_plane_visible(crtc_state, plane_state, visible);
16041
16042                 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
16043                               plane->base.base.id, plane->base.name,
16044                               enableddisabled(visible), pipe_name(pipe));
16045         }
16046
16047         for_each_intel_crtc(&dev_priv->drm, crtc) {
16048                 struct intel_crtc_state *crtc_state =
16049                         to_intel_crtc_state(crtc->base.state);
16050
16051                 fixup_active_planes(crtc_state);
16052         }
16053 }
16054
16055 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16056 {
16057         struct drm_i915_private *dev_priv = to_i915(dev);
16058         enum pipe pipe;
16059         struct intel_crtc *crtc;
16060         struct intel_encoder *encoder;
16061         struct intel_connector *connector;
16062         struct drm_connector_list_iter conn_iter;
16063         int i;
16064
16065         dev_priv->active_crtcs = 0;
16066
16067         for_each_intel_crtc(dev, crtc) {
16068                 struct intel_crtc_state *crtc_state =
16069                         to_intel_crtc_state(crtc->base.state);
16070
16071                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16072                 memset(crtc_state, 0, sizeof(*crtc_state));
16073                 crtc_state->base.crtc = &crtc->base;
16074
16075                 crtc_state->base.active = crtc_state->base.enable =
16076                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16077
16078                 crtc->base.enabled = crtc_state->base.enable;
16079                 crtc->active = crtc_state->base.active;
16080
16081                 if (crtc_state->base.active)
16082                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16083
16084                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16085                               crtc->base.base.id, crtc->base.name,
16086                               enableddisabled(crtc_state->base.active));
16087         }
16088
16089         readout_plane_state(dev_priv);
16090
16091         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16092                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16093
16094                 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
16095                                                         &pll->state.hw_state);
16096                 pll->state.crtc_mask = 0;
16097                 for_each_intel_crtc(dev, crtc) {
16098                         struct intel_crtc_state *crtc_state =
16099                                 to_intel_crtc_state(crtc->base.state);
16100
16101                         if (crtc_state->base.active &&
16102                             crtc_state->shared_dpll == pll)
16103                                 pll->state.crtc_mask |= 1 << crtc->pipe;
16104                 }
16105                 pll->active_mask = pll->state.crtc_mask;
16106
16107                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16108                               pll->info->name, pll->state.crtc_mask, pll->on);
16109         }
16110
16111         for_each_intel_encoder(dev, encoder) {
16112                 pipe = 0;
16113
16114                 if (encoder->get_hw_state(encoder, &pipe)) {
16115                         struct intel_crtc_state *crtc_state;
16116
16117                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16118                         crtc_state = to_intel_crtc_state(crtc->base.state);
16119
16120                         encoder->base.crtc = &crtc->base;
16121                         encoder->get_config(encoder, crtc_state);
16122                 } else {
16123                         encoder->base.crtc = NULL;
16124                 }
16125
16126                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16127                               encoder->base.base.id, encoder->base.name,
16128                               enableddisabled(encoder->base.crtc),
16129                               pipe_name(pipe));
16130         }
16131
16132         drm_connector_list_iter_begin(dev, &conn_iter);
16133         for_each_intel_connector_iter(connector, &conn_iter) {
16134                 if (connector->get_hw_state(connector)) {
16135                         connector->base.dpms = DRM_MODE_DPMS_ON;
16136
16137                         encoder = connector->encoder;
16138                         connector->base.encoder = &encoder->base;
16139
16140                         if (encoder->base.crtc &&
16141                             encoder->base.crtc->state->active) {
16142                                 /*
16143                                  * This has to be done during hardware readout
16144                                  * because anything calling .crtc_disable may
16145                                  * rely on the connector_mask being accurate.
16146                                  */
16147                                 encoder->base.crtc->state->connector_mask |=
16148                                         drm_connector_mask(&connector->base);
16149                                 encoder->base.crtc->state->encoder_mask |=
16150                                         drm_encoder_mask(&encoder->base);
16151                         }
16152
16153                 } else {
16154                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16155                         connector->base.encoder = NULL;
16156                 }
16157                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16158                               connector->base.base.id, connector->base.name,
16159                               enableddisabled(connector->base.encoder));
16160         }
16161         drm_connector_list_iter_end(&conn_iter);
16162
16163         for_each_intel_crtc(dev, crtc) {
16164                 struct intel_crtc_state *crtc_state =
16165                         to_intel_crtc_state(crtc->base.state);
16166                 int min_cdclk = 0;
16167
16168                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16169                 if (crtc_state->base.active) {
16170                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
16171                         crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
16172                         crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
16173                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
16174                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16175
16176                         /*
16177                          * The initial mode needs to be set in order to keep
16178                          * the atomic core happy. It wants a valid mode if the
16179                          * crtc's enabled, so we do the above call.
16180                          *
16181                          * But we don't set all the derived state fully, hence
16182                          * set a flag to indicate that a full recalculation is
16183                          * needed on the next commit.
16184                          */
16185                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
16186
16187                         intel_crtc_compute_pixel_rate(crtc_state);
16188
16189                         if (dev_priv->display.modeset_calc_cdclk) {
16190                                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
16191                                 if (WARN_ON(min_cdclk < 0))
16192                                         min_cdclk = 0;
16193                         }
16194
16195                         drm_calc_timestamping_constants(&crtc->base,
16196                                                         &crtc_state->base.adjusted_mode);
16197                         update_scanline_offset(crtc_state);
16198                 }
16199
16200                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
16201                 dev_priv->min_voltage_level[crtc->pipe] =
16202                         crtc_state->min_voltage_level;
16203
16204                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
16205         }
16206 }
16207
16208 static void
16209 get_encoder_power_domains(struct drm_i915_private *dev_priv)
16210 {
16211         struct intel_encoder *encoder;
16212
16213         for_each_intel_encoder(&dev_priv->drm, encoder) {
16214                 u64 get_domains;
16215                 enum intel_display_power_domain domain;
16216                 struct intel_crtc_state *crtc_state;
16217
16218                 if (!encoder->get_power_domains)
16219                         continue;
16220
16221                 /*
16222                  * MST-primary and inactive encoders don't have a crtc state
16223                  * and neither of these require any power domain references.
16224                  */
16225                 if (!encoder->base.crtc)
16226                         continue;
16227
16228                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
16229                 get_domains = encoder->get_power_domains(encoder, crtc_state);
16230                 for_each_power_domain(domain, get_domains)
16231                         intel_display_power_get(dev_priv, domain);
16232         }
16233 }
16234
16235 static void intel_early_display_was(struct drm_i915_private *dev_priv)
16236 {
16237         /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
16238         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
16239                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
16240                            DARBF_GATING_DIS);
16241
16242         if (IS_HASWELL(dev_priv)) {
16243                 /*
16244                  * WaRsPkgCStateDisplayPMReq:hsw
16245                  * System hang if this isn't done before disabling all planes!
16246                  */
16247                 I915_WRITE(CHICKEN_PAR1_1,
16248                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
16249         }
16250 }
16251
16252 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
16253                                        enum port port, i915_reg_t hdmi_reg)
16254 {
16255         u32 val = I915_READ(hdmi_reg);
16256
16257         if (val & SDVO_ENABLE ||
16258             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
16259                 return;
16260
16261         DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
16262                       port_name(port));
16263
16264         val &= ~SDVO_PIPE_SEL_MASK;
16265         val |= SDVO_PIPE_SEL(PIPE_A);
16266
16267         I915_WRITE(hdmi_reg, val);
16268 }
16269
16270 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
16271                                      enum port port, i915_reg_t dp_reg)
16272 {
16273         u32 val = I915_READ(dp_reg);
16274
16275         if (val & DP_PORT_EN ||
16276             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
16277                 return;
16278
16279         DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
16280                       port_name(port));
16281
16282         val &= ~DP_PIPE_SEL_MASK;
16283         val |= DP_PIPE_SEL(PIPE_A);
16284
16285         I915_WRITE(dp_reg, val);
16286 }
16287
16288 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
16289 {
16290         /*
16291          * The BIOS may select transcoder B on some of the PCH
16292          * ports even it doesn't enable the port. This would trip
16293          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
16294          * Sanitize the transcoder select bits to prevent that. We
16295          * assume that the BIOS never actually enabled the port,
16296          * because if it did we'd actually have to toggle the port
16297          * on and back off to make the transcoder A select stick
16298          * (see. intel_dp_link_down(), intel_disable_hdmi(),
16299          * intel_disable_sdvo()).
16300          */
16301         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
16302         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
16303         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
16304
16305         /* PCH SDVOB multiplex with HDMIB */
16306         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
16307         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
16308         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
16309 }
16310
16311 /* Scan out the current hw modeset state,
16312  * and sanitizes it to the current state
16313  */
16314 static void
16315 intel_modeset_setup_hw_state(struct drm_device *dev,
16316                              struct drm_modeset_acquire_ctx *ctx)
16317 {
16318         struct drm_i915_private *dev_priv = to_i915(dev);
16319         struct intel_crtc_state *crtc_state;
16320         struct intel_encoder *encoder;
16321         struct intel_crtc *crtc;
16322         intel_wakeref_t wakeref;
16323         int i;
16324
16325         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
16326
16327         intel_early_display_was(dev_priv);
16328         intel_modeset_readout_hw_state(dev);
16329
16330         /* HW state is read out, now we need to sanitize this mess. */
16331         get_encoder_power_domains(dev_priv);
16332
16333         if (HAS_PCH_IBX(dev_priv))
16334                 ibx_sanitize_pch_ports(dev_priv);
16335
16336         /*
16337          * intel_sanitize_plane_mapping() may need to do vblank
16338          * waits, so we need vblank interrupts restored beforehand.
16339          */
16340         for_each_intel_crtc(&dev_priv->drm, crtc) {
16341                 crtc_state = to_intel_crtc_state(crtc->base.state);
16342
16343                 drm_crtc_vblank_reset(&crtc->base);
16344
16345                 if (crtc_state->base.active)
16346                         intel_crtc_vblank_on(crtc_state);
16347         }
16348
16349         intel_sanitize_plane_mapping(dev_priv);
16350
16351         for_each_intel_encoder(dev, encoder)
16352                 intel_sanitize_encoder(encoder);
16353
16354         for_each_intel_crtc(&dev_priv->drm, crtc) {
16355                 crtc_state = to_intel_crtc_state(crtc->base.state);
16356                 intel_sanitize_crtc(crtc, ctx);
16357                 intel_dump_pipe_config(crtc, crtc_state,
16358                                        "[setup_hw_state]");
16359         }
16360
16361         intel_modeset_update_connector_atomic_state(dev);
16362
16363         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16364                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16365
16366                 if (!pll->on || pll->active_mask)
16367                         continue;
16368
16369                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
16370                               pll->info->name);
16371
16372                 pll->info->funcs->disable(dev_priv, pll);
16373                 pll->on = false;
16374         }
16375
16376         if (IS_G4X(dev_priv)) {
16377                 g4x_wm_get_hw_state(dev_priv);
16378                 g4x_wm_sanitize(dev_priv);
16379         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16380                 vlv_wm_get_hw_state(dev_priv);
16381                 vlv_wm_sanitize(dev_priv);
16382         } else if (INTEL_GEN(dev_priv) >= 9) {
16383                 skl_wm_get_hw_state(dev_priv);
16384         } else if (HAS_PCH_SPLIT(dev_priv)) {
16385                 ilk_wm_get_hw_state(dev_priv);
16386         }
16387
16388         for_each_intel_crtc(dev, crtc) {
16389                 u64 put_domains;
16390
16391                 crtc_state = to_intel_crtc_state(crtc->base.state);
16392                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc_state);
16393                 if (WARN_ON(put_domains))
16394                         modeset_put_power_domains(dev_priv, put_domains);
16395         }
16396
16397         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
16398
16399         intel_fbc_init_pipe_state(dev_priv);
16400 }
16401
16402 void intel_display_resume(struct drm_device *dev)
16403 {
16404         struct drm_i915_private *dev_priv = to_i915(dev);
16405         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16406         struct drm_modeset_acquire_ctx ctx;
16407         int ret;
16408
16409         dev_priv->modeset_restore_state = NULL;
16410         if (state)
16411                 state->acquire_ctx = &ctx;
16412
16413         drm_modeset_acquire_init(&ctx, 0);
16414
16415         while (1) {
16416                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16417                 if (ret != -EDEADLK)
16418                         break;
16419
16420                 drm_modeset_backoff(&ctx);
16421         }
16422
16423         if (!ret)
16424                 ret = __intel_display_resume(dev, state, &ctx);
16425
16426         intel_enable_ipc(dev_priv);
16427         drm_modeset_drop_locks(&ctx);
16428         drm_modeset_acquire_fini(&ctx);
16429
16430         if (ret)
16431                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16432         if (state)
16433                 drm_atomic_state_put(state);
16434 }
16435
16436 static void intel_hpd_poll_fini(struct drm_device *dev)
16437 {
16438         struct intel_connector *connector;
16439         struct drm_connector_list_iter conn_iter;
16440
16441         /* Kill all the work that may have been queued by hpd. */
16442         drm_connector_list_iter_begin(dev, &conn_iter);
16443         for_each_intel_connector_iter(connector, &conn_iter) {
16444                 if (connector->modeset_retry_work.func)
16445                         cancel_work_sync(&connector->modeset_retry_work);
16446                 if (connector->hdcp.shim) {
16447                         cancel_delayed_work_sync(&connector->hdcp.check_work);
16448                         cancel_work_sync(&connector->hdcp.prop_work);
16449                 }
16450         }
16451         drm_connector_list_iter_end(&conn_iter);
16452 }
16453
16454 void intel_modeset_cleanup(struct drm_device *dev)
16455 {
16456         struct drm_i915_private *dev_priv = to_i915(dev);
16457
16458         flush_workqueue(dev_priv->modeset_wq);
16459
16460         flush_work(&dev_priv->atomic_helper.free_work);
16461         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
16462
16463         /*
16464          * Interrupts and polling as the first thing to avoid creating havoc.
16465          * Too much stuff here (turning of connectors, ...) would
16466          * experience fancy races otherwise.
16467          */
16468         intel_irq_uninstall(dev_priv);
16469
16470         /*
16471          * Due to the hpd irq storm handling the hotplug work can re-arm the
16472          * poll handlers. Hence disable polling after hpd handling is shut down.
16473          */
16474         intel_hpd_poll_fini(dev);
16475
16476         /* poll work can call into fbdev, hence clean that up afterwards */
16477         intel_fbdev_fini(dev_priv);
16478
16479         intel_unregister_dsm_handler();
16480
16481         intel_fbc_global_disable(dev_priv);
16482
16483         /* flush any delayed tasks or pending work */
16484         flush_scheduled_work();
16485
16486         intel_hdcp_component_fini(dev_priv);
16487
16488         drm_mode_config_cleanup(dev);
16489
16490         intel_overlay_cleanup(dev_priv);
16491
16492         intel_teardown_gmbus(dev_priv);
16493
16494         destroy_workqueue(dev_priv->modeset_wq);
16495
16496         intel_fbc_cleanup_cfb(dev_priv);
16497 }
16498
16499 /*
16500  * set vga decode state - true == enable VGA decode
16501  */
16502 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
16503 {
16504         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16505         u16 gmch_ctrl;
16506
16507         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16508                 DRM_ERROR("failed to read control word\n");
16509                 return -EIO;
16510         }
16511
16512         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16513                 return 0;
16514
16515         if (state)
16516                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16517         else
16518                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16519
16520         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16521                 DRM_ERROR("failed to write control word\n");
16522                 return -EIO;
16523         }
16524
16525         return 0;
16526 }
16527
16528 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
16529
16530 struct intel_display_error_state {
16531
16532         u32 power_well_driver;
16533
16534         struct intel_cursor_error_state {
16535                 u32 control;
16536                 u32 position;
16537                 u32 base;
16538                 u32 size;
16539         } cursor[I915_MAX_PIPES];
16540
16541         struct intel_pipe_error_state {
16542                 bool power_domain_on;
16543                 u32 source;
16544                 u32 stat;
16545         } pipe[I915_MAX_PIPES];
16546
16547         struct intel_plane_error_state {
16548                 u32 control;
16549                 u32 stride;
16550                 u32 size;
16551                 u32 pos;
16552                 u32 addr;
16553                 u32 surface;
16554                 u32 tile_offset;
16555         } plane[I915_MAX_PIPES];
16556
16557         struct intel_transcoder_error_state {
16558                 bool available;
16559                 bool power_domain_on;
16560                 enum transcoder cpu_transcoder;
16561
16562                 u32 conf;
16563
16564                 u32 htotal;
16565                 u32 hblank;
16566                 u32 hsync;
16567                 u32 vtotal;
16568                 u32 vblank;
16569                 u32 vsync;
16570         } transcoder[4];
16571 };
16572
16573 struct intel_display_error_state *
16574 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16575 {
16576         struct intel_display_error_state *error;
16577         int transcoders[] = {
16578                 TRANSCODER_A,
16579                 TRANSCODER_B,
16580                 TRANSCODER_C,
16581                 TRANSCODER_EDP,
16582         };
16583         int i;
16584
16585         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
16586
16587         if (!HAS_DISPLAY(dev_priv))
16588                 return NULL;
16589
16590         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16591         if (error == NULL)
16592                 return NULL;
16593
16594         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16595                 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
16596
16597         for_each_pipe(dev_priv, i) {
16598                 error->pipe[i].power_domain_on =
16599                         __intel_display_power_is_enabled(dev_priv,
16600                                                          POWER_DOMAIN_PIPE(i));
16601                 if (!error->pipe[i].power_domain_on)
16602                         continue;
16603
16604                 error->cursor[i].control = I915_READ(CURCNTR(i));
16605                 error->cursor[i].position = I915_READ(CURPOS(i));
16606                 error->cursor[i].base = I915_READ(CURBASE(i));
16607
16608                 error->plane[i].control = I915_READ(DSPCNTR(i));
16609                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16610                 if (INTEL_GEN(dev_priv) <= 3) {
16611                         error->plane[i].size = I915_READ(DSPSIZE(i));
16612                         error->plane[i].pos = I915_READ(DSPPOS(i));
16613                 }
16614                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16615                         error->plane[i].addr = I915_READ(DSPADDR(i));
16616                 if (INTEL_GEN(dev_priv) >= 4) {
16617                         error->plane[i].surface = I915_READ(DSPSURF(i));
16618                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16619                 }
16620
16621                 error->pipe[i].source = I915_READ(PIPESRC(i));
16622
16623                 if (HAS_GMCH(dev_priv))
16624                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16625         }
16626
16627         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
16628                 enum transcoder cpu_transcoder = transcoders[i];
16629
16630                 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
16631                         continue;
16632
16633                 error->transcoder[i].available = true;
16634                 error->transcoder[i].power_domain_on =
16635                         __intel_display_power_is_enabled(dev_priv,
16636                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16637                 if (!error->transcoder[i].power_domain_on)
16638                         continue;
16639
16640                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16641
16642                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16643                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16644                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16645                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16646                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16647                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16648                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16649         }
16650
16651         return error;
16652 }
16653
16654 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16655
16656 void
16657 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16658                                 struct intel_display_error_state *error)
16659 {
16660         struct drm_i915_private *dev_priv = m->i915;
16661         int i;
16662
16663         if (!error)
16664                 return;
16665
16666         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
16667         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16668                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16669                            error->power_well_driver);
16670         for_each_pipe(dev_priv, i) {
16671                 err_printf(m, "Pipe [%d]:\n", i);
16672                 err_printf(m, "  Power: %s\n",
16673                            onoff(error->pipe[i].power_domain_on));
16674                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16675                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16676
16677                 err_printf(m, "Plane [%d]:\n", i);
16678                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16679                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16680                 if (INTEL_GEN(dev_priv) <= 3) {
16681                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16682                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16683                 }
16684                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16685                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16686                 if (INTEL_GEN(dev_priv) >= 4) {
16687                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16688                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16689                 }
16690
16691                 err_printf(m, "Cursor [%d]:\n", i);
16692                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16693                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16694                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16695         }
16696
16697         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
16698                 if (!error->transcoder[i].available)
16699                         continue;
16700
16701                 err_printf(m, "CPU transcoder: %s\n",
16702                            transcoder_name(error->transcoder[i].cpu_transcoder));
16703                 err_printf(m, "  Power: %s\n",
16704                            onoff(error->transcoder[i].power_domain_on));
16705                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16706                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16707                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16708                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16709                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16710                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16711                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16712         }
16713 }
16714
16715 #endif