i915: when kgdb is active display compression should be off
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "drm_dp_helper.h"
37
38 #include "drm_crtc_helper.h"
39
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41
42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
43 static void intel_update_watermarks(struct drm_device *dev);
44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
45
46 typedef struct {
47     /* given values */
48     int n;
49     int m1, m2;
50     int p1, p2;
51     /* derived values */
52     int dot;
53     int vco;
54     int m;
55     int p;
56 } intel_clock_t;
57
58 typedef struct {
59     int min, max;
60 } intel_range_t;
61
62 typedef struct {
63     int dot_limit;
64     int p2_slow, p2_fast;
65 } intel_p2_t;
66
67 #define INTEL_P2_NUM                  2
68 typedef struct intel_limit intel_limit_t;
69 struct intel_limit {
70     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
71     intel_p2_t      p2;
72     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
73                       int, int, intel_clock_t *);
74 };
75
76 #define I8XX_DOT_MIN              25000
77 #define I8XX_DOT_MAX             350000
78 #define I8XX_VCO_MIN             930000
79 #define I8XX_VCO_MAX            1400000
80 #define I8XX_N_MIN                    3
81 #define I8XX_N_MAX                   16
82 #define I8XX_M_MIN                   96
83 #define I8XX_M_MAX                  140
84 #define I8XX_M1_MIN                  18
85 #define I8XX_M1_MAX                  26
86 #define I8XX_M2_MIN                   6
87 #define I8XX_M2_MAX                  16
88 #define I8XX_P_MIN                    4
89 #define I8XX_P_MAX                  128
90 #define I8XX_P1_MIN                   2
91 #define I8XX_P1_MAX                  33
92 #define I8XX_P1_LVDS_MIN              1
93 #define I8XX_P1_LVDS_MAX              6
94 #define I8XX_P2_SLOW                  4
95 #define I8XX_P2_FAST                  2
96 #define I8XX_P2_LVDS_SLOW             14
97 #define I8XX_P2_LVDS_FAST             7
98 #define I8XX_P2_SLOW_LIMIT       165000
99
100 #define I9XX_DOT_MIN              20000
101 #define I9XX_DOT_MAX             400000
102 #define I9XX_VCO_MIN            1400000
103 #define I9XX_VCO_MAX            2800000
104 #define PINEVIEW_VCO_MIN                1700000
105 #define PINEVIEW_VCO_MAX                3500000
106 #define I9XX_N_MIN                    1
107 #define I9XX_N_MAX                    6
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN                3
110 #define PINEVIEW_N_MAX                6
111 #define I9XX_M_MIN                   70
112 #define I9XX_M_MAX                  120
113 #define PINEVIEW_M_MIN                2
114 #define PINEVIEW_M_MAX              256
115 #define I9XX_M1_MIN                  10
116 #define I9XX_M1_MAX                  22
117 #define I9XX_M2_MIN                   5
118 #define I9XX_M2_MAX                   9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN               0
121 #define PINEVIEW_M1_MAX               0
122 #define PINEVIEW_M2_MIN               0
123 #define PINEVIEW_M2_MAX               254
124 #define I9XX_P_SDVO_DAC_MIN           5
125 #define I9XX_P_SDVO_DAC_MAX          80
126 #define I9XX_P_LVDS_MIN               7
127 #define I9XX_P_LVDS_MAX              98
128 #define PINEVIEW_P_LVDS_MIN                   7
129 #define PINEVIEW_P_LVDS_MAX                  112
130 #define I9XX_P1_MIN                   1
131 #define I9XX_P1_MAX                   8
132 #define I9XX_P2_SDVO_DAC_SLOW                10
133 #define I9XX_P2_SDVO_DAC_FAST                 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
135 #define I9XX_P2_LVDS_SLOW                    14
136 #define I9XX_P2_LVDS_FAST                     7
137 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
138
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN           25000
141 #define G4X_DOT_SDVO_MAX           270000
142 #define G4X_VCO_MIN                1750000
143 #define G4X_VCO_MAX                3500000
144 #define G4X_N_SDVO_MIN             1
145 #define G4X_N_SDVO_MAX             4
146 #define G4X_M_SDVO_MIN             104
147 #define G4X_M_SDVO_MAX             138
148 #define G4X_M1_SDVO_MIN            17
149 #define G4X_M1_SDVO_MAX            23
150 #define G4X_M2_SDVO_MIN            5
151 #define G4X_M2_SDVO_MAX            11
152 #define G4X_P_SDVO_MIN             10
153 #define G4X_P_SDVO_MAX             30
154 #define G4X_P1_SDVO_MIN            1
155 #define G4X_P1_SDVO_MAX            3
156 #define G4X_P2_SDVO_SLOW           10
157 #define G4X_P2_SDVO_FAST           10
158 #define G4X_P2_SDVO_LIMIT          270000
159
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN           22000
162 #define G4X_DOT_HDMI_DAC_MAX           400000
163 #define G4X_N_HDMI_DAC_MIN             1
164 #define G4X_N_HDMI_DAC_MAX             4
165 #define G4X_M_HDMI_DAC_MIN             104
166 #define G4X_M_HDMI_DAC_MAX             138
167 #define G4X_M1_HDMI_DAC_MIN            16
168 #define G4X_M1_HDMI_DAC_MAX            23
169 #define G4X_M2_HDMI_DAC_MIN            5
170 #define G4X_M2_HDMI_DAC_MAX            11
171 #define G4X_P_HDMI_DAC_MIN             5
172 #define G4X_P_HDMI_DAC_MAX             80
173 #define G4X_P1_HDMI_DAC_MIN            1
174 #define G4X_P1_HDMI_DAC_MAX            8
175 #define G4X_P2_HDMI_DAC_SLOW           10
176 #define G4X_P2_HDMI_DAC_FAST           5
177 #define G4X_P2_HDMI_DAC_LIMIT          165000
178
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
197
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
216
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN           161670
219 #define G4X_DOT_DISPLAY_PORT_MAX           227000
220 #define G4X_N_DISPLAY_PORT_MIN             1
221 #define G4X_N_DISPLAY_PORT_MAX             2
222 #define G4X_M_DISPLAY_PORT_MIN             97
223 #define G4X_M_DISPLAY_PORT_MAX             108
224 #define G4X_M1_DISPLAY_PORT_MIN            0x10
225 #define G4X_M1_DISPLAY_PORT_MAX            0x12
226 #define G4X_M2_DISPLAY_PORT_MIN            0x05
227 #define G4X_M2_DISPLAY_PORT_MAX            0x06
228 #define G4X_P_DISPLAY_PORT_MIN             10
229 #define G4X_P_DISPLAY_PORT_MAX             20
230 #define G4X_P1_DISPLAY_PORT_MIN            1
231 #define G4X_P1_DISPLAY_PORT_MAX            2
232 #define G4X_P2_DISPLAY_PORT_SLOW           10
233 #define G4X_P2_DISPLAY_PORT_FAST           10
234 #define G4X_P2_DISPLAY_PORT_LIMIT          0
235
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238    N/M1/M2, so here the range value for them is (actual_value-2).
239  */
240 #define IRONLAKE_DOT_MIN         25000
241 #define IRONLAKE_DOT_MAX         350000
242 #define IRONLAKE_VCO_MIN         1760000
243 #define IRONLAKE_VCO_MAX         3510000
244 #define IRONLAKE_M1_MIN          12
245 #define IRONLAKE_M1_MAX          22
246 #define IRONLAKE_M2_MIN          5
247 #define IRONLAKE_M2_MAX          9
248 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
249
250 /* We have parameter ranges for different type of outputs. */
251
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN      1
254 #define IRONLAKE_DAC_N_MAX      5
255 #define IRONLAKE_DAC_M_MIN      79
256 #define IRONLAKE_DAC_M_MAX      127
257 #define IRONLAKE_DAC_P_MIN      5
258 #define IRONLAKE_DAC_P_MAX      80
259 #define IRONLAKE_DAC_P1_MIN     1
260 #define IRONLAKE_DAC_P1_MAX     8
261 #define IRONLAKE_DAC_P2_SLOW    10
262 #define IRONLAKE_DAC_P2_FAST    5
263
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN   1
266 #define IRONLAKE_LVDS_S_N_MAX   3
267 #define IRONLAKE_LVDS_S_M_MIN   79
268 #define IRONLAKE_LVDS_S_M_MAX   118
269 #define IRONLAKE_LVDS_S_P_MIN   28
270 #define IRONLAKE_LVDS_S_P_MAX   112
271 #define IRONLAKE_LVDS_S_P1_MIN  2
272 #define IRONLAKE_LVDS_S_P1_MAX  8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
275
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN   1
278 #define IRONLAKE_LVDS_D_N_MAX   3
279 #define IRONLAKE_LVDS_D_M_MIN   79
280 #define IRONLAKE_LVDS_D_M_MAX   127
281 #define IRONLAKE_LVDS_D_P_MIN   14
282 #define IRONLAKE_LVDS_D_P_MAX   56
283 #define IRONLAKE_LVDS_D_P1_MIN  2
284 #define IRONLAKE_LVDS_D_P1_MAX  8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
287
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
299
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
311
312 /* DisplayPort */
313 #define IRONLAKE_DP_N_MIN               1
314 #define IRONLAKE_DP_N_MAX               2
315 #define IRONLAKE_DP_M_MIN               81
316 #define IRONLAKE_DP_M_MAX               90
317 #define IRONLAKE_DP_P_MIN               10
318 #define IRONLAKE_DP_P_MAX               20
319 #define IRONLAKE_DP_P2_FAST             10
320 #define IRONLAKE_DP_P2_SLOW             10
321 #define IRONLAKE_DP_P2_LIMIT            0
322 #define IRONLAKE_DP_P1_MIN              1
323 #define IRONLAKE_DP_P1_MAX              2
324
325 static bool
326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
327                     int target, int refclk, intel_clock_t *best_clock);
328 static bool
329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
330                         int target, int refclk, intel_clock_t *best_clock);
331
332 static bool
333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
334                       int target, int refclk, intel_clock_t *best_clock);
335 static bool
336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
337                            int target, int refclk, intel_clock_t *best_clock);
338
339 static const intel_limit_t intel_limits_i8xx_dvo = {
340         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
341         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
342         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
343         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
344         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
345         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
346         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
347         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
348         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
349                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
350         .find_pll = intel_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_i8xx_lvds = {
354         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
355         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
356         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
357         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
358         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
359         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
360         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
361         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
362         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
363                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
364         .find_pll = intel_find_best_PLL,
365 };
366         
367 static const intel_limit_t intel_limits_i9xx_sdvo = {
368         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
369         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
370         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
371         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
372         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
373         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
374         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
375         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
376         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
377                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
378         .find_pll = intel_find_best_PLL,
379 };
380
381 static const intel_limit_t intel_limits_i9xx_lvds = {
382         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
383         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
384         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
385         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
386         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
387         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
388         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
389         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
390         /* The single-channel range is 25-112Mhz, and dual-channel
391          * is 80-224Mhz.  Prefer single channel as much as possible.
392          */
393         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
394                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
395         .find_pll = intel_find_best_PLL,
396 };
397
398     /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo = {
400         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
401         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
402         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
403         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
404         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
405         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
406         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
407         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
408         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
409                  .p2_slow = G4X_P2_SDVO_SLOW,
410                  .p2_fast = G4X_P2_SDVO_FAST
411         },
412         .find_pll = intel_g4x_find_best_PLL,
413 };
414
415 static const intel_limit_t intel_limits_g4x_hdmi = {
416         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
418         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
419         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
420         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
421         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
422         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
423         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
424         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
425                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
426                  .p2_fast = G4X_P2_HDMI_DAC_FAST
427         },
428         .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
432         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
433                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
434         .vco = { .min = G4X_VCO_MIN,
435                  .max = G4X_VCO_MAX },
436         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
437                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
438         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
439                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
440         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
441                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
442         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
443                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
444         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
445                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
446         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
447                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
448         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
449                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
450                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
451         },
452         .find_pll = intel_g4x_find_best_PLL,
453 };
454
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
456         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
457                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
458         .vco = { .min = G4X_VCO_MIN,
459                  .max = G4X_VCO_MAX },
460         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
461                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
462         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
463                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
464         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
465                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
466         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
467                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
468         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
469                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
470         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
471                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
472         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
473                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
474                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
475         },
476         .find_pll = intel_g4x_find_best_PLL,
477 };
478
479 static const intel_limit_t intel_limits_g4x_display_port = {
480         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
481                  .max = G4X_DOT_DISPLAY_PORT_MAX },
482         .vco = { .min = G4X_VCO_MIN,
483                  .max = G4X_VCO_MAX},
484         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
485                  .max = G4X_N_DISPLAY_PORT_MAX },
486         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
487                  .max = G4X_M_DISPLAY_PORT_MAX },
488         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
489                  .max = G4X_M1_DISPLAY_PORT_MAX },
490         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
491                  .max = G4X_M2_DISPLAY_PORT_MAX },
492         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
493                  .max = G4X_P_DISPLAY_PORT_MAX },
494         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
495                  .max = G4X_P1_DISPLAY_PORT_MAX},
496         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
497                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
498                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
499         .find_pll = intel_find_pll_g4x_dp,
500 };
501
502 static const intel_limit_t intel_limits_pineview_sdvo = {
503         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
504         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
505         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
506         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
507         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
508         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
509         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
510         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
511         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
512                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
513         .find_pll = intel_find_best_PLL,
514 };
515
516 static const intel_limit_t intel_limits_pineview_lvds = {
517         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
518         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
519         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
520         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
521         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
522         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
523         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
524         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
525         /* Pineview only supports single-channel mode. */
526         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
527                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
528         .find_pll = intel_find_best_PLL,
529 };
530
531 static const intel_limit_t intel_limits_ironlake_dac = {
532         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
533         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
534         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
535         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
536         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
537         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
538         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
539         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
540         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
541                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
542                  .p2_fast = IRONLAKE_DAC_P2_FAST },
543         .find_pll = intel_g4x_find_best_PLL,
544 };
545
546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
547         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
548         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
549         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
550         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
551         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
552         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
553         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
554         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
555         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
556                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
557                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
558         .find_pll = intel_g4x_find_best_PLL,
559 };
560
561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
562         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
563         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
564         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
565         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
566         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
567         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
568         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
569         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
570         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
571                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
572                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
573         .find_pll = intel_g4x_find_best_PLL,
574 };
575
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
577         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
578         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
579         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
580         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
581         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
582         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
583         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
584         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
585         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
586                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
587                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
588         .find_pll = intel_g4x_find_best_PLL,
589 };
590
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
592         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
593         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
594         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
595         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
596         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
597         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
598         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
599         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
600         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
601                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
602                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
603         .find_pll = intel_g4x_find_best_PLL,
604 };
605
606 static const intel_limit_t intel_limits_ironlake_display_port = {
607         .dot = { .min = IRONLAKE_DOT_MIN,
608                  .max = IRONLAKE_DOT_MAX },
609         .vco = { .min = IRONLAKE_VCO_MIN,
610                  .max = IRONLAKE_VCO_MAX},
611         .n   = { .min = IRONLAKE_DP_N_MIN,
612                  .max = IRONLAKE_DP_N_MAX },
613         .m   = { .min = IRONLAKE_DP_M_MIN,
614                  .max = IRONLAKE_DP_M_MAX },
615         .m1  = { .min = IRONLAKE_M1_MIN,
616                  .max = IRONLAKE_M1_MAX },
617         .m2  = { .min = IRONLAKE_M2_MIN,
618                  .max = IRONLAKE_M2_MAX },
619         .p   = { .min = IRONLAKE_DP_P_MIN,
620                  .max = IRONLAKE_DP_P_MAX },
621         .p1  = { .min = IRONLAKE_DP_P1_MIN,
622                  .max = IRONLAKE_DP_P1_MAX},
623         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
624                  .p2_slow = IRONLAKE_DP_P2_SLOW,
625                  .p2_fast = IRONLAKE_DP_P2_FAST },
626         .find_pll = intel_find_pll_ironlake_dp,
627 };
628
629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
630 {
631         struct drm_device *dev = crtc->dev;
632         struct drm_i915_private *dev_priv = dev->dev_private;
633         const intel_limit_t *limit;
634         int refclk = 120;
635
636         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
638                         refclk = 100;
639
640                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
641                     LVDS_CLKB_POWER_UP) {
642                         /* LVDS dual channel */
643                         if (refclk == 100)
644                                 limit = &intel_limits_ironlake_dual_lvds_100m;
645                         else
646                                 limit = &intel_limits_ironlake_dual_lvds;
647                 } else {
648                         if (refclk == 100)
649                                 limit = &intel_limits_ironlake_single_lvds_100m;
650                         else
651                                 limit = &intel_limits_ironlake_single_lvds;
652                 }
653         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
654                         HAS_eDP)
655                 limit = &intel_limits_ironlake_display_port;
656         else
657                 limit = &intel_limits_ironlake_dac;
658
659         return limit;
660 }
661
662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
663 {
664         struct drm_device *dev = crtc->dev;
665         struct drm_i915_private *dev_priv = dev->dev_private;
666         const intel_limit_t *limit;
667
668         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
669                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
670                     LVDS_CLKB_POWER_UP)
671                         /* LVDS with dual channel */
672                         limit = &intel_limits_g4x_dual_channel_lvds;
673                 else
674                         /* LVDS with dual channel */
675                         limit = &intel_limits_g4x_single_channel_lvds;
676         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
677                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
678                 limit = &intel_limits_g4x_hdmi;
679         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
680                 limit = &intel_limits_g4x_sdvo;
681         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
682                 limit = &intel_limits_g4x_display_port;
683         } else /* The option is for other outputs */
684                 limit = &intel_limits_i9xx_sdvo;
685
686         return limit;
687 }
688
689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
690 {
691         struct drm_device *dev = crtc->dev;
692         const intel_limit_t *limit;
693
694         if (HAS_PCH_SPLIT(dev))
695                 limit = intel_ironlake_limit(crtc);
696         else if (IS_G4X(dev)) {
697                 limit = intel_g4x_limit(crtc);
698         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
699                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
700                         limit = &intel_limits_i9xx_lvds;
701                 else
702                         limit = &intel_limits_i9xx_sdvo;
703         } else if (IS_PINEVIEW(dev)) {
704                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705                         limit = &intel_limits_pineview_lvds;
706                 else
707                         limit = &intel_limits_pineview_sdvo;
708         } else {
709                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710                         limit = &intel_limits_i8xx_lvds;
711                 else
712                         limit = &intel_limits_i8xx_dvo;
713         }
714         return limit;
715 }
716
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk, intel_clock_t *clock)
719 {
720         clock->m = clock->m2 + 2;
721         clock->p = clock->p1 * clock->p2;
722         clock->vco = refclk * clock->m / clock->n;
723         clock->dot = clock->vco / clock->p;
724 }
725
726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
727 {
728         if (IS_PINEVIEW(dev)) {
729                 pineview_clock(refclk, clock);
730                 return;
731         }
732         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
733         clock->p = clock->p1 * clock->p2;
734         clock->vco = refclk * clock->m / (clock->n + 2);
735         clock->dot = clock->vco / clock->p;
736 }
737
738 /**
739  * Returns whether any output on the specified pipe is of the specified type
740  */
741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742 {
743     struct drm_device *dev = crtc->dev;
744     struct drm_mode_config *mode_config = &dev->mode_config;
745     struct drm_encoder *l_entry;
746
747     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
748             if (l_entry && l_entry->crtc == crtc) {
749                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
750                     if (intel_encoder->type == type)
751                             return true;
752             }
753     }
754     return false;
755 }
756
757 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
758 /**
759  * Returns whether the given set of divisors are valid for a given refclk with
760  * the given connectors.
761  */
762
763 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
764 {
765         const intel_limit_t *limit = intel_limit (crtc);
766         struct drm_device *dev = crtc->dev;
767
768         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
769                 INTELPllInvalid ("p1 out of range\n");
770         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
771                 INTELPllInvalid ("p out of range\n");
772         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
773                 INTELPllInvalid ("m2 out of range\n");
774         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
775                 INTELPllInvalid ("m1 out of range\n");
776         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
777                 INTELPllInvalid ("m1 <= m2\n");
778         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
779                 INTELPllInvalid ("m out of range\n");
780         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
781                 INTELPllInvalid ("n out of range\n");
782         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
783                 INTELPllInvalid ("vco out of range\n");
784         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785          * connector, etc., rather than just a single range.
786          */
787         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
788                 INTELPllInvalid ("dot out of range\n");
789
790         return true;
791 }
792
793 static bool
794 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
795                     int target, int refclk, intel_clock_t *best_clock)
796
797 {
798         struct drm_device *dev = crtc->dev;
799         struct drm_i915_private *dev_priv = dev->dev_private;
800         intel_clock_t clock;
801         int err = target;
802
803         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
804             (I915_READ(LVDS)) != 0) {
805                 /*
806                  * For LVDS, if the panel is on, just rely on its current
807                  * settings for dual-channel.  We haven't figured out how to
808                  * reliably set up different single/dual channel state, if we
809                  * even can.
810                  */
811                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
812                     LVDS_CLKB_POWER_UP)
813                         clock.p2 = limit->p2.p2_fast;
814                 else
815                         clock.p2 = limit->p2.p2_slow;
816         } else {
817                 if (target < limit->p2.dot_limit)
818                         clock.p2 = limit->p2.p2_slow;
819                 else
820                         clock.p2 = limit->p2.p2_fast;
821         }
822
823         memset (best_clock, 0, sizeof (*best_clock));
824
825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826              clock.m1++) {
827                 for (clock.m2 = limit->m2.min;
828                      clock.m2 <= limit->m2.max; clock.m2++) {
829                         /* m1 is always 0 in Pineview */
830                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
831                                 break;
832                         for (clock.n = limit->n.min;
833                              clock.n <= limit->n.max; clock.n++) {
834                                 for (clock.p1 = limit->p1.min;
835                                         clock.p1 <= limit->p1.max; clock.p1++) {
836                                         int this_err;
837
838                                         intel_clock(dev, refclk, &clock);
839
840                                         if (!intel_PLL_is_valid(crtc, &clock))
841                                                 continue;
842
843                                         this_err = abs(clock.dot - target);
844                                         if (this_err < err) {
845                                                 *best_clock = clock;
846                                                 err = this_err;
847                                         }
848                                 }
849                         }
850                 }
851         }
852
853         return (err != target);
854 }
855
856 static bool
857 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
858                         int target, int refclk, intel_clock_t *best_clock)
859 {
860         struct drm_device *dev = crtc->dev;
861         struct drm_i915_private *dev_priv = dev->dev_private;
862         intel_clock_t clock;
863         int max_n;
864         bool found;
865         /* approximately equals target * 0.00585 */
866         int err_most = (target >> 8) + (target >> 9);
867         found = false;
868
869         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
870                 int lvds_reg;
871
872                 if (HAS_PCH_SPLIT(dev))
873                         lvds_reg = PCH_LVDS;
874                 else
875                         lvds_reg = LVDS;
876                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
877                     LVDS_CLKB_POWER_UP)
878                         clock.p2 = limit->p2.p2_fast;
879                 else
880                         clock.p2 = limit->p2.p2_slow;
881         } else {
882                 if (target < limit->p2.dot_limit)
883                         clock.p2 = limit->p2.p2_slow;
884                 else
885                         clock.p2 = limit->p2.p2_fast;
886         }
887
888         memset(best_clock, 0, sizeof(*best_clock));
889         max_n = limit->n.max;
890         /* based on hardware requirement, prefer smaller n to precision */
891         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
892                 /* based on hardware requirement, prefere larger m1,m2 */
893                 for (clock.m1 = limit->m1.max;
894                      clock.m1 >= limit->m1.min; clock.m1--) {
895                         for (clock.m2 = limit->m2.max;
896                              clock.m2 >= limit->m2.min; clock.m2--) {
897                                 for (clock.p1 = limit->p1.max;
898                                      clock.p1 >= limit->p1.min; clock.p1--) {
899                                         int this_err;
900
901                                         intel_clock(dev, refclk, &clock);
902                                         if (!intel_PLL_is_valid(crtc, &clock))
903                                                 continue;
904                                         this_err = abs(clock.dot - target) ;
905                                         if (this_err < err_most) {
906                                                 *best_clock = clock;
907                                                 err_most = this_err;
908                                                 max_n = clock.n;
909                                                 found = true;
910                                         }
911                                 }
912                         }
913                 }
914         }
915         return found;
916 }
917
918 static bool
919 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
920                            int target, int refclk, intel_clock_t *best_clock)
921 {
922         struct drm_device *dev = crtc->dev;
923         intel_clock_t clock;
924
925         /* return directly when it is eDP */
926         if (HAS_eDP)
927                 return true;
928
929         if (target < 200000) {
930                 clock.n = 1;
931                 clock.p1 = 2;
932                 clock.p2 = 10;
933                 clock.m1 = 12;
934                 clock.m2 = 9;
935         } else {
936                 clock.n = 2;
937                 clock.p1 = 1;
938                 clock.p2 = 10;
939                 clock.m1 = 14;
940                 clock.m2 = 8;
941         }
942         intel_clock(dev, refclk, &clock);
943         memcpy(best_clock, &clock, sizeof(intel_clock_t));
944         return true;
945 }
946
947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
948 static bool
949 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
950                       int target, int refclk, intel_clock_t *best_clock)
951 {
952     intel_clock_t clock;
953     if (target < 200000) {
954         clock.p1 = 2;
955         clock.p2 = 10;
956         clock.n = 2;
957         clock.m1 = 23;
958         clock.m2 = 8;
959     } else {
960         clock.p1 = 1;
961         clock.p2 = 10;
962         clock.n = 1;
963         clock.m1 = 14;
964         clock.m2 = 2;
965     }
966     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
967     clock.p = (clock.p1 * clock.p2);
968     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
969     clock.vco = 0;
970     memcpy(best_clock, &clock, sizeof(intel_clock_t));
971     return true;
972 }
973
974 void
975 intel_wait_for_vblank(struct drm_device *dev)
976 {
977         /* Wait for 20ms, i.e. one cycle at 50hz. */
978         if (in_dbg_master())
979                 mdelay(20); /* The kernel debugger cannot call msleep() */
980         else
981                 msleep(20);
982 }
983
984 /* Parameters have changed, update FBC info */
985 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
986 {
987         struct drm_device *dev = crtc->dev;
988         struct drm_i915_private *dev_priv = dev->dev_private;
989         struct drm_framebuffer *fb = crtc->fb;
990         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
991         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
993         int plane, i;
994         u32 fbc_ctl, fbc_ctl2;
995
996         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
997
998         if (fb->pitch < dev_priv->cfb_pitch)
999                 dev_priv->cfb_pitch = fb->pitch;
1000
1001         /* FBC_CTL wants 64B units */
1002         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1003         dev_priv->cfb_fence = obj_priv->fence_reg;
1004         dev_priv->cfb_plane = intel_crtc->plane;
1005         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1006
1007         /* Clear old tags */
1008         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1009                 I915_WRITE(FBC_TAG + (i * 4), 0);
1010
1011         /* Set it up... */
1012         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1013         if (obj_priv->tiling_mode != I915_TILING_NONE)
1014                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1015         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1016         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1017
1018         /* enable it... */
1019         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1020         if (IS_I945GM(dev))
1021                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1022         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1023         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1024         if (obj_priv->tiling_mode != I915_TILING_NONE)
1025                 fbc_ctl |= dev_priv->cfb_fence;
1026         I915_WRITE(FBC_CONTROL, fbc_ctl);
1027
1028         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1029                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1030 }
1031
1032 void i8xx_disable_fbc(struct drm_device *dev)
1033 {
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1036         u32 fbc_ctl;
1037
1038         if (!I915_HAS_FBC(dev))
1039                 return;
1040
1041         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1042                 return; /* Already off, just return */
1043
1044         /* Disable compression */
1045         fbc_ctl = I915_READ(FBC_CONTROL);
1046         fbc_ctl &= ~FBC_CTL_EN;
1047         I915_WRITE(FBC_CONTROL, fbc_ctl);
1048
1049         /* Wait for compressing bit to clear */
1050         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1051                 if (time_after(jiffies, timeout)) {
1052                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1053                         break;
1054                 }
1055                 ; /* do nothing */
1056         }
1057
1058         intel_wait_for_vblank(dev);
1059
1060         DRM_DEBUG_KMS("disabled FBC\n");
1061 }
1062
1063 static bool i8xx_fbc_enabled(struct drm_device *dev)
1064 {
1065         struct drm_i915_private *dev_priv = dev->dev_private;
1066
1067         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1068 }
1069
1070 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1071 {
1072         struct drm_device *dev = crtc->dev;
1073         struct drm_i915_private *dev_priv = dev->dev_private;
1074         struct drm_framebuffer *fb = crtc->fb;
1075         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1076         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1078         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1079                      DPFC_CTL_PLANEB);
1080         unsigned long stall_watermark = 200;
1081         u32 dpfc_ctl;
1082
1083         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1084         dev_priv->cfb_fence = obj_priv->fence_reg;
1085         dev_priv->cfb_plane = intel_crtc->plane;
1086
1087         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1088         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1089                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1090                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1091         } else {
1092                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1093         }
1094
1095         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1096         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1097                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1098                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1099         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1100
1101         /* enable it... */
1102         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1103
1104         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1105 }
1106
1107 void g4x_disable_fbc(struct drm_device *dev)
1108 {
1109         struct drm_i915_private *dev_priv = dev->dev_private;
1110         u32 dpfc_ctl;
1111
1112         /* Disable compression */
1113         dpfc_ctl = I915_READ(DPFC_CONTROL);
1114         dpfc_ctl &= ~DPFC_CTL_EN;
1115         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1116         intel_wait_for_vblank(dev);
1117
1118         DRM_DEBUG_KMS("disabled FBC\n");
1119 }
1120
1121 static bool g4x_fbc_enabled(struct drm_device *dev)
1122 {
1123         struct drm_i915_private *dev_priv = dev->dev_private;
1124
1125         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1126 }
1127
1128 bool intel_fbc_enabled(struct drm_device *dev)
1129 {
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131
1132         if (!dev_priv->display.fbc_enabled)
1133                 return false;
1134
1135         return dev_priv->display.fbc_enabled(dev);
1136 }
1137
1138 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1139 {
1140         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1141
1142         if (!dev_priv->display.enable_fbc)
1143                 return;
1144
1145         dev_priv->display.enable_fbc(crtc, interval);
1146 }
1147
1148 void intel_disable_fbc(struct drm_device *dev)
1149 {
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151
1152         if (!dev_priv->display.disable_fbc)
1153                 return;
1154
1155         dev_priv->display.disable_fbc(dev);
1156 }
1157
1158 /**
1159  * intel_update_fbc - enable/disable FBC as needed
1160  * @crtc: CRTC to point the compressor at
1161  * @mode: mode in use
1162  *
1163  * Set up the framebuffer compression hardware at mode set time.  We
1164  * enable it if possible:
1165  *   - plane A only (on pre-965)
1166  *   - no pixel mulitply/line duplication
1167  *   - no alpha buffer discard
1168  *   - no dual wide
1169  *   - framebuffer <= 2048 in width, 1536 in height
1170  *
1171  * We can't assume that any compression will take place (worst case),
1172  * so the compressed buffer has to be the same size as the uncompressed
1173  * one.  It also must reside (along with the line length buffer) in
1174  * stolen memory.
1175  *
1176  * We need to enable/disable FBC on a global basis.
1177  */
1178 static void intel_update_fbc(struct drm_crtc *crtc,
1179                              struct drm_display_mode *mode)
1180 {
1181         struct drm_device *dev = crtc->dev;
1182         struct drm_i915_private *dev_priv = dev->dev_private;
1183         struct drm_framebuffer *fb = crtc->fb;
1184         struct intel_framebuffer *intel_fb;
1185         struct drm_i915_gem_object *obj_priv;
1186         struct drm_crtc *tmp_crtc;
1187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1188         int plane = intel_crtc->plane;
1189         int crtcs_enabled = 0;
1190
1191         DRM_DEBUG_KMS("\n");
1192
1193         if (!i915_powersave)
1194                 return;
1195
1196         if (!I915_HAS_FBC(dev))
1197                 return;
1198
1199         if (!crtc->fb)
1200                 return;
1201
1202         intel_fb = to_intel_framebuffer(fb);
1203         obj_priv = to_intel_bo(intel_fb->obj);
1204
1205         /*
1206          * If FBC is already on, we just have to verify that we can
1207          * keep it that way...
1208          * Need to disable if:
1209          *   - more than one pipe is active
1210          *   - changing FBC params (stride, fence, mode)
1211          *   - new fb is too large to fit in compressed buffer
1212          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1213          */
1214         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1215                 if (tmp_crtc->enabled)
1216                         crtcs_enabled++;
1217         }
1218         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1219         if (crtcs_enabled > 1) {
1220                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1221                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1222                 goto out_disable;
1223         }
1224         if (intel_fb->obj->size > dev_priv->cfb_size) {
1225                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1226                                 "compression\n");
1227                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1228                 goto out_disable;
1229         }
1230         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1231             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1232                 DRM_DEBUG_KMS("mode incompatible with compression, "
1233                                 "disabling\n");
1234                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1235                 goto out_disable;
1236         }
1237         if ((mode->hdisplay > 2048) ||
1238             (mode->vdisplay > 1536)) {
1239                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1240                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1241                 goto out_disable;
1242         }
1243         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1244                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1245                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1246                 goto out_disable;
1247         }
1248         if (obj_priv->tiling_mode != I915_TILING_X) {
1249                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1250                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1251                 goto out_disable;
1252         }
1253
1254         /* If the kernel debugger is active, always disable compression */
1255         if (in_dbg_master())
1256                 goto out_disable;
1257
1258         if (intel_fbc_enabled(dev)) {
1259                 /* We can re-enable it in this case, but need to update pitch */
1260                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1261                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1262                     (plane != dev_priv->cfb_plane))
1263                         intel_disable_fbc(dev);
1264         }
1265
1266         /* Now try to turn it back on if possible */
1267         if (!intel_fbc_enabled(dev))
1268                 intel_enable_fbc(crtc, 500);
1269
1270         return;
1271
1272 out_disable:
1273         /* Multiple disables should be harmless */
1274         if (intel_fbc_enabled(dev)) {
1275                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1276                 intel_disable_fbc(dev);
1277         }
1278 }
1279
1280 int
1281 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1282 {
1283         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1284         u32 alignment;
1285         int ret;
1286
1287         switch (obj_priv->tiling_mode) {
1288         case I915_TILING_NONE:
1289                 alignment = 64 * 1024;
1290                 break;
1291         case I915_TILING_X:
1292                 /* pin() will align the object as required by fence */
1293                 alignment = 0;
1294                 break;
1295         case I915_TILING_Y:
1296                 /* FIXME: Is this true? */
1297                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1298                 return -EINVAL;
1299         default:
1300                 BUG();
1301         }
1302
1303         ret = i915_gem_object_pin(obj, alignment);
1304         if (ret != 0)
1305                 return ret;
1306
1307         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1308          * fence, whereas 965+ only requires a fence if using
1309          * framebuffer compression.  For simplicity, we always install
1310          * a fence as the cost is not that onerous.
1311          */
1312         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1313             obj_priv->tiling_mode != I915_TILING_NONE) {
1314                 ret = i915_gem_object_get_fence_reg(obj);
1315                 if (ret != 0) {
1316                         i915_gem_object_unpin(obj);
1317                         return ret;
1318                 }
1319         }
1320
1321         return 0;
1322 }
1323
1324 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1325 static int
1326 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1327                            int x, int y)
1328 {
1329         struct drm_device *dev = crtc->dev;
1330         struct drm_i915_private *dev_priv = dev->dev_private;
1331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1332         struct intel_framebuffer *intel_fb;
1333         struct drm_i915_gem_object *obj_priv;
1334         struct drm_gem_object *obj;
1335         int plane = intel_crtc->plane;
1336         unsigned long Start, Offset;
1337         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1338         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1339         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1340         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1341         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1342         u32 dspcntr;
1343
1344         switch (plane) {
1345         case 0:
1346         case 1:
1347                 break;
1348         default:
1349                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1350                 return -EINVAL;
1351         }
1352
1353         intel_fb = to_intel_framebuffer(fb);
1354         obj = intel_fb->obj;
1355         obj_priv = to_intel_bo(obj);
1356
1357         dspcntr = I915_READ(dspcntr_reg);
1358         /* Mask out pixel format bits in case we change it */
1359         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1360         switch (fb->bits_per_pixel) {
1361         case 8:
1362                 dspcntr |= DISPPLANE_8BPP;
1363                 break;
1364         case 16:
1365                 if (fb->depth == 15)
1366                         dspcntr |= DISPPLANE_15_16BPP;
1367                 else
1368                         dspcntr |= DISPPLANE_16BPP;
1369                 break;
1370         case 24:
1371         case 32:
1372                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1373                 break;
1374         default:
1375                 DRM_ERROR("Unknown color depth\n");
1376                 return -EINVAL;
1377         }
1378         if (IS_I965G(dev)) {
1379                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1380                         dspcntr |= DISPPLANE_TILED;
1381                 else
1382                         dspcntr &= ~DISPPLANE_TILED;
1383         }
1384
1385         if (IS_IRONLAKE(dev))
1386                 /* must disable */
1387                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1388
1389         I915_WRITE(dspcntr_reg, dspcntr);
1390
1391         Start = obj_priv->gtt_offset;
1392         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1393
1394         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1395         I915_WRITE(dspstride, fb->pitch);
1396         if (IS_I965G(dev)) {
1397                 I915_WRITE(dspbase, Offset);
1398                 I915_READ(dspbase);
1399                 I915_WRITE(dspsurf, Start);
1400                 I915_READ(dspsurf);
1401                 I915_WRITE(dsptileoff, (y << 16) | x);
1402         } else {
1403                 I915_WRITE(dspbase, Start + Offset);
1404                 I915_READ(dspbase);
1405         }
1406
1407         if ((IS_I965G(dev) || plane == 0))
1408                 intel_update_fbc(crtc, &crtc->mode);
1409
1410         intel_wait_for_vblank(dev);
1411         intel_increase_pllclock(crtc, true);
1412
1413         return 0;
1414 }
1415
1416 static int
1417 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1418                     struct drm_framebuffer *old_fb)
1419 {
1420         struct drm_device *dev = crtc->dev;
1421         struct drm_i915_private *dev_priv = dev->dev_private;
1422         struct drm_i915_master_private *master_priv;
1423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1424         struct intel_framebuffer *intel_fb;
1425         struct drm_i915_gem_object *obj_priv;
1426         struct drm_gem_object *obj;
1427         int pipe = intel_crtc->pipe;
1428         int plane = intel_crtc->plane;
1429         unsigned long Start, Offset;
1430         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1431         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1432         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1433         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1434         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1435         u32 dspcntr;
1436         int ret;
1437
1438         /* no fb bound */
1439         if (!crtc->fb) {
1440                 DRM_DEBUG_KMS("No FB bound\n");
1441                 return 0;
1442         }
1443
1444         switch (plane) {
1445         case 0:
1446         case 1:
1447                 break;
1448         default:
1449                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1450                 return -EINVAL;
1451         }
1452
1453         intel_fb = to_intel_framebuffer(crtc->fb);
1454         obj = intel_fb->obj;
1455         obj_priv = to_intel_bo(obj);
1456
1457         mutex_lock(&dev->struct_mutex);
1458         ret = intel_pin_and_fence_fb_obj(dev, obj);
1459         if (ret != 0) {
1460                 mutex_unlock(&dev->struct_mutex);
1461                 return ret;
1462         }
1463
1464         ret = i915_gem_object_set_to_display_plane(obj);
1465         if (ret != 0) {
1466                 i915_gem_object_unpin(obj);
1467                 mutex_unlock(&dev->struct_mutex);
1468                 return ret;
1469         }
1470
1471         dspcntr = I915_READ(dspcntr_reg);
1472         /* Mask out pixel format bits in case we change it */
1473         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1474         switch (crtc->fb->bits_per_pixel) {
1475         case 8:
1476                 dspcntr |= DISPPLANE_8BPP;
1477                 break;
1478         case 16:
1479                 if (crtc->fb->depth == 15)
1480                         dspcntr |= DISPPLANE_15_16BPP;
1481                 else
1482                         dspcntr |= DISPPLANE_16BPP;
1483                 break;
1484         case 24:
1485         case 32:
1486                 if (crtc->fb->depth == 30)
1487                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1488                 else
1489                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1490                 break;
1491         default:
1492                 DRM_ERROR("Unknown color depth\n");
1493                 i915_gem_object_unpin(obj);
1494                 mutex_unlock(&dev->struct_mutex);
1495                 return -EINVAL;
1496         }
1497         if (IS_I965G(dev)) {
1498                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1499                         dspcntr |= DISPPLANE_TILED;
1500                 else
1501                         dspcntr &= ~DISPPLANE_TILED;
1502         }
1503
1504         if (HAS_PCH_SPLIT(dev))
1505                 /* must disable */
1506                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1507
1508         I915_WRITE(dspcntr_reg, dspcntr);
1509
1510         Start = obj_priv->gtt_offset;
1511         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1512
1513         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1514                       Start, Offset, x, y, crtc->fb->pitch);
1515         I915_WRITE(dspstride, crtc->fb->pitch);
1516         if (IS_I965G(dev)) {
1517                 I915_WRITE(dspbase, Offset);
1518                 I915_READ(dspbase);
1519                 I915_WRITE(dspsurf, Start);
1520                 I915_READ(dspsurf);
1521                 I915_WRITE(dsptileoff, (y << 16) | x);
1522         } else {
1523                 I915_WRITE(dspbase, Start + Offset);
1524                 I915_READ(dspbase);
1525         }
1526
1527         if ((IS_I965G(dev) || plane == 0))
1528                 intel_update_fbc(crtc, &crtc->mode);
1529
1530         intel_wait_for_vblank(dev);
1531
1532         if (old_fb) {
1533                 intel_fb = to_intel_framebuffer(old_fb);
1534                 obj_priv = to_intel_bo(intel_fb->obj);
1535                 i915_gem_object_unpin(intel_fb->obj);
1536         }
1537         intel_increase_pllclock(crtc, true);
1538
1539         mutex_unlock(&dev->struct_mutex);
1540
1541         if (!dev->primary->master)
1542                 return 0;
1543
1544         master_priv = dev->primary->master->driver_priv;
1545         if (!master_priv->sarea_priv)
1546                 return 0;
1547
1548         if (pipe) {
1549                 master_priv->sarea_priv->pipeB_x = x;
1550                 master_priv->sarea_priv->pipeB_y = y;
1551         } else {
1552                 master_priv->sarea_priv->pipeA_x = x;
1553                 master_priv->sarea_priv->pipeA_y = y;
1554         }
1555
1556         return 0;
1557 }
1558
1559 /* Disable the VGA plane that we never use */
1560 static void i915_disable_vga (struct drm_device *dev)
1561 {
1562         struct drm_i915_private *dev_priv = dev->dev_private;
1563         u8 sr1;
1564         u32 vga_reg;
1565
1566         if (HAS_PCH_SPLIT(dev))
1567                 vga_reg = CPU_VGACNTRL;
1568         else
1569                 vga_reg = VGACNTRL;
1570
1571         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1572                 return;
1573
1574         I915_WRITE8(VGA_SR_INDEX, 1);
1575         sr1 = I915_READ8(VGA_SR_DATA);
1576         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1577         udelay(100);
1578
1579         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1580 }
1581
1582 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1583 {
1584         struct drm_device *dev = crtc->dev;
1585         struct drm_i915_private *dev_priv = dev->dev_private;
1586         u32 dpa_ctl;
1587
1588         DRM_DEBUG_KMS("\n");
1589         dpa_ctl = I915_READ(DP_A);
1590         dpa_ctl &= ~DP_PLL_ENABLE;
1591         I915_WRITE(DP_A, dpa_ctl);
1592 }
1593
1594 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1595 {
1596         struct drm_device *dev = crtc->dev;
1597         struct drm_i915_private *dev_priv = dev->dev_private;
1598         u32 dpa_ctl;
1599
1600         dpa_ctl = I915_READ(DP_A);
1601         dpa_ctl |= DP_PLL_ENABLE;
1602         I915_WRITE(DP_A, dpa_ctl);
1603         udelay(200);
1604 }
1605
1606
1607 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1608 {
1609         struct drm_device *dev = crtc->dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         u32 dpa_ctl;
1612
1613         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1614         dpa_ctl = I915_READ(DP_A);
1615         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1616
1617         if (clock < 200000) {
1618                 u32 temp;
1619                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1620                 /* workaround for 160Mhz:
1621                    1) program 0x4600c bits 15:0 = 0x8124
1622                    2) program 0x46010 bit 0 = 1
1623                    3) program 0x46034 bit 24 = 1
1624                    4) program 0x64000 bit 14 = 1
1625                    */
1626                 temp = I915_READ(0x4600c);
1627                 temp &= 0xffff0000;
1628                 I915_WRITE(0x4600c, temp | 0x8124);
1629
1630                 temp = I915_READ(0x46010);
1631                 I915_WRITE(0x46010, temp | 1);
1632
1633                 temp = I915_READ(0x46034);
1634                 I915_WRITE(0x46034, temp | (1 << 24));
1635         } else {
1636                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1637         }
1638         I915_WRITE(DP_A, dpa_ctl);
1639
1640         udelay(500);
1641 }
1642
1643 /* The FDI link training functions for ILK/Ibexpeak. */
1644 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1645 {
1646         struct drm_device *dev = crtc->dev;
1647         struct drm_i915_private *dev_priv = dev->dev_private;
1648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1649         int pipe = intel_crtc->pipe;
1650         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1651         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1652         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1653         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1654         u32 temp, tries = 0;
1655
1656         /* enable CPU FDI TX and PCH FDI RX */
1657         temp = I915_READ(fdi_tx_reg);
1658         temp |= FDI_TX_ENABLE;
1659         temp &= ~(7 << 19);
1660         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1661         temp &= ~FDI_LINK_TRAIN_NONE;
1662         temp |= FDI_LINK_TRAIN_PATTERN_1;
1663         I915_WRITE(fdi_tx_reg, temp);
1664         I915_READ(fdi_tx_reg);
1665
1666         temp = I915_READ(fdi_rx_reg);
1667         temp &= ~FDI_LINK_TRAIN_NONE;
1668         temp |= FDI_LINK_TRAIN_PATTERN_1;
1669         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1670         I915_READ(fdi_rx_reg);
1671         udelay(150);
1672
1673         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1674            for train result */
1675         temp = I915_READ(fdi_rx_imr_reg);
1676         temp &= ~FDI_RX_SYMBOL_LOCK;
1677         temp &= ~FDI_RX_BIT_LOCK;
1678         I915_WRITE(fdi_rx_imr_reg, temp);
1679         I915_READ(fdi_rx_imr_reg);
1680         udelay(150);
1681
1682         for (;;) {
1683                 temp = I915_READ(fdi_rx_iir_reg);
1684                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1685
1686                 if ((temp & FDI_RX_BIT_LOCK)) {
1687                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1688                         I915_WRITE(fdi_rx_iir_reg,
1689                                    temp | FDI_RX_BIT_LOCK);
1690                         break;
1691                 }
1692
1693                 tries++;
1694
1695                 if (tries > 5) {
1696                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1697                         break;
1698                 }
1699         }
1700
1701         /* Train 2 */
1702         temp = I915_READ(fdi_tx_reg);
1703         temp &= ~FDI_LINK_TRAIN_NONE;
1704         temp |= FDI_LINK_TRAIN_PATTERN_2;
1705         I915_WRITE(fdi_tx_reg, temp);
1706
1707         temp = I915_READ(fdi_rx_reg);
1708         temp &= ~FDI_LINK_TRAIN_NONE;
1709         temp |= FDI_LINK_TRAIN_PATTERN_2;
1710         I915_WRITE(fdi_rx_reg, temp);
1711         udelay(150);
1712
1713         tries = 0;
1714
1715         for (;;) {
1716                 temp = I915_READ(fdi_rx_iir_reg);
1717                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1718
1719                 if (temp & FDI_RX_SYMBOL_LOCK) {
1720                         I915_WRITE(fdi_rx_iir_reg,
1721                                    temp | FDI_RX_SYMBOL_LOCK);
1722                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1723                         break;
1724                 }
1725
1726                 tries++;
1727
1728                 if (tries > 5) {
1729                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1730                         break;
1731                 }
1732         }
1733
1734         DRM_DEBUG_KMS("FDI train done\n");
1735 }
1736
1737 static int snb_b_fdi_train_param [] = {
1738         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1739         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1740         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1741         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1742 };
1743
1744 /* The FDI link training functions for SNB/Cougarpoint. */
1745 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1746 {
1747         struct drm_device *dev = crtc->dev;
1748         struct drm_i915_private *dev_priv = dev->dev_private;
1749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1750         int pipe = intel_crtc->pipe;
1751         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1752         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1753         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1754         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1755         u32 temp, i;
1756
1757         /* enable CPU FDI TX and PCH FDI RX */
1758         temp = I915_READ(fdi_tx_reg);
1759         temp |= FDI_TX_ENABLE;
1760         temp &= ~(7 << 19);
1761         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1762         temp &= ~FDI_LINK_TRAIN_NONE;
1763         temp |= FDI_LINK_TRAIN_PATTERN_1;
1764         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1765         /* SNB-B */
1766         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1767         I915_WRITE(fdi_tx_reg, temp);
1768         I915_READ(fdi_tx_reg);
1769
1770         temp = I915_READ(fdi_rx_reg);
1771         if (HAS_PCH_CPT(dev)) {
1772                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1773                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1774         } else {
1775                 temp &= ~FDI_LINK_TRAIN_NONE;
1776                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1777         }
1778         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1779         I915_READ(fdi_rx_reg);
1780         udelay(150);
1781
1782         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1783            for train result */
1784         temp = I915_READ(fdi_rx_imr_reg);
1785         temp &= ~FDI_RX_SYMBOL_LOCK;
1786         temp &= ~FDI_RX_BIT_LOCK;
1787         I915_WRITE(fdi_rx_imr_reg, temp);
1788         I915_READ(fdi_rx_imr_reg);
1789         udelay(150);
1790
1791         for (i = 0; i < 4; i++ ) {
1792                 temp = I915_READ(fdi_tx_reg);
1793                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1794                 temp |= snb_b_fdi_train_param[i];
1795                 I915_WRITE(fdi_tx_reg, temp);
1796                 udelay(500);
1797
1798                 temp = I915_READ(fdi_rx_iir_reg);
1799                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1800
1801                 if (temp & FDI_RX_BIT_LOCK) {
1802                         I915_WRITE(fdi_rx_iir_reg,
1803                                    temp | FDI_RX_BIT_LOCK);
1804                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1805                         break;
1806                 }
1807         }
1808         if (i == 4)
1809                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1810
1811         /* Train 2 */
1812         temp = I915_READ(fdi_tx_reg);
1813         temp &= ~FDI_LINK_TRAIN_NONE;
1814         temp |= FDI_LINK_TRAIN_PATTERN_2;
1815         if (IS_GEN6(dev)) {
1816                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1817                 /* SNB-B */
1818                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1819         }
1820         I915_WRITE(fdi_tx_reg, temp);
1821
1822         temp = I915_READ(fdi_rx_reg);
1823         if (HAS_PCH_CPT(dev)) {
1824                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1825                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1826         } else {
1827                 temp &= ~FDI_LINK_TRAIN_NONE;
1828                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1829         }
1830         I915_WRITE(fdi_rx_reg, temp);
1831         udelay(150);
1832
1833         for (i = 0; i < 4; i++ ) {
1834                 temp = I915_READ(fdi_tx_reg);
1835                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1836                 temp |= snb_b_fdi_train_param[i];
1837                 I915_WRITE(fdi_tx_reg, temp);
1838                 udelay(500);
1839
1840                 temp = I915_READ(fdi_rx_iir_reg);
1841                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1842
1843                 if (temp & FDI_RX_SYMBOL_LOCK) {
1844                         I915_WRITE(fdi_rx_iir_reg,
1845                                    temp | FDI_RX_SYMBOL_LOCK);
1846                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1847                         break;
1848                 }
1849         }
1850         if (i == 4)
1851                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1852
1853         DRM_DEBUG_KMS("FDI train done.\n");
1854 }
1855
1856 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1857 {
1858         struct drm_device *dev = crtc->dev;
1859         struct drm_i915_private *dev_priv = dev->dev_private;
1860         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1861         int pipe = intel_crtc->pipe;
1862         int plane = intel_crtc->plane;
1863         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1864         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1865         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1866         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1867         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1868         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1869         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1870         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1871         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1872         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1873         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1874         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1875         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1876         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1877         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1878         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1879         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1880         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1881         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1882         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1883         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1884         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1885         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1886         u32 temp;
1887         int n;
1888         u32 pipe_bpc;
1889
1890         temp = I915_READ(pipeconf_reg);
1891         pipe_bpc = temp & PIPE_BPC_MASK;
1892
1893         /* XXX: When our outputs are all unaware of DPMS modes other than off
1894          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1895          */
1896         switch (mode) {
1897         case DRM_MODE_DPMS_ON:
1898         case DRM_MODE_DPMS_STANDBY:
1899         case DRM_MODE_DPMS_SUSPEND:
1900                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1901
1902                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1903                         temp = I915_READ(PCH_LVDS);
1904                         if ((temp & LVDS_PORT_EN) == 0) {
1905                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1906                                 POSTING_READ(PCH_LVDS);
1907                         }
1908                 }
1909
1910                 if (HAS_eDP) {
1911                         /* enable eDP PLL */
1912                         ironlake_enable_pll_edp(crtc);
1913                 } else {
1914
1915                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1916                         temp = I915_READ(fdi_rx_reg);
1917                         /*
1918                          * make the BPC in FDI Rx be consistent with that in
1919                          * pipeconf reg.
1920                          */
1921                         temp &= ~(0x7 << 16);
1922                         temp |= (pipe_bpc << 11);
1923                         temp &= ~(7 << 19);
1924                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1925                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1926                         I915_READ(fdi_rx_reg);
1927                         udelay(200);
1928
1929                         /* Switch from Rawclk to PCDclk */
1930                         temp = I915_READ(fdi_rx_reg);
1931                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1932                         I915_READ(fdi_rx_reg);
1933                         udelay(200);
1934
1935                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1936                         temp = I915_READ(fdi_tx_reg);
1937                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1938                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1939                                 I915_READ(fdi_tx_reg);
1940                                 udelay(100);
1941                         }
1942                 }
1943
1944                 /* Enable panel fitting for LVDS */
1945                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1946                         temp = I915_READ(pf_ctl_reg);
1947                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1948
1949                         /* currently full aspect */
1950                         I915_WRITE(pf_win_pos, 0);
1951
1952                         I915_WRITE(pf_win_size,
1953                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1954                                    (dev_priv->panel_fixed_mode->vdisplay));
1955                 }
1956
1957                 /* Enable CPU pipe */
1958                 temp = I915_READ(pipeconf_reg);
1959                 if ((temp & PIPEACONF_ENABLE) == 0) {
1960                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1961                         I915_READ(pipeconf_reg);
1962                         udelay(100);
1963                 }
1964
1965                 /* configure and enable CPU plane */
1966                 temp = I915_READ(dspcntr_reg);
1967                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1968                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1969                         /* Flush the plane changes */
1970                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1971                 }
1972
1973                 if (!HAS_eDP) {
1974                         /* For PCH output, training FDI link */
1975                         if (IS_GEN6(dev))
1976                                 gen6_fdi_link_train(crtc);
1977                         else
1978                                 ironlake_fdi_link_train(crtc);
1979
1980                         /* enable PCH DPLL */
1981                         temp = I915_READ(pch_dpll_reg);
1982                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1983                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1984                                 I915_READ(pch_dpll_reg);
1985                         }
1986                         udelay(200);
1987
1988                         if (HAS_PCH_CPT(dev)) {
1989                                 /* Be sure PCH DPLL SEL is set */
1990                                 temp = I915_READ(PCH_DPLL_SEL);
1991                                 if (trans_dpll_sel == 0 &&
1992                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1993                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1994                                 else if (trans_dpll_sel == 1 &&
1995                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1996                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1997                                 I915_WRITE(PCH_DPLL_SEL, temp);
1998                                 I915_READ(PCH_DPLL_SEL);
1999                         }
2000
2001                         /* set transcoder timing */
2002                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2003                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2004                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2005
2006                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2007                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2008                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2009
2010                         /* enable normal train */
2011                         temp = I915_READ(fdi_tx_reg);
2012                         temp &= ~FDI_LINK_TRAIN_NONE;
2013                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2014                                         FDI_TX_ENHANCE_FRAME_ENABLE);
2015                         I915_READ(fdi_tx_reg);
2016
2017                         temp = I915_READ(fdi_rx_reg);
2018                         if (HAS_PCH_CPT(dev)) {
2019                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2020                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2021                         } else {
2022                                 temp &= ~FDI_LINK_TRAIN_NONE;
2023                                 temp |= FDI_LINK_TRAIN_NONE;
2024                         }
2025                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2026                         I915_READ(fdi_rx_reg);
2027
2028                         /* wait one idle pattern time */
2029                         udelay(100);
2030
2031                         /* For PCH DP, enable TRANS_DP_CTL */
2032                         if (HAS_PCH_CPT(dev) &&
2033                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2034                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2035                                 int reg;
2036
2037                                 reg = I915_READ(trans_dp_ctl);
2038                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
2039                                 reg = TRANS_DP_OUTPUT_ENABLE |
2040                                       TRANS_DP_ENH_FRAMING |
2041                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
2042                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
2043
2044                                 switch (intel_trans_dp_port_sel(crtc)) {
2045                                 case PCH_DP_B:
2046                                         reg |= TRANS_DP_PORT_SEL_B;
2047                                         break;
2048                                 case PCH_DP_C:
2049                                         reg |= TRANS_DP_PORT_SEL_C;
2050                                         break;
2051                                 case PCH_DP_D:
2052                                         reg |= TRANS_DP_PORT_SEL_D;
2053                                         break;
2054                                 default:
2055                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2056                                         reg |= TRANS_DP_PORT_SEL_B;
2057                                         break;
2058                                 }
2059
2060                                 I915_WRITE(trans_dp_ctl, reg);
2061                                 POSTING_READ(trans_dp_ctl);
2062                         }
2063
2064                         /* enable PCH transcoder */
2065                         temp = I915_READ(transconf_reg);
2066                         /*
2067                          * make the BPC in transcoder be consistent with
2068                          * that in pipeconf reg.
2069                          */
2070                         temp &= ~PIPE_BPC_MASK;
2071                         temp |= pipe_bpc;
2072                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2073                         I915_READ(transconf_reg);
2074
2075                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
2076                                 ;
2077
2078                 }
2079
2080                 intel_crtc_load_lut(crtc);
2081
2082         break;
2083         case DRM_MODE_DPMS_OFF:
2084                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
2085
2086                 drm_vblank_off(dev, pipe);
2087                 /* Disable display plane */
2088                 temp = I915_READ(dspcntr_reg);
2089                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2090                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2091                         /* Flush the plane changes */
2092                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2093                         I915_READ(dspbase_reg);
2094                 }
2095
2096                 i915_disable_vga(dev);
2097
2098                 /* disable cpu pipe, disable after all planes disabled */
2099                 temp = I915_READ(pipeconf_reg);
2100                 if ((temp & PIPEACONF_ENABLE) != 0) {
2101                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2102                         I915_READ(pipeconf_reg);
2103                         n = 0;
2104                         /* wait for cpu pipe off, pipe state */
2105                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2106                                 n++;
2107                                 if (n < 60) {
2108                                         udelay(500);
2109                                         continue;
2110                                 } else {
2111                                         DRM_DEBUG_KMS("pipe %d off delay\n",
2112                                                                 pipe);
2113                                         break;
2114                                 }
2115                         }
2116                 } else
2117                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2118
2119                 udelay(100);
2120
2121                 /* Disable PF */
2122                 temp = I915_READ(pf_ctl_reg);
2123                 if ((temp & PF_ENABLE) != 0) {
2124                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2125                         I915_READ(pf_ctl_reg);
2126                 }
2127                 I915_WRITE(pf_win_size, 0);
2128                 POSTING_READ(pf_win_size);
2129
2130
2131                 /* disable CPU FDI tx and PCH FDI rx */
2132                 temp = I915_READ(fdi_tx_reg);
2133                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2134                 I915_READ(fdi_tx_reg);
2135
2136                 temp = I915_READ(fdi_rx_reg);
2137                 /* BPC in FDI rx is consistent with that in pipeconf */
2138                 temp &= ~(0x07 << 16);
2139                 temp |= (pipe_bpc << 11);
2140                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2141                 I915_READ(fdi_rx_reg);
2142
2143                 udelay(100);
2144
2145                 /* still set train pattern 1 */
2146                 temp = I915_READ(fdi_tx_reg);
2147                 temp &= ~FDI_LINK_TRAIN_NONE;
2148                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2149                 I915_WRITE(fdi_tx_reg, temp);
2150                 POSTING_READ(fdi_tx_reg);
2151
2152                 temp = I915_READ(fdi_rx_reg);
2153                 if (HAS_PCH_CPT(dev)) {
2154                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2155                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2156                 } else {
2157                         temp &= ~FDI_LINK_TRAIN_NONE;
2158                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2159                 }
2160                 I915_WRITE(fdi_rx_reg, temp);
2161                 POSTING_READ(fdi_rx_reg);
2162
2163                 udelay(100);
2164
2165                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2166                         temp = I915_READ(PCH_LVDS);
2167                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2168                         I915_READ(PCH_LVDS);
2169                         udelay(100);
2170                 }
2171
2172                 /* disable PCH transcoder */
2173                 temp = I915_READ(transconf_reg);
2174                 if ((temp & TRANS_ENABLE) != 0) {
2175                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2176                         I915_READ(transconf_reg);
2177                         n = 0;
2178                         /* wait for PCH transcoder off, transcoder state */
2179                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2180                                 n++;
2181                                 if (n < 60) {
2182                                         udelay(500);
2183                                         continue;
2184                                 } else {
2185                                         DRM_DEBUG_KMS("transcoder %d off "
2186                                                         "delay\n", pipe);
2187                                         break;
2188                                 }
2189                         }
2190                 }
2191
2192                 temp = I915_READ(transconf_reg);
2193                 /* BPC in transcoder is consistent with that in pipeconf */
2194                 temp &= ~PIPE_BPC_MASK;
2195                 temp |= pipe_bpc;
2196                 I915_WRITE(transconf_reg, temp);
2197                 I915_READ(transconf_reg);
2198                 udelay(100);
2199
2200                 if (HAS_PCH_CPT(dev)) {
2201                         /* disable TRANS_DP_CTL */
2202                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2203                         int reg;
2204
2205                         reg = I915_READ(trans_dp_ctl);
2206                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2207                         I915_WRITE(trans_dp_ctl, reg);
2208                         POSTING_READ(trans_dp_ctl);
2209
2210                         /* disable DPLL_SEL */
2211                         temp = I915_READ(PCH_DPLL_SEL);
2212                         if (trans_dpll_sel == 0)
2213                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2214                         else
2215                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2216                         I915_WRITE(PCH_DPLL_SEL, temp);
2217                         I915_READ(PCH_DPLL_SEL);
2218
2219                 }
2220
2221                 /* disable PCH DPLL */
2222                 temp = I915_READ(pch_dpll_reg);
2223                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2224                 I915_READ(pch_dpll_reg);
2225
2226                 if (HAS_eDP) {
2227                         ironlake_disable_pll_edp(crtc);
2228                 }
2229
2230                 /* Switch from PCDclk to Rawclk */
2231                 temp = I915_READ(fdi_rx_reg);
2232                 temp &= ~FDI_SEL_PCDCLK;
2233                 I915_WRITE(fdi_rx_reg, temp);
2234                 I915_READ(fdi_rx_reg);
2235
2236                 /* Disable CPU FDI TX PLL */
2237                 temp = I915_READ(fdi_tx_reg);
2238                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2239                 I915_READ(fdi_tx_reg);
2240                 udelay(100);
2241
2242                 temp = I915_READ(fdi_rx_reg);
2243                 temp &= ~FDI_RX_PLL_ENABLE;
2244                 I915_WRITE(fdi_rx_reg, temp);
2245                 I915_READ(fdi_rx_reg);
2246
2247                 /* Wait for the clocks to turn off. */
2248                 udelay(100);
2249                 break;
2250         }
2251 }
2252
2253 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2254 {
2255         struct intel_overlay *overlay;
2256         int ret;
2257
2258         if (!enable && intel_crtc->overlay) {
2259                 overlay = intel_crtc->overlay;
2260                 mutex_lock(&overlay->dev->struct_mutex);
2261                 for (;;) {
2262                         ret = intel_overlay_switch_off(overlay);
2263                         if (ret == 0)
2264                                 break;
2265
2266                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2267                         if (ret != 0) {
2268                                 /* overlay doesn't react anymore. Usually
2269                                  * results in a black screen and an unkillable
2270                                  * X server. */
2271                                 BUG();
2272                                 overlay->hw_wedged = HW_WEDGED;
2273                                 break;
2274                         }
2275                 }
2276                 mutex_unlock(&overlay->dev->struct_mutex);
2277         }
2278         /* Let userspace switch the overlay on again. In most cases userspace
2279          * has to recompute where to put it anyway. */
2280
2281         return;
2282 }
2283
2284 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2285 {
2286         struct drm_device *dev = crtc->dev;
2287         struct drm_i915_private *dev_priv = dev->dev_private;
2288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289         int pipe = intel_crtc->pipe;
2290         int plane = intel_crtc->plane;
2291         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2292         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2293         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2294         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2295         u32 temp;
2296
2297         /* XXX: When our outputs are all unaware of DPMS modes other than off
2298          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2299          */
2300         switch (mode) {
2301         case DRM_MODE_DPMS_ON:
2302         case DRM_MODE_DPMS_STANDBY:
2303         case DRM_MODE_DPMS_SUSPEND:
2304                 intel_update_watermarks(dev);
2305
2306                 /* Enable the DPLL */
2307                 temp = I915_READ(dpll_reg);
2308                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2309                         I915_WRITE(dpll_reg, temp);
2310                         I915_READ(dpll_reg);
2311                         /* Wait for the clocks to stabilize. */
2312                         udelay(150);
2313                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2314                         I915_READ(dpll_reg);
2315                         /* Wait for the clocks to stabilize. */
2316                         udelay(150);
2317                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2318                         I915_READ(dpll_reg);
2319                         /* Wait for the clocks to stabilize. */
2320                         udelay(150);
2321                 }
2322
2323                 /* Enable the pipe */
2324                 temp = I915_READ(pipeconf_reg);
2325                 if ((temp & PIPEACONF_ENABLE) == 0)
2326                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2327
2328                 /* Enable the plane */
2329                 temp = I915_READ(dspcntr_reg);
2330                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2331                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2332                         /* Flush the plane changes */
2333                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2334                 }
2335
2336                 intel_crtc_load_lut(crtc);
2337
2338                 if ((IS_I965G(dev) || plane == 0))
2339                         intel_update_fbc(crtc, &crtc->mode);
2340
2341                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2342                 intel_crtc_dpms_overlay(intel_crtc, true);
2343         break;
2344         case DRM_MODE_DPMS_OFF:
2345                 intel_update_watermarks(dev);
2346
2347                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2348                 intel_crtc_dpms_overlay(intel_crtc, false);
2349                 drm_vblank_off(dev, pipe);
2350
2351                 if (dev_priv->cfb_plane == plane &&
2352                     dev_priv->display.disable_fbc)
2353                         dev_priv->display.disable_fbc(dev);
2354
2355                 /* Disable the VGA plane that we never use */
2356                 i915_disable_vga(dev);
2357
2358                 /* Disable display plane */
2359                 temp = I915_READ(dspcntr_reg);
2360                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2361                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2362                         /* Flush the plane changes */
2363                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2364                         I915_READ(dspbase_reg);
2365                 }
2366
2367                 if (!IS_I9XX(dev)) {
2368                         /* Wait for vblank for the disable to take effect */
2369                         intel_wait_for_vblank(dev);
2370                 }
2371
2372                 /* Don't disable pipe A or pipe A PLLs if needed */
2373                 if (pipeconf_reg == PIPEACONF &&
2374                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2375                         goto skip_pipe_off;
2376
2377                 /* Next, disable display pipes */
2378                 temp = I915_READ(pipeconf_reg);
2379                 if ((temp & PIPEACONF_ENABLE) != 0) {
2380                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2381                         I915_READ(pipeconf_reg);
2382                 }
2383
2384                 /* Wait for vblank for the disable to take effect. */
2385                 intel_wait_for_vblank(dev);
2386
2387                 temp = I915_READ(dpll_reg);
2388                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2389                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2390                         I915_READ(dpll_reg);
2391                 }
2392         skip_pipe_off:
2393                 /* Wait for the clocks to turn off. */
2394                 udelay(150);
2395                 break;
2396         }
2397 }
2398
2399 /**
2400  * Sets the power management mode of the pipe and plane.
2401  *
2402  * This code should probably grow support for turning the cursor off and back
2403  * on appropriately at the same time as we're turning the pipe off/on.
2404  */
2405 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2406 {
2407         struct drm_device *dev = crtc->dev;
2408         struct drm_i915_private *dev_priv = dev->dev_private;
2409         struct drm_i915_master_private *master_priv;
2410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411         int pipe = intel_crtc->pipe;
2412         bool enabled;
2413
2414         dev_priv->display.dpms(crtc, mode);
2415
2416         intel_crtc->dpms_mode = mode;
2417
2418         if (!dev->primary->master)
2419                 return;
2420
2421         master_priv = dev->primary->master->driver_priv;
2422         if (!master_priv->sarea_priv)
2423                 return;
2424
2425         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2426
2427         switch (pipe) {
2428         case 0:
2429                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2430                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2431                 break;
2432         case 1:
2433                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2434                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2435                 break;
2436         default:
2437                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2438                 break;
2439         }
2440 }
2441
2442 static void intel_crtc_prepare (struct drm_crtc *crtc)
2443 {
2444         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2445         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2446 }
2447
2448 static void intel_crtc_commit (struct drm_crtc *crtc)
2449 {
2450         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2451         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2452 }
2453
2454 void intel_encoder_prepare (struct drm_encoder *encoder)
2455 {
2456         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2457         /* lvds has its own version of prepare see intel_lvds_prepare */
2458         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2459 }
2460
2461 void intel_encoder_commit (struct drm_encoder *encoder)
2462 {
2463         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2464         /* lvds has its own version of commit see intel_lvds_commit */
2465         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2466 }
2467
2468 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2469                                   struct drm_display_mode *mode,
2470                                   struct drm_display_mode *adjusted_mode)
2471 {
2472         struct drm_device *dev = crtc->dev;
2473         if (HAS_PCH_SPLIT(dev)) {
2474                 /* FDI link clock is fixed at 2.7G */
2475                 if (mode->clock * 3 > 27000 * 4)
2476                         return MODE_CLOCK_HIGH;
2477         }
2478         return true;
2479 }
2480
2481 static int i945_get_display_clock_speed(struct drm_device *dev)
2482 {
2483         return 400000;
2484 }
2485
2486 static int i915_get_display_clock_speed(struct drm_device *dev)
2487 {
2488         return 333000;
2489 }
2490
2491 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2492 {
2493         return 200000;
2494 }
2495
2496 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2497 {
2498         u16 gcfgc = 0;
2499
2500         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2501
2502         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2503                 return 133000;
2504         else {
2505                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2506                 case GC_DISPLAY_CLOCK_333_MHZ:
2507                         return 333000;
2508                 default:
2509                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2510                         return 190000;
2511                 }
2512         }
2513 }
2514
2515 static int i865_get_display_clock_speed(struct drm_device *dev)
2516 {
2517         return 266000;
2518 }
2519
2520 static int i855_get_display_clock_speed(struct drm_device *dev)
2521 {
2522         u16 hpllcc = 0;
2523         /* Assume that the hardware is in the high speed state.  This
2524          * should be the default.
2525          */
2526         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2527         case GC_CLOCK_133_200:
2528         case GC_CLOCK_100_200:
2529                 return 200000;
2530         case GC_CLOCK_166_250:
2531                 return 250000;
2532         case GC_CLOCK_100_133:
2533                 return 133000;
2534         }
2535
2536         /* Shouldn't happen */
2537         return 0;
2538 }
2539
2540 static int i830_get_display_clock_speed(struct drm_device *dev)
2541 {
2542         return 133000;
2543 }
2544
2545 /**
2546  * Return the pipe currently connected to the panel fitter,
2547  * or -1 if the panel fitter is not present or not in use
2548  */
2549 int intel_panel_fitter_pipe (struct drm_device *dev)
2550 {
2551         struct drm_i915_private *dev_priv = dev->dev_private;
2552         u32  pfit_control;
2553
2554         /* i830 doesn't have a panel fitter */
2555         if (IS_I830(dev))
2556                 return -1;
2557
2558         pfit_control = I915_READ(PFIT_CONTROL);
2559
2560         /* See if the panel fitter is in use */
2561         if ((pfit_control & PFIT_ENABLE) == 0)
2562                 return -1;
2563
2564         /* 965 can place panel fitter on either pipe */
2565         if (IS_I965G(dev))
2566                 return (pfit_control >> 29) & 0x3;
2567
2568         /* older chips can only use pipe 1 */
2569         return 1;
2570 }
2571
2572 struct fdi_m_n {
2573         u32        tu;
2574         u32        gmch_m;
2575         u32        gmch_n;
2576         u32        link_m;
2577         u32        link_n;
2578 };
2579
2580 static void
2581 fdi_reduce_ratio(u32 *num, u32 *den)
2582 {
2583         while (*num > 0xffffff || *den > 0xffffff) {
2584                 *num >>= 1;
2585                 *den >>= 1;
2586         }
2587 }
2588
2589 #define DATA_N 0x800000
2590 #define LINK_N 0x80000
2591
2592 static void
2593 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2594                      int link_clock, struct fdi_m_n *m_n)
2595 {
2596         u64 temp;
2597
2598         m_n->tu = 64; /* default size */
2599
2600         temp = (u64) DATA_N * pixel_clock;
2601         temp = div_u64(temp, link_clock);
2602         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2603         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2604         m_n->gmch_n = DATA_N;
2605         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2606
2607         temp = (u64) LINK_N * pixel_clock;
2608         m_n->link_m = div_u64(temp, link_clock);
2609         m_n->link_n = LINK_N;
2610         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2611 }
2612
2613
2614 struct intel_watermark_params {
2615         unsigned long fifo_size;
2616         unsigned long max_wm;
2617         unsigned long default_wm;
2618         unsigned long guard_size;
2619         unsigned long cacheline_size;
2620 };
2621
2622 /* Pineview has different values for various configs */
2623 static struct intel_watermark_params pineview_display_wm = {
2624         PINEVIEW_DISPLAY_FIFO,
2625         PINEVIEW_MAX_WM,
2626         PINEVIEW_DFT_WM,
2627         PINEVIEW_GUARD_WM,
2628         PINEVIEW_FIFO_LINE_SIZE
2629 };
2630 static struct intel_watermark_params pineview_display_hplloff_wm = {
2631         PINEVIEW_DISPLAY_FIFO,
2632         PINEVIEW_MAX_WM,
2633         PINEVIEW_DFT_HPLLOFF_WM,
2634         PINEVIEW_GUARD_WM,
2635         PINEVIEW_FIFO_LINE_SIZE
2636 };
2637 static struct intel_watermark_params pineview_cursor_wm = {
2638         PINEVIEW_CURSOR_FIFO,
2639         PINEVIEW_CURSOR_MAX_WM,
2640         PINEVIEW_CURSOR_DFT_WM,
2641         PINEVIEW_CURSOR_GUARD_WM,
2642         PINEVIEW_FIFO_LINE_SIZE,
2643 };
2644 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2645         PINEVIEW_CURSOR_FIFO,
2646         PINEVIEW_CURSOR_MAX_WM,
2647         PINEVIEW_CURSOR_DFT_WM,
2648         PINEVIEW_CURSOR_GUARD_WM,
2649         PINEVIEW_FIFO_LINE_SIZE
2650 };
2651 static struct intel_watermark_params g4x_wm_info = {
2652         G4X_FIFO_SIZE,
2653         G4X_MAX_WM,
2654         G4X_MAX_WM,
2655         2,
2656         G4X_FIFO_LINE_SIZE,
2657 };
2658 static struct intel_watermark_params i945_wm_info = {
2659         I945_FIFO_SIZE,
2660         I915_MAX_WM,
2661         1,
2662         2,
2663         I915_FIFO_LINE_SIZE
2664 };
2665 static struct intel_watermark_params i915_wm_info = {
2666         I915_FIFO_SIZE,
2667         I915_MAX_WM,
2668         1,
2669         2,
2670         I915_FIFO_LINE_SIZE
2671 };
2672 static struct intel_watermark_params i855_wm_info = {
2673         I855GM_FIFO_SIZE,
2674         I915_MAX_WM,
2675         1,
2676         2,
2677         I830_FIFO_LINE_SIZE
2678 };
2679 static struct intel_watermark_params i830_wm_info = {
2680         I830_FIFO_SIZE,
2681         I915_MAX_WM,
2682         1,
2683         2,
2684         I830_FIFO_LINE_SIZE
2685 };
2686
2687 static struct intel_watermark_params ironlake_display_wm_info = {
2688         ILK_DISPLAY_FIFO,
2689         ILK_DISPLAY_MAXWM,
2690         ILK_DISPLAY_DFTWM,
2691         2,
2692         ILK_FIFO_LINE_SIZE
2693 };
2694
2695 static struct intel_watermark_params ironlake_display_srwm_info = {
2696         ILK_DISPLAY_SR_FIFO,
2697         ILK_DISPLAY_MAX_SRWM,
2698         ILK_DISPLAY_DFT_SRWM,
2699         2,
2700         ILK_FIFO_LINE_SIZE
2701 };
2702
2703 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2704         ILK_CURSOR_SR_FIFO,
2705         ILK_CURSOR_MAX_SRWM,
2706         ILK_CURSOR_DFT_SRWM,
2707         2,
2708         ILK_FIFO_LINE_SIZE
2709 };
2710
2711 /**
2712  * intel_calculate_wm - calculate watermark level
2713  * @clock_in_khz: pixel clock
2714  * @wm: chip FIFO params
2715  * @pixel_size: display pixel size
2716  * @latency_ns: memory latency for the platform
2717  *
2718  * Calculate the watermark level (the level at which the display plane will
2719  * start fetching from memory again).  Each chip has a different display
2720  * FIFO size and allocation, so the caller needs to figure that out and pass
2721  * in the correct intel_watermark_params structure.
2722  *
2723  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2724  * on the pixel size.  When it reaches the watermark level, it'll start
2725  * fetching FIFO line sized based chunks from memory until the FIFO fills
2726  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2727  * will occur, and a display engine hang could result.
2728  */
2729 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2730                                         struct intel_watermark_params *wm,
2731                                         int pixel_size,
2732                                         unsigned long latency_ns)
2733 {
2734         long entries_required, wm_size;
2735
2736         /*
2737          * Note: we need to make sure we don't overflow for various clock &
2738          * latency values.
2739          * clocks go from a few thousand to several hundred thousand.
2740          * latency is usually a few thousand
2741          */
2742         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2743                 1000;
2744         entries_required /= wm->cacheline_size;
2745
2746         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2747
2748         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2749
2750         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2751
2752         /* Don't promote wm_size to unsigned... */
2753         if (wm_size > (long)wm->max_wm)
2754                 wm_size = wm->max_wm;
2755         if (wm_size <= 0)
2756                 wm_size = wm->default_wm;
2757         return wm_size;
2758 }
2759
2760 struct cxsr_latency {
2761         int is_desktop;
2762         int is_ddr3;
2763         unsigned long fsb_freq;
2764         unsigned long mem_freq;
2765         unsigned long display_sr;
2766         unsigned long display_hpll_disable;
2767         unsigned long cursor_sr;
2768         unsigned long cursor_hpll_disable;
2769 };
2770
2771 static struct cxsr_latency cxsr_latency_table[] = {
2772         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2773         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2774         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2775         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2776         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2777
2778         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2779         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2780         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2781         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2782         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2783
2784         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2785         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2786         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2787         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2788         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2789
2790         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2791         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2792         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2793         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2794         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2795
2796         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2797         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2798         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2799         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2800         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2801
2802         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2803         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2804         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2805         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2806         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2807 };
2808
2809 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3, 
2810                                                    int fsb, int mem)
2811 {
2812         int i;
2813         struct cxsr_latency *latency;
2814
2815         if (fsb == 0 || mem == 0)
2816                 return NULL;
2817
2818         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2819                 latency = &cxsr_latency_table[i];
2820                 if (is_desktop == latency->is_desktop &&
2821                     is_ddr3 == latency->is_ddr3 &&
2822                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2823                         return latency;
2824         }
2825
2826         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2827
2828         return NULL;
2829 }
2830
2831 static void pineview_disable_cxsr(struct drm_device *dev)
2832 {
2833         struct drm_i915_private *dev_priv = dev->dev_private;
2834         u32 reg;
2835
2836         /* deactivate cxsr */
2837         reg = I915_READ(DSPFW3);
2838         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2839         I915_WRITE(DSPFW3, reg);
2840         DRM_INFO("Big FIFO is disabled\n");
2841 }
2842
2843 /*
2844  * Latency for FIFO fetches is dependent on several factors:
2845  *   - memory configuration (speed, channels)
2846  *   - chipset
2847  *   - current MCH state
2848  * It can be fairly high in some situations, so here we assume a fairly
2849  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2850  * set this value too high, the FIFO will fetch frequently to stay full)
2851  * and power consumption (set it too low to save power and we might see
2852  * FIFO underruns and display "flicker").
2853  *
2854  * A value of 5us seems to be a good balance; safe for very low end
2855  * platforms but not overly aggressive on lower latency configs.
2856  */
2857 static const int latency_ns = 5000;
2858
2859 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2860 {
2861         struct drm_i915_private *dev_priv = dev->dev_private;
2862         uint32_t dsparb = I915_READ(DSPARB);
2863         int size;
2864
2865         if (plane == 0)
2866                 size = dsparb & 0x7f;
2867         else
2868                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2869                         (dsparb & 0x7f);
2870
2871         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2872                         plane ? "B" : "A", size);
2873
2874         return size;
2875 }
2876
2877 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2878 {
2879         struct drm_i915_private *dev_priv = dev->dev_private;
2880         uint32_t dsparb = I915_READ(DSPARB);
2881         int size;
2882
2883         if (plane == 0)
2884                 size = dsparb & 0x1ff;
2885         else
2886                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2887                         (dsparb & 0x1ff);
2888         size >>= 1; /* Convert to cachelines */
2889
2890         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2891                         plane ? "B" : "A", size);
2892
2893         return size;
2894 }
2895
2896 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2897 {
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         uint32_t dsparb = I915_READ(DSPARB);
2900         int size;
2901
2902         size = dsparb & 0x7f;
2903         size >>= 2; /* Convert to cachelines */
2904
2905         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2906                         plane ? "B" : "A",
2907                   size);
2908
2909         return size;
2910 }
2911
2912 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2913 {
2914         struct drm_i915_private *dev_priv = dev->dev_private;
2915         uint32_t dsparb = I915_READ(DSPARB);
2916         int size;
2917
2918         size = dsparb & 0x7f;
2919         size >>= 1; /* Convert to cachelines */
2920
2921         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2922                         plane ? "B" : "A", size);
2923
2924         return size;
2925 }
2926
2927 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2928                           int planeb_clock, int sr_hdisplay, int pixel_size)
2929 {
2930         struct drm_i915_private *dev_priv = dev->dev_private;
2931         u32 reg;
2932         unsigned long wm;
2933         struct cxsr_latency *latency;
2934         int sr_clock;
2935
2936         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 
2937                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2938         if (!latency) {
2939                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2940                 pineview_disable_cxsr(dev);
2941                 return;
2942         }
2943
2944         if (!planea_clock || !planeb_clock) {
2945                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2946
2947                 /* Display SR */
2948                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2949                                         pixel_size, latency->display_sr);
2950                 reg = I915_READ(DSPFW1);
2951                 reg &= ~DSPFW_SR_MASK;
2952                 reg |= wm << DSPFW_SR_SHIFT;
2953                 I915_WRITE(DSPFW1, reg);
2954                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2955
2956                 /* cursor SR */
2957                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2958                                         pixel_size, latency->cursor_sr);
2959                 reg = I915_READ(DSPFW3);
2960                 reg &= ~DSPFW_CURSOR_SR_MASK;
2961                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2962                 I915_WRITE(DSPFW3, reg);
2963
2964                 /* Display HPLL off SR */
2965                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2966                                         pixel_size, latency->display_hpll_disable);
2967                 reg = I915_READ(DSPFW3);
2968                 reg &= ~DSPFW_HPLL_SR_MASK;
2969                 reg |= wm & DSPFW_HPLL_SR_MASK;
2970                 I915_WRITE(DSPFW3, reg);
2971
2972                 /* cursor HPLL off SR */
2973                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2974                                         pixel_size, latency->cursor_hpll_disable);
2975                 reg = I915_READ(DSPFW3);
2976                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2977                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2978                 I915_WRITE(DSPFW3, reg);
2979                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2980
2981                 /* activate cxsr */
2982                 reg = I915_READ(DSPFW3);
2983                 reg |= PINEVIEW_SELF_REFRESH_EN;
2984                 I915_WRITE(DSPFW3, reg);
2985                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2986         } else {
2987                 pineview_disable_cxsr(dev);
2988                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2989         }
2990 }
2991
2992 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2993                           int planeb_clock, int sr_hdisplay, int pixel_size)
2994 {
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996         int total_size, cacheline_size;
2997         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2998         struct intel_watermark_params planea_params, planeb_params;
2999         unsigned long line_time_us;
3000         int sr_clock, sr_entries = 0, entries_required;
3001
3002         /* Create copies of the base settings for each pipe */
3003         planea_params = planeb_params = g4x_wm_info;
3004