Merge tag 'drm-intel-next-2016-10-24' of git://anongit.freedesktop.org/drm-intel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_dmabuf.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54         return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59         DRM_FORMAT_C8,
60         DRM_FORMAT_RGB565,
61         DRM_FORMAT_XRGB1555,
62         DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67         DRM_FORMAT_C8,
68         DRM_FORMAT_RGB565,
69         DRM_FORMAT_XRGB8888,
70         DRM_FORMAT_XBGR8888,
71         DRM_FORMAT_XRGB2101010,
72         DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76         DRM_FORMAT_C8,
77         DRM_FORMAT_RGB565,
78         DRM_FORMAT_XRGB8888,
79         DRM_FORMAT_XBGR8888,
80         DRM_FORMAT_ARGB8888,
81         DRM_FORMAT_ABGR8888,
82         DRM_FORMAT_XRGB2101010,
83         DRM_FORMAT_XBGR2101010,
84         DRM_FORMAT_YUYV,
85         DRM_FORMAT_YVYU,
86         DRM_FORMAT_UYVY,
87         DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92         DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96                                 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98                                    struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct drm_device *dev,
101                                   struct intel_framebuffer *ifb,
102                                   struct drm_mode_fb_cmd2 *mode_cmd,
103                                   struct drm_i915_gem_object *obj);
104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
108                                          struct intel_link_m_n *m_n,
109                                          struct intel_link_m_n *m2_n2);
110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
113 static void vlv_prepare_pll(struct intel_crtc *crtc,
114                             const struct intel_crtc_state *pipe_config);
115 static void chv_prepare_pll(struct intel_crtc *crtc,
116                             const struct intel_crtc_state *pipe_config);
117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
120         struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
128
129 struct intel_limit {
130         struct {
131                 int min, max;
132         } dot, vco, n, m, m1, m2, p, p1;
133
134         struct {
135                 int dot_limit;
136                 int p2_slow, p2_fast;
137         } p2;
138 };
139
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
142 {
143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144
145         /* Obtain SKU information */
146         mutex_lock(&dev_priv->sb_lock);
147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148                 CCK_FUSE_HPLL_FREQ_MASK;
149         mutex_unlock(&dev_priv->sb_lock);
150
151         return vco_freq[hpll_freq] * 1000;
152 }
153
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155                       const char *name, u32 reg, int ref_freq)
156 {
157         u32 val;
158         int divider;
159
160         mutex_lock(&dev_priv->sb_lock);
161         val = vlv_cck_read(dev_priv, reg);
162         mutex_unlock(&dev_priv->sb_lock);
163
164         divider = val & CCK_FREQUENCY_VALUES;
165
166         WARN((val & CCK_FREQUENCY_STATUS) !=
167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
168              "%s change in progress\n", name);
169
170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
171 }
172
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174                                   const char *name, u32 reg)
175 {
176         if (dev_priv->hpll_freq == 0)
177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
178
179         return vlv_get_cck_clock(dev_priv, name, reg,
180                                  dev_priv->hpll_freq);
181 }
182
183 static int
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
185 {
186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
187 }
188
189 static int
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
191 {
192         /* RAWCLK_FREQ_VLV register updated from power well code */
193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
195 }
196
197 static int
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
199 {
200         uint32_t clkcfg;
201
202         /* hrawclock is 1/4 the FSB frequency */
203         clkcfg = I915_READ(CLKCFG);
204         switch (clkcfg & CLKCFG_FSB_MASK) {
205         case CLKCFG_FSB_400:
206                 return 100000;
207         case CLKCFG_FSB_533:
208                 return 133333;
209         case CLKCFG_FSB_667:
210                 return 166667;
211         case CLKCFG_FSB_800:
212                 return 200000;
213         case CLKCFG_FSB_1067:
214                 return 266667;
215         case CLKCFG_FSB_1333:
216                 return 333333;
217         /* these two are just a guess; one of them might be right */
218         case CLKCFG_FSB_1600:
219         case CLKCFG_FSB_1600_ALT:
220                 return 400000;
221         default:
222                 return 133333;
223         }
224 }
225
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
227 {
228         if (HAS_PCH_SPLIT(dev_priv))
229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
234         else
235                 return; /* no rawclk on other platforms, or no need to know it */
236
237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
238 }
239
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
241 {
242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
243                 return;
244
245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246                                                       CCK_CZ_CLOCK_CONTROL);
247
248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
249 }
250
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253                     const struct intel_crtc_state *pipe_config)
254 {
255         if (HAS_DDI(dev_priv))
256                 return pipe_config->port_clock; /* SPLL */
257         else if (IS_GEN5(dev_priv))
258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
259         else
260                 return 270000;
261 }
262
263 static const struct intel_limit intel_limits_i8xx_dac = {
264         .dot = { .min = 25000, .max = 350000 },
265         .vco = { .min = 908000, .max = 1512000 },
266         .n = { .min = 2, .max = 16 },
267         .m = { .min = 96, .max = 140 },
268         .m1 = { .min = 18, .max = 26 },
269         .m2 = { .min = 6, .max = 16 },
270         .p = { .min = 4, .max = 128 },
271         .p1 = { .min = 2, .max = 33 },
272         .p2 = { .dot_limit = 165000,
273                 .p2_slow = 4, .p2_fast = 2 },
274 };
275
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277         .dot = { .min = 25000, .max = 350000 },
278         .vco = { .min = 908000, .max = 1512000 },
279         .n = { .min = 2, .max = 16 },
280         .m = { .min = 96, .max = 140 },
281         .m1 = { .min = 18, .max = 26 },
282         .m2 = { .min = 6, .max = 16 },
283         .p = { .min = 4, .max = 128 },
284         .p1 = { .min = 2, .max = 33 },
285         .p2 = { .dot_limit = 165000,
286                 .p2_slow = 4, .p2_fast = 4 },
287 };
288
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290         .dot = { .min = 25000, .max = 350000 },
291         .vco = { .min = 908000, .max = 1512000 },
292         .n = { .min = 2, .max = 16 },
293         .m = { .min = 96, .max = 140 },
294         .m1 = { .min = 18, .max = 26 },
295         .m2 = { .min = 6, .max = 16 },
296         .p = { .min = 4, .max = 128 },
297         .p1 = { .min = 1, .max = 6 },
298         .p2 = { .dot_limit = 165000,
299                 .p2_slow = 14, .p2_fast = 7 },
300 };
301
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303         .dot = { .min = 20000, .max = 400000 },
304         .vco = { .min = 1400000, .max = 2800000 },
305         .n = { .min = 1, .max = 6 },
306         .m = { .min = 70, .max = 120 },
307         .m1 = { .min = 8, .max = 18 },
308         .m2 = { .min = 3, .max = 7 },
309         .p = { .min = 5, .max = 80 },
310         .p1 = { .min = 1, .max = 8 },
311         .p2 = { .dot_limit = 200000,
312                 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316         .dot = { .min = 20000, .max = 400000 },
317         .vco = { .min = 1400000, .max = 2800000 },
318         .n = { .min = 1, .max = 6 },
319         .m = { .min = 70, .max = 120 },
320         .m1 = { .min = 8, .max = 18 },
321         .m2 = { .min = 3, .max = 7 },
322         .p = { .min = 7, .max = 98 },
323         .p1 = { .min = 1, .max = 8 },
324         .p2 = { .dot_limit = 112000,
325                 .p2_slow = 14, .p2_fast = 7 },
326 };
327
328
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330         .dot = { .min = 25000, .max = 270000 },
331         .vco = { .min = 1750000, .max = 3500000},
332         .n = { .min = 1, .max = 4 },
333         .m = { .min = 104, .max = 138 },
334         .m1 = { .min = 17, .max = 23 },
335         .m2 = { .min = 5, .max = 11 },
336         .p = { .min = 10, .max = 30 },
337         .p1 = { .min = 1, .max = 3},
338         .p2 = { .dot_limit = 270000,
339                 .p2_slow = 10,
340                 .p2_fast = 10
341         },
342 };
343
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345         .dot = { .min = 22000, .max = 400000 },
346         .vco = { .min = 1750000, .max = 3500000},
347         .n = { .min = 1, .max = 4 },
348         .m = { .min = 104, .max = 138 },
349         .m1 = { .min = 16, .max = 23 },
350         .m2 = { .min = 5, .max = 11 },
351         .p = { .min = 5, .max = 80 },
352         .p1 = { .min = 1, .max = 8},
353         .p2 = { .dot_limit = 165000,
354                 .p2_slow = 10, .p2_fast = 5 },
355 };
356
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358         .dot = { .min = 20000, .max = 115000 },
359         .vco = { .min = 1750000, .max = 3500000 },
360         .n = { .min = 1, .max = 3 },
361         .m = { .min = 104, .max = 138 },
362         .m1 = { .min = 17, .max = 23 },
363         .m2 = { .min = 5, .max = 11 },
364         .p = { .min = 28, .max = 112 },
365         .p1 = { .min = 2, .max = 8 },
366         .p2 = { .dot_limit = 0,
367                 .p2_slow = 14, .p2_fast = 14
368         },
369 };
370
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372         .dot = { .min = 80000, .max = 224000 },
373         .vco = { .min = 1750000, .max = 3500000 },
374         .n = { .min = 1, .max = 3 },
375         .m = { .min = 104, .max = 138 },
376         .m1 = { .min = 17, .max = 23 },
377         .m2 = { .min = 5, .max = 11 },
378         .p = { .min = 14, .max = 42 },
379         .p1 = { .min = 2, .max = 6 },
380         .p2 = { .dot_limit = 0,
381                 .p2_slow = 7, .p2_fast = 7
382         },
383 };
384
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386         .dot = { .min = 20000, .max = 400000},
387         .vco = { .min = 1700000, .max = 3500000 },
388         /* Pineview's Ncounter is a ring counter */
389         .n = { .min = 3, .max = 6 },
390         .m = { .min = 2, .max = 256 },
391         /* Pineview only has one combined m divider, which we treat as m2. */
392         .m1 = { .min = 0, .max = 0 },
393         .m2 = { .min = 0, .max = 254 },
394         .p = { .min = 5, .max = 80 },
395         .p1 = { .min = 1, .max = 8 },
396         .p2 = { .dot_limit = 200000,
397                 .p2_slow = 10, .p2_fast = 5 },
398 };
399
400 static const struct intel_limit intel_limits_pineview_lvds = {
401         .dot = { .min = 20000, .max = 400000 },
402         .vco = { .min = 1700000, .max = 3500000 },
403         .n = { .min = 3, .max = 6 },
404         .m = { .min = 2, .max = 256 },
405         .m1 = { .min = 0, .max = 0 },
406         .m2 = { .min = 0, .max = 254 },
407         .p = { .min = 7, .max = 112 },
408         .p1 = { .min = 1, .max = 8 },
409         .p2 = { .dot_limit = 112000,
410                 .p2_slow = 14, .p2_fast = 14 },
411 };
412
413 /* Ironlake / Sandybridge
414  *
415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
416  * the range value for them is (actual_value - 2).
417  */
418 static const struct intel_limit intel_limits_ironlake_dac = {
419         .dot = { .min = 25000, .max = 350000 },
420         .vco = { .min = 1760000, .max = 3510000 },
421         .n = { .min = 1, .max = 5 },
422         .m = { .min = 79, .max = 127 },
423         .m1 = { .min = 12, .max = 22 },
424         .m2 = { .min = 5, .max = 9 },
425         .p = { .min = 5, .max = 80 },
426         .p1 = { .min = 1, .max = 8 },
427         .p2 = { .dot_limit = 225000,
428                 .p2_slow = 10, .p2_fast = 5 },
429 };
430
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432         .dot = { .min = 25000, .max = 350000 },
433         .vco = { .min = 1760000, .max = 3510000 },
434         .n = { .min = 1, .max = 3 },
435         .m = { .min = 79, .max = 118 },
436         .m1 = { .min = 12, .max = 22 },
437         .m2 = { .min = 5, .max = 9 },
438         .p = { .min = 28, .max = 112 },
439         .p1 = { .min = 2, .max = 8 },
440         .p2 = { .dot_limit = 225000,
441                 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445         .dot = { .min = 25000, .max = 350000 },
446         .vco = { .min = 1760000, .max = 3510000 },
447         .n = { .min = 1, .max = 3 },
448         .m = { .min = 79, .max = 127 },
449         .m1 = { .min = 12, .max = 22 },
450         .m2 = { .min = 5, .max = 9 },
451         .p = { .min = 14, .max = 56 },
452         .p1 = { .min = 2, .max = 8 },
453         .p2 = { .dot_limit = 225000,
454                 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459         .dot = { .min = 25000, .max = 350000 },
460         .vco = { .min = 1760000, .max = 3510000 },
461         .n = { .min = 1, .max = 2 },
462         .m = { .min = 79, .max = 126 },
463         .m1 = { .min = 12, .max = 22 },
464         .m2 = { .min = 5, .max = 9 },
465         .p = { .min = 28, .max = 112 },
466         .p1 = { .min = 2, .max = 8 },
467         .p2 = { .dot_limit = 225000,
468                 .p2_slow = 14, .p2_fast = 14 },
469 };
470
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472         .dot = { .min = 25000, .max = 350000 },
473         .vco = { .min = 1760000, .max = 3510000 },
474         .n = { .min = 1, .max = 3 },
475         .m = { .min = 79, .max = 126 },
476         .m1 = { .min = 12, .max = 22 },
477         .m2 = { .min = 5, .max = 9 },
478         .p = { .min = 14, .max = 42 },
479         .p1 = { .min = 2, .max = 6 },
480         .p2 = { .dot_limit = 225000,
481                 .p2_slow = 7, .p2_fast = 7 },
482 };
483
484 static const struct intel_limit intel_limits_vlv = {
485          /*
486           * These are the data rate limits (measured in fast clocks)
487           * since those are the strictest limits we have. The fast
488           * clock and actual rate limits are more relaxed, so checking
489           * them would make no difference.
490           */
491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492         .vco = { .min = 4000000, .max = 6000000 },
493         .n = { .min = 1, .max = 7 },
494         .m1 = { .min = 2, .max = 3 },
495         .m2 = { .min = 11, .max = 156 },
496         .p1 = { .min = 2, .max = 3 },
497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
498 };
499
500 static const struct intel_limit intel_limits_chv = {
501         /*
502          * These are the data rate limits (measured in fast clocks)
503          * since those are the strictest limits we have.  The fast
504          * clock and actual rate limits are more relaxed, so checking
505          * them would make no difference.
506          */
507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
508         .vco = { .min = 4800000, .max = 6480000 },
509         .n = { .min = 1, .max = 1 },
510         .m1 = { .min = 2, .max = 2 },
511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
512         .p1 = { .min = 2, .max = 4 },
513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
514 };
515
516 static const struct intel_limit intel_limits_bxt = {
517         /* FIXME: find real dot limits */
518         .dot = { .min = 0, .max = INT_MAX },
519         .vco = { .min = 4800000, .max = 6700000 },
520         .n = { .min = 1, .max = 1 },
521         .m1 = { .min = 2, .max = 2 },
522         /* FIXME: find real m2 limits */
523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
524         .p1 = { .min = 2, .max = 4 },
525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
526 };
527
528 static bool
529 needs_modeset(struct drm_crtc_state *state)
530 {
531         return drm_atomic_crtc_needs_modeset(state);
532 }
533
534 /*
535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538  * The helpers' return value is the rate of the clock that is fed to the
539  * display engine's pipe which can be the above fast dot clock rate or a
540  * divided-down version of it.
541  */
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
544 {
545         clock->m = clock->m2 + 2;
546         clock->p = clock->p1 * clock->p2;
547         if (WARN_ON(clock->n == 0 || clock->p == 0))
548                 return 0;
549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
551
552         return clock->dot;
553 }
554
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
556 {
557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
558 }
559
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
561 {
562         clock->m = i9xx_dpll_compute_m(clock);
563         clock->p = clock->p1 * clock->p2;
564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
565                 return 0;
566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568
569         return clock->dot;
570 }
571
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
573 {
574         clock->m = clock->m1 * clock->m2;
575         clock->p = clock->p1 * clock->p2;
576         if (WARN_ON(clock->n == 0 || clock->p == 0))
577                 return 0;
578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580
581         return clock->dot / 5;
582 }
583
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
585 {
586         clock->m = clock->m1 * clock->m2;
587         clock->p = clock->p1 * clock->p2;
588         if (WARN_ON(clock->n == 0 || clock->p == 0))
589                 return 0;
590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591                         clock->n << 22);
592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593
594         return clock->dot / 5;
595 }
596
597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
598 /**
599  * Returns whether the given set of divisors are valid for a given refclk with
600  * the given connectors.
601  */
602
603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
604                                const struct intel_limit *limit,
605                                const struct dpll *clock)
606 {
607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
608                 INTELPllInvalid("n out of range\n");
609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
610                 INTELPllInvalid("p1 out of range\n");
611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
612                 INTELPllInvalid("m2 out of range\n");
613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
614                 INTELPllInvalid("m1 out of range\n");
615
616         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
617             !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
618                 if (clock->m1 <= clock->m2)
619                         INTELPllInvalid("m1 <= m2\n");
620
621         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
622             !IS_BROXTON(dev_priv)) {
623                 if (clock->p < limit->p.min || limit->p.max < clock->p)
624                         INTELPllInvalid("p out of range\n");
625                 if (clock->m < limit->m.min || limit->m.max < clock->m)
626                         INTELPllInvalid("m out of range\n");
627         }
628
629         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
630                 INTELPllInvalid("vco out of range\n");
631         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
632          * connector, etc., rather than just a single range.
633          */
634         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
635                 INTELPllInvalid("dot out of range\n");
636
637         return true;
638 }
639
640 static int
641 i9xx_select_p2_div(const struct intel_limit *limit,
642                    const struct intel_crtc_state *crtc_state,
643                    int target)
644 {
645         struct drm_device *dev = crtc_state->base.crtc->dev;
646
647         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
648                 /*
649                  * For LVDS just rely on its current settings for dual-channel.
650                  * We haven't figured out how to reliably set up different
651                  * single/dual channel state, if we even can.
652                  */
653                 if (intel_is_dual_link_lvds(dev))
654                         return limit->p2.p2_fast;
655                 else
656                         return limit->p2.p2_slow;
657         } else {
658                 if (target < limit->p2.dot_limit)
659                         return limit->p2.p2_slow;
660                 else
661                         return limit->p2.p2_fast;
662         }
663 }
664
665 /*
666  * Returns a set of divisors for the desired target clock with the given
667  * refclk, or FALSE.  The returned values represent the clock equation:
668  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
669  *
670  * Target and reference clocks are specified in kHz.
671  *
672  * If match_clock is provided, then best_clock P divider must match the P
673  * divider from @match_clock used for LVDS downclocking.
674  */
675 static bool
676 i9xx_find_best_dpll(const struct intel_limit *limit,
677                     struct intel_crtc_state *crtc_state,
678                     int target, int refclk, struct dpll *match_clock,
679                     struct dpll *best_clock)
680 {
681         struct drm_device *dev = crtc_state->base.crtc->dev;
682         struct dpll clock;
683         int err = target;
684
685         memset(best_clock, 0, sizeof(*best_clock));
686
687         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
688
689         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
690              clock.m1++) {
691                 for (clock.m2 = limit->m2.min;
692                      clock.m2 <= limit->m2.max; clock.m2++) {
693                         if (clock.m2 >= clock.m1)
694                                 break;
695                         for (clock.n = limit->n.min;
696                              clock.n <= limit->n.max; clock.n++) {
697                                 for (clock.p1 = limit->p1.min;
698                                         clock.p1 <= limit->p1.max; clock.p1++) {
699                                         int this_err;
700
701                                         i9xx_calc_dpll_params(refclk, &clock);
702                                         if (!intel_PLL_is_valid(to_i915(dev),
703                                                                 limit,
704                                                                 &clock))
705                                                 continue;
706                                         if (match_clock &&
707                                             clock.p != match_clock->p)
708                                                 continue;
709
710                                         this_err = abs(clock.dot - target);
711                                         if (this_err < err) {
712                                                 *best_clock = clock;
713                                                 err = this_err;
714                                         }
715                                 }
716                         }
717                 }
718         }
719
720         return (err != target);
721 }
722
723 /*
724  * Returns a set of divisors for the desired target clock with the given
725  * refclk, or FALSE.  The returned values represent the clock equation:
726  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
727  *
728  * Target and reference clocks are specified in kHz.
729  *
730  * If match_clock is provided, then best_clock P divider must match the P
731  * divider from @match_clock used for LVDS downclocking.
732  */
733 static bool
734 pnv_find_best_dpll(const struct intel_limit *limit,
735                    struct intel_crtc_state *crtc_state,
736                    int target, int refclk, struct dpll *match_clock,
737                    struct dpll *best_clock)
738 {
739         struct drm_device *dev = crtc_state->base.crtc->dev;
740         struct dpll clock;
741         int err = target;
742
743         memset(best_clock, 0, sizeof(*best_clock));
744
745         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746
747         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
748              clock.m1++) {
749                 for (clock.m2 = limit->m2.min;
750                      clock.m2 <= limit->m2.max; clock.m2++) {
751                         for (clock.n = limit->n.min;
752                              clock.n <= limit->n.max; clock.n++) {
753                                 for (clock.p1 = limit->p1.min;
754                                         clock.p1 <= limit->p1.max; clock.p1++) {
755                                         int this_err;
756
757                                         pnv_calc_dpll_params(refclk, &clock);
758                                         if (!intel_PLL_is_valid(to_i915(dev),
759                                                                 limit,
760                                                                 &clock))
761                                                 continue;
762                                         if (match_clock &&
763                                             clock.p != match_clock->p)
764                                                 continue;
765
766                                         this_err = abs(clock.dot - target);
767                                         if (this_err < err) {
768                                                 *best_clock = clock;
769                                                 err = this_err;
770                                         }
771                                 }
772                         }
773                 }
774         }
775
776         return (err != target);
777 }
778
779 /*
780  * Returns a set of divisors for the desired target clock with the given
781  * refclk, or FALSE.  The returned values represent the clock equation:
782  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
783  *
784  * Target and reference clocks are specified in kHz.
785  *
786  * If match_clock is provided, then best_clock P divider must match the P
787  * divider from @match_clock used for LVDS downclocking.
788  */
789 static bool
790 g4x_find_best_dpll(const struct intel_limit *limit,
791                    struct intel_crtc_state *crtc_state,
792                    int target, int refclk, struct dpll *match_clock,
793                    struct dpll *best_clock)
794 {
795         struct drm_device *dev = crtc_state->base.crtc->dev;
796         struct dpll clock;
797         int max_n;
798         bool found = false;
799         /* approximately equals target * 0.00585 */
800         int err_most = (target >> 8) + (target >> 9);
801
802         memset(best_clock, 0, sizeof(*best_clock));
803
804         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
805
806         max_n = limit->n.max;
807         /* based on hardware requirement, prefer smaller n to precision */
808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
809                 /* based on hardware requirement, prefere larger m1,m2 */
810                 for (clock.m1 = limit->m1.max;
811                      clock.m1 >= limit->m1.min; clock.m1--) {
812                         for (clock.m2 = limit->m2.max;
813                              clock.m2 >= limit->m2.min; clock.m2--) {
814                                 for (clock.p1 = limit->p1.max;
815                                      clock.p1 >= limit->p1.min; clock.p1--) {
816                                         int this_err;
817
818                                         i9xx_calc_dpll_params(refclk, &clock);
819                                         if (!intel_PLL_is_valid(to_i915(dev),
820                                                                 limit,
821                                                                 &clock))
822                                                 continue;
823
824                                         this_err = abs(clock.dot - target);
825                                         if (this_err < err_most) {
826                                                 *best_clock = clock;
827                                                 err_most = this_err;
828                                                 max_n = clock.n;
829                                                 found = true;
830                                         }
831                                 }
832                         }
833                 }
834         }
835         return found;
836 }
837
838 /*
839  * Check if the calculated PLL configuration is more optimal compared to the
840  * best configuration and error found so far. Return the calculated error.
841  */
842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
843                                const struct dpll *calculated_clock,
844                                const struct dpll *best_clock,
845                                unsigned int best_error_ppm,
846                                unsigned int *error_ppm)
847 {
848         /*
849          * For CHV ignore the error and consider only the P value.
850          * Prefer a bigger P value based on HW requirements.
851          */
852         if (IS_CHERRYVIEW(to_i915(dev))) {
853                 *error_ppm = 0;
854
855                 return calculated_clock->p > best_clock->p;
856         }
857
858         if (WARN_ON_ONCE(!target_freq))
859                 return false;
860
861         *error_ppm = div_u64(1000000ULL *
862                                 abs(target_freq - calculated_clock->dot),
863                              target_freq);
864         /*
865          * Prefer a better P value over a better (smaller) error if the error
866          * is small. Ensure this preference for future configurations too by
867          * setting the error to 0.
868          */
869         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
870                 *error_ppm = 0;
871
872                 return true;
873         }
874
875         return *error_ppm + 10 < best_error_ppm;
876 }
877
878 /*
879  * Returns a set of divisors for the desired target clock with the given
880  * refclk, or FALSE.  The returned values represent the clock equation:
881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
882  */
883 static bool
884 vlv_find_best_dpll(const struct intel_limit *limit,
885                    struct intel_crtc_state *crtc_state,
886                    int target, int refclk, struct dpll *match_clock,
887                    struct dpll *best_clock)
888 {
889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
890         struct drm_device *dev = crtc->base.dev;
891         struct dpll clock;
892         unsigned int bestppm = 1000000;
893         /* min update 19.2 MHz */
894         int max_n = min(limit->n.max, refclk / 19200);
895         bool found = false;
896
897         target *= 5; /* fast clock */
898
899         memset(best_clock, 0, sizeof(*best_clock));
900
901         /* based on hardware requirement, prefer smaller n to precision */
902         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
903                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
904                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
905                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
906                                 clock.p = clock.p1 * clock.p2;
907                                 /* based on hardware requirement, prefer bigger m1,m2 values */
908                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
909                                         unsigned int ppm;
910
911                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
912                                                                      refclk * clock.m1);
913
914                                         vlv_calc_dpll_params(refclk, &clock);
915
916                                         if (!intel_PLL_is_valid(to_i915(dev),
917                                                                 limit,
918                                                                 &clock))
919                                                 continue;
920
921                                         if (!vlv_PLL_is_optimal(dev, target,
922                                                                 &clock,
923                                                                 best_clock,
924                                                                 bestppm, &ppm))
925                                                 continue;
926
927                                         *best_clock = clock;
928                                         bestppm = ppm;
929                                         found = true;
930                                 }
931                         }
932                 }
933         }
934
935         return found;
936 }
937
938 /*
939  * Returns a set of divisors for the desired target clock with the given
940  * refclk, or FALSE.  The returned values represent the clock equation:
941  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
942  */
943 static bool
944 chv_find_best_dpll(const struct intel_limit *limit,
945                    struct intel_crtc_state *crtc_state,
946                    int target, int refclk, struct dpll *match_clock,
947                    struct dpll *best_clock)
948 {
949         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
950         struct drm_device *dev = crtc->base.dev;
951         unsigned int best_error_ppm;
952         struct dpll clock;
953         uint64_t m2;
954         int found = false;
955
956         memset(best_clock, 0, sizeof(*best_clock));
957         best_error_ppm = 1000000;
958
959         /*
960          * Based on hardware doc, the n always set to 1, and m1 always
961          * set to 2.  If requires to support 200Mhz refclk, we need to
962          * revisit this because n may not 1 anymore.
963          */
964         clock.n = 1, clock.m1 = 2;
965         target *= 5;    /* fast clock */
966
967         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
968                 for (clock.p2 = limit->p2.p2_fast;
969                                 clock.p2 >= limit->p2.p2_slow;
970                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
971                         unsigned int error_ppm;
972
973                         clock.p = clock.p1 * clock.p2;
974
975                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
976                                         clock.n) << 22, refclk * clock.m1);
977
978                         if (m2 > INT_MAX/clock.m1)
979                                 continue;
980
981                         clock.m2 = m2;
982
983                         chv_calc_dpll_params(refclk, &clock);
984
985                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
986                                 continue;
987
988                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
989                                                 best_error_ppm, &error_ppm))
990                                 continue;
991
992                         *best_clock = clock;
993                         best_error_ppm = error_ppm;
994                         found = true;
995                 }
996         }
997
998         return found;
999 }
1000
1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1002                         struct dpll *best_clock)
1003 {
1004         int refclk = 100000;
1005         const struct intel_limit *limit = &intel_limits_bxt;
1006
1007         return chv_find_best_dpll(limit, crtc_state,
1008                                   target_clock, refclk, NULL, best_clock);
1009 }
1010
1011 bool intel_crtc_active(struct drm_crtc *crtc)
1012 {
1013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1014
1015         /* Be paranoid as we can arrive here with only partial
1016          * state retrieved from the hardware during setup.
1017          *
1018          * We can ditch the adjusted_mode.crtc_clock check as soon
1019          * as Haswell has gained clock readout/fastboot support.
1020          *
1021          * We can ditch the crtc->primary->fb check as soon as we can
1022          * properly reconstruct framebuffers.
1023          *
1024          * FIXME: The intel_crtc->active here should be switched to
1025          * crtc->state->active once we have proper CRTC states wired up
1026          * for atomic.
1027          */
1028         return intel_crtc->active && crtc->primary->state->fb &&
1029                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1030 }
1031
1032 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1033                                              enum pipe pipe)
1034 {
1035         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1037
1038         return intel_crtc->config->cpu_transcoder;
1039 }
1040
1041 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1042 {
1043         struct drm_i915_private *dev_priv = to_i915(dev);
1044         i915_reg_t reg = PIPEDSL(pipe);
1045         u32 line1, line2;
1046         u32 line_mask;
1047
1048         if (IS_GEN2(dev_priv))
1049                 line_mask = DSL_LINEMASK_GEN2;
1050         else
1051                 line_mask = DSL_LINEMASK_GEN3;
1052
1053         line1 = I915_READ(reg) & line_mask;
1054         msleep(5);
1055         line2 = I915_READ(reg) & line_mask;
1056
1057         return line1 == line2;
1058 }
1059
1060 /*
1061  * intel_wait_for_pipe_off - wait for pipe to turn off
1062  * @crtc: crtc whose pipe to wait for
1063  *
1064  * After disabling a pipe, we can't wait for vblank in the usual way,
1065  * spinning on the vblank interrupt status bit, since we won't actually
1066  * see an interrupt when the pipe is disabled.
1067  *
1068  * On Gen4 and above:
1069  *   wait for the pipe register state bit to turn off
1070  *
1071  * Otherwise:
1072  *   wait for the display line value to settle (it usually
1073  *   ends up stopping at the start of the next frame).
1074  *
1075  */
1076 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1077 {
1078         struct drm_device *dev = crtc->base.dev;
1079         struct drm_i915_private *dev_priv = to_i915(dev);
1080         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1081         enum pipe pipe = crtc->pipe;
1082
1083         if (INTEL_INFO(dev)->gen >= 4) {
1084                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1085
1086                 /* Wait for the Pipe State to go off */
1087                 if (intel_wait_for_register(dev_priv,
1088                                             reg, I965_PIPECONF_ACTIVE, 0,
1089                                             100))
1090                         WARN(1, "pipe_off wait timed out\n");
1091         } else {
1092                 /* Wait for the display line to settle */
1093                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1094                         WARN(1, "pipe_off wait timed out\n");
1095         }
1096 }
1097
1098 /* Only for pre-ILK configs */
1099 void assert_pll(struct drm_i915_private *dev_priv,
1100                 enum pipe pipe, bool state)
1101 {
1102         u32 val;
1103         bool cur_state;
1104
1105         val = I915_READ(DPLL(pipe));
1106         cur_state = !!(val & DPLL_VCO_ENABLE);
1107         I915_STATE_WARN(cur_state != state,
1108              "PLL state assertion failure (expected %s, current %s)\n",
1109                         onoff(state), onoff(cur_state));
1110 }
1111
1112 /* XXX: the dsi pll is shared between MIPI DSI ports */
1113 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1114 {
1115         u32 val;
1116         bool cur_state;
1117
1118         mutex_lock(&dev_priv->sb_lock);
1119         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1120         mutex_unlock(&dev_priv->sb_lock);
1121
1122         cur_state = val & DSI_PLL_VCO_EN;
1123         I915_STATE_WARN(cur_state != state,
1124              "DSI PLL state assertion failure (expected %s, current %s)\n",
1125                         onoff(state), onoff(cur_state));
1126 }
1127
1128 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1129                           enum pipe pipe, bool state)
1130 {
1131         bool cur_state;
1132         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1133                                                                       pipe);
1134
1135         if (HAS_DDI(dev_priv)) {
1136                 /* DDI does not have a specific FDI_TX register */
1137                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1138                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1139         } else {
1140                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1141                 cur_state = !!(val & FDI_TX_ENABLE);
1142         }
1143         I915_STATE_WARN(cur_state != state,
1144              "FDI TX state assertion failure (expected %s, current %s)\n",
1145                         onoff(state), onoff(cur_state));
1146 }
1147 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1148 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1149
1150 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1151                           enum pipe pipe, bool state)
1152 {
1153         u32 val;
1154         bool cur_state;
1155
1156         val = I915_READ(FDI_RX_CTL(pipe));
1157         cur_state = !!(val & FDI_RX_ENABLE);
1158         I915_STATE_WARN(cur_state != state,
1159              "FDI RX state assertion failure (expected %s, current %s)\n",
1160                         onoff(state), onoff(cur_state));
1161 }
1162 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1163 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1164
1165 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         u32 val;
1169
1170         /* ILK FDI PLL is always enabled */
1171         if (IS_GEN5(dev_priv))
1172                 return;
1173
1174         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1175         if (HAS_DDI(dev_priv))
1176                 return;
1177
1178         val = I915_READ(FDI_TX_CTL(pipe));
1179         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1180 }
1181
1182 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1183                        enum pipe pipe, bool state)
1184 {
1185         u32 val;
1186         bool cur_state;
1187
1188         val = I915_READ(FDI_RX_CTL(pipe));
1189         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190         I915_STATE_WARN(cur_state != state,
1191              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192                         onoff(state), onoff(cur_state));
1193 }
1194
1195 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1196 {
1197         i915_reg_t pp_reg;
1198         u32 val;
1199         enum pipe panel_pipe = PIPE_A;
1200         bool locked = true;
1201
1202         if (WARN_ON(HAS_DDI(dev_priv)))
1203                 return;
1204
1205         if (HAS_PCH_SPLIT(dev_priv)) {
1206                 u32 port_sel;
1207
1208                 pp_reg = PP_CONTROL(0);
1209                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1210
1211                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1212                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1213                         panel_pipe = PIPE_B;
1214                 /* XXX: else fix for eDP */
1215         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1216                 /* presumably write lock depends on pipe, not port select */
1217                 pp_reg = PP_CONTROL(pipe);
1218                 panel_pipe = pipe;
1219         } else {
1220                 pp_reg = PP_CONTROL(0);
1221                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1222                         panel_pipe = PIPE_B;
1223         }
1224
1225         val = I915_READ(pp_reg);
1226         if (!(val & PANEL_POWER_ON) ||
1227             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1228                 locked = false;
1229
1230         I915_STATE_WARN(panel_pipe == pipe && locked,
1231              "panel assertion failure, pipe %c regs locked\n",
1232              pipe_name(pipe));
1233 }
1234
1235 static void assert_cursor(struct drm_i915_private *dev_priv,
1236                           enum pipe pipe, bool state)
1237 {
1238         bool cur_state;
1239
1240         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
1241                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1242         else
1243                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1244
1245         I915_STATE_WARN(cur_state != state,
1246              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1247                         pipe_name(pipe), onoff(state), onoff(cur_state));
1248 }
1249 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1250 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1251
1252 void assert_pipe(struct drm_i915_private *dev_priv,
1253                  enum pipe pipe, bool state)
1254 {
1255         bool cur_state;
1256         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1257                                                                       pipe);
1258         enum intel_display_power_domain power_domain;
1259
1260         /* if we need the pipe quirk it must be always on */
1261         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1262             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1263                 state = true;
1264
1265         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1266         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1267                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1268                 cur_state = !!(val & PIPECONF_ENABLE);
1269
1270                 intel_display_power_put(dev_priv, power_domain);
1271         } else {
1272                 cur_state = false;
1273         }
1274
1275         I915_STATE_WARN(cur_state != state,
1276              "pipe %c assertion failure (expected %s, current %s)\n",
1277                         pipe_name(pipe), onoff(state), onoff(cur_state));
1278 }
1279
1280 static void assert_plane(struct drm_i915_private *dev_priv,
1281                          enum plane plane, bool state)
1282 {
1283         u32 val;
1284         bool cur_state;
1285
1286         val = I915_READ(DSPCNTR(plane));
1287         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1288         I915_STATE_WARN(cur_state != state,
1289              "plane %c assertion failure (expected %s, current %s)\n",
1290                         plane_name(plane), onoff(state), onoff(cur_state));
1291 }
1292
1293 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1294 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1295
1296 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1297                                    enum pipe pipe)
1298 {
1299         struct drm_device *dev = &dev_priv->drm;
1300         int i;
1301
1302         /* Primary planes are fixed to pipes on gen4+ */
1303         if (INTEL_INFO(dev)->gen >= 4) {
1304                 u32 val = I915_READ(DSPCNTR(pipe));
1305                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1306                      "plane %c assertion failure, should be disabled but not\n",
1307                      plane_name(pipe));
1308                 return;
1309         }
1310
1311         /* Need to check both planes against the pipe */
1312         for_each_pipe(dev_priv, i) {
1313                 u32 val = I915_READ(DSPCNTR(i));
1314                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1315                         DISPPLANE_SEL_PIPE_SHIFT;
1316                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1317                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1318                      plane_name(i), pipe_name(pipe));
1319         }
1320 }
1321
1322 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1323                                     enum pipe pipe)
1324 {
1325         struct drm_device *dev = &dev_priv->drm;
1326         int sprite;
1327
1328         if (INTEL_INFO(dev)->gen >= 9) {
1329                 for_each_sprite(dev_priv, pipe, sprite) {
1330                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1331                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1332                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1333                              sprite, pipe_name(pipe));
1334                 }
1335         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1336                 for_each_sprite(dev_priv, pipe, sprite) {
1337                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1338                         I915_STATE_WARN(val & SP_ENABLE,
1339                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1340                              sprite_name(pipe, sprite), pipe_name(pipe));
1341                 }
1342         } else if (INTEL_INFO(dev)->gen >= 7) {
1343                 u32 val = I915_READ(SPRCTL(pipe));
1344                 I915_STATE_WARN(val & SPRITE_ENABLE,
1345                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1346                      plane_name(pipe), pipe_name(pipe));
1347         } else if (INTEL_INFO(dev)->gen >= 5) {
1348                 u32 val = I915_READ(DVSCNTR(pipe));
1349                 I915_STATE_WARN(val & DVS_ENABLE,
1350                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351                      plane_name(pipe), pipe_name(pipe));
1352         }
1353 }
1354
1355 static void assert_vblank_disabled(struct drm_crtc *crtc)
1356 {
1357         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1358                 drm_crtc_vblank_put(crtc);
1359 }
1360
1361 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1362                                     enum pipe pipe)
1363 {
1364         u32 val;
1365         bool enabled;
1366
1367         val = I915_READ(PCH_TRANSCONF(pipe));
1368         enabled = !!(val & TRANS_ENABLE);
1369         I915_STATE_WARN(enabled,
1370              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1371              pipe_name(pipe));
1372 }
1373
1374 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1375                             enum pipe pipe, u32 port_sel, u32 val)
1376 {
1377         if ((val & DP_PORT_EN) == 0)
1378                 return false;
1379
1380         if (HAS_PCH_CPT(dev_priv)) {
1381                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1382                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1383                         return false;
1384         } else if (IS_CHERRYVIEW(dev_priv)) {
1385                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1386                         return false;
1387         } else {
1388                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1389                         return false;
1390         }
1391         return true;
1392 }
1393
1394 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1395                               enum pipe pipe, u32 val)
1396 {
1397         if ((val & SDVO_ENABLE) == 0)
1398                 return false;
1399
1400         if (HAS_PCH_CPT(dev_priv)) {
1401                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1402                         return false;
1403         } else if (IS_CHERRYVIEW(dev_priv)) {
1404                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1405                         return false;
1406         } else {
1407                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1408                         return false;
1409         }
1410         return true;
1411 }
1412
1413 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1414                               enum pipe pipe, u32 val)
1415 {
1416         if ((val & LVDS_PORT_EN) == 0)
1417                 return false;
1418
1419         if (HAS_PCH_CPT(dev_priv)) {
1420                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1421                         return false;
1422         } else {
1423                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1424                         return false;
1425         }
1426         return true;
1427 }
1428
1429 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1430                               enum pipe pipe, u32 val)
1431 {
1432         if ((val & ADPA_DAC_ENABLE) == 0)
1433                 return false;
1434         if (HAS_PCH_CPT(dev_priv)) {
1435                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1436                         return false;
1437         } else {
1438                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1439                         return false;
1440         }
1441         return true;
1442 }
1443
1444 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1445                                    enum pipe pipe, i915_reg_t reg,
1446                                    u32 port_sel)
1447 {
1448         u32 val = I915_READ(reg);
1449         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1450              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1451              i915_mmio_reg_offset(reg), pipe_name(pipe));
1452
1453         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1454              && (val & DP_PIPEB_SELECT),
1455              "IBX PCH dp port still using transcoder B\n");
1456 }
1457
1458 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1459                                      enum pipe pipe, i915_reg_t reg)
1460 {
1461         u32 val = I915_READ(reg);
1462         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1463              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1464              i915_mmio_reg_offset(reg), pipe_name(pipe));
1465
1466         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1467              && (val & SDVO_PIPE_B_SELECT),
1468              "IBX PCH hdmi port still using transcoder B\n");
1469 }
1470
1471 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1472                                       enum pipe pipe)
1473 {
1474         u32 val;
1475
1476         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1477         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1478         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1479
1480         val = I915_READ(PCH_ADPA);
1481         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1482              "PCH VGA enabled on transcoder %c, should be disabled\n",
1483              pipe_name(pipe));
1484
1485         val = I915_READ(PCH_LVDS);
1486         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1487              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1488              pipe_name(pipe));
1489
1490         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1491         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1492         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1493 }
1494
1495 static void _vlv_enable_pll(struct intel_crtc *crtc,
1496                             const struct intel_crtc_state *pipe_config)
1497 {
1498         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1499         enum pipe pipe = crtc->pipe;
1500
1501         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1502         POSTING_READ(DPLL(pipe));
1503         udelay(150);
1504
1505         if (intel_wait_for_register(dev_priv,
1506                                     DPLL(pipe),
1507                                     DPLL_LOCK_VLV,
1508                                     DPLL_LOCK_VLV,
1509                                     1))
1510                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1511 }
1512
1513 static void vlv_enable_pll(struct intel_crtc *crtc,
1514                            const struct intel_crtc_state *pipe_config)
1515 {
1516         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1517         enum pipe pipe = crtc->pipe;
1518
1519         assert_pipe_disabled(dev_priv, pipe);
1520
1521         /* PLL is protected by panel, make sure we can write it */
1522         assert_panel_unlocked(dev_priv, pipe);
1523
1524         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1525                 _vlv_enable_pll(crtc, pipe_config);
1526
1527         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1528         POSTING_READ(DPLL_MD(pipe));
1529 }
1530
1531
1532 static void _chv_enable_pll(struct intel_crtc *crtc,
1533                             const struct intel_crtc_state *pipe_config)
1534 {
1535         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1536         enum pipe pipe = crtc->pipe;
1537         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1538         u32 tmp;
1539
1540         mutex_lock(&dev_priv->sb_lock);
1541
1542         /* Enable back the 10bit clock to display controller */
1543         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1544         tmp |= DPIO_DCLKP_EN;
1545         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1546
1547         mutex_unlock(&dev_priv->sb_lock);
1548
1549         /*
1550          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1551          */
1552         udelay(1);
1553
1554         /* Enable PLL */
1555         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1556
1557         /* Check PLL is locked */
1558         if (intel_wait_for_register(dev_priv,
1559                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1560                                     1))
1561                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1562 }
1563
1564 static void chv_enable_pll(struct intel_crtc *crtc,
1565                            const struct intel_crtc_state *pipe_config)
1566 {
1567         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1568         enum pipe pipe = crtc->pipe;
1569
1570         assert_pipe_disabled(dev_priv, pipe);
1571
1572         /* PLL is protected by panel, make sure we can write it */
1573         assert_panel_unlocked(dev_priv, pipe);
1574
1575         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1576                 _chv_enable_pll(crtc, pipe_config);
1577
1578         if (pipe != PIPE_A) {
1579                 /*
1580                  * WaPixelRepeatModeFixForC0:chv
1581                  *
1582                  * DPLLCMD is AWOL. Use chicken bits to propagate
1583                  * the value from DPLLBMD to either pipe B or C.
1584                  */
1585                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1586                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1587                 I915_WRITE(CBR4_VLV, 0);
1588                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1589
1590                 /*
1591                  * DPLLB VGA mode also seems to cause problems.
1592                  * We should always have it disabled.
1593                  */
1594                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1595         } else {
1596                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1597                 POSTING_READ(DPLL_MD(pipe));
1598         }
1599 }
1600
1601 static int intel_num_dvo_pipes(struct drm_device *dev)
1602 {
1603         struct intel_crtc *crtc;
1604         int count = 0;
1605
1606         for_each_intel_crtc(dev, crtc) {
1607                 count += crtc->base.state->active &&
1608                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1609         }
1610
1611         return count;
1612 }
1613
1614 static void i9xx_enable_pll(struct intel_crtc *crtc)
1615 {
1616         struct drm_device *dev = crtc->base.dev;
1617         struct drm_i915_private *dev_priv = to_i915(dev);
1618         i915_reg_t reg = DPLL(crtc->pipe);
1619         u32 dpll = crtc->config->dpll_hw_state.dpll;
1620
1621         assert_pipe_disabled(dev_priv, crtc->pipe);
1622
1623         /* PLL is protected by panel, make sure we can write it */
1624         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1625                 assert_panel_unlocked(dev_priv, crtc->pipe);
1626
1627         /* Enable DVO 2x clock on both PLLs if necessary */
1628         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev) > 0) {
1629                 /*
1630                  * It appears to be important that we don't enable this
1631                  * for the current pipe before otherwise configuring the
1632                  * PLL. No idea how this should be handled if multiple
1633                  * DVO outputs are enabled simultaneosly.
1634                  */
1635                 dpll |= DPLL_DVO_2X_MODE;
1636                 I915_WRITE(DPLL(!crtc->pipe),
1637                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1638         }
1639
1640         /*
1641          * Apparently we need to have VGA mode enabled prior to changing
1642          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1643          * dividers, even though the register value does change.
1644          */
1645         I915_WRITE(reg, 0);
1646
1647         I915_WRITE(reg, dpll);
1648
1649         /* Wait for the clocks to stabilize. */
1650         POSTING_READ(reg);
1651         udelay(150);
1652
1653         if (INTEL_INFO(dev)->gen >= 4) {
1654                 I915_WRITE(DPLL_MD(crtc->pipe),
1655                            crtc->config->dpll_hw_state.dpll_md);
1656         } else {
1657                 /* The pixel multiplier can only be updated once the
1658                  * DPLL is enabled and the clocks are stable.
1659                  *
1660                  * So write it again.
1661                  */
1662                 I915_WRITE(reg, dpll);
1663         }
1664
1665         /* We do this three times for luck */
1666         I915_WRITE(reg, dpll);
1667         POSTING_READ(reg);
1668         udelay(150); /* wait for warmup */
1669         I915_WRITE(reg, dpll);
1670         POSTING_READ(reg);
1671         udelay(150); /* wait for warmup */
1672         I915_WRITE(reg, dpll);
1673         POSTING_READ(reg);
1674         udelay(150); /* wait for warmup */
1675 }
1676
1677 /**
1678  * i9xx_disable_pll - disable a PLL
1679  * @dev_priv: i915 private structure
1680  * @pipe: pipe PLL to disable
1681  *
1682  * Disable the PLL for @pipe, making sure the pipe is off first.
1683  *
1684  * Note!  This is for pre-ILK only.
1685  */
1686 static void i9xx_disable_pll(struct intel_crtc *crtc)
1687 {
1688         struct drm_device *dev = crtc->base.dev;
1689         struct drm_i915_private *dev_priv = to_i915(dev);
1690         enum pipe pipe = crtc->pipe;
1691
1692         /* Disable DVO 2x clock on both PLLs if necessary */
1693         if (IS_I830(dev_priv) &&
1694             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1695             !intel_num_dvo_pipes(dev)) {
1696                 I915_WRITE(DPLL(PIPE_B),
1697                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1698                 I915_WRITE(DPLL(PIPE_A),
1699                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1700         }
1701
1702         /* Don't disable pipe or pipe PLLs if needed */
1703         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1704             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1705                 return;
1706
1707         /* Make sure the pipe isn't still relying on us */
1708         assert_pipe_disabled(dev_priv, pipe);
1709
1710         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1711         POSTING_READ(DPLL(pipe));
1712 }
1713
1714 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1715 {
1716         u32 val;
1717
1718         /* Make sure the pipe isn't still relying on us */
1719         assert_pipe_disabled(dev_priv, pipe);
1720
1721         val = DPLL_INTEGRATED_REF_CLK_VLV |
1722                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1723         if (pipe != PIPE_A)
1724                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1725
1726         I915_WRITE(DPLL(pipe), val);
1727         POSTING_READ(DPLL(pipe));
1728 }
1729
1730 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1731 {
1732         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1733         u32 val;
1734
1735         /* Make sure the pipe isn't still relying on us */
1736         assert_pipe_disabled(dev_priv, pipe);
1737
1738         val = DPLL_SSC_REF_CLK_CHV |
1739                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1740         if (pipe != PIPE_A)
1741                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1742
1743         I915_WRITE(DPLL(pipe), val);
1744         POSTING_READ(DPLL(pipe));
1745
1746         mutex_lock(&dev_priv->sb_lock);
1747
1748         /* Disable 10bit clock to display controller */
1749         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1750         val &= ~DPIO_DCLKP_EN;
1751         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1752
1753         mutex_unlock(&dev_priv->sb_lock);
1754 }
1755
1756 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1757                          struct intel_digital_port *dport,
1758                          unsigned int expected_mask)
1759 {
1760         u32 port_mask;
1761         i915_reg_t dpll_reg;
1762
1763         switch (dport->port) {
1764         case PORT_B:
1765                 port_mask = DPLL_PORTB_READY_MASK;
1766                 dpll_reg = DPLL(0);
1767                 break;
1768         case PORT_C:
1769                 port_mask = DPLL_PORTC_READY_MASK;
1770                 dpll_reg = DPLL(0);
1771                 expected_mask <<= 4;
1772                 break;
1773         case PORT_D:
1774                 port_mask = DPLL_PORTD_READY_MASK;
1775                 dpll_reg = DPIO_PHY_STATUS;
1776                 break;
1777         default:
1778                 BUG();
1779         }
1780
1781         if (intel_wait_for_register(dev_priv,
1782                                     dpll_reg, port_mask, expected_mask,
1783                                     1000))
1784                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1785                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1786 }
1787
1788 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1789                                            enum pipe pipe)
1790 {
1791         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1793         i915_reg_t reg;
1794         uint32_t val, pipeconf_val;
1795
1796         /* Make sure PCH DPLL is enabled */
1797         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1798
1799         /* FDI must be feeding us bits for PCH ports */
1800         assert_fdi_tx_enabled(dev_priv, pipe);
1801         assert_fdi_rx_enabled(dev_priv, pipe);
1802
1803         if (HAS_PCH_CPT(dev_priv)) {
1804                 /* Workaround: Set the timing override bit before enabling the
1805                  * pch transcoder. */
1806                 reg = TRANS_CHICKEN2(pipe);
1807                 val = I915_READ(reg);
1808                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1809                 I915_WRITE(reg, val);
1810         }
1811
1812         reg = PCH_TRANSCONF(pipe);
1813         val = I915_READ(reg);
1814         pipeconf_val = I915_READ(PIPECONF(pipe));
1815
1816         if (HAS_PCH_IBX(dev_priv)) {
1817                 /*
1818                  * Make the BPC in transcoder be consistent with
1819                  * that in pipeconf reg. For HDMI we must use 8bpc
1820                  * here for both 8bpc and 12bpc.
1821                  */
1822                 val &= ~PIPECONF_BPC_MASK;
1823                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1824                         val |= PIPECONF_8BPC;
1825                 else
1826                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1827         }
1828
1829         val &= ~TRANS_INTERLACE_MASK;
1830         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1831                 if (HAS_PCH_IBX(dev_priv) &&
1832                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1833                         val |= TRANS_LEGACY_INTERLACED_ILK;
1834                 else
1835                         val |= TRANS_INTERLACED;
1836         else
1837                 val |= TRANS_PROGRESSIVE;
1838
1839         I915_WRITE(reg, val | TRANS_ENABLE);
1840         if (intel_wait_for_register(dev_priv,
1841                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1842                                     100))
1843                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1844 }
1845
1846 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1847                                       enum transcoder cpu_transcoder)
1848 {
1849         u32 val, pipeconf_val;
1850
1851         /* FDI must be feeding us bits for PCH ports */
1852         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1853         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1854
1855         /* Workaround: set timing override bit. */
1856         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1857         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1858         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1859
1860         val = TRANS_ENABLE;
1861         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1862
1863         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1864             PIPECONF_INTERLACED_ILK)
1865                 val |= TRANS_INTERLACED;
1866         else
1867                 val |= TRANS_PROGRESSIVE;
1868
1869         I915_WRITE(LPT_TRANSCONF, val);
1870         if (intel_wait_for_register(dev_priv,
1871                                     LPT_TRANSCONF,
1872                                     TRANS_STATE_ENABLE,
1873                                     TRANS_STATE_ENABLE,
1874                                     100))
1875                 DRM_ERROR("Failed to enable PCH transcoder\n");
1876 }
1877
1878 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1879                                             enum pipe pipe)
1880 {
1881         i915_reg_t reg;
1882         uint32_t val;
1883
1884         /* FDI relies on the transcoder */
1885         assert_fdi_tx_disabled(dev_priv, pipe);
1886         assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888         /* Ports must be off as well */
1889         assert_pch_ports_disabled(dev_priv, pipe);
1890
1891         reg = PCH_TRANSCONF(pipe);
1892         val = I915_READ(reg);
1893         val &= ~TRANS_ENABLE;
1894         I915_WRITE(reg, val);
1895         /* wait for PCH transcoder off, transcoder state */
1896         if (intel_wait_for_register(dev_priv,
1897                                     reg, TRANS_STATE_ENABLE, 0,
1898                                     50))
1899                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901         if (HAS_PCH_CPT(dev_priv)) {
1902                 /* Workaround: Clear the timing override chicken bit again. */
1903                 reg = TRANS_CHICKEN2(pipe);
1904                 val = I915_READ(reg);
1905                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906                 I915_WRITE(reg, val);
1907         }
1908 }
1909
1910 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912         u32 val;
1913
1914         val = I915_READ(LPT_TRANSCONF);
1915         val &= ~TRANS_ENABLE;
1916         I915_WRITE(LPT_TRANSCONF, val);
1917         /* wait for PCH transcoder off, transcoder state */
1918         if (intel_wait_for_register(dev_priv,
1919                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920                                     50))
1921                 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923         /* Workaround: clear timing override bit. */
1924         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1930 {
1931         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1932
1933         WARN_ON(!crtc->config->has_pch_encoder);
1934
1935         if (HAS_PCH_LPT(dev_priv))
1936                 return TRANSCODER_A;
1937         else
1938                 return (enum transcoder) crtc->pipe;
1939 }
1940
1941 /**
1942  * intel_enable_pipe - enable a pipe, asserting requirements
1943  * @crtc: crtc responsible for the pipe
1944  *
1945  * Enable @crtc's pipe, making sure that various hardware specific requirements
1946  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1947  */
1948 static void intel_enable_pipe(struct intel_crtc *crtc)
1949 {
1950         struct drm_device *dev = crtc->base.dev;
1951         struct drm_i915_private *dev_priv = to_i915(dev);
1952         enum pipe pipe = crtc->pipe;
1953         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1954         i915_reg_t reg;
1955         u32 val;
1956
1957         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1958
1959         assert_planes_disabled(dev_priv, pipe);
1960         assert_cursor_disabled(dev_priv, pipe);
1961         assert_sprites_disabled(dev_priv, pipe);
1962
1963         /*
1964          * A pipe without a PLL won't actually be able to drive bits from
1965          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1966          * need the check.
1967          */
1968         if (HAS_GMCH_DISPLAY(dev_priv)) {
1969                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1970                         assert_dsi_pll_enabled(dev_priv);
1971                 else
1972                         assert_pll_enabled(dev_priv, pipe);
1973         } else {
1974                 if (crtc->config->has_pch_encoder) {
1975                         /* if driving the PCH, we need FDI enabled */
1976                         assert_fdi_rx_pll_enabled(dev_priv,
1977                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1978                         assert_fdi_tx_pll_enabled(dev_priv,
1979                                                   (enum pipe) cpu_transcoder);
1980                 }
1981                 /* FIXME: assert CPU port conditions for SNB+ */
1982         }
1983
1984         reg = PIPECONF(cpu_transcoder);
1985         val = I915_READ(reg);
1986         if (val & PIPECONF_ENABLE) {
1987                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1988                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1989                 return;
1990         }
1991
1992         I915_WRITE(reg, val | PIPECONF_ENABLE);
1993         POSTING_READ(reg);
1994
1995         /*
1996          * Until the pipe starts DSL will read as 0, which would cause
1997          * an apparent vblank timestamp jump, which messes up also the
1998          * frame count when it's derived from the timestamps. So let's
1999          * wait for the pipe to start properly before we call
2000          * drm_crtc_vblank_on()
2001          */
2002         if (dev->max_vblank_count == 0 &&
2003             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2004                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2005 }
2006
2007 /**
2008  * intel_disable_pipe - disable a pipe, asserting requirements
2009  * @crtc: crtc whose pipes is to be disabled
2010  *
2011  * Disable the pipe of @crtc, making sure that various hardware
2012  * specific requirements are met, if applicable, e.g. plane
2013  * disabled, panel fitter off, etc.
2014  *
2015  * Will wait until the pipe has shut down before returning.
2016  */
2017 static void intel_disable_pipe(struct intel_crtc *crtc)
2018 {
2019         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2020         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2021         enum pipe pipe = crtc->pipe;
2022         i915_reg_t reg;
2023         u32 val;
2024
2025         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2026
2027         /*
2028          * Make sure planes won't keep trying to pump pixels to us,
2029          * or we might hang the display.
2030          */
2031         assert_planes_disabled(dev_priv, pipe);
2032         assert_cursor_disabled(dev_priv, pipe);
2033         assert_sprites_disabled(dev_priv, pipe);
2034
2035         reg = PIPECONF(cpu_transcoder);
2036         val = I915_READ(reg);
2037         if ((val & PIPECONF_ENABLE) == 0)
2038                 return;
2039
2040         /*
2041          * Double wide has implications for planes
2042          * so best keep it disabled when not needed.
2043          */
2044         if (crtc->config->double_wide)
2045                 val &= ~PIPECONF_DOUBLE_WIDE;
2046
2047         /* Don't disable pipe or pipe PLLs if needed */
2048         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2049             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2050                 val &= ~PIPECONF_ENABLE;
2051
2052         I915_WRITE(reg, val);
2053         if ((val & PIPECONF_ENABLE) == 0)
2054                 intel_wait_for_pipe_off(crtc);
2055 }
2056
2057 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2058 {
2059         return IS_GEN2(dev_priv) ? 2048 : 4096;
2060 }
2061
2062 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2063                                            uint64_t fb_modifier, unsigned int cpp)
2064 {
2065         switch (fb_modifier) {
2066         case DRM_FORMAT_MOD_NONE:
2067                 return cpp;
2068         case I915_FORMAT_MOD_X_TILED:
2069                 if (IS_GEN2(dev_priv))
2070                         return 128;
2071                 else
2072                         return 512;
2073         case I915_FORMAT_MOD_Y_TILED:
2074                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2075                         return 128;
2076                 else
2077                         return 512;
2078         case I915_FORMAT_MOD_Yf_TILED:
2079                 switch (cpp) {
2080                 case 1:
2081                         return 64;
2082                 case 2:
2083                 case 4:
2084                         return 128;
2085                 case 8:
2086                 case 16:
2087                         return 256;
2088                 default:
2089                         MISSING_CASE(cpp);
2090                         return cpp;
2091                 }
2092                 break;
2093         default:
2094                 MISSING_CASE(fb_modifier);
2095                 return cpp;
2096         }
2097 }
2098
2099 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2100                                uint64_t fb_modifier, unsigned int cpp)
2101 {
2102         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2103                 return 1;
2104         else
2105                 return intel_tile_size(dev_priv) /
2106                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2107 }
2108
2109 /* Return the tile dimensions in pixel units */
2110 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2111                             unsigned int *tile_width,
2112                             unsigned int *tile_height,
2113                             uint64_t fb_modifier,
2114                             unsigned int cpp)
2115 {
2116         unsigned int tile_width_bytes =
2117                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2118
2119         *tile_width = tile_width_bytes / cpp;
2120         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2121 }
2122
2123 unsigned int
2124 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2125                       uint32_t pixel_format, uint64_t fb_modifier)
2126 {
2127         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2128         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2129
2130         return ALIGN(height, tile_height);
2131 }
2132
2133 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2134 {
2135         unsigned int size = 0;
2136         int i;
2137
2138         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2139                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2140
2141         return size;
2142 }
2143
2144 static void
2145 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2146                         const struct drm_framebuffer *fb,
2147                         unsigned int rotation)
2148 {
2149         if (drm_rotation_90_or_270(rotation)) {
2150                 *view = i915_ggtt_view_rotated;
2151                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2152         } else {
2153                 *view = i915_ggtt_view_normal;
2154         }
2155 }
2156
2157 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2158 {
2159         if (INTEL_INFO(dev_priv)->gen >= 9)
2160                 return 256 * 1024;
2161         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2162                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2163                 return 128 * 1024;
2164         else if (INTEL_INFO(dev_priv)->gen >= 4)
2165                 return 4 * 1024;
2166         else
2167                 return 0;
2168 }
2169
2170 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2171                                          uint64_t fb_modifier)
2172 {
2173         switch (fb_modifier) {
2174         case DRM_FORMAT_MOD_NONE:
2175                 return intel_linear_alignment(dev_priv);
2176         case I915_FORMAT_MOD_X_TILED:
2177                 if (INTEL_INFO(dev_priv)->gen >= 9)
2178                         return 256 * 1024;
2179                 return 0;
2180         case I915_FORMAT_MOD_Y_TILED:
2181         case I915_FORMAT_MOD_Yf_TILED:
2182                 return 1 * 1024 * 1024;
2183         default:
2184                 MISSING_CASE(fb_modifier);
2185                 return 0;
2186         }
2187 }
2188
2189 struct i915_vma *
2190 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2191 {
2192         struct drm_device *dev = fb->dev;
2193         struct drm_i915_private *dev_priv = to_i915(dev);
2194         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2195         struct i915_ggtt_view view;
2196         struct i915_vma *vma;
2197         u32 alignment;
2198
2199         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2200
2201         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2202
2203         intel_fill_fb_ggtt_view(&view, fb, rotation);
2204
2205         /* Note that the w/a also requires 64 PTE of padding following the
2206          * bo. We currently fill all unused PTE with the shadow page and so
2207          * we should always have valid PTE following the scanout preventing
2208          * the VT-d warning.
2209          */
2210         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2211                 alignment = 256 * 1024;
2212
2213         /*
2214          * Global gtt pte registers are special registers which actually forward
2215          * writes to a chunk of system memory. Which means that there is no risk
2216          * that the register values disappear as soon as we call
2217          * intel_runtime_pm_put(), so it is correct to wrap only the
2218          * pin/unpin/fence and not more.
2219          */
2220         intel_runtime_pm_get(dev_priv);
2221
2222         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2223         if (IS_ERR(vma))
2224                 goto err;
2225
2226         if (i915_vma_is_map_and_fenceable(vma)) {
2227                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2228                  * fence, whereas 965+ only requires a fence if using
2229                  * framebuffer compression.  For simplicity, we always, when
2230                  * possible, install a fence as the cost is not that onerous.
2231                  *
2232                  * If we fail to fence the tiled scanout, then either the
2233                  * modeset will reject the change (which is highly unlikely as
2234                  * the affected systems, all but one, do not have unmappable
2235                  * space) or we will not be able to enable full powersaving
2236                  * techniques (also likely not to apply due to various limits
2237                  * FBC and the like impose on the size of the buffer, which
2238                  * presumably we violated anyway with this unmappable buffer).
2239                  * Anyway, it is presumably better to stumble onwards with
2240                  * something and try to run the system in a "less than optimal"
2241                  * mode that matches the user configuration.
2242                  */
2243                 if (i915_vma_get_fence(vma) == 0)
2244                         i915_vma_pin_fence(vma);
2245         }
2246
2247 err:
2248         intel_runtime_pm_put(dev_priv);
2249         return vma;
2250 }
2251
2252 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2253 {
2254         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2255         struct i915_ggtt_view view;
2256         struct i915_vma *vma;
2257
2258         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2259
2260         intel_fill_fb_ggtt_view(&view, fb, rotation);
2261         vma = i915_gem_object_to_ggtt(obj, &view);
2262
2263         i915_vma_unpin_fence(vma);
2264         i915_gem_object_unpin_from_display_plane(vma);
2265 }
2266
2267 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2268                           unsigned int rotation)
2269 {
2270         if (drm_rotation_90_or_270(rotation))
2271                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2272         else
2273                 return fb->pitches[plane];
2274 }
2275
2276 /*
2277  * Convert the x/y offsets into a linear offset.
2278  * Only valid with 0/180 degree rotation, which is fine since linear
2279  * offset is only used with linear buffers on pre-hsw and tiled buffers
2280  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2281  */
2282 u32 intel_fb_xy_to_linear(int x, int y,
2283                           const struct intel_plane_state *state,
2284                           int plane)
2285 {
2286         const struct drm_framebuffer *fb = state->base.fb;
2287         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2288         unsigned int pitch = fb->pitches[plane];
2289
2290         return y * pitch + x * cpp;
2291 }
2292
2293 /*
2294  * Add the x/y offsets derived from fb->offsets[] to the user
2295  * specified plane src x/y offsets. The resulting x/y offsets
2296  * specify the start of scanout from the beginning of the gtt mapping.
2297  */
2298 void intel_add_fb_offsets(int *x, int *y,
2299                           const struct intel_plane_state *state,
2300                           int plane)
2301
2302 {
2303         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2304         unsigned int rotation = state->base.rotation;
2305
2306         if (drm_rotation_90_or_270(rotation)) {
2307                 *x += intel_fb->rotated[plane].x;
2308                 *y += intel_fb->rotated[plane].y;
2309         } else {
2310                 *x += intel_fb->normal[plane].x;
2311                 *y += intel_fb->normal[plane].y;
2312         }
2313 }
2314
2315 /*
2316  * Input tile dimensions and pitch must already be
2317  * rotated to match x and y, and in pixel units.
2318  */
2319 static u32 _intel_adjust_tile_offset(int *x, int *y,
2320                                      unsigned int tile_width,
2321                                      unsigned int tile_height,
2322                                      unsigned int tile_size,
2323                                      unsigned int pitch_tiles,
2324                                      u32 old_offset,
2325                                      u32 new_offset)
2326 {
2327         unsigned int pitch_pixels = pitch_tiles * tile_width;
2328         unsigned int tiles;
2329
2330         WARN_ON(old_offset & (tile_size - 1));
2331         WARN_ON(new_offset & (tile_size - 1));
2332         WARN_ON(new_offset > old_offset);
2333
2334         tiles = (old_offset - new_offset) / tile_size;
2335
2336         *y += tiles / pitch_tiles * tile_height;
2337         *x += tiles % pitch_tiles * tile_width;
2338
2339         /* minimize x in case it got needlessly big */
2340         *y += *x / pitch_pixels * tile_height;
2341         *x %= pitch_pixels;
2342
2343         return new_offset;
2344 }
2345
2346 /*
2347  * Adjust the tile offset by moving the difference into
2348  * the x/y offsets.
2349  */
2350 static u32 intel_adjust_tile_offset(int *x, int *y,
2351                                     const struct intel_plane_state *state, int plane,
2352                                     u32 old_offset, u32 new_offset)
2353 {
2354         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2355         const struct drm_framebuffer *fb = state->base.fb;
2356         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2357         unsigned int rotation = state->base.rotation;
2358         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2359
2360         WARN_ON(new_offset > old_offset);
2361
2362         if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2363                 unsigned int tile_size, tile_width, tile_height;
2364                 unsigned int pitch_tiles;
2365
2366                 tile_size = intel_tile_size(dev_priv);
2367                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2368                                 fb->modifier[plane], cpp);
2369
2370                 if (drm_rotation_90_or_270(rotation)) {
2371                         pitch_tiles = pitch / tile_height;
2372                         swap(tile_width, tile_height);
2373                 } else {
2374                         pitch_tiles = pitch / (tile_width * cpp);
2375                 }
2376
2377                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2378                                           tile_size, pitch_tiles,
2379                                           old_offset, new_offset);
2380         } else {
2381                 old_offset += *y * pitch + *x * cpp;
2382
2383                 *y = (old_offset - new_offset) / pitch;
2384                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2385         }
2386
2387         return new_offset;
2388 }
2389
2390 /*
2391  * Computes the linear offset to the base tile and adjusts
2392  * x, y. bytes per pixel is assumed to be a power-of-two.
2393  *
2394  * In the 90/270 rotated case, x and y are assumed
2395  * to be already rotated to match the rotated GTT view, and
2396  * pitch is the tile_height aligned framebuffer height.
2397  *
2398  * This function is used when computing the derived information
2399  * under intel_framebuffer, so using any of that information
2400  * here is not allowed. Anything under drm_framebuffer can be
2401  * used. This is why the user has to pass in the pitch since it
2402  * is specified in the rotated orientation.
2403  */
2404 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2405                                       int *x, int *y,
2406                                       const struct drm_framebuffer *fb, int plane,
2407                                       unsigned int pitch,
2408                                       unsigned int rotation,
2409                                       u32 alignment)
2410 {
2411         uint64_t fb_modifier = fb->modifier[plane];
2412         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2413         u32 offset, offset_aligned;
2414
2415         if (alignment)
2416                 alignment--;
2417
2418         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2419                 unsigned int tile_size, tile_width, tile_height;
2420                 unsigned int tile_rows, tiles, pitch_tiles;
2421
2422                 tile_size = intel_tile_size(dev_priv);
2423                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2424                                 fb_modifier, cpp);
2425
2426                 if (drm_rotation_90_or_270(rotation)) {
2427                         pitch_tiles = pitch / tile_height;
2428                         swap(tile_width, tile_height);
2429                 } else {
2430                         pitch_tiles = pitch / (tile_width * cpp);
2431                 }
2432
2433                 tile_rows = *y / tile_height;
2434                 *y %= tile_height;
2435
2436                 tiles = *x / tile_width;
2437                 *x %= tile_width;
2438
2439                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2440                 offset_aligned = offset & ~alignment;
2441
2442                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2443                                           tile_size, pitch_tiles,
2444                                           offset, offset_aligned);
2445         } else {
2446                 offset = *y * pitch + *x * cpp;
2447                 offset_aligned = offset & ~alignment;
2448
2449                 *y = (offset & alignment) / pitch;
2450                 *x = ((offset & alignment) - *y * pitch) / cpp;
2451         }
2452
2453         return offset_aligned;
2454 }
2455
2456 u32 intel_compute_tile_offset(int *x, int *y,
2457                               const struct intel_plane_state *state,
2458                               int plane)
2459 {
2460         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2461         const struct drm_framebuffer *fb = state->base.fb;
2462         unsigned int rotation = state->base.rotation;
2463         int pitch = intel_fb_pitch(fb, plane, rotation);
2464         u32 alignment;
2465
2466         /* AUX_DIST needs only 4K alignment */
2467         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2468                 alignment = 4096;
2469         else
2470                 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2471
2472         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2473                                           rotation, alignment);
2474 }
2475
2476 /* Convert the fb->offset[] linear offset into x/y offsets */
2477 static void intel_fb_offset_to_xy(int *x, int *y,
2478                                   const struct drm_framebuffer *fb, int plane)
2479 {
2480         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2481         unsigned int pitch = fb->pitches[plane];
2482         u32 linear_offset = fb->offsets[plane];
2483
2484         *y = linear_offset / pitch;
2485         *x = linear_offset % pitch / cpp;
2486 }
2487
2488 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2489 {
2490         switch (fb_modifier) {
2491         case I915_FORMAT_MOD_X_TILED:
2492                 return I915_TILING_X;
2493         case I915_FORMAT_MOD_Y_TILED:
2494                 return I915_TILING_Y;
2495         default:
2496                 return I915_TILING_NONE;
2497         }
2498 }
2499
2500 static int
2501 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2502                    struct drm_framebuffer *fb)
2503 {
2504         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2505         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2506         u32 gtt_offset_rotated = 0;
2507         unsigned int max_size = 0;
2508         uint32_t format = fb->pixel_format;
2509         int i, num_planes = drm_format_num_planes(format);
2510         unsigned int tile_size = intel_tile_size(dev_priv);
2511
2512         for (i = 0; i < num_planes; i++) {
2513                 unsigned int width, height;
2514                 unsigned int cpp, size;
2515                 u32 offset;
2516                 int x, y;
2517
2518                 cpp = drm_format_plane_cpp(format, i);
2519                 width = drm_format_plane_width(fb->width, format, i);
2520                 height = drm_format_plane_height(fb->height, format, i);
2521
2522                 intel_fb_offset_to_xy(&x, &y, fb, i);
2523
2524                 /*
2525                  * The fence (if used) is aligned to the start of the object
2526                  * so having the framebuffer wrap around across the edge of the
2527                  * fenced region doesn't really work. We have no API to configure
2528                  * the fence start offset within the object (nor could we probably
2529                  * on gen2/3). So it's just easier if we just require that the
2530                  * fb layout agrees with the fence layout. We already check that the
2531                  * fb stride matches the fence stride elsewhere.
2532                  */
2533                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2534                     (x + width) * cpp > fb->pitches[i]) {
2535                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2536                                   i, fb->offsets[i]);
2537                         return -EINVAL;
2538                 }
2539
2540                 /*
2541                  * First pixel of the framebuffer from
2542                  * the start of the normal gtt mapping.
2543                  */
2544                 intel_fb->normal[i].x = x;
2545                 intel_fb->normal[i].y = y;
2546
2547                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2548                                                     fb, 0, fb->pitches[i],
2549                                                     DRM_ROTATE_0, tile_size);
2550                 offset /= tile_size;
2551
2552                 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2553                         unsigned int tile_width, tile_height;
2554                         unsigned int pitch_tiles;
2555                         struct drm_rect r;
2556
2557                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2558                                         fb->modifier[i], cpp);
2559
2560                         rot_info->plane[i].offset = offset;
2561                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2562                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2563                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2564
2565                         intel_fb->rotated[i].pitch =
2566                                 rot_info->plane[i].height * tile_height;
2567
2568                         /* how many tiles does this plane need */
2569                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2570                         /*
2571                          * If the plane isn't horizontally tile aligned,
2572                          * we need one more tile.
2573                          */
2574                         if (x != 0)
2575                                 size++;
2576
2577                         /* rotate the x/y offsets to match the GTT view */
2578                         r.x1 = x;
2579                         r.y1 = y;
2580                         r.x2 = x + width;
2581                         r.y2 = y + height;
2582                         drm_rect_rotate(&r,
2583                                         rot_info->plane[i].width * tile_width,
2584                                         rot_info->plane[i].height * tile_height,
2585                                         DRM_ROTATE_270);
2586                         x = r.x1;
2587                         y = r.y1;
2588
2589                         /* rotate the tile dimensions to match the GTT view */
2590                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2591                         swap(tile_width, tile_height);
2592
2593                         /*
2594                          * We only keep the x/y offsets, so push all of the
2595                          * gtt offset into the x/y offsets.
2596                          */
2597                         _intel_adjust_tile_offset(&x, &y, tile_size,
2598                                                   tile_width, tile_height, pitch_tiles,
2599                                                   gtt_offset_rotated * tile_size, 0);
2600
2601                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2602
2603                         /*
2604                          * First pixel of the framebuffer from
2605                          * the start of the rotated gtt mapping.
2606                          */
2607                         intel_fb->rotated[i].x = x;
2608                         intel_fb->rotated[i].y = y;
2609                 } else {
2610                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2611                                             x * cpp, tile_size);
2612                 }
2613
2614                 /* how many tiles in total needed in the bo */
2615                 max_size = max(max_size, offset + size);
2616         }
2617
2618         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2619                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2620                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2621                 return -EINVAL;
2622         }
2623
2624         return 0;
2625 }
2626
2627 static int i9xx_format_to_fourcc(int format)
2628 {
2629         switch (format) {
2630         case DISPPLANE_8BPP:
2631                 return DRM_FORMAT_C8;
2632         case DISPPLANE_BGRX555:
2633                 return DRM_FORMAT_XRGB1555;
2634         case DISPPLANE_BGRX565:
2635                 return DRM_FORMAT_RGB565;
2636         default:
2637         case DISPPLANE_BGRX888:
2638                 return DRM_FORMAT_XRGB8888;
2639         case DISPPLANE_RGBX888:
2640                 return DRM_FORMAT_XBGR8888;
2641         case DISPPLANE_BGRX101010:
2642                 return DRM_FORMAT_XRGB2101010;
2643         case DISPPLANE_RGBX101010:
2644                 return DRM_FORMAT_XBGR2101010;
2645         }
2646 }
2647
2648 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2649 {
2650         switch (format) {
2651         case PLANE_CTL_FORMAT_RGB_565:
2652                 return DRM_FORMAT_RGB565;
2653         default:
2654         case PLANE_CTL_FORMAT_XRGB_8888:
2655                 if (rgb_order) {
2656                         if (alpha)
2657                                 return DRM_FORMAT_ABGR8888;
2658                         else
2659                                 return DRM_FORMAT_XBGR8888;
2660                 } else {
2661                         if (alpha)
2662                                 return DRM_FORMAT_ARGB8888;
2663                         else
2664                                 return DRM_FORMAT_XRGB8888;
2665                 }
2666         case PLANE_CTL_FORMAT_XRGB_2101010:
2667                 if (rgb_order)
2668                         return DRM_FORMAT_XBGR2101010;
2669                 else
2670                         return DRM_FORMAT_XRGB2101010;
2671         }
2672 }
2673
2674 static bool
2675 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2676                               struct intel_initial_plane_config *plane_config)
2677 {
2678         struct drm_device *dev = crtc->base.dev;
2679         struct drm_i915_private *dev_priv = to_i915(dev);
2680         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2681         struct drm_i915_gem_object *obj = NULL;
2682         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2683         struct drm_framebuffer *fb = &plane_config->fb->base;
2684         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2685         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2686                                     PAGE_SIZE);
2687
2688         size_aligned -= base_aligned;
2689
2690         if (plane_config->size == 0)
2691                 return false;
2692
2693         /* If the FB is too big, just don't use it since fbdev is not very
2694          * important and we should probably use that space with FBC or other
2695          * features. */
2696         if (size_aligned * 2 > ggtt->stolen_usable_size)
2697                 return false;
2698
2699         mutex_lock(&dev->struct_mutex);
2700
2701         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2702                                                              base_aligned,
2703                                                              base_aligned,
2704                                                              size_aligned);
2705         if (!obj) {
2706                 mutex_unlock(&dev->struct_mutex);
2707                 return false;
2708         }
2709
2710         if (plane_config->tiling == I915_TILING_X)
2711                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2712
2713         mode_cmd.pixel_format = fb->pixel_format;
2714         mode_cmd.width = fb->width;
2715         mode_cmd.height = fb->height;
2716         mode_cmd.pitches[0] = fb->pitches[0];
2717         mode_cmd.modifier[0] = fb->modifier[0];
2718         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2719
2720         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2721                                    &mode_cmd, obj)) {
2722                 DRM_DEBUG_KMS("intel fb init failed\n");
2723                 goto out_unref_obj;
2724         }
2725
2726         mutex_unlock(&dev->struct_mutex);
2727
2728         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2729         return true;
2730
2731 out_unref_obj:
2732         i915_gem_object_put(obj);
2733         mutex_unlock(&dev->struct_mutex);
2734         return false;
2735 }
2736
2737 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2738 static void
2739 update_state_fb(struct drm_plane *plane)
2740 {
2741         if (plane->fb == plane->state->fb)
2742                 return;
2743
2744         if (plane->state->fb)
2745                 drm_framebuffer_unreference(plane->state->fb);
2746         plane->state->fb = plane->fb;
2747         if (plane->state->fb)
2748                 drm_framebuffer_reference(plane->state->fb);
2749 }
2750
2751 static void
2752 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2753                              struct intel_initial_plane_config *plane_config)
2754 {
2755         struct drm_device *dev = intel_crtc->base.dev;
2756         struct drm_i915_private *dev_priv = to_i915(dev);
2757         struct drm_crtc *c;
2758         struct intel_crtc *i;
2759         struct drm_i915_gem_object *obj;
2760         struct drm_plane *primary = intel_crtc->base.primary;
2761         struct drm_plane_state *plane_state = primary->state;
2762         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2763         struct intel_plane *intel_plane = to_intel_plane(primary);
2764         struct intel_plane_state *intel_state =
2765                 to_intel_plane_state(plane_state);
2766         struct drm_framebuffer *fb;
2767
2768         if (!plane_config->fb)
2769                 return;
2770
2771         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2772                 fb = &plane_config->fb->base;
2773                 goto valid_fb;
2774         }
2775
2776         kfree(plane_config->fb);
2777
2778         /*
2779          * Failed to alloc the obj, check to see if we should share
2780          * an fb with another CRTC instead
2781          */
2782         for_each_crtc(dev, c) {
2783                 i = to_intel_crtc(c);
2784
2785                 if (c == &intel_crtc->base)
2786                         continue;
2787
2788                 if (!i->active)
2789                         continue;
2790
2791                 fb = c->primary->fb;
2792                 if (!fb)
2793                         continue;
2794
2795                 obj = intel_fb_obj(fb);
2796                 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2797                         drm_framebuffer_reference(fb);
2798                         goto valid_fb;
2799                 }
2800         }
2801
2802         /*
2803          * We've failed to reconstruct the BIOS FB.  Current display state
2804          * indicates that the primary plane is visible, but has a NULL FB,
2805          * which will lead to problems later if we don't fix it up.  The
2806          * simplest solution is to just disable the primary plane now and
2807          * pretend the BIOS never had it enabled.
2808          */
2809         to_intel_plane_state(plane_state)->base.visible = false;
2810         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2811         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2812         intel_plane->disable_plane(primary, &intel_crtc->base);
2813
2814         return;
2815
2816 valid_fb:
2817         plane_state->src_x = 0;
2818         plane_state->src_y = 0;
2819         plane_state->src_w = fb->width << 16;
2820         plane_state->src_h = fb->height << 16;
2821
2822         plane_state->crtc_x = 0;
2823         plane_state->crtc_y = 0;
2824         plane_state->crtc_w = fb->width;
2825         plane_state->crtc_h = fb->height;
2826
2827         intel_state->base.src.x1 = plane_state->src_x;
2828         intel_state->base.src.y1 = plane_state->src_y;
2829         intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2830         intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2831         intel_state->base.dst.x1 = plane_state->crtc_x;
2832         intel_state->base.dst.y1 = plane_state->crtc_y;
2833         intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2834         intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2835
2836         obj = intel_fb_obj(fb);
2837         if (i915_gem_object_is_tiled(obj))
2838                 dev_priv->preserve_bios_swizzle = true;
2839
2840         drm_framebuffer_reference(fb);
2841         primary->fb = primary->state->fb = fb;
2842         primary->crtc = primary->state->crtc = &intel_crtc->base;
2843         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2844         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2845                   &obj->frontbuffer_bits);
2846 }
2847
2848 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2849                                unsigned int rotation)
2850 {
2851         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2852
2853         switch (fb->modifier[plane]) {
2854         case DRM_FORMAT_MOD_NONE:
2855         case I915_FORMAT_MOD_X_TILED:
2856                 switch (cpp) {
2857                 case 8:
2858                         return 4096;
2859                 case 4:
2860                 case 2:
2861                 case 1:
2862                         return 8192;
2863                 default:
2864                         MISSING_CASE(cpp);
2865                         break;
2866                 }
2867                 break;
2868         case I915_FORMAT_MOD_Y_TILED:
2869         case I915_FORMAT_MOD_Yf_TILED:
2870                 switch (cpp) {
2871                 case 8:
2872                         return 2048;
2873                 case 4:
2874                         return 4096;
2875                 case 2:
2876                 case 1:
2877                         return 8192;
2878                 default:
2879                         MISSING_CASE(cpp);
2880                         break;
2881                 }
2882                 break;
2883         default:
2884                 MISSING_CASE(fb->modifier[plane]);
2885         }
2886
2887         return 2048;
2888 }
2889
2890 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2891 {
2892         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2893         const struct drm_framebuffer *fb = plane_state->base.fb;
2894         unsigned int rotation = plane_state->base.rotation;
2895         int x = plane_state->base.src.x1 >> 16;
2896         int y = plane_state->base.src.y1 >> 16;
2897         int w = drm_rect_width(&plane_state->base.src) >> 16;
2898         int h = drm_rect_height(&plane_state->base.src) >> 16;
2899         int max_width = skl_max_plane_width(fb, 0, rotation);
2900         int max_height = 4096;
2901         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2902
2903         if (w > max_width || h > max_height) {
2904                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2905                               w, h, max_width, max_height);
2906                 return -EINVAL;
2907         }
2908
2909         intel_add_fb_offsets(&x, &y, plane_state, 0);
2910         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2911
2912         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2913
2914         /*
2915          * AUX surface offset is specified as the distance from the
2916          * main surface offset, and it must be non-negative. Make
2917          * sure that is what we will get.
2918          */
2919         if (offset > aux_offset)
2920                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2921                                                   offset, aux_offset & ~(alignment - 1));
2922
2923         /*
2924          * When using an X-tiled surface, the plane blows up
2925          * if the x offset + width exceed the stride.
2926          *
2927          * TODO: linear and Y-tiled seem fine, Yf untested,
2928          */
2929         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2930                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2931
2932                 while ((x + w) * cpp > fb->pitches[0]) {
2933                         if (offset == 0) {
2934                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2935                                 return -EINVAL;
2936                         }
2937
2938                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2939                                                           offset, offset - alignment);
2940                 }
2941         }
2942
2943         plane_state->main.offset = offset;
2944         plane_state->main.x = x;
2945         plane_state->main.y = y;
2946
2947         return 0;
2948 }
2949
2950 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2951 {
2952         const struct drm_framebuffer *fb = plane_state->base.fb;
2953         unsigned int rotation = plane_state->base.rotation;
2954         int max_width = skl_max_plane_width(fb, 1, rotation);
2955         int max_height = 4096;
2956         int x = plane_state->base.src.x1 >> 17;
2957         int y = plane_state->base.src.y1 >> 17;
2958         int w = drm_rect_width(&plane_state->base.src) >> 17;
2959         int h = drm_rect_height(&plane_state->base.src) >> 17;
2960         u32 offset;
2961
2962         intel_add_fb_offsets(&x, &y, plane_state, 1);
2963         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2964
2965         /* FIXME not quite sure how/if these apply to the chroma plane */
2966         if (w > max_width || h > max_height) {
2967                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2968                               w, h, max_width, max_height);
2969                 return -EINVAL;
2970         }
2971
2972         plane_state->aux.offset = offset;
2973         plane_state->aux.x = x;
2974         plane_state->aux.y = y;
2975
2976         return 0;
2977 }
2978
2979 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2980 {
2981         const struct drm_framebuffer *fb = plane_state->base.fb;
2982         unsigned int rotation = plane_state->base.rotation;
2983         int ret;
2984
2985         /* Rotate src coordinates to match rotated GTT view */
2986         if (drm_rotation_90_or_270(rotation))
2987                 drm_rect_rotate(&plane_state->base.src,
2988                                 fb->width, fb->height, DRM_ROTATE_270);
2989
2990         /*
2991          * Handle the AUX surface first since
2992          * the main surface setup depends on it.
2993          */
2994         if (fb->pixel_format == DRM_FORMAT_NV12) {
2995                 ret = skl_check_nv12_aux_surface(plane_state);
2996                 if (ret)
2997                         return ret;
2998         } else {
2999                 plane_state->aux.offset = ~0xfff;
3000                 plane_state->aux.x = 0;
3001                 plane_state->aux.y = 0;
3002         }
3003
3004         ret = skl_check_main_surface(plane_state);
3005         if (ret)
3006                 return ret;
3007
3008         return 0;
3009 }
3010
3011 static void i9xx_update_primary_plane(struct drm_plane *primary,
3012                                       const struct intel_crtc_state *crtc_state,
3013                                       const struct intel_plane_state *plane_state)
3014 {
3015         struct drm_device *dev = primary->dev;
3016         struct drm_i915_private *dev_priv = to_i915(dev);
3017         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3018         struct drm_framebuffer *fb = plane_state->base.fb;
3019         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3020         int plane = intel_crtc->plane;
3021         u32 linear_offset;
3022         u32 dspcntr;
3023         i915_reg_t reg = DSPCNTR(plane);
3024         unsigned int rotation = plane_state->base.rotation;
3025         int x = plane_state->base.src.x1 >> 16;
3026         int y = plane_state->base.src.y1 >> 16;
3027
3028         dspcntr = DISPPLANE_GAMMA_ENABLE;
3029
3030         dspcntr |= DISPLAY_PLANE_ENABLE;
3031
3032         if (INTEL_INFO(dev)->gen < 4) {
3033                 if (intel_crtc->pipe == PIPE_B)