drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_set_mode(struct drm_crtc *crtc,
  90                           struct drm_atomic_state *state,
  91                           bool force_restore);
  92 static int intel_framebuffer_init(struct drm_device *dev,
  93                                   struct intel_framebuffer *ifb,
  94                                   struct drm_mode_fb_cmd2 *mode_cmd,
  95                                   struct drm_i915_gem_object *obj);
  96 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  97 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  98 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  99                                          struct intel_link_m_n *m_n,
 100                                          struct intel_link_m_n *m2_n2);
 101 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 102 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 103 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 104 static void vlv_prepare_pll(struct intel_crtc *crtc,
 105                             const struct intel_crtc_state *pipe_config);
 106 static void chv_prepare_pll(struct intel_crtc *crtc,
 107                             const struct intel_crtc_state *pipe_config);
 108 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 109 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 110 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 111         struct intel_crtc_state *crtc_state);
 112 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 113                            int num_connectors);
 114 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
 115 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
 116
 117 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 118 {
 119         if (!connector->mst_port)
 120                 return connector->encoder;
 121         else
 122                 return &connector->mst_port->mst_encoders[pipe]->base;
 123 }
 124
 125 typedef struct {
 126         int     min, max;
 127 } intel_range_t;
 128
 129 typedef struct {
 130         int     dot_limit;
 131         int     p2_slow, p2_fast;
 132 } intel_p2_t;
 133
 134 typedef struct intel_limit intel_limit_t;
 135 struct intel_limit {
 136         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 137         intel_p2_t          p2;
 138 };
 139
 140 int
 141 intel_pch_rawclk(struct drm_device *dev)
 142 {
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144
 145         WARN_ON(!HAS_PCH_SPLIT(dev));
 146
 147         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 148 }
 149
 150 static inline u32 /* units of 100MHz */
 151 intel_fdi_link_freq(struct drm_device *dev)
 152 {
 153         if (IS_GEN5(dev)) {
 154                 struct drm_i915_private *dev_priv = dev->dev_private;
 155                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 156         } else
 157                 return 27;
 158 }
 159
 160 static const intel_limit_t intel_limits_i8xx_dac = {
 161         .dot = { .min = 25000, .max = 350000 },
 162         .vco = { .min = 908000, .max = 1512000 },
 163         .n = { .min = 2, .max = 16 },
 164         .m = { .min = 96, .max = 140 },
 165         .m1 = { .min = 18, .max = 26 },
 166         .m2 = { .min = 6, .max = 16 },
 167         .p = { .min = 4, .max = 128 },
 168         .p1 = { .min = 2, .max = 33 },
 169         .p2 = { .dot_limit = 165000,
 170                 .p2_slow = 4, .p2_fast = 2 },
 171 };
 172
 173 static const intel_limit_t intel_limits_i8xx_dvo = {
 174         .dot = { .min = 25000, .max = 350000 },
 175         .vco = { .min = 908000, .max = 1512000 },
 176         .n = { .min = 2, .max = 16 },
 177         .m = { .min = 96, .max = 140 },
 178         .m1 = { .min = 18, .max = 26 },
 179         .m2 = { .min = 6, .max = 16 },
 180         .p = { .min = 4, .max = 128 },
 181         .p1 = { .min = 2, .max = 33 },
 182         .p2 = { .dot_limit = 165000,
 183                 .p2_slow = 4, .p2_fast = 4 },
 184 };
 185
 186 static const intel_limit_t intel_limits_i8xx_lvds = {
 187         .dot = { .min = 25000, .max = 350000 },
 188         .vco = { .min = 908000, .max = 1512000 },
 189         .n = { .min = 2, .max = 16 },
 190         .m = { .min = 96, .max = 140 },
 191         .m1 = { .min = 18, .max = 26 },
 192         .m2 = { .min = 6, .max = 16 },
 193         .p = { .min = 4, .max = 128 },
 194         .p1 = { .min = 1, .max = 6 },
 195         .p2 = { .dot_limit = 165000,
 196                 .p2_slow = 14, .p2_fast = 7 },
 197 };
 198
 199 static const intel_limit_t intel_limits_i9xx_sdvo = {
 200         .dot = { .min = 20000, .max = 400000 },
 201         .vco = { .min = 1400000, .max = 2800000 },
 202         .n = { .min = 1, .max = 6 },
 203         .m = { .min = 70, .max = 120 },
 204         .m1 = { .min = 8, .max = 18 },
 205         .m2 = { .min = 3, .max = 7 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8 },
 208         .p2 = { .dot_limit = 200000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210 };
 211
 212 static const intel_limit_t intel_limits_i9xx_lvds = {
 213         .dot = { .min = 20000, .max = 400000 },
 214         .vco = { .min = 1400000, .max = 2800000 },
 215         .n = { .min = 1, .max = 6 },
 216         .m = { .min = 70, .max = 120 },
 217         .m1 = { .min = 8, .max = 18 },
 218         .m2 = { .min = 3, .max = 7 },
 219         .p = { .min = 7, .max = 98 },
 220         .p1 = { .min = 1, .max = 8 },
 221         .p2 = { .dot_limit = 112000,
 222                 .p2_slow = 14, .p2_fast = 7 },
 223 };
 224
 225
 226 static const intel_limit_t intel_limits_g4x_sdvo = {
 227         .dot = { .min = 25000, .max = 270000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 17, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 10, .max = 30 },
 234         .p1 = { .min = 1, .max = 3},
 235         .p2 = { .dot_limit = 270000,
 236                 .p2_slow = 10,
 237                 .p2_fast = 10
 238         },
 239 };
 240
 241 static const intel_limit_t intel_limits_g4x_hdmi = {
 242         .dot = { .min = 22000, .max = 400000 },
 243         .vco = { .min = 1750000, .max = 3500000},
 244         .n = { .min = 1, .max = 4 },
 245         .m = { .min = 104, .max = 138 },
 246         .m1 = { .min = 16, .max = 23 },
 247         .m2 = { .min = 5, .max = 11 },
 248         .p = { .min = 5, .max = 80 },
 249         .p1 = { .min = 1, .max = 8},
 250         .p2 = { .dot_limit = 165000,
 251                 .p2_slow = 10, .p2_fast = 5 },
 252 };
 253
 254 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 255         .dot = { .min = 20000, .max = 115000 },
 256         .vco = { .min = 1750000, .max = 3500000 },
 257         .n = { .min = 1, .max = 3 },
 258         .m = { .min = 104, .max = 138 },
 259         .m1 = { .min = 17, .max = 23 },
 260         .m2 = { .min = 5, .max = 11 },
 261         .p = { .min = 28, .max = 112 },
 262         .p1 = { .min = 2, .max = 8 },
 263         .p2 = { .dot_limit = 0,
 264                 .p2_slow = 14, .p2_fast = 14
 265         },
 266 };
 267
 268 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 269         .dot = { .min = 80000, .max = 224000 },
 270         .vco = { .min = 1750000, .max = 3500000 },
 271         .n = { .min = 1, .max = 3 },
 272         .m = { .min = 104, .max = 138 },
 273         .m1 = { .min = 17, .max = 23 },
 274         .m2 = { .min = 5, .max = 11 },
 275         .p = { .min = 14, .max = 42 },
 276         .p1 = { .min = 2, .max = 6 },
 277         .p2 = { .dot_limit = 0,
 278                 .p2_slow = 7, .p2_fast = 7
 279         },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_sdvo = {
 283         .dot = { .min = 20000, .max = 400000},
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         /* Pineview's Ncounter is a ring counter */
 286         .n = { .min = 3, .max = 6 },
 287         .m = { .min = 2, .max = 256 },
 288         /* Pineview only has one combined m divider, which we treat as m2. */
 289         .m1 = { .min = 0, .max = 0 },
 290         .m2 = { .min = 0, .max = 254 },
 291         .p = { .min = 5, .max = 80 },
 292         .p1 = { .min = 1, .max = 8 },
 293         .p2 = { .dot_limit = 200000,
 294                 .p2_slow = 10, .p2_fast = 5 },
 295 };
 296
 297 static const intel_limit_t intel_limits_pineview_lvds = {
 298         .dot = { .min = 20000, .max = 400000 },
 299         .vco = { .min = 1700000, .max = 3500000 },
 300         .n = { .min = 3, .max = 6 },
 301         .m = { .min = 2, .max = 256 },
 302         .m1 = { .min = 0, .max = 0 },
 303         .m2 = { .min = 0, .max = 254 },
 304         .p = { .min = 7, .max = 112 },
 305         .p1 = { .min = 1, .max = 8 },
 306         .p2 = { .dot_limit = 112000,
 307                 .p2_slow = 14, .p2_fast = 14 },
 308 };
 309
 310 /* Ironlake / Sandybridge
 311  *
 312  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 313  * the range value for them is (actual_value - 2).
 314  */
 315 static const intel_limit_t intel_limits_ironlake_dac = {
 316         .dot = { .min = 25000, .max = 350000 },
 317         .vco = { .min = 1760000, .max = 3510000 },
 318         .n = { .min = 1, .max = 5 },
 319         .m = { .min = 79, .max = 127 },
 320         .m1 = { .min = 12, .max = 22 },
 321         .m2 = { .min = 5, .max = 9 },
 322         .p = { .min = 5, .max = 80 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 225000,
 325                 .p2_slow = 10, .p2_fast = 5 },
 326 };
 327
 328 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 329         .dot = { .min = 25000, .max = 350000 },
 330         .vco = { .min = 1760000, .max = 3510000 },
 331         .n = { .min = 1, .max = 3 },
 332         .m = { .min = 79, .max = 118 },
 333         .m1 = { .min = 12, .max = 22 },
 334         .m2 = { .min = 5, .max = 9 },
 335         .p = { .min = 28, .max = 112 },
 336         .p1 = { .min = 2, .max = 8 },
 337         .p2 = { .dot_limit = 225000,
 338                 .p2_slow = 14, .p2_fast = 14 },
 339 };
 340
 341 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 342         .dot = { .min = 25000, .max = 350000 },
 343         .vco = { .min = 1760000, .max = 3510000 },
 344         .n = { .min = 1, .max = 3 },
 345         .m = { .min = 79, .max = 127 },
 346         .m1 = { .min = 12, .max = 22 },
 347         .m2 = { .min = 5, .max = 9 },
 348         .p = { .min = 14, .max = 56 },
 349         .p1 = { .min = 2, .max = 8 },
 350         .p2 = { .dot_limit = 225000,
 351                 .p2_slow = 7, .p2_fast = 7 },
 352 };
 353
 354 /* LVDS 100mhz refclk limits. */
 355 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 356         .dot = { .min = 25000, .max = 350000 },
 357         .vco = { .min = 1760000, .max = 3510000 },
 358         .n = { .min = 1, .max = 2 },
 359         .m = { .min = 79, .max = 126 },
 360         .m1 = { .min = 12, .max = 22 },
 361         .m2 = { .min = 5, .max = 9 },
 362         .p = { .min = 28, .max = 112 },
 363         .p1 = { .min = 2, .max = 8 },
 364         .p2 = { .dot_limit = 225000,
 365                 .p2_slow = 14, .p2_fast = 14 },
 366 };
 367
 368 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 369         .dot = { .min = 25000, .max = 350000 },
 370         .vco = { .min = 1760000, .max = 3510000 },
 371         .n = { .min = 1, .max = 3 },
 372         .m = { .min = 79, .max = 126 },
 373         .m1 = { .min = 12, .max = 22 },
 374         .m2 = { .min = 5, .max = 9 },
 375         .p = { .min = 14, .max = 42 },
 376         .p1 = { .min = 2, .max = 6 },
 377         .p2 = { .dot_limit = 225000,
 378                 .p2_slow = 7, .p2_fast = 7 },
 379 };
 380
 381 static const intel_limit_t intel_limits_vlv = {
 382          /*
 383           * These are the data rate limits (measured in fast clocks)
 384           * since those are the strictest limits we have. The fast
 385           * clock and actual rate limits are more relaxed, so checking
 386           * them would make no difference.
 387           */
 388         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 389         .vco = { .min = 4000000, .max = 6000000 },
 390         .n = { .min = 1, .max = 7 },
 391         .m1 = { .min = 2, .max = 3 },
 392         .m2 = { .min = 11, .max = 156 },
 393         .p1 = { .min = 2, .max = 3 },
 394         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 395 };
 396
 397 static const intel_limit_t intel_limits_chv = {
 398         /*
 399          * These are the data rate limits (measured in fast clocks)
 400          * since those are the strictest limits we have.  The fast
 401          * clock and actual rate limits are more relaxed, so checking
 402          * them would make no difference.
 403          */
 404         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 405         .vco = { .min = 4800000, .max = 6480000 },
 406         .n = { .min = 1, .max = 1 },
 407         .m1 = { .min = 2, .max = 2 },
 408         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 409         .p1 = { .min = 2, .max = 4 },
 410         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 411 };
 412
 413 static const intel_limit_t intel_limits_bxt = {
 414         /* FIXME: find real dot limits */
 415         .dot = { .min = 0, .max = INT_MAX },
 416         .vco = { .min = 4800000, .max = 6480000 },
 417         .n = { .min = 1, .max = 1 },
 418         .m1 = { .min = 2, .max = 2 },
 419         /* FIXME: find real m2 limits */
 420         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 421         .p1 = { .min = 2, .max = 4 },
 422         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 423 };
 424
 425 static void vlv_clock(int refclk, intel_clock_t *clock)
 426 {
 427         clock->m = clock->m1 * clock->m2;
 428         clock->p = clock->p1 * clock->p2;
 429         if (WARN_ON(clock->n == 0 || clock->p == 0))
 430                 return;
 431         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 432         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 433 }
 434
 435 /**
 436  * Returns whether any output on the specified pipe is of the specified type
 437  */
 438 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 439 {
 440         struct drm_device *dev = crtc->base.dev;
 441         struct intel_encoder *encoder;
 442
 443         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 444                 if (encoder->type == type)
 445                         return true;
 446
 447         return false;
 448 }
 449
 450 /**
 451  * Returns whether any output on the specified pipe will have the specified
 452  * type after a staged modeset is complete, i.e., the same as
 453  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 454  * encoder->crtc.
 455  */
 456 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 457                                       int type)
 458 {
 459         struct drm_atomic_state *state = crtc_state->base.state;
 460         struct drm_connector *connector;
 461         struct drm_connector_state *connector_state;
 462         struct intel_encoder *encoder;
 463         int i, num_connectors = 0;
 464
 465         for_each_connector_in_state(state, connector, connector_state, i) {
 466                 if (connector_state->crtc != crtc_state->base.crtc)
 467                         continue;
 468
 469                 num_connectors++;
 470
 471                 encoder = to_intel_encoder(connector_state->best_encoder);
 472                 if (encoder->type == type)
 473                         return true;
 474         }
 475
 476         WARN_ON(num_connectors == 0);
 477
 478         return false;
 479 }
 480
 481 static const intel_limit_t *
 482 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 483 {
 484         struct drm_device *dev = crtc_state->base.crtc->dev;
 485         const intel_limit_t *limit;
 486
 487         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 488                 if (intel_is_dual_link_lvds(dev)) {
 489                         if (refclk == 100000)
 490                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 491                         else
 492                                 limit = &intel_limits_ironlake_dual_lvds;
 493                 } else {
 494                         if (refclk == 100000)
 495                                 limit = &intel_limits_ironlake_single_lvds_100m;
 496                         else
 497                                 limit = &intel_limits_ironlake_single_lvds;
 498                 }
 499         } else
 500                 limit = &intel_limits_ironlake_dac;
 501
 502         return limit;
 503 }
 504
 505 static const intel_limit_t *
 506 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 507 {
 508         struct drm_device *dev = crtc_state->base.crtc->dev;
 509         const intel_limit_t *limit;
 510
 511         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 512                 if (intel_is_dual_link_lvds(dev))
 513                         limit = &intel_limits_g4x_dual_channel_lvds;
 514                 else
 515                         limit = &intel_limits_g4x_single_channel_lvds;
 516         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 517                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 518                 limit = &intel_limits_g4x_hdmi;
 519         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 520                 limit = &intel_limits_g4x_sdvo;
 521         } else /* The option is for other outputs */
 522                 limit = &intel_limits_i9xx_sdvo;
 523
 524         return limit;
 525 }
 526
 527 static const intel_limit_t *
 528 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 529 {
 530         struct drm_device *dev = crtc_state->base.crtc->dev;
 531         const intel_limit_t *limit;
 532
 533         if (IS_BROXTON(dev))
 534                 limit = &intel_limits_bxt;
 535         else if (HAS_PCH_SPLIT(dev))
 536                 limit = intel_ironlake_limit(crtc_state, refclk);
 537         else if (IS_G4X(dev)) {
 538                 limit = intel_g4x_limit(crtc_state);
 539         } else if (IS_PINEVIEW(dev)) {
 540                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 541                         limit = &intel_limits_pineview_lvds;
 542                 else
 543                         limit = &intel_limits_pineview_sdvo;
 544         } else if (IS_CHERRYVIEW(dev)) {
 545                 limit = &intel_limits_chv;
 546         } else if (IS_VALLEYVIEW(dev)) {
 547                 limit = &intel_limits_vlv;
 548         } else if (!IS_GEN2(dev)) {
 549                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 550                         limit = &intel_limits_i9xx_lvds;
 551                 else
 552                         limit = &intel_limits_i9xx_sdvo;
 553         } else {
 554                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 555                         limit = &intel_limits_i8xx_lvds;
 556                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 557                         limit = &intel_limits_i8xx_dvo;
 558                 else
 559                         limit = &intel_limits_i8xx_dac;
 560         }
 561         return limit;
 562 }
 563
 564 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 565 static void pineview_clock(int refclk, intel_clock_t *clock)
 566 {
 567         clock->m = clock->m2 + 2;
 568         clock->p = clock->p1 * clock->p2;
 569         if (WARN_ON(clock->n == 0 || clock->p == 0))
 570                 return;
 571         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 572         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 573 }
 574
 575 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 576 {
 577         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 578 }
 579
 580 static void i9xx_clock(int refclk, intel_clock_t *clock)
 581 {
 582         clock->m = i9xx_dpll_compute_m(clock);
 583         clock->p = clock->p1 * clock->p2;
 584         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 585                 return;
 586         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 587         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 588 }
 589
 590 static void chv_clock(int refclk, intel_clock_t *clock)
 591 {
 592         clock->m = clock->m1 * clock->m2;
 593         clock->p = clock->p1 * clock->p2;
 594         if (WARN_ON(clock->n == 0 || clock->p == 0))
 595                 return;
 596         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 597                         clock->n << 22);
 598         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 599 }
 600
 601 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 602 /**
 603  * Returns whether the given set of divisors are valid for a given refclk with
 604  * the given connectors.
 605  */
 606
 607 static bool intel_PLL_is_valid(struct drm_device *dev,
 608                                const intel_limit_t *limit,
 609                                const intel_clock_t *clock)
 610 {
 611         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 612                 INTELPllInvalid("n out of range\n");
 613         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 614                 INTELPllInvalid("p1 out of range\n");
 615         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 616                 INTELPllInvalid("m2 out of range\n");
 617         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 618                 INTELPllInvalid("m1 out of range\n");
 619
 620         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 621                 if (clock->m1 <= clock->m2)
 622                         INTELPllInvalid("m1 <= m2\n");
 623
 624         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 625                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 626                         INTELPllInvalid("p out of range\n");
 627                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 628                         INTELPllInvalid("m out of range\n");
 629         }
 630
 631         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 632                 INTELPllInvalid("vco out of range\n");
 633         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 634          * connector, etc., rather than just a single range.
 635          */
 636         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 637                 INTELPllInvalid("dot out of range\n");
 638
 639         return true;
 640 }
 641
 642 static bool
 643 i9xx_find_best_dpll(const intel_limit_t *limit,
 644                     struct intel_crtc_state *crtc_state,
 645                     int target, int refclk, intel_clock_t *match_clock,
 646                     intel_clock_t *best_clock)
 647 {
 648         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 649         struct drm_device *dev = crtc->base.dev;
 650         intel_clock_t clock;
 651         int err = target;
 652
 653         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 654                 /*
 655                  * For LVDS just rely on its current settings for dual-channel.
 656                  * We haven't figured out how to reliably set up different
 657                  * single/dual channel state, if we even can.
 658                  */
 659                 if (intel_is_dual_link_lvds(dev))
 660                         clock.p2 = limit->p2.p2_fast;
 661                 else
 662                         clock.p2 = limit->p2.p2_slow;
 663         } else {
 664                 if (target < limit->p2.dot_limit)
 665                         clock.p2 = limit->p2.p2_slow;
 666                 else
 667                         clock.p2 = limit->p2.p2_fast;
 668         }
 669
 670         memset(best_clock, 0, sizeof(*best_clock));
 671
 672         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 673              clock.m1++) {
 674                 for (clock.m2 = limit->m2.min;
 675                      clock.m2 <= limit->m2.max; clock.m2++) {
 676                         if (clock.m2 >= clock.m1)
 677                                 break;
 678                         for (clock.n = limit->n.min;
 679                              clock.n <= limit->n.max; clock.n++) {
 680                                 for (clock.p1 = limit->p1.min;
 681                                         clock.p1 <= limit->p1.max; clock.p1++) {
 682                                         int this_err;
 683
 684                                         i9xx_clock(refclk, &clock);
 685                                         if (!intel_PLL_is_valid(dev, limit,
 686                                                                 &clock))
 687                                                 continue;
 688                                         if (match_clock &&
 689                                             clock.p != match_clock->p)
 690                                                 continue;
 691
 692                                         this_err = abs(clock.dot - target);
 693                                         if (this_err < err) {
 694                                                 *best_clock = clock;
 695                                                 err = this_err;
 696                                         }
 697                                 }
 698                         }
 699                 }
 700         }
 701
 702         return (err != target);
 703 }
 704
 705 static bool
 706 pnv_find_best_dpll(const intel_limit_t *limit,
 707                    struct intel_crtc_state *crtc_state,
 708                    int target, int refclk, intel_clock_t *match_clock,
 709                    intel_clock_t *best_clock)
 710 {
 711         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 712         struct drm_device *dev = crtc->base.dev;
 713         intel_clock_t clock;
 714         int err = target;
 715
 716         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 717                 /*
 718                  * For LVDS just rely on its current settings for dual-channel.
 719                  * We haven't figured out how to reliably set up different
 720                  * single/dual channel state, if we even can.
 721                  */
 722                 if (intel_is_dual_link_lvds(dev))
 723                         clock.p2 = limit->p2.p2_fast;
 724                 else
 725                         clock.p2 = limit->p2.p2_slow;
 726         } else {
 727                 if (target < limit->p2.dot_limit)
 728                         clock.p2 = limit->p2.p2_slow;
 729                 else
 730                         clock.p2 = limit->p2.p2_fast;
 731         }
 732
 733         memset(best_clock, 0, sizeof(*best_clock));
 734
 735         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 736              clock.m1++) {
 737                 for (clock.m2 = limit->m2.min;
 738                      clock.m2 <= limit->m2.max; clock.m2++) {
 739                         for (clock.n = limit->n.min;
 740                              clock.n <= limit->n.max; clock.n++) {
 741                                 for (clock.p1 = limit->p1.min;
 742                                         clock.p1 <= limit->p1.max; clock.p1++) {
 743                                         int this_err;
 744
 745                                         pineview_clock(refclk, &clock);
 746                                         if (!intel_PLL_is_valid(dev, limit,
 747                                                                 &clock))
 748                                                 continue;
 749                                         if (match_clock &&
 750                                             clock.p != match_clock->p)
 751                                                 continue;
 752
 753                                         this_err = abs(clock.dot - target);
 754                                         if (this_err < err) {
 755                                                 *best_clock = clock;
 756                                                 err = this_err;
 757                                         }
 758                                 }
 759                         }
 760                 }
 761         }
 762
 763         return (err != target);
 764 }
 765
 766 static bool
 767 g4x_find_best_dpll(const intel_limit_t *limit,
 768                    struct intel_crtc_state *crtc_state,
 769                    int target, int refclk, intel_clock_t *match_clock,
 770                    intel_clock_t *best_clock)
 771 {
 772         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 773         struct drm_device *dev = crtc->base.dev;
 774         intel_clock_t clock;
 775         int max_n;
 776         bool found;
 777         /* approximately equals target * 0.00585 */
 778         int err_most = (target >> 8) + (target >> 9);
 779         found = false;
 780
 781         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 782                 if (intel_is_dual_link_lvds(dev))
 783                         clock.p2 = limit->p2.p2_fast;
 784                 else
 785                         clock.p2 = limit->p2.p2_slow;
 786         } else {
 787                 if (target < limit->p2.dot_limit)
 788                         clock.p2 = limit->p2.p2_slow;
 789                 else
 790                         clock.p2 = limit->p2.p2_fast;
 791         }
 792
 793         memset(best_clock, 0, sizeof(*best_clock));
 794         max_n = limit->n.max;
 795         /* based on hardware requirement, prefer smaller n to precision */
 796         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 797                 /* based on hardware requirement, prefere larger m1,m2 */
 798                 for (clock.m1 = limit->m1.max;
 799                      clock.m1 >= limit->m1.min; clock.m1--) {
 800                         for (clock.m2 = limit->m2.max;
 801                              clock.m2 >= limit->m2.min; clock.m2--) {
 802                                 for (clock.p1 = limit->p1.max;
 803                                      clock.p1 >= limit->p1.min; clock.p1--) {
 804                                         int this_err;
 805
 806                                         i9xx_clock(refclk, &clock);
 807                                         if (!intel_PLL_is_valid(dev, limit,
 808                                                                 &clock))
 809                                                 continue;
 810
 811                                         this_err = abs(clock.dot - target);
 812                                         if (this_err < err_most) {
 813                                                 *best_clock = clock;
 814                                                 err_most = this_err;
 815                                                 max_n = clock.n;
 816                                                 found = true;
 817                                         }
 818                                 }
 819                         }
 820                 }
 821         }
 822         return found;
 823 }
 824
 825 /*
 826  * Check if the calculated PLL configuration is more optimal compared to the
 827  * best configuration and error found so far. Return the calculated error.
 828  */
 829 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 830                                const intel_clock_t *calculated_clock,
 831                                const intel_clock_t *best_clock,
 832                                unsigned int best_error_ppm,
 833                                unsigned int *error_ppm)
 834 {
 835         /*
 836          * For CHV ignore the error and consider only the P value.
 837          * Prefer a bigger P value based on HW requirements.
 838          */
 839         if (IS_CHERRYVIEW(dev)) {
 840                 *error_ppm = 0;
 841
 842                 return calculated_clock->p > best_clock->p;
 843         }
 844
 845         if (WARN_ON_ONCE(!target_freq))
 846                 return false;
 847
 848         *error_ppm = div_u64(1000000ULL *
 849                                 abs(target_freq - calculated_clock->dot),
 850                              target_freq);
 851         /*
 852          * Prefer a better P value over a better (smaller) error if the error
 853          * is small. Ensure this preference for future configurations too by
 854          * setting the error to 0.
 855          */
 856         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 857                 *error_ppm = 0;
 858
 859                 return true;
 860         }
 861
 862         return *error_ppm + 10 < best_error_ppm;
 863 }
 864
 865 static bool
 866 vlv_find_best_dpll(const intel_limit_t *limit,
 867                    struct intel_crtc_state *crtc_state,
 868                    int target, int refclk, intel_clock_t *match_clock,
 869                    intel_clock_t *best_clock)
 870 {
 871         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 872         struct drm_device *dev = crtc->base.dev;
 873         intel_clock_t clock;
 874         unsigned int bestppm = 1000000;
 875         /* min update 19.2 MHz */
 876         int max_n = min(limit->n.max, refclk / 19200);
 877         bool found = false;
 878
 879         target *= 5; /* fast clock */
 880
 881         memset(best_clock, 0, sizeof(*best_clock));
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 885                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 886                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 887                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 888                                 clock.p = clock.p1 * clock.p2;
 889                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 890                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 891                                         unsigned int ppm;
 892
 893                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 894                                                                      refclk * clock.m1);
 895
 896                                         vlv_clock(refclk, &clock);
 897
 898                                         if (!intel_PLL_is_valid(dev, limit,
 899                                                                 &clock))
 900                                                 continue;
 901
 902                                         if (!vlv_PLL_is_optimal(dev, target,
 903                                                                 &clock,
 904                                                                 best_clock,
 905                                                                 bestppm, &ppm))
 906                                                 continue;
 907
 908                                         *best_clock = clock;
 909                                         bestppm = ppm;
 910                                         found = true;
 911                                 }
 912                         }
 913                 }
 914         }
 915
 916         return found;
 917 }
 918
 919 static bool
 920 chv_find_best_dpll(const intel_limit_t *limit,
 921                    struct intel_crtc_state *crtc_state,
 922                    int target, int refclk, intel_clock_t *match_clock,
 923                    intel_clock_t *best_clock)
 924 {
 925         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 926         struct drm_device *dev = crtc->base.dev;
 927         unsigned int best_error_ppm;
 928         intel_clock_t clock;
 929         uint64_t m2;
 930         int found = false;
 931
 932         memset(best_clock, 0, sizeof(*best_clock));
 933         best_error_ppm = 1000000;
 934
 935         /*
 936          * Based on hardware doc, the n always set to 1, and m1 always
 937          * set to 2.  If requires to support 200Mhz refclk, we need to
 938          * revisit this because n may not 1 anymore.
 939          */
 940         clock.n = 1, clock.m1 = 2;
 941         target *= 5;    /* fast clock */
 942
 943         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 944                 for (clock.p2 = limit->p2.p2_fast;
 945                                 clock.p2 >= limit->p2.p2_slow;
 946                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 947                         unsigned int error_ppm;
 948
 949                         clock.p = clock.p1 * clock.p2;
 950
 951                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 952                                         clock.n) << 22, refclk * clock.m1);
 953
 954                         if (m2 > INT_MAX/clock.m1)
 955                                 continue;
 956
 957                         clock.m2 = m2;
 958
 959                         chv_clock(refclk, &clock);
 960
 961                         if (!intel_PLL_is_valid(dev, limit, &clock))
 962                                 continue;
 963
 964                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 965                                                 best_error_ppm, &error_ppm))
 966                                 continue;
 967
 968                         *best_clock = clock;
 969                         best_error_ppm = error_ppm;
 970                         found = true;
 971                 }
 972         }
 973
 974         return found;
 975 }
 976
 977 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 978                         intel_clock_t *best_clock)
 979 {
 980         int refclk = i9xx_get_refclk(crtc_state, 0);
 981
 982         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 983                                   target_clock, refclk, NULL, best_clock);
 984 }
 985
 986 bool intel_crtc_active(struct drm_crtc *crtc)
 987 {
 988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 989
 990         /* Be paranoid as we can arrive here with only partial
 991          * state retrieved from the hardware during setup.
 992          *
 993          * We can ditch the adjusted_mode.crtc_clock check as soon
 994          * as Haswell has gained clock readout/fastboot support.
 995          *
 996          * We can ditch the crtc->primary->fb check as soon as we can
 997          * properly reconstruct framebuffers.
 998          *
 999          * FIXME: The intel_crtc->active here should be switched to
1000          * crtc->state->active once we have proper CRTC states wired up
1001          * for atomic.
1002          */
1003         return intel_crtc->active && crtc->primary->state->fb &&
1004                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1005 }
1006
1007 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1008                                              enum pipe pipe)
1009 {
1010         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1012
1013         return intel_crtc->config->cpu_transcoder;
1014 }
1015
1016 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1017 {
1018         struct drm_i915_private *dev_priv = dev->dev_private;
1019         u32 reg = PIPEDSL(pipe);
1020         u32 line1, line2;
1021         u32 line_mask;
1022
1023         if (IS_GEN2(dev))
1024                 line_mask = DSL_LINEMASK_GEN2;
1025         else
1026                 line_mask = DSL_LINEMASK_GEN3;
1027
1028         line1 = I915_READ(reg) & line_mask;
1029         mdelay(5);
1030         line2 = I915_READ(reg) & line_mask;
1031
1032         return line1 == line2;
1033 }
1034
1035 /*
1036  * intel_wait_for_pipe_off - wait for pipe to turn off
1037  * @crtc: crtc whose pipe to wait for
1038  *
1039  * After disabling a pipe, we can't wait for vblank in the usual way,
1040  * spinning on the vblank interrupt status bit, since we won't actually
1041  * see an interrupt when the pipe is disabled.
1042  *
1043  * On Gen4 and above:
1044  *   wait for the pipe register state bit to turn off
1045  *
1046  * Otherwise:
1047  *   wait for the display line value to settle (it usually
1048  *   ends up stopping at the start of the next frame).
1049  *
1050  */
1051 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1052 {
1053         struct drm_device *dev = crtc->base.dev;
1054         struct drm_i915_private *dev_priv = dev->dev_private;
1055         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1056         enum pipe pipe = crtc->pipe;
1057
1058         if (INTEL_INFO(dev)->gen >= 4) {
1059                 int reg = PIPECONF(cpu_transcoder);
1060
1061                 /* Wait for the Pipe State to go off */
1062                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1063                              100))
1064                         WARN(1, "pipe_off wait timed out\n");
1065         } else {
1066                 /* Wait for the display line to settle */
1067                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1068                         WARN(1, "pipe_off wait timed out\n");
1069         }
1070 }
1071
1072 /*
1073  * ibx_digital_port_connected - is the specified port connected?
1074  * @dev_priv: i915 private structure
1075  * @port: the port to test
1076  *
1077  * Returns true if @port is connected, false otherwise.
1078  */
1079 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1080                                 struct intel_digital_port *port)
1081 {
1082         u32 bit;
1083
1084         if (HAS_PCH_IBX(dev_priv->dev)) {
1085                 switch (port->port) {
1086                 case PORT_B:
1087                         bit = SDE_PORTB_HOTPLUG;
1088                         break;
1089                 case PORT_C:
1090                         bit = SDE_PORTC_HOTPLUG;
1091                         break;
1092                 case PORT_D:
1093                         bit = SDE_PORTD_HOTPLUG;
1094                         break;
1095                 default:
1096                         return true;
1097                 }
1098         } else {
1099                 switch (port->port) {
1100                 case PORT_B:
1101                         bit = SDE_PORTB_HOTPLUG_CPT;
1102                         break;
1103                 case PORT_C:
1104                         bit = SDE_PORTC_HOTPLUG_CPT;
1105                         break;
1106                 case PORT_D:
1107                         bit = SDE_PORTD_HOTPLUG_CPT;
1108                         break;
1109                 default:
1110                         return true;
1111                 }
1112         }
1113
1114         return I915_READ(SDEISR) & bit;
1115 }
1116
1117 static const char *state_string(bool enabled)
1118 {
1119         return enabled ? "on" : "off";
1120 }
1121
1122 /* Only for pre-ILK configs */
1123 void assert_pll(struct drm_i915_private *dev_priv,
1124                 enum pipe pipe, bool state)
1125 {
1126         int reg;
1127         u32 val;
1128         bool cur_state;
1129
1130         reg = DPLL(pipe);
1131         val = I915_READ(reg);
1132         cur_state = !!(val & DPLL_VCO_ENABLE);
1133         I915_STATE_WARN(cur_state != state,
1134              "PLL state assertion failure (expected %s, current %s)\n",
1135              state_string(state), state_string(cur_state));
1136 }
1137
1138 /* XXX: the dsi pll is shared between MIPI DSI ports */
1139 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1140 {
1141         u32 val;
1142         bool cur_state;
1143
1144         mutex_lock(&dev_priv->sb_lock);
1145         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1146         mutex_unlock(&dev_priv->sb_lock);
1147
1148         cur_state = val & DSI_PLL_VCO_EN;
1149         I915_STATE_WARN(cur_state != state,
1150              "DSI PLL state assertion failure (expected %s, current %s)\n",
1151              state_string(state), state_string(cur_state));
1152 }
1153 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1154 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1155
1156 struct intel_shared_dpll *
1157 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1158 {
1159         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1160
1161         if (crtc->config->shared_dpll < 0)
1162                 return NULL;
1163
1164         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1165 }
1166
1167 /* For ILK+ */
1168 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1169                         struct intel_shared_dpll *pll,
1170                         bool state)
1171 {
1172         bool cur_state;
1173         struct intel_dpll_hw_state hw_state;
1174
1175         if (WARN (!pll,
1176                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1177                 return;
1178
1179         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1180         I915_STATE_WARN(cur_state != state,
1181              "%s assertion failure (expected %s, current %s)\n",
1182              pll->name, state_string(state), state_string(cur_state));
1183 }
1184
1185 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1186                           enum pipe pipe, bool state)
1187 {
1188         int reg;
1189         u32 val;
1190         bool cur_state;
1191         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192                                                                       pipe);
1193
1194         if (HAS_DDI(dev_priv->dev)) {
1195                 /* DDI does not have a specific FDI_TX register */
1196                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1197                 val = I915_READ(reg);
1198                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1199         } else {
1200                 reg = FDI_TX_CTL(pipe);
1201                 val = I915_READ(reg);
1202                 cur_state = !!(val & FDI_TX_ENABLE);
1203         }
1204         I915_STATE_WARN(cur_state != state,
1205              "FDI TX state assertion failure (expected %s, current %s)\n",
1206              state_string(state), state_string(cur_state));
1207 }
1208 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1209 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1210
1211 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1212                           enum pipe pipe, bool state)
1213 {
1214         int reg;
1215         u32 val;
1216         bool cur_state;
1217
1218         reg = FDI_RX_CTL(pipe);
1219         val = I915_READ(reg);
1220         cur_state = !!(val & FDI_RX_ENABLE);
1221         I915_STATE_WARN(cur_state != state,
1222              "FDI RX state assertion failure (expected %s, current %s)\n",
1223              state_string(state), state_string(cur_state));
1224 }
1225 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1226 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1227
1228 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1229                                       enum pipe pipe)
1230 {
1231         int reg;
1232         u32 val;
1233
1234         /* ILK FDI PLL is always enabled */
1235         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1236                 return;
1237
1238         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1239         if (HAS_DDI(dev_priv->dev))
1240                 return;
1241
1242         reg = FDI_TX_CTL(pipe);
1243         val = I915_READ(reg);
1244         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1245 }
1246
1247 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1248                        enum pipe pipe, bool state)
1249 {
1250         int reg;
1251         u32 val;
1252         bool cur_state;
1253
1254         reg = FDI_RX_CTL(pipe);
1255         val = I915_READ(reg);
1256         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1257         I915_STATE_WARN(cur_state != state,
1258              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1259              state_string(state), state_string(cur_state));
1260 }
1261
1262 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1263                            enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int pp_reg;
1267         u32 val;
1268         enum pipe panel_pipe = PIPE_A;
1269         bool locked = true;
1270
1271         if (WARN_ON(HAS_DDI(dev)))
1272                 return;
1273
1274         if (HAS_PCH_SPLIT(dev)) {
1275                 u32 port_sel;
1276
1277                 pp_reg = PCH_PP_CONTROL;
1278                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1279
1280                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1281                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1282                         panel_pipe = PIPE_B;
1283                 /* XXX: else fix for eDP */
1284         } else if (IS_VALLEYVIEW(dev)) {
1285                 /* presumably write lock depends on pipe, not port select */
1286                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1287                 panel_pipe = pipe;
1288         } else {
1289                 pp_reg = PP_CONTROL;
1290                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1291                         panel_pipe = PIPE_B;
1292         }
1293
1294         val = I915_READ(pp_reg);
1295         if (!(val & PANEL_POWER_ON) ||
1296             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1297                 locked = false;
1298
1299         I915_STATE_WARN(panel_pipe == pipe && locked,
1300              "panel assertion failure, pipe %c regs locked\n",
1301              pipe_name(pipe));
1302 }
1303
1304 static void assert_cursor(struct drm_i915_private *dev_priv,
1305                           enum pipe pipe, bool state)
1306 {
1307         struct drm_device *dev = dev_priv->dev;
1308         bool cur_state;
1309
1310         if (IS_845G(dev) || IS_I865G(dev))
1311                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1312         else
1313                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1314
1315         I915_STATE_WARN(cur_state != state,
1316              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1317              pipe_name(pipe), state_string(state), state_string(cur_state));
1318 }
1319 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1320 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1321
1322 void assert_pipe(struct drm_i915_private *dev_priv,
1323                  enum pipe pipe, bool state)
1324 {
1325         int reg;
1326         u32 val;
1327         bool cur_state;
1328         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1329                                                                       pipe);
1330
1331         /* if we need the pipe quirk it must be always on */
1332         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1333             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1334                 state = true;
1335
1336         if (!intel_display_power_is_enabled(dev_priv,
1337                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1338                 cur_state = false;
1339         } else {
1340                 reg = PIPECONF(cpu_transcoder);
1341                 val = I915_READ(reg);
1342                 cur_state = !!(val & PIPECONF_ENABLE);
1343         }
1344
1345         I915_STATE_WARN(cur_state != state,
1346              "pipe %c assertion failure (expected %s, current %s)\n",
1347              pipe_name(pipe), state_string(state), state_string(cur_state));
1348 }
1349
1350 static void assert_plane(struct drm_i915_private *dev_priv,
1351                          enum plane plane, bool state)
1352 {
1353         int reg;
1354         u32 val;
1355         bool cur_state;
1356
1357         reg = DSPCNTR(plane);
1358         val = I915_READ(reg);
1359         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1360         I915_STATE_WARN(cur_state != state,
1361              "plane %c assertion failure (expected %s, current %s)\n",
1362              plane_name(plane), state_string(state), state_string(cur_state));
1363 }
1364
1365 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1366 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1367
1368 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1369                                    enum pipe pipe)
1370 {
1371         struct drm_device *dev = dev_priv->dev;
1372         int reg, i;
1373         u32 val;
1374         int cur_pipe;
1375
1376         /* Primary planes are fixed to pipes on gen4+ */
1377         if (INTEL_INFO(dev)->gen >= 4) {
1378                 reg = DSPCNTR(pipe);
1379                 val = I915_READ(reg);
1380                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1381                      "plane %c assertion failure, should be disabled but not\n",
1382                      plane_name(pipe));
1383                 return;
1384         }
1385
1386         /* Need to check both planes against the pipe */
1387         for_each_pipe(dev_priv, i) {
1388                 reg = DSPCNTR(i);
1389                 val = I915_READ(reg);
1390                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1391                         DISPPLANE_SEL_PIPE_SHIFT;
1392                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1393                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1394                      plane_name(i), pipe_name(pipe));
1395         }
1396 }
1397
1398 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1399                                     enum pipe pipe)
1400 {
1401         struct drm_device *dev = dev_priv->dev;
1402         int reg, sprite;
1403         u32 val;
1404
1405         if (INTEL_INFO(dev)->gen >= 9) {
1406                 for_each_sprite(dev_priv, pipe, sprite) {
1407                         val = I915_READ(PLANE_CTL(pipe, sprite));
1408                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1409                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1410                              sprite, pipe_name(pipe));
1411                 }
1412         } else if (IS_VALLEYVIEW(dev)) {
1413                 for_each_sprite(dev_priv, pipe, sprite) {
1414                         reg = SPCNTR(pipe, sprite);
1415                         val = I915_READ(reg);
1416                         I915_STATE_WARN(val & SP_ENABLE,
1417                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1418                              sprite_name(pipe, sprite), pipe_name(pipe));
1419                 }
1420         } else if (INTEL_INFO(dev)->gen >= 7) {
1421                 reg = SPRCTL(pipe);
1422                 val = I915_READ(reg);
1423                 I915_STATE_WARN(val & SPRITE_ENABLE,
1424                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425                      plane_name(pipe), pipe_name(pipe));
1426         } else if (INTEL_INFO(dev)->gen >= 5) {
1427                 reg = DVSCNTR(pipe);
1428                 val = I915_READ(reg);
1429                 I915_STATE_WARN(val & DVS_ENABLE,
1430                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431                      plane_name(pipe), pipe_name(pipe));
1432         }
1433 }
1434
1435 static void assert_vblank_disabled(struct drm_crtc *crtc)
1436 {
1437         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1438                 drm_crtc_vblank_put(crtc);
1439 }
1440
1441 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1442 {
1443         u32 val;
1444         bool enabled;
1445
1446         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1447
1448         val = I915_READ(PCH_DREF_CONTROL);
1449         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1450                             DREF_SUPERSPREAD_SOURCE_MASK));
1451         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1452 }
1453
1454 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1455                                            enum pipe pipe)
1456 {
1457         int reg;
1458         u32 val;
1459         bool enabled;
1460
1461         reg = PCH_TRANSCONF(pipe);
1462         val = I915_READ(reg);
1463         enabled = !!(val & TRANS_ENABLE);
1464         I915_STATE_WARN(enabled,
1465              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1466              pipe_name(pipe));
1467 }
1468
1469 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1470                             enum pipe pipe, u32 port_sel, u32 val)
1471 {
1472         if ((val & DP_PORT_EN) == 0)
1473                 return false;
1474
1475         if (HAS_PCH_CPT(dev_priv->dev)) {
1476                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1477                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1478                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1479                         return false;
1480         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1481                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1482                         return false;
1483         } else {
1484                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1485                         return false;
1486         }
1487         return true;
1488 }
1489
1490 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1491                               enum pipe pipe, u32 val)
1492 {
1493         if ((val & SDVO_ENABLE) == 0)
1494                 return false;
1495
1496         if (HAS_PCH_CPT(dev_priv->dev)) {
1497                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1498                         return false;
1499         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1500                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1501                         return false;
1502         } else {
1503                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1504                         return false;
1505         }
1506         return true;
1507 }
1508
1509 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1510                               enum pipe pipe, u32 val)
1511 {
1512         if ((val & LVDS_PORT_EN) == 0)
1513                 return false;
1514
1515         if (HAS_PCH_CPT(dev_priv->dev)) {
1516                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1517                         return false;
1518         } else {
1519                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1520                         return false;
1521         }
1522         return true;
1523 }
1524
1525 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1526                               enum pipe pipe, u32 val)
1527 {
1528         if ((val & ADPA_DAC_ENABLE) == 0)
1529                 return false;
1530         if (HAS_PCH_CPT(dev_priv->dev)) {
1531                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1532                         return false;
1533         } else {
1534                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1535                         return false;
1536         }
1537         return true;
1538 }
1539
1540 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1541                                    enum pipe pipe, int reg, u32 port_sel)
1542 {
1543         u32 val = I915_READ(reg);
1544         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1545              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1546              reg, pipe_name(pipe));
1547
1548         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1549              && (val & DP_PIPEB_SELECT),
1550              "IBX PCH dp port still using transcoder B\n");
1551 }
1552
1553 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1554                                      enum pipe pipe, int reg)
1555 {
1556         u32 val = I915_READ(reg);
1557         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1558              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1559              reg, pipe_name(pipe));
1560
1561         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1562              && (val & SDVO_PIPE_B_SELECT),
1563              "IBX PCH hdmi port still using transcoder B\n");
1564 }
1565
1566 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1567                                       enum pipe pipe)
1568 {
1569         int reg;
1570         u32 val;
1571
1572         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1573         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1574         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1575
1576         reg = PCH_ADPA;
1577         val = I915_READ(reg);
1578         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1579              "PCH VGA enabled on transcoder %c, should be disabled\n",
1580              pipe_name(pipe));
1581
1582         reg = PCH_LVDS;
1583         val = I915_READ(reg);
1584         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1585              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1586              pipe_name(pipe));
1587
1588         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1591 }
1592
1593 static void intel_init_dpio(struct drm_device *dev)
1594 {
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597         if (!IS_VALLEYVIEW(dev))
1598                 return;
1599
1600         /*
1601          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1602          * CHV x1 PHY (DP/HDMI D)
1603          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1604          */
1605         if (IS_CHERRYVIEW(dev)) {
1606                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1607                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1608         } else {
1609                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1610         }
1611 }
1612
1613 static void vlv_enable_pll(struct intel_crtc *crtc,
1614                            const struct intel_crtc_state *pipe_config)
1615 {
1616         struct drm_device *dev = crtc->base.dev;
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618         int reg = DPLL(crtc->pipe);
1619         u32 dpll = pipe_config->dpll_hw_state.dpll;
1620
1621         assert_pipe_disabled(dev_priv, crtc->pipe);
1622
1623         /* No really, not for ILK+ */
1624         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1625
1626         /* PLL is protected by panel, make sure we can write it */
1627         if (IS_MOBILE(dev_priv->dev))
1628                 assert_panel_unlocked(dev_priv, crtc->pipe);
1629
1630         I915_WRITE(reg, dpll);
1631         POSTING_READ(reg);
1632         udelay(150);
1633
1634         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1636
1637         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1638         POSTING_READ(DPLL_MD(crtc->pipe));
1639
1640         /* We do this three times for luck */
1641         I915_WRITE(reg, dpll);
1642         POSTING_READ(reg);
1643         udelay(150); /* wait for warmup */
1644         I915_WRITE(reg, dpll);
1645         POSTING_READ(reg);
1646         udelay(150); /* wait for warmup */
1647         I915_WRITE(reg, dpll);
1648         POSTING_READ(reg);
1649         udelay(150); /* wait for warmup */
1650 }
1651
1652 static void chv_enable_pll(struct intel_crtc *crtc,
1653                            const struct intel_crtc_state *pipe_config)
1654 {
1655         struct drm_device *dev = crtc->base.dev;
1656         struct drm_i915_private *dev_priv = dev->dev_private;
1657         int pipe = crtc->pipe;
1658         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1659         u32 tmp;
1660
1661         assert_pipe_disabled(dev_priv, crtc->pipe);
1662
1663         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1664
1665         mutex_lock(&dev_priv->sb_lock);
1666
1667         /* Enable back the 10bit clock to display controller */
1668         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1669         tmp |= DPIO_DCLKP_EN;
1670         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1671
1672         mutex_unlock(&dev_priv->sb_lock);
1673
1674         /*
1675          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1676          */
1677         udelay(1);
1678
1679         /* Enable PLL */
1680         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1681
1682         /* Check PLL is locked */
1683         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1684                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1685
1686         /* not sure when this should be written */
1687         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1688         POSTING_READ(DPLL_MD(pipe));
1689 }
1690
1691 static int intel_num_dvo_pipes(struct drm_device *dev)
1692 {
1693         struct intel_crtc *crtc;
1694         int count = 0;
1695
1696         for_each_intel_crtc(dev, crtc)
1697                 count += crtc->active &&
1698                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1699
1700         return count;
1701 }
1702
1703 static void i9xx_enable_pll(struct intel_crtc *crtc)
1704 {
1705         struct drm_device *dev = crtc->base.dev;
1706         struct drm_i915_private *dev_priv = dev->dev_private;
1707         int reg = DPLL(crtc->pipe);
1708         u32 dpll = crtc->config->dpll_hw_state.dpll;
1709
1710         assert_pipe_disabled(dev_priv, crtc->pipe);
1711
1712         /* No really, not for ILK+ */
1713         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1714
1715         /* PLL is protected by panel, make sure we can write it */
1716         if (IS_MOBILE(dev) && !IS_I830(dev))
1717                 assert_panel_unlocked(dev_priv, crtc->pipe);
1718
1719         /* Enable DVO 2x clock on both PLLs if necessary */
1720         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1721                 /*
1722                  * It appears to be important that we don't enable this
1723                  * for the current pipe before otherwise configuring the
1724                  * PLL. No idea how this should be handled if multiple
1725                  * DVO outputs are enabled simultaneosly.
1726                  */
1727                 dpll |= DPLL_DVO_2X_MODE;
1728                 I915_WRITE(DPLL(!crtc->pipe),
1729                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1730         }
1731
1732         /* Wait for the clocks to stabilize. */
1733         POSTING_READ(reg);
1734         udelay(150);
1735
1736         if (INTEL_INFO(dev)->gen >= 4) {
1737                 I915_WRITE(DPLL_MD(crtc->pipe),
1738                            crtc->config->dpll_hw_state.dpll_md);
1739         } else {
1740                 /* The pixel multiplier can only be updated once the
1741                  * DPLL is enabled and the clocks are stable.
1742                  *
1743                  * So write it again.
1744                  */
1745                 I915_WRITE(reg, dpll);
1746         }
1747
1748         /* We do this three times for luck */
1749         I915_WRITE(reg, dpll);
1750         POSTING_READ(reg);
1751         udelay(150); /* wait for warmup */
1752         I915_WRITE(reg, dpll);
1753         POSTING_READ(reg);
1754         udelay(150); /* wait for warmup */
1755         I915_WRITE(reg, dpll);
1756         POSTING_READ(reg);
1757         udelay(150); /* wait for warmup */
1758 }
1759
1760 /**
1761  * i9xx_disable_pll - disable a PLL
1762  * @dev_priv: i915 private structure
1763  * @pipe: pipe PLL to disable
1764  *
1765  * Disable the PLL for @pipe, making sure the pipe is off first.
1766  *
1767  * Note!  This is for pre-ILK only.
1768  */
1769 static void i9xx_disable_pll(struct intel_crtc *crtc)
1770 {
1771         struct drm_device *dev = crtc->base.dev;
1772         struct drm_i915_private *dev_priv = dev->dev_private;
1773         enum pipe pipe = crtc->pipe;
1774
1775         /* Disable DVO 2x clock on both PLLs if necessary */
1776         if (IS_I830(dev) &&
1777             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1778             intel_num_dvo_pipes(dev) == 1) {
1779                 I915_WRITE(DPLL(PIPE_B),
1780                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1781                 I915_WRITE(DPLL(PIPE_A),
1782                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1783         }
1784
1785         /* Don't disable pipe or pipe PLLs if needed */
1786         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1787             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1788                 return;
1789
1790         /* Make sure the pipe isn't still relying on us */
1791         assert_pipe_disabled(dev_priv, pipe);
1792
1793         I915_WRITE(DPLL(pipe), 0);
1794         POSTING_READ(DPLL(pipe));
1795 }
1796
1797 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1798 {
1799         u32 val = 0;
1800
1801         /* Make sure the pipe isn't still relying on us */
1802         assert_pipe_disabled(dev_priv, pipe);
1803
1804         /*
1805          * Leave integrated clock source and reference clock enabled for pipe B.
1806          * The latter is needed for VGA hotplug / manual detection.
1807          */
1808         if (pipe == PIPE_B)
1809                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1810         I915_WRITE(DPLL(pipe), val);
1811         POSTING_READ(DPLL(pipe));
1812
1813 }
1814
1815 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1816 {
1817         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1818         u32 val;
1819
1820         /* Make sure the pipe isn't still relying on us */
1821         assert_pipe_disabled(dev_priv, pipe);
1822
1823         /* Set PLL en = 0 */
1824         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1825         if (pipe != PIPE_A)
1826                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1827         I915_WRITE(DPLL(pipe), val);
1828         POSTING_READ(DPLL(pipe));
1829
1830         mutex_lock(&dev_priv->sb_lock);
1831
1832         /* Disable 10bit clock to display controller */
1833         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1834         val &= ~DPIO_DCLKP_EN;
1835         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1836
1837         /* disable left/right clock distribution */
1838         if (pipe != PIPE_B) {
1839                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1840                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1841                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1842         } else {
1843                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1844                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1845                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1846         }
1847
1848         mutex_unlock(&dev_priv->sb_lock);
1849 }
1850
1851 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1852                          struct intel_digital_port *dport,
1853                          unsigned int expected_mask)
1854 {
1855         u32 port_mask;
1856         int dpll_reg;
1857
1858         switch (dport->port) {
1859         case PORT_B:
1860                 port_mask = DPLL_PORTB_READY_MASK;
1861                 dpll_reg = DPLL(0);
1862                 break;
1863         case PORT_C:
1864                 port_mask = DPLL_PORTC_READY_MASK;
1865                 dpll_reg = DPLL(0);
1866                 expected_mask <<= 4;
1867                 break;
1868         case PORT_D:
1869                 port_mask = DPLL_PORTD_READY_MASK;
1870                 dpll_reg = DPIO_PHY_STATUS;
1871                 break;
1872         default:
1873                 BUG();
1874         }
1875
1876         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1877                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1878                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1879 }
1880
1881 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1882 {
1883         struct drm_device *dev = crtc->base.dev;
1884         struct drm_i915_private *dev_priv = dev->dev_private;
1885         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1886
1887         if (WARN_ON(pll == NULL))
1888                 return;
1889
1890         WARN_ON(!pll->config.crtc_mask);
1891         if (pll->active == 0) {
1892                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1893                 WARN_ON(pll->on);
1894                 assert_shared_dpll_disabled(dev_priv, pll);
1895
1896                 pll->mode_set(dev_priv, pll);
1897         }
1898 }
1899
1900 /**
1901  * intel_enable_shared_dpll - enable PCH PLL
1902  * @dev_priv: i915 private structure
1903  * @pipe: pipe PLL to enable
1904  *
1905  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1906  * drives the transcoder clock.
1907  */
1908 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1909 {
1910         struct drm_device *dev = crtc->base.dev;
1911         struct drm_i915_private *dev_priv = dev->dev_private;
1912         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1913
1914         if (WARN_ON(pll == NULL))
1915                 return;
1916
1917         if (WARN_ON(pll->config.crtc_mask == 0))
1918                 return;
1919
1920         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1921                       pll->name, pll->active, pll->on,
1922                       crtc->base.base.id);
1923
1924         if (pll->active++) {
1925                 WARN_ON(!pll->on);
1926                 assert_shared_dpll_enabled(dev_priv, pll);
1927                 return;
1928         }
1929         WARN_ON(pll->on);
1930
1931         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1932
1933         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1934         pll->enable(dev_priv, pll);
1935         pll->on = true;
1936 }
1937
1938 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1939 {
1940         struct drm_device *dev = crtc->base.dev;
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1943
1944         /* PCH only available on ILK+ */
1945         BUG_ON(INTEL_INFO(dev)->gen < 5);
1946         if (WARN_ON(pll == NULL))
1947                return;
1948
1949         if (WARN_ON(pll->config.crtc_mask == 0))
1950                 return;
1951
1952         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1953                       pll->name, pll->active, pll->on,
1954                       crtc->base.base.id);
1955
1956         if (WARN_ON(pll->active == 0)) {
1957                 assert_shared_dpll_disabled(dev_priv, pll);
1958                 return;
1959         }
1960
1961         assert_shared_dpll_enabled(dev_priv, pll);
1962         WARN_ON(!pll->on);
1963         if (--pll->active)
1964                 return;
1965
1966         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1967         pll->disable(dev_priv, pll);
1968         pll->on = false;
1969
1970         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1971 }
1972
1973 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1974                                            enum pipe pipe)
1975 {
1976         struct drm_device *dev = dev_priv->dev;
1977         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1979         uint32_t reg, val, pipeconf_val;
1980
1981         /* PCH only available on ILK+ */
1982         BUG_ON(!HAS_PCH_SPLIT(dev));
1983
1984         /* Make sure PCH DPLL is enabled */
1985         assert_shared_dpll_enabled(dev_priv,
1986                                    intel_crtc_to_shared_dpll(intel_crtc));
1987
1988         /* FDI must be feeding us bits for PCH ports */
1989         assert_fdi_tx_enabled(dev_priv, pipe);
1990         assert_fdi_rx_enabled(dev_priv, pipe);
1991
1992         if (HAS_PCH_CPT(dev)) {
1993                 /* Workaround: Set the timing override bit before enabling the
1994                  * pch transcoder. */
1995                 reg = TRANS_CHICKEN2(pipe);
1996                 val = I915_READ(reg);
1997                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1998                 I915_WRITE(reg, val);
1999         }
2000
2001         reg = PCH_TRANSCONF(pipe);
2002         val = I915_READ(reg);
2003         pipeconf_val = I915_READ(PIPECONF(pipe));
2004
2005         if (HAS_PCH_IBX(dev_priv->dev)) {
2006                 /*
2007                  * make the BPC in transcoder be consistent with
2008                  * that in pipeconf reg.
2009                  */
2010                 val &= ~PIPECONF_BPC_MASK;
2011                 val |= pipeconf_val & PIPECONF_BPC_MASK;
2012         }
2013
2014         val &= ~TRANS_INTERLACE_MASK;
2015         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2016                 if (HAS_PCH_IBX(dev_priv->dev) &&
2017                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2018                         val |= TRANS_LEGACY_INTERLACED_ILK;
2019                 else
2020                         val |= TRANS_INTERLACED;
2021         else
2022                 val |= TRANS_PROGRESSIVE;
2023
2024         I915_WRITE(reg, val | TRANS_ENABLE);
2025         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2026                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2027 }
2028
2029 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2030                                       enum transcoder cpu_transcoder)
2031 {
2032         u32 val, pipeconf_val;
2033
2034         /* PCH only available on ILK+ */
2035         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2036
2037         /* FDI must be feeding us bits for PCH ports */
2038         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2039         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2040
2041         /* Workaround: set timing override bit. */
2042         val = I915_READ(_TRANSA_CHICKEN2);
2043         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2044         I915_WRITE(_TRANSA_CHICKEN2, val);
2045
2046         val = TRANS_ENABLE;
2047         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2048
2049         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2050             PIPECONF_INTERLACED_ILK)
2051                 val |= TRANS_INTERLACED;
2052         else
2053                 val |= TRANS_PROGRESSIVE;
2054
2055         I915_WRITE(LPT_TRANSCONF, val);
2056         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2057                 DRM_ERROR("Failed to enable PCH transcoder\n");
2058 }
2059
2060 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2061                                             enum pipe pipe)
2062 {
2063         struct drm_device *dev = dev_priv->dev;
2064         uint32_t reg, val;
2065
2066         /* FDI relies on the transcoder */
2067         assert_fdi_tx_disabled(dev_priv, pipe);
2068         assert_fdi_rx_disabled(dev_priv, pipe);
2069
2070         /* Ports must be off as well */
2071         assert_pch_ports_disabled(dev_priv, pipe);
2072
2073         reg = PCH_TRANSCONF(pipe);
2074         val = I915_READ(reg);
2075         val &= ~TRANS_ENABLE;
2076         I915_WRITE(reg, val);
2077         /* wait for PCH transcoder off, transcoder state */
2078         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2079                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2080
2081         if (!HAS_PCH_IBX(dev)) {
2082                 /* Workaround: Clear the timing override chicken bit again. */
2083                 reg = TRANS_CHICKEN2(pipe);
2084                 val = I915_READ(reg);
2085                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2086                 I915_WRITE(reg, val);
2087         }
2088 }
2089
2090 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2091 {
2092         u32 val;
2093
2094         val = I915_READ(LPT_TRANSCONF);
2095         val &= ~TRANS_ENABLE;
2096         I915_WRITE(LPT_TRANSCONF, val);
2097         /* wait for PCH transcoder off, transcoder state */
2098         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2099                 DRM_ERROR("Failed to disable PCH transcoder\n");
2100
2101         /* Workaround: clear timing override bit. */
2102         val = I915_READ(_TRANSA_CHICKEN2);
2103         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2104         I915_WRITE(_TRANSA_CHICKEN2, val);
2105 }
2106
2107 /**
2108  * intel_enable_pipe - enable a pipe, asserting requirements
2109  * @crtc: crtc responsible for the pipe
2110  *
2111  * Enable @crtc's pipe, making sure that various hardware specific requirements
2112  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2113  */
2114 static void intel_enable_pipe(struct intel_crtc *crtc)
2115 {
2116         struct drm_device *dev = crtc->base.dev;
2117         struct drm_i915_private *dev_priv = dev->dev_private;
2118         enum pipe pipe = crtc->pipe;
2119         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2120                                                                       pipe);
2121         enum pipe pch_transcoder;
2122         int reg;
2123         u32 val;
2124
2125         assert_planes_disabled(dev_priv, pipe);
2126         assert_cursor_disabled(dev_priv, pipe);
2127         assert_sprites_disabled(dev_priv, pipe);
2128
2129         if (HAS_PCH_LPT(dev_priv->dev))
2130                 pch_transcoder = TRANSCODER_A;
2131         else
2132                 pch_transcoder = pipe;
2133
2134         /*
2135          * A pipe without a PLL won't actually be able to drive bits from
2136          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2137          * need the check.
2138          */
2139         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2140                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2141                         assert_dsi_pll_enabled(dev_priv);
2142                 else
2143                         assert_pll_enabled(dev_priv, pipe);
2144         else {
2145                 if (crtc->config->has_pch_encoder) {
2146                         /* if driving the PCH, we need FDI enabled */
2147                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2148                         assert_fdi_tx_pll_enabled(dev_priv,
2149                                                   (enum pipe) cpu_transcoder);
2150                 }
2151                 /* FIXME: assert CPU port conditions for SNB+ */
2152         }
2153
2154         reg = PIPECONF(cpu_transcoder);
2155         val = I915_READ(reg);
2156         if (val & PIPECONF_ENABLE) {
2157                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2158                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2159                 return;
2160         }
2161
2162         I915_WRITE(reg, val | PIPECONF_ENABLE);
2163         POSTING_READ(reg);
2164 }
2165
2166 /**
2167  * intel_disable_pipe - disable a pipe, asserting requirements
2168  * @crtc: crtc whose pipes is to be disabled
2169  *
2170  * Disable the pipe of @crtc, making sure that various hardware
2171  * specific requirements are met, if applicable, e.g. plane
2172  * disabled, panel fitter off, etc.
2173  *
2174  * Will wait until the pipe has shut down before returning.
2175  */
2176 static void intel_disable_pipe(struct intel_crtc *crtc)
2177 {
2178         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2179         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2180         enum pipe pipe = crtc->pipe;
2181         int reg;
2182         u32 val;
2183
2184         /*
2185          * Make sure planes won't keep trying to pump pixels to us,
2186          * or we might hang the display.
2187          */
2188         assert_planes_disabled(dev_priv, pipe);
2189         assert_cursor_disabled(dev_priv, pipe);
2190         assert_sprites_disabled(dev_priv, pipe);
2191
2192         reg = PIPECONF(cpu_transcoder);
2193         val = I915_READ(reg);
2194         if ((val & PIPECONF_ENABLE) == 0)
2195                 return;
2196
2197         /*
2198          * Double wide has implications for planes
2199          * so best keep it disabled when not needed.
2200          */
2201         if (crtc->config->double_wide)
2202                 val &= ~PIPECONF_DOUBLE_WIDE;
2203
2204         /* Don't disable pipe or pipe PLLs if needed */
2205         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2206             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2207                 val &= ~PIPECONF_ENABLE;
2208
2209         I915_WRITE(reg, val);
2210         if ((val & PIPECONF_ENABLE) == 0)
2211                 intel_wait_for_pipe_off(crtc);
2212 }
2213
2214 /**
2215  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2216  * @plane:  plane to be enabled
2217  * @crtc: crtc for the plane
2218  *
2219  * Enable @plane on @crtc, making sure that the pipe is running first.
2220  */
2221 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2222                                           struct drm_crtc *crtc)
2223 {
2224         struct drm_device *dev = plane->dev;
2225         struct drm_i915_private *dev_priv = dev->dev_private;
2226         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2227
2228         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2229         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2230         to_intel_plane_state(plane->state)->visible = true;
2231
2232         dev_priv->display.update_primary_plane(crtc, plane->fb,
2233                                                crtc->x, crtc->y);
2234 }
2235
2236 static bool need_vtd_wa(struct drm_device *dev)
2237 {
2238 #ifdef CONFIG_INTEL_IOMMU
2239         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2240                 return true;
2241 #endif
2242         return false;
2243 }
2244
2245 unsigned int
2246 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2247                   uint64_t fb_format_modifier)
2248 {
2249         unsigned int tile_height;
2250         uint32_t pixel_bytes;
2251
2252         switch (fb_format_modifier) {
2253         case DRM_FORMAT_MOD_NONE:
2254                 tile_height = 1;
2255                 break;
2256         case I915_FORMAT_MOD_X_TILED:
2257                 tile_height = IS_GEN2(dev) ? 16 : 8;
2258                 break;
2259         case I915_FORMAT_MOD_Y_TILED:
2260                 tile_height = 32;
2261                 break;
2262         case I915_FORMAT_MOD_Yf_TILED:
2263                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2264                 switch (pixel_bytes) {
2265                 default:
2266                 case 1:
2267                         tile_height = 64;
2268                         break;
2269                 case 2:
2270                 case 4:
2271                         tile_height = 32;
2272                         break;
2273                 case 8:
2274                         tile_height = 16;
2275                         break;
2276                 case 16:
2277                         WARN_ONCE(1,
2278                                   "128-bit pixels are not supported for display!");
2279                         tile_height = 16;
2280                         break;
2281                 }
2282                 break;
2283         default:
2284                 MISSING_CASE(fb_format_modifier);
2285                 tile_height = 1;
2286                 break;
2287         }
2288
2289         return tile_height;
2290 }
2291
2292 unsigned int
2293 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2294                       uint32_t pixel_format, uint64_t fb_format_modifier)
2295 {
2296         return ALIGN(height, intel_tile_height(dev, pixel_format,
2297                                                fb_format_modifier));
2298 }
2299
2300 static int
2301 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2302                         const struct drm_plane_state *plane_state)
2303 {
2304         struct intel_rotation_info *info = &view->rotation_info;
2305
2306         *view = i915_ggtt_view_normal;
2307
2308         if (!plane_state)
2309                 return 0;
2310
2311         if (!intel_rotation_90_or_270(plane_state->rotation))
2312                 return 0;
2313
2314         *view = i915_ggtt_view_rotated;
2315
2316         info->height = fb->height;
2317         info->pixel_format = fb->pixel_format;
2318         info->pitch = fb->pitches[0];
2319         info->fb_modifier = fb->modifier[0];
2320
2321         return 0;
2322 }
2323
2324 int
2325 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2326                            struct drm_framebuffer *fb,
2327                            const struct drm_plane_state *plane_state,
2328                            struct intel_engine_cs *pipelined)
2329 {
2330         struct drm_device *dev = fb->dev;
2331         struct drm_i915_private *dev_priv = dev->dev_private;
2332         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2333         struct i915_ggtt_view view;
2334         u32 alignment;
2335         int ret;
2336
2337         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2338
2339         switch (fb->modifier[0]) {
2340         case DRM_FORMAT_MOD_NONE:
2341                 if (INTEL_INFO(dev)->gen >= 9)
2342                         alignment = 256 * 1024;
2343                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2344                         alignment = 128 * 1024;
2345                 else if (INTEL_INFO(dev)->gen >= 4)
2346                         alignment = 4 * 1024;
2347                 else
2348                         alignment = 64 * 1024;
2349                 break;
2350         case I915_FORMAT_MOD_X_TILED:
2351                 if (INTEL_INFO(dev)->gen >= 9)
2352                         alignment = 256 * 1024;
2353                 else {
2354                         /* pin() will align the object as required by fence */
2355                         alignment = 0;
2356                 }
2357                 break;
2358         case I915_FORMAT_MOD_Y_TILED:
2359         case I915_FORMAT_MOD_Yf_TILED:
2360                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2361                           "Y tiling bo slipped through, driver bug!\n"))
2362                         return -EINVAL;
2363                 alignment = 1 * 1024 * 1024;
2364                 break;
2365         default:
2366                 MISSING_CASE(fb->modifier[0]);
2367                 return -EINVAL;
2368         }
2369
2370         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2371         if (ret)
2372                 return ret;
2373
2374         /* Note that the w/a also requires 64 PTE of padding following the
2375          * bo. We currently fill all unused PTE with the shadow page and so
2376          * we should always have valid PTE following the scanout preventing
2377          * the VT-d warning.
2378          */
2379         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2380                 alignment = 256 * 1024;
2381
2382         /*
2383          * Global gtt pte registers are special registers which actually forward
2384          * writes to a chunk of system memory. Which means that there is no risk
2385          * that the register values disappear as soon as we call
2386          * intel_runtime_pm_put(), so it is correct to wrap only the
2387          * pin/unpin/fence and not more.
2388          */
2389         intel_runtime_pm_get(dev_priv);
2390
2391         dev_priv->mm.interruptible = false;
2392         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2393                                                    &view);
2394         if (ret)
2395                 goto err_interruptible;
2396
2397         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2398          * fence, whereas 965+ only requires a fence if using
2399          * framebuffer compression.  For simplicity, we always install
2400          * a fence as the cost is not that onerous.
2401          */
2402         ret = i915_gem_object_get_fence(obj);
2403         if (ret)
2404                 goto err_unpin;
2405
2406         i915_gem_object_pin_fence(obj);
2407
2408         dev_priv->mm.interruptible = true;
2409         intel_runtime_pm_put(dev_priv);
2410         return 0;
2411
2412 err_unpin:
2413         i915_gem_object_unpin_from_display_plane(obj, &view);
2414 err_interruptible:
2415         dev_priv->mm.interruptible = true;
2416         intel_runtime_pm_put(dev_priv);
2417         return ret;
2418 }
2419
2420 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2421                                const struct drm_plane_state *plane_state)
2422 {
2423         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2424         struct i915_ggtt_view view;
2425         int ret;
2426
2427         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2428
2429         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2430         WARN_ONCE(ret, "Couldn't get view from plane state!");
2431
2432         i915_gem_object_unpin_fence(obj);
2433         i915_gem_object_unpin_from_display_plane(obj, &view);
2434 }
2435
2436 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2437  * is assumed to be a power-of-two. */
2438 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2439                                              unsigned int tiling_mode,
2440                                              unsigned int cpp,
2441                                              unsigned int pitch)
2442 {
2443         if (tiling_mode != I915_TILING_NONE) {
2444                 unsigned int tile_rows, tiles;
2445
2446                 tile_rows = *y / 8;
2447                 *y %= 8;
2448
2449                 tiles = *x / (512/cpp);
2450                 *x %= 512/cpp;
2451
2452                 return tile_rows * pitch * 8 + tiles * 4096;
2453         } else {
2454                 unsigned int offset;
2455
2456                 offset = *y * pitch + *x * cpp;
2457                 *y = 0;
2458                 *x = (offset & 4095) / cpp;
2459                 return offset & -4096;
2460         }
2461 }
2462
2463 static int i9xx_format_to_fourcc(int format)
2464 {
2465         switch (format) {
2466         case DISPPLANE_8BPP:
2467                 return DRM_FORMAT_C8;
2468         case DISPPLANE_BGRX555:
2469                 return DRM_FORMAT_XRGB1555;
2470         case DISPPLANE_BGRX565:
2471                 return DRM_FORMAT_RGB565;
2472         default:
2473         case DISPPLANE_BGRX888:
2474                 return DRM_FORMAT_XRGB8888;
2475         case DISPPLANE_RGBX888:
2476                 return DRM_FORMAT_XBGR8888;
2477         case DISPPLANE_BGRX101010:
2478                 return DRM_FORMAT_XRGB2101010;
2479         case DISPPLANE_RGBX101010:
2480                 return DRM_FORMAT_XBGR2101010;
2481         }
2482 }
2483
2484 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2485 {
2486         switch (format) {
2487         case PLANE_CTL_FORMAT_RGB_565:
2488                 return DRM_FORMAT_RGB565;
2489         default:
2490         case PLANE_CTL_FORMAT_XRGB_8888:
2491                 if (rgb_order) {
2492                         if (alpha)
2493                                 return DRM_FORMAT_ABGR8888;
2494                         else
2495                                 return DRM_FORMAT_XBGR8888;
2496                 } else {
2497                         if (alpha)
2498                                 return DRM_FORMAT_ARGB8888;
2499                         else
2500                                 return DRM_FORMAT_XRGB8888;
2501                 }
2502         case PLANE_CTL_FORMAT_XRGB_2101010:
2503                 if (rgb_order)
2504                         return DRM_FORMAT_XBGR2101010;
2505                 else
2506                         return DRM_FORMAT_XRGB2101010;
2507         }
2508 }
2509
2510 static bool
2511 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2512                               struct intel_initial_plane_config *plane_config)
2513 {
2514         struct drm_device *dev = crtc->base.dev;
2515         struct drm_i915_gem_object *obj = NULL;
2516         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2517         struct drm_framebuffer *fb = &plane_config->fb->base;
2518         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2519         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2520                                     PAGE_SIZE);
2521
2522         size_aligned -= base_aligned;
2523
2524         if (plane_config->size == 0)
2525                 return false;
2526
2527         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2528                                                              base_aligned,
2529                                                              base_aligned,
2530                                                              size_aligned);
2531         if (!obj)
2532                 return false;
2533
2534         obj->tiling_mode = plane_config->tiling;
2535         if (obj->tiling_mode == I915_TILING_X)
2536                 obj->stride = fb->pitches[0];
2537
2538         mode_cmd.pixel_format = fb->pixel_format;
2539         mode_cmd.width = fb->width;
2540         mode_cmd.height = fb->height;
2541         mode_cmd.pitches[0] = fb->pitches[0];
2542         mode_cmd.modifier[0] = fb->modifier[0];
2543         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2544
2545         mutex_lock(&dev->struct_mutex);
2546         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2547                                    &mode_cmd, obj)) {
2548                 DRM_DEBUG_KMS("intel fb init failed\n");
2549                 goto out_unref_obj;
2550         }
2551         mutex_unlock(&dev->struct_mutex);
2552
2553         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2554         return true;
2555
2556 out_unref_obj:
2557         drm_gem_object_unreference(&obj->base);
2558         mutex_unlock(&dev->struct_mutex);
2559         return false;
2560 }
2561
2562 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2563 static void
2564 update_state_fb(struct drm_plane *plane)
2565 {
2566         if (plane->fb == plane->state->fb)
2567                 return;
2568
2569         if (plane->state->fb)
2570                 drm_framebuffer_unreference(plane->state->fb);
2571         plane->state->fb = plane->fb;
2572         if (plane->state->fb)
2573                 drm_framebuffer_reference(plane->state->fb);
2574 }
2575
2576 static void
2577 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2578                              struct intel_initial_plane_config *plane_config)
2579 {
2580         struct drm_device *dev = intel_crtc->base.dev;
2581         struct drm_i915_private *dev_priv = dev->dev_private;
2582         struct drm_crtc *c;
2583         struct intel_crtc *i;
2584         struct drm_i915_gem_object *obj;
2585         struct drm_plane *primary = intel_crtc->base.primary;
2586         struct drm_framebuffer *fb;
2587
2588         if (!plane_config->fb)
2589                 return;
2590
2591         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2592                 fb = &plane_config->fb->base;
2593                 goto valid_fb;
2594         }
2595
2596         kfree(plane_config->fb);
2597
2598         /*
2599          * Failed to alloc the obj, check to see if we should share
2600          * an fb with another CRTC instead
2601          */
2602         for_each_crtc(dev, c) {
2603                 i = to_intel_crtc(c);
2604
2605                 if (c == &intel_crtc->base)
2606                         continue;
2607
2608                 if (!i->active)
2609                         continue;
2610
2611                 fb = c->primary->fb;
2612                 if (!fb)
2613                         continue;
2614
2615                 obj = intel_fb_obj(fb);
2616                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2617                         drm_framebuffer_reference(fb);
2618                         goto valid_fb;
2619                 }
2620         }
2621
2622         return;
2623
2624 valid_fb:
2625         obj = intel_fb_obj(fb);
2626         if (obj->tiling_mode != I915_TILING_NONE)
2627                 dev_priv->preserve_bios_swizzle = true;
2628
2629         primary->fb = fb;
2630         primary->state->crtc = &intel_crtc->base;
2631         primary->crtc = &intel_crtc->base;
2632         update_state_fb(primary);
2633         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2634 }
2635
2636 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2637                                       struct drm_framebuffer *fb,
2638                                       int x, int y)
2639 {
2640         struct drm_device *dev = crtc->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643         struct drm_plane *primary = crtc->primary;
2644         bool visible = to_intel_plane_state(primary->state)->visible;
2645         struct drm_i915_gem_object *obj;
2646         int plane = intel_crtc->plane;
2647         unsigned long linear_offset;
2648         u32 dspcntr;
2649         u32 reg = DSPCNTR(plane);
2650         int pixel_size;
2651
2652         if (!visible || !fb) {
2653                 I915_WRITE(reg, 0);
2654                 if (INTEL_INFO(dev)->gen >= 4)
2655                         I915_WRITE(DSPSURF(plane), 0);
2656                 else
2657                         I915_WRITE(DSPADDR(plane), 0);
2658                 POSTING_READ(reg);
2659                 return;
2660         }
2661
2662         obj = intel_fb_obj(fb);
2663         if (WARN_ON(obj == NULL))
2664                 return;
2665
2666         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2667
2668         dspcntr = DISPPLANE_GAMMA_ENABLE;
2669
2670         dspcntr |= DISPLAY_PLANE_ENABLE;
2671
2672         if (INTEL_INFO(dev)->gen < 4) {
2673                 if (intel_crtc->pipe == PIPE_B)
2674                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2675
2676                 /* pipesrc and dspsize control the size that is scaled from,
2677                  * which should always be the user's requested size.
2678                  */
2679                 I915_WRITE(DSPSIZE(plane),
2680                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2681                            (intel_crtc->config->pipe_src_w - 1));
2682                 I915_WRITE(DSPPOS(plane), 0);
2683         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2684                 I915_WRITE(PRIMSIZE(plane),
2685                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2686                            (intel_crtc->config->pipe_src_w - 1));
2687                 I915_WRITE(PRIMPOS(plane), 0);
2688                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2689         }
2690
2691         switch (fb->pixel_format) {
2692         case DRM_FORMAT_C8:
2693                 dspcntr |= DISPPLANE_8BPP;
2694                 break;
2695         case DRM_FORMAT_XRGB1555:
2696                 dspcntr |= DISPPLANE_BGRX555;
2697                 break;
2698         case DRM_FORMAT_RGB565:
2699                 dspcntr |= DISPPLANE_BGRX565;
2700                 break;
2701         case DRM_FORMAT_XRGB8888:
2702                 dspcntr |= DISPPLANE_BGRX888;
2703                 break;
2704         case DRM_FORMAT_XBGR8888:
2705                 dspcntr |= DISPPLANE_RGBX888;
2706                 break;
2707         case DRM_FORMAT_XRGB2101010:
2708                 dspcntr |= DISPPLANE_BGRX101010;
2709                 break;
2710         case DRM_FORMAT_XBGR2101010:
2711                 dspcntr |= DISPPLANE_RGBX101010;
2712                 break;
2713         default:
2714                 BUG();
2715         }
2716
2717         if (INTEL_INFO(dev)->gen >= 4 &&
2718             obj->tiling_mode != I915_TILING_NONE)
2719                 dspcntr |= DISPPLANE_TILED;
2720
2721         if (IS_G4X(dev))
2722                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2723
2724         linear_offset = y * fb->pitches[0] + x * pixel_size;
2725
2726         if (INTEL_INFO(dev)->gen >= 4) {
2727                 intel_crtc->dspaddr_offset =
2728                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2729                                                        pixel_size,
2730                                                        fb->pitches[0]);
2731                 linear_offset -= intel_crtc->dspaddr_offset;
2732         } else {
2733                 intel_crtc->dspaddr_offset = linear_offset;
2734         }
2735
2736         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2737                 dspcntr |= DISPPLANE_ROTATE_180;
2738
2739                 x += (intel_crtc->config->pipe_src_w - 1);
2740                 y += (intel_crtc->config->pipe_src_h - 1);
2741
2742                 /* Finding the last pixel of the last line of the display
2743                 data and adding to linear_offset*/
2744                 linear_offset +=
2745                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2746                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2747         }
2748
2749         I915_WRITE(reg, dspcntr);
2750
2751         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2752         if (INTEL_INFO(dev)->gen >= 4) {
2753                 I915_WRITE(DSPSURF(plane),
2754                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2755                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2756                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2757         } else
2758                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2759         POSTING_READ(reg);
2760 }
2761
2762 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2763                                           struct drm_framebuffer *fb,
2764                                           int x, int y)
2765 {
2766         struct drm_device *dev = crtc->dev;
2767         struct drm_i915_private *dev_priv = dev->dev_private;
2768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2769         struct drm_plane *primary = crtc->primary;
2770         bool visible = to_intel_plane_state(primary->state)->visible;
2771         struct drm_i915_gem_object *obj;
2772         int plane = intel_crtc->plane;
2773         unsigned long linear_offset;
2774         u32 dspcntr;
2775         u32 reg = DSPCNTR(plane);
2776         int pixel_size;
2777
2778         if (!visible || !fb) {
2779                 I915_WRITE(reg, 0);
2780                 I915_WRITE(DSPSURF(plane), 0);
2781                 POSTING_READ(reg);
2782                 return;
2783         }
2784
2785         obj = intel_fb_obj(fb);
2786         if (WARN_ON(obj == NULL))
2787                 return;
2788
2789         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2790
2791         dspcntr = DISPPLANE_GAMMA_ENABLE;
2792
2793         dspcntr |= DISPLAY_PLANE_ENABLE;
2794
2795         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2796                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2797
2798         switch (fb->pixel_format) {
2799         case DRM_FORMAT_C8:
2800                 dspcntr |= DISPPLANE_8BPP;
2801                 break;
2802         case DRM_FORMAT_RGB565:
2803                 dspcntr |= DISPPLANE_BGRX565;
2804                 break;
2805         case DRM_FORMAT_XRGB8888:
2806                 dspcntr |= DISPPLANE_BGRX888;
2807                 break;
2808         case DRM_FORMAT_XBGR8888:
2809                 dspcntr |= DISPPLANE_RGBX888;
2810                 break;
2811         case DRM_FORMAT_XRGB2101010:
2812                 dspcntr |= DISPPLANE_BGRX101010;
2813                 break;
2814         case DRM_FORMAT_XBGR2101010:
2815                 dspcntr |= DISPPLANE_RGBX101010;
2816                 break;
2817         default:
2818                 BUG();
2819         }
2820
2821         if (obj->tiling_mode != I915_TILING_NONE)
2822                 dspcntr |= DISPPLANE_TILED;
2823
2824         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2825                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2826
2827         linear_offset = y * fb->pitches[0] + x * pixel_size;
2828         intel_crtc->dspaddr_offset =
2829                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2830                                                pixel_size,
2831                                                fb->pitches[0]);
2832         linear_offset -= intel_crtc->dspaddr_offset;
2833         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2834                 dspcntr |= DISPPLANE_ROTATE_180;
2835
2836                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2837                         x += (intel_crtc->config->pipe_src_w - 1);
2838                         y += (intel_crtc->config->pipe_src_h - 1);
2839
2840                         /* Finding the last pixel of the last line of the display
2841                         data and adding to linear_offset*/
2842                         linear_offset +=
2843                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2844                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2845                 }
2846         }
2847
2848         I915_WRITE(reg, dspcntr);
2849
2850         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2851         I915_WRITE(DSPSURF(plane),
2852                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2853         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2854                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2855         } else {
2856                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2857                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2858         }
2859         POSTING_READ(reg);
2860 }
2861
2862 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2863                               uint32_t pixel_format)
2864 {
2865         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2866
2867         /*
2868          * The stride is either expressed as a multiple of 64 bytes
2869          * chunks for linear buffers or in number of tiles for tiled
2870          * buffers.
2871          */
2872         switch (fb_modifier) {
2873         case DRM_FORMAT_MOD_NONE:
2874                 return 64;
2875         case I915_FORMAT_MOD_X_TILED:
2876                 if (INTEL_INFO(dev)->gen == 2)
2877                         return 128;
2878                 return 512;
2879         case I915_FORMAT_MOD_Y_TILED:
2880                 /* No need to check for old gens and Y tiling since this is
2881                  * about the display engine and those will be blocked before
2882                  * we get here.
2883                  */
2884                 return 128;
2885         case I915_FORMAT_MOD_Yf_TILED:
2886                 if (bits_per_pixel == 8)
2887                         return 64;
2888                 else
2889                         return 128;
2890         default:
2891                 MISSING_CASE(fb_modifier);
2892                 return 64;
2893         }
2894 }
2895
2896 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2897                                      struct drm_i915_gem_object *obj)
2898 {
2899         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2900
2901         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2902                 view = &i915_ggtt_view_rotated;
2903
2904         return i915_gem_obj_ggtt_offset_view(obj, view);
2905 }
2906
2907 /*
2908  * This function detaches (aka. unbinds) unused scalers in hardware
2909  */
2910 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2911 {
2912         struct drm_device *dev;
2913         struct drm_i915_private *dev_priv;
2914         struct intel_crtc_scaler_state *scaler_state;
2915         int i;
2916
2917         if (!intel_crtc || !intel_crtc->config)
2918                 return;
2919
2920         dev = intel_crtc->base.dev;
2921         dev_priv = dev->dev_private;
2922         scaler_state = &intel_crtc->config->scaler_state;
2923
2924         /* loop through and disable scalers that aren't in use */
2925         for (i = 0; i < intel_crtc->num_scalers; i++) {
2926                 if (!scaler_state->scalers[i].in_use) {
2927                         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2928                         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2929                         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2930                         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2931                                 intel_crtc->base.base.id, intel_crtc->pipe, i);
2932                 }
2933         }
2934 }
2935
2936 u32 skl_plane_ctl_format(uint32_t pixel_format)
2937 {
2938         switch (pixel_format) {
2939         case DRM_FORMAT_C8:
2940                 return PLANE_CTL_FORMAT_INDEXED;
2941         case DRM_FORMAT_RGB565:
2942                 return PLANE_CTL_FORMAT_RGB_565;
2943         case DRM_FORMAT_XBGR8888:
2944                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2945         case DRM_FORMAT_XRGB8888:
2946                 return PLANE_CTL_FORMAT_XRGB_8888;
2947         /*
2948          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2949          * to be already pre-multiplied. We need to add a knob (or a different
2950          * DRM_FORMAT) for user-space to configure that.
2951          */
2952         case DRM_FORMAT_ABGR8888:
2953                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2954                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2955         case DRM_FORMAT_ARGB8888:
2956                 return PLANE_CTL_FORMAT_XRGB_8888 |
2957                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2958         case DRM_FORMAT_XRGB2101010:
2959                 return PLANE_CTL_FORMAT_XRGB_2101010;
2960         case DRM_FORMAT_XBGR2101010:
2961                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2962         case DRM_FORMAT_YUYV:
2963                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2964         case DRM_FORMAT_YVYU:
2965                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2966         case DRM_FORMAT_UYVY:
2967                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2968         case DRM_FORMAT_VYUY:
2969                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2970         default:
2971                 MISSING_CASE(pixel_format);
2972         }
2973
2974         return 0;
2975 }
2976
2977 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2978 {
2979         switch (fb_modifier) {
2980         case DRM_FORMAT_MOD_NONE:
2981                 break;
2982         case I915_FORMAT_MOD_X_TILED:
2983                 return PLANE_CTL_TILED_X;
2984         case I915_FORMAT_MOD_Y_TILED:
2985                 return PLANE_CTL_TILED_Y;
2986         case I915_FORMAT_MOD_Yf_TILED:
2987                 return PLANE_CTL_TILED_YF;
2988         default:
2989                 MISSING_CASE(fb_modifier);
2990         }
2991
2992         return 0;
2993 }
2994
2995 u32 skl_plane_ctl_rotation(unsigned int rotation)
2996 {
2997         switch (rotation) {
2998         case BIT(DRM_ROTATE_0):
2999                 break;
3000         /*
3001          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3002          * while i915 HW rotation is clockwise, thats why this swapping.
3003          */
3004         case BIT(DRM_ROTATE_90):
3005                 return PLANE_CTL_ROTATE_270;
3006         case BIT(DRM_ROTATE_180):
3007                 return PLANE_CTL_ROTATE_180;
3008         case BIT(DRM_ROTATE_270):
3009                 return PLANE_CTL_ROTATE_90;
3010         default:
3011                 MISSING_CASE(rotation);
3012         }
3013
3014         return 0;
3015 }
3016
3017 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3018                                          struct drm_framebuffer *fb,
3019                                          int x, int y)
3020 {
3021         struct drm_device *dev = crtc->dev;
3022         struct drm_i915_private *dev_priv = dev->dev_private;
3023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3024         struct drm_plane *plane = crtc->primary;
3025         bool visible = to_intel_plane_state(plane->state)->visible;
3026         struct drm_i915_gem_object *obj;
3027         int pipe = intel_crtc->pipe;
3028         u32 plane_ctl, stride_div, stride;
3029         u32 tile_height, plane_offset, plane_size;
3030         unsigned int rotation;
3031         int x_offset, y_offset;
3032         unsigned long surf_addr;
3033         struct intel_crtc_state *crtc_state = intel_crtc->config;
3034         struct intel_plane_state *plane_state;
3035         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3036         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3037         int scaler_id = -1;
3038
3039         plane_state = to_intel_plane_state(plane->state);
3040
3041         if (!visible || !fb) {
3042                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3043                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3044                 POSTING_READ(PLANE_CTL(pipe, 0));
3045                 return;
3046         }
3047
3048         plane_ctl = PLANE_CTL_ENABLE |
3049                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3050                     PLANE_CTL_PIPE_CSC_ENABLE;
3051
3052         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3053         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3054         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3055
3056         rotation = plane->state->rotation;
3057         plane_ctl |= skl_plane_ctl_rotation(rotation);
3058
3059         obj = intel_fb_obj(fb);
3060         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3061                                                fb->pixel_format);
3062         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3063
3064         /*
3065          * FIXME: intel_plane_state->src, dst aren't set when transitional
3066          * update_plane helpers are called from legacy paths.
3067          * Once full atomic crtc is available, below check can be avoided.
3068          */
3069         if (drm_rect_width(&plane_state->src)) {
3070                 scaler_id = plane_state->scaler_id;
3071                 src_x = plane_state->src.x1 >> 16;
3072                 src_y = plane_state->src.y1 >> 16;
3073                 src_w = drm_rect_width(&plane_state->src) >> 16;
3074                 src_h = drm_rect_height(&plane_state->src) >> 16;
3075                 dst_x = plane_state->dst.x1;
3076                 dst_y = plane_state->dst.y1;
3077                 dst_w = drm_rect_width(&plane_state->dst);
3078                 dst_h = drm_rect_height(&plane_state->dst);
3079
3080                 WARN_ON(x != src_x || y != src_y);
3081         } else {
3082                 src_w = intel_crtc->config->pipe_src_w;
3083                 src_h = intel_crtc->config->pipe_src_h;
3084         }
3085
3086         if (intel_rotation_90_or_270(rotation)) {
3087                 /* stride = Surface height in tiles */
3088                 tile_height = intel_tile_height(dev, fb->pixel_format,
3089                                                 fb->modifier[0]);
3090                 stride = DIV_ROUND_UP(fb->height, tile_height);
3091                 x_offset = stride * tile_height - y - src_h;
3092                 y_offset = x;
3093                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3094         } else {
3095                 stride = fb->pitches[0] / stride_div;
3096                 x_offset = x;
3097                 y_offset = y;
3098                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3099         }
3100         plane_offset = y_offset << 16 | x_offset;
3101
3102         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3103         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3104         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3105         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3106
3107         if (scaler_id >= 0) {
3108                 uint32_t ps_ctrl = 0;
3109
3110                 WARN_ON(!dst_w || !dst_h);
3111                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3112                         crtc_state->scaler_state.scalers[scaler_id].mode;
3113                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3114                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3115                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3116                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3117                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3118         } else {
3119                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3120         }
3121
3122         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3123
3124         POSTING_READ(PLANE_SURF(pipe, 0));
3125 }
3126
3127 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3128 static int
3129 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3130                            int x, int y, enum mode_set_atomic state)
3131 {
3132         struct drm_device *dev = crtc->dev;
3133         struct drm_i915_private *dev_priv = dev->dev_private;
3134
3135         if (dev_priv->display.disable_fbc)
3136                 dev_priv->display.disable_fbc(dev);
3137
3138         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3139
3140         return 0;
3141 }
3142
3143 static void intel_complete_page_flips(struct drm_device *dev)
3144 {
3145         struct drm_crtc *crtc;
3146
3147         for_each_crtc(dev, crtc) {
3148                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3149                 enum plane plane = intel_crtc->plane;
3150
3151                 intel_prepare_page_flip(dev, plane);
3152                 intel_finish_page_flip_plane(dev, plane);
3153         }
3154 }
3155
3156 static void intel_update_primary_planes(struct drm_device *dev)
3157 {
3158         struct drm_i915_private *dev_priv = dev->dev_private;
3159         struct drm_crtc *crtc;
3160
3161         for_each_crtc(dev, crtc) {
3162                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3163
3164                 drm_modeset_lock(&crtc->mutex, NULL);
3165                 /*
3166                  * FIXME: Once we have proper support for primary planes (and
3167                  * disabling them without disabling the entire crtc) allow again
3168                  * a NULL crtc->primary->fb.
3169                  */
3170                 if (intel_crtc->active && crtc->primary->fb)
3171                         dev_priv->display.update_primary_plane(crtc,
3172                                                                crtc->primary->fb,
3173                                                                crtc->x,
3174                                                                crtc->y);
3175                 drm_modeset_unlock(&crtc->mutex);
3176         }
3177 }
3178
3179 void intel_crtc_reset(struct intel_crtc *crtc)
3180 {
3181         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3182
3183         if (!crtc->active)
3184                 return;
3185
3186         intel_crtc_disable_planes(&crtc->base);
3187         dev_priv->display.crtc_disable(&crtc->base);
3188         dev_priv->display.crtc_enable(&crtc->base);
3189         intel_crtc_enable_planes(&crtc->base);
3190 }
3191
3192 void intel_prepare_reset(struct drm_device *dev)
3193 {
3194         struct drm_i915_private *dev_priv = to_i915(dev);
3195         struct intel_crtc *crtc;
3196
3197         /* no reset support for gen2 */
3198         if (IS_GEN2(dev))
3199                 return;
3200
3201         /* reset doesn't touch the display */
3202         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3203                 return;
3204
3205         drm_modeset_lock_all(dev);
3206
3207         /*
3208          * Disabling the crtcs gracefully seems nicer. Also the
3209          * g33 docs say we should at least disable all the planes.
3210          */
3211         for_each_intel_crtc(dev, crtc) {
3212                 if (!crtc->active)
3213                         continue;
3214
3215                 intel_crtc_disable_planes(&crtc->base);
3216                 dev_priv->display.crtc_disable(&crtc->base);
3217         }
3218 }
3219
3220 void intel_finish_reset(struct drm_device *dev)
3221 {
3222         struct drm_i915_private *dev_priv = to_i915(dev);
3223
3224         /*
3225          * Flips in the rings will be nuked by the reset,
3226          * so complete all pending flips so that user space
3227          * will get its events and not get stuck.
3228          */
3229         intel_complete_page_flips(dev);
3230
3231         /* no reset support for gen2 */
3232         if (IS_GEN2(dev))
3233                 return;
3234
3235         /* reset doesn't touch the display */
3236         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3237                 /*
3238                  * Flips in the rings have been nuked by the reset,
3239                  * so update the base address of all primary
3240                  * planes to the the last fb to make sure we're
3241                  * showing the correct fb after a reset.
3242                  */
3243                 intel_update_primary_planes(dev);
3244                 return;
3245         }
3246
3247         /*
3248          * The display has been reset as well,
3249          * so need a full re-initialization.
3250          */
3251         intel_runtime_pm_disable_interrupts(dev_priv);
3252         intel_runtime_pm_enable_interrupts(dev_priv);
3253
3254         intel_modeset_init_hw(dev);
3255
3256         spin_lock_irq(&dev_priv->irq_lock);
3257         if (dev_priv->display.hpd_irq_setup)
3258                 dev_priv->display.hpd_irq_setup(dev);
3259         spin_unlock_irq(&dev_priv->irq_lock);
3260
3261         intel_modeset_setup_hw_state(dev, true);
3262
3263         intel_hpd_init(dev_priv);
3264
3265         drm_modeset_unlock_all(dev);
3266 }
3267
3268 static void
3269 intel_finish_fb(struct drm_framebuffer *old_fb)
3270 {
3271         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3272         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3273         bool was_interruptible = dev_priv->mm.interruptible;
3274         int ret;
3275
3276         /* Big Hammer, we also need to ensure that any pending
3277          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3278          * current scanout is retired before unpinning the old
3279          * framebuffer. Note that we rely on userspace rendering
3280          * into the buffer attached to the pipe they are waiting
3281          * on. If not, userspace generates a GPU hang with IPEHR
3282          * point to the MI_WAIT_FOR_EVENT.
3283          *
3284          * This should only fail upon a hung GPU, in which case we
3285          * can safely continue.
3286          */
3287         dev_priv->mm.interruptible = false;
3288         ret = i915_gem_object_wait_rendering(obj, true);
3289         dev_priv->mm.interruptible = was_interruptible;
3290
3291         WARN_ON(ret);
3292 }
3293
3294 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3295 {
3296         struct drm_device *dev = crtc->dev;
3297         struct drm_i915_private *dev_priv = dev->dev_private;
3298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3299         bool pending;
3300
3301         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3302             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3303                 return false;
3304
3305         spin_lock_irq(&dev->event_lock);
3306         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3307         spin_unlock_irq(&dev->event_lock);
3308
3309         return pending;
3310 }
3311
3312 static void intel_update_pipe_size(struct intel_crtc *crtc)
3313 {
3314         struct drm_device *dev = crtc->base.dev;
3315         struct drm_i915_private *dev_priv = dev->dev_private;
3316         const struct drm_display_mode *adjusted_mode;
3317
3318         if (!i915.fastboot)
3319                 return;
3320
3321         /*
3322          * Update pipe size and adjust fitter if needed: the reason for this is
3323          * that in compute_mode_changes we check the native mode (not the pfit
3324          * mode) to see if we can flip rather than do a full mode set. In the
3325          * fastboot case, we'll flip, but if we don't update the pipesrc and
3326          * pfit state, we'll end up with a big fb scanned out into the wrong
3327          * sized surface.
3328          *
3329          * To fix this properly, we need to hoist the checks up into
3330          * compute_mode_changes (or above), check the actual pfit state and
3331          * whether the platform allows pfit disable with pipe active, and only
3332          * then update the pipesrc and pfit state, even on the flip path.
3333          */
3334
3335         adjusted_mode = &crtc->config->base.adjusted_mode;
3336
3337         I915_WRITE(PIPESRC(crtc->pipe),
3338                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3339                    (adjusted_mode->crtc_vdisplay - 1));
3340         if (!crtc->config->pch_pfit.enabled &&
3341             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3342              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3343                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3344                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3345                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3346         }
3347         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3348         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3349 }
3350
3351 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3352 {
3353         struct drm_device *dev = crtc->dev;
3354         struct drm_i915_private *dev_priv = dev->dev_private;
3355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3356         int pipe = intel_crtc->pipe;
3357         u32 reg, temp;
3358
3359         /* enable normal train */
3360         reg = FDI_TX_CTL(pipe);
3361         temp = I915_READ(reg);
3362         if (IS_IVYBRIDGE(dev)) {
3363                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3364                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3365         } else {
3366                 temp &= ~FDI_LINK_TRAIN_NONE;
3367                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3368         }
3369         I915_WRITE(reg, temp);
3370
3371         reg = FDI_RX_CTL(pipe);
3372         temp = I915_READ(reg);
3373         if (HAS_PCH_CPT(dev)) {
3374                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3375                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3376         } else {
3377                 temp &= ~FDI_LINK_TRAIN_NONE;
3378                 temp |= FDI_LINK_TRAIN_NONE;
3379         }
3380         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3381
3382         /* wait one idle pattern time */
3383         POSTING_READ(reg);
3384         udelay(1000);
3385
3386         /* IVB wants error correction enabled */
3387         if (IS_IVYBRIDGE(dev))
3388                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3389                            FDI_FE_ERRC_ENABLE);
3390 }
3391
3392 /* The FDI link training functions for ILK/Ibexpeak. */
3393 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3394 {
3395         struct drm_device *dev = crtc->dev;
3396         struct drm_i915_private *dev_priv = dev->dev_private;
3397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3398         int pipe = intel_crtc->pipe;
3399         u32 reg, temp, tries;
3400
3401         /* FDI needs bits from pipe first */
3402         assert_pipe_enabled(dev_priv, pipe);
3403
3404         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3405            for train result */
3406         reg = FDI_RX_IMR(pipe);
3407         temp = I915_READ(reg);
3408         temp &= ~FDI_RX_SYMBOL_LOCK;
3409         temp &= ~FDI_RX_BIT_LOCK;
3410         I915_WRITE(reg, temp);
3411         I915_READ(reg);
3412         udelay(150);
3413
3414         /* enable CPU FDI TX and PCH FDI RX */
3415         reg = FDI_TX_CTL(pipe);
3416         temp = I915_READ(reg);
3417         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3418         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3419         temp &= ~FDI_LINK_TRAIN_NONE;
3420         temp |= FDI_LINK_TRAIN_PATTERN_1;
3421         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3422
3423         reg = FDI_RX_CTL(pipe);
3424         temp = I915_READ(reg);
3425         temp &= ~FDI_LINK_TRAIN_NONE;
3426         temp |= FDI_LINK_TRAIN_PATTERN_1;
3427         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3428
3429         POSTING_READ(reg);
3430         udelay(150);
3431
3432         /* Ironlake workaround, enable clock pointer after FDI enable*/
3433         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3434         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3435                    FDI_RX_PHASE_SYNC_POINTER_EN);
3436
3437         reg = FDI_RX_IIR(pipe);
3438         for (tries = 0; tries < 5; tries++) {
3439                 temp = I915_READ(reg);
3440                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3441
3442                 if ((temp & FDI_RX_BIT_LOCK)) {
3443                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3444                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3445                         break;
3446                 }
3447         }
3448         if (tries == 5)
3449                 DRM_ERROR("FDI train 1 fail!\n");
3450
3451         /* Train 2 */
3452         reg = FDI_TX_CTL(pipe);
3453         temp = I915_READ(reg);
3454         temp &= ~FDI_LINK_TRAIN_NONE;
3455         temp |= FDI_LINK_TRAIN_PATTERN_2;
3456         I915_WRITE(reg, temp);
3457
3458         reg = FDI_RX_CTL(pipe);
3459         temp = I915_READ(reg);
3460         temp &= ~FDI_LINK_TRAIN_NONE;
3461         temp |= FDI_LINK_TRAIN_PATTERN_2;
3462         I915_WRITE(reg, temp);
3463
3464         POSTING_READ(reg);
3465         udelay(150);
3466
3467         reg = FDI_RX_IIR(pipe);
3468         for (tries = 0; tries < 5; tries++) {
3469                 temp = I915_READ(reg);
3470                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3471
3472                 if (temp & FDI_RX_SYMBOL_LOCK) {
3473                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3474                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3475                         break;
3476                 }
3477         }
3478         if (tries == 5)
3479                 DRM_ERROR("FDI train 2 fail!\n");
3480
3481         DRM_DEBUG_KMS("FDI train done\n");
3482
3483 }
3484
3485 static const int snb_b_fdi_train_param[] = {
3486         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3487         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3488         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3489         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3490 };
3491
3492 /* The FDI link training functions for SNB/Cougarpoint. */
3493 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3494 {
3495         struct drm_device *dev = crtc->dev;
3496         struct drm_i915_private *dev_priv = dev->dev_private;
3497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3498         int pipe = intel_crtc->pipe;
3499         u32 reg, temp, i, retry;
3500
3501         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3502            for train result */
3503         reg = FDI_RX_IMR(pipe);
3504         temp = I915_READ(reg);
3505         temp &= ~FDI_RX_SYMBOL_LOCK;
3506         temp &= ~FDI_RX_BIT_LOCK;
3507         I915_WRITE(reg, temp);
3508
3509         POSTING_READ(reg);
3510         udelay(150);
3511
3512         /* enable CPU FDI TX and PCH FDI RX */
3513         reg = FDI_TX_CTL(pipe);
3514         temp = I915_READ(reg);
3515         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3516         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3517         temp &= ~FDI_LINK_TRAIN_NONE;
3518         temp |= FDI_LINK_TRAIN_PATTERN_1;
3519         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3520         /* SNB-B */
3521         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3522         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3523
3524         I915_WRITE(FDI_RX_MISC(pipe),
3525                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3526
3527         reg = FDI_RX_CTL(pipe);
3528         temp = I915_READ(reg);
3529         if (HAS_PCH_CPT(dev)) {
3530                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3531                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3532         } else {
3533                 temp &= ~FDI_LINK_TRAIN_NONE;
3534                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3535         }
3536         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3537
3538         POSTING_READ(reg);
3539         udelay(150);
3540
3541         for (i = 0; i < 4; i++) {
3542                 reg = FDI_TX_CTL(pipe);
3543                 temp = I915_READ(reg);
3544                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3545                 temp |= snb_b_fdi_train_param[i];
3546                 I915_WRITE(reg, temp);
3547
3548                 POSTING_READ(reg);
3549                 udelay(500);
3550
3551                 for (retry = 0; retry < 5; retry++) {
3552                         reg = FDI_RX_IIR(pipe);
3553                         temp = I915_READ(reg);
3554                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3555                         if (temp & FDI_RX_BIT_LOCK) {
3556                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3557                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3558                                 break;
3559                         }
3560                         udelay(50);
3561                 }
3562                 if (retry < 5)
3563                         break;
3564         }
3565         if (i == 4)
3566                 DRM_ERROR("FDI train 1 fail!\n");
3567
3568         /* Train 2 */
3569         reg = FDI_TX_CTL(pipe);
3570         temp = I915_READ(reg);
3571         temp &= ~FDI_LINK_TRAIN_NONE;
3572         temp |= FDI_LINK_TRAIN_PATTERN_2;
3573         if (IS_GEN6(dev)) {
3574                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3575                 /* SNB-B */
3576                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3577         }
3578         I915_WRITE(reg, temp);
3579
3580         reg = FDI_RX_CTL(pipe);
3581         temp = I915_READ(reg);
3582         if (HAS_PCH_CPT(dev)) {
3583                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3584                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3585         } else {
3586                 temp &= ~FDI_LINK_TRAIN_NONE;
3587                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3588         }
3589         I915_WRITE(reg, temp);
3590
3591         POSTING_READ(reg);
3592         udelay(150);
3593
3594         for (i = 0; i < 4; i++) {
3595                 reg = FDI_TX_CTL(pipe);
3596                 temp = I915_READ(reg);
3597                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3598                 temp |= snb_b_fdi_train_param[i];
3599                 I915_WRITE(reg, temp);
3600
3601                 POSTING_READ(reg);
3602                 udelay(500);
3603
3604                 for (retry = 0; retry < 5; retry++) {
3605                         reg = FDI_RX_IIR(pipe);
3606                         temp = I915_READ(reg);
3607                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3608                         if (temp & FDI_RX_SYMBOL_LOCK) {
3609                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3610                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3611                                 break;
3612                         }
3613                         udelay(50);
3614                 }
3615                 if (retry < 5)
3616                         break;
3617         }
3618         if (i == 4)
3619                 DRM_ERROR("FDI train 2 fail!\n");
3620
3621         DRM_DEBUG_KMS("FDI train done.\n");
3622 }
3623
3624 /* Manual link training for Ivy Bridge A0 parts */
3625 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3626 {
3627         struct drm_device *dev = crtc->dev;
3628         struct drm_i915_private *dev_priv = dev->dev_private;
3629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3630         int pipe = intel_crtc->pipe;
3631         u32 reg, temp, i, j;
3632
3633         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3634            for train result */
3635         reg = FDI_RX_IMR(pipe);
3636         temp = I915_READ(reg);
3637         temp &= ~FDI_RX_SYMBOL_LOCK;
3638         temp &= ~FDI_RX_BIT_LOCK;
3639         I915_WRITE(reg, temp);
3640
3641         POSTING_READ(reg);
3642         udelay(150);
3643
3644         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3645                       I915_READ(FDI_RX_IIR(pipe)));
3646
3647         /* Try each vswing and preemphasis setting twice before moving on */
3648         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3649                 /* disable first in case we need to retry */
3650                 reg = FDI_TX_CTL(pipe);
3651                 temp = I915_READ(reg);
3652                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3653                 temp &= ~FDI_TX_ENABLE;
3654                 I915_WRITE(reg, temp);
3655
3656                 reg = FDI_RX_CTL(pipe);
3657                 temp = I915_READ(reg);
3658                 temp &= ~FDI_LINK_TRAIN_AUTO;
3659                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3660                 temp &= ~FDI_RX_ENABLE;
3661                 I915_WRITE(reg, temp);
3662
3663                 /* enable CPU FDI TX and PCH FDI RX */
3664                 reg = FDI_TX_CTL(pipe);
3665                 temp = I915_READ(reg);
3666                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3667                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3668                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3669                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3670                 temp |= snb_b_fdi_train_param[j/2];
3671                 temp |= FDI_COMPOSITE_SYNC;
3672                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3673
3674                 I915_WRITE(FDI_RX_MISC(pipe),
3675                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3676
3677                 reg = FDI_RX_CTL(pipe);
3678                 temp = I915_READ(reg);
3679                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3680                 temp |= FDI_COMPOSITE_SYNC;
3681                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3682
3683                 POSTING_READ(reg);
3684                 udelay(1); /* should be 0.5us */
3685
3686                 for (i = 0; i < 4; i++) {
3687                         reg = FDI_RX_IIR(pipe);
3688                         temp = I915_READ(reg);
3689                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3690
3691                         if (temp & FDI_RX_BIT_LOCK ||
3692                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3693                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3694                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3695                                               i);
3696                                 break;
3697                         }
3698                         udelay(1); /* should be 0.5us */
3699                 }
3700                 if (i == 4) {
3701                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3702                         continue;
3703                 }
3704
3705                 /* Train 2 */
3706                 reg = FDI_TX_CTL(pipe);
3707                 temp = I915_READ(reg);
3708                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3709                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3710                 I915_WRITE(reg, temp);
3711
3712                 reg = FDI_RX_CTL(pipe);
3713                 temp = I915_READ(reg);
3714                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3715                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3716                 I915_WRITE(reg, temp);
3717
3718                 POSTING_READ(reg);
3719                 udelay(2); /* should be 1.5us */
3720
3721                 for (i = 0; i < 4; i++) {
3722                         reg = FDI_RX_IIR(pipe);
3723                         temp = I915_READ(reg);
3724                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3725
3726                         if (temp & FDI_RX_SYMBOL_LOCK ||
3727                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3728                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3729                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3730                                               i);
3731                                 goto train_done;
3732                         }
3733                         udelay(2); /* should be 1.5us */
3734                 }
3735                 if (i == 4)
3736                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3737         }
3738
3739 train_done:
3740         DRM_DEBUG_KMS("FDI train done.\n");
3741 }
3742
3743 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3744 {
3745         struct drm_device *dev = intel_crtc->base.dev;
3746         struct drm_i915_private *dev_priv = dev->dev_private;
3747         int pipe = intel_crtc->pipe;
3748         u32 reg, temp;
3749
3750
3751         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3752         reg = FDI_RX_CTL(pipe);
3753         temp = I915_READ(reg);
3754         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3755         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3756         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3757         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3758
3759         POSTING_READ(reg);
3760         udelay(200);
3761
3762         /* Switch from Rawclk to PCDclk */
3763         temp = I915_READ(reg);
3764         I915_WRITE(reg, temp | FDI_PCDCLK);
3765
3766         POSTING_READ(reg);
3767         udelay(200);
3768
3769         /* Enable CPU FDI TX PLL, always on for Ironlake */
3770         reg = FDI_TX_CTL(pipe);
3771         temp = I915_READ(reg);
3772         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3773                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3774
3775                 POSTING_READ(reg);
3776                 udelay(100);
3777         }
3778 }
3779
3780 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3781 {
3782         struct drm_device *dev = intel_crtc->base.dev;
3783         struct drm_i915_private *dev_priv = dev->dev_private;
3784         int pipe = intel_crtc->pipe;
3785         u32 reg, temp;
3786
3787         /* Switch from PCDclk to Rawclk */
3788         reg = FDI_RX_CTL(pipe);
3789         temp = I915_READ(reg);
3790         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3791
3792         /* Disable CPU FDI TX PLL */
3793         reg = FDI_TX_CTL(pipe);
3794         temp = I915_READ(reg);
3795         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3796
3797         POSTING_READ(reg);
3798         udelay(100);
3799
3800         reg = FDI_RX_CTL(pipe);
3801         temp = I915_READ(reg);
3802         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3803
3804         /* Wait for the clocks to turn off. */
3805         POSTING_READ(reg);
3806         udelay(100);
3807 }
3808
3809 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3810 {
3811         struct drm_device *dev = crtc->dev;
3812         struct drm_i915_private *dev_priv = dev->dev_private;
3813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814         int pipe = intel_crtc->pipe;
3815         u32 reg, temp;
3816
3817         /* disable CPU FDI tx and PCH FDI rx */
3818         reg = FDI_TX_CTL(pipe);
3819         temp = I915_READ(reg);
3820         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3821         POSTING_READ(reg);
3822
3823         reg = FDI_RX_CTL(pipe);
3824         temp = I915_READ(reg);
3825         temp &= ~(0x7 << 16);
3826         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3827         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3828
3829         POSTING_READ(reg);
3830         udelay(100);
3831
3832         /* Ironlake workaround, disable clock pointer after downing FDI */
3833         if (HAS_PCH_IBX(dev))
3834                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3835
3836         /* still set train pattern 1 */
3837         reg = FDI_TX_CTL(pipe);
3838         temp = I915_READ(reg);
3839         temp &= ~FDI_LINK_TRAIN_NONE;
3840         temp |= FDI_LINK_TRAIN_PATTERN_1;
3841         I915_WRITE(reg, temp);
3842
3843         reg = FDI_RX_CTL(pipe);
3844         temp = I915_READ(reg);
3845         if (HAS_PCH_CPT(dev)) {
3846                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3847                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3848         } else {
3849                 temp &= ~FDI_LINK_TRAIN_NONE;
3850                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3851         }
3852         /* BPC in FDI rx is consistent with that in PIPECONF */
3853         temp &= ~(0x07 << 16);
3854         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3855         I915_WRITE(reg, temp);
3856
3857         POSTING_READ(reg);
3858         udelay(100);
3859 }
3860
3861 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3862 {
3863         struct intel_crtc *crtc;
3864
3865         /* Note that we don't need to be called with mode_config.lock here
3866          * as our list of CRTC objects is static for the lifetime of the
3867          * device and so cannot disappear as we iterate. Similarly, we can
3868          * happily treat the predicates as racy, atomic checks as userspace
3869          * cannot claim and pin a new fb without at least acquring the
3870          * struct_mutex and so serialising with us.
3871          */
3872         for_each_intel_crtc(dev, crtc) {
3873                 if (atomic_read(&crtc->unpin_work_count) == 0)
3874                         continue;
3875
3876                 if (crtc->unpin_work)
3877                         intel_wait_for_vblank(dev, crtc->pipe);
3878
3879                 return true;
3880         }
3881
3882         return false;
3883 }
3884
3885 static void page_flip_completed(struct intel_crtc *intel_crtc)
3886 {
3887         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3888         struct intel_unpin_work *work = intel_crtc->unpin_work;
3889
3890         /* ensure that the unpin work is consistent wrt ->pending. */
3891         smp_rmb();
3892         intel_crtc->unpin_work = NULL;
3893
3894         if (work->event)
3895                 drm_send_vblank_event(intel_crtc->base.dev,
3896                                       intel_crtc->pipe,
3897                                       work->event);
3898
3899         drm_crtc_vblank_put(&intel_crtc->base);
3900
3901         wake_up_all(&dev_priv->pending_flip_queue);
3902         queue_work(dev_priv->wq, &work->work);
3903
3904         trace_i915_flip_complete(intel_crtc->plane,
3905                                  work->pending_flip_obj);
3906 }
3907
3908 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3909 {
3910         struct drm_device *dev = crtc->dev;
3911         struct drm_i915_private *dev_priv = dev->dev_private;
3912
3913         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3914         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3915                                        !intel_crtc_has_pending_flip(crtc),
3916                                        60*HZ) == 0)) {
3917                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3918
3919                 spin_lock_irq(&dev->event_lock);
3920                 if (intel_crtc->unpin_work) {
3921                         WARN_ONCE(1, "Removing stuck page flip\n");
3922                         page_flip_completed(intel_crtc);
3923                 }
3924                 spin_unlock_irq(&dev->event_lock);
3925         }
3926
3927         if (crtc->primary->fb) {
3928                 mutex_lock(&dev->struct_mutex);
3929                 intel_finish_fb(crtc->primary->fb);
3930                 mutex_unlock(&dev->struct_mutex);
3931         }
3932 }
3933
3934 /* Program iCLKIP clock to the desired frequency */
3935 static void lpt_program_iclkip(struct drm_crtc *crtc)
3936 {
3937         struct drm_device *dev = crtc->dev;
3938         struct drm_i915_private *dev_priv = dev->dev_private;
3939         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3940         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3941         u32 temp;
3942
3943         mutex_lock(&dev_priv->sb_lock);
3944
3945         /* It is necessary to ungate the pixclk gate prior to programming
3946          * the divisors, and gate it back when it is done.
3947          */
3948         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3949
3950         /* Disable SSCCTL */
3951         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3952                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3953                                 SBI_SSCCTL_DISABLE,
3954                         SBI_ICLK);
3955
3956         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3957         if (clock == 20000) {
3958                 auxdiv = 1;
3959                 divsel = 0x41;
3960                 phaseinc = 0x20;
3961         } else {
3962                 /* The iCLK virtual clock root frequency is in MHz,
3963                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3964                  * divisors, it is necessary to divide one by another, so we
3965                  * convert the virtual clock precision to KHz here for higher
3966                  * precision.
3967                  */
3968                 u32 iclk_virtual_root_freq = 172800 * 1000;
3969                 u32 iclk_pi_range = 64;
3970                 u32 desired_divisor, msb_divisor_value, pi_value;
3971
3972                 desired_divisor = (iclk_virtual_root_freq / clock);
3973                 msb_divisor_value = desired_divisor / iclk_pi_range;
3974                 pi_value = desired_divisor % iclk_pi_range;
3975
3976                 auxdiv = 0;
3977                 divsel = msb_divisor_value - 2;
3978                 phaseinc = pi_value;
3979         }
3980
3981         /* This should not happen with any sane values */
3982         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3983                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3984         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3985                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3986
3987         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3988                         clock,
3989                         auxdiv,
3990                         divsel,
3991                         phasedir,
3992                         phaseinc);
3993
3994         /* Program SSCDIVINTPHASE6 */
3995         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3996         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3997         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3998         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3999         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4000         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4001         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4002         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4003
4004         /* Program SSCAUXDIV */
4005         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4006         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4007         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4008         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4009
4010         /* Enable modulator and associated divider */
4011         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4012         temp &= ~SBI_SSCCTL_DISABLE;
4013         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4014
4015         /* Wait for initialization time */
4016         udelay(24);
4017
4018         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4019
4020         mutex_unlock(&dev_priv->sb_lock);
4021 }
4022
4023 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4024                                                 enum pipe pch_transcoder)
4025 {
4026         struct drm_device *dev = crtc->base.dev;
4027         struct drm_i915_private *dev_priv = dev->dev_private;
4028         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4029
4030         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4031                    I915_READ(HTOTAL(cpu_transcoder)));
4032         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4033                    I915_READ(HBLANK(cpu_transcoder)));
4034         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4035                    I915_READ(HSYNC(cpu_transcoder)));
4036
4037         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4038                    I915_READ(VTOTAL(cpu_transcoder)));
4039         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4040                    I915_READ(VBLANK(cpu_transcoder)));
4041         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4042                    I915_READ(VSYNC(cpu_transcoder)));
4043         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4044                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4045 }
4046
4047 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4048 {
4049         struct drm_i915_private *dev_priv = dev->dev_private;
4050         uint32_t temp;
4051
4052         temp = I915_READ(SOUTH_CHICKEN1);
4053         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4054                 return;
4055
4056         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4057         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4058
4059         temp &= ~FDI_BC_BIFURCATION_SELECT;
4060         if (enable)
4061                 temp |= FDI_BC_BIFURCATION_SELECT;
4062
4063         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4064         I915_WRITE(SOUTH_CHICKEN1, temp);
4065         POSTING_READ(SOUTH_CHICKEN1);
4066 }
4067
4068 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4069 {
4070         struct drm_device *dev = intel_crtc->base.dev;
4071
4072         switch (intel_crtc->pipe) {
4073         case PIPE_A:
4074                 break;
4075         case PIPE_B:
4076                 if (intel_crtc->config->fdi_lanes > 2)
4077                         cpt_set_fdi_bc_bifurcation(dev, false);
4078                 else
4079                         cpt_set_fdi_bc_bifurcation(dev, true);
4080
4081                 break;
4082         case PIPE_C:
4083                 cpt_set_fdi_bc_bifurcation(dev, true);
4084
4085                 break;
4086         default:
4087                 BUG();
4088         }
4089 }
4090
4091 /*
4092  * Enable PCH resources required for PCH ports:
4093  *   - PCH PLLs
4094  *   - FDI training & RX/TX
4095  *   - update transcoder timings
4096  *   - DP transcoding bits
4097  *   - transcoder
4098  */
4099 static void ironlake_pch_enable(struct drm_crtc *crtc)
4100 {
4101         struct drm_device *dev = crtc->dev;
4102         struct drm_i915_private *dev_priv = dev->dev_private;
4103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104         int pipe = intel_crtc->pipe;
4105         u32 reg, temp;
4106
4107         assert_pch_transcoder_disabled(dev_priv, pipe);
4108
4109         if (IS_IVYBRIDGE(dev))
4110                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4111
4112         /* Write the TU size bits before fdi link training, so that error
4113          * detection works. */
4114         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4115                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4116
4117         /* For PCH output, training FDI link */
4118         dev_priv->display.fdi_link_train(crtc);
4119
4120         /* We need to program the right clock selection before writing the pixel
4121          * mutliplier into the DPLL. */
4122         if (HAS_PCH_CPT(dev)) {
4123                 u32 sel;
4124
4125                 temp = I915_READ(PCH_DPLL_SEL);
4126                 temp |= TRANS_DPLL_ENABLE(pipe);
4127                 sel = TRANS_DPLLB_SEL(pipe);
4128                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4129                         temp |= sel;
4130                 else
4131                         temp &= ~sel;
4132                 I915_WRITE(PCH_DPLL_SEL, temp);
4133         }
4134
4135         /* XXX: pch pll's can be enabled any time before we enable the PCH
4136          * transcoder, and we actually should do this to not upset any PCH
4137          * transcoder that already use the clock when we share it.
4138          *
4139          * Note that enable_shared_dpll tries to do the right thing, but
4140          * get_shared_dpll unconditionally resets the pll - we need that to have
4141          * the right LVDS enable sequence. */
4142         intel_enable_shared_dpll(intel_crtc);
4143
4144         /* set transcoder timing, panel must allow it */
4145         assert_panel_unlocked(dev_priv, pipe);
4146         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4147
4148         intel_fdi_normal_train(crtc);
4149
4150         /* For PCH DP, enable TRANS_DP_CTL */
4151         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4152                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4153                 reg = TRANS_DP_CTL(pipe);
4154                 temp = I915_READ(reg);
4155                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4156                           TRANS_DP_SYNC_MASK |
4157                           TRANS_DP_BPC_MASK);
4158                 temp |= TRANS_DP_OUTPUT_ENABLE;
4159                 temp |= bpc << 9; /* same format but at 11:9 */
4160
4161                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4162                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4163                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4164                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4165
4166                 switch (intel_trans_dp_port_sel(crtc)) {
4167                 case PCH_DP_B:
4168                         temp |= TRANS_DP_PORT_SEL_B;
4169                         break;
4170                 case PCH_DP_C:
4171                         temp |= TRANS_DP_PORT_SEL_C;
4172                         break;
4173                 case PCH_DP_D:
4174                         temp |= TRANS_DP_PORT_SEL_D;
4175                         break;
4176                 default:
4177                         BUG();
4178                 }
4179
4180                 I915_WRITE(reg, temp);
4181         }
4182
4183         ironlake_enable_pch_transcoder(dev_priv, pipe);
4184 }
4185
4186 static void lpt_pch_enable(struct drm_crtc *crtc)
4187 {
4188         struct drm_device *dev = crtc->dev;
4189         struct drm_i915_private *dev_priv = dev->dev_private;
4190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4191         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4192
4193         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4194
4195         lpt_program_iclkip(crtc);
4196
4197         /* Set transcoder timing. */
4198         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4199
4200         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4201 }
4202
4203 void intel_put_shared_dpll(struct intel_crtc *crtc)
4204 {
4205         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4206
4207         if (pll == NULL)
4208                 return;
4209
4210         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4211                 WARN(1, "bad %s crtc mask\n", pll->name);
4212                 return;
4213         }
4214
4215         pll->config.crtc_mask &= ~(1 << crtc->pipe);
4216         if (pll->config.crtc_mask == 0) {
4217                 WARN_ON(pll->on);
4218                 WARN_ON(pll->active);
4219         }
4220
4221         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4222 }
4223
4224 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4225                                                 struct intel_crtc_state *crtc_state)
4226 {
4227         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4228         struct intel_shared_dpll *pll;
4229         enum intel_dpll_id i;
4230
4231         if (HAS_PCH_IBX(dev_priv->dev)) {
4232                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4233                 i = (enum intel_dpll_id) crtc->pipe;
4234                 pll = &dev_priv->shared_dplls[i];
4235
4236                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4237                               crtc->base.base.id, pll->name);
4238
4239                 WARN_ON(pll->new_config->crtc_mask);
4240
4241                 goto found;
4242         }
4243
4244         if (IS_BROXTON(dev_priv->dev)) {
4245                 /* PLL is attached to port in bxt */
4246                 struct intel_encoder *encoder;
4247                 struct intel_digital_port *intel_dig_port;
4248
4249                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4250                 if (WARN_ON(!encoder))
4251                         return NULL;
4252
4253                 intel_dig_port = enc_to_dig_port(&encoder->base);
4254                 /* 1:1 mapping between ports and PLLs */
4255                 i = (enum intel_dpll_id)intel_dig_port->port;
4256                 pll = &dev_priv->shared_dplls[i];
4257                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4258                         crtc->base.base.id, pll->name);
4259                 WARN_ON(pll->new_config->crtc_mask);
4260
4261                 goto found;
4262         }
4263
4264         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4265                 pll = &dev_priv->shared_dplls[i];
4266
4267                 /* Only want to check enabled timings first */
4268                 if (pll->new_config->crtc_mask == 0)
4269                         continue;
4270
4271                 if (memcmp(&crtc_state->dpll_hw_state,
4272                            &pll->new_config->hw_state,
4273                            sizeof(pll->new_config->hw_state)) == 0) {
4274                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4275                                       crtc->base.base.id, pll->name,
4276                                       pll->new_config->crtc_mask,
4277                                       pll->active);
4278                         goto found;
4279                 }
4280         }
4281
4282         /* Ok no matching timings, maybe there's a free one? */
4283         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4284                 pll = &dev_priv->shared_dplls[i];
4285                 if (pll->new_config->crtc_mask == 0) {
4286                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4287                                       crtc->base.base.id, pll->name);
4288                         goto found;
4289                 }
4290         }
4291
4292         return NULL;
4293
4294 found:
4295         if (pll->new_config->crtc_mask == 0)
4296                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4297
4298         crtc_state->shared_dpll = i;
4299         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4300                          pipe_name(crtc->pipe));
4301
4302         pll->new_config->crtc_mask |= 1 << crtc->pipe;
4303
4304         return pll;
4305 }
4306
4307 /**
4308  * intel_shared_dpll_start_config - start a new PLL staged config
4309  * @dev_priv: DRM device
4310  * @clear_pipes: mask of pipes that will have their PLLs freed
4311  *
4312  * Starts a new PLL staged config, copying the current config but
4313  * releasing the references of pipes specified in clear_pipes.
4314  */
4315 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4316                                           unsigned clear_pipes)
4317 {
4318         struct intel_shared_dpll *pll;
4319         enum intel_dpll_id i;
4320
4321         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4322                 pll = &dev_priv->shared_dplls[i];
4323
4324                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4325                                           GFP_KERNEL);
4326                 if (!pll->new_config)
4327                         goto cleanup;
4328
4329                 pll->new_config->crtc_mask &= ~clear_pipes;
4330         }
4331
4332         return 0;
4333
4334 cleanup:
4335         while (--i >= 0) {
4336                 pll = &dev_priv->shared_dplls[i];
4337                 kfree(pll->new_config);
4338                 pll->new_config = NULL;
4339         }
4340
4341         return -ENOMEM;
4342 }
4343
4344 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4345 {
4346         struct intel_shared_dpll *pll;
4347         enum intel_dpll_id i;
4348
4349         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4350                 pll = &dev_priv->shared_dplls[i];
4351
4352                 WARN_ON(pll->new_config == &pll->config);
4353
4354                 pll->config = *pll->new_config;
4355                 kfree(pll->new_config);
4356                 pll->new_config = NULL;
4357         }
4358 }
4359
4360 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4361 {
4362         struct intel_shared_dpll *pll;
4363         enum intel_dpll_id i;
4364
4365         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4366                 pll = &dev_priv->shared_dplls[i];
4367
4368                 WARN_ON(pll->new_config == &pll->config);
4369
4370                 kfree(pll->new_config);
4371                 pll->new_config = NULL;
4372         }
4373 }
4374
4375 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4376 {
4377         struct drm_i915_private *dev_priv = dev->dev_private;
4378         int dslreg = PIPEDSL(pipe);
4379         u32 temp;
4380
4381         temp = I915_READ(dslreg);
4382         udelay(500);
4383         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4384                 if (wait_for(I915_READ(dslreg) != temp, 5))
4385                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4386         }
4387 }
4388
4389 /**
4390  * skl_update_scaler_users - Stages update to crtc's scaler state
4391  * @intel_crtc: crtc
4392  * @crtc_state: crtc_state
4393  * @plane: plane (NULL indicates crtc is requesting update)
4394  * @plane_state: plane's state
4395  * @force_detach: request unconditional detachment of scaler
4396  *
4397  * This function updates scaler state for requested plane or crtc.
4398  * To request scaler usage update for a plane, caller shall pass plane pointer.
4399  * To request scaler usage update for crtc, caller shall pass plane pointer
4400  * as NULL.
4401  *
4402  * Return
4403  *     0 - scaler_usage updated successfully
4404  *    error - requested scaling cannot be supported or other error condition
4405  */
4406 int
4407 skl_update_scaler_users(
4408         struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4409         struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4410         int force_detach)
4411 {
4412         int need_scaling;
4413         int idx;
4414         int src_w, src_h, dst_w, dst_h;
4415         int *scaler_id;
4416         struct drm_framebuffer *fb;
4417         struct intel_crtc_scaler_state *scaler_state;
4418         unsigned int rotation;
4419
4420         if (!intel_crtc || !crtc_state)
4421                 return 0;
4422
4423         scaler_state = &crtc_state->scaler_state;
4424
4425         idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4426         fb = intel_plane ? plane_state->base.fb : NULL;
4427
4428         if (intel_plane) {
4429                 src_w = drm_rect_width(&plane_state->src) >> 16;
4430                 src_h = drm_rect_height(&plane_state->src) >> 16;
4431                 dst_w = drm_rect_width(&plane_state->dst);
4432                 dst_h = drm_rect_height(&plane_state->dst);
4433                 scaler_id = &plane_state->scaler_id;
4434                 rotation = plane_state->base.rotation;
4435         } else {
4436                 struct drm_display_mode *adjusted_mode =
4437                         &crtc_state->base.adjusted_mode;
4438                 src_w = crtc_state->pipe_src_w;
4439                 src_h = crtc_state->pipe_src_h;
4440                 dst_w = adjusted_mode->hdisplay;
4441                 dst_h = adjusted_mode->vdisplay;
4442                 scaler_id = &scaler_state->scaler_id;
4443                 rotation = DRM_ROTATE_0;
4444         }
4445
4446         need_scaling = intel_rotation_90_or_270(rotation) ?
4447                 (src_h != dst_w || src_w != dst_h):
4448                 (src_w != dst_w || src_h != dst_h);
4449
4450         /*
4451          * if plane is being disabled or scaler is no more required or force detach
4452          *  - free scaler binded to this plane/crtc
4453          *  - in order to do this, update crtc->scaler_usage
4454          *
4455          * Here scaler state in crtc_state is set free so that
4456          * scaler can be assigned to other user. Actual register
4457          * update to free the scaler is done in plane/panel-fit programming.
4458          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4459          */
4460         if (force_detach || !need_scaling || (intel_plane &&
4461                 (!fb || !plane_state->visible))) {
4462                 if (*scaler_id >= 0) {
4463                         scaler_state->scaler_users &= ~(1 << idx);
4464                         scaler_state->scalers[*scaler_id].in_use = 0;
4465
4466                         DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4467                                 "crtc_state = %p scaler_users = 0x%x\n",
4468                                 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4469                                 intel_plane ? intel_plane->base.base.id :
4470                                 intel_crtc->base.base.id, crtc_state,
4471                                 scaler_state->scaler_users);
4472                         *scaler_id = -1;
4473                 }
4474                 return 0;
4475         }
4476
4477         /* range checks */
4478         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4479                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4480
4481                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4482                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4483                 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4484                         "size is out of scaler range\n",
4485                         intel_plane ? "PLANE" : "CRTC",
4486                         intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4487                         intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4488                 return -EINVAL;
4489         }
4490
4491         /* check colorkey */
4492         if (WARN_ON(intel_plane &&
4493                 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4494                 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4495                         intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
4496                 return -EINVAL;
4497         }
4498
4499         /* Check src format */
4500         if (intel_plane) {
4501                 switch (fb->pixel_format) {
4502                 case DRM_FORMAT_RGB565:
4503                 case DRM_FORMAT_XBGR8888:
4504                 case DRM_FORMAT_XRGB8888:
4505                 case DRM_FORMAT_ABGR8888:
4506                 case DRM_FORMAT_ARGB8888:
4507                 case DRM_FORMAT_XRGB2101010:
4508                 case DRM_FORMAT_XBGR2101010:
4509                 case DRM_FORMAT_YUYV:
4510                 case DRM_FORMAT_YVYU:
4511                 case DRM_FORMAT_UYVY:
4512                 case DRM_FORMAT_VYUY:
4513                         break;
4514                 default:
4515                         DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4516                                 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4517                         return -EINVAL;
4518                 }
4519         }
4520
4521         /* mark this plane as a scaler user in crtc_state */
4522         scaler_state->scaler_users |= (1 << idx);
4523         DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4524                 "crtc_state = %p scaler_users = 0x%x\n",
4525                 intel_plane ? "PLANE" : "CRTC",
4526                 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4527                 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4528         return 0;
4529 }
4530
4531 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4532 {
4533         struct drm_device *dev = crtc->base.dev;
4534         struct drm_i915_private *dev_priv = dev->dev_private;
4535         int pipe = crtc->pipe;
4536         struct intel_crtc_scaler_state *scaler_state =
4537                 &crtc->config->scaler_state;
4538
4539         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4540
4541         /* To update pfit, first update scaler state */
4542         skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4543         intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4544         skl_detach_scalers(crtc);
4545         if (!enable)
4546                 return;
4547
4548         if (crtc->config->pch_pfit.enabled) {
4549                 int id;
4550
4551                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4552                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4553                         return;
4554                 }
4555
4556                 id = scaler_state->scaler_id;
4557                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4558                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4559                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4560                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4561
4562                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4563         }
4564 }
4565
4566 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4567 {
4568         struct drm_device *dev = crtc->base.dev;
4569         struct drm_i915_private *dev_priv = dev->dev_private;
4570         int pipe = crtc->pipe;
4571
4572         if (crtc->config->pch_pfit.enabled) {
4573                 /* Force use of hard-coded filter coefficients
4574                  * as some pre-programmed values are broken,
4575                  * e.g. x201.
4576                  */
4577                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4578                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4579                                                  PF_PIPE_SEL_IVB(pipe));
4580                 else
4581                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4582                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4583                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4584         }
4585 }
4586
4587 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4588 {
4589         struct drm_device *dev = crtc->dev;
4590         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4591         struct drm_plane *plane;
4592         struct intel_plane *intel_plane;
4593
4594         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4595                 intel_plane = to_intel_plane(plane);
4596                 if (intel_plane->pipe == pipe)
4597                         intel_plane_restore(&intel_plane->base);
4598         }
4599 }
4600
4601 void hsw_enable_ips(struct intel_crtc *crtc)
4602 {
4603         struct drm_device *dev = crtc->base.dev;
4604         struct drm_i915_private *dev_priv = dev->dev_private;
4605
4606         if (!crtc->config->ips_enabled)
4607                 return;
4608
4609         /* We can only enable IPS after we enable a plane and wait for a vblank */
4610         intel_wait_for_vblank(dev, crtc->pipe);
4611
4612         assert_plane_enabled(dev_priv, crtc->plane);
4613         if (IS_BROADWELL(dev)) {
4614                 mutex_lock(&dev_priv->rps.hw_lock);
4615                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4616                 mutex_unlock(&dev_priv->rps.hw_lock);
4617                 /* Quoting Art Runyan: "its not safe to expect any particular
4618                  * value in IPS_CTL bit 31 after enabling IPS through the
4619                  * mailbox." Moreover, the mailbox may return a bogus state,
4620                  * so we need to just enable it and continue on.
4621                  */
4622         } else {
4623                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4624                 /* The bit only becomes 1 in the next vblank, so this wait here
4625                  * is essentially intel_wait_for_vblank. If we don't have this
4626                  * and don't wait for vblanks until the end of crtc_enable, then
4627                  * the HW state readout code will complain that the expected
4628                  * IPS_CTL value is not the one we read. */
4629                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4630                         DRM_ERROR("Timed out waiting for IPS enable\n");
4631         }
4632 }
4633
4634 void hsw_disable_ips(struct intel_crtc *crtc)
4635 {
4636         struct drm_device *dev = crtc->base.dev;
4637         struct drm_i915_private *dev_priv = dev->dev_private;
4638
4639         if (!crtc->config->ips_enabled)
4640                 return;
4641
4642         assert_plane_enabled(dev_priv, crtc->plane);
4643         if (IS_BROADWELL(dev)) {
4644                 mutex_lock(&dev_priv->rps.hw_lock);
4645                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4646                 mutex_unlock(&dev_priv->rps.hw_lock);
4647                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4648                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4649                         DRM_ERROR("Timed out waiting for IPS disable\n");
4650         } else {
4651                 I915_WRITE(IPS_CTL, 0);
4652                 POSTING_READ(IPS_CTL);
4653         }
4654
4655         /* We need to wait for a vblank before we can disable the plane. */
4656         intel_wait_for_vblank(dev, crtc->pipe);
4657 }
4658
4659 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4660 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4661 {
4662         struct drm_device *dev = crtc->dev;
4663         struct drm_i915_private *dev_priv = dev->dev_private;
4664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4665         enum pipe pipe = intel_crtc->pipe;
4666         int palreg = PALETTE(pipe);
4667         int i;
4668         bool reenable_ips = false;
4669
4670         /* The clocks have to be on to load the palette. */
4671         if (!crtc->state->enable || !intel_crtc->active)
4672                 return;
4673
4674         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4675                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4676                         assert_dsi_pll_enabled(dev_priv);
4677                 else
4678                         assert_pll_enabled(dev_priv, pipe);
4679         }
4680
4681         /* use legacy palette for Ironlake */
4682         if (!HAS_GMCH_DISPLAY(dev))
4683                 palreg = LGC_PALETTE(pipe);
4684
4685         /* Workaround : Do not read or write the pipe palette/gamma data while
4686          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4687          */
4688         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4689             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4690              GAMMA_MODE_MODE_SPLIT)) {
4691                 hsw_disable_ips(intel_crtc);
4692                 reenable_ips = true;
4693         }
4694
4695         for (i = 0; i < 256; i++) {
4696                 I915_WRITE(palreg + 4 * i,
4697                            (intel_crtc->lut_r[i] << 16) |
4698                            (intel_crtc->lut_g[i] << 8) |
4699                            intel_crtc->lut_b[i]);
4700         }
4701
4702         if (reenable_ips)
4703                 hsw_enable_ips(intel_crtc);
4704 }
4705
4706 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4707 {
4708         if (intel_crtc->overlay) {
4709                 struct drm_device *dev = intel_crtc->base.dev;
4710                 struct drm_i915_private *dev_priv = dev->dev_private;
4711
4712                 mutex_lock(&dev->struct_mutex);
4713                 dev_priv->mm.interruptible = false;
4714                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4715                 dev_priv->mm.interruptible = true;
4716                 mutex_unlock(&dev->struct_mutex);
4717         }
4718
4719         /* Let userspace switch the overlay on again. In most cases userspace
4720          * has to recompute where to put it anyway.
4721          */
4722 }
4723
4724 /**
4725  * intel_post_enable_primary - Perform operations after enabling primary plane
4726  * @crtc: the CRTC whose primary plane was just enabled
4727  *
4728  * Performs potentially sleeping operations that must be done after the primary
4729  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4730  * called due to an explicit primary plane update, or due to an implicit
4731  * re-enable that is caused when a sprite plane is updated to no longer
4732  * completely hide the primary plane.
4733  */
4734 static void
4735 intel_post_enable_primary(struct drm_crtc *crtc)
4736 {
4737         struct drm_device *dev = crtc->dev;
4738         struct drm_i915_private *dev_priv = dev->dev_private;
4739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4740         int pipe = intel_crtc->pipe;
4741
4742         /*
4743          * BDW signals flip done immediately if the plane
4744          * is disabled, even if the plane enable is already
4745          * armed to occur at the next vblank :(
4746          */
4747         if (IS_BROADWELL(dev))
4748                 intel_wait_for_vblank(dev, pipe);
4749
4750         /*
4751          * FIXME IPS should be fine as long as one plane is
4752          * enabled, but in practice it seems to have problems
4753          * when going from primary only to sprite only and vice
4754          * versa.
4755          */
4756         hsw_enable_ips(intel_crtc);
4757
4758         mutex_lock(&dev->struct_mutex);
4759         intel_fbc_update(dev);
4760         mutex_unlock(&dev->struct_mutex);
4761
4762         /*
4763          * Gen2 reports pipe underruns whenever all planes are disabled.
4764          * So don't enable underrun reporting before at least some planes
4765          * are enabled.
4766          * FIXME: Need to fix the logic to work when we turn off all planes
4767          * but leave the pipe running.
4768          */
4769         if (IS_GEN2(dev))
4770                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4771
4772         /* Underruns don't raise interrupts, so check manually. */
4773         if (HAS_GMCH_DISPLAY(dev))
4774                 i9xx_check_fifo_underruns(dev_priv);
4775 }
4776
4777 /**
4778  * intel_pre_disable_primary - Perform operations before disabling primary plane
4779  * @crtc: the CRTC whose primary plane is to be disabled
4780  *
4781  * Performs potentially sleeping operations that must be done before the
4782  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4783  * be called due to an explicit primary plane update, or due to an implicit
4784  * disable that is caused when a sprite plane completely hides the primary
4785  * plane.
4786  */
4787 static void
4788 intel_pre_disable_primary(struct drm_crtc *crtc)
4789 {
4790         struct drm_device *dev = crtc->dev;
4791         struct drm_i915_private *dev_priv = dev->dev_private;
4792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4793         int pipe = intel_crtc->pipe;
4794
4795         /*
4796          * Gen2 reports pipe underruns whenever all planes are disabled.
4797          * So diasble underrun reporting before all the planes get disabled.
4798          * FIXME: Need to fix the logic to work when we turn off all planes
4799          * but leave the pipe running.
4800          */
4801         if (IS_GEN2(dev))
4802                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4803
4804         /*
4805          * Vblank time updates from the shadow to live plane control register
4806          * are blocked if the memory self-refresh mode is active at that
4807          * moment. So to make sure the plane gets truly disabled, disable
4808          * first the self-refresh mode. The self-refresh enable bit in turn
4809          * will be checked/applied by the HW only at the next frame start
4810          * event which is after the vblank start event, so we need to have a
4811          * wait-for-vblank between disabling the plane and the pipe.
4812          */
4813         if (HAS_GMCH_DISPLAY(dev))
4814                 intel_set_memory_cxsr(dev_priv, false);
4815
4816         mutex_lock(&dev->struct_mutex);
4817         if (dev_priv->fbc.crtc == intel_crtc)
4818                 intel_fbc_disable(dev);
4819         mutex_unlock(&dev->struct_mutex);
4820
4821         /*
4822          * FIXME IPS should be fine as long as one plane is
4823          * enabled, but in practice it seems to have problems
4824          * when going from primary only to sprite only and vice
4825          * versa.
4826          */
4827         hsw_disable_ips(intel_crtc);
4828 }
4829
4830 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4831 {
4832         struct drm_device *dev = crtc->dev;
4833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4834         int pipe = intel_crtc->pipe;
4835
4836         intel_enable_primary_hw_plane(crtc->primary, crtc);
4837         intel_enable_sprite_planes(crtc);
4838         intel_crtc_update_cursor(crtc, true);
4839
4840         intel_post_enable_primary(crtc);
4841
4842         /*
4843          * FIXME: Once we grow proper nuclear flip support out of this we need
4844          * to compute the mask of flip planes precisely. For the time being
4845          * consider this a flip to a NULL plane.
4846          */
4847         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4848 }
4849
4850 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4851 {
4852         struct drm_device *dev = crtc->dev;
4853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854         struct intel_plane *intel_plane;
4855         int pipe = intel_crtc->pipe;
4856
4857         if (!intel_crtc->active)
4858                 return;
4859
4860         intel_crtc_wait_for_pending_flips(crtc);
4861
4862         intel_pre_disable_primary(crtc);
4863
4864         intel_crtc_dpms_overlay_disable(intel_crtc);
4865         for_each_intel_plane(dev, intel_plane) {
4866                 if (intel_plane->pipe == pipe) {
4867                         struct drm_crtc *from = intel_plane->base.crtc;
4868
4869                         intel_plane->disable_plane(&intel_plane->base,
4870                                                    from ?: crtc, true);
4871                 }
4872         }
4873
4874         /*
4875          * FIXME: Once we grow proper nuclear flip support out of this we need
4876          * to compute the mask of flip planes precisely. For the time being
4877          * consider this a flip to a NULL plane.
4878          */
4879         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4880 }
4881
4882 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4883 {
4884         struct drm_device *dev = crtc->dev;
4885         struct drm_i915_private *dev_priv = dev->dev_private;
4886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4887         struct intel_encoder *encoder;
4888         int pipe = intel_crtc->pipe;
4889
4890         WARN_ON(!crtc->state->enable);
4891
4892         if (intel_crtc->active)
4893                 return;
4894
4895         if (intel_crtc->config->has_pch_encoder)
4896                 intel_prepare_shared_dpll(intel_crtc);
4897
4898         if (intel_crtc->config->has_dp_encoder)
4899                 intel_dp_set_m_n(intel_crtc, M1_N1);
4900
4901         intel_set_pipe_timings(intel_crtc);
4902
4903         if (intel_crtc->config->has_pch_encoder) {
4904                 intel_cpu_transcoder_set_m_n(intel_crtc,
4905                                      &intel_crtc->config->fdi_m_n, NULL);
4906         }
4907
4908         ironlake_set_pipeconf(crtc);
4909
4910         intel_crtc->active = true;
4911
4912         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4913         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4914
4915         for_each_encoder_on_crtc(dev, crtc, encoder)
4916                 if (encoder->pre_enable)
4917                         encoder->pre_enable(encoder);
4918
4919         if (intel_crtc->config->has_pch_encoder) {
4920                 /* Note: FDI PLL enabling _must_ be done before we enable the
4921                  * cpu pipes, hence this is separate from all the other fdi/pch
4922                  * enabling. */
4923                 ironlake_fdi_pll_enable(intel_crtc);
4924         } else {
4925                 assert_fdi_tx_disabled(dev_priv, pipe);
4926                 assert_fdi_rx_disabled(dev_priv, pipe);
4927         }
4928
4929         ironlake_pfit_enable(intel_crtc);
4930
4931         /*
4932          * On ILK+ LUT must be loaded before the pipe is running but with
4933          * clocks enabled
4934          */
4935         intel_crtc_load_lut(crtc);
4936
4937         intel_update_watermarks(crtc);
4938         intel_enable_pipe(intel_crtc);
4939
4940         if (intel_crtc->config->has_pch_encoder)
4941                 ironlake_pch_enable(crtc);
4942
4943         assert_vblank_disabled(crtc);
4944         drm_crtc_vblank_on(crtc);
4945
4946         for_each_encoder_on_crtc(dev, crtc, encoder)
4947                 encoder->enable(encoder);
4948
4949         if (HAS_PCH_CPT(dev))
4950                 cpt_verify_modeset(dev, intel_crtc->pipe);
4951 }
4952
4953 /* IPS only exists on ULT machines and is tied to pipe A. */
4954 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4955 {
4956         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4957 }
4958
4959 /*
4960  * This implements the workaround described in the "notes" section of the mode
4961  * set sequence documentation. When going from no pipes or single pipe to
4962  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4963  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4964  */
4965 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4966 {
4967         struct drm_device *dev = crtc->base.dev;
4968         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4969
4970         /* We want to get the other_active_crtc only if there's only 1 other
4971          * active crtc. */
4972         for_each_intel_crtc(dev, crtc_it) {
4973                 if (!crtc_it->active || crtc_it == crtc)
4974                         continue;
4975
4976                 if (other_active_crtc)
4977                         return;
4978
4979                 other_active_crtc = crtc_it;
4980         }
4981         if (!other_active_crtc)
4982                 return;
4983
4984         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4985         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4986 }
4987
4988 static void haswell_crtc_enable(struct drm_crtc *crtc)
4989 {
4990         struct drm_device *dev = crtc->dev;
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4993         struct intel_encoder *encoder;
4994         int pipe = intel_crtc->pipe;
4995
4996         WARN_ON(!crtc->state->enable);
4997
4998         if (intel_crtc->active)
4999                 return;
5000
5001         if (intel_crtc_to_shared_dpll(intel_crtc))
5002                 intel_enable_shared_dpll(intel_crtc);
5003
5004         if (intel_crtc->config->has_dp_encoder)
5005                 intel_dp_set_m_n(intel_crtc, M1_N1);
5006
5007         intel_set_pipe_timings(intel_crtc);
5008
5009         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5010                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5011                            intel_crtc->config->pixel_multiplier - 1);
5012         }
5013
5014         if (intel_crtc->config->has_pch_encoder) {
5015                 intel_cpu_transcoder_set_m_n(intel_crtc,
5016                                      &intel_crtc->config->fdi_m_n, NULL);
5017         }
5018
5019         haswell_set_pipeconf(crtc);
5020
5021         intel_set_pipe_csc(crtc);
5022
5023         intel_crtc->active = true;
5024
5025         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5026         for_each_encoder_on_crtc(dev, crtc, encoder)
5027                 if (encoder->pre_enable)
5028                         encoder->pre_enable(encoder);
5029
5030         if (intel_crtc->config->has_pch_encoder) {
5031                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5032                                                       true);
5033                 dev_priv->display.fdi_link_train(crtc);
5034         }
5035
5036         intel_ddi_enable_pipe_clock(intel_crtc);
5037
5038         if (INTEL_INFO(dev)->gen == 9)
5039                 skylake_pfit_update(intel_crtc, 1);
5040         else if (INTEL_INFO(dev)->gen < 9)
5041                 ironlake_pfit_enable(intel_crtc);
5042         else
5043                 MISSING_CASE(INTEL_INFO(dev)->gen);
5044
5045         /*
5046          * On ILK+ LUT must be loaded before the pipe is running but with
5047          * clocks enabled
5048          */
5049         intel_crtc_load_lut(crtc);
5050
5051         intel_ddi_set_pipe_settings(crtc);
5052         intel_ddi_enable_transcoder_func(crtc);
5053
5054         intel_update_watermarks(crtc);
5055         intel_enable_pipe(intel_crtc);
5056
5057         if (intel_crtc->config->has_pch_encoder)
5058                 lpt_pch_enable(crtc);
5059
5060         if (intel_crtc->config->dp_encoder_is_mst)
5061                 intel_ddi_set_vc_payload_alloc(crtc, true);
5062
5063         assert_vblank_disabled(crtc);
5064         drm_crtc_vblank_on(crtc);
5065
5066         for_each_encoder_on_crtc(dev, crtc, encoder) {
5067                 encoder->enable(encoder);
5068                 intel_opregion_notify_encoder(encoder, true);
5069         }
5070
5071         /* If we change the relative order between pipe/planes enabling, we need
5072          * to change the workaround. */
5073         haswell_mode_set_planes_workaround(intel_crtc);
5074 }
5075
5076 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5077 {
5078         struct drm_device *dev = crtc->base.dev;
5079         struct drm_i915_private *dev_priv = dev->dev_private;
5080         int pipe = crtc->pipe;
5081
5082         /* To avoid upsetting the power well on haswell only disable the pfit if
5083          * it's in use. The hw state code will make sure we get this right. */
5084         if (crtc->config->pch_pfit.enabled) {
5085                 I915_WRITE(PF_CTL(pipe), 0);
5086                 I915_WRITE(PF_WIN_POS(pipe), 0);
5087                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5088         }
5089 }
5090
5091 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5092 {
5093         struct drm_device *dev = crtc->dev;
5094         struct drm_i915_private *dev_priv = dev->dev_private;
5095         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5096         struct intel_encoder *encoder;
5097         int pipe = intel_crtc->pipe;
5098         u32 reg, temp;
5099
5100         if (!intel_crtc->active)
5101                 return;
5102
5103         for_each_encoder_on_crtc(dev, crtc, encoder)
5104                 encoder->disable(encoder);
5105
5106         drm_crtc_vblank_off(crtc);
5107         assert_vblank_disabled(crtc);
5108
5109         if (intel_crtc->config->has_pch_encoder)
5110                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5111
5112         intel_disable_pipe(intel_crtc);
5113
5114         ironlake_pfit_disable(intel_crtc);
5115
5116         if (intel_crtc->config->has_pch_encoder)
5117                 ironlake_fdi_disable(crtc);
5118
5119         for_each_encoder_on_crtc(dev, crtc, encoder)
5120                 if (encoder->post_disable)
5121                         encoder->post_disable(encoder);
5122
5123         if (intel_crtc->config->has_pch_encoder) {
5124                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5125
5126                 if (HAS_PCH_CPT(dev)) {
5127                         /* disable TRANS_DP_CTL */
5128                         reg = TRANS_DP_CTL(pipe);
5129                         temp = I915_READ(reg);
5130                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5131                                   TRANS_DP_PORT_SEL_MASK);
5132                         temp |= TRANS_DP_PORT_SEL_NONE;
5133                         I915_WRITE(reg, temp);
5134
5135                         /* disable DPLL_SEL */
5136                         temp = I915_READ(PCH_DPLL_SEL);
5137                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5138                         I915_WRITE(PCH_DPLL_SEL, temp);
5139                 }
5140
5141                 /* disable PCH DPLL */
5142                 intel_disable_shared_dpll(intel_crtc);
5143
5144                 ironlake_fdi_pll_disable(intel_crtc);
5145         }
5146
5147         intel_crtc->active = false;
5148         intel_update_watermarks(crtc);
5149
5150         mutex_lock(&dev->struct_mutex);
5151         intel_fbc_update(dev);
5152         mutex_unlock(&dev->struct_mutex);
5153 }
5154
5155 static void haswell_crtc_disable(struct drm_crtc *crtc)
5156 {
5157         struct drm_device *dev = crtc->dev;
5158         struct drm_i915_private *dev_priv = dev->dev_private;
5159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5160         struct intel_encoder *encoder;
5161         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5162
5163         if (!intel_crtc->active)
5164                 return;
5165
5166         for_each_encoder_on_crtc(dev, crtc, encoder) {
5167                 intel_opregion_notify_encoder(encoder, false);
5168                 encoder->disable(encoder);
5169         }
5170
5171         drm_crtc_vblank_off(crtc);
5172         assert_vblank_disabled(crtc);
5173
5174         if (intel_crtc->config->has_pch_encoder)
5175                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5176                                                       false);
5177         intel_disable_pipe(intel_crtc);
5178
5179         if (intel_crtc->config->dp_encoder_is_mst)
5180                 intel_ddi_set_vc_payload_alloc(crtc, false);
5181
5182         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5183
5184         if (INTEL_INFO(dev)->gen == 9)
5185                 skylake_pfit_update(intel_crtc, 0);
5186         else if (INTEL_INFO(dev)->gen < 9)
5187                 ironlake_pfit_disable(intel_crtc);
5188         else
5189                 MISSING_CASE(INTEL_INFO(dev)->gen);
5190
5191         intel_ddi_disable_pipe_clock(intel_crtc);
5192
5193         if (intel_crtc->config->has_pch_encoder) {
5194                 lpt_disable_pch_transcoder(dev_priv);
5195                 intel_ddi_fdi_disable(crtc);
5196         }
5197
5198         for_each_encoder_on_crtc(dev, crtc, encoder)
5199                 if (encoder->post_disable)
5200                         encoder->post_disable(encoder);
5201
5202         intel_crtc->active = false;
5203         intel_update_watermarks(crtc);
5204
5205         mutex_lock(&dev->struct_mutex);
5206         intel_fbc_update(dev);
5207         mutex_unlock(&dev->struct_mutex);
5208
5209         if (intel_crtc_to_shared_dpll(intel_crtc))
5210                 intel_disable_shared_dpll(intel_crtc);
5211 }
5212
5213 static void ironlake_crtc_off(struct drm_crtc *crtc)
5214 {
5215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5216         intel_put_shared_dpll(intel_crtc);
5217 }
5218
5219
5220 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5221 {
5222         struct drm_device *dev = crtc->base.dev;
5223         struct drm_i915_private *dev_priv = dev->dev_private;
5224         struct intel_crtc_state *pipe_config = crtc->config;
5225
5226         if (!pipe_config->gmch_pfit.control)
5227                 return;
5228
5229         /*
5230          * The panel fitter should only be adjusted whilst the pipe is disabled,
5231          * according to register description and PRM.
5232          */
5233         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5234         assert_pipe_disabled(dev_priv, crtc->pipe);
5235
5236         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5237         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5238
5239         /* Border color in case we don't scale up to the full screen. Black by
5240          * default, change to something else for debugging. */
5241         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5242 }
5243
5244 static enum intel_display_power_domain port_to_power_domain(enum port port)
5245 {
5246         switch (port) {
5247         case PORT_A:
5248                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5249         case PORT_B:
5250                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5251         case PORT_C:
5252                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5253         case PORT_D:
5254                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5255         default:
5256                 WARN_ON_ONCE(1);
5257                 return POWER_DOMAIN_PORT_OTHER;
5258         }
5259 }
5260
5261 #define for_each_power_domain(domain, mask)                             \
5262         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5263                 if ((1 << (domain)) & (mask))
5264
5265 enum intel_display_power_domain
5266 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5267 {
5268         struct drm_device *dev = intel_encoder->base.dev;
5269         struct intel_digital_port *intel_dig_port;
5270
5271         switch (intel_encoder->type) {
5272         case INTEL_OUTPUT_UNKNOWN:
5273                 /* Only DDI platforms should ever use this output type */
5274                 WARN_ON_ONCE(!HAS_DDI(dev));
5275         case INTEL_OUTPUT_DISPLAYPORT:
5276         case INTEL_OUTPUT_HDMI:
5277         case INTEL_OUTPUT_EDP:
5278                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5279                 return port_to_power_domain(intel_dig_port->port);
5280         case INTEL_OUTPUT_DP_MST:
5281                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5282                 return port_to_power_domain(intel_dig_port->port);
5283         case INTEL_OUTPUT_ANALOG:
5284                 return POWER_DOMAIN_PORT_CRT;
5285         case INTEL_OUTPUT_DSI:
5286                 return POWER_DOMAIN_PORT_DSI;
5287         default:
5288                 return POWER_DOMAIN_PORT_OTHER;
5289         }
5290 }
5291
5292 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5293 {
5294         struct drm_device *dev = crtc->dev;
5295         struct intel_encoder *intel_encoder;
5296         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5297         enum pipe pipe = intel_crtc->pipe;
5298         unsigned long mask;
5299         enum transcoder transcoder;
5300
5301         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5302
5303         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5304         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5305         if (intel_crtc->config->pch_pfit.enabled ||
5306             intel_crtc->config->pch_pfit.force_thru)
5307                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5308
5309         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5310                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5311
5312         return mask;
5313 }
5314
5315 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5316 {
5317         struct drm_device *dev = state->dev;
5318         struct drm_i915_private *dev_priv = dev->dev_private;
5319         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5320         struct intel_crtc *crtc;
5321
5322         /*
5323          * First get all needed power domains, then put all unneeded, to avoid
5324          * any unnecessary toggling of the power wells.
5325          */
5326         for_each_intel_crtc(dev, crtc) {
5327                 enum intel_display_power_domain domain;
5328
5329                 if (!crtc->base.state->enable)
5330                         continue;
5331
5332                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5333
5334                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5335                         intel_display_power_get(dev_priv, domain);
5336         }
5337
5338         if (dev_priv->display.modeset_global_resources)
5339                 dev_priv->display.modeset_global_resources(state);
5340
5341         for_each_intel_crtc(dev, crtc) {
5342                 enum intel_display_power_domain domain;
5343
5344                 for_each_power_domain(domain, crtc->enabled_power_domains)
5345                         intel_display_power_put(dev_priv, domain);
5346
5347                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5348         }
5349
5350         intel_display_set_init_power(dev_priv, false);
5351 }
5352
5353 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5354 {
5355         struct drm_i915_private *dev_priv = dev->dev_private;
5356         uint32_t divider;
5357         uint32_t ratio;
5358         uint32_t current_freq;
5359         int ret;
5360
5361         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5362         switch (frequency) {
5363         case 144000:
5364                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5365                 ratio = BXT_DE_PLL_RATIO(60);
5366                 break;
5367         case 288000:
5368                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5369                 ratio = BXT_DE_PLL_RATIO(60);
5370                 break;
5371         case 384000:
5372                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5373                 ratio = BXT_DE_PLL_RATIO(60);
5374                 break;
5375         case 576000:
5376                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5377                 ratio = BXT_DE_PLL_RATIO(60);
5378                 break;
5379         case 624000:
5380                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5381                 ratio = BXT_DE_PLL_RATIO(65);
5382                 break;
5383         case 19200:
5384                 /*
5385                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5386                  * to suppress GCC warning.
5387                  */
5388                 ratio = 0;
5389                 divider = 0;
5390                 break;
5391         default:
5392                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5393
5394                 return;
5395         }
5396
5397         mutex_lock(&dev_priv->rps.hw_lock);
5398         /* Inform power controller of upcoming frequency change */
5399         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5400                                       0x80000000);
5401         mutex_unlock(&dev_priv->rps.hw_lock);
5402
5403         if (ret) {
5404                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5405                           ret, frequency);
5406                 return;
5407         }
5408
5409         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5410         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5411         current_freq = current_freq * 500 + 1000;
5412
5413         /*
5414          * DE PLL has to be disabled when
5415          * - setting to 19.2MHz (bypass, PLL isn't used)
5416          * - before setting to 624MHz (PLL needs toggling)
5417          * - before setting to any frequency from 624MHz (PLL needs toggling)
5418          */
5419         if (frequency == 19200 || frequency == 624000 ||
5420             current_freq == 624000) {
5421                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5422                 /* Timeout 200us */
5423                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5424                              1))
5425                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5426         }
5427
5428         if (frequency != 19200) {
5429                 uint32_t val;
5430
5431                 val = I915_READ(BXT_DE_PLL_CTL);
5432                 val &= ~BXT_DE_PLL_RATIO_MASK;
5433                 val |= ratio;
5434                 I915_WRITE(BXT_DE_PLL_CTL, val);
5435
5436                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5437                 /* Timeout 200us */
5438                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5439                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5440
5441                 val = I915_READ(CDCLK_CTL);
5442                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5443                 val |= divider;
5444                 /*
5445                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5446                  * enable otherwise.
5447                  */
5448                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5449                 if (frequency >= 500000)
5450                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5451
5452                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5453                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5454                 val |= (frequency - 1000) / 500;
5455                 I915_WRITE(CDCLK_CTL, val);
5456         }
5457
5458         mutex_lock(&dev_priv->rps.hw_lock);
5459         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5460                                       DIV_ROUND_UP(frequency, 25000));
5461         mutex_unlock(&dev_priv->rps.hw_lock);
5462
5463         if (ret) {
5464                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5465                           ret, frequency);
5466                 return;
5467         }
5468
5469         dev_priv->cdclk_freq = frequency;
5470 }
5471
5472 void broxton_init_cdclk(struct drm_device *dev)
5473 {
5474         struct drm_i915_private *dev_priv = dev->dev_private;
5475         uint32_t val;
5476
5477         /*
5478          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5479          * or else the reset will hang because there is no PCH to respond.
5480          * Move the handshake programming to initialization sequence.
5481          * Previously was left up to BIOS.
5482          */
5483         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5484         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5485         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5486
5487         /* Enable PG1 for cdclk */
5488         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5489
5490         /* check if cd clock is enabled */
5491         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5492                 DRM_DEBUG_KMS("Display already initialized\n");
5493                 return;
5494         }
5495
5496         /*
5497          * FIXME:
5498          * - The initial CDCLK needs to be read from VBT.
5499          *   Need to make this change after VBT has changes for BXT.
5500          * - check if setting the max (or any) cdclk freq is really necessary
5501          *   here, it belongs to modeset time
5502          */
5503         broxton_set_cdclk(dev, 624000);
5504
5505         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5506         POSTING_READ(DBUF_CTL);
5507
5508         udelay(10);
5509
5510         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5511                 DRM_ERROR("DBuf power enable timeout!\n");
5512 }
5513
5514 void broxton_uninit_cdclk(struct drm_device *dev)
5515 {
5516         struct drm_i915_private *dev_priv = dev->dev_private;
5517
5518         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5519         POSTING_READ(DBUF_CTL);
5520
5521         udelay(10);
5522
5523         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5524                 DRM_ERROR("DBuf power disable timeout!\n");
5525
5526         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5527         broxton_set_cdclk(dev, 19200);
5528
5529         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5530 }
5531
5532 static const struct skl_cdclk_entry {
5533         unsigned int freq;
5534         unsigned int vco;
5535 } skl_cdclk_frequencies[] = {
5536         { .freq = 308570, .vco = 8640 },
5537         { .freq = 337500, .vco = 8100 },
5538         { .freq = 432000, .vco = 8640 },
5539         { .freq = 450000, .vco = 8100 },
5540         { .freq = 540000, .vco = 8100 },
5541         { .freq = 617140, .vco = 8640 },
5542         { .freq = 675000, .vco = 8100 },
5543 };
5544
5545 static unsigned int skl_cdclk_decimal(unsigned int freq)
5546 {
5547         return (freq - 1000) / 500;
5548 }
5549
5550 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5551 {
5552         unsigned int i;
5553
5554         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5555                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5556
5557                 if (e->freq == freq)
5558                         return e->vco;
5559         }
5560
5561         return 8100;
5562 }
5563
5564 static void
5565 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5566 {
5567         unsigned int min_freq;
5568         u32 val;
5569
5570         /* select the minimum CDCLK before enabling DPLL 0 */
5571         val = I915_READ(CDCLK_CTL);
5572         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5573         val |= CDCLK_FREQ_337_308;
5574
5575         if (required_vco == 8640)
5576                 min_freq = 308570;
5577         else
5578                 min_freq = 337500;
5579
5580         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5581
5582         I915_WRITE(CDCLK_CTL, val);
5583         POSTING_READ(CDCLK_CTL);
5584
5585         /*
5586          * We always enable DPLL0 with the lowest link rate possible, but still
5587          * taking into account the VCO required to operate the eDP panel at the
5588          * desired frequency. The usual DP link rates operate with a VCO of
5589          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5590          * The modeset code is responsible for the selection of the exact link
5591          * rate later on, with the constraint of choosing a frequency that
5592          * works with required_vco.
5593          */
5594         val = I915_READ(DPLL_CTRL1);
5595
5596         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5597                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5598         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5599         if (required_vco == 8640)
5600                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5601                                             SKL_DPLL0);
5602         else
5603                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5604                                             SKL_DPLL0);
5605
5606         I915_WRITE(DPLL_CTRL1, val);
5607         POSTING_READ(DPLL_CTRL1);
5608
5609         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5610
5611         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5612                 DRM_ERROR("DPLL0 not locked\n");
5613 }
5614
5615 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5616 {
5617         int ret;
5618         u32 val;
5619
5620         /* inform PCU we want to change CDCLK */
5621         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5622         mutex_lock(&dev_priv->rps.hw_lock);
5623         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5624         mutex_unlock(&dev_priv->rps.hw_lock);
5625
5626         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5627 }
5628
5629 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5630 {
5631         unsigned int i;
5632
5633         for (i = 0; i < 15; i++) {
5634                 if (skl_cdclk_pcu_ready(dev_priv))
5635                         return true;
5636                 udelay(10);
5637         }
5638
5639         return false;
5640 }
5641
5642 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5643 {
5644         u32 freq_select, pcu_ack;
5645
5646         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5647
5648         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5649                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5650                 return;
5651         }
5652
5653         /* set CDCLK_CTL */
5654         switch(freq) {
5655         case 450000:
5656         case 432000:
5657                 freq_select = CDCLK_FREQ_450_432;
5658                 pcu_ack = 1;
5659                 break;
5660         case 540000:
5661                 freq_select = CDCLK_FREQ_540;
5662                 pcu_ack = 2;
5663                 break;
5664         case 308570:
5665         case 337500:
5666         default:
5667                 freq_select = CDCLK_FREQ_337_308;
5668                 pcu_ack = 0;
5669                 break;
5670         case 617140:
5671         case 675000:
5672                 freq_select = CDCLK_FREQ_675_617;
5673                 pcu_ack = 3;
5674                 break;
5675         }
5676
5677         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5678         POSTING_READ(CDCLK_CTL);
5679
5680         /* inform PCU of the change */
5681         mutex_lock(&dev_priv->rps.hw_lock);
5682         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5683         mutex_unlock(&dev_priv->rps.hw_lock);
5684 }
5685
5686 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5687 {
5688         /* disable DBUF power */
5689         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5690         POSTING_READ(DBUF_CTL);
5691
5692         udelay(10);
5693
5694         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5695                 DRM_ERROR("DBuf power disable timeout\n");
5696
5697         /* disable DPLL0 */
5698         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5699         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5700                 DRM_ERROR("Couldn't disable DPLL0\n");
5701
5702         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5703 }
5704
5705 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5706 {
5707         u32 val;
5708         unsigned int required_vco;
5709
5710         /* enable PCH reset handshake */
5711         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5712         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5713
5714         /* enable PG1 and Misc I/O */
5715         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5716
5717         /* DPLL0 already enabed !? */
5718         if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5719                 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5720                 return;
5721         }
5722
5723         /* enable DPLL0 */
5724         required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5725         skl_dpll0_enable(dev_priv, required_vco);
5726
5727         /* set CDCLK to the frequency the BIOS chose */
5728         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5729
5730         /* enable DBUF power */
5731         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5732         POSTING_READ(DBUF_CTL);
5733
5734         udelay(10);
5735
5736         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5737                 DRM_ERROR("DBuf power enable timeout\n");
5738 }
5739
5740 /* returns HPLL frequency in kHz */
5741 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5742 {
5743         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5744
5745         /* Obtain SKU information */
5746         mutex_lock(&dev_priv->sb_lock);
5747         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5748                 CCK_FUSE_HPLL_FREQ_MASK;
5749         mutex_unlock(&dev_priv->sb_lock);
5750
5751         return vco_freq[hpll_freq] * 1000;
5752 }
5753
5754 static void vlv_update_cdclk(struct drm_device *dev)
5755 {
5756         struct drm_i915_private *dev_priv = dev->dev_private;
5757
5758         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5759         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5760                          dev_priv->cdclk_freq);
5761
5762         /*
5763          * Program the gmbus_freq based on the cdclk frequency.
5764          * BSpec erroneously claims we should aim for 4MHz, but
5765          * in fact 1MHz is the correct frequency.
5766          */
5767         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5768 }
5769
5770 /* Adjust CDclk dividers to allow high res or save power if possible */
5771 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5772 {
5773         struct drm_i915_private *dev_priv = dev->dev_private;
5774         u32 val, cmd;
5775
5776         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5777                                         != dev_priv->cdclk_freq);
5778
5779         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5780                 cmd = 2;
5781         else if (cdclk == 266667)
5782                 cmd = 1;
5783         else
5784                 cmd = 0;
5785
5786         mutex_lock(&dev_priv->rps.hw_lock);
5787         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5788         val &= ~DSPFREQGUAR_MASK;
5789         val |= (cmd << DSPFREQGUAR_SHIFT);
5790         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5791         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5792                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5793                      50)) {
5794                 DRM_ERROR("timed out waiting for CDclk change\n");
5795         }
5796         mutex_unlock(&dev_priv->rps.hw_lock);
5797
5798         mutex_lock(&dev_priv->sb_lock);
5799
5800         if (cdclk == 400000) {
5801                 u32 divider;
5802
5803                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5804
5805                 /* adjust cdclk divider */
5806                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5807                 val &= ~DISPLAY_FREQUENCY_VALUES;
5808                 val |= divider;
5809                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5810
5811                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5812                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5813                              50))
5814                         DRM_ERROR("timed out waiting for CDclk change\n");
5815         }
5816
5817         /* adjust self-refresh exit latency value */
5818         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5819         val &= ~0x7f;
5820
5821         /*
5822          * For high bandwidth configs, we set a higher latency in the bunit
5823          * so that the core display fetch happens in time to avoid underruns.
5824          */
5825         if (cdclk == 400000)
5826                 val |= 4500 / 250; /* 4.5 usec */
5827         else
5828                 val |= 3000 / 250; /* 3.0 usec */
5829         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5830
5831         mutex_unlock(&dev_priv->sb_lock);
5832
5833         vlv_update_cdclk(dev);
5834 }
5835
5836 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5837 {
5838         struct drm_i915_private *dev_priv = dev->dev_private;
5839         u32 val, cmd;
5840
5841         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5842                                                 != dev_priv->cdclk_freq);
5843
5844         switch (cdclk) {
5845         case 333333:
5846         case 320000:
5847         case 266667:
5848         case 200000:
5849                 break;
5850         default:
5851                 MISSING_CASE(cdclk);
5852                 return;
5853         }
5854
5855         /*
5856          * Specs are full of misinformation, but testing on actual
5857          * hardware has shown that we just need to write the desired
5858          * CCK divider into the Punit register.
5859          */
5860         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5861
5862         mutex_lock(&dev_priv->rps.hw_lock);
5863         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5864         val &= ~DSPFREQGUAR_MASK_CHV;
5865         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5866         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5867         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5868                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5869                      50)) {
5870                 DRM_ERROR("timed out waiting for CDclk change\n");
5871         }
5872         mutex_unlock(&dev_priv->rps.hw_lock);
5873
5874         vlv_update_cdclk(dev);
5875 }
5876
5877 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5878                                  int max_pixclk)
5879 {
5880         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5881         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5882
5883         /*
5884          * Really only a few cases to deal with, as only 4 CDclks are supported:
5885          *   200MHz
5886          *   267MHz
5887          *   320/333MHz (depends on HPLL freq)
5888          *   400MHz (VLV only)
5889          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5890          * of the lower bin and adjust if needed.
5891          *
5892          * We seem to get an unstable or solid color picture at 200MHz.
5893          * Not sure what's wrong. For now use 200MHz only when all pipes
5894          * are off.
5895          */
5896         if (!IS_CHERRYVIEW(dev_priv) &&
5897             max_pixclk > freq_320*limit/100)
5898                 return 400000;
5899         else if (max_pixclk > 266667*limit/100)
5900                 return freq_320;
5901         else if (max_pixclk > 0)
5902                 return 266667;
5903         else
5904                 return 200000;
5905 }
5906
5907 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5908                               int max_pixclk)
5909 {
5910         /*
5911          * FIXME:
5912          * - remove the guardband, it's not needed on BXT
5913          * - set 19.2MHz bypass frequency if there are no active pipes
5914          */
5915         if (max_pixclk > 576000*9/10)
5916                 return 624000;
5917         else if (max_pixclk > 384000*9/10)
5918                 return 576000;
5919         else if (max_pixclk > 288000*9/10)
5920                 return 384000;
5921         else if (max_pixclk > 144000*9/10)
5922                 return 288000;
5923         else
5924                 return 144000;
5925 }
5926
5927 /* Compute the max pixel clock for new configuration. Uses atomic state if
5928  * that's non-NULL, look at current state otherwise. */
5929 static int intel_mode_max_pixclk(struct drm_device *dev,
5930                                  struct drm_atomic_state *state)
5931 {
5932         struct intel_crtc *intel_crtc;
5933         struct intel_crtc_state *crtc_state;
5934         int max_pixclk = 0;
5935
5936         for_each_intel_crtc(dev, intel_crtc) {
5937                 if (state)
5938                         crtc_state =
5939                                 intel_atomic_get_crtc_state(state, intel_crtc);
5940                 else
5941                         crtc_state = intel_crtc->config;
5942                 if (IS_ERR(crtc_state))
5943                         return PTR_ERR(crtc_state);
5944
5945                 if (!crtc_state->base.enable)
5946                         continue;
5947
5948                 max_pixclk = max(max_pixclk,
5949                                  crtc_state->base.adjusted_mode.crtc_clock);
5950         }
5951
5952         return max_pixclk;
5953 }
5954
5955 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5956 {
5957         struct drm_i915_private *dev_priv = to_i915(state->dev);
5958         struct drm_crtc *crtc;
5959         struct drm_crtc_state *crtc_state;
5960         int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5961         int cdclk, i;
5962
5963         if (max_pixclk < 0)
5964                 return max_pixclk;
5965
5966         if (IS_VALLEYVIEW(dev_priv))
5967                 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5968         else
5969                 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5970
5971         if (cdclk == dev_priv->cdclk_freq)
5972                 return 0;
5973
5974         /* add all active pipes to the state */
5975         for_each_crtc(state->dev, crtc) {
5976                 if (!crtc->state->enable)
5977                         continue;
5978
5979                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5980                 if (IS_ERR(crtc_state))
5981                         return PTR_ERR(crtc_state);
5982         }
5983
5984         /* disable/enable all currently active pipes while we change cdclk */
5985         for_each_crtc_in_state(state, crtc, crtc_state, i)
5986                 if (crtc_state->enable)
5987                         crtc_state->mode_changed = true;
5988
5989         return 0;
5990 }
5991
5992 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5993 {
5994         unsigned int credits, default_credits;
5995
5996         if (IS_CHERRYVIEW(dev_priv))
5997                 default_credits = PFI_CREDIT(12);
5998         else
5999                 default_credits = PFI_CREDIT(8);
6000
6001         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
6002                 /* CHV suggested value is 31 or 63 */
6003                 if (IS_CHERRYVIEW(dev_priv))
6004                         credits = PFI_CREDIT_31;
6005                 else
6006                         credits = PFI_CREDIT(15);
6007         } else {
6008                 credits = default_credits;
6009         }
6010
6011         /*
6012          * WA - write default credits before re-programming
6013          * FIXME: should we also set the resend bit here?
6014          */
6015         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6016                    default_credits);
6017
6018         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6019                    credits | PFI_CREDIT_RESEND);
6020
6021         /*
6022          * FIXME is this guaranteed to clear
6023          * immediately or should we poll for it?
6024          */
6025         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6026 }
6027
6028 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
6029 {
6030         struct drm_device *dev = old_state->dev;
6031         struct drm_i915_private *dev_priv = dev->dev_private;
6032         int max_pixclk = intel_mode_max_pixclk(dev, NULL);
6033         int req_cdclk;
6034
6035         /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6036          * never fail. */
6037         if (WARN_ON(max_pixclk < 0))
6038                 return;
6039
6040         req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
6041
6042         if (req_cdclk != dev_priv->cdclk_freq) {
6043                 /*
6044                  * FIXME: We can end up here with all power domains off, yet
6045                  * with a CDCLK frequency other than the minimum. To account
6046                  * for this take the PIPE-A power domain, which covers the HW
6047                  * blocks needed for the following programming. This can be
6048                  * removed once it's guaranteed that we get here either with
6049                  * the minimum CDCLK set, or the required power domains
6050                  * enabled.
6051                  */
6052                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6053
6054                 if (IS_CHERRYVIEW(dev))
6055                         cherryview_set_cdclk(dev, req_cdclk);
6056                 else
6057                         valleyview_set_cdclk(dev, req_cdclk);
6058
6059                 vlv_program_pfi_credits(dev_priv);
6060
6061                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6062         }
6063 }
6064
6065 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6066 {
6067         struct drm_device *dev = crtc->dev;
6068         struct drm_i915_private *dev_priv = to_i915(dev);
6069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6070         struct intel_encoder *encoder;
6071         int pipe = intel_crtc->pipe;
6072         bool is_dsi;
6073
6074         WARN_ON(!crtc->state->enable);
6075
6076         if (intel_crtc->active)
6077                 return;
6078
6079         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6080
6081         if (!is_dsi) {
6082                 if (IS_CHERRYVIEW(dev))
6083                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6084                 else
6085                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6086         }
6087
6088         if (intel_crtc->config->has_dp_encoder)
6089                 intel_dp_set_m_n(intel_crtc, M1_N1);
6090
6091         intel_set_pipe_timings(intel_crtc);
6092
6093         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6094                 struct drm_i915_private *dev_priv = dev->dev_private;
6095
6096                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6097                 I915_WRITE(CHV_CANVAS(pipe), 0);
6098         }
6099
6100         i9xx_set_pipeconf(intel_crtc);
6101
6102         intel_crtc->active = true;
6103
6104         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6105
6106         for_each_encoder_on_crtc(dev, crtc, encoder)
6107                 if (encoder->pre_pll_enable)
6108                         encoder->pre_pll_enable(encoder);
6109
6110         if (!is_dsi) {
6111                 if (IS_CHERRYVIEW(dev))
6112                         chv_enable_pll(intel_crtc, intel_crtc->config);
6113                 else
6114                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6115         }
6116
6117         for_each_encoder_on_crtc(dev, crtc, encoder)
6118                 if (encoder->pre_enable)
6119                         encoder->pre_enable(encoder);
6120
6121         i9xx_pfit_enable(intel_crtc);
6122
6123         intel_crtc_load_lut(crtc);
6124
6125         intel_update_watermarks(crtc);
6126         intel_enable_pipe(intel_crtc);
6127
6128         assert_vblank_disabled(crtc);
6129         drm_crtc_vblank_on(crtc);
6130
6131         for_each_encoder_on_crtc(dev, crtc, encoder)
6132                 encoder->enable(encoder);
6133 }
6134
6135 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6136 {
6137         struct drm_device *dev = crtc->base.dev;
6138         struct drm_i915_private *dev_priv = dev->dev_private;
6139
6140         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6141         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6142 }
6143
6144 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6145 {
6146         struct drm_device *dev = crtc->dev;
6147         struct drm_i915_private *dev_priv = to_i915(dev);
6148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6149         struct intel_encoder *encoder;
6150         int pipe = intel_crtc->pipe;
6151
6152         WARN_ON(!crtc->state->enable);
6153
6154         if (intel_crtc->active)
6155                 return;
6156
6157         i9xx_set_pll_dividers(intel_crtc);
6158
6159         if (intel_crtc->config->has_dp_encoder)
6160                 intel_dp_set_m_n(intel_crtc, M1_N1);
6161
6162         intel_set_pipe_timings(intel_crtc);
6163
6164         i9xx_set_pipeconf(intel_crtc);
6165
6166         intel_crtc->active = true;
6167
6168         if (!IS_GEN2(dev))
6169                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6170
6171         for_each_encoder_on_crtc(dev, crtc, encoder)
6172                 if (encoder->pre_enable)
6173                         encoder->pre_enable(encoder);
6174
6175         i9xx_enable_pll(intel_crtc);
6176
6177         i9xx_pfit_enable(intel_crtc);
6178
6179         intel_crtc_load_lut(crtc);
6180
6181         intel_update_watermarks(crtc);
6182         intel_enable_pipe(intel_crtc);
6183
6184         assert_vblank_disabled(crtc);
6185         drm_crtc_vblank_on(crtc);
6186
6187         for_each_encoder_on_crtc(dev, crtc, encoder)
6188                 encoder->enable(encoder);
6189 }
6190
6191 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6192 {
6193         struct drm_device *dev = crtc->base.dev;
6194         struct drm_i915_private *dev_priv = dev->dev_private;
6195
6196         if (!crtc->config->gmch_pfit.control)
6197                 return;
6198
6199         assert_pipe_disabled(dev_priv, crtc->pipe);
6200
6201         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6202                          I915_READ(PFIT_CONTROL));
6203         I915_WRITE(PFIT_CONTROL, 0);
6204 }
6205
6206 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6207 {
6208         struct drm_device *dev = crtc->dev;
6209         struct drm_i915_private *dev_priv = dev->dev_private;
6210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6211         struct intel_encoder *encoder;
6212         int pipe = intel_crtc->pipe;
6213
6214         if (!intel_crtc->active)
6215                 return;
6216
6217         /*
6218          * On gen2 planes are double buffered but the pipe isn't, so we must
6219          * wait for planes to fully turn off before disabling the pipe.
6220          * We also need to wait on all gmch platforms because of the
6221          * self-refresh mode constraint explained above.
6222          */
6223         intel_wait_for_vblank(dev, pipe);
6224
6225         for_each_encoder_on_crtc(dev, crtc, encoder)
6226                 encoder->disable(encoder);
6227
6228         drm_crtc_vblank_off(crtc);
6229         assert_vblank_disabled(crtc);
6230
6231         intel_disable_pipe(intel_crtc);
6232
6233         i9xx_pfit_disable(intel_crtc);
6234
6235         for_each_encoder_on_crtc(dev, crtc, encoder)
6236                 if (encoder->post_disable)
6237                         encoder->post_disable(encoder);
6238
6239         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6240                 if (IS_CHERRYVIEW(dev))
6241                         chv_disable_pll(dev_priv, pipe);
6242                 else if (IS_VALLEYVIEW(dev))
6243                         vlv_disable_pll(dev_priv, pipe);
6244                 else
6245                         i9xx_disable_pll(intel_crtc);
6246         }
6247
6248         if (!IS_GEN2(dev))
6249                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6250
6251         intel_crtc->active = false;
6252         intel_update_watermarks(crtc);
6253
6254         mutex_lock(&dev->struct_mutex);
6255         intel_fbc_update(dev);
6256         mutex_unlock(&dev->struct_mutex);
6257 }
6258
6259 static void i9xx_crtc_off(struct drm_crtc *crtc)
6260 {
6261 }
6262
6263 /* Master function to enable/disable CRTC and corresponding power wells */
6264 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6265 {
6266         struct drm_device *dev = crtc->dev;
6267         struct drm_i915_private *dev_priv = dev->dev_private;
6268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6269         enum intel_display_power_domain domain;
6270         unsigned long domains;
6271
6272         if (enable) {
6273                 if (!intel_crtc->active) {
6274                         domains = get_crtc_power_domains(crtc);
6275                         for_each_power_domain(domain, domains)
6276                                 intel_display_power_get(dev_priv, domain);
6277                         intel_crtc->enabled_power_domains = domains;
6278
6279                         dev_priv->display.crtc_enable(crtc);
6280                         intel_crtc_enable_planes(crtc);
6281                 }
6282         } else {
6283                 if (intel_crtc->active) {
6284                         intel_crtc_disable_planes(crtc);
6285                         dev_priv->display.crtc_disable(crtc);
6286
6287                         domains = intel_crtc->enabled_power_domains;
6288                         for_each_power_domain(domain, domains)
6289                                 intel_display_power_put(dev_priv, domain);
6290                         intel_crtc->enabled_power_domains = 0;
6291                 }
6292         }
6293 }
6294
6295 /**
6296  * Sets the power management mode of the pipe and plane.
6297  */
6298 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6299 {
6300         struct drm_device *dev = crtc->dev;
6301         struct intel_encoder *intel_encoder;
6302         bool enable = false;
6303
6304         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6305                 enable |= intel_encoder->connectors_active;
6306
6307         intel_crtc_control(crtc, enable);
6308
6309         crtc->state->active = enable;
6310 }
6311
6312 static void intel_crtc_disable(struct drm_crtc *crtc)
6313 {
6314         struct drm_device *dev = crtc->dev;
6315         struct drm_connector *connector;
6316         struct drm_i915_private *dev_priv = dev->dev_private;
6317
6318         /* crtc should still be enabled when we disable it. */
6319         WARN_ON(!crtc->state->enable);
6320
6321         intel_crtc_disable_planes(crtc);
6322         dev_priv->display.crtc_disable(crtc);
6323         dev_priv->display.off(crtc);
6324
6325         drm_plane_helper_disable(crtc->primary);
6326
6327         /* Update computed state. */
6328         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6329                 if (!connector->encoder || !connector->encoder->crtc)
6330                         continue;
6331
6332                 if (connector->encoder->crtc != crtc)
6333                         continue;
6334
6335                 connector->dpms = DRM_MODE_DPMS_OFF;
6336                 to_intel_encoder(connector->encoder)->connectors_active = false;
6337         }
6338 }
6339
6340 void intel_encoder_destroy(struct drm_encoder *encoder)
6341 {
6342         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6343
6344         drm_encoder_cleanup(encoder);
6345         kfree(intel_encoder);
6346 }
6347
6348 /* Simple dpms helper for encoders with just one connector, no cloning and only
6349  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6350  * state of the entire output pipe. */
6351 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6352 {
6353         if (mode == DRM_MODE_DPMS_ON) {
6354                 encoder->connectors_active = true;
6355
6356                 intel_crtc_update_dpms(encoder->base.crtc);
6357         } else {
6358                 encoder->connectors_active = false;
6359
6360                 intel_crtc_update_dpms(encoder->base.crtc);
6361         }
6362 }
6363
6364 /* Cross check the actual hw state with our own modeset state tracking (and it's
6365  * internal consistency). */
6366 static void intel_connector_check_state(struct intel_connector *connector)
6367 {
6368         if (connector->get_hw_state(connector)) {
6369                 struct intel_encoder *encoder = connector->encoder;
6370                 struct drm_crtc *crtc;
6371                 bool encoder_enabled;
6372                 enum pipe pipe;
6373
6374                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6375                               connector->base.base.id,
6376                               connector->base.name);
6377
6378                 /* there is no real hw state for MST connectors */
6379                 if (connector->mst_port)
6380                         return;
6381
6382                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6383                      "wrong connector dpms state\n");
6384                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6385                      "active connector not linked to encoder\n");
6386
6387                 if (encoder) {
6388                         I915_STATE_WARN(!encoder->connectors_active,
6389                              "encoder->connectors_active not set\n");
6390
6391                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6392                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6393                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
6394                                 return;
6395
6396                         crtc = encoder->base.crtc;
6397
6398                         I915_STATE_WARN(!crtc->state->enable,
6399                                         "crtc not enabled\n");
6400                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6401                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6402                              "encoder active on the wrong pipe\n");
6403                 }
6404         }
6405 }
6406
6407 int intel_connector_init(struct intel_connector *connector)
6408 {
6409         struct drm_connector_state *connector_state;
6410
6411         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6412         if (!connector_state)
6413                 return -ENOMEM;
6414
6415         connector->base.state = connector_state;
6416         return 0;
6417 }
6418
6419 struct intel_connector *intel_connector_alloc(void)
6420 {
6421         struct intel_connector *connector;
6422
6423         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6424         if (!connector)
6425                 return NULL;
6426
6427         if (intel_connector_init(connector) < 0) {
6428                 kfree(connector);
6429                 return NULL;
6430         }
6431
6432         return connector;
6433 }
6434
6435 /* Even simpler default implementation, if there's really no special case to
6436  * consider. */
6437 void intel_connector_dpms(struct drm_connector *connector, int mode)
6438 {
6439         /* All the simple cases only support two dpms states. */
6440         if (mode != DRM_MODE_DPMS_ON)
6441                 mode = DRM_MODE_DPMS_OFF;
6442
6443         if (mode == connector->dpms)
6444                 return;
6445
6446         connector->dpms = mode;
6447
6448         /* Only need to change hw state when actually enabled */
6449         if (connector->encoder)
6450                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6451
6452         intel_modeset_check_state(connector->dev);
6453 }
6454
6455 /* Simple connector->get_hw_state implementation for encoders that support only
6456  * one connector and no cloning and hence the encoder state determines the state
6457  * of the connector. */
6458 bool intel_connector_get_hw_state(struct intel_connector *connector)
6459 {
6460         enum pipe pipe = 0;
6461         struct intel_encoder *encoder = connector->encoder;
6462
6463         return encoder->get_hw_state(encoder, &pipe);
6464 }
6465
6466 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6467 {
6468         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6469                 return crtc_state->fdi_lanes;
6470
6471         return 0;
6472 }
6473
6474 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6475                                      struct intel_crtc_state *pipe_config)
6476 {
6477         struct drm_atomic_state *state = pipe_config->base.state;
6478         struct intel_crtc *other_crtc;
6479         struct intel_crtc_state *other_crtc_state;
6480
6481         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6482                       pipe_name(pipe), pipe_config->fdi_lanes);
6483         if (pipe_config->fdi_lanes > 4) {
6484                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6485                               pipe_name(pipe), pipe_config->fdi_lanes);
6486                 return -EINVAL;
6487         }
6488
6489         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6490                 if (pipe_config->fdi_lanes > 2) {
6491                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6492                                       pipe_config->fdi_lanes);
6493                         return -EINVAL;
6494                 } else {
6495                         return 0;
6496                 }
6497         }
6498
6499         if (INTEL_INFO(dev)->num_pipes == 2)
6500                 return 0;
6501
6502         /* Ivybridge 3 pipe is really complicated */
6503         switch (pipe) {
6504         case PIPE_A:
6505                 return 0;
6506         case PIPE_B:
6507                 if (pipe_config->fdi_lanes <= 2)
6508                         return 0;
6509
6510                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6511                 other_crtc_state =
6512                         intel_atomic_get_crtc_state(state, other_crtc);
6513                 if (IS_ERR(other_crtc_state))
6514                         return PTR_ERR(other_crtc_state);
6515
6516                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6517                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6518                                       pipe_name(pipe), pipe_config->fdi_lanes);
6519                         return -EINVAL;
6520                 }
6521                 return 0;
6522         case PIPE_C:
6523                 if (pipe_config->fdi_lanes > 2) {
6524                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6525                                       pipe_name(pipe), pipe_config->fdi_lanes);
6526                         return -EINVAL;
6527                 }
6528
6529                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6530                 other_crtc_state =
6531                         intel_atomic_get_crtc_state(state, other_crtc);
6532                 if (IS_ERR(other_crtc_state))
6533                         return PTR_ERR(other_crtc_state);
6534
6535                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6536                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6537                         return -EINVAL;
6538                 }
6539                 return 0;
6540         default:
6541                 BUG();
6542         }
6543 }
6544
6545 #define RETRY 1
6546 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6547                                        struct intel_crtc_state *pipe_config)
6548 {
6549         struct drm_device *dev = intel_crtc->base.dev;
6550         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6551         int lane, link_bw, fdi_dotclock, ret;
6552         bool needs_recompute = false;
6553
6554 retry:
6555         /* FDI is a binary signal running at ~2.7GHz, encoding
6556          * each output octet as 10 bits. The actual frequency
6557          * is stored as a divider into a 100MHz clock, and the
6558          * mode pixel clock is stored in units of 1KHz.
6559          * Hence the bw of each lane in terms of the mode signal
6560          * is:
6561          */
6562         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6563
6564         fdi_dotclock = adjusted_mode->crtc_clock;
6565
6566         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6567                                            pipe_config->pipe_bpp);
6568
6569         pipe_config->fdi_lanes = lane;
6570
6571         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6572                                link_bw, &pipe_config->fdi_m_n);
6573
6574         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6575                                        intel_crtc->pipe, pipe_config);
6576         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6577                 pipe_config->pipe_bpp -= 2*3;
6578                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6579                               pipe_config->pipe_bpp);
6580                 needs_recompute = true;
6581                 pipe_config->bw_constrained = true;
6582
6583                 goto retry;
6584         }
6585
6586         if (needs_recompute)
6587                 return RETRY;
6588
6589         return ret;
6590 }
6591
6592 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6593                                    struct intel_crtc_state *pipe_config)
6594 {
6595         pipe_config->ips_enabled = i915.enable_ips &&
6596                                    hsw_crtc_supports_ips(crtc) &&
6597                                    pipe_config->pipe_bpp <= 24;
6598 }
6599
6600 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6601                                      struct intel_crtc_state *pipe_config)
6602 {
6603         struct drm_device *dev = crtc->base.dev;
6604         struct drm_i915_private *dev_priv = dev->dev_private;
6605         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6606         int ret;
6607
6608         /* FIXME should check pixel clock limits on all platforms */
6609         if (INTEL_INFO(dev)->gen < 4) {
6610                 int clock_limit =
6611                         dev_priv->display.get_display_clock_speed(dev);
6612
6613                 /*
6614                  * Enable pixel doubling when the dot clock
6615                  * is > 90% of the (display) core speed.
6616                  *
6617                  * GDG double wide on either pipe,
6618                  * otherwise pipe A only.
6619                  */
6620                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6621                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6622                         clock_limit *= 2;
6623                         pipe_config->double_wide = true;
6624                 }
6625
6626                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6627                         return -EINVAL;
6628         }
6629
6630         /*
6631          * Pipe horizontal size must be even in:
6632          * - DVO ganged mode
6633          * - LVDS dual channel mode
6634          * - Double wide pipe
6635          */
6636         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6637              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6638                 pipe_config->pipe_src_w &= ~1;
6639
6640         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6641          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6642          */
6643         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6644                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6645                 return -EINVAL;
6646
6647         if (HAS_IPS(dev))
6648                 hsw_compute_ips_config(crtc, pipe_config);
6649
6650         if (pipe_config->has_pch_encoder)
6651                 return ironlake_fdi_compute_config(crtc, pipe_config);
6652
6653         /* FIXME: remove below call once atomic mode set is place and all crtc
6654          * related checks called from atomic_crtc_check function */
6655         ret = 0;
6656         DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6657                 crtc, pipe_config->base.state);
6658         ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6659
6660         return ret;
6661 }
6662
6663 static int skylake_get_display_clock_speed(struct drm_device *dev)
6664 {
6665         struct drm_i915_private *dev_priv = to_i915(dev);
6666         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6667         uint32_t cdctl = I915_READ(CDCLK_CTL);
6668         uint32_t linkrate;
6669
6670         if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6671                 WARN(1, "LCPLL1 not enabled\n");
6672                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6673         }
6674
6675         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6676                 return 540000;
6677
6678         linkrate = (I915_READ(DPLL_CTRL1) &
6679                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6680
6681         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6682             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6683                 /* vco 8640 */
6684                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6685                 case CDCLK_FREQ_450_432:
6686                         return 432000;
6687                 case CDCLK_FREQ_337_308:
6688                         return 308570;
6689                 case CDCLK_FREQ_675_617:
6690                         return 617140;
6691                 default:
6692                         WARN(1, "Unknown cd freq selection\n");
6693                 }
6694         } else {
6695                 /* vco 8100 */
6696                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6697                 case CDCLK_FREQ_450_432:
6698                         return 450000;
6699                 case CDCLK_FREQ_337_308:
6700                         return 337500;
6701                 case CDCLK_FREQ_675_617:
6702                         return 675000;
6703                 default:
6704                         WARN(1, "Unknown cd freq selection\n");
6705                 }
6706         }
6707
6708         /* error case, do as if DPLL0 isn't enabled */
6709         return 24000;
6710 }
6711
6712 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6713 {
6714         struct drm_i915_private *dev_priv = dev->dev_private;
6715         uint32_t lcpll = I915_READ(LCPLL_CTL);
6716         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6717
6718         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6719                 return 800000;
6720         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6721                 return 450000;
6722         else if (freq == LCPLL_CLK_FREQ_450)
6723                 return 450000;
6724         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6725                 return 540000;
6726         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6727                 return 337500;
6728         else
6729                 return 675000;
6730 }
6731
6732 static int haswell_get_display_clock_speed(struct drm_device *dev)
6733 {
6734         struct drm_i915_private *dev_priv = dev->dev_private;
6735         uint32_t lcpll = I915_READ(LCPLL_CTL);
6736         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6737
6738         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6739                 return 800000;
6740         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6741                 return 450000;
6742         else if (freq == LCPLL_CLK_FREQ_450)
6743                 return 450000;
6744         else if (IS_HSW_ULT(dev))
6745                 return 337500;
6746         else
6747                 return 540000;
6748 }
6749
6750 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6751 {
6752         struct drm_i915_private *dev_priv = dev->dev_private;
6753         u32 val;
6754         int divider;
6755
6756         if (dev_priv->hpll_freq == 0)
6757                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6758
6759         mutex_lock(&dev_priv->sb_lock);
6760         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6761         mutex_unlock(&dev_priv->sb_lock);
6762
6763         divider = val & DISPLAY_FREQUENCY_VALUES;
6764
6765         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6766              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6767              "cdclk change in progress\n");
6768
6769         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6770 }
6771
6772 static int ilk_get_display_clock_speed(struct drm_device *dev)
6773 {
6774         return 450000;
6775 }
6776
6777 static int i945_get_display_clock_speed(struct drm_device *dev)
6778 {
6779         return 400000;
6780 }
6781
6782 static int i915_get_display_clock_speed(struct drm_device *dev)
6783 {
6784         return 333333;
6785 }
6786
6787 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6788 {
6789         return 200000;
6790 }
6791
6792 static int pnv_get_display_clock_speed(struct drm_device *dev)
6793 {
6794         u16 gcfgc = 0;
6795
6796         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6797
6798         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6799         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6800                 return 266667;
6801         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6802                 return 333333;
6803         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6804                 return 444444;
6805         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6806                 return 200000;
6807         default:
6808                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6809         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6810                 return 133333;
6811         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6812                 return 166667;
6813         }
6814 }
6815
6816 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6817 {
6818         u16 gcfgc = 0;
6819
6820         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6821
6822         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6823                 return 133333;
6824         else {
6825                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6826                 case GC_DISPLAY_CLOCK_333_MHZ:
6827                         return 333333;
6828                 default:
6829                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6830                         return 190000;
6831                 }
6832         }
6833 }
6834
6835 static int i865_get_display_clock_speed(struct drm_device *dev)
6836 {
6837         return 266667;
6838 }
6839
6840 static int i855_get_display_clock_speed(struct drm_device *dev)
6841 {
6842         u16 hpllcc = 0;
6843         /* Assume that the hardware is in the high speed state.  This
6844          * should be the default.
6845          */
6846         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6847         case GC_CLOCK_133_200:
6848         case GC_CLOCK_100_200:
6849                 return 200000;
6850         case GC_CLOCK_166_250:
6851                 return 250000;
6852         case GC_CLOCK_100_133:
6853                 return 133333;
6854         }
6855
6856         /* Shouldn't happen */
6857         return 0;
6858 }
6859
6860 static int i830_get_display_clock_speed(struct drm_device *dev)
6861 {
6862         return 133333;
6863 }
6864
6865 static void
6866 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6867 {
6868         while (*num > DATA_LINK_M_N_MASK ||
6869                *den > DATA_LINK_M_N_MASK) {
6870                 *num >>= 1;
6871                 *den >>= 1;
6872         }
6873 }
6874
6875 static void compute_m_n(unsigned int m, unsigned int n,
6876                         uint32_t *ret_m, uint32_t *ret_n)
6877 {
6878         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6879         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6880         intel_reduce_m_n_ratio(ret_m, ret_n);
6881 }
6882
6883 void
6884 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6885                        int pixel_clock, int link_clock,
6886                        struct intel_link_m_n *m_n)
6887 {
6888         m_n->tu = 64;
6889
6890         compute_m_n(bits_per_pixel * pixel_clock,
6891                     link_clock * nlanes * 8,
6892                     &m_n->gmch_m, &m_n->gmch_n);
6893
6894         compute_m_n(pixel_clock, link_clock,
6895                     &m_n->link_m, &m_n->link_n);
6896 }
6897
6898 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6899 {
6900         if (i915.panel_use_ssc >= 0)
6901                 return i915.panel_use_ssc != 0;
6902         return dev_priv->vbt.lvds_use_ssc
6903                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6904 }
6905
6906 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6907                            int num_connectors)
6908 {
6909         struct drm_device *dev = crtc_state->base.crtc->dev;
6910         struct drm_i915_private *dev_priv = dev->dev_private;
6911         int refclk;
6912
6913         WARN_ON(!crtc_state->base.state);
6914
6915         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6916                 refclk = 100000;
6917         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6918             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6919                 refclk = dev_priv->vbt.lvds_ssc_freq;
6920                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6921         } else if (!IS_GEN2(dev)) {
6922                 refclk = 96000;
6923         } else {
6924                 refclk = 48000;
6925         }
6926
6927         return refclk;
6928 }
6929
6930 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6931 {
6932         return (1 << dpll->n) << 16 | dpll->m2;
6933 }
6934
6935 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6936 {
6937         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6938 }
6939
6940 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6941                                      struct intel_crtc_state *crtc_state,
6942                                      intel_clock_t *reduced_clock)
6943 {
6944         struct drm_device *dev = crtc->base.dev;
6945         u32 fp, fp2 = 0;
6946
6947         if (IS_PINEVIEW(dev)) {
6948                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6949                 if (reduced_clock)
6950                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6951         } else {
6952                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6953                 if (reduced_clock)
6954                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6955         }
6956
6957         crtc_state->dpll_hw_state.fp0 = fp;
6958
6959         crtc->lowfreq_avail = false;
6960         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6961             reduced_clock) {
6962                 crtc_state->dpll_hw_state.fp1 = fp2;
6963                 crtc->lowfreq_avail = true;
6964         } else {
6965                 crtc_state->dpll_hw_state.fp1 = fp;
6966         }
6967 }
6968
6969 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6970                 pipe)
6971 {
6972         u32 reg_val;
6973
6974         /*
6975          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6976          * and set it to a reasonable value instead.
6977          */
6978         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6979         reg_val &= 0xffffff00;
6980         reg_val |= 0x00000030;
6981         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6982
6983         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6984         reg_val &= 0x8cffffff;
6985         reg_val = 0x8c000000;
6986         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6987
6988         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6989         reg_val &= 0xffffff00;
6990         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6991
6992         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6993         reg_val &= 0x00ffffff;
6994         reg_val |= 0xb0000000;
6995         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6996 }
6997
6998 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6999                                          struct intel_link_m_n *m_n)
7000 {
7001         struct drm_device *dev = crtc->base.dev;
7002         struct drm_i915_private *dev_priv = dev->dev_private;
7003         int pipe = crtc->pipe;
7004
7005         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7006         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7007         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7008         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7009 }
7010
7011 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7012                                          struct intel_link_m_n *m_n,
7013                                          struct intel_link_m_n *m2_n2)
7014 {
7015         struct drm_device *dev = crtc->base.dev;
7016         struct drm_i915_private *dev_priv = dev->dev_private;
7017         int pipe = crtc->pipe;
7018         enum transcoder transcoder = crtc->config->cpu_transcoder;
7019
7020         if (INTEL_INFO(dev)->gen >= 5) {
7021                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7022                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7023                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7024                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7025                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7026                  * for gen < 8) and if DRRS is supported (to make sure the
7027                  * registers are not unnecessarily accessed).
7028                  */
7029                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7030                         crtc->config->has_drrs) {
7031                         I915_WRITE(PIPE_DATA_M2(transcoder),
7032                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7033                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7034                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7035                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7036                 }
7037         } else {
7038                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7039                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7040                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7041                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7042         }
7043 }
7044
7045 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7046 {
7047         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7048
7049         if (m_n == M1_N1) {
7050                 dp_m_n = &crtc->config->dp_m_n;
7051                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7052         } else if (m_n == M2_N2) {
7053
7054                 /*
7055                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7056                  * needs to be programmed into M1_N1.
7057                  */
7058                 dp_m_n = &crtc->config->dp_m2_n2;
7059         } else {
7060                 DRM_ERROR("Unsupported divider value\n");
7061                 return;
7062         }
7063
7064         if (crtc->config->has_pch_encoder)
7065                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7066         else
7067                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7068 }
7069
7070 static void vlv_update_pll(struct intel_crtc *crtc,
7071                            struct intel_crtc_state *pipe_config)
7072 {
7073         u32 dpll, dpll_md;
7074
7075         /*
7076          * Enable DPIO clock input. We should never disable the reference
7077          * clock for pipe B, since VGA hotplug / manual detection depends
7078          * on it.
7079          */
7080         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7081                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7082         /* We should never disable this, set it here for state tracking */
7083         if (crtc->pipe == PIPE_B)
7084                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7085         dpll |= DPLL_VCO_ENABLE;
7086         pipe_config->dpll_hw_state.dpll = dpll;
7087
7088         dpll_md = (pipe_config->pixel_multiplier - 1)
7089                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7090         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7091 }
7092
7093 static void vlv_prepare_pll(struct intel_crtc *crtc,
7094                             const struct intel_crtc_state *pipe_config)
7095 {
7096         struct drm_device *dev = crtc->base.dev;
7097         struct drm_i915_private *dev_priv = dev->dev_private;
7098         int pipe = crtc->pipe;
7099         u32 mdiv;
7100         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7101         u32 coreclk, reg_val;
7102
7103         mutex_lock(&dev_priv->sb_lock);
7104
7105         bestn = pipe_config->dpll.n;
7106         bestm1 = pipe_config->dpll.m1;
7107         bestm2 = pipe_config->dpll.m2;
7108         bestp1 = pipe_config->dpll.p1;
7109         bestp2 = pipe_config->dpll.p2;
7110
7111         /* See eDP HDMI DPIO driver vbios notes doc */
7112
7113         /* PLL B needs special handling */
7114         if (pipe == PIPE_B)
7115                 vlv_pllb_recal_opamp(dev_priv, pipe);
7116
7117         /* Set up Tx target for periodic Rcomp update */
7118         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7119
7120         /* Disable target IRef on PLL */
7121         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7122         reg_val &= 0x00ffffff;
7123         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7124
7125         /* Disable fast lock */
7126         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7127
7128         /* Set idtafcrecal before PLL is enabled */
7129         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7130         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7131         mdiv |= ((bestn << DPIO_N_SHIFT));
7132         mdiv |= (1 << DPIO_K_SHIFT);
7133
7134         /*
7135          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7136          * but we don't support that).
7137          * Note: don't use the DAC post divider as it seems unstable.
7138          */
7139         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7140         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7141
7142         mdiv |= DPIO_ENABLE_CALIBRATION;
7143         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7144
7145         /* Set HBR and RBR LPF coefficients */
7146         if (pipe_config->port_clock == 162000 ||
7147             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7148             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7149                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7150                                  0x009f0003);
7151         else
7152                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7153                                  0x00d0000f);
7154
7155         if (pipe_config->has_dp_encoder) {
7156                 /* Use SSC source */
7157                 if (pipe == PIPE_A)
7158                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7159                                          0x0df40000);
7160                 else
7161                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7162                                          0x0df70000);
7163         } else { /* HDMI or VGA */
7164                 /* Use bend source */
7165                 if (pipe == PIPE_A)
7166                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7167                                          0x0df70000);
7168                 else
7169                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7170                                          0x0df40000);
7171         }
7172
7173         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7174         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7175         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7176             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7177                 coreclk |= 0x01000000;
7178         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7179
7180         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7181         mutex_unlock(&dev_priv->sb_lock);
7182 }
7183
7184 static void chv_update_pll(struct intel_crtc *crtc,
7185                            struct intel_crtc_state *pipe_config)
7186 {
7187         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7188                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7189                 DPLL_VCO_ENABLE;
7190         if (crtc->pipe != PIPE_A)
7191                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7192
7193         pipe_config->dpll_hw_state.dpll_md =
7194                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7195 }
7196
7197 static void chv_prepare_pll(struct intel_crtc *crtc,
7198                             const struct intel_crtc_state *pipe_config)
7199 {
7200         struct drm_device *dev = crtc->base.dev;
7201         struct drm_i915_private *dev_priv = dev->dev_private;
7202         int pipe = crtc->pipe;
7203         int dpll_reg = DPLL(crtc->pipe);
7204         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7205         u32 loopfilter, tribuf_calcntr;
7206         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7207         u32 dpio_val;
7208         int vco;
7209
7210         bestn = pipe_config->dpll.n;
7211         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7212         bestm1 = pipe_config->dpll.m1;
7213         bestm2 = pipe_config->dpll.m2 >> 22;
7214         bestp1 = pipe_config->dpll.p1;
7215         bestp2 = pipe_config->dpll.p2;
7216         vco = pipe_config->dpll.vco;
7217         dpio_val = 0;
7218         loopfilter = 0;
7219
7220         /*
7221          * Enable Refclk and SSC
7222          */
7223         I915_WRITE(dpll_reg,
7224                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7225
7226         mutex_lock(&dev_priv->sb_lock);
7227
7228         /* p1 and p2 divider */
7229         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7230                         5 << DPIO_CHV_S1_DIV_SHIFT |
7231                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7232                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7233                         1 << DPIO_CHV_K_DIV_SHIFT);
7234
7235         /* Feedback post-divider - m2 */
7236         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7237
7238         /* Feedback refclk divider - n and m1 */
7239         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7240                         DPIO_CHV_M1_DIV_BY_2 |
7241                         1 << DPIO_CHV_N_DIV_SHIFT);
7242
7243         /* M2 fraction division */
7244         if (bestm2_frac)
7245                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7246
7247         /* M2 fraction division enable */
7248         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7249         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7250         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7251         if (bestm2_frac)
7252                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7253         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7254
7255         /* Program digital lock detect threshold */
7256         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7257         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7258                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7259         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7260         if (!bestm2_frac)
7261                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7262         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7263
7264         /* Loop filter */
7265         if (vco == 5400000) {
7266                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7267                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7268                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7269                 tribuf_calcntr = 0x9;
7270         } else if (vco <= 6200000) {
7271                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7272                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7273                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7274                 tribuf_calcntr = 0x9;
7275         } else if (vco <= 6480000) {
7276                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7277                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7278                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7279                 tribuf_calcntr = 0x8;
7280         } else {
7281                 /* Not supported. Apply the same limits as in the max case */
7282                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7283                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7284                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7285                 tribuf_calcntr = 0;
7286         }
7287         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7288
7289         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7290         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7291         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7292         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7293
7294         /* AFC Recal */
7295         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7296                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7297                         DPIO_AFC_RECAL);
7298
7299         mutex_unlock(&dev_priv->sb_lock);
7300 }
7301
7302 /**
7303  * vlv_force_pll_on - forcibly enable just the PLL
7304  * @dev_priv: i915 private structure
7305  * @pipe: pipe PLL to enable
7306  * @dpll: PLL configuration
7307  *
7308  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7309  * in cases where we need the PLL enabled even when @pipe is not going to
7310  * be enabled.
7311  */
7312 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7313                       const struct dpll *dpll)
7314 {
7315         struct intel_crtc *crtc =
7316                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7317         struct intel_crtc_state pipe_config = {
7318                 .base.crtc = &crtc->base,
7319                 .pixel_multiplier = 1,
7320                 .dpll = *dpll,
7321         };
7322
7323         if (IS_CHERRYVIEW(dev)) {
7324                 chv_update_pll(crtc, &pipe_config);
7325                 chv_prepare_pll(crtc, &pipe_config);
7326                 chv_enable_pll(crtc, &pipe_config);
7327         } else {
7328                 vlv_update_pll(crtc, &pipe_config);
7329                 vlv_prepare_pll(crtc, &pipe_config);
7330                 vlv_enable_pll(crtc, &pipe_config);
7331         }
7332 }
7333
7334 /**
7335  * vlv_force_pll_off - forcibly disable just the PLL
7336  * @dev_priv: i915 private structure
7337  * @pipe: pipe PLL to disable
7338  *
7339  * Disable the PLL for @pipe. To be used in cases where we need
7340  * the PLL enabled even when @pipe is not going to be enabled.
7341  */
7342 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7343 {
7344         if (IS_CHERRYVIEW(dev))
7345                 chv_disable_pll(to_i915(dev), pipe);
7346         else
7347                 vlv_disable_pll(to_i915(dev), pipe);
7348 }
7349
7350 static void i9xx_update_pll(struct intel_crtc *crtc,
7351                             struct intel_crtc_state *crtc_state,
7352                             intel_clock_t *reduced_clock,
7353                             int num_connectors)
7354 {
7355         struct drm_device *dev = crtc->base.dev;
7356         struct drm_i915_private *dev_priv = dev->dev_private;
7357         u32 dpll;
7358         bool is_sdvo;
7359         struct dpll *clock = &crtc_state->dpll;
7360
7361         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7362
7363         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7364                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7365
7366         dpll = DPLL_VGA_MODE_DIS;
7367
7368         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7369                 dpll |= DPLLB_MODE_LVDS;
7370         else
7371                 dpll |= DPLLB_MODE_DAC_SERIAL;
7372
7373         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7374                 dpll |= (crtc_state->pixel_multiplier - 1)
7375                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7376         }
7377
7378         if (is_sdvo)
7379                 dpll |= DPLL_SDVO_HIGH_SPEED;
7380
7381         if (crtc_state->has_dp_encoder)
7382                 dpll |= DPLL_SDVO_HIGH_SPEED;
7383
7384         /* compute bitmask from p1 value */
7385         if (IS_PINEVIEW(dev))
7386                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7387         else {
7388                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7389                 if (IS_G4X(dev) && reduced_clock)
7390                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7391         }
7392         switch (clock->p2) {
7393         case 5:
7394                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7395                 break;
7396         case 7:
7397                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7398                 break;
7399         case 10:
7400                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7401                 break;
7402         case 14:
7403                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7404                 break;
7405         }
7406         if (INTEL_INFO(dev)->gen >= 4)
7407                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7408
7409         if (crtc_state->sdvo_tv_clock)
7410                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7411         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7412                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7413                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7414         else
7415                 dpll |= PLL_REF_INPUT_DREFCLK;
7416
7417         dpll |= DPLL_VCO_ENABLE;
7418         crtc_state->dpll_hw_state.dpll = dpll;
7419
7420         if (INTEL_INFO(dev)->gen >= 4) {
7421                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7422                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7423                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7424         }
7425 }
7426
7427 static void i8xx_update_pll(struct intel_crtc *crtc,
7428                             struct intel_crtc_state *crtc_state,
7429                             intel_clock_t *reduced_clock,
7430                             int num_connectors)
7431 {
7432         struct drm_device *dev = crtc->base.dev;
7433         struct drm_i915_private *dev_priv = dev->dev_private;
7434         u32 dpll;
7435         struct dpll *clock = &crtc_state->dpll;
7436
7437         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7438
7439         dpll = DPLL_VGA_MODE_DIS;
7440
7441         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7442                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7443         } else {
7444                 if (clock->p1 == 2)
7445                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7446                 else
7447                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7448                 if (clock->p2 == 4)
7449                         dpll |= PLL_P2_DIVIDE_BY_4;
7450         }
7451
7452         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7453                 dpll |= DPLL_DVO_2X_MODE;
7454
7455         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7456                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7457                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7458         else
7459                 dpll |= PLL_REF_INPUT_DREFCLK;
7460
7461         dpll |= DPLL_VCO_ENABLE;
7462         crtc_state->dpll_hw_state.dpll = dpll;
7463 }
7464
7465 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7466 {
7467         struct drm_device *dev = intel_crtc->base.dev;
7468         struct drm_i915_private *dev_priv = dev->dev_private;
7469         enum pipe pipe = intel_crtc->pipe;
7470         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7471         struct drm_display_mode *adjusted_mode =
7472                 &intel_crtc->config->base.adjusted_mode;
7473         uint32_t crtc_vtotal, crtc_vblank_end;
7474         int vsyncshift = 0;
7475
7476         /* We need to be careful not to changed the adjusted mode, for otherwise
7477          * the hw state checker will get angry at the mismatch. */
7478         crtc_vtotal = adjusted_mode->crtc_vtotal;
7479         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7480
7481         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7482                 /* the chip adds 2 halflines automatically */
7483                 crtc_vtotal -= 1;
7484                 crtc_vblank_end -= 1;
7485
7486                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7487                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7488                 else
7489                         vsyncshift = adjusted_mode->crtc_hsync_start -
7490                                 adjusted_mode->crtc_htotal / 2;
7491                 if (vsyncshift < 0)
7492                         vsyncshift += adjusted_mode->crtc_htotal;
7493         }
7494
7495         if (INTEL_INFO(dev)->gen > 3)
7496                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7497
7498         I915_WRITE(HTOTAL(cpu_transcoder),
7499                    (adjusted_mode->crtc_hdisplay - 1) |
7500                    ((adjusted_mode->crtc_htotal - 1) << 16));
7501         I915_WRITE(HBLANK(cpu_transcoder),
7502                    (adjusted_mode->crtc_hblank_start - 1) |
7503                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7504         I915_WRITE(HSYNC(cpu_transcoder),
7505                    (adjusted_mode->crtc_hsync_start - 1) |
7506                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7507
7508         I915_WRITE(VTOTAL(cpu_transcoder),
7509                    (adjusted_mode->crtc_vdisplay - 1) |
7510                    ((crtc_vtotal - 1) << 16));
7511         I915_WRITE(VBLANK(cpu_transcoder),
7512                    (adjusted_mode->crtc_vblank_start - 1) |
7513                    ((crtc_vblank_end - 1) << 16));
7514         I915_WRITE(VSYNC(cpu_transcoder),
7515                    (adjusted_mode->crtc_vsync_start - 1) |
7516                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7517
7518         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7519          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7520          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7521          * bits. */
7522         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7523             (pipe == PIPE_B || pipe == PIPE_C))
7524                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7525
7526         /* pipesrc controls the size that is scaled from, which should
7527          * always be the user's requested size.
7528          */
7529         I915_WRITE(PIPESRC(pipe),
7530                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7531                    (intel_crtc->config->pipe_src_h - 1));
7532 }
7533
7534 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7535                                    struct intel_crtc_state *pipe_config)
7536 {
7537         struct drm_device *dev = crtc->base.dev;
7538         struct drm_i915_private *dev_priv = dev->dev_private;
7539         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7540         uint32_t tmp;
7541
7542         tmp = I915_READ(HTOTAL(cpu_transcoder));
7543         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7544         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7545         tmp = I915_READ(HBLANK(cpu_transcoder));
7546         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7547         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7548         tmp = I915_READ(HSYNC(cpu_transcoder));
7549         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7550         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7551
7552         tmp = I915_READ(VTOTAL(cpu_transcoder));
7553         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7554         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7555         tmp = I915_READ(VBLANK(cpu_transcoder));
7556         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7557         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7558         tmp = I915_READ(VSYNC(cpu_transcoder));
7559         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7560         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7561
7562         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7563                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7564                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7565                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7566         }
7567
7568         tmp = I915_READ(PIPESRC(crtc->pipe));
7569         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7570         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7571
7572         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7573         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7574 }
7575
7576 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7577                                  struct intel_crtc_state *pipe_config)
7578 {
7579         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7580         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7581         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7582         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7583
7584         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7585         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7586         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7587         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7588
7589         mode->flags = pipe_config->base.adjusted_mode.flags;
7590
7591         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7592         mode->flags |= pipe_config->base.adjusted_mode.flags;
7593 }
7594
7595 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7596 {
7597         struct drm_device *dev = intel_crtc->base.dev;
7598         struct drm_i915_private *dev_priv = dev->dev_private;
7599         uint32_t pipeconf;
7600
7601         pipeconf = 0;
7602
7603         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7604             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7605                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7606
7607         if (intel_crtc->config->double_wide)
7608                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7609
7610         /* only g4x and later have fancy bpc/dither controls */
7611         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7612                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7613                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7614                         pipeconf |= PIPECONF_DITHER_EN |
7615                                     PIPECONF_DITHER_TYPE_SP;
7616
7617                 switch (intel_crtc->config->pipe_bpp) {
7618                 case 18:
7619                         pipeconf |= PIPECONF_6BPC;
7620                         break;
7621                 case 24:
7622                         pipeconf |= PIPECONF_8BPC;
7623                         break;
7624                 case 30:
7625                         pipeconf |= PIPECONF_10BPC;
7626                         break;
7627                 default:
7628                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7629                         BUG();
7630                 }
7631         }
7632
7633         if (HAS_PIPE_CXSR(dev)) {
7634                 if (intel_crtc->lowfreq_avail) {
7635                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7636                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7637                 } else {
7638                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7639                 }
7640         }
7641
7642         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7643                 if (INTEL_INFO(dev)->gen < 4 ||
7644                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7645                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7646                 else
7647                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7648         } else
7649                 pipeconf |= PIPECONF_PROGRESSIVE;
7650
7651         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7652                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7653
7654         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7655         POSTING_READ(PIPECONF(intel_crtc->pipe));
7656 }
7657
7658 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7659                                    struct intel_crtc_state *crtc_state)
7660 {
7661         struct drm_device *dev = crtc->base.dev;
7662         struct drm_i915_private *dev_priv = dev->dev_private;
7663         int refclk, num_connectors = 0;
7664         intel_clock_t clock, reduced_clock;
7665         bool ok, has_reduced_clock = false;
7666         bool is_lvds = false, is_dsi = false;
7667         struct intel_encoder *encoder;
7668         const intel_limit_t *limit;
7669         struct drm_atomic_state *state = crtc_state->base.state;
7670         struct drm_connector *connector;
7671         struct drm_connector_state *connector_state;
7672         int i;
7673
7674         memset(&crtc_state->dpll_hw_state, 0,
7675                sizeof(crtc_state->dpll_hw_state));
7676
7677         for_each_connector_in_state(state, connector, connector_state, i) {
7678                 if (connector_state->crtc != &crtc->base)
7679                         continue;
7680
7681                 encoder = to_intel_encoder(connector_state->best_encoder);
7682
7683                 switch (encoder->type) {
7684                 case INTEL_OUTPUT_LVDS:
7685                         is_lvds = true;
7686                         break;
7687                 case INTEL_OUTPUT_DSI:
7688                         is_dsi = true;
7689                         break;
7690                 default:
7691                         break;
7692                 }
7693
7694                 num_connectors++;
7695         }
7696
7697         if (is_dsi)
7698                 return 0;
7699
7700         if (!crtc_state->clock_set) {
7701                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7702
7703                 /*
7704                  * Returns a set of divisors for the desired target clock with
7705                  * the given refclk, or FALSE.  The returned values represent
7706                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7707                  * 2) / p1 / p2.
7708                  */
7709                 limit = intel_limit(crtc_state, refclk);
7710                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7711                                                  crtc_state->port_clock,
7712                                                  refclk, NULL, &clock);
7713                 if (!ok) {
7714                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7715                         return -EINVAL;
7716                 }
7717
7718                 if (is_lvds && dev_priv->lvds_downclock_avail) {
7719                         /*
7720                          * Ensure we match the reduced clock's P to the target
7721                          * clock.  If the clocks don't match, we can't switch
7722                          * the display clock by using the FP0/FP1. In such case
7723                          * we will disable the LVDS downclock feature.
7724                          */
7725                         has_reduced_clock =
7726                                 dev_priv->display.find_dpll(limit, crtc_state,
7727                                                             dev_priv->lvds_downclock,
7728                                                             refclk, &clock,
7729                                                             &reduced_clock);
7730                 }
7731                 /* Compat-code for transition, will disappear. */
7732                 crtc_state->dpll.n = clock.n;
7733                 crtc_state->dpll.m1 = clock.m1;
7734                 crtc_state->dpll.m2 = clock.m2;
7735                 crtc_state->dpll.p1 = clock.p1;
7736                 crtc_state->dpll.p2 = clock.p2;
7737         }
7738
7739         if (IS_GEN2(dev)) {
7740                 i8xx_update_pll(crtc, crtc_state,
7741                                 has_reduced_clock ? &reduced_clock : NULL,
7742                                 num_connectors);
7743         } else if (IS_CHERRYVIEW(dev)) {
7744                 chv_update_pll(crtc, crtc_state);
7745         } else if (IS_VALLEYVIEW(dev)) {
7746                 vlv_update_pll(crtc, crtc_state);
7747         } else {
7748                 i9xx_update_pll(crtc, crtc_state,
7749                                 has_reduced_clock ? &reduced_clock : NULL,
7750                                 num_connectors);
7751         }
7752
7753         return 0;
7754 }
7755
7756 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7757                                  struct intel_crtc_state *pipe_config)
7758 {
7759         struct drm_device *dev = crtc->base.dev;
7760         struct drm_i915_private *dev_priv = dev->dev_private;
7761         uint32_t tmp;
7762
7763         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7764                 return;
7765
7766         tmp = I915_READ(PFIT_CONTROL);
7767         if (!(tmp & PFIT_ENABLE))
7768                 return;
7769
7770         /* Check whether the pfit is attached to our pipe. */
7771         if (INTEL_INFO(dev)->gen < 4) {
7772                 if (crtc->pipe != PIPE_B)
7773                         return;
7774         } else {
7775                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7776                         return;
7777         }
7778
7779         pipe_config->gmch_pfit.control = tmp;
7780         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7781         if (INTEL_INFO(dev)->gen < 5)
7782                 pipe_config->gmch_pfit.lvds_border_bits =
7783                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7784 }
7785
7786 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7787                                struct intel_crtc_state *pipe_config)
7788 {
7789         struct drm_device *dev = crtc->base.dev;
7790         struct drm_i915_private *dev_priv = dev->dev_private;
7791         int pipe = pipe_config->cpu_transcoder;
7792         intel_clock_t clock;
7793         u32 mdiv;
7794         int refclk = 100000;
7795
7796         /* In case of MIPI DPLL will not even be used */
7797         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7798                 return;
7799
7800         mutex_lock(&dev_priv->sb_lock);
7801         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7802         mutex_unlock(&dev_priv->sb_lock);
7803
7804         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7805         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7806         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7807         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7808         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7809
7810         vlv_clock(refclk, &clock);
7811
7812         /* clock.dot is the fast clock */
7813         pipe_config->port_clock = clock.dot / 5;
7814 }
7815
7816 static void
7817 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7818                               struct intel_initial_plane_config *plane_config)
7819 {
7820         struct drm_device *dev = crtc->base.dev;
7821         struct drm_i915_private *dev_priv = dev->dev_private;
7822         u32 val, base, offset;
7823         int pipe = crtc->pipe, plane = crtc->plane;
7824         int fourcc, pixel_format;
7825         unsigned int aligned_height;
7826         struct drm_framebuffer *fb;
7827         struct intel_framebuffer *intel_fb;
7828
7829         val = I915_READ(DSPCNTR(plane));
7830         if (!(val & DISPLAY_PLANE_ENABLE))
7831                 return;
7832
7833         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7834         if (!intel_fb) {
7835                 DRM_DEBUG_KMS("failed to alloc fb\n");
7836                 return;
7837         }
7838
7839         fb = &intel_fb->base;
7840
7841         if (INTEL_INFO(dev)->gen >= 4) {
7842                 if (val & DISPPLANE_TILED) {
7843                         plane_config->tiling = I915_TILING_X;
7844                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7845                 }
7846         }
7847
7848         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7849         fourcc = i9xx_format_to_fourcc(pixel_format);
7850         fb->pixel_format = fourcc;
7851         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7852
7853         if (INTEL_INFO(dev)->gen >= 4) {
7854                 if (plane_config->tiling)
7855                         offset = I915_READ(DSPTILEOFF(plane));
7856                 else
7857                         offset = I915_READ(DSPLINOFF(plane));
7858                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7859         } else {
7860                 base = I915_READ(DSPADDR(plane));
7861         }
7862         plane_config->base = base;
7863
7864         val = I915_READ(PIPESRC(pipe));
7865         fb->width = ((val >> 16) & 0xfff) + 1;
7866         fb->height = ((val >> 0) & 0xfff) + 1;
7867
7868         val = I915_READ(DSPSTRIDE(pipe));
7869         fb->pitches[0] = val & 0xffffffc0;
7870
7871         aligned_height = intel_fb_align_height(dev, fb->height,
7872                                                fb->pixel_format,
7873                                                fb->modifier[0]);
7874
7875         plane_config->size = fb->pitches[0] * aligned_height;
7876
7877         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7878                       pipe_name(pipe), plane, fb->width, fb->height,
7879                       fb->bits_per_pixel, base, fb->pitches[0],
7880                       plane_config->size);
7881
7882         plane_config->fb = intel_fb;
7883 }
7884
7885 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7886                                struct intel_crtc_state *pipe_config)
7887 {
7888         struct drm_device *dev = crtc->base.dev;
7889         struct drm_i915_private *dev_priv = dev->dev_private;
7890         int pipe = pipe_config->cpu_transcoder;
7891         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7892         intel_clock_t clock;
7893         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7894         int refclk = 100000;
7895
7896         mutex_lock(&dev_priv->sb_lock);
7897         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7898         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7899         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7900         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7901         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7902         mutex_unlock(&dev_priv->sb_lock);
7903
7904         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7905         clock.m2 = (pll_dw0 & 0xff) << 22;
7906         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7907                 clock.m2 |= pll_dw2 & 0x3fffff;
7908         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7909         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7910         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7911
7912         chv_clock(refclk, &clock);
7913
7914         /* clock.dot is the fast clock */
7915         pipe_config->port_clock = clock.dot / 5;
7916 }
7917
7918 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7919                                  struct intel_crtc_state *pipe_config)
7920 {
7921         struct drm_device *dev = crtc->base.dev;
7922         struct drm_i915_private *dev_priv = dev->dev_private;
7923         uint32_t tmp;
7924
7925         if (!intel_display_power_is_enabled(dev_priv,
7926                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7927                 return false;
7928
7929         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7930         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7931
7932         tmp = I915_READ(PIPECONF(crtc->pipe));
7933         if (!(tmp & PIPECONF_ENABLE))
7934                 return false;
7935
7936         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7937                 switch (tmp & PIPECONF_BPC_MASK) {
7938                 case PIPECONF_6BPC:
7939                         pipe_config->pipe_bpp = 18;
7940                         break;
7941                 case PIPECONF_8BPC:
7942                         pipe_config->pipe_bpp = 24;
7943                         break;
7944                 case PIPECONF_10BPC:
7945                         pipe_config->pipe_bpp = 30;
7946                         break;
7947                 default:
7948                         break;
7949                 }
7950         }
7951
7952         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7953                 pipe_config->limited_color_range = true;
7954
7955         if (INTEL_INFO(dev)->gen < 4)
7956                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7957
7958         intel_get_pipe_timings(crtc, pipe_config);
7959
7960         i9xx_get_pfit_config(crtc, pipe_config);
7961
7962         if (INTEL_INFO(dev)->gen >= 4) {
7963                 tmp = I915_READ(DPLL_MD(crtc->pipe));
7964                 pipe_config->pixel_multiplier =
7965                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7966                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7967                 pipe_config->dpll_hw_state.dpll_md = tmp;
7968         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7969                 tmp = I915_READ(DPLL(crtc->pipe));
7970                 pipe_config->pixel_multiplier =
7971                         ((tmp & SDVO_MULTIPLIER_MASK)
7972                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7973         } else {
7974                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7975                  * port and will be fixed up in the encoder->get_config
7976                  * function. */
7977                 pipe_config->pixel_multiplier = 1;
7978         }
7979         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7980         if (!IS_VALLEYVIEW(dev)) {
7981                 /*
7982                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7983                  * on 830. Filter it out here so that we don't
7984                  * report errors due to that.
7985                  */
7986                 if (IS_I830(dev))
7987                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7988
7989                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7990                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7991         } else {
7992                 /* Mask out read-only status bits. */
7993                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7994                                                      DPLL_PORTC_READY_MASK |
7995                                                      DPLL_PORTB_READY_MASK);
7996         }
7997
7998         if (IS_CHERRYVIEW(dev))
7999                 chv_crtc_clock_get(crtc, pipe_config);
8000         else if (IS_VALLEYVIEW(dev))
8001                 vlv_crtc_clock_get(crtc, pipe_config);
8002         else
8003                 i9xx_crtc_clock_get(crtc, pipe_config);
8004
8005         return true;
8006 }
8007
8008 static void ironlake_init_pch_refclk(struct drm_device *dev)
8009 {
8010         struct drm_i915_private *dev_priv = dev->dev_private;
8011         struct intel_encoder *encoder;
8012         u32 val, final;
8013         bool has_lvds = false;
8014         bool has_cpu_edp = false;
8015         bool has_panel = false;
8016         bool has_ck505 = false;
8017         bool can_ssc = false;
8018
8019         /* We need to take the global config into account */
8020         for_each_intel_encoder(dev, encoder) {
8021                 switch (encoder->type) {
8022                 case INTEL_OUTPUT_LVDS:
8023                         has_panel = true;
8024                         has_lvds = true;
8025                         break;
8026                 case INTEL_OUTPUT_EDP:
8027                         has_panel = true;
8028                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8029                                 has_cpu_edp = true;
8030                         break;
8031                 default:
8032                         break;
8033                 }
8034         }
8035
8036         if (HAS_PCH_IBX(dev)) {
8037                 has_ck505 = dev_priv->vbt.display_clock_mode;
8038                 can_ssc = has_ck505;
8039         } else {
8040                 has_ck505 = false;
8041                 can_ssc = true;
8042         }
8043
8044         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8045                       has_panel, has_lvds, has_ck505);
8046
8047         /* Ironlake: try to setup display ref clock before DPLL
8048          * enabling. This is only under driver's control after
8049          * PCH B stepping, previous chipset stepping should be
8050          * ignoring this setting.
8051          */
8052         val = I915_READ(PCH_DREF_CONTROL);
8053
8054         /* As we must carefully and slowly disable/enable each source in turn,
8055          * compute the final state we want first and check if we need to
8056          * make any changes at all.
8057          */
8058         final = val;
8059         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8060         if (has_ck505)
8061                 final |= DREF_NONSPREAD_CK505_ENABLE;
8062         else
8063                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8064
8065         final &= ~DREF_SSC_SOURCE_MASK;
8066         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8067         final &= ~DREF_SSC1_ENABLE;
8068
8069         if (has_panel) {
8070                 final |= DREF_SSC_SOURCE_ENABLE;
8071
8072                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8073                         final |= DREF_SSC1_ENABLE;
8074
8075                 if (has_cpu_edp) {
8076                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8077                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8078                         else
8079                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8080                 } else
8081                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8082         } else {
8083                 final |= DREF_SSC_SOURCE_DISABLE;
8084                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8085         }
8086
8087         if (final == val)
8088                 return;
8089
8090         /* Always enable nonspread source */
8091         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8092
8093         if (has_ck505)
8094                 val |= DREF_NONSPREAD_CK505_ENABLE;
8095         else
8096                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8097
8098         if (has_panel) {
8099                 val &= ~DREF_SSC_SOURCE_MASK;
8100                 val |= DREF_SSC_SOURCE_ENABLE;
8101
8102                 /* SSC must be turned on before enabling the CPU output  */
8103                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8104                         DRM_DEBUG_KMS("Using SSC on panel\n");
8105                         val |= DREF_SSC1_ENABLE;
8106                 } else
8107                         val &= ~DREF_SSC1_ENABLE;
8108
8109                 /* Get SSC going before enabling the outputs */
8110                 I915_WRITE(PCH_DREF_CONTROL, val);
8111                 POSTING_READ(PCH_DREF_CONTROL);
8112                 udelay(200);
8113
8114                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8115
8116                 /* Enable CPU source on CPU attached eDP */
8117                 if (has_cpu_edp) {
8118                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8119                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8120                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8121                         } else
8122                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8123                 } else
8124                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8125
8126                 I915_WRITE(PCH_DREF_CONTROL, val);
8127                 POSTING_READ(PCH_DREF_CONTROL);
8128                 udelay(200);
8129         } else {
8130                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8131
8132                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8133
8134                 /* Turn off CPU output */
8135                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8136
8137                 I915_WRITE(PCH_DREF_CONTROL, val);
8138                 POSTING_READ(PCH_DREF_CONTROL);
8139                 udelay(200);
8140
8141                 /* Turn off the SSC source */
8142                 val &= ~DREF_SSC_SOURCE_MASK;
8143                 val |= DREF_SSC_SOURCE_DISABLE;
8144
8145                 /* Turn off SSC1 */
8146                 val &= ~DREF_SSC1_ENABLE;
8147
8148                 I915_WRITE(PCH_DREF_CONTROL, val);
8149                 POSTING_READ(PCH_DREF_CONTROL);
8150                 udelay(200);
8151         }
8152
8153         BUG_ON(val != final);
8154 }
8155
8156 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8157 {
8158         uint32_t tmp;
8159
8160         tmp = I915_READ(SOUTH_CHICKEN2);
8161         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8162         I915_WRITE(SOUTH_CHICKEN2, tmp);
8163
8164         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8165                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8166                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8167
8168         tmp = I915_READ(SOUTH_CHICKEN2);
8169         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8170         I915_WRITE(SOUTH_CHICKEN2, tmp);
8171
8172         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8173                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8174                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8175 }
8176
8177 /* WaMPhyProgramming:hsw */
8178 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8179 {
8180         uint32_t tmp;
8181
8182         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8183         tmp &= ~(0xFF << 24);
8184         tmp |= (0x12 << 24);
8185         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8186
8187         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8188         tmp |= (1 << 11);
8189         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8190
8191         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8192         tmp |= (1 << 11);
8193         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8194
8195         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8196         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8197         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8198
8199         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8200         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8201         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8202
8203         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8204         tmp &= ~(7 << 13);
8205         tmp |= (5 << 13);
8206         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8207
8208         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8209         tmp &= ~(7 << 13);
8210         tmp |= (5 << 13);
8211         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8212
8213         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8214         tmp &= ~0xFF;
8215         tmp |= 0x1C;
8216         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8217
8218         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8219         tmp &= ~0xFF;
8220         tmp |= 0x1C;
8221         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8222
8223         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8224         tmp &= ~(0xFF << 16);
8225         tmp |= (0x1C << 16);
8226         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8227
8228         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8229         tmp &= ~(0xFF << 16);
8230         tmp |= (0x1C << 16);
8231         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8232
8233         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8234         tmp |= (1 << 27);
8235         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8236
8237         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8238         tmp |= (1 << 27);
8239         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8240
8241         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8242         tmp &= ~(0xF << 28);
8243         tmp |= (4 << 28);
8244         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8245
8246         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8247         tmp &= ~(0xF << 28);
8248         tmp |= (4 << 28);
8249         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8250 }
8251
8252 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8253  * Programming" based on the parameters passed:
8254  * - Sequence to enable CLKOUT_DP
8255  * - Sequence to enable CLKOUT_DP without spread
8256  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8257  */
8258 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8259                                  bool with_fdi)
8260 {
8261         struct drm_i915_private *dev_priv = dev->dev_private;
8262         uint32_t reg, tmp;
8263
8264         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8265                 with_spread = true;
8266         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8267                  with_fdi, "LP PCH doesn't have FDI\n"))
8268                 with_fdi = false;
8269
8270         mutex_lock(&dev_priv->sb_lock);
8271
8272         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8273         tmp &= ~SBI_SSCCTL_DISABLE;
8274         tmp |= SBI_SSCCTL_PATHALT;
8275         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8276
8277         udelay(24);
8278
8279         if (with_spread) {
8280                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8281                 tmp &= ~SBI_SSCCTL_PATHALT;
8282                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8283
8284                 if (with_fdi) {
8285                         lpt_reset_fdi_mphy(dev_priv);
8286                         lpt_program_fdi_mphy(dev_priv);
8287                 }
8288         }
8289
8290         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8291                SBI_GEN0 : SBI_DBUFF0;
8292         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8293         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8294         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8295
8296         mutex_unlock(&dev_priv->sb_lock);
8297 }
8298
8299 /* Sequence to disable CLKOUT_DP */
8300 static void lpt_disable_clkout_dp(struct drm_device *dev)
8301 {
8302         struct drm_i915_private *dev_priv = dev->dev_private;
8303         uint32_t reg, tmp;
8304
8305         mutex_lock(&dev_priv->sb_lock);
8306
8307         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8308                SBI_GEN0 : SBI_DBUFF0;
8309         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8310         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8311         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8312
8313         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8314         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8315                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8316                         tmp |= SBI_SSCCTL_PATHALT;
8317                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8318                         udelay(32);
8319                 }
8320                 tmp |= SBI_SSCCTL_DISABLE;
8321                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8322         }
8323
8324         mutex_unlock(&dev_priv->sb_lock);
8325 }
8326
8327 static void lpt_init_pch_refclk(struct drm_device *dev)
8328 {
8329         struct intel_encoder *encoder;
8330         bool has_vga = false;
8331
8332         for_each_intel_encoder(dev, encoder) {
8333                 switch (encoder->type) {
8334                 case INTEL_OUTPUT_ANALOG:
8335                         has_vga = true;
8336                         break;
8337                 default:
8338                         break;
8339                 }
8340         }
8341
8342         if (has_vga)
8343                 lpt_enable_clkout_dp(dev, true, true);
8344         else
8345                 lpt_disable_clkout_dp(dev);
8346 }
8347
8348 /*
8349  * Initialize reference clocks when the driver loads
8350  */
8351 void intel_init_pch_refclk(struct drm_device *dev)
8352 {
8353         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8354                 ironlake_init_pch_refclk(dev);
8355         else if (HAS_PCH_LPT(dev))
8356                 lpt_init_pch_refclk(dev);
8357 }
8358
8359 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8360 {
8361         struct drm_device *dev = crtc_state->base.crtc->dev;
8362         struct drm_i915_private *dev_priv = dev->dev_private;
8363         struct drm_atomic_state *state = crtc_state->base.state;
8364         struct drm_connector *connector;
8365         struct drm_connector_state *connector_state;
8366         struct intel_encoder *encoder;
8367         int num_connectors = 0, i;
8368         bool is_lvds = false;
8369
8370         for_each_connector_in_state(state, connector, connector_state, i) {
8371                 if (connector_state->crtc != crtc_state->base.crtc)
8372                         continue;
8373
8374                 encoder = to_intel_encoder(connector_state->best_encoder);
8375
8376                 switch (encoder->type) {
8377                 case INTEL_OUTPUT_LVDS:
8378                         is_lvds = true;
8379                         break;
8380                 default:
8381                         break;
8382                 }
8383                 num_connectors++;
8384         }
8385
8386         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8387                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8388                               dev_priv->vbt.lvds_ssc_freq);
8389                 return dev_priv->vbt.lvds_ssc_freq;
8390         }
8391
8392         return 120000;
8393 }
8394
8395 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8396 {
8397         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8399         int pipe = intel_crtc->pipe;
8400         uint32_t val;
8401
8402         val = 0;
8403
8404         switch (intel_crtc->config->pipe_bpp) {
8405         case 18:
8406                 val |= PIPECONF_6BPC;
8407                 break;
8408         case 24:
8409                 val |= PIPECONF_8BPC;
8410                 break;
8411         case 30:
8412                 val |= PIPECONF_10BPC;
8413                 break;
8414         case 36:
8415                 val |= PIPECONF_12BPC;
8416                 break;
8417         default:
8418                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8419                 BUG();
8420         }
8421
8422         if (intel_crtc->config->dither)
8423                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8424
8425         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8426                 val |= PIPECONF_INTERLACED_ILK;
8427         else
8428                 val |= PIPECONF_PROGRESSIVE;
8429
8430         if (intel_crtc->config->limited_color_range)
8431                 val |= PIPECONF_COLOR_RANGE_SELECT;
8432
8433         I915_WRITE(PIPECONF(pipe), val);
8434         POSTING_READ(PIPECONF(pipe));
8435 }
8436
8437 /*
8438  * Set up the pipe CSC unit.
8439  *
8440  * Currently only full range RGB to limited range RGB conversion
8441  * is supported, but eventually this should handle various
8442  * RGB<->YCbCr scenarios as well.
8443  */
8444 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8445 {
8446         struct drm_device *dev = crtc->dev;
8447         struct drm_i915_private *dev_priv = dev->dev_private;
8448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8449         int pipe = intel_crtc->pipe;
8450         uint16_t coeff = 0x7800; /* 1.0 */
8451
8452         /*
8453          * TODO: Check what kind of values actually come out of the pipe
8454          * with these coeff/postoff values and adjust to get the best
8455          * accuracy. Perhaps we even need to take the bpc value into
8456          * consideration.
8457          */
8458
8459         if (intel_crtc->config->limited_color_range)
8460                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8461
8462         /*
8463          * GY/GU and RY/RU should be the other way around according
8464          * to BSpec, but reality doesn't agree. Just set them up in
8465          * a way that results in the correct picture.
8466          */
8467         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8468         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8469
8470         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8471         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8472
8473         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8474         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8475
8476         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8477         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8478         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8479
8480         if (INTEL_INFO(dev)->gen > 6) {
8481                 uint16_t postoff = 0;
8482
8483                 if (intel_crtc->config->limited_color_range)
8484                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8485
8486                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8487                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8488                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8489
8490                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8491         } else {
8492                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8493
8494                 if (intel_crtc->config->limited_color_range)
8495                         mode |= CSC_BLACK_SCREEN_OFFSET;
8496
8497                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8498         }
8499 }
8500
8501 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8502 {
8503         struct drm_device *dev = crtc->dev;
8504         struct drm_i915_private *dev_priv = dev->dev_private;
8505         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8506         enum pipe pipe = intel_crtc->pipe;
8507         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8508         uint32_t val;
8509
8510         val = 0;
8511
8512         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8513                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8514
8515         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8516                 val |= PIPECONF_INTERLACED_ILK;
8517         else
8518                 val |= PIPECONF_PROGRESSIVE;
8519
8520         I915_WRITE(PIPECONF(cpu_transcoder), val);
8521         POSTING_READ(PIPECONF(cpu_transcoder));
8522
8523         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8524         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8525
8526         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8527                 val = 0;
8528
8529                 switch (intel_crtc->config->pipe_bpp) {
8530                 case 18:
8531                         val |= PIPEMISC_DITHER_6_BPC;
8532                         break;
8533                 case 24:
8534                         val |= PIPEMISC_DITHER_8_BPC;
8535                         break;
8536                 case 30:
8537                         val |= PIPEMISC_DITHER_10_BPC;
8538                         break;
8539                 case 36:
8540                         val |= PIPEMISC_DITHER_12_BPC;
8541                         break;
8542                 default:
8543                         /* Case prevented by pipe_config_set_bpp. */
8544                         BUG();
8545                 }
8546
8547                 if (intel_crtc->config->dither)
8548                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8549
8550                 I915_WRITE(PIPEMISC(pipe), val);
8551         }
8552 }
8553
8554 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8555                                     struct intel_crtc_state *crtc_state,
8556                                     intel_clock_t *clock,
8557                                     bool *has_reduced_clock,
8558                                     intel_clock_t *reduced_clock)
8559 {
8560         struct drm_device *dev = crtc->dev;
8561         struct drm_i915_private *dev_priv = dev->dev_private;
8562         int refclk;
8563         const intel_limit_t *limit;
8564         bool ret, is_lvds = false;
8565
8566         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8567
8568         refclk = ironlake_get_refclk(crtc_state);
8569
8570         /*
8571          * Returns a set of divisors for the desired target clock with the given
8572          * refclk, or FALSE.  The returned values represent the clock equation:
8573          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8574          */
8575         limit = intel_limit(crtc_state, refclk);
8576         ret = dev_priv->display.find_dpll(limit, crtc_state,
8577                                           crtc_state->port_clock,
8578                                           refclk, NULL, clock);
8579         if (!ret)
8580                 return false;
8581
8582         if (is_lvds && dev_priv->lvds_downclock_avail) {
8583                 /*
8584                  * Ensure we match the reduced clock's P to the target clock.
8585                  * If the clocks don't match, we can't switch the display clock
8586                  * by using the FP0/FP1. In such case we will disable the LVDS
8587                  * downclock feature.
8588                 */
8589                 *has_reduced_clock =
8590                         dev_priv->display.find_dpll(limit, crtc_state,
8591                                                     dev_priv->lvds_downclock,
8592                                                     refclk, clock,
8593                                                     reduced_clock);
8594         }
8595
8596         return true;
8597 }
8598
8599 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8600 {
8601         /*
8602          * Account for spread spectrum to avoid
8603          * oversubscribing the link. Max center spread
8604          * is 2.5%; use 5% for safety's sake.
8605          */
8606         u32 bps = target_clock * bpp * 21 / 20;
8607         return DIV_ROUND_UP(bps, link_bw * 8);
8608 }
8609
8610 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8611 {
8612         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8613 }
8614
8615 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8616                                       struct intel_crtc_state *crtc_state,
8617                                       u32 *fp,
8618                                       intel_clock_t *reduced_clock, u32 *fp2)
8619 {
8620         struct drm_crtc *crtc = &intel_crtc->base;
8621         struct drm_device *dev = crtc->dev;
8622         struct drm_i915_private *dev_priv = dev->dev_private;
8623         struct drm_atomic_state *state = crtc_state->base.state;
8624         struct drm_connector *connector;
8625         struct drm_connector_state *connector_state;
8626         struct intel_encoder *encoder;
8627         uint32_t dpll;
8628         int factor, num_connectors = 0, i;
8629         bool is_lvds = false, is_sdvo = false;
8630
8631         for_each_connector_in_state(state, connector, connector_state, i) {
8632                 if (connector_state->crtc != crtc_state->base.crtc)
8633                         continue;
8634
8635                 encoder = to_intel_encoder(connector_state->best_encoder);
8636
8637                 switch (encoder->type) {
8638                 case INTEL_OUTPUT_LVDS:
8639                         is_lvds = true;
8640                         break;
8641                 case INTEL_OUTPUT_SDVO:
8642                 case INTEL_OUTPUT_HDMI:
8643                         is_sdvo = true;
8644                         break;
8645                 default:
8646                         break;
8647                 }
8648
8649                 num_connectors++;
8650         }
8651
8652         /* Enable autotuning of the PLL clock (if permissible) */
8653         factor = 21;
8654         if (is_lvds) {
8655                 if ((intel_panel_use_ssc(dev_priv) &&
8656                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8657                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8658                         factor = 25;
8659         } else if (crtc_state->sdvo_tv_clock)
8660                 factor = 20;
8661
8662         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8663                 *fp |= FP_CB_TUNE;
8664
8665         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8666                 *fp2 |= FP_CB_TUNE;
8667
8668         dpll = 0;
8669
8670         if (is_lvds)
8671                 dpll |= DPLLB_MODE_LVDS;
8672         else
8673                 dpll |= DPLLB_MODE_DAC_SERIAL;
8674
8675         dpll |= (crtc_state->pixel_multiplier - 1)
8676                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8677
8678         if (is_sdvo)
8679                 dpll |= DPLL_SDVO_HIGH_SPEED;
8680         if (crtc_state->has_dp_encoder)
8681                 dpll |= DPLL_SDVO_HIGH_SPEED;
8682
8683         /* compute bitmask from p1 value */
8684         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8685         /* also FPA1 */
8686         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8687
8688         switch (crtc_state->dpll.p2) {
8689         case 5:
8690                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8691                 break;
8692         case 7:
8693                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8694                 break;
8695         case 10:
8696                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8697                 break;
8698         case 14:
8699                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8700                 break;
8701         }
8702
8703         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8704                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8705         else
8706                 dpll |= PLL_REF_INPUT_DREFCLK;
8707
8708         return dpll | DPLL_VCO_ENABLE;
8709 }
8710
8711 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8712                                        struct intel_crtc_state *crtc_state)
8713 {
8714         struct drm_device *dev = crtc->base.dev;
8715         intel_clock_t clock, reduced_clock;
8716         u32 dpll = 0, fp = 0, fp2 = 0;
8717         bool ok, has_reduced_clock = false;
8718         bool is_lvds = false;
8719         struct intel_shared_dpll *pll;
8720
8721         memset(&crtc_state->dpll_hw_state, 0,
8722                sizeof(crtc_state->dpll_hw_state));
8723
8724         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8725
8726         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8727              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8728
8729         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8730                                      &has_reduced_clock, &reduced_clock);
8731         if (!ok && !crtc_state->clock_set) {
8732                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8733                 return -EINVAL;
8734         }
8735         /* Compat-code for transition, will disappear. */
8736         if (!crtc_state->clock_set) {
8737                 crtc_state->dpll.n = clock.n;
8738                 crtc_state->dpll.m1 = clock.m1;
8739                 crtc_state->dpll.m2 = clock.m2;
8740                 crtc_state->dpll.p1 = clock.p1;
8741                 crtc_state->dpll.p2 = clock.p2;
8742         }
8743
8744         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8745         if (crtc_state->has_pch_encoder) {
8746                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8747                 if (has_reduced_clock)
8748                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8749
8750                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8751                                              &fp, &reduced_clock,
8752                                              has_reduced_clock ? &fp2 : NULL);
8753
8754                 crtc_state->dpll_hw_state.dpll = dpll;
8755                 crtc_state->dpll_hw_state.fp0 = fp;
8756                 if (has_reduced_clock)
8757                         crtc_state->dpll_hw_state.fp1 = fp2;
8758                 else
8759                         crtc_state->dpll_hw_state.fp1 = fp;
8760
8761                 pll = intel_get_shared_dpll(crtc, crtc_state);
8762                 if (pll == NULL) {
8763                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8764                                          pipe_name(crtc->pipe));
8765                         return -EINVAL;
8766                 }
8767         }
8768
8769         if (is_lvds && has_reduced_clock)
8770                 crtc->lowfreq_avail = true;
8771         else
8772                 crtc->lowfreq_avail = false;
8773
8774         return 0;
8775 }
8776
8777 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8778                                          struct intel_link_m_n *m_n)
8779 {
8780         struct drm_device *dev = crtc->base.dev;
8781         struct drm_i915_private *dev_priv = dev->dev_private;
8782         enum pipe pipe = crtc->pipe;
8783
8784         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8785         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8786         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8787                 & ~TU_SIZE_MASK;
8788         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8789         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8790                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8791 }
8792
8793 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8794                                          enum transcoder transcoder,
8795                                          struct intel_link_m_n *m_n,
8796                                          struct intel_link_m_n *m2_n2)
8797 {
8798         struct drm_device *dev = crtc->base.dev;
8799         struct drm_i915_private *dev_priv = dev->dev_private;
8800         enum pipe pipe = crtc->pipe;
8801
8802         if (INTEL_INFO(dev)->gen >= 5) {
8803                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8804                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8805                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8806                         & ~TU_SIZE_MASK;
8807                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8808                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8809                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8810                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8811                  * gen < 8) and if DRRS is supported (to make sure the
8812                  * registers are not unnecessarily read).
8813                  */
8814                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8815                         crtc->config->has_drrs) {
8816                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8817                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8818                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8819                                         & ~TU_SIZE_MASK;
8820                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8821                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8822                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8823                 }
8824         } else {
8825                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8826                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8827                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8828                         & ~TU_SIZE_MASK;
8829                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8830                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8831                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8832         }
8833 }
8834
8835 void intel_dp_get_m_n(struct intel_crtc *crtc,
8836                       struct intel_crtc_state *pipe_config)
8837 {
8838         if (pipe_config->has_pch_encoder)
8839                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8840         else
8841                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8842                                              &pipe_config->dp_m_n,
8843                                              &pipe_config->dp_m2_n2);
8844 }
8845
8846 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8847                                         struct intel_crtc_state *pipe_config)
8848 {
8849         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8850                                      &pipe_config->fdi_m_n, NULL);
8851 }
8852
8853 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8854                                     struct intel_crtc_state *pipe_config)
8855 {
8856         struct drm_device *dev = crtc->base.dev;
8857         struct drm_i915_private *dev_priv = dev->dev_private;
8858         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8859         uint32_t ps_ctrl = 0;
8860         int id = -1;
8861         int i;
8862
8863         /* find scaler attached to this pipe */
8864         for (i = 0; i < crtc->num_scalers; i++) {
8865                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8866                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8867                         id = i;
8868                         pipe_config->pch_pfit.enabled = true;
8869                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8870                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8871                         break;
8872                 }
8873         }
8874
8875         scaler_state->scaler_id = id;
8876         if (id >= 0) {
8877                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8878         } else {
8879                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8880         }
8881 }
8882
8883 static void
8884 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8885                                  struct intel_initial_plane_config *plane_config)
8886 {
8887         struct drm_device *dev = crtc->base.dev;
8888         struct drm_i915_private *dev_priv = dev->dev_private;
8889         u32 val, base, offset, stride_mult, tiling;
8890         int pipe = crtc->pipe;
8891         int fourcc, pixel_format;
8892         unsigned int aligned_height;
8893         struct drm_framebuffer *fb;
8894         struct intel_framebuffer *intel_fb;
8895
8896         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8897         if (!intel_fb) {
8898                 DRM_DEBUG_KMS("failed to alloc fb\n");
8899                 return;
8900         }
8901
8902         fb = &intel_fb->base;
8903
8904         val = I915_READ(PLANE_CTL(pipe, 0));
8905         if (!(val & PLANE_CTL_ENABLE))
8906                 goto error;
8907
8908         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8909         fourcc = skl_format_to_fourcc(pixel_format,
8910                                       val & PLANE_CTL_ORDER_RGBX,
8911                                       val & PLANE_CTL_ALPHA_MASK);
8912         fb->pixel_format = fourcc;
8913         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8914
8915         tiling = val & PLANE_CTL_TILED_MASK;
8916         switch (tiling) {
8917         case PLANE_CTL_TILED_LINEAR:
8918                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8919                 break;
8920         case PLANE_CTL_TILED_X:
8921                 plane_config->tiling = I915_TILING_X;
8922                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8923                 break;
8924         case PLANE_CTL_TILED_Y:
8925                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8926                 break;
8927         case PLANE_CTL_TILED_YF:
8928                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8929                 break;
8930         default:
8931                 MISSING_CASE(tiling);
8932                 goto error;
8933         }
8934
8935         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8936         plane_config->base = base;
8937
8938         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8939
8940         val = I915_READ(PLANE_SIZE(pipe, 0));
8941         fb->height = ((val >> 16) & 0xfff) + 1;
8942         fb->width = ((val >> 0) & 0x1fff) + 1;
8943
8944         val = I915_READ(PLANE_STRIDE(pipe, 0));
8945         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8946                                                 fb->pixel_format);
8947         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8948
8949         aligned_height = intel_fb_align_height(dev, fb->height,
8950                                                fb->pixel_format,
8951                                                fb->modifier[0]);
8952
8953         plane_config->size = fb->pitches[0] * aligned_height;
8954
8955         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8956                       pipe_name(pipe), fb->width, fb->height,
8957                       fb->bits_per_pixel, base, fb->pitches[0],
8958                       plane_config->size);
8959
8960         plane_config->fb = intel_fb;
8961         return;
8962
8963 error:
8964         kfree(fb);
8965 }
8966
8967 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8968                                      struct intel_crtc_state *pipe_config)
8969 {
8970         struct drm_device *dev = crtc->base.dev;
8971         struct drm_i915_private *dev_priv = dev->dev_private;
8972         uint32_t tmp;
8973
8974         tmp = I915_READ(PF_CTL(crtc->pipe));
8975
8976         if (tmp & PF_ENABLE) {
8977                 pipe_config->pch_pfit.enabled = true;
8978                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8979                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8980
8981                 /* We currently do not free assignements of panel fitters on
8982                  * ivb/hsw (since we don't use the higher upscaling modes which
8983                  * differentiates them) so just WARN about this case for now. */
8984                 if (IS_GEN7(dev)) {
8985                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8986                                 PF_PIPE_SEL_IVB(crtc->pipe));
8987                 }
8988         }
8989 }
8990
8991 static void
8992 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8993                                   struct intel_initial_plane_config *plane_config)
8994 {
8995         struct drm_device *dev = crtc->base.dev;
8996         struct drm_i915_private *dev_priv = dev->dev_private;
8997         u32 val, base, offset;
8998         int pipe = crtc->pipe;
8999         int fourcc, pixel_format;
9000         unsigned int aligned_height;
9001         struct drm_framebuffer *fb;
9002         struct intel_framebuffer *intel_fb;
9003
9004         val = I915_READ(DSPCNTR(pipe));
9005         if (!(val & DISPLAY_PLANE_ENABLE))
9006                 return;
9007
9008         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9009         if (!intel_fb) {
9010                 DRM_DEBUG_KMS("failed to alloc fb\n");
9011                 return;
9012         }
9013
9014         fb = &intel_fb->base;
9015
9016         if (INTEL_INFO(dev)->gen >= 4) {
9017                 if (val & DISPPLANE_TILED) {
9018                         plane_config->tiling = I915_TILING_X;
9019                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9020                 }
9021         }
9022
9023         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9024         fourcc = i9xx_format_to_fourcc(pixel_format);
9025         fb->pixel_format = fourcc;
9026         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9027
9028         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9029         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9030                 offset = I915_READ(DSPOFFSET(pipe));
9031         } else {
9032                 if (plane_config->tiling)
9033                         offset = I915_READ(DSPTILEOFF(pipe));
9034                 else
9035                         offset = I915_READ(DSPLINOFF(pipe));
9036         }
9037         plane_config->base = base;
9038
9039         val = I915_READ(PIPESRC(pipe));
9040         fb->width = ((val >> 16) & 0xfff) + 1;
9041         fb->height = ((val >> 0) & 0xfff) + 1;
9042
9043         val = I915_READ(DSPSTRIDE(pipe));
9044         fb->pitches[0] = val & 0xffffffc0;
9045
9046         aligned_height = intel_fb_align_height(dev, fb->height,
9047                                                fb->pixel_format,
9048                                                fb->modifier[0]);
9049
9050         plane_config->size = fb->pitches[0] * aligned_height;
9051
9052         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9053                       pipe_name(pipe), fb->width, fb->height,
9054                       fb->bits_per_pixel, base, fb->pitches[0],
9055                       plane_config->size);
9056
9057         plane_config->fb = intel_fb;
9058 }
9059
9060 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9061                                      struct intel_crtc_state *pipe_config)
9062 {
9063         struct drm_device *dev = crtc->base.dev;
9064         struct drm_i915_private *dev_priv = dev->dev_private;
9065         uint32_t tmp;
9066
9067         if (!intel_display_power_is_enabled(dev_priv,
9068                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9069                 return false;
9070
9071         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9072         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9073
9074         tmp = I915_READ(PIPECONF(crtc->pipe));
9075         if (!(tmp & PIPECONF_ENABLE))
9076                 return false;
9077
9078         switch (tmp & PIPECONF_BPC_MASK) {
9079         case PIPECONF_6BPC:
9080                 pipe_config->pipe_bpp = 18;
9081                 break;
9082         case PIPECONF_8BPC:
9083                 pipe_config->pipe_bpp = 24;
9084                 break;
9085         case PIPECONF_10BPC:
9086                 pipe_config->pipe_bpp = 30;
9087                 break;
9088         case PIPECONF_12BPC:
9089                 pipe_config->pipe_bpp = 36;
9090                 break;
9091         default:
9092                 break;
9093         }
9094
9095         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9096                 pipe_config->limited_color_range = true;
9097
9098         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9099                 struct intel_shared_dpll *pll;
9100
9101                 pipe_config->has_pch_encoder = true;
9102
9103                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9104                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9105                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9106
9107                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9108
9109                 if (HAS_PCH_IBX(dev_priv->dev)) {
9110                         pipe_config->shared_dpll =
9111                                 (enum intel_dpll_id) crtc->pipe;
9112                 } else {
9113                         tmp = I915_READ(PCH_DPLL_SEL);
9114                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9115                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9116                         else
9117                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9118                 }
9119
9120                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9121
9122                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9123                                            &pipe_config->dpll_hw_state));
9124
9125                 tmp = pipe_config->dpll_hw_state.dpll;
9126                 pipe_config->pixel_multiplier =
9127                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9128                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9129
9130                 ironlake_pch_clock_get(crtc, pipe_config);
9131         } else {
9132                 pipe_config->pixel_multiplier = 1;
9133         }
9134
9135         intel_get_pipe_timings(crtc, pipe_config);
9136
9137         ironlake_get_pfit_config(crtc, pipe_config);
9138
9139         return true;
9140 }
9141
9142 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9143 {
9144         struct drm_device *dev = dev_priv->dev;
9145         struct intel_crtc *crtc;
9146
9147         for_each_intel_crtc(dev, crtc)
9148                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9149                      pipe_name(crtc->pipe));
9150
9151         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9152         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9153         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9154         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9155         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9156         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9157              "CPU PWM1 enabled\n");
9158         if (IS_HASWELL(dev))
9159                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9160                      "CPU PWM2 enabled\n");
9161         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9162              "PCH PWM1 enabled\n");
9163         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9164              "Utility pin enabled\n");
9165         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9166
9167         /*
9168          * In theory we can still leave IRQs enabled, as long as only the HPD
9169          * interrupts remain enabled. We used to check for that, but since it's
9170          * gen-specific and since we only disable LCPLL after we fully disable
9171          * the interrupts, the check below should be enough.
9172          */
9173         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9174 }
9175
9176 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9177 {
9178         struct drm_device *dev = dev_priv->dev;
9179
9180         if (IS_HASWELL(dev))
9181                 return I915_READ(D_COMP_HSW);
9182         else
9183                 return I915_READ(D_COMP_BDW);
9184 }
9185
9186 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9187 {
9188         struct drm_device *dev = dev_priv->dev;
9189
9190         if (IS_HASWELL(dev)) {
9191                 mutex_lock(&dev_priv->rps.hw_lock);
9192                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9193                                             val))
9194                         DRM_ERROR("Failed to write to D_COMP\n");
9195                 mutex_unlock(&dev_priv->rps.hw_lock);
9196         } else {
9197                 I915_WRITE(D_COMP_BDW, val);
9198                 POSTING_READ(D_COMP_BDW);
9199         }
9200 }
9201
9202 /*
9203  * This function implements pieces of two sequences from BSpec:
9204  * - Sequence for display software to disable LCPLL
9205  * - Sequence for display software to allow package C8+
9206  * The steps implemented here are just the steps that actually touch the LCPLL
9207  * register. Callers should take care of disabling all the display engine
9208  * functions, doing the mode unset, fixing interrupts, etc.
9209  */
9210 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9211                               bool switch_to_fclk, bool allow_power_down)
9212 {
9213         uint32_t val;
9214
9215         assert_can_disable_lcpll(dev_priv);
9216
9217         val = I915_READ(LCPLL_CTL);
9218
9219         if (switch_to_fclk) {
9220                 val |= LCPLL_CD_SOURCE_FCLK;
9221                 I915_WRITE(LCPLL_CTL, val);
9222
9223                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9224                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9225                         DRM_ERROR("Switching to FCLK failed\n");
9226
9227                 val = I915_READ(LCPLL_CTL);
9228         }
9229
9230         val |= LCPLL_PLL_DISABLE;
9231         I915_WRITE(LCPLL_CTL, val);
9232         POSTING_READ(LCPLL_CTL);
9233
9234         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9235                 DRM_ERROR("LCPLL still locked\n");
9236
9237         val = hsw_read_dcomp(dev_priv);
9238         val |= D_COMP_COMP_DISABLE;
9239         hsw_write_dcomp(dev_priv, val);
9240         ndelay(100);
9241
9242         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9243                      1))
9244                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9245
9246         if (allow_power_down) {
9247                 val = I915_READ(LCPLL_CTL);
9248                 val |= LCPLL_POWER_DOWN_ALLOW;
9249                 I915_WRITE(LCPLL_CTL, val);
9250                 POSTING_READ(LCPLL_CTL);
9251         }
9252 }
9253
9254 /*
9255  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9256  * source.
9257  */
9258 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9259 {
9260         uint32_t val;
9261
9262         val = I915_READ(LCPLL_CTL);
9263
9264         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9265                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9266                 return;
9267
9268         /*
9269          * Make sure we're not on PC8 state before disabling PC8, otherwise
9270          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9271          */
9272         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9273
9274         if (val & LCPLL_POWER_DOWN_ALLOW) {
9275                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9276                 I915_WRITE(LCPLL_CTL, val);
9277                 POSTING_READ(LCPLL_CTL);
9278         }
9279
9280         val = hsw_read_dcomp(dev_priv);
9281         val |= D_COMP_COMP_FORCE;
9282         val &= ~D_COMP_COMP_DISABLE;
9283         hsw_write_dcomp(dev_priv, val);
9284
9285         val = I915_READ(LCPLL_CTL);
9286         val &= ~LCPLL_PLL_DISABLE;
9287         I915_WRITE(LCPLL_CTL, val);
9288
9289         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9290                 DRM_ERROR("LCPLL not locked yet\n");
9291
9292         if (val & LCPLL_CD_SOURCE_FCLK) {
9293                 val = I915_READ(LCPLL_CTL);
9294                 val &= ~LCPLL_CD_SOURCE_FCLK;
9295                 I915_WRITE(LCPLL_CTL, val);
9296
9297                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9298                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9299                         DRM_ERROR("Switching back to LCPLL failed\n");
9300         }
9301
9302         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9303 }
9304
9305 /*
9306  * Package states C8 and deeper are really deep PC states that can only be
9307  * reached when all the devices on the system allow it, so even if the graphics
9308  * device allows PC8+, it doesn't mean the system will actually get to these
9309  * states. Our driver only allows PC8+ when going into runtime PM.
9310  *
9311  * The requirements for PC8+ are that all the outputs are disabled, the power
9312  * well is disabled and most interrupts are disabled, and these are also
9313  * requirements for runtime PM. When these conditions are met, we manually do
9314  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9315  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9316  * hang the machine.
9317  *
9318  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9319  * the state of some registers, so when we come back from PC8+ we need to
9320  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9321  * need to take care of the registers kept by RC6. Notice that this happens even
9322  * if we don't put the device in PCI D3 state (which is what currently happens
9323  * because of the runtime PM support).
9324  *
9325  * For more, read "Display Sequences for Package C8" on the hardware
9326  * documentation.
9327  */
9328 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9329 {
9330         struct drm_device *dev = dev_priv->dev;
9331         uint32_t val;
9332
9333         DRM_DEBUG_KMS("Enabling package C8+\n");
9334
9335         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9336                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9337                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9338                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9339         }
9340
9341         lpt_disable_clkout_dp(dev);
9342         hsw_disable_lcpll(dev_priv, true, true);
9343 }
9344
9345 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9346 {
9347         struct drm_device *dev = dev_priv->dev;
9348         uint32_t val;
9349
9350         DRM_DEBUG_KMS("Disabling package C8+\n");
9351
9352         hsw_restore_lcpll(dev_priv);
9353         lpt_init_pch_refclk(dev);
9354
9355         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9356                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9357                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9358                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9359         }
9360
9361         intel_prepare_ddi(dev);
9362 }
9363
9364 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9365 {
9366         struct drm_device *dev = old_state->dev;
9367         struct drm_i915_private *dev_priv = dev->dev_private;
9368         int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9369         int req_cdclk;
9370
9371         /* see the comment in valleyview_modeset_global_resources */
9372         if (WARN_ON(max_pixclk < 0))
9373                 return;
9374
9375         req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9376
9377         if (req_cdclk != dev_priv->cdclk_freq)
9378                 broxton_set_cdclk(dev, req_cdclk);
9379 }
9380
9381 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9382                                       struct intel_crtc_state *crtc_state)
9383 {
9384         if (!intel_ddi_pll_select(crtc, crtc_state))
9385                 return -EINVAL;
9386
9387         crtc->lowfreq_avail = false;
9388
9389         return 0;
9390 }
9391
9392 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9393                                 enum port port,
9394                                 struct intel_crtc_state *pipe_config)
9395 {
9396         switch (port) {
9397         case PORT_A:
9398                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9399                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9400                 break;
9401         case PORT_B:
9402                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9403                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9404                 break;
9405         case PORT_C:
9406                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9407                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9408                 break;
9409         default:
9410                 DRM_ERROR("Incorrect port type\n");
9411         }
9412 }
9413
9414 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9415                                 enum port port,
9416                                 struct intel_crtc_state *pipe_config)
9417 {
9418         u32 temp, dpll_ctl1;
9419
9420         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9421         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9422
9423         switch (pipe_config->ddi_pll_sel) {
9424         case SKL_DPLL0:
9425                 /*
9426                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9427                  * of the shared DPLL framework and thus needs to be read out
9428                  * separately
9429                  */
9430                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9431                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9432                 break;
9433         case SKL_DPLL1:
9434                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9435                 break;
9436         case SKL_DPLL2:
9437                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9438                 break;
9439         case SKL_DPLL3:
9440                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9441                 break;
9442         }
9443 }
9444
9445 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9446                                 enum port port,
9447                                 struct intel_crtc_state *pipe_config)
9448 {
9449         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9450
9451         switch (pipe_config->ddi_pll_sel) {
9452         case PORT_CLK_SEL_WRPLL1:
9453                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9454                 break;
9455         case PORT_CLK_SEL_WRPLL2:
9456                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9457                 break;
9458         }
9459 }
9460
9461 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9462                                        struct intel_crtc_state *pipe_config)
9463 {
9464         struct drm_device *dev = crtc->base.dev;
9465         struct drm_i915_private *dev_priv = dev->dev_private;
9466         struct intel_shared_dpll *pll;
9467         enum port port;
9468         uint32_t tmp;
9469
9470         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9471
9472         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9473
9474         if (IS_SKYLAKE(dev))
9475                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9476         else if (IS_BROXTON(dev))
9477                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9478         else
9479                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9480
9481         if (pipe_config->shared_dpll >= 0) {
9482                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9483
9484                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9485                                            &pipe_config->dpll_hw_state));
9486         }
9487
9488         /*
9489          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9490          * DDI E. So just check whether this pipe is wired to DDI E and whether
9491          * the PCH transcoder is on.
9492          */
9493         if (INTEL_INFO(dev)->gen < 9 &&
9494             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9495                 pipe_config->has_pch_encoder = true;
9496
9497                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9498                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9499                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9500
9501                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9502         }
9503 }
9504
9505 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9506                                     struct intel_crtc_state *pipe_config)
9507 {
9508         struct drm_device *dev = crtc->base.dev;
9509         struct drm_i915_private *dev_priv = dev->dev_private;
9510         enum intel_display_power_domain pfit_domain;
9511         uint32_t tmp;
9512
9513         if (!intel_display_power_is_enabled(dev_priv,
9514                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9515                 return false;
9516
9517         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9518         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9519
9520         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9521         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9522                 enum pipe trans_edp_pipe;
9523                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9524                 default:
9525                         WARN(1, "unknown pipe linked to edp transcoder\n");
9526                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9527                 case TRANS_DDI_EDP_INPUT_A_ON:
9528                         trans_edp_pipe = PIPE_A;
9529                         break;
9530                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9531                         trans_edp_pipe = PIPE_B;
9532                         break;
9533                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9534                         trans_edp_pipe = PIPE_C;
9535                         break;
9536                 }
9537
9538                 if (trans_edp_pipe == crtc->pipe)
9539                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9540         }
9541
9542         if (!intel_display_power_is_enabled(dev_priv,
9543                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9544                 return false;
9545
9546         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9547         if (!(tmp & PIPECONF_ENABLE))
9548                 return false;
9549
9550         haswell_get_ddi_port_state(crtc, pipe_config);
9551
9552         intel_get_pipe_timings(crtc, pipe_config);
9553
9554         if (INTEL_INFO(dev)->gen >= 9) {
9555                 skl_init_scalers(dev, crtc, pipe_config);
9556         }
9557
9558         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9559
9560         if (INTEL_INFO(dev)->gen >= 9) {
9561                 pipe_config->scaler_state.scaler_id = -1;
9562                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9563         }
9564
9565         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9566                 if (INTEL_INFO(dev)->gen == 9)
9567                         skylake_get_pfit_config(crtc, pipe_config);
9568                 else if (INTEL_INFO(dev)->gen < 9)
9569                         ironlake_get_pfit_config(crtc, pipe_config);
9570                 else
9571                         MISSING_CASE(INTEL_INFO(dev)->gen);
9572         }
9573
9574         if (IS_HASWELL(dev))
9575                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9576                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9577
9578         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9579                 pipe_config->pixel_multiplier =
9580                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9581         } else {
9582                 pipe_config->pixel_multiplier = 1;
9583         }
9584
9585         return true;
9586 }
9587
9588 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9589 {
9590         struct drm_device *dev = crtc->dev;
9591         struct drm_i915_private *dev_priv = dev->dev_private;
9592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9593         uint32_t cntl = 0, size = 0;
9594
9595         if (base) {
9596                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9597                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9598                 unsigned int stride = roundup_pow_of_two(width) * 4;
9599
9600                 switch (stride) {
9601                 default:
9602                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9603                                   width, stride);
9604                         stride = 256;
9605                         /* fallthrough */
9606                 case 256:
9607                 case 512:
9608                 case 1024:
9609                 case 2048:
9610                         break;
9611                 }
9612
9613                 cntl |= CURSOR_ENABLE |
9614                         CURSOR_GAMMA_ENABLE |
9615                         CURSOR_FORMAT_ARGB |
9616                         CURSOR_STRIDE(stride);
9617
9618                 size = (height << 12) | width;
9619         }
9620
9621         if (intel_crtc->cursor_cntl != 0 &&
9622             (intel_crtc->cursor_base != base ||
9623              intel_crtc->cursor_size != size ||
9624              intel_crtc->cursor_cntl != cntl)) {
9625                 /* On these chipsets we can only modify the base/size/stride
9626                  * whilst the cursor is disabled.
9627                  */
9628                 I915_WRITE(_CURACNTR, 0);
9629                 POSTING_READ(_CURACNTR);
9630                 intel_crtc->cursor_cntl = 0;
9631         }
9632
9633         if (intel_crtc->cursor_base != base) {
9634                 I915_WRITE(_CURABASE, base);
9635                 intel_crtc->cursor_base = base;
9636         }
9637
9638         if (intel_crtc->cursor_size != size) {
9639                 I915_WRITE(CURSIZE, size);
9640                 intel_crtc->cursor_size = size;
9641         }
9642
9643         if (intel_crtc->cursor_cntl != cntl) {
9644                 I915_WRITE(_CURACNTR, cntl);
9645                 POSTING_READ(_CURACNTR);
9646                 intel_crtc->cursor_cntl = cntl;
9647         }
9648 }
9649
9650 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9651 {
9652         struct drm_device *dev = crtc->dev;
9653         struct drm_i915_private *dev_priv = dev->dev_private;
9654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9655         int pipe = intel_crtc->pipe;
9656         uint32_t cntl;
9657
9658         cntl = 0;
9659         if (base) {
9660                 cntl = MCURSOR_GAMMA_ENABLE;
9661                 switch (intel_crtc->base.cursor->state->crtc_w) {
9662                         case 64:
9663                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9664                                 break;
9665                         case 128:
9666                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9667                                 break;
9668                         case 256:
9669                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9670                                 break;
9671                         default:
9672                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9673                                 return;
9674                 }
9675                 cntl |= pipe << 28; /* Connect to correct pipe */
9676
9677                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9678                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9679         }
9680
9681         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9682                 cntl |= CURSOR_ROTATE_180;
9683
9684         if (intel_crtc->cursor_cntl != cntl) {
9685                 I915_WRITE(CURCNTR(pipe), cntl);
9686                 POSTING_READ(CURCNTR(pipe));
9687                 intel_crtc->cursor_cntl = cntl;
9688         }
9689
9690         /* and commit changes on next vblank */
9691         I915_WRITE(CURBASE(pipe), base);
9692         POSTING_READ(CURBASE(pipe));
9693
9694         intel_crtc->cursor_base = base;
9695 }
9696
9697 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9698 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9699                                      bool on)
9700 {
9701         struct drm_device *dev = crtc->dev;
9702         struct drm_i915_private *dev_priv = dev->dev_private;
9703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9704         int pipe = intel_crtc->pipe;
9705         int x = crtc->cursor_x;
9706         int y = crtc->cursor_y;
9707         u32 base = 0, pos = 0;
9708
9709         if (on)
9710                 base = intel_crtc->cursor_addr;
9711
9712         if (x >= intel_crtc->config->pipe_src_w)
9713                 base = 0;
9714
9715         if (y >= intel_crtc->config->pipe_src_h)
9716                 base = 0;
9717
9718         if (x < 0) {
9719                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9720                         base = 0;
9721
9722                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9723                 x = -x;
9724         }
9725         pos |= x << CURSOR_X_SHIFT;
9726
9727         if (y < 0) {
9728                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9729                         base = 0;
9730
9731                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9732                 y = -y;
9733         }
9734         pos |= y << CURSOR_Y_SHIFT;
9735
9736         if (base == 0 && intel_crtc->cursor_base == 0)
9737                 return;
9738
9739         I915_WRITE(CURPOS(pipe), pos);
9740
9741         /* ILK+ do this automagically */
9742         if (HAS_GMCH_DISPLAY(dev) &&
9743             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9744                 base += (intel_crtc->base.cursor->state->crtc_h *
9745                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9746         }
9747
9748         if (IS_845G(dev) || IS_I865G(dev))
9749                 i845_update_cursor(crtc, base);
9750         else
9751                 i9xx_update_cursor(crtc, base);
9752 }
9753
9754 static bool cursor_size_ok(struct drm_device *dev,
9755                            uint32_t width, uint32_t height)
9756 {
9757         if (width == 0 || height == 0)
9758                 return false;
9759
9760         /*
9761          * 845g/865g are special in that they are only limited by
9762          * the width of their cursors, the height is arbitrary up to
9763          * the precision of the register. Everything else requires
9764          * square cursors, limited to a few power-of-two sizes.
9765          */
9766         if (IS_845G(dev) || IS_I865G(dev)) {
9767                 if ((width & 63) != 0)
9768                         return false;
9769
9770                 if (width > (IS_845G(dev) ? 64 : 512))
9771                         return false;
9772
9773                 if (height > 1023)
9774                         return false;
9775         } else {
9776                 switch (width | height) {
9777                 case 256:
9778                 case 128:
9779                         if (IS_GEN2(dev))
9780                                 return false;
9781                 case 64:
9782                         break;
9783                 default:
9784                         return false;
9785                 }
9786         }
9787
9788         return true;
9789 }
9790
9791 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9792                                  u16 *blue, uint32_t start, uint32_t size)
9793 {
9794         int end = (start + size > 256) ? 256 : start + size, i;
9795         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9796
9797         for (i = start; i < end; i++) {
9798                 intel_crtc->lut_r[i] = red[i] >> 8;
9799                 intel_crtc->lut_g[i] = green[i] >> 8;
9800                 intel_crtc->lut_b[i] = blue[i] >> 8;
9801         }
9802
9803         intel_crtc_load_lut(crtc);
9804 }
9805
9806 /* VESA 640x480x72Hz mode to set on the pipe */
9807 static struct drm_display_mode load_detect_mode = {
9808         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9809                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9810 };
9811
9812 struct drm_framebuffer *
9813 __intel_framebuffer_create(struct drm_device *dev,
9814                            struct drm_mode_fb_cmd2 *mode_cmd,
9815                            struct drm_i915_gem_object *obj)
9816 {
9817         struct intel_framebuffer *intel_fb;
9818         int ret;
9819
9820         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9821         if (!intel_fb) {
9822                 drm_gem_object_unreference(&obj->base);
9823                 return ERR_PTR(-ENOMEM);
9824         }
9825
9826         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9827         if (ret)
9828                 goto err;
9829
9830         return &intel_fb->base;
9831 err:
9832         drm_gem_object_unreference(&obj->base);
9833         kfree(intel_fb);
9834
9835         return ERR_PTR(ret);
9836 }
9837
9838 static struct drm_framebuffer *
9839 intel_framebuffer_create(struct drm_device *dev,
9840                          struct drm_mode_fb_cmd2 *mode_cmd,
9841                          struct drm_i915_gem_object *obj)
9842 {
9843         struct drm_framebuffer *fb;
9844         int ret;
9845
9846         ret = i915_mutex_lock_interruptible(dev);
9847         if (ret)
9848                 return ERR_PTR(ret);
9849         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9850         mutex_unlock(&dev->struct_mutex);
9851
9852         return fb;
9853 }
9854
9855 static u32
9856 intel_framebuffer_pitch_for_width(int width, int bpp)
9857 {
9858         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9859         return ALIGN(pitch, 64);
9860 }
9861
9862 static u32
9863 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9864 {
9865         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9866         return PAGE_ALIGN(pitch * mode->vdisplay);
9867 }
9868
9869 static struct drm_framebuffer *
9870 intel_framebuffer_create_for_mode(struct drm_device *dev,
9871                                   struct drm_display_mode *mode,
9872                                   int depth, int bpp)
9873 {
9874         struct drm_i915_gem_object *obj;
9875         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9876
9877         obj = i915_gem_alloc_object(dev,
9878                                     intel_framebuffer_size_for_mode(mode, bpp));
9879         if (obj == NULL)
9880                 return ERR_PTR(-ENOMEM);
9881
9882         mode_cmd.width = mode->hdisplay;
9883         mode_cmd.height = mode->vdisplay;
9884         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9885                                                                 bpp);
9886         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9887
9888         return intel_framebuffer_create(dev, &mode_cmd, obj);
9889 }
9890
9891 static struct drm_framebuffer *
9892 mode_fits_in_fbdev(struct drm_device *dev,
9893                    struct drm_display_mode *mode)
9894 {
9895 #ifdef CONFIG_DRM_I915_FBDEV
9896         struct drm_i915_private *dev_priv = dev->dev_private;
9897         struct drm_i915_gem_object *obj;
9898         struct drm_framebuffer *fb;
9899
9900         if (!dev_priv->fbdev)
9901                 return NULL;
9902
9903         if (!dev_priv->fbdev->fb)
9904                 return NULL;
9905
9906         obj = dev_priv->fbdev->fb->obj;
9907         BUG_ON(!obj);
9908
9909         fb = &dev_priv->fbdev->fb->base;
9910         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9911                                                                fb->bits_per_pixel))
9912                 return NULL;
9913
9914         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9915                 return NULL;
9916
9917         return fb;
9918 #else
9919         return NULL;
9920 #endif
9921 }
9922
9923 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9924                                            struct drm_crtc *crtc,
9925                                            struct drm_display_mode *mode,
9926                                            struct drm_framebuffer *fb,
9927                                            int x, int y)
9928 {
9929         struct drm_plane_state *plane_state;
9930         int hdisplay, vdisplay;
9931         int ret;
9932
9933         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9934         if (IS_ERR(plane_state))
9935                 return PTR_ERR(plane_state);
9936
9937         if (mode)
9938                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9939         else
9940                 hdisplay = vdisplay = 0;
9941
9942         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9943         if (ret)
9944                 return ret;
9945         drm_atomic_set_fb_for_plane(plane_state, fb);
9946         plane_state->crtc_x = 0;
9947         plane_state->crtc_y = 0;
9948         plane_state->crtc_w = hdisplay;
9949         plane_state->crtc_h = vdisplay;
9950         plane_state->src_x = x << 16;
9951         plane_state->src_y = y << 16;
9952         plane_state->src_w = hdisplay << 16;
9953         plane_state->src_h = vdisplay << 16;
9954
9955         return 0;
9956 }
9957
9958 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9959                                 struct drm_display_mode *mode,
9960                                 struct intel_load_detect_pipe *old,
9961                                 struct drm_modeset_acquire_ctx *ctx)
9962 {
9963         struct intel_crtc *intel_crtc;
9964         struct intel_encoder *intel_encoder =
9965                 intel_attached_encoder(connector);
9966         struct drm_crtc *possible_crtc;
9967         struct drm_encoder *encoder = &intel_encoder->base;
9968         struct drm_crtc *crtc = NULL;
9969         struct drm_device *dev = encoder->dev;
9970         struct drm_framebuffer *fb;
9971         struct drm_mode_config *config = &dev->mode_config;
9972         struct drm_atomic_state *state = NULL;
9973         struct drm_connector_state *connector_state;
9974         struct intel_crtc_state *crtc_state;
9975         int ret, i = -1;
9976
9977         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9978                       connector->base.id, connector->name,
9979                       encoder->base.id, encoder->name);
9980
9981 retry:
9982         ret = drm_modeset_lock(&config->connection_mutex, ctx);
9983         if (ret)
9984                 goto fail_unlock;
9985
9986         /*
9987          * Algorithm gets a little messy:
9988          *
9989          *   - if the connector already has an assigned crtc, use it (but make
9990          *     sure it's on first)
9991          *
9992          *   - try to find the first unused crtc that can drive this connector,
9993          *     and use that if we find one
9994          */
9995
9996         /* See if we already have a CRTC for this connector */
9997         if (encoder->crtc) {
9998                 crtc = encoder->crtc;
9999
10000                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10001                 if (ret)
10002                         goto fail_unlock;
10003                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10004                 if (ret)
10005                         goto fail_unlock;
10006
10007                 old->dpms_mode = connector->dpms;
10008                 old->load_detect_temp = false;
10009
10010                 /* Make sure the crtc and connector are running */
10011                 if (connector->dpms != DRM_MODE_DPMS_ON)
10012                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10013
10014                 return true;
10015         }
10016
10017         /* Find an unused one (if possible) */
10018         for_each_crtc(dev, possible_crtc) {
10019                 i++;
10020                 if (!(encoder->possible_crtcs & (1 << i)))
10021                         continue;
10022                 if (possible_crtc->state->enable)
10023                         continue;
10024                 /* This can occur when applying the pipe A quirk on resume. */
10025                 if (to_intel_crtc(possible_crtc)->new_enabled)
10026                         continue;
10027
10028                 crtc = possible_crtc;
10029                 break;
10030         }
10031
10032         /*
10033          * If we didn't find an unused CRTC, don't use any.
10034          */
10035         if (!crtc) {
10036                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10037                 goto fail_unlock;
10038         }
10039
10040         ret = drm_modeset_lock(&crtc->mutex, ctx);
10041         if (ret)
10042                 goto fail_unlock;
10043         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10044         if (ret)
10045                 goto fail_unlock;
10046         intel_encoder->new_crtc = to_intel_crtc(crtc);
10047         to_intel_connector(connector)->new_encoder = intel_encoder;
10048
10049         intel_crtc = to_intel_crtc(crtc);
10050         intel_crtc->new_enabled = true;
10051         old->dpms_mode = connector->dpms;
10052         old->load_detect_temp = true;
10053         old->release_fb = NULL;
10054
10055         state = drm_atomic_state_alloc(dev);
10056         if (!state)
10057                 return false;
10058
10059         state->acquire_ctx = ctx;
10060
10061         connector_state = drm_atomic_get_connector_state(state, connector);
10062         if (IS_ERR(connector_state)) {
10063                 ret = PTR_ERR(connector_state);
10064                 goto fail;
10065         }
10066
10067         connector_state->crtc = crtc;
10068         connector_state->best_encoder = &intel_encoder->base;
10069
10070         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10071         if (IS_ERR(crtc_state)) {
10072                 ret = PTR_ERR(crtc_state);
10073                 goto fail;
10074         }
10075
10076         crtc_state->base.active = crtc_state->base.enable = true;
10077
10078         if (!mode)
10079                 mode = &load_detect_mode;
10080
10081         /* We need a framebuffer large enough to accommodate all accesses
10082          * that the plane may generate whilst we perform load detection.
10083          * We can not rely on the fbcon either being present (we get called
10084          * during its initialisation to detect all boot displays, or it may
10085          * not even exist) or that it is large enough to satisfy the
10086          * requested mode.
10087          */
10088         fb = mode_fits_in_fbdev(dev, mode);
10089         if (fb == NULL) {
10090                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10091                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10092                 old->release_fb = fb;
10093         } else
10094                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10095         if (IS_ERR(fb)) {
10096                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10097                 goto fail;
10098         }
10099
10100         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10101         if (ret)
10102                 goto fail;
10103
10104         drm_mode_copy(&crtc_state->base.mode, mode);
10105
10106         if (intel_set_mode(crtc, state, true)) {
10107                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10108                 if (old->release_fb)
10109                         old->release_fb->funcs->destroy(old->release_fb);
10110                 goto fail;
10111         }
10112         crtc->primary->crtc = crtc;
10113
10114         /* let the connector get through one full cycle before testing */
10115         intel_wait_for_vblank(dev, intel_crtc->pipe);
10116         return true;
10117
10118  fail:
10119         intel_crtc->new_enabled = crtc->state->enable;
10120 fail_unlock:
10121         drm_atomic_state_free(state);
10122         state = NULL;
10123
10124         if (ret == -EDEADLK) {
10125                 drm_modeset_backoff(ctx);
10126                 goto retry;
10127         }
10128
10129         return false;
10130 }
10131
10132 void intel_release_load_detect_pipe(struct drm_connector *connector,
10133                                     struct intel_load_detect_pipe *old,
10134                                     struct drm_modeset_acquire_ctx *ctx)
10135 {
10136         struct drm_device *dev = connector->dev;
10137         struct intel_encoder *intel_encoder =
10138                 intel_attached_encoder(connector);
10139         struct drm_encoder *encoder = &intel_encoder->base;
10140         struct drm_crtc *crtc = encoder->crtc;
10141         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10142         struct drm_atomic_state *state;
10143         struct drm_connector_state *connector_state;
10144         struct intel_crtc_state *crtc_state;
10145         int ret;
10146
10147         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10148                       connector->base.id, connector->name,
10149                       encoder->base.id, encoder->name);
10150
10151         if (old->load_detect_temp) {
10152                 state = drm_atomic_state_alloc(dev);
10153                 if (!state)
10154                         goto fail;
10155
10156                 state->acquire_ctx = ctx;
10157
10158                 connector_state = drm_atomic_get_connector_state(state, connector);
10159                 if (IS_ERR(connector_state))
10160                         goto fail;
10161
10162                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10163                 if (IS_ERR(crtc_state))
10164                         goto fail;
10165
10166                 to_intel_connector(connector)->new_encoder = NULL;
10167                 intel_encoder->new_crtc = NULL;
10168                 intel_crtc->new_enabled = false;
10169
10170                 connector_state->best_encoder = NULL;
10171                 connector_state->crtc = NULL;
10172
10173                 crtc_state->base.enable = crtc_state->base.active = false;
10174
10175                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10176                                                       0, 0);
10177                 if (ret)
10178                         goto fail;
10179
10180                 ret = intel_set_mode(crtc, state, true);
10181                 if (ret)
10182                         goto fail;
10183
10184                 if (old->release_fb) {
10185                         drm_framebuffer_unregister_private(old->release_fb);
10186                         drm_framebuffer_unreference(old->release_fb);
10187                 }
10188
10189                 return;
10190         }
10191
10192         /* Switch crtc and encoder back off if necessary */
10193         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10194                 connector->funcs->dpms(connector, old->dpms_mode);
10195
10196         return;
10197 fail:
10198         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10199         drm_atomic_state_free(state);
10200 }
10201
10202 static int i9xx_pll_refclk(struct drm_device *dev,
10203                            const struct intel_crtc_state *pipe_config)
10204 {
10205         struct drm_i915_private *dev_priv = dev->dev_private;
10206         u32 dpll = pipe_config->dpll_hw_state.dpll;
10207
10208         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10209                 return dev_priv->vbt.lvds_ssc_freq;
10210         else if (HAS_PCH_SPLIT(dev))
10211                 return 120000;
10212         else if (!IS_GEN2(dev))
10213                 return 96000;
10214         else
10215                 return 48000;
10216 }
10217
10218 /* Returns the clock of the currently programmed mode of the given pipe. */
10219 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10220                                 struct intel_crtc_state *pipe_config)
10221 {
10222         struct drm_device *dev = crtc->base.dev;
10223         struct drm_i915_private *dev_priv = dev->dev_private;
10224         int pipe = pipe_config->cpu_transcoder;
10225         u32 dpll = pipe_config->dpll_hw_state.dpll;
10226         u32 fp;
10227         intel_clock_t clock;
10228         int refclk = i9xx_pll_refclk(dev, pipe_config);
10229
10230         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10231                 fp = pipe_config->dpll_hw_state.fp0;
10232         else
10233                 fp = pipe_config->dpll_hw_state.fp1;
10234
10235         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10236         if (IS_PINEVIEW(dev)) {
10237                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10238                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10239         } else {
10240                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10241                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10242         }
10243
10244         if (!IS_GEN2(dev)) {
10245                 if (IS_PINEVIEW(dev))
10246                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10247                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10248                 else
10249                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10250                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10251
10252                 switch (dpll & DPLL_MODE_MASK) {
10253                 case DPLLB_MODE_DAC_SERIAL:
10254                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10255                                 5 : 10;
10256                         break;
10257                 case DPLLB_MODE_LVDS:
10258                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10259                                 7 : 14;
10260                         break;
10261                 default:
10262                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10263                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10264                         return;
10265                 }
10266
10267                 if (IS_PINEVIEW(dev))
10268                         pineview_clock(refclk, &clock);
10269                 else
10270                         i9xx_clock(refclk, &clock);
10271         } else {
10272                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10273                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10274
10275                 if (is_lvds) {
10276                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10277                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10278
10279                         if (lvds & LVDS_CLKB_POWER_UP)
10280                                 clock.p2 = 7;
10281                         else
10282                                 clock.p2 = 14;
10283                 } else {
10284                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10285                                 clock.p1 = 2;
10286                         else {
10287                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10288                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10289                         }
10290                         if (dpll & PLL_P2_DIVIDE_BY_4)
10291                                 clock.p2 = 4;
10292                         else
10293                                 clock.p2 = 2;
10294                 }
10295
10296                 i9xx_clock(refclk, &clock);
10297         }
10298
10299         /*
10300          * This value includes pixel_multiplier. We will use
10301          * port_clock to compute adjusted_mode.crtc_clock in the
10302          * encoder's get_config() function.
10303          */
10304         pipe_config->port_clock = clock.dot;
10305 }
10306
10307 int intel_dotclock_calculate(int link_freq,
10308                              const struct intel_link_m_n *m_n)
10309 {
10310         /*
10311          * The calculation for the data clock is:
10312          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10313          * But we want to avoid losing precison if possible, so:
10314          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10315          *
10316          * and the link clock is simpler:
10317          * link_clock = (m * link_clock) / n
10318          */
10319
10320         if (!m_n->link_n)
10321                 return 0;
10322
10323         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10324 }
10325
10326 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10327                                    struct intel_crtc_state *pipe_config)
10328 {
10329         struct drm_device *dev = crtc->base.dev;
10330
10331         /* read out port_clock from the DPLL */
10332         i9xx_crtc_clock_get(crtc, pipe_config);
10333
10334         /*
10335          * This value does not include pixel_multiplier.
10336          * We will check that port_clock and adjusted_mode.crtc_clock
10337          * agree once we know their relationship in the encoder's
10338          * get_config() function.
10339          */
10340         pipe_config->base.adjusted_mode.crtc_clock =
10341                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10342                                          &pipe_config->fdi_m_n);
10343 }
10344
10345 /** Returns the currently programmed mode of the given pipe. */
10346 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10347                                              struct drm_crtc *crtc)
10348 {
10349         struct drm_i915_private *dev_priv = dev->dev_private;
10350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10351         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10352         struct drm_display_mode *mode;
10353         struct intel_crtc_state pipe_config;
10354         int htot = I915_READ(HTOTAL(cpu_transcoder));
10355         int hsync = I915_READ(HSYNC(cpu_transcoder));
10356         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10357         int vsync = I915_READ(VSYNC(cpu_transcoder));
10358         enum pipe pipe = intel_crtc->pipe;
10359
10360         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10361         if (!mode)
10362                 return NULL;
10363
10364         /*
10365          * Construct a pipe_config sufficient for getting the clock info
10366          * back out of crtc_clock_get.
10367          *
10368          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10369          * to use a real value here instead.
10370          */
10371         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10372         pipe_config.pixel_multiplier = 1;
10373         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10374         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10375         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10376         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10377
10378         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10379         mode->hdisplay = (htot & 0xffff) + 1;
10380         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10381         mode->hsync_start = (hsync & 0xffff) + 1;
10382         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10383         mode->vdisplay = (vtot & 0xffff) + 1;
10384         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10385         mode->vsync_start = (vsync & 0xffff) + 1;
10386         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10387
10388         drm_mode_set_name(mode);
10389
10390         return mode;
10391 }
10392
10393 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10394 {
10395         struct drm_device *dev = crtc->dev;
10396         struct drm_i915_private *dev_priv = dev->dev_private;
10397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10398
10399         if (!HAS_GMCH_DISPLAY(dev))
10400                 return;
10401
10402         if (!dev_priv->lvds_downclock_avail)
10403                 return;
10404
10405         /*
10406          * Since this is called by a timer, we should never get here in
10407          * the manual case.
10408          */
10409         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10410                 int pipe = intel_crtc->pipe;
10411                 int dpll_reg = DPLL(pipe);
10412                 int dpll;
10413
10414                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10415
10416                 assert_panel_unlocked(dev_priv, pipe);
10417
10418                 dpll = I915_READ(dpll_reg);
10419                 dpll |= DISPLAY_RATE_SELECT_FPA1;
10420                 I915_WRITE(dpll_reg, dpll);
10421                 intel_wait_for_vblank(dev, pipe);
10422                 dpll = I915_READ(dpll_reg);
10423                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10424                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10425         }
10426
10427 }
10428
10429 void intel_mark_busy(struct drm_device *dev)
10430 {
10431         struct drm_i915_private *dev_priv = dev->dev_private;
10432
10433         if (dev_priv->mm.busy)
10434                 return;
10435
10436         intel_runtime_pm_get(dev_priv);
10437         i915_update_gfx_val(dev_priv);
10438         if (INTEL_INFO(dev)->gen >= 6)
10439                 gen6_rps_busy(dev_priv);
10440         dev_priv->mm.busy = true;
10441 }
10442
10443 void intel_mark_idle(struct drm_device *dev)
10444 {
10445         struct drm_i915_private *dev_priv = dev->dev_private;
10446         struct drm_crtc *crtc;
10447
10448         if (!dev_priv->mm.busy)
10449                 return;
10450
10451         dev_priv->mm.busy = false;
10452
10453         for_each_crtc(dev, crtc) {
10454                 if (!crtc->primary->fb)
10455                         continue;
10456
10457                 intel_decrease_pllclock(crtc);
10458         }
10459
10460         if (INTEL_INFO(dev)->gen >= 6)
10461                 gen6_rps_idle(dev->dev_private);
10462
10463         intel_runtime_pm_put(dev_priv);
10464 }
10465
10466 static void intel_crtc_destroy(struct drm_crtc *crtc)
10467 {
10468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10469         struct drm_device *dev = crtc->dev;
10470         struct intel_unpin_work *work;
10471
10472         spin_lock_irq(&dev->event_lock);
10473         work = intel_crtc->unpin_work;
10474         intel_crtc->unpin_work = NULL;
10475         spin_unlock_irq(&dev->event_lock);
10476
10477         if (work) {
10478                 cancel_work_sync(&work->work);
10479                 kfree(work);
10480         }
10481
10482         drm_crtc_cleanup(crtc);
10483
10484         kfree(intel_crtc);
10485 }
10486
10487 static void intel_unpin_work_fn(struct work_struct *__work)
10488 {
10489         struct intel_unpin_work *work =
10490                 container_of(__work, struct intel_unpin_work, work);
10491         struct drm_device *dev = work->crtc->dev;
10492         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10493
10494         mutex_lock(&dev->struct_mutex);
10495         intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10496         drm_gem_object_unreference(&work->pending_flip_obj->base);
10497
10498         intel_fbc_update(dev);
10499
10500         if (work->flip_queued_req)
10501                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10502         mutex_unlock(&dev->struct_mutex);
10503
10504         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10505         drm_framebuffer_unreference(work->old_fb);
10506
10507         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10508         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10509
10510         kfree(work);
10511 }
10512
10513 static void do_intel_finish_page_flip(struct drm_device *dev,
10514                                       struct drm_crtc *crtc)
10515 {
10516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10517         struct intel_unpin_work *work;
10518         unsigned long flags;
10519
10520         /* Ignore early vblank irqs */
10521         if (intel_crtc == NULL)
10522                 return;
10523
10524         /*
10525          * This is called both by irq handlers and the reset code (to complete
10526          * lost pageflips) so needs the full irqsave spinlocks.
10527          */
10528         spin_lock_irqsave(&dev->event_lock, flags);
10529         work = intel_crtc->unpin_work;
10530
10531         /* Ensure we don't miss a work->pending update ... */
10532         smp_rmb();
10533
10534         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10535                 spin_unlock_irqrestore(&dev->event_lock, flags);
10536                 return;
10537         }
10538
10539         page_flip_completed(intel_crtc);
10540
10541         spin_unlock_irqrestore(&dev->event_lock, flags);
10542 }
10543
10544 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10545 {
10546         struct drm_i915_private *dev_priv = dev->dev_private;
10547         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10548
10549         do_intel_finish_page_flip(dev, crtc);
10550 }
10551
10552 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10553 {
10554         struct drm_i915_private *dev_priv = dev->dev_private;
10555         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10556
10557         do_intel_finish_page_flip(dev, crtc);
10558 }
10559
10560 /* Is 'a' after or equal to 'b'? */
10561 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10562 {
10563         return !((a - b) & 0x80000000);
10564 }
10565
10566 static bool page_flip_finished(struct intel_crtc *crtc)
10567 {
10568         struct drm_device *dev = crtc->base.dev;
10569         struct drm_i915_private *dev_priv = dev->dev_private;
10570
10571         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10572             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10573                 return true;
10574
10575         /*
10576          * The relevant registers doen't exist on pre-ctg.
10577          * As the flip done interrupt doesn't trigger for mmio
10578          * flips on gmch platforms, a flip count check isn't
10579          * really needed there. But since ctg has the registers,
10580          * include it in the check anyway.
10581          */
10582         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10583                 return true;
10584
10585         /*
10586          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10587          * used the same base address. In that case the mmio flip might
10588          * have completed, but the CS hasn't even executed the flip yet.
10589          *
10590          * A flip count check isn't enough as the CS might have updated
10591          * the base address just after start of vblank, but before we
10592          * managed to process the interrupt. This means we'd complete the
10593          * CS flip too soon.
10594          *
10595          * Combining both checks should get us a good enough result. It may
10596          * still happen that the CS flip has been executed, but has not
10597          * yet actually completed. But in case the base address is the same
10598          * anyway, we don't really care.
10599          */
10600         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10601                 crtc->unpin_work->gtt_offset &&
10602                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10603                                     crtc->unpin_work->flip_count);
10604 }
10605
10606 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10607 {
10608         struct drm_i915_private *dev_priv = dev->dev_private;
10609         struct intel_crtc *intel_crtc =
10610                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10611         unsigned long flags;
10612
10613
10614         /*
10615          * This is called both by irq handlers and the reset code (to complete
10616          * lost pageflips) so needs the full irqsave spinlocks.
10617          *
10618          * NB: An MMIO update of the plane base pointer will also
10619          * generate a page-flip completion irq, i.e. every modeset
10620          * is also accompanied by a spurious intel_prepare_page_flip().
10621          */
10622         spin_lock_irqsave(&dev->event_lock, flags);
10623         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10624                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10625         spin_unlock_irqrestore(&dev->event_lock, flags);
10626 }
10627
10628 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10629 {
10630         /* Ensure that the work item is consistent when activating it ... */
10631         smp_wmb();
10632         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10633         /* and that it is marked active as soon as the irq could fire. */
10634         smp_wmb();
10635 }
10636
10637 static int intel_gen2_queue_flip(struct drm_device *dev,
10638                                  struct drm_crtc *crtc,
10639                                  struct drm_framebuffer *fb,
10640                                  struct drm_i915_gem_object *obj,
10641                                  struct intel_engine_cs *ring,
10642                                  uint32_t flags)
10643 {
10644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10645         u32 flip_mask;
10646         int ret;
10647
10648         ret = intel_ring_begin(ring, 6);
10649         if (ret)
10650                 return ret;
10651
10652         /* Can't queue multiple flips, so wait for the previous
10653          * one to finish before executing the next.
10654          */
10655         if (intel_crtc->plane)
10656                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10657         else
10658                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10659         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10660         intel_ring_emit(ring, MI_NOOP);
10661         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10662                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10663         intel_ring_emit(ring, fb->pitches[0]);
10664         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10665         intel_ring_emit(ring, 0); /* aux display base address, unused */
10666
10667         intel_mark_page_flip_active(intel_crtc);
10668         __intel_ring_advance(ring);
10669         return 0;
10670 }
10671
10672 static int intel_gen3_queue_flip(struct drm_device *dev,
10673                                  struct drm_crtc *crtc,
10674                                  struct drm_framebuffer *fb,
10675                                  struct drm_i915_gem_object *obj,
10676                                  struct intel_engine_cs *ring,
10677                                  uint32_t flags)
10678 {
10679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10680         u32 flip_mask;
10681         int ret;
10682
10683         ret = intel_ring_begin(ring, 6);
10684         if (ret)
10685                 return ret;
10686
10687         if (intel_crtc->plane)
10688                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10689         else
10690                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10691         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10692         intel_ring_emit(ring, MI_NOOP);
10693         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10694                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10695         intel_ring_emit(ring, fb->pitches[0]);
10696         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10697         intel_ring_emit(ring, MI_NOOP);
10698
10699         intel_mark_page_flip_active(intel_crtc);
10700         __intel_ring_advance(ring);
10701         return 0;
10702 }
10703
10704 static int intel_gen4_queue_flip(struct drm_device *dev,
10705                                  struct drm_crtc *crtc,
10706                                  struct drm_framebuffer *fb,
10707                                  struct drm_i915_gem_object *obj,
10708                                  struct intel_engine_cs *ring,
10709                                  uint32_t flags)
10710 {
10711         struct drm_i915_private *dev_priv = dev->dev_private;
10712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10713         uint32_t pf, pipesrc;
10714         int ret;
10715
10716         ret = intel_ring_begin(ring, 4);
10717         if (ret)
10718                 return ret;
10719
10720         /* i965+ uses the linear or tiled offsets from the
10721          * Display Registers (which do not change across a page-flip)
10722          * so we need only reprogram the base address.
10723          */
10724         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10725                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10726         intel_ring_emit(ring, fb->pitches[0]);
10727         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10728                         obj->tiling_mode);
10729
10730         /* XXX Enabling the panel-fitter across page-flip is so far
10731          * untested on non-native modes, so ignore it for now.
10732          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10733          */
10734         pf = 0;
10735         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10736         intel_ring_emit(ring, pf | pipesrc);
10737
10738         intel_mark_page_flip_active(intel_crtc);
10739         __intel_ring_advance(ring);
10740         return 0;
10741 }
10742
10743 static int intel_gen6_queue_flip(struct drm_device *dev,
10744                                  struct drm_crtc *crtc,
10745                                  struct drm_framebuffer *fb,
10746                                  struct drm_i915_gem_object *obj,
10747                                  struct intel_engine_cs *ring,
10748                                  uint32_t flags)
10749 {
10750         struct drm_i915_private *dev_priv = dev->dev_private;
10751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10752         uint32_t pf, pipesrc;
10753         int ret;
10754
10755         ret = intel_ring_begin(ring, 4);
10756         if (ret)
10757                 return ret;
10758
10759         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10760                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10761         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10762         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10763
10764         /* Contrary to the suggestions in the documentation,
10765          * "Enable Panel Fitter" does not seem to be required when page
10766          * flipping with a non-native mode, and worse causes a normal
10767          * modeset to fail.
10768          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10769          */
10770         pf = 0;
10771         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10772         intel_ring_emit(ring, pf | pipesrc);
10773
10774         intel_mark_page_flip_active(intel_crtc);
10775         __intel_ring_advance(ring);
10776         return 0;
10777 }
10778
10779 static int intel_gen7_queue_flip(struct drm_device *dev,
10780                                  struct drm_crtc *crtc,
10781                                  struct drm_framebuffer *fb,
10782                                  struct drm_i915_gem_object *obj,
10783                                  struct intel_engine_cs *ring,
10784                                  uint32_t flags)
10785 {
10786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10787         uint32_t plane_bit = 0;
10788         int len, ret;
10789
10790         switch (intel_crtc->plane) {
10791         case PLANE_A:
10792                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10793                 break;
10794         case PLANE_B:
10795                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10796                 break;
10797         case PLANE_C:
10798                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10799                 break;
10800         default:
10801                 WARN_ONCE(1, "unknown plane in flip command\n");
10802                 return -ENODEV;
10803         }
10804
10805         len = 4;
10806         if (ring->id == RCS) {
10807                 len += 6;
10808                 /*
10809                  * On Gen 8, SRM is now taking an extra dword to accommodate
10810                  * 48bits addresses, and we need a NOOP for the batch size to
10811                  * stay even.
10812                  */
10813                 if (IS_GEN8(dev))
10814                         len += 2;
10815         }
10816
10817         /*
10818          * BSpec MI_DISPLAY_FLIP for IVB:
10819          * "The full packet must be contained within the same cache line."
10820          *
10821          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10822          * cacheline, if we ever start emitting more commands before
10823          * the MI_DISPLAY_FLIP we may need to first emit everything else,
10824          * then do the cacheline alignment, and finally emit the
10825          * MI_DISPLAY_FLIP.
10826          */
10827         ret = intel_ring_cacheline_align(ring);
10828         if (ret)
10829                 return ret;
10830
10831         ret = intel_ring_begin(ring, len);
10832         if (ret)
10833                 return ret;
10834
10835         /* Unmask the flip-done completion message. Note that the bspec says that
10836          * we should do this for both the BCS and RCS, and that we must not unmask
10837          * more than one flip event at any time (or ensure that one flip message
10838          * can be sent by waiting for flip-done prior to queueing new flips).
10839          * Experimentation says that BCS works despite DERRMR masking all
10840          * flip-done completion events and that unmasking all planes at once
10841          * for the RCS also doesn't appear to drop events. Setting the DERRMR
10842          * to zero does lead to lockups within MI_DISPLAY_FLIP.
10843          */
10844         if (ring->id == RCS) {
10845                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10846                 intel_ring_emit(ring, DERRMR);
10847                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10848                                         DERRMR_PIPEB_PRI_FLIP_DONE |
10849                                         DERRMR_PIPEC_PRI_FLIP_DONE));
10850                 if (IS_GEN8(dev))
10851                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10852                                               MI_SRM_LRM_GLOBAL_GTT);
10853                 else
10854                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10855                                               MI_SRM_LRM_GLOBAL_GTT);
10856                 intel_ring_emit(ring, DERRMR);
10857                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10858                 if (IS_GEN8(dev)) {
10859                         intel_ring_emit(ring, 0);
10860                         intel_ring_emit(ring, MI_NOOP);
10861                 }
10862         }
10863
10864         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10865         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10866         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10867         intel_ring_emit(ring, (MI_NOOP));
10868
10869         intel_mark_page_flip_active(intel_crtc);
10870         __intel_ring_advance(ring);
10871         return 0;
10872 }
10873
10874 static bool use_mmio_flip(struct intel_engine_cs *ring,
10875                           struct drm_i915_gem_object *obj)
10876 {
10877         /*
10878          * This is not being used for older platforms, because
10879          * non-availability of flip done interrupt forces us to use
10880          * CS flips. Older platforms derive flip done using some clever
10881          * tricks involving the flip_pending status bits and vblank irqs.
10882          * So using MMIO flips there would disrupt this mechanism.
10883          */
10884
10885         if (ring == NULL)
10886                 return true;
10887
10888         if (INTEL_INFO(ring->dev)->gen < 5)
10889                 return false;
10890
10891         if (i915.use_mmio_flip < 0)
10892                 return false;
10893         else if (i915.use_mmio_flip > 0)
10894                 return true;
10895         else if (i915.enable_execlists)
10896                 return true;
10897         else
10898                 return ring != i915_gem_request_get_ring(obj->last_write_req);
10899 }
10900
10901 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10902 {
10903         struct drm_device *dev = intel_crtc->base.dev;
10904         struct drm_i915_private *dev_priv = dev->dev_private;
10905         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10906         const enum pipe pipe = intel_crtc->pipe;
10907         u32 ctl, stride;
10908
10909         ctl = I915_READ(PLANE_CTL(pipe, 0));
10910         ctl &= ~PLANE_CTL_TILED_MASK;
10911         switch (fb->modifier[0]) {
10912         case DRM_FORMAT_MOD_NONE:
10913                 break;
10914         case I915_FORMAT_MOD_X_TILED:
10915                 ctl |= PLANE_CTL_TILED_X;
10916                 break;
10917         case I915_FORMAT_MOD_Y_TILED:
10918                 ctl |= PLANE_CTL_TILED_Y;
10919                 break;
10920         case I915_FORMAT_MOD_Yf_TILED:
10921                 ctl |= PLANE_CTL_TILED_YF;
10922                 break;
10923         default:
10924                 MISSING_CASE(fb->modifier[0]);
10925         }
10926
10927         /*
10928          * The stride is either expressed as a multiple of 64 bytes chunks for
10929          * linear buffers or in number of tiles for tiled buffers.
10930          */
10931         stride = fb->pitches[0] /
10932                  intel_fb_stride_alignment(dev, fb->modifier[0],
10933                                            fb->pixel_format);
10934
10935         /*
10936          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10937          * PLANE_SURF updates, the update is then guaranteed to be atomic.
10938          */
10939         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10940         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10941
10942         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10943         POSTING_READ(PLANE_SURF(pipe, 0));
10944 }
10945
10946 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10947 {
10948         struct drm_device *dev = intel_crtc->base.dev;
10949         struct drm_i915_private *dev_priv = dev->dev_private;
10950         struct intel_framebuffer *intel_fb =
10951                 to_intel_framebuffer(intel_crtc->base.primary->fb);
10952         struct drm_i915_gem_object *obj = intel_fb->obj;
10953         u32 dspcntr;
10954         u32 reg;
10955
10956         reg = DSPCNTR(intel_crtc->plane);
10957         dspcntr = I915_READ(reg);
10958
10959         if (obj->tiling_mode != I915_TILING_NONE)
10960                 dspcntr |= DISPPLANE_TILED;
10961         else
10962                 dspcntr &= ~DISPPLANE_TILED;
10963
10964         I915_WRITE(reg, dspcntr);
10965
10966         I915_WRITE(DSPSURF(intel_crtc->plane),
10967                    intel_crtc->unpin_work->gtt_offset);
10968         POSTING_READ(DSPSURF(intel_crtc->plane));
10969
10970 }
10971
10972 /*
10973  * XXX: This is the temporary way to update the plane registers until we get
10974  * around to using the usual plane update functions for MMIO flips
10975  */
10976 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10977 {
10978         struct drm_device *dev = intel_crtc->base.dev;
10979         bool atomic_update;
10980         u32 start_vbl_count;
10981
10982         intel_mark_page_flip_active(intel_crtc);
10983
10984         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10985
10986         if (INTEL_INFO(dev)->gen >= 9)
10987                 skl_do_mmio_flip(intel_crtc);
10988         else
10989                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10990                 ilk_do_mmio_flip(intel_crtc);
10991
10992         if (atomic_update)
10993                 intel_pipe_update_end(intel_crtc, start_vbl_count);
10994 }
10995
10996 static void intel_mmio_flip_work_func(struct work_struct *work)
10997 {
10998         struct intel_mmio_flip *mmio_flip =
10999                 container_of(work, struct intel_mmio_flip, work);
11000
11001         if (mmio_flip->req)
11002                 WARN_ON(__i915_wait_request(mmio_flip->req,
11003                                             mmio_flip->crtc->reset_counter,
11004                                             false, NULL,
11005                                             &mmio_flip->i915->rps.mmioflips));
11006
11007         intel_do_mmio_flip(mmio_flip->crtc);
11008
11009         i915_gem_request_unreference__unlocked(mmio_flip->req);
11010         kfree(mmio_flip);
11011 }
11012
11013 static int intel_queue_mmio_flip(struct drm_device *dev,
11014                                  struct drm_crtc *crtc,
11015                                  struct drm_framebuffer *fb,
11016                                  struct drm_i915_gem_object *obj,
11017                                  struct intel_engine_cs *ring,
11018                                  uint32_t flags)
11019 {
11020         struct intel_mmio_flip *mmio_flip;
11021
11022         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11023         if (mmio_flip == NULL)
11024                 return -ENOMEM;
11025
11026         mmio_flip->i915 = to_i915(dev);
11027         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11028         mmio_flip->crtc = to_intel_crtc(crtc);
11029
11030         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11031         schedule_work(&mmio_flip->work);
11032
11033         return 0;
11034 }
11035
11036 static int intel_default_queue_flip(struct drm_device *dev,
11037                                     struct drm_crtc *crtc,
11038                                     struct drm_framebuffer *fb,
11039                                     struct drm_i915_gem_object *obj,
11040                                     struct intel_engine_cs *ring,
11041                                     uint32_t flags)
11042 {
11043         return -ENODEV;
11044 }
11045
11046 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11047                                          struct drm_crtc *crtc)
11048 {
11049         struct drm_i915_private *dev_priv = dev->dev_private;
11050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11051         struct intel_unpin_work *work = intel_crtc->unpin_work;
11052         u32 addr;
11053
11054         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11055                 return true;
11056
11057         if (!work->enable_stall_check)
11058                 return false;
11059
11060         if (work->flip_ready_vblank == 0) {
11061                 if (work->flip_queued_req &&
11062                     !i915_gem_request_completed(work->flip_queued_req, true))
11063                         return false;
11064
11065                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11066         }
11067
11068         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11069                 return false;
11070
11071         /* Potential stall - if we see that the flip has happened,
11072          * assume a missed interrupt. */
11073         if (INTEL_INFO(dev)->gen >= 4)
11074                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11075         else
11076                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11077
11078         /* There is a potential issue here with a false positive after a flip
11079          * to the same address. We could address this by checking for a
11080          * non-incrementing frame counter.
11081          */
11082         return addr == work->gtt_offset;
11083 }
11084
11085 void intel_check_page_flip(struct drm_device *dev, int pipe)
11086 {
11087         struct drm_i915_private *dev_priv = dev->dev_private;
11088         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11090         struct intel_unpin_work *work;
11091
11092         WARN_ON(!in_interrupt());
11093
11094         if (crtc == NULL)
11095                 return;
11096
11097         spin_lock(&dev->event_lock);
11098         work = intel_crtc->unpin_work;
11099         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11100                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11101                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11102                 page_flip_completed(intel_crtc);
11103                 work = NULL;
11104         }
11105         if (work != NULL &&
11106             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11107                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11108         spin_unlock(&dev->event_lock);
11109 }
11110
11111 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11112                                 struct drm_framebuffer *fb,
11113                                 struct drm_pending_vblank_event *event,
11114                                 uint32_t page_flip_flags)
11115 {
11116         struct drm_device *dev = crtc->dev;
11117         struct drm_i915_private *dev_priv = dev->dev_private;
11118         struct drm_framebuffer *old_fb = crtc->primary->fb;
11119         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11121         struct drm_plane *primary = crtc->primary;
11122         enum pipe pipe = intel_crtc->pipe;
11123         struct intel_unpin_work *work;
11124         struct intel_engine_cs *ring;
11125         bool mmio_flip;
11126         int ret;
11127
11128         /*
11129          * drm_mode_page_flip_ioctl() should already catch this, but double
11130          * check to be safe.  In the future we may enable pageflipping from
11131          * a disabled primary plane.
11132          */
11133         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11134                 return -EBUSY;
11135
11136         /* Can't change pixel format via MI display flips. */
11137         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11138                 return -EINVAL;
11139
11140         /*
11141          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11142          * Note that pitch changes could also affect these register.
11143          */
11144         if (INTEL_INFO(dev)->gen > 3 &&
11145             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11146              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11147                 return -EINVAL;
11148
11149         if (i915_terminally_wedged(&dev_priv->gpu_error))
11150                 goto out_hang;
11151
11152         work = kzalloc(sizeof(*work), GFP_KERNEL);
11153         if (work == NULL)
11154                 return -ENOMEM;
11155
11156         work->event = event;
11157         work->crtc = crtc;
11158         work->old_fb = old_fb;
11159         INIT_WORK(&work->work, intel_unpin_work_fn);
11160
11161         ret = drm_crtc_vblank_get(crtc);
11162         if (ret)
11163                 goto free_work;
11164
11165         /* We borrow the event spin lock for protecting unpin_work */
11166         spin_lock_irq(&dev->event_lock);
11167         if (intel_crtc->unpin_work) {
11168                 /* Before declaring the flip queue wedged, check if
11169                  * the hardware completed the operation behind our backs.
11170                  */
11171                 if (__intel_pageflip_stall_check(dev, crtc)) {
11172                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11173                         page_flip_completed(intel_crtc);
11174                 } else {
11175                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11176                         spin_unlock_irq(&dev->event_lock);
11177
11178                         drm_crtc_vblank_put(crtc);
11179                         kfree(work);
11180                         return -EBUSY;
11181                 }
11182         }
11183         intel_crtc->unpin_work = work;
11184         spin_unlock_irq(&dev->event_lock);
11185
11186         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11187                 flush_workqueue(dev_priv->wq);
11188
11189         /* Reference the objects for the scheduled work. */
11190         drm_framebuffer_reference(work->old_fb);
11191         drm_gem_object_reference(&obj->base);
11192
11193         crtc->primary->fb = fb;
11194         update_state_fb(crtc->primary);
11195
11196         work->pending_flip_obj = obj;
11197
11198         ret = i915_mutex_lock_interruptible(dev);
11199         if (ret)
11200                 goto cleanup;
11201
11202         atomic_inc(&intel_crtc->unpin_work_count);
11203         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11204
11205         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11206                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11207
11208         if (IS_VALLEYVIEW(dev)) {
11209                 ring = &dev_priv->ring[BCS];
11210                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11211                         /* vlv: DISPLAY_FLIP fails to change tiling */
11212                         ring = NULL;
11213         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11214                 ring = &dev_priv->ring[BCS];
11215         } else if (INTEL_INFO(dev)->gen >= 7) {
11216                 ring = i915_gem_request_get_ring(obj->last_write_req);
11217                 if (ring == NULL || ring->id != RCS)
11218                         ring = &dev_priv->ring[BCS];
11219         } else {
11220                 ring = &dev_priv->ring[RCS];
11221         }
11222
11223         mmio_flip = use_mmio_flip(ring, obj);
11224
11225         /* When using CS flips, we want to emit semaphores between rings.
11226          * However, when using mmio flips we will create a task to do the
11227          * synchronisation, so all we want here is to pin the framebuffer
11228          * into the display plane and skip any waits.
11229          */
11230         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11231                                          crtc->primary->state,
11232                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11233         if (ret)
11234                 goto cleanup_pending;
11235
11236         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11237                                                   + intel_crtc->dspaddr_offset;
11238
11239         if (mmio_flip) {
11240                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11241                                             page_flip_flags);
11242                 if (ret)
11243                         goto cleanup_unpin;
11244
11245                 i915_gem_request_assign(&work->flip_queued_req,
11246                                         obj->last_write_req);
11247         } else {
11248                 if (obj->last_write_req) {
11249                         ret = i915_gem_check_olr(obj->last_write_req);
11250                         if (ret)
11251                                 goto cleanup_unpin;
11252                 }
11253
11254                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11255                                                    page_flip_flags);
11256                 if (ret)
11257                         goto cleanup_unpin;
11258
11259                 i915_gem_request_assign(&work->flip_queued_req,
11260                                         intel_ring_get_request(ring));
11261         }
11262
11263         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11264         work->enable_stall_check = true;
11265
11266         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11267                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11268
11269         intel_fbc_disable(dev);
11270         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11271         mutex_unlock(&dev->struct_mutex);
11272
11273         trace_i915_flip_request(intel_crtc->plane, obj);
11274
11275         return 0;
11276
11277 cleanup_unpin:
11278         intel_unpin_fb_obj(fb, crtc->primary->state);
11279 cleanup_pending:
11280         atomic_dec(&intel_crtc->unpin_work_count);
11281         mutex_unlock(&dev->struct_mutex);
11282 cleanup:
11283         crtc->primary->fb = old_fb;
11284         update_state_fb(crtc->primary);
11285
11286         drm_gem_object_unreference_unlocked(&obj->base);
11287         drm_framebuffer_unreference(work->old_fb);
11288
11289         spin_lock_irq(&dev->event_lock);
11290         intel_crtc->unpin_work = NULL;
11291         spin_unlock_irq(&dev->event_lock);
11292
11293         drm_crtc_vblank_put(crtc);
11294 free_work:
11295         kfree(work);
11296
11297         if (ret == -EIO) {
11298 out_hang:
11299                 ret = intel_plane_restore(primary);
11300                 if (ret == 0 && event) {
11301                         spin_lock_irq(&dev->event_lock);
11302                         drm_send_vblank_event(dev, pipe, event);
11303                         spin_unlock_irq(&dev->event_lock);
11304                 }
11305         }
11306         return ret;
11307 }
11308
11309 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11310         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11311         .load_lut = intel_crtc_load_lut,
11312         .atomic_begin = intel_begin_crtc_commit,
11313         .atomic_flush = intel_finish_crtc_commit,
11314 };
11315
11316 /**
11317  * intel_modeset_update_staged_output_state
11318  *
11319  * Updates the staged output configuration state, e.g. after we've read out the
11320  * current hw state.
11321  */
11322 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11323 {
11324         struct intel_crtc *crtc;
11325         struct intel_encoder *encoder;
11326         struct intel_connector *connector;
11327
11328         for_each_intel_connector(dev, connector) {
11329                 connector->new_encoder =
11330                         to_intel_encoder(connector->base.encoder);
11331         }
11332
11333         for_each_intel_encoder(dev, encoder) {
11334                 encoder->new_crtc =
11335                         to_intel_crtc(encoder->base.crtc);
11336         }
11337
11338         for_each_intel_crtc(dev, crtc) {
11339                 crtc->new_enabled = crtc->base.state->enable;
11340         }
11341 }
11342
11343 /* Transitional helper to copy current connector/encoder state to
11344  * connector->state. This is needed so that code that is partially
11345  * converted to atomic does the right thing.
11346  */
11347 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11348 {
11349         struct intel_connector *connector;
11350
11351         for_each_intel_connector(dev, connector) {
11352                 if (connector->base.encoder) {
11353                         connector->base.state->best_encoder =
11354                                 connector->base.encoder;
11355                         connector->base.state->crtc =
11356                                 connector->base.encoder->crtc;
11357                 } else {
11358                         connector->base.state->best_encoder = NULL;
11359                         connector->base.state->crtc = NULL;
11360                 }
11361         }
11362 }
11363
11364 /* Fixup legacy state after an atomic state swap.
11365  */
11366 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11367 {
11368         struct intel_crtc *crtc;
11369         struct intel_encoder *encoder;
11370         struct intel_connector *connector;
11371
11372         for_each_intel_connector(state->dev, connector) {
11373                 connector->base.encoder = connector->base.state->best_encoder;
11374                 if (connector->base.encoder)
11375                         connector->base.encoder->crtc =
11376                                 connector->base.state->crtc;
11377         }
11378
11379         /* Update crtc of disabled encoders */
11380         for_each_intel_encoder(state->dev, encoder) {
11381                 int num_connectors = 0;
11382
11383                 for_each_intel_connector(state->dev, connector)
11384                         if (connector->base.encoder == &encoder->base)
11385                                 num_connectors++;
11386
11387                 if (num_connectors == 0)
11388                         encoder->base.crtc = NULL;
11389         }
11390
11391         for_each_intel_crtc(state->dev, crtc) {
11392                 crtc->base.enabled = crtc->base.state->enable;
11393                 crtc->config = to_intel_crtc_state(crtc->base.state);
11394         }
11395 }
11396
11397 static void
11398 connected_sink_compute_bpp(struct intel_connector *connector,
11399                            struct intel_crtc_state *pipe_config)
11400 {
11401         int bpp = pipe_config->pipe_bpp;
11402
11403         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11404                 connector->base.base.id,
11405                 connector->base.name);
11406
11407         /* Don't use an invalid EDID bpc value */
11408         if (connector->base.display_info.bpc &&
11409             connector->base.display_info.bpc * 3 < bpp) {
11410                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11411                               bpp, connector->base.display_info.bpc*3);
11412                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11413         }
11414
11415         /* Clamp bpp to 8 on screens without EDID 1.4 */
11416         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11417                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11418                               bpp);
11419                 pipe_config->pipe_bpp = 24;
11420         }
11421 }
11422
11423 static int
11424 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11425                           struct intel_crtc_state *pipe_config)
11426 {
11427         struct drm_device *dev = crtc->base.dev;
11428         struct drm_atomic_state *state;
11429         struct drm_connector *connector;
11430         struct drm_connector_state *connector_state;
11431         int bpp, i;
11432
11433         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11434                 bpp = 10*3;
11435         else if (INTEL_INFO(dev)->gen >= 5)
11436                 bpp = 12*3;
11437         else
11438                 bpp = 8*3;
11439
11440
11441         pipe_config->pipe_bpp = bpp;
11442
11443         state = pipe_config->base.state;
11444
11445         /* Clamp display bpp to EDID value */
11446         for_each_connector_in_state(state, connector, connector_state, i) {
11447                 if (connector_state->crtc != &crtc->base)
11448                         continue;
11449
11450                 connected_sink_compute_bpp(to_intel_connector(connector),
11451                                            pipe_config);
11452         }
11453
11454         return bpp;
11455 }
11456
11457 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11458 {
11459         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11460                         "type: 0x%x flags: 0x%x\n",
11461                 mode->crtc_clock,
11462                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11463                 mode->crtc_hsync_end, mode->crtc_htotal,
11464                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11465                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11466 }
11467
11468 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11469                                    struct intel_crtc_state *pipe_config,
11470                                    const char *context)
11471 {
11472         struct drm_device *dev = crtc->base.dev;
11473         struct drm_plane *plane;
11474         struct intel_plane *intel_plane;
11475         struct intel_plane_state *state;
11476         struct drm_framebuffer *fb;
11477
11478         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11479                       context, pipe_config, pipe_name(crtc->pipe));
11480
11481         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11482         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11483                       pipe_config->pipe_bpp, pipe_config->dither);
11484         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11485                       pipe_config->has_pch_encoder,
11486                       pipe_config->fdi_lanes,
11487                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11488                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11489                       pipe_config->fdi_m_n.tu);
11490         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11491                       pipe_config->has_dp_encoder,
11492                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11493                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11494                       pipe_config->dp_m_n.tu);
11495
11496         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11497                       pipe_config->has_dp_encoder,
11498                       pipe_config->dp_m2_n2.gmch_m,
11499                       pipe_config->dp_m2_n2.gmch_n,
11500                       pipe_config->dp_m2_n2.link_m,
11501                       pipe_config->dp_m2_n2.link_n,
11502                       pipe_config->dp_m2_n2.tu);
11503
11504         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11505                       pipe_config->has_audio,
11506                       pipe_config->has_infoframe);
11507
11508         DRM_DEBUG_KMS("requested mode:\n");
11509         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11510         DRM_DEBUG_KMS("adjusted mode:\n");
11511         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11512         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11513         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11514         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11515                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11516         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11517                       crtc->num_scalers,
11518                       pipe_config->scaler_state.scaler_users,
11519                       pipe_config->scaler_state.scaler_id);
11520         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11521                       pipe_config->gmch_pfit.control,
11522                       pipe_config->gmch_pfit.pgm_ratios,
11523                       pipe_config->gmch_pfit.lvds_border_bits);
11524         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11525                       pipe_config->pch_pfit.pos,
11526                       pipe_config->pch_pfit.size,
11527                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11528         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11529         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11530
11531         if (IS_BROXTON(dev)) {
11532                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11533                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11534                               "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11535                               pipe_config->ddi_pll_sel,
11536                               pipe_config->dpll_hw_state.ebb0,
11537                               pipe_config->dpll_hw_state.pll0,
11538                               pipe_config->dpll_hw_state.pll1,
11539                               pipe_config->dpll_hw_state.pll2,
11540                               pipe_config->dpll_hw_state.pll3,
11541                               pipe_config->dpll_hw_state.pll6,
11542                               pipe_config->dpll_hw_state.pll8,
11543                               pipe_config->dpll_hw_state.pcsdw12);
11544         } else if (IS_SKYLAKE(dev)) {
11545                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11546                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11547                               pipe_config->ddi_pll_sel,
11548                               pipe_config->dpll_hw_state.ctrl1,
11549                               pipe_config->dpll_hw_state.cfgcr1,
11550                               pipe_config->dpll_hw_state.cfgcr2);
11551         } else if (HAS_DDI(dev)) {
11552                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11553                               pipe_config->ddi_pll_sel,
11554                               pipe_config->dpll_hw_state.wrpll);
11555         } else {
11556                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11557                               "fp0: 0x%x, fp1: 0x%x\n",
11558                               pipe_config->dpll_hw_state.dpll,
11559                               pipe_config->dpll_hw_state.dpll_md,
11560                               pipe_config->dpll_hw_state.fp0,
11561                               pipe_config->dpll_hw_state.fp1);
11562         }
11563
11564         DRM_DEBUG_KMS("planes on this crtc\n");
11565         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11566                 intel_plane = to_intel_plane(plane);
11567                 if (intel_plane->pipe != crtc->pipe)
11568                         continue;
11569
11570                 state = to_intel_plane_state(plane->state);
11571                 fb = state->base.fb;
11572                 if (!fb) {
11573                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11574                                 "disabled, scaler_id = %d\n",
11575                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11576                                 plane->base.id, intel_plane->pipe,
11577                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11578                                 drm_plane_index(plane), state->scaler_id);
11579                         continue;
11580                 }
11581
11582                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11583                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11584                         plane->base.id, intel_plane->pipe,
11585                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11586                         drm_plane_index(plane));
11587                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11588                         fb->base.id, fb->width, fb->height, fb->pixel_format);
11589                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11590                         state->scaler_id,
11591                         state->src.x1 >> 16, state->src.y1 >> 16,
11592                         drm_rect_width(&state->src) >> 16,
11593                         drm_rect_height(&state->src) >> 16,
11594                         state->dst.x1, state->dst.y1,
11595                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11596         }
11597 }
11598
11599 static bool encoders_cloneable(const struct intel_encoder *a,
11600                                const struct intel_encoder *b)
11601 {
11602         /* masks could be asymmetric, so check both ways */
11603         return a == b || (a->cloneable & (1 << b->type) &&
11604                           b->cloneable & (1 << a->type));
11605 }
11606
11607 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11608                                          struct intel_crtc *crtc,
11609                                          struct intel_encoder *encoder)
11610 {
11611         struct intel_encoder *source_encoder;
11612         struct drm_connector *connector;
11613         struct drm_connector_state *connector_state;
11614         int i;
11615
11616         for_each_connector_in_state(state, connector, connector_state, i) {
11617                 if (connector_state->crtc != &crtc->base)
11618                         continue;
11619
11620                 source_encoder =
11621                         to_intel_encoder(connector_state->best_encoder);
11622                 if (!encoders_cloneable(encoder, source_encoder))
11623                         return false;
11624         }
11625
11626         return true;
11627 }
11628
11629 static bool check_encoder_cloning(struct drm_atomic_state *state,
11630                                   struct intel_crtc *crtc)
11631 {
11632         struct intel_encoder *encoder;
11633         struct drm_connector *connector;
11634         struct drm_connector_state *connector_state;
11635         int i;
11636
11637         for_each_connector_in_state(state, connector, connector_state, i) {
11638                 if (connector_state->crtc != &crtc->base)
11639                         continue;
11640
11641                 encoder = to_intel_encoder(connector_state->best_encoder);
11642                 if (!check_single_encoder_cloning(state, crtc, encoder))
11643                         return false;
11644         }
11645
11646         return true;
11647 }
11648
11649 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11650 {
11651         struct drm_device *dev = state->dev;
11652         struct intel_encoder *encoder;
11653         struct drm_connector *connector;
11654         struct drm_connector_state *connector_state;
11655         unsigned int used_ports = 0;
11656         int i;
11657
11658         /*
11659          * Walk the connector list instead of the encoder
11660          * list to detect the problem on ddi platforms
11661          * where there's just one encoder per digital port.
11662          */
11663         for_each_connector_in_state(state, connector, connector_state, i) {
11664                 if (!connector_state->best_encoder)
11665                         continue;
11666
11667                 encoder = to_intel_encoder(connector_state->best_encoder);
11668
11669                 WARN_ON(!connector_state->crtc);
11670
11671                 switch (encoder->type) {
11672                         unsigned int port_mask;
11673                 case INTEL_OUTPUT_UNKNOWN:
11674                         if (WARN_ON(!HAS_DDI(dev)))
11675                                 break;
11676                 case INTEL_OUTPUT_DISPLAYPORT:
11677                 case INTEL_OUTPUT_HDMI:
11678                 case INTEL_OUTPUT_EDP:
11679                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11680
11681                         /* the same port mustn't appear more than once */
11682                         if (used_ports & port_mask)
11683                                 return false;
11684
11685                         used_ports |= port_mask;
11686                 default:
11687                         break;
11688                 }
11689         }
11690
11691         return true;
11692 }
11693
11694 static void
11695 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11696 {
11697         struct drm_crtc_state tmp_state;
11698         struct intel_crtc_scaler_state scaler_state;
11699         struct intel_dpll_hw_state dpll_hw_state;
11700         enum intel_dpll_id shared_dpll;
11701         uint32_t ddi_pll_sel;
11702
11703         /* FIXME: before the switch to atomic started, a new pipe_config was
11704          * kzalloc'd. Code that depends on any field being zero should be
11705          * fixed, so that the crtc_state can be safely duplicated. For now,
11706          * only fields that are know to not cause problems are preserved. */
11707
11708         tmp_state = crtc_state->base;
11709         scaler_state = crtc_state->scaler_state;
11710         shared_dpll = crtc_state->shared_dpll;
11711         dpll_hw_state = crtc_state->dpll_hw_state;
11712         ddi_pll_sel = crtc_state->ddi_pll_sel;
11713
11714         memset(crtc_state, 0, sizeof *crtc_state);
11715
11716         crtc_state->base = tmp_state;
11717         crtc_state->scaler_state = scaler_state;
11718         crtc_state->shared_dpll = shared_dpll;
11719         crtc_state->dpll_hw_state = dpll_hw_state;
11720         crtc_state->ddi_pll_sel = ddi_pll_sel;
11721 }
11722
11723 static int
11724 intel_modeset_pipe_config(struct drm_crtc *crtc,
11725                           struct drm_atomic_state *state,
11726                           struct intel_crtc_state *pipe_config)
11727 {
11728         struct intel_encoder *encoder;
11729         struct drm_connector *connector;
11730         struct drm_connector_state *connector_state;
11731         int base_bpp, ret = -EINVAL;
11732         int i;
11733         bool retry = true;
11734
11735         if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11736                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11737                 return -EINVAL;
11738         }
11739
11740         if (!check_digital_port_conflicts(state)) {
11741                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11742                 return -EINVAL;
11743         }
11744
11745         clear_intel_crtc_state(pipe_config);
11746
11747         pipe_config->cpu_transcoder =
11748                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11749
11750         /*
11751          * Sanitize sync polarity flags based on requested ones. If neither
11752          * positive or negative polarity is requested, treat this as meaning
11753          * negative polarity.
11754          */
11755         if (!(pipe_config->base.adjusted_mode.flags &
11756               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11757                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11758
11759         if (!(pipe_config->base.adjusted_mode.flags &
11760               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11761                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11762
11763         /* Compute a starting value for pipe_config->pipe_bpp taking the source
11764          * plane pixel format and any sink constraints into account. Returns the
11765          * source plane bpp so that dithering can be selected on mismatches
11766          * after encoders and crtc also have had their say. */
11767         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11768                                              pipe_config);
11769         if (base_bpp < 0)
11770                 goto fail;
11771
11772         /*
11773          * Determine the real pipe dimensions. Note that stereo modes can
11774          * increase the actual pipe size due to the frame doubling and
11775          * insertion of additional space for blanks between the frame. This
11776          * is stored in the crtc timings. We use the requested mode to do this
11777          * computation to clearly distinguish it from the adjusted mode, which
11778          * can be changed by the connectors in the below retry loop.
11779          */
11780         drm_crtc_get_hv_timing(&pipe_config->base.mode,
11781                                &pipe_config->pipe_src_w,
11782                                &pipe_config->pipe_src_h);
11783
11784 encoder_retry:
11785         /* Ensure the port clock defaults are reset when retrying. */
11786         pipe_config->port_clock = 0;
11787         pipe_config->pixel_multiplier = 1;
11788
11789         /* Fill in default crtc timings, allow encoders to overwrite them. */
11790         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11791                               CRTC_STEREO_DOUBLE);
11792
11793         /* Pass our mode to the connectors and the CRTC to give them a chance to
11794          * adjust it according to limitations or connector properties, and also
11795          * a chance to reject the mode entirely.
11796          */
11797         for_each_connector_in_state(state, connector, connector_state, i) {
11798                 if (connector_state->crtc != crtc)
11799                         continue;
11800
11801                 encoder = to_intel_encoder(connector_state->best_encoder);
11802
11803                 if (!(encoder->compute_config(encoder, pipe_config))) {
11804                         DRM_DEBUG_KMS("Encoder config failure\n");
11805                         goto fail;
11806                 }
11807         }
11808
11809         /* Set default port clock if not overwritten by the encoder. Needs to be
11810          * done afterwards in case the encoder adjusts the mode. */
11811         if (!pipe_config->port_clock)
11812                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11813                         * pipe_config->pixel_multiplier;
11814
11815         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11816         if (ret < 0) {
11817                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11818                 goto fail;
11819         }
11820
11821         if (ret == RETRY) {
11822                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11823                         ret = -EINVAL;
11824                         goto fail;
11825                 }
11826
11827                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11828                 retry = false;
11829                 goto encoder_retry;
11830         }
11831
11832         pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11833         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11834                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11835
11836         return 0;
11837 fail:
11838         return ret;
11839 }
11840
11841 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11842 {
11843         struct drm_encoder *encoder;
11844         struct drm_device *dev = crtc->dev;
11845
11846         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11847                 if (encoder->crtc == crtc)
11848                         return true;
11849
11850         return false;
11851 }
11852
11853 static bool
11854 needs_modeset(struct drm_crtc_state *state)
11855 {
11856         return state->mode_changed || state->active_changed;
11857 }
11858
11859 static void
11860 intel_modeset_update_state(struct drm_atomic_state *state)
11861 {
11862         struct drm_device *dev = state->dev;
11863         struct drm_i915_private *dev_priv = dev->dev_private;
11864         struct intel_encoder *intel_encoder;
11865         struct drm_crtc *crtc;
11866         struct drm_crtc_state *crtc_state;
11867         struct drm_connector *connector;
11868         int i;
11869
11870         intel_shared_dpll_commit(dev_priv);
11871
11872         for_each_intel_encoder(dev, intel_encoder) {
11873                 if (!intel_encoder->base.crtc)
11874                         continue;
11875
11876                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
11877                         if (crtc != intel_encoder->base.crtc)
11878                                 continue;
11879
11880                         if (crtc_state->enable && needs_modeset(crtc_state))
11881                                 intel_encoder->connectors_active = false;
11882
11883                         break;
11884                 }
11885         }
11886
11887         drm_atomic_helper_swap_state(state->dev, state);
11888         intel_modeset_fixup_state(state);
11889
11890         /* Double check state. */
11891         for_each_crtc(dev, crtc) {
11892                 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11893         }
11894
11895         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11896                 if (!connector->encoder || !connector->encoder->crtc)
11897                         continue;
11898
11899                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
11900                         if (crtc != connector->encoder->crtc)
11901                                 continue;
11902
11903                         if (crtc->state->enable && needs_modeset(crtc->state)) {
11904                                 struct drm_property *dpms_property =
11905                                         dev->mode_config.dpms_property;
11906
11907                                 connector->dpms = DRM_MODE_DPMS_ON;
11908                                 drm_object_property_set_value(&connector->base,
11909                                                                  dpms_property,
11910                                                                  DRM_MODE_DPMS_ON);
11911
11912                                 intel_encoder = to_intel_encoder(connector->encoder);
11913                                 intel_encoder->connectors_active = true;
11914                         }
11915
11916                         break;
11917                 }
11918         }
11919
11920 }
11921
11922 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11923 {
11924         int diff;
11925
11926         if (clock1 == clock2)
11927                 return true;
11928
11929         if (!clock1 || !clock2)
11930                 return false;
11931
11932         diff = abs(clock1 - clock2);
11933
11934         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11935                 return true;
11936
11937         return false;
11938 }
11939
11940 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11941         list_for_each_entry((intel_crtc), \
11942                             &(dev)->mode_config.crtc_list, \
11943                             base.head) \
11944                 if (mask & (1 <<(intel_crtc)->pipe))
11945
11946 static bool
11947 intel_pipe_config_compare(struct drm_device *dev,
11948                           struct intel_crtc_state *current_config,
11949                           struct intel_crtc_state *pipe_config)
11950 {
11951 #define PIPE_CONF_CHECK_X(name) \
11952         if (current_config->name != pipe_config->name) { \
11953                 DRM_ERROR("mismatch in " #name " " \
11954                           "(expected 0x%08x, found 0x%08x)\n", \
11955                           current_config->name, \
11956                           pipe_config->name); \
11957                 return false; \
11958         }
11959
11960 #define PIPE_CONF_CHECK_I(name) \
11961         if (current_config->name != pipe_config->name) { \
11962                 DRM_ERROR("mismatch in " #name " " \
11963                           "(expected %i, found %i)\n", \
11964                           current_config->name, \
11965                           pipe_config->name); \
11966                 return false; \
11967         }
11968
11969 /* This is required for BDW+ where there is only one set of registers for
11970  * switching between high and low RR.
11971  * This macro can be used whenever a comparison has to be made between one
11972  * hw state and multiple sw state variables.
11973  */
11974 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11975         if ((current_config->name != pipe_config->name) && \
11976                 (current_config->alt_name != pipe_config->name)) { \
11977                         DRM_ERROR("mismatch in " #name " " \
11978                                   "(expected %i or %i, found %i)\n", \
11979                                   current_config->name, \
11980                                   current_config->alt_name, \
11981                                   pipe_config->name); \
11982                         return false; \
11983         }
11984
11985 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11986         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11987                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
11988                           "(expected %i, found %i)\n", \
11989                           current_config->name & (mask), \
11990                           pipe_config->name & (mask)); \
11991                 return false; \
11992         }
11993
11994 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11995         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11996                 DRM_ERROR("mismatch in " #name " " \
11997                           "(expected %i, found %i)\n", \
11998                           current_config->name, \
11999                           pipe_config->name); \
12000                 return false; \
12001         }
12002
12003 #define PIPE_CONF_QUIRK(quirk)  \
12004         ((current_config->quirks | pipe_config->quirks) & (quirk))
12005
12006         PIPE_CONF_CHECK_I(cpu_transcoder);
12007
12008         PIPE_CONF_CHECK_I(has_pch_encoder);
12009         PIPE_CONF_CHECK_I(fdi_lanes);
12010         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12011         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12012         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12013         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12014         PIPE_CONF_CHECK_I(fdi_m_n.tu);
12015
12016         PIPE_CONF_CHECK_I(has_dp_encoder);
12017
12018         if (INTEL_INFO(dev)->gen < 8) {
12019                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12020                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12021                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12022                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12023                 PIPE_CONF_CHECK_I(dp_m_n.tu);
12024
12025                 if (current_config->has_drrs) {
12026                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12027                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12028                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12029                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12030                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12031                 }
12032         } else {
12033                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12034                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12035                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12036                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12037                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12038         }
12039
12040         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12041         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12042         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12043         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12044         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12045         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12046
12047         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12048         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12049         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12050         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12051         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12052         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12053
12054         PIPE_CONF_CHECK_I(pixel_multiplier);
12055         PIPE_CONF_CHECK_I(has_hdmi_sink);
12056         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12057             IS_VALLEYVIEW(dev))
12058                 PIPE_CONF_CHECK_I(limited_color_range);
12059         PIPE_CONF_CHECK_I(has_infoframe);
12060
12061         PIPE_CONF_CHECK_I(has_audio);
12062
12063         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12064                               DRM_MODE_FLAG_INTERLACE);
12065
12066         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12067                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12068                                       DRM_MODE_FLAG_PHSYNC);
12069                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12070                                       DRM_MODE_FLAG_NHSYNC);
12071                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12072                                       DRM_MODE_FLAG_PVSYNC);
12073                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12074                                       DRM_MODE_FLAG_NVSYNC);
12075         }
12076
12077         PIPE_CONF_CHECK_I(pipe_src_w);
12078         PIPE_CONF_CHECK_I(pipe_src_h);
12079
12080         /*
12081          * FIXME: BIOS likes to set up a cloned config with lvds+external
12082          * screen. Since we don't yet re-compute the pipe config when moving
12083          * just the lvds port away to another pipe the sw tracking won't match.
12084          *
12085          * Proper atomic modesets with recomputed global state will fix this.
12086          * Until then just don't check gmch state for inherited modes.
12087          */
12088         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12089                 PIPE_CONF_CHECK_I(gmch_pfit.control);
12090                 /* pfit ratios are autocomputed by the hw on gen4+ */
12091                 if (INTEL_INFO(dev)->gen < 4)
12092                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12093                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12094         }
12095
12096         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12097         if (current_config->pch_pfit.enabled) {
12098                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12099                 PIPE_CONF_CHECK_I(pch_pfit.size);
12100         }
12101
12102         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12103
12104         /* BDW+ don't expose a synchronous way to read the state */
12105         if (IS_HASWELL(dev))
12106                 PIPE_CONF_CHECK_I(ips_enabled);
12107
12108         PIPE_CONF_CHECK_I(double_wide);
12109
12110         PIPE_CONF_CHECK_X(ddi_pll_sel);
12111
12112         PIPE_CONF_CHECK_I(shared_dpll);
12113         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12114         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12115         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12116         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12117         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12118         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12119         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12120         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12121
12122         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12123                 PIPE_CONF_CHECK_I(pipe_bpp);
12124
12125         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12126         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12127
12128 #undef PIPE_CONF_CHECK_X
12129 #undef PIPE_CONF_CHECK_I
12130 #undef PIPE_CONF_CHECK_I_ALT
12131 #undef PIPE_CONF_CHECK_FLAGS
12132 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12133 #undef PIPE_CONF_QUIRK
12134
12135         return true;
12136 }
12137
12138 static void check_wm_state(struct drm_device *dev)
12139 {
12140         struct drm_i915_private *dev_priv = dev->dev_private;
12141         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12142         struct intel_crtc *intel_crtc;
12143         int plane;
12144
12145         if (INTEL_INFO(dev)->gen < 9)
12146                 return;
12147
12148         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12149         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12150
12151         for_each_intel_crtc(dev, intel_crtc) {
12152                 struct skl_ddb_entry *hw_entry, *sw_entry;
12153                 const enum pipe pipe = intel_crtc->pipe;
12154
12155                 if (!intel_crtc->active)
12156                         continue;
12157
12158                 /* planes */
12159                 for_each_plane(dev_priv, pipe, plane) {
12160                         hw_entry = &hw_ddb.plane[pipe][plane];
12161                         sw_entry = &sw_ddb->plane[pipe][plane];
12162
12163                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12164                                 continue;
12165
12166                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12167                                   "(expected (%u,%u), found (%u,%u))\n",
12168                                   pipe_name(pipe), plane + 1,
12169                                   sw_entry->start, sw_entry->end,
12170                                   hw_entry->start, hw_entry->end);
12171                 }
12172
12173                 /* cursor */
12174                 hw_entry = &hw_ddb.cursor[pipe];
12175                 sw_entry = &sw_ddb->cursor[pipe];
12176
12177                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12178                         continue;
12179
12180                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12181                           "(expected (%u,%u), found (%u,%u))\n",
12182                           pipe_name(pipe),
12183                           sw_entry->start, sw_entry->end,
12184                           hw_entry->start, hw_entry->end);
12185         }
12186 }
12187
12188 static void
12189 check_connector_state(struct drm_device *dev)
12190 {
12191         struct intel_connector *connector;
12192
12193         for_each_intel_connector(dev, connector) {
12194                 /* This also checks the encoder/connector hw state with the
12195                  * ->get_hw_state callbacks. */
12196                 intel_connector_check_state(connector);
12197
12198                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12199                      "connector's staged encoder doesn't match current encoder\n");
12200         }
12201 }
12202
12203 static void
12204 check_encoder_state(struct drm_device *dev)
12205 {
12206         struct intel_encoder *encoder;
12207         struct intel_connector *connector;
12208
12209         for_each_intel_encoder(dev, encoder) {
12210                 bool enabled = false;
12211                 bool active = false;
12212                 enum pipe pipe, tracked_pipe;
12213
12214                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12215                               encoder->base.base.id,
12216                               encoder->base.name);
12217
12218                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12219                      "encoder's stage crtc doesn't match current crtc\n");
12220                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12221                      "encoder's active_connectors set, but no crtc\n");
12222
12223                 for_each_intel_connector(dev, connector) {
12224                         if (connector->base.encoder != &encoder->base)
12225                                 continue;
12226                         enabled = true;
12227                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12228                                 active = true;
12229                 }
12230                 /*
12231                  * for MST connectors if we unplug the connector is gone
12232                  * away but the encoder is still connected to a crtc
12233                  * until a modeset happens in response to the hotplug.
12234                  */
12235                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12236                         continue;
12237
12238                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12239                      "encoder's enabled state mismatch "
12240                      "(expected %i, found %i)\n",
12241                      !!encoder->base.crtc, enabled);
12242                 I915_STATE_WARN(active && !encoder->base.crtc,
12243                      "active encoder with no crtc\n");
12244
12245                 I915_STATE_WARN(encoder->connectors_active != active,
12246                      "encoder's computed active state doesn't match tracked active state "
12247                      "(expected %i, found %i)\n", active, encoder->connectors_active);
12248
12249                 active = encoder->get_hw_state(encoder, &pipe);
12250                 I915_STATE_WARN(active != encoder->connectors_active,
12251                      "encoder's hw state doesn't match sw tracking "
12252                      "(expected %i, found %i)\n",
12253                      encoder->connectors_active, active);
12254
12255                 if (!encoder->base.crtc)
12256                         continue;
12257
12258                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12259                 I915_STATE_WARN(active && pipe != tracked_pipe,
12260                      "active encoder's pipe doesn't match"
12261                      "(expected %i, found %i)\n",
12262                      tracked_pipe, pipe);
12263
12264         }
12265 }
12266
12267 static void
12268 check_crtc_state(struct drm_device *dev)
12269 {
12270         struct drm_i915_private *dev_priv = dev->dev_private;
12271         struct intel_crtc *crtc;
12272         struct intel_encoder *encoder;
12273         struct intel_crtc_state pipe_config;
12274
12275         for_each_intel_crtc(dev, crtc) {
12276                 bool enabled = false;
12277                 bool active = false;
12278
12279                 memset(&pipe_config, 0, sizeof(pipe_config));
12280
12281                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12282                               crtc->base.base.id);
12283
12284                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12285                      "active crtc, but not enabled in sw tracking\n");
12286
12287                 for_each_intel_encoder(dev, encoder) {
12288                         if (encoder->base.crtc != &crtc->base)
12289                                 continue;
12290                         enabled = true;
12291                         if (encoder->connectors_active)
12292                                 active = true;
12293                 }
12294
12295                 I915_STATE_WARN(active != crtc->active,
12296                      "crtc's computed active state doesn't match tracked active state "
12297                      "(expected %i, found %i)\n", active, crtc->active);
12298                 I915_STATE_WARN(enabled != crtc->base.state->enable,
12299                      "crtc's computed enabled state doesn't match tracked enabled state "
12300                      "(expected %i, found %i)\n", enabled,
12301                                 crtc->base.state->enable);
12302
12303                 active = dev_priv->display.get_pipe_config(crtc,
12304                                                            &pipe_config);
12305
12306                 /* hw state is inconsistent with the pipe quirk */
12307                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12308                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12309                         active = crtc->active;
12310
12311                 for_each_intel_encoder(dev, encoder) {
12312                         enum pipe pipe;
12313                         if (encoder->base.crtc != &crtc->base)
12314                                 continue;
12315                         if (encoder->get_hw_state(encoder, &pipe))
12316                                 encoder->get_config(encoder, &pipe_config);
12317                 }
12318
12319                 I915_STATE_WARN(crtc->active != active,
12320                      "crtc active state doesn't match with hw state "
12321                      "(expected %i, found %i)\n", crtc->active, active);
12322
12323                 if (active &&
12324                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12325                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12326                         intel_dump_pipe_config(crtc, &pipe_config,
12327                                                "[hw state]");
12328                         intel_dump_pipe_config(crtc, crtc->config,
12329                                                "[sw state]");
12330                 }
12331         }
12332 }
12333
12334 static void
12335 check_shared_dpll_state(struct drm_device *dev)
12336 {
12337         struct drm_i915_private *dev_priv = dev->dev_private;
12338         struct intel_crtc *crtc;
12339         struct intel_dpll_hw_state dpll_hw_state;
12340         int i;
12341
12342         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12343                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12344                 int enabled_crtcs = 0, active_crtcs = 0;
12345                 bool active;
12346
12347                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12348
12349                 DRM_DEBUG_KMS("%s\n", pll->name);
12350
12351                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12352
12353                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12354                      "more active pll users than references: %i vs %i\n",
12355                      pll->active, hweight32(pll->config.crtc_mask));
12356                 I915_STATE_WARN(pll->active && !pll->on,
12357                      "pll in active use but not on in sw tracking\n");
12358                 I915_STATE_WARN(pll->on && !pll->active,
12359                      "pll in on but not on in use in sw tracking\n");
12360                 I915_STATE_WARN(pll->on != active,
12361                      "pll on state mismatch (expected %i, found %i)\n",
12362                      pll->on, active);
12363
12364                 for_each_intel_crtc(dev, crtc) {
12365                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12366                                 enabled_crtcs++;
12367                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12368                                 active_crtcs++;
12369                 }
12370                 I915_STATE_WARN(pll->active != active_crtcs,
12371                      "pll active crtcs mismatch (expected %i, found %i)\n",
12372                      pll->active, active_crtcs);
12373                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12374                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12375                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12376
12377                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12378                                        sizeof(dpll_hw_state)),
12379                      "pll hw state mismatch\n");
12380         }
12381 }
12382
12383 void
12384 intel_modeset_check_state(struct drm_device *dev)
12385 {
12386         check_wm_state(dev);
12387         check_connector_state(dev);
12388         check_encoder_state(dev);
12389         check_crtc_state(dev);
12390         check_shared_dpll_state(dev);
12391 }
12392
12393 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12394                                      int dotclock)
12395 {
12396         /*
12397          * FDI already provided one idea for the dotclock.
12398          * Yell if the encoder disagrees.
12399          */
12400         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12401              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12402              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12403 }
12404
12405 static void update_scanline_offset(struct intel_crtc *crtc)
12406 {
12407         struct drm_device *dev = crtc->base.dev;
12408
12409         /*
12410          * The scanline counter increments at the leading edge of hsync.
12411          *
12412          * On most platforms it starts counting from vtotal-1 on the
12413          * first active line. That means the scanline counter value is
12414          * always one less than what we would expect. Ie. just after
12415          * start of vblank, which also occurs at start of hsync (on the
12416          * last active line), the scanline counter will read vblank_start-1.
12417          *
12418          * On gen2 the scanline counter starts counting from 1 instead
12419          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12420          * to keep the value positive), instead of adding one.
12421          *
12422          * On HSW+ the behaviour of the scanline counter depends on the output
12423          * type. For DP ports it behaves like most other platforms, but on HDMI
12424          * there's an extra 1 line difference. So we need to add two instead of
12425          * one to the value.
12426          */
12427         if (IS_GEN2(dev)) {
12428                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12429                 int vtotal;
12430
12431                 vtotal = mode->crtc_vtotal;
12432                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12433                         vtotal /= 2;
12434
12435                 crtc->scanline_offset = vtotal - 1;
12436         } else if (HAS_DDI(dev) &&
12437                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12438                 crtc->scanline_offset = 2;
12439         } else
12440                 crtc->scanline_offset = 1;
12441 }
12442
12443 static struct intel_crtc_state *
12444 intel_modeset_compute_config(struct drm_crtc *crtc,
12445                              struct drm_atomic_state *state)
12446 {
12447         struct intel_crtc_state *pipe_config;
12448         int ret = 0;
12449
12450         ret = drm_atomic_add_affected_connectors(state, crtc);
12451         if (ret)
12452                 return ERR_PTR(ret);
12453
12454         ret = drm_atomic_helper_check_modeset(state->dev, state);
12455         if (ret)
12456                 return ERR_PTR(ret);
12457
12458         /*
12459          * Note this needs changes when we start tracking multiple modes
12460          * and crtcs.  At that point we'll need to compute the whole config
12461          * (i.e. one pipe_config for each crtc) rather than just the one
12462          * for this crtc.
12463          */
12464         pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12465         if (IS_ERR(pipe_config))
12466                 return pipe_config;
12467
12468         if (!pipe_config->base.enable)
12469                 return pipe_config;
12470
12471         ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12472         if (ret)
12473                 return ERR_PTR(ret);
12474
12475         /* Check things that can only be changed through modeset */
12476         if (pipe_config->has_audio !=
12477             to_intel_crtc(crtc)->config->has_audio)
12478                 pipe_config->base.mode_changed = true;
12479
12480         /*
12481          * Note we have an issue here with infoframes: current code
12482          * only updates them on the full mode set path per hw
12483          * requirements.  So here we should be checking for any
12484          * required changes and forcing a mode set.
12485          */
12486
12487         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12488
12489         ret = drm_atomic_helper_check_planes(state->dev, state);
12490         if (ret)
12491                 return ERR_PTR(ret);
12492
12493         return pipe_config;
12494 }
12495
12496 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12497 {
12498         struct drm_device *dev = state->dev;
12499         struct drm_i915_private *dev_priv = to_i915(dev);
12500         unsigned clear_pipes = 0;
12501         struct intel_crtc *intel_crtc;
12502         struct intel_crtc_state *intel_crtc_state;
12503         struct drm_crtc *crtc;
12504         struct drm_crtc_state *crtc_state;
12505         int ret = 0;
12506         int i;
12507
12508         if (!dev_priv->display.crtc_compute_clock)
12509                 return 0;
12510
12511         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12512                 intel_crtc = to_intel_crtc(crtc);
12513                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12514
12515                 if (needs_modeset(crtc_state)) {
12516                         clear_pipes |= 1 << intel_crtc->pipe;
12517                         intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12518                 }
12519         }
12520
12521         ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12522         if (ret)
12523                 goto done;
12524
12525         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12526                 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12527                         continue;
12528
12529                 intel_crtc = to_intel_crtc(crtc);
12530                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12531
12532                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12533                                                            intel_crtc_state);
12534                 if (ret) {
12535                         intel_shared_dpll_abort_config(dev_priv);
12536                         goto done;
12537                 }
12538         }
12539
12540 done:
12541         return ret;
12542 }
12543
12544 /* Code that should eventually be part of atomic_check() */
12545 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12546 {
12547         struct drm_device *dev = state->dev;
12548         int ret;
12549
12550         /*
12551          * See if the config requires any additional preparation, e.g.
12552          * to adjust global state with pipes off.  We need to do this
12553          * here so we can get the modeset_pipe updated config for the new
12554          * mode set on this crtc.  For other crtcs we need to use the
12555          * adjusted_mode bits in the crtc directly.
12556          */
12557         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12558                 ret = valleyview_modeset_global_pipes(state);
12559                 if (ret)
12560                         return ret;
12561         }
12562
12563         ret = __intel_set_mode_setup_plls(state);
12564         if (ret)
12565                 return ret;
12566
12567         return 0;
12568 }
12569
12570 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12571                             struct intel_crtc_state *pipe_config)
12572 {
12573         struct drm_device *dev = modeset_crtc->dev;
12574         struct drm_i915_private *dev_priv = dev->dev_private;
12575         struct drm_atomic_state *state = pipe_config->base.state;
12576         struct drm_crtc *crtc;
12577         struct drm_crtc_state *crtc_state;
12578         int ret = 0;
12579         int i;
12580
12581         ret = __intel_set_mode_checks(state);
12582         if (ret < 0)
12583                 return ret;
12584
12585         ret = drm_atomic_helper_prepare_planes(dev, state);
12586         if (ret)
12587                 return ret;
12588
12589         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12590                 if (!needs_modeset(crtc_state))
12591                         continue;
12592
12593                 if (!crtc_state->enable) {
12594                         intel_crtc_disable(crtc);
12595                 } else if (crtc->state->enable) {
12596                         intel_crtc_disable_planes(crtc);
12597                         dev_priv->display.crtc_disable(crtc);
12598                 }
12599         }
12600
12601         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12602          * to set it here already despite that we pass it down the callchain.
12603          *
12604          * Note we'll need to fix this up when we start tracking multiple
12605          * pipes; here we assume a single modeset_pipe and only track the
12606          * single crtc and mode.
12607          */
12608         if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12609                 modeset_crtc->mode = pipe_config->base.mode;
12610
12611                 /*
12612                  * Calculate and store various constants which
12613                  * are later needed by vblank and swap-completion
12614                  * timestamping. They are derived from true hwmode.
12615                  */
12616                 drm_calc_timestamping_constants(modeset_crtc,
12617                                                 &pipe_config->base.adjusted_mode);
12618         }
12619
12620         /* Only after disabling all output pipelines that will be changed can we
12621          * update the the output configuration. */
12622         intel_modeset_update_state(state);
12623
12624         /* The state has been swaped above, so state actually contains the
12625          * old state now. */
12626
12627         modeset_update_crtc_power_domains(state);
12628
12629         drm_atomic_helper_commit_planes(dev, state);
12630
12631         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12632         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12633                 if (!needs_modeset(crtc->state) || !crtc->state->enable)
12634                         continue;
12635
12636                 update_scanline_offset(to_intel_crtc(crtc));
12637
12638                 dev_priv->display.crtc_enable(crtc);
12639                 intel_crtc_enable_planes(crtc);
12640         }
12641
12642         /* FIXME: add subpixel order */
12643
12644         drm_atomic_helper_cleanup_planes(dev, state);
12645
12646         drm_atomic_state_free(state);
12647
12648         return 0;
12649 }
12650
12651 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12652                                       struct intel_crtc_state *pipe_config,
12653                                       bool force_restore)
12654 {
12655         int ret;
12656
12657         ret = __intel_set_mode(crtc, pipe_config);
12658
12659         if (ret == 0 && force_restore) {
12660                 intel_modeset_update_staged_output_state(crtc->dev);
12661                 intel_modeset_check_state(crtc->dev);
12662         }
12663
12664         return ret;
12665 }
12666
12667 static int intel_set_mode(struct drm_crtc *crtc,
12668                           struct drm_atomic_state *state,
12669                           bool force_restore)
12670 {
12671         struct intel_crtc_state *pipe_config;
12672         int ret = 0;
12673
12674         pipe_config = intel_modeset_compute_config(crtc, state);
12675         if (IS_ERR(pipe_config)) {
12676                 ret = PTR_ERR(pipe_config);
12677                 goto out;
12678         }
12679
12680         ret = intel_set_mode_with_config(crtc, pipe_config, force_restore);
12681         if (ret)
12682                 goto out;
12683
12684 out:
12685         return ret;
12686 }
12687
12688 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12689 {
12690         struct drm_device *dev = crtc->dev;
12691         struct drm_atomic_state *state;
12692         struct intel_encoder *encoder;
12693         struct intel_connector *connector;
12694         struct drm_connector_state *connector_state;
12695         struct intel_crtc_state *crtc_state;
12696         int ret;
12697
12698         state = drm_atomic_state_alloc(dev);
12699         if (!state) {
12700                 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12701                               crtc->base.id);
12702                 return;
12703         }
12704
12705         state->acquire_ctx = dev->mode_config.acquire_ctx;
12706
12707         /* The force restore path in the HW readout code relies on the staged
12708          * config still keeping the user requested config while the actual
12709          * state has been overwritten by the configuration read from HW. We
12710          * need to copy the staged config to the atomic state, otherwise the
12711          * mode set will just reapply the state the HW is already in. */
12712         for_each_intel_encoder(dev, encoder) {
12713                 if (&encoder->new_crtc->base != crtc)
12714                         continue;
12715
12716                 for_each_intel_connector(dev, connector) {
12717                         if (connector->new_encoder != encoder)
12718                                 continue;
12719
12720                         connector_state = drm_atomic_get_connector_state(state, &connector->base);
12721                         if (IS_ERR(connector_state)) {
12722                                 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12723                                               connector->base.base.id,
12724                                               connector->base.name,
12725                                               PTR_ERR(connector_state));
12726                                 continue;
12727                         }
12728
12729                         connector_state->crtc = crtc;
12730                         connector_state->best_encoder = &encoder->base;
12731                 }
12732         }
12733
12734         crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12735         if (IS_ERR(crtc_state)) {
12736                 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12737                               crtc->base.id, PTR_ERR(crtc_state));
12738                 drm_atomic_state_free(state);
12739                 return;
12740         }
12741
12742         crtc_state->base.active = crtc_state->base.enable =
12743                 to_intel_crtc(crtc)->new_enabled;
12744
12745         drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12746
12747         intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12748                                         crtc->primary->fb, crtc->x, crtc->y);
12749
12750         ret = intel_set_mode(crtc, state, false);
12751         if (ret)
12752                 drm_atomic_state_free(state);
12753 }
12754
12755 #undef for_each_intel_crtc_masked
12756
12757 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12758                                         struct drm_mode_set *set)
12759 {
12760         int ro;
12761
12762         for (ro = 0; ro < set->num_connectors; ro++)
12763                 if (set->connectors[ro] == &connector->base)
12764                         return true;
12765
12766         return false;
12767 }
12768
12769 static int
12770 intel_modeset_stage_output_state(struct drm_device *dev,
12771                                  struct drm_mode_set *set,
12772                                  struct drm_atomic_state *state)
12773 {
12774         struct intel_connector *connector;
12775         struct drm_connector *drm_connector;
12776         struct drm_connector_state *connector_state;
12777         struct drm_crtc *crtc;
12778         struct drm_crtc_state *crtc_state;
12779         int i, ret;
12780
12781         /* The upper layers ensure that we either disable a crtc or have a list
12782          * of connectors. For paranoia, double-check this. */
12783         WARN_ON(!set->fb && (set->num_connectors != 0));
12784         WARN_ON(set->fb && (set->num_connectors == 0));
12785
12786         for_each_intel_connector(dev, connector) {
12787                 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12788
12789                 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12790                         continue;
12791
12792                 connector_state =
12793                         drm_atomic_get_connector_state(state, &connector->base);
12794                 if (IS_ERR(connector_state))
12795                         return PTR_ERR(connector_state);
12796
12797                 if (in_mode_set) {
12798                         int pipe = to_intel_crtc(set->crtc)->pipe;
12799                         connector_state->best_encoder =
12800                                 &intel_find_encoder(connector, pipe)->base;
12801                 }
12802
12803                 if (connector->base.state->crtc != set->crtc)
12804                         continue;
12805
12806                 /* If we disable the crtc, disable all its connectors. Also, if
12807                  * the connector is on the changing crtc but not on the new
12808                  * connector list, disable it. */
12809                 if (!set->fb || !in_mode_set) {
12810                         connector_state->best_encoder = NULL;
12811
12812                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12813                                 connector->base.base.id,
12814                                 connector->base.name);
12815                 }
12816         }
12817         /* connector->new_encoder is now updated for all connectors. */
12818
12819         for_each_connector_in_state(state, drm_connector, connector_state, i) {
12820                 connector = to_intel_connector(drm_connector);
12821
12822                 if (!connector_state->best_encoder) {
12823                         ret = drm_atomic_set_crtc_for_connector(connector_state,
12824                                                                 NULL);
12825                         if (ret)
12826                                 return ret;
12827
12828                         continue;
12829                 }
12830
12831                 if (intel_connector_in_mode_set(connector, set)) {
12832                         struct drm_crtc *crtc = connector->base.state->crtc;
12833
12834                         /* If this connector was in a previous crtc, add it
12835                          * to the state. We might need to disable it. */
12836                         if (crtc) {
12837                                 crtc_state =
12838                                         drm_atomic_get_crtc_state(state, crtc);
12839                                 if (IS_ERR(crtc_state))
12840                                         return PTR_ERR(crtc_state);
12841                         }
12842
12843                         ret = drm_atomic_set_crtc_for_connector(connector_state,
12844                                                                 set->crtc);
12845                         if (ret)
12846                                 return ret;
12847                 }
12848
12849                 /* Make sure the new CRTC will work with the encoder */
12850                 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12851                                          connector_state->crtc)) {
12852                         return -EINVAL;
12853                 }
12854
12855                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12856                         connector->base.base.id,
12857                         connector->base.name,
12858                         connector_state->crtc->base.id);
12859
12860                 if (connector_state->best_encoder != &connector->encoder->base)
12861                         connector->encoder =
12862                                 to_intel_encoder(connector_state->best_encoder);
12863         }
12864
12865         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12866                 bool has_connectors;
12867
12868                 ret = drm_atomic_add_affected_connectors(state, crtc);
12869                 if (ret)
12870                         return ret;
12871
12872                 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12873                 if (has_connectors != crtc_state->enable)
12874                         crtc_state->enable =
12875                         crtc_state->active = has_connectors;
12876         }
12877
12878         ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12879                                               set->fb, set->x, set->y);
12880         if (ret)
12881                 return ret;
12882
12883         crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12884         if (IS_ERR(crtc_state))
12885                 return PTR_ERR(crtc_state);
12886
12887         if (set->mode)
12888                 drm_mode_copy(&crtc_state->mode, set->mode);
12889
12890         if (set->num_connectors)
12891                 crtc_state->active = true;
12892
12893         return 0;
12894 }
12895
12896 static bool primary_plane_visible(struct drm_crtc *crtc)
12897 {
12898         struct intel_plane_state *plane_state =
12899                 to_intel_plane_state(crtc->primary->state);
12900
12901         return plane_state->visible;
12902 }
12903
12904 static int intel_crtc_set_config(struct drm_mode_set *set)
12905 {
12906         struct drm_device *dev;
12907         struct drm_atomic_state *state = NULL;
12908         struct intel_crtc_state *pipe_config;
12909         bool primary_plane_was_visible;
12910         int ret;
12911
12912         BUG_ON(!set);
12913         BUG_ON(!set->crtc);
12914         BUG_ON(!set->crtc->helper_private);
12915
12916         /* Enforce sane interface api - has been abused by the fb helper. */
12917         BUG_ON(!set->mode && set->fb);
12918         BUG_ON(set->fb && set->num_connectors == 0);
12919
12920         if (set->fb) {
12921                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12922                                 set->crtc->base.id, set->fb->base.id,
12923                                 (int)set->num_connectors, set->x, set->y);
12924         } else {
12925                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12926         }
12927
12928         dev = set->crtc->dev;
12929
12930         state = drm_atomic_state_alloc(dev);
12931         if (!state)
12932                 return -ENOMEM;
12933
12934         state->acquire_ctx = dev->mode_config.acquire_ctx;
12935
12936         ret = intel_modeset_stage_output_state(dev, set, state);
12937         if (ret)
12938                 goto out;
12939
12940         pipe_config = intel_modeset_compute_config(set->crtc, state);
12941         if (IS_ERR(pipe_config)) {
12942                 ret = PTR_ERR(pipe_config);
12943                 goto out;
12944         }
12945
12946         intel_update_pipe_size(to_intel_crtc(set->crtc));
12947
12948         primary_plane_was_visible = primary_plane_visible(set->crtc);
12949
12950         ret = intel_set_mode_with_config(set->crtc, pipe_config, true);
12951
12952         if (ret == 0 &&
12953             pipe_config->base.enable &&
12954             pipe_config->base.planes_changed &&
12955             !needs_modeset(&pipe_config->base)) {
12956                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12957
12958                 /*
12959                  * We need to make sure the primary plane is re-enabled if it
12960                  * has previously been turned off.
12961                  */
12962                 if (ret == 0 && !primary_plane_was_visible &&
12963                     primary_plane_visible(set->crtc)) {
12964                         WARN_ON(!intel_crtc->active);
12965                         intel_post_enable_primary(set->crtc);
12966                 }
12967
12968                 /*
12969                  * In the fastboot case this may be our only check of the
12970                  * state after boot.  It would be better to only do it on
12971                  * the first update, but we don't have a nice way of doing that
12972                  * (and really, set_config isn't used much for high freq page
12973                  * flipping, so increasing its cost here shouldn't be a big
12974                  * deal).
12975                  */
12976                 if (i915.fastboot && ret == 0)
12977                         intel_modeset_check_state(set->crtc->dev);
12978         }
12979
12980         if (ret) {
12981                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12982                               set->crtc->base.id, ret);
12983         }
12984
12985 out:
12986         if (ret)
12987                 drm_atomic_state_free(state);
12988         return ret;
12989 }
12990
12991 static const struct drm_crtc_funcs intel_crtc_funcs = {
12992         .gamma_set = intel_crtc_gamma_set,
12993         .set_config = intel_crtc_set_config,
12994         .destroy = intel_crtc_destroy,
12995         .page_flip = intel_crtc_page_flip,
12996         .atomic_duplicate_state = intel_crtc_duplicate_state,
12997         .atomic_destroy_state = intel_crtc_destroy_state,
12998 };
12999
13000 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13001                                       struct intel_shared_dpll *pll,
13002                                       struct intel_dpll_hw_state *hw_state)
13003 {
13004         uint32_t val;
13005
13006         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13007                 return false;
13008
13009         val = I915_READ(PCH_DPLL(pll->id));
13010         hw_state->dpll = val;
13011         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13012         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13013
13014         return val & DPLL_VCO_ENABLE;
13015 }
13016
13017 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13018                                   struct intel_shared_dpll *pll)
13019 {
13020         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13021         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13022 }
13023
13024 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13025                                 struct intel_shared_dpll *pll)
13026 {
13027         /* PCH refclock must be enabled first */
13028         ibx_assert_pch_refclk_enabled(dev_priv);
13029
13030         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13031
13032         /* Wait for the clocks to stabilize. */
13033         POSTING_READ(PCH_DPLL(pll->id));
13034         udelay(150);
13035
13036         /* The pixel multiplier can only be updated once the
13037          * DPLL is enabled and the clocks are stable.
13038          *
13039          * So write it again.
13040          */
13041         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13042         POSTING_READ(PCH_DPLL(pll->id));
13043         udelay(200);
13044 }
13045
13046 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13047                                  struct intel_shared_dpll *pll)
13048 {
13049         struct drm_device *dev = dev_priv->dev;
13050         struct intel_crtc *crtc;
13051
13052         /* Make sure no transcoder isn't still depending on us. */
13053         for_each_intel_crtc(dev, crtc) {
13054                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13055                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13056         }
13057
13058         I915_WRITE(PCH_DPLL(pll->id), 0);
13059         POSTING_READ(PCH_DPLL(pll->id));
13060         udelay(200);
13061 }
13062
13063 static char *ibx_pch_dpll_names[] = {
13064         "PCH DPLL A",
13065         "PCH DPLL B",
13066 };
13067
13068 static void ibx_pch_dpll_init(struct drm_device *dev)
13069 {
13070         struct drm_i915_private *dev_priv = dev->dev_private;
13071         int i;
13072
13073         dev_priv->num_shared_dpll = 2;
13074
13075         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13076                 dev_priv->shared_dplls[i].id = i;
13077                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13078                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13079                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13080                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13081                 dev_priv->shared_dplls[i].get_hw_state =
13082                         ibx_pch_dpll_get_hw_state;
13083         }
13084 }
13085
13086 static void intel_shared_dpll_init(struct drm_device *dev)
13087 {
13088         struct drm_i915_private *dev_priv = dev->dev_private;
13089
13090         if (HAS_DDI(dev))
13091                 intel_ddi_pll_init(dev);
13092         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13093                 ibx_pch_dpll_init(dev);
13094         else
13095                 dev_priv->num_shared_dpll = 0;
13096
13097         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13098 }
13099
13100 /**
13101  * intel_wm_need_update - Check whether watermarks need updating
13102  * @plane: drm plane
13103  * @state: new plane state
13104  *
13105  * Check current plane state versus the new one to determine whether
13106  * watermarks need to be recalculated.
13107  *
13108  * Returns true or false.
13109  */
13110 bool intel_wm_need_update(struct drm_plane *plane,
13111                           struct drm_plane_state *state)
13112 {
13113         /* Update watermarks on tiling changes. */
13114         if (!plane->state->fb || !state->fb ||
13115             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13116             plane->state->rotation != state->rotation)
13117                 return true;
13118
13119         return false;
13120 }
13121
13122 /**
13123  * intel_prepare_plane_fb - Prepare fb for usage on plane
13124  * @plane: drm plane to prepare for
13125  * @fb: framebuffer to prepare for presentation
13126  *
13127  * Prepares a framebuffer for usage on a display plane.  Generally this
13128  * involves pinning the underlying object and updating the frontbuffer tracking
13129  * bits.  Some older platforms need special physical address handling for
13130  * cursor planes.
13131  *
13132  * Returns 0 on success, negative error code on failure.
13133  */
13134 int
13135 intel_prepare_plane_fb(struct drm_plane *plane,
13136                        struct drm_framebuffer *fb,
13137                        const struct drm_plane_state *new_state)
13138 {
13139         struct drm_device *dev = plane->dev;
13140         struct intel_plane *intel_plane = to_intel_plane(plane);
13141         enum pipe pipe = intel_plane->pipe;
13142         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13143         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13144         unsigned frontbuffer_bits = 0;
13145         int ret = 0;
13146
13147         if (!obj)
13148                 return 0;
13149
13150         switch (plane->type) {
13151         case DRM_PLANE_TYPE_PRIMARY:
13152                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13153                 break;
13154         case DRM_PLANE_TYPE_CURSOR:
13155                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13156                 break;
13157         case DRM_PLANE_TYPE_OVERLAY:
13158                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13159                 break;
13160         }
13161
13162         mutex_lock(&dev->struct_mutex);
13163
13164         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13165             INTEL_INFO(dev)->cursor_needs_physical) {
13166                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13167                 ret = i915_gem_object_attach_phys(obj, align);
13168                 if (ret)
13169                         DRM_DEBUG_KMS("failed to attach phys object\n");
13170         } else {
13171                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13172         }
13173
13174         if (ret == 0)
13175                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13176
13177         mutex_unlock(&dev->struct_mutex);
13178
13179         return ret;
13180 }
13181
13182 /**
13183  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13184  * @plane: drm plane to clean up for
13185  * @fb: old framebuffer that was on plane
13186  *
13187  * Cleans up a framebuffer that has just been removed from a plane.
13188  */
13189 void
13190 intel_cleanup_plane_fb(struct drm_plane *plane,
13191                        struct drm_framebuffer *fb,
13192                        const struct drm_plane_state *old_state)
13193 {
13194         struct drm_device *dev = plane->dev;
13195         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13196
13197         if (WARN_ON(!obj))
13198                 return;
13199
13200         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13201             !INTEL_INFO(dev)->cursor_needs_physical) {
13202                 mutex_lock(&dev->struct_mutex);
13203                 intel_unpin_fb_obj(fb, old_state);
13204                 mutex_unlock(&dev->struct_mutex);
13205         }
13206 }
13207
13208 int
13209 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13210 {
13211         int max_scale;
13212         struct drm_device *dev;
13213         struct drm_i915_private *dev_priv;
13214         int crtc_clock, cdclk;
13215
13216         if (!intel_crtc || !crtc_state)
13217                 return DRM_PLANE_HELPER_NO_SCALING;
13218
13219         dev = intel_crtc->base.dev;
13220         dev_priv = dev->dev_private;
13221         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13222         cdclk = dev_priv->display.get_display_clock_speed(dev);
13223
13224         if (!crtc_clock || !cdclk)
13225                 return DRM_PLANE_HELPER_NO_SCALING;
13226
13227         /*
13228          * skl max scale is lower of:
13229          *    close to 3 but not 3, -1 is for that purpose
13230          *            or
13231          *    cdclk/crtc_clock
13232          */
13233         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13234
13235         return max_scale;
13236 }
13237
13238 static int
13239 intel_check_primary_plane(struct drm_plane *plane,
13240                           struct intel_plane_state *state)
13241 {
13242         struct drm_device *dev = plane->dev;
13243         struct drm_i915_private *dev_priv = dev->dev_private;
13244         struct drm_crtc *crtc = state->base.crtc;
13245         struct intel_crtc *intel_crtc;
13246         struct intel_crtc_state *crtc_state;
13247         struct drm_framebuffer *fb = state->base.fb;
13248         struct drm_rect *dest = &state->dst;
13249         struct drm_rect *src = &state->src;
13250         const struct drm_rect *clip = &state->clip;
13251         bool can_position = false;
13252         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13253         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13254         int ret;
13255
13256         crtc = crtc ? crtc : plane->crtc;
13257         intel_crtc = to_intel_crtc(crtc);
13258         crtc_state = state->base.state ?
13259                 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13260
13261         if (INTEL_INFO(dev)->gen >= 9) {
13262                 /* use scaler when colorkey is not required */
13263                 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13264                         min_scale = 1;
13265                         max_scale = skl_max_scale(intel_crtc, crtc_state);
13266                 }
13267                 can_position = true;
13268         }
13269
13270         ret = drm_plane_helper_check_update(plane, crtc, fb,
13271                                             src, dest, clip,
13272                                             min_scale,
13273                                             max_scale,
13274                                             can_position, true,
13275                                             &state->visible);
13276         if (ret)
13277                 return ret;
13278
13279         if (intel_crtc->active) {
13280                 struct intel_plane_state *old_state =
13281                         to_intel_plane_state(plane->state);
13282
13283                 intel_crtc->atomic.wait_for_flips = true;
13284
13285                 /*
13286                  * FBC does not work on some platforms for rotated
13287                  * planes, so disable it when rotation is not 0 and
13288                  * update it when rotation is set back to 0.
13289                  *
13290                  * FIXME: This is redundant with the fbc update done in
13291                  * the primary plane enable function except that that
13292                  * one is done too late. We eventually need to unify
13293                  * this.
13294                  */
13295                 if (state->visible &&
13296                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13297                     dev_priv->fbc.crtc == intel_crtc &&
13298                     state->base.rotation != BIT(DRM_ROTATE_0)) {
13299                         intel_crtc->atomic.disable_fbc = true;
13300                 }
13301
13302                 if (state->visible && !old_state->visible) {
13303                         /*
13304                          * BDW signals flip done immediately if the plane
13305                          * is disabled, even if the plane enable is already
13306                          * armed to occur at the next vblank :(
13307                          */
13308                         if (IS_BROADWELL(dev))
13309                                 intel_crtc->atomic.wait_vblank = true;
13310                 }
13311
13312                 /*
13313                  * FIXME: Actually if we will still have any other plane enabled
13314                  * on the pipe we could let IPS enabled still, but for
13315                  * now lets consider that when we make primary invisible
13316                  * by setting DSPCNTR to 0 on update_primary_plane function
13317                  * IPS needs to be disable.
13318                  */
13319                 if (!state->visible || !fb)
13320                         intel_crtc->atomic.disable_ips = true;
13321
13322                 intel_crtc->atomic.fb_bits |=
13323                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13324
13325                 intel_crtc->atomic.update_fbc = true;
13326
13327                 if (intel_wm_need_update(plane, &state->base))
13328                         intel_crtc->atomic.update_wm = true;
13329         }
13330
13331         if (INTEL_INFO(dev)->gen >= 9) {
13332                 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13333                         to_intel_plane(plane), state, 0);
13334                 if (ret)
13335                         return ret;
13336         }
13337
13338         return 0;
13339 }
13340
13341 static void
13342 intel_commit_primary_plane(struct drm_plane *plane,
13343                            struct intel_plane_state *state)
13344 {
13345         struct drm_crtc *crtc = state->base.crtc;
13346         struct drm_framebuffer *fb = state->base.fb;
13347         struct drm_device *dev = plane->dev;
13348         struct drm_i915_private *dev_priv = dev->dev_private;
13349         struct intel_crtc *intel_crtc;
13350         struct drm_rect *src = &state->src;
13351
13352         crtc = crtc ? crtc : plane->crtc;
13353         intel_crtc = to_intel_crtc(crtc);
13354
13355         plane->fb = fb;
13356         crtc->x = src->x1 >> 16;
13357         crtc->y = src->y1 >> 16;
13358
13359         if (intel_crtc->active) {
13360                 if (state->visible)
13361                         /* FIXME: kill this fastboot hack */
13362                         intel_update_pipe_size(intel_crtc);
13363
13364                 dev_priv->display.update_primary_plane(crtc, plane->fb,
13365                                                        crtc->x, crtc->y);
13366         }
13367 }
13368
13369 static void
13370 intel_disable_primary_plane(struct drm_plane *plane,
13371                             struct drm_crtc *crtc,
13372                             bool force)
13373 {
13374         struct drm_device *dev = plane->dev;
13375         struct drm_i915_private *dev_priv = dev->dev_private;
13376
13377         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13378 }
13379
13380 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13381 {
13382         struct drm_device *dev = crtc->dev;
13383         struct drm_i915_private *dev_priv = dev->dev_private;
13384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13385         struct intel_plane *intel_plane;
13386         struct drm_plane *p;
13387         unsigned fb_bits = 0;
13388
13389         /* Track fb's for any planes being disabled */
13390         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13391                 intel_plane = to_intel_plane(p);
13392
13393                 if (intel_crtc->atomic.disabled_planes &
13394                     (1 << drm_plane_index(p))) {
13395                         switch (p->type) {
13396                         case DRM_PLANE_TYPE_PRIMARY:
13397                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13398                                 break;
13399                         case DRM_PLANE_TYPE_CURSOR:
13400                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13401                                 break;
13402                         case DRM_PLANE_TYPE_OVERLAY:
13403                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13404                                 break;
13405                         }
13406
13407                         mutex_lock(&dev->struct_mutex);
13408                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13409                         mutex_unlock(&dev->struct_mutex);
13410                 }
13411         }
13412
13413         if (intel_crtc->atomic.wait_for_flips)
13414                 intel_crtc_wait_for_pending_flips(crtc);
13415
13416         if (intel_crtc->atomic.disable_fbc)
13417                 intel_fbc_disable(dev);
13418
13419         if (intel_crtc->atomic.disable_ips)
13420                 hsw_disable_ips(intel_crtc);
13421
13422         if (intel_crtc->atomic.pre_disable_primary)
13423                 intel_pre_disable_primary(crtc);
13424
13425         if (intel_crtc->atomic.update_wm)
13426                 intel_update_watermarks(crtc);
13427
13428         intel_runtime_pm_get(dev_priv);
13429
13430         /* Perform vblank evasion around commit operation */
13431         if (intel_crtc->active)
13432                 intel_crtc->atomic.evade =
13433                         intel_pipe_update_start(intel_crtc,
13434                                                 &intel_crtc->atomic.start_vbl_count);
13435 }
13436
13437 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13438 {
13439         struct drm_device *dev = crtc->dev;
13440         struct drm_i915_private *dev_priv = dev->dev_private;
13441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13442         struct drm_plane *p;
13443
13444         if (intel_crtc->atomic.evade)
13445                 intel_pipe_update_end(intel_crtc,
13446                                       intel_crtc->atomic.start_vbl_count);
13447
13448         intel_runtime_pm_put(dev_priv);
13449
13450         if (intel_crtc->atomic.wait_vblank)
13451                 intel_wait_for_vblank(dev, intel_crtc->pipe);
13452
13453         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13454
13455         if (intel_crtc->atomic.update_fbc) {
13456                 mutex_lock(&dev->struct_mutex);
13457                 intel_fbc_update(dev);
13458                 mutex_unlock(&dev->struct_mutex);
13459         }
13460
13461         if (intel_crtc->atomic.post_enable_primary)
13462                 intel_post_enable_primary(crtc);
13463
13464         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13465                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13466                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13467                                                        false, false);
13468
13469         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13470 }
13471
13472 /**
13473  * intel_plane_destroy - destroy a plane
13474  * @plane: plane to destroy
13475  *
13476  * Common destruction function for all types of planes (primary, cursor,
13477  * sprite).
13478  */
13479 void intel_plane_destroy(struct drm_plane *plane)
13480 {
13481         struct intel_plane *intel_plane = to_intel_plane(plane);
13482         drm_plane_cleanup(plane);
13483         kfree(intel_plane);
13484 }
13485
13486 const struct drm_plane_funcs intel_plane_funcs = {
13487         .update_plane = drm_atomic_helper_update_plane,
13488         .disable_plane = drm_atomic_helper_disable_plane,
13489         .destroy = intel_plane_destroy,
13490         .set_property = drm_atomic_helper_plane_set_property,
13491         .atomic_get_property = intel_plane_atomic_get_property,
13492         .atomic_set_property = intel_plane_atomic_set_property,
13493         .atomic_duplicate_state = intel_plane_duplicate_state,
13494         .atomic_destroy_state = intel_plane_destroy_state,
13495
13496 };
13497
13498 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13499                                                     int pipe)
13500 {
13501         struct intel_plane *primary;
13502         struct intel_plane_state *state;
13503         const uint32_t *intel_primary_formats;
13504         int num_formats;
13505
13506         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13507         if (primary == NULL)
13508                 return NULL;
13509
13510         state = intel_create_plane_state(&primary->base);
13511         if (!state) {
13512                 kfree(primary);
13513                 return NULL;
13514         }
13515         primary->base.state = &state->base;
13516
13517         primary->can_scale = false;
13518         primary->max_downscale = 1;
13519         if (INTEL_INFO(dev)->gen >= 9) {
13520                 primary->can_scale = true;
13521                 state->scaler_id = -1;
13522         }
13523         primary->pipe = pipe;
13524         primary->plane = pipe;
13525         primary->check_plane = intel_check_primary_plane;
13526         primary->commit_plane = intel_commit_primary_plane;
13527         primary->disable_plane = intel_disable_primary_plane;
13528         primary->ckey.flags = I915_SET_COLORKEY_NONE;
13529         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13530                 primary->plane = !pipe;
13531
13532         if (INTEL_INFO(dev)->gen >= 9) {
13533                 intel_primary_formats = skl_primary_formats;
13534                 num_formats = ARRAY_SIZE(skl_primary_formats);
13535         } else if (INTEL_INFO(dev)->gen >= 4) {
13536                 intel_primary_formats = i965_primary_formats;
13537                 num_formats = ARRAY_SIZE(i965_primary_formats);
13538         } else {
13539                 intel_primary_formats = i8xx_primary_formats;
13540                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13541         }
13542
13543         drm_universal_plane_init(dev, &primary->base, 0,
13544                                  &intel_plane_funcs,
13545                                  intel_primary_formats, num_formats,
13546                                  DRM_PLANE_TYPE_PRIMARY);
13547
13548         if (INTEL_INFO(dev)->gen >= 4)
13549                 intel_create_rotation_property(dev, primary);
13550
13551         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13552
13553         return &primary->base;
13554 }
13555
13556 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13557 {
13558         if (!dev->mode_config.rotation_property) {
13559                 unsigned long flags = BIT(DRM_ROTATE_0) |
13560                         BIT(DRM_ROTATE_180);
13561
13562                 if (INTEL_INFO(dev)->gen >= 9)
13563                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13564
13565                 dev->mode_config.rotation_property =
13566                         drm_mode_create_rotation_property(dev, flags);
13567         }
13568         if (dev->mode_config.rotation_property)
13569                 drm_object_attach_property(&plane->base.base,
13570                                 dev->mode_config.rotation_property,
13571                                 plane->base.state->rotation);
13572 }
13573
13574 static int
13575 intel_check_cursor_plane(struct drm_plane *plane,
13576                          struct intel_plane_state *state)
13577 {
13578         struct drm_crtc *crtc = state->base.crtc;
13579         struct drm_device *dev = plane->dev;
13580         struct drm_framebuffer *fb = state->base.fb;
13581         struct drm_rect *dest = &state->dst;
13582         struct drm_rect *src = &state->src;
13583         const struct drm_rect *clip = &state->clip;
13584         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13585         struct intel_crtc *intel_crtc;
13586         unsigned stride;
13587         int ret;
13588
13589         crtc = crtc ? crtc : plane->crtc;
13590         intel_crtc = to_intel_crtc(crtc);
13591
13592         ret = drm_plane_helper_check_update(plane, crtc, fb,
13593                                             src, dest, clip,
13594                                             DRM_PLANE_HELPER_NO_SCALING,
13595                                             DRM_PLANE_HELPER_NO_SCALING,
13596                                             true, true, &state->visible);
13597         if (ret)
13598                 return ret;
13599
13600
13601         /* if we want to turn off the cursor ignore width and height */
13602         if (!obj)
13603                 goto finish;
13604
13605         /* Check for which cursor types we support */
13606         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13607                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13608                           state->base.crtc_w, state->base.crtc_h);
13609                 return -EINVAL;
13610         }
13611
13612         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13613         if (obj->base.size < stride * state->base.crtc_h) {
13614                 DRM_DEBUG_KMS("buffer is too small\n");
13615                 return -ENOMEM;
13616         }
13617
13618         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13619                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13620                 ret = -EINVAL;
13621         }
13622
13623 finish:
13624         if (intel_crtc->active) {
13625                 if (plane->state->crtc_w != state->base.crtc_w)
13626                         intel_crtc->atomic.update_wm = true;
13627
13628                 intel_crtc->atomic.fb_bits |=
13629                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13630         }
13631
13632         return ret;
13633 }
13634
13635 static void
13636 intel_disable_cursor_plane(struct drm_plane *plane,
13637                            struct drm_crtc *crtc,
13638                            bool force)
13639 {
13640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13641
13642         if (!force) {
13643                 plane->fb = NULL;
13644                 intel_crtc->cursor_bo = NULL;
13645                 intel_crtc->cursor_addr = 0;
13646         }
13647
13648         intel_crtc_update_cursor(crtc, false);
13649 }
13650
13651 static void
13652 intel_commit_cursor_plane(struct drm_plane *plane,
13653                           struct intel_plane_state *state)
13654 {
13655         struct drm_crtc *crtc = state->base.crtc;
13656         struct drm_device *dev = plane->dev;
13657         struct intel_crtc *intel_crtc;
13658         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13659         uint32_t addr;
13660
13661         crtc = crtc ? crtc : plane->crtc;
13662         intel_crtc = to_intel_crtc(crtc);
13663
13664         plane->fb = state->base.fb;
13665         crtc->cursor_x = state->base.crtc_x;
13666         crtc->cursor_y = state->base.crtc_y;
13667
13668         if (intel_crtc->cursor_bo == obj)
13669                 goto update;
13670
13671         if (!obj)
13672                 addr = 0;
13673         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13674                 addr = i915_gem_obj_ggtt_offset(obj);
13675         else
13676                 addr = obj->phys_handle->busaddr;
13677
13678         intel_crtc->cursor_addr = addr;
13679         intel_crtc->cursor_bo = obj;
13680 update:
13681
13682         if (intel_crtc->active)
13683                 intel_crtc_update_cursor(crtc, state->visible);
13684 }
13685
13686 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13687                                                    int pipe)
13688 {
13689         struct intel_plane *cursor;
13690         struct intel_plane_state *state;
13691
13692         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13693         if (cursor == NULL)
13694                 return NULL;
13695
13696         state = intel_create_plane_state(&cursor->base);
13697         if (!state) {
13698                 kfree(cursor);
13699                 return NULL;
13700         }
13701         cursor->base.state = &state->base;
13702
13703         cursor->can_scale = false;
13704         cursor->max_downscale = 1;
13705         cursor->pipe = pipe;
13706         cursor->plane = pipe;
13707         cursor->check_plane = intel_check_cursor_plane;
13708         cursor->commit_plane = intel_commit_cursor_plane;
13709         cursor->disable_plane = intel_disable_cursor_plane;
13710
13711         drm_universal_plane_init(dev, &cursor->base, 0,
13712                                  &intel_plane_funcs,
13713                                  intel_cursor_formats,
13714                                  ARRAY_SIZE(intel_cursor_formats),
13715                                  DRM_PLANE_TYPE_CURSOR);
13716
13717         if (INTEL_INFO(dev)->gen >= 4) {
13718                 if (!dev->mode_config.rotation_property)
13719                         dev->mode_config.rotation_property =
13720                                 drm_mode_create_rotation_property(dev,
13721                                                         BIT(DRM_ROTATE_0) |
13722                                                         BIT(DRM_ROTATE_180));
13723                 if (dev->mode_config.rotation_property)
13724                         drm_object_attach_property(&cursor->base.base,
13725                                 dev->mode_config.rotation_property,
13726                                 state->base.rotation);
13727         }
13728
13729         if (INTEL_INFO(dev)->gen >=9)
13730                 state->scaler_id = -1;
13731
13732         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13733
13734         return &cursor->base;
13735 }
13736
13737 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13738         struct intel_crtc_state *crtc_state)
13739 {
13740         int i;
13741         struct intel_scaler *intel_scaler;
13742         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13743
13744         for (i = 0; i < intel_crtc->num_scalers; i++) {
13745                 intel_scaler = &scaler_state->scalers[i];
13746                 intel_scaler->in_use = 0;
13747                 intel_scaler->id = i;
13748
13749                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13750         }
13751
13752         scaler_state->scaler_id = -1;
13753 }
13754
13755 static void intel_crtc_init(struct drm_device *dev, int pipe)
13756 {
13757         struct drm_i915_private *dev_priv = dev->dev_private;
13758         struct intel_crtc *intel_crtc;
13759         struct intel_crtc_state *crtc_state = NULL;
13760         struct drm_plane *primary = NULL;
13761         struct drm_plane *cursor = NULL;
13762         int i, ret;
13763
13764         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13765         if (intel_crtc == NULL)
13766                 return;
13767
13768         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13769         if (!crtc_state)
13770                 goto fail;
13771         intel_crtc->config = crtc_state;
13772         intel_crtc->base.state = &crtc_state->base;
13773         crtc_state->base.crtc = &intel_crtc->base;
13774
13775         /* initialize shared scalers */
13776         if (INTEL_INFO(dev)->gen >= 9) {
13777                 if (pipe == PIPE_C)
13778                         intel_crtc->num_scalers = 1;
13779                 else
13780                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13781
13782                 skl_init_scalers(dev, intel_crtc, crtc_state);
13783         }
13784
13785         primary = intel_primary_plane_create(dev, pipe);
13786         if (!primary)
13787                 goto fail;
13788
13789         cursor = intel_cursor_plane_create(dev, pipe);
13790         if (!cursor)
13791                 goto fail;
13792
13793         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13794                                         cursor, &intel_crtc_funcs);
13795         if (ret)
13796                 goto fail;
13797
13798         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13799         for (i = 0; i < 256; i++) {
13800                 intel_crtc->lut_r[i] = i;
13801                 intel_crtc->lut_g[i] = i;
13802                 intel_crtc->lut_b[i] = i;
13803         }
13804
13805         /*
13806          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13807          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13808          */
13809         intel_crtc->pipe = pipe;
13810         intel_crtc->plane = pipe;
13811         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13812                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13813                 intel_crtc->plane = !pipe;
13814         }
13815
13816         intel_crtc->cursor_base = ~0;
13817         intel_crtc->cursor_cntl = ~0;
13818         intel_crtc->cursor_size = ~0;
13819
13820         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13821                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13822         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13823         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13824
13825         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13826
13827         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13828         return;
13829
13830 fail:
13831         if (primary)
13832                 drm_plane_cleanup(primary);
13833         if (cursor)
13834                 drm_plane_cleanup(cursor);
13835         kfree(crtc_state);
13836         kfree(intel_crtc);
13837 }
13838
13839 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13840 {
13841         struct drm_encoder *encoder = connector->base.encoder;
13842         struct drm_device *dev = connector->base.dev;
13843
13844         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13845
13846         if (!encoder || WARN_ON(!encoder->crtc))
13847                 return INVALID_PIPE;
13848
13849         return to_intel_crtc(encoder->crtc)->pipe;
13850 }
13851
13852 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13853                                 struct drm_file *file)
13854 {
13855         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13856         struct drm_crtc *drmmode_crtc;
13857         struct intel_crtc *crtc;
13858
13859         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13860
13861         if (!drmmode_crtc) {
13862                 DRM_ERROR("no such CRTC id\n");
13863                 return -ENOENT;
13864         }
13865
13866         crtc = to_intel_crtc(drmmode_crtc);
13867         pipe_from_crtc_id->pipe = crtc->pipe;
13868
13869         return 0;
13870 }
13871
13872 static int intel_encoder_clones(struct intel_encoder *encoder)
13873 {
13874         struct drm_device *dev = encoder->base.dev;
13875         struct intel_encoder *source_encoder;
13876         int index_mask = 0;
13877         int entry = 0;
13878
13879         for_each_intel_encoder(dev, source_encoder) {
13880                 if (encoders_cloneable(encoder, source_encoder))
13881                         index_mask |= (1 << entry);
13882
13883                 entry++;
13884         }
13885
13886         return index_mask;
13887 }
13888
13889 static bool has_edp_a(struct drm_device *dev)
13890 {
13891         struct drm_i915_private *dev_priv = dev->dev_private;
13892
13893         if (!IS_MOBILE(dev))
13894                 return false;
13895
13896         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13897                 return false;
13898
13899         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13900                 return false;
13901
13902         return true;
13903 }
13904
13905 static bool intel_crt_present(struct drm_device *dev)
13906 {
13907         struct drm_i915_private *dev_priv = dev->dev_private;
13908
13909         if (INTEL_INFO(dev)->gen >= 9)
13910                 return false;
13911
13912         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13913                 return false;
13914
13915         if (IS_CHERRYVIEW(dev))
13916                 return false;
13917
13918         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13919                 return false;
13920
13921         return true;
13922 }
13923
13924 static void intel_setup_outputs(struct drm_device *dev)
13925 {
13926         struct drm_i915_private *dev_priv = dev->dev_private;
13927         struct intel_encoder *encoder;
13928         bool dpd_is_edp = false;
13929
13930         intel_lvds_init(dev);
13931
13932         if (intel_crt_present(dev))
13933                 intel_crt_init(dev);
13934
13935         if (IS_BROXTON(dev)) {
13936                 /*
13937                  * FIXME: Broxton doesn't support port detection via the
13938                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13939                  * detect the ports.
13940                  */
13941                 intel_ddi_init(dev, PORT_A);
13942                 intel_ddi_init(dev, PORT_B);
13943                 intel_ddi_init(dev, PORT_C);
13944         } else if (HAS_DDI(dev)) {
13945                 int found;
13946
13947                 /*
13948                  * Haswell uses DDI functions to detect digital outputs.
13949                  * On SKL pre-D0 the strap isn't connected, so we assume
13950                  * it's there.
13951                  */
13952                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13953                 /* WaIgnoreDDIAStrap: skl */
13954                 if (found ||
13955                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13956                         intel_ddi_init(dev, PORT_A);
13957
13958                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13959                  * register */
13960                 found = I915_READ(SFUSE_STRAP);
13961
13962                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13963                         intel_ddi_init(dev, PORT_B);
13964                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13965                         intel_ddi_init(dev, PORT_C);
13966                 if (found & SFUSE_STRAP_DDID_DETECTED)
13967                         intel_ddi_init(dev, PORT_D);
13968         } else if (HAS_PCH_SPLIT(dev)) {
13969                 int found;
13970                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13971
13972                 if (has_edp_a(dev))
13973                         intel_dp_init(dev, DP_A, PORT_A);
13974
13975                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13976                         /* PCH SDVOB multiplex with HDMIB */
13977                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
13978                         if (!found)
13979                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13980                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13981                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
13982                 }
13983
13984                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13985                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13986
13987                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13988                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13989
13990                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13991                         intel_dp_init(dev, PCH_DP_C, PORT_C);
13992
13993                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13994                         intel_dp_init(dev, PCH_DP_D, PORT_D);
13995         } else if (IS_VALLEYVIEW(dev)) {
13996                 /*
13997                  * The DP_DETECTED bit is the latched state of the DDC
13998                  * SDA pin at boot. However since eDP doesn't require DDC
13999                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14000                  * eDP ports may have been muxed to an alternate function.
14001                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14002                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14003                  * detect eDP ports.
14004                  */
14005                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14006                     !intel_dp_is_edp(dev, PORT_B))
14007                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14008                                         PORT_B);
14009                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14010                     intel_dp_is_edp(dev, PORT_B))
14011                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14012
14013                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14014                     !intel_dp_is_edp(dev, PORT_C))
14015                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14016                                         PORT_C);
14017                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14018                     intel_dp_is_edp(dev, PORT_C))
14019                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14020
14021                 if (IS_CHERRYVIEW(dev)) {
14022                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14023                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14024                                                 PORT_D);
14025                         /* eDP not supported on port D, so don't check VBT */
14026                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14027                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14028                 }
14029
14030                 intel_dsi_init(dev);
14031         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14032                 bool found = false;
14033
14034                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14035                         DRM_DEBUG_KMS("probing SDVOB\n");
14036                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14037                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14038                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14039                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14040                         }
14041
14042                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
14043                                 intel_dp_init(dev, DP_B, PORT_B);
14044                 }
14045
14046                 /* Before G4X SDVOC doesn't have its own detect register */
14047
14048                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14049                         DRM_DEBUG_KMS("probing SDVOC\n");
14050                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14051                 }
14052
14053                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14054
14055                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14056                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14057                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14058                         }
14059                         if (SUPPORTS_INTEGRATED_DP(dev))
14060                                 intel_dp_init(dev, DP_C, PORT_C);
14061                 }
14062
14063                 if (SUPPORTS_INTEGRATED_DP(dev) &&
14064                     (I915_READ(DP_D) & DP_DETECTED))
14065                         intel_dp_init(dev, DP_D, PORT_D);
14066         } else if (IS_GEN2(dev))
14067                 intel_dvo_init(dev);
14068
14069         if (SUPPORTS_TV(dev))
14070                 intel_tv_init(dev);
14071
14072         intel_psr_init(dev);
14073
14074         for_each_intel_encoder(dev, encoder) {
14075                 encoder->base.possible_crtcs = encoder->crtc_mask;
14076                 encoder->base.possible_clones =
14077                         intel_encoder_clones(encoder);
14078         }
14079
14080         intel_init_pch_refclk(dev);
14081
14082         drm_helper_move_panel_connectors_to_head(dev);
14083 }
14084
14085 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14086 {
14087         struct drm_device *dev = fb->dev;
14088         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14089
14090         drm_framebuffer_cleanup(fb);
14091         mutex_lock(&dev->struct_mutex);
14092         WARN_ON(!intel_fb->obj->framebuffer_references--);
14093         drm_gem_object_unreference(&intel_fb->obj->base);
14094         mutex_unlock(&dev->struct_mutex);
14095         kfree(intel_fb);
14096 }
14097
14098 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14099                                                 struct drm_file *file,
14100                                                 unsigned int *handle)
14101 {
14102         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14103         struct drm_i915_gem_object *obj = intel_fb->obj;
14104
14105         return drm_gem_handle_create(file, &obj->base, handle);
14106 }
14107
14108 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14109         .destroy = intel_user_framebuffer_destroy,
14110         .create_handle = intel_user_framebuffer_create_handle,
14111 };
14112
14113 static
14114 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14115                          uint32_t pixel_format)
14116 {
14117         u32 gen = INTEL_INFO(dev)->gen;
14118
14119         if (gen >= 9) {
14120                 /* "The stride in bytes must not exceed the of the size of 8K
14121                  *  pixels and 32K bytes."
14122                  */
14123                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14124         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14125                 return 32*1024;
14126         } else if (gen >= 4) {
14127                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14128                         return 16*1024;
14129                 else
14130                         return 32*1024;
14131         } else if (gen >= 3) {
14132                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14133                         return 8*1024;
14134                 else
14135                         return 16*1024;
14136         } else {
14137                 /* XXX DSPC is limited to 4k tiled */
14138                 return 8*1024;
14139         }
14140 }
14141
14142 static int intel_framebuffer_init(struct drm_device *dev,
14143                                   struct intel_framebuffer *intel_fb,
14144                                   struct drm_mode_fb_cmd2 *mode_cmd,
14145                                   struct drm_i915_gem_object *obj)
14146 {
14147         unsigned int aligned_height;
14148         int ret;
14149         u32 pitch_limit, stride_alignment;
14150
14151         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14152
14153         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14154                 /* Enforce that fb modifier and tiling mode match, but only for
14155                  * X-tiled. This is needed for FBC. */
14156                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14157                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14158                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14159                         return -EINVAL;
14160                 }
14161         } else {
14162                 if (obj->tiling_mode == I915_TILING_X)
14163                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14164                 else if (obj->tiling_mode == I915_TILING_Y) {
14165                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14166                         return -EINVAL;
14167                 }
14168         }
14169
14170         /* Passed in modifier sanity checking. */
14171         switch (mode_cmd->modifier[0]) {
14172         case I915_FORMAT_MOD_Y_TILED:
14173         case I915_FORMAT_MOD_Yf_TILED:
14174                 if (INTEL_INFO(dev)->gen < 9) {
14175                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14176                                   mode_cmd->modifier[0]);
14177                         return -EINVAL;
14178                 }
14179         case DRM_FORMAT_MOD_NONE:
14180         case I915_FORMAT_MOD_X_TILED:
14181                 break;
14182         default:
14183                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14184                           mode_cmd->modifier[0]);
14185                 return -EINVAL;
14186         }
14187
14188         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14189                                                      mode_cmd->pixel_format);
14190         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14191                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14192                           mode_cmd->pitches[0], stride_alignment);
14193                 return -EINVAL;
14194         }
14195
14196         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14197                                            mode_cmd->pixel_format);
14198         if (mode_cmd->pitches[0] > pitch_limit) {
14199                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14200                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14201                           "tiled" : "linear",
14202                           mode_cmd->pitches[0], pitch_limit);
14203                 return -EINVAL;
14204         }
14205
14206         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14207             mode_cmd->pitches[0] != obj->stride) {
14208                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14209                           mode_cmd->pitches[0], obj->stride);
14210                 return -EINVAL;
14211         }
14212
14213         /* Reject formats not supported by any plane early. */
14214         switch (mode_cmd->pixel_format) {
14215         case DRM_FORMAT_C8:
14216         case DRM_FORMAT_RGB565:
14217         case DRM_FORMAT_XRGB8888:
14218         case DRM_FORMAT_ARGB8888:
14219                 break;
14220         case DRM_FORMAT_XRGB1555:
14221                 if (INTEL_INFO(dev)->gen > 3) {
14222                         DRM_DEBUG("unsupported pixel format: %s\n",
14223                                   drm_get_format_name(mode_cmd->pixel_format));
14224                         return -EINVAL;
14225                 }
14226                 break;
14227         case DRM_FORMAT_ABGR8888:
14228                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14229                         DRM_DEBUG("unsupported pixel format: %s\n",
14230                                   drm_get_format_name(mode_cmd->pixel_format));
14231                         return -EINVAL;
14232                 }
14233                 break;
14234         case DRM_FORMAT_XBGR8888:
14235         case DRM_FORMAT_XRGB2101010:
14236         case DRM_FORMAT_XBGR2101010:
14237                 if (INTEL_INFO(dev)->gen < 4) {
14238                         DRM_DEBUG("unsupported pixel format: %s\n",
14239                                   drm_get_format_name(mode_cmd->pixel_format));
14240                         return -EINVAL;
14241                 }
14242                 break;
14243         case DRM_FORMAT_ABGR2101010:
14244                 if (!IS_VALLEYVIEW(dev)) {
14245                         DRM_DEBUG("unsupported pixel format: %s\n",
14246                                   drm_get_format_name(mode_cmd->pixel_format));
14247                         return -EINVAL;
14248                 }
14249                 break;
14250         case DRM_FORMAT_YUYV:
14251         case DRM_FORMAT_UYVY:
14252         case DRM_FORMAT_YVYU:
14253         case DRM_FORMAT_VYUY:
14254                 if (INTEL_INFO(dev)->gen < 5) {
14255                         DRM_DEBUG("unsupported pixel format: %s\n",
14256                                   drm_get_format_name(mode_cmd->pixel_format));
14257                         return -EINVAL;
14258                 }
14259                 break;
14260         default:
14261                 DRM_DEBUG("unsupported pixel format: %s\n",
14262                           drm_get_format_name(mode_cmd->pixel_format));
14263                 return -EINVAL;
14264         }
14265
14266         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14267         if (mode_cmd->offsets[0] != 0)
14268                 return -EINVAL;
14269
14270         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14271                                                mode_cmd->pixel_format,
14272                                                mode_cmd->modifier[0]);
14273         /* FIXME drm helper for size checks (especially planar formats)? */
14274         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14275                 return -EINVAL;
14276
14277         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14278         intel_fb->obj = obj;
14279         intel_fb->obj->framebuffer_references++;
14280
14281         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14282         if (ret) {
14283                 DRM_ERROR("framebuffer init failed %d\n", ret);
14284                 return ret;
14285         }
14286
14287         return 0;
14288 }
14289
14290 static struct drm_framebuffer *
14291 intel_user_framebuffer_create(struct drm_device *dev,
14292                               struct drm_file *filp,
14293                               struct drm_mode_fb_cmd2 *mode_cmd)
14294 {
14295         struct drm_i915_gem_object *obj;
14296
14297         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14298                                                 mode_cmd->handles[0]));
14299         if (&obj->base == NULL)
14300                 return ERR_PTR(-ENOENT);
14301
14302         return intel_framebuffer_create(dev, mode_cmd, obj);
14303 }
14304
14305 #ifndef CONFIG_DRM_I915_FBDEV
14306 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14307 {
14308 }
14309 #endif
14310
14311 static const struct drm_mode_config_funcs intel_mode_funcs = {
14312         .fb_create = intel_user_framebuffer_create,
14313         .output_poll_changed = intel_fbdev_output_poll_changed,
14314         .atomic_check = intel_atomic_check,
14315         .atomic_commit = intel_atomic_commit,
14316 };
14317
14318 /* Set up chip specific display functions */
14319 static void intel_init_display(struct drm_device *dev)
14320 {
14321         struct drm_i915_private *dev_priv = dev->dev_private;
14322
14323         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14324                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14325         else if (IS_CHERRYVIEW(dev))
14326                 dev_priv->display.find_dpll = chv_find_best_dpll;
14327         else if (IS_VALLEYVIEW(dev))
14328                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14329         else if (IS_PINEVIEW(dev))
14330                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14331         else
14332                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14333
14334         if (INTEL_INFO(dev)->gen >= 9) {
14335                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14336                 dev_priv->display.get_initial_plane_config =
14337                         skylake_get_initial_plane_config;
14338                 dev_priv->display.crtc_compute_clock =
14339                         haswell_crtc_compute_clock;
14340                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14341                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14342                 dev_priv->display.off = ironlake_crtc_off;
14343                 dev_priv->display.update_primary_plane =
14344                         skylake_update_primary_plane;
14345         } else if (HAS_DDI(dev)) {
14346                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14347                 dev_priv->display.get_initial_plane_config =
14348                         ironlake_get_initial_plane_config;
14349                 dev_priv->display.crtc_compute_clock =
14350                         haswell_crtc_compute_clock;
14351                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14352                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14353                 dev_priv->display.off = ironlake_crtc_off;
14354                 dev_priv->display.update_primary_plane =
14355                         ironlake_update_primary_plane;
14356         } else if (HAS_PCH_SPLIT(dev)) {
14357                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14358                 dev_priv->display.get_initial_plane_config =
14359                         ironlake_get_initial_plane_config;
14360                 dev_priv->display.crtc_compute_clock =
14361                         ironlake_crtc_compute_clock;
14362                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14363                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14364                 dev_priv->display.off = ironlake_crtc_off;
14365                 dev_priv->display.update_primary_plane =
14366                         ironlake_update_primary_plane;
14367         } else if (IS_VALLEYVIEW(dev)) {
14368                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14369                 dev_priv->display.get_initial_plane_config =
14370                         i9xx_get_initial_plane_config;
14371                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14372                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14373                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14374                 dev_priv->display.off = i9xx_crtc_off;
14375                 dev_priv->display.update_primary_plane =
14376                         i9xx_update_primary_plane;
14377         } else {
14378                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14379                 dev_priv->display.get_initial_plane_config =
14380                         i9xx_get_initial_plane_config;
14381                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14382                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14383                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14384                 dev_priv->display.off = i9xx_crtc_off;
14385                 dev_priv->display.update_primary_plane =
14386                         i9xx_update_primary_plane;
14387         }
14388
14389         /* Returns the core display clock speed */
14390         if (IS_SKYLAKE(dev))
14391                 dev_priv->display.get_display_clock_speed =
14392                         skylake_get_display_clock_speed;
14393         else if (IS_BROADWELL(dev))
14394                 dev_priv->display.get_display_clock_speed =
14395                         broadwell_get_display_clock_speed;
14396         else if (IS_HASWELL(dev))
14397                 dev_priv->display.get_display_clock_speed =
14398                         haswell_get_display_clock_speed;
14399         else if (IS_VALLEYVIEW(dev))
14400                 dev_priv->display.get_display_clock_speed =
14401                         valleyview_get_display_clock_speed;
14402         else if (IS_GEN5(dev))
14403                 dev_priv->display.get_display_clock_speed =
14404                         ilk_get_display_clock_speed;
14405         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14406                  IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14407                 dev_priv->display.get_display_clock_speed =
14408                         i945_get_display_clock_speed;
14409         else if (IS_I915G(dev))
14410                 dev_priv->display.get_display_clock_speed =
14411                         i915_get_display_clock_speed;
14412         else if (IS_I945GM(dev) || IS_845G(dev))
14413                 dev_priv->display.get_display_clock_speed =
14414                         i9xx_misc_get_display_clock_speed;
14415         else if (IS_PINEVIEW(dev))
14416                 dev_priv->display.get_display_clock_speed =
14417                         pnv_get_display_clock_speed;
14418         else if (IS_I915GM(dev))
14419                 dev_priv->display.get_display_clock_speed =
14420                         i915gm_get_display_clock_speed;
14421         else if (IS_I865G(dev))
14422                 dev_priv->display.get_display_clock_speed =
14423                         i865_get_display_clock_speed;
14424         else if (IS_I85X(dev))
14425                 dev_priv->display.get_display_clock_speed =
14426                         i855_get_display_clock_speed;
14427         else /* 852, 830 */
14428                 dev_priv->display.get_display_clock_speed =
14429                         i830_get_display_clock_speed;
14430
14431         if (IS_GEN5(dev)) {
14432                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14433         } else if (IS_GEN6(dev)) {
14434                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14435         } else if (IS_IVYBRIDGE(dev)) {
14436                 /* FIXME: detect B0+ stepping and use auto training */
14437                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14438         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14439                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14440         } else if (IS_VALLEYVIEW(dev)) {
14441                 dev_priv->display.modeset_global_resources =
14442                         valleyview_modeset_global_resources;
14443         } else if (IS_BROXTON(dev)) {
14444                 dev_priv->display.modeset_global_resources =
14445                         broxton_modeset_global_resources;
14446         }
14447
14448         switch (INTEL_INFO(dev)->gen) {
14449         case 2:
14450                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14451                 break;
14452
14453         case 3:
14454                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14455                 break;
14456
14457         case 4:
14458         case 5:
14459                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14460                 break;
14461
14462         case 6:
14463                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14464                 break;
14465         case 7:
14466         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14467                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14468                 break;
14469         case 9:
14470                 /* Drop through - unsupported since execlist only. */
14471         default:
14472                 /* Default just returns -ENODEV to indicate unsupported */
14473                 dev_priv->display.queue_flip = intel_default_queue_flip;
14474         }
14475
14476         intel_panel_init_backlight_funcs(dev);
14477
14478         mutex_init(&dev_priv->pps_mutex);
14479 }
14480
14481 /*
14482  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14483  * resume, or other times.  This quirk makes sure that's the case for
14484  * affected systems.
14485  */
14486 static void quirk_pipea_force(struct drm_device *dev)
14487 {
14488         struct drm_i915_private *dev_priv = dev->dev_private;
14489
14490         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14491         DRM_INFO("applying pipe a force quirk\n");
14492 }
14493
14494 static void quirk_pipeb_force(struct drm_device *dev)
14495 {
14496         struct drm_i915_private *dev_priv = dev->dev_private;
14497
14498         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14499         DRM_INFO("applying pipe b force quirk\n");
14500 }
14501
14502 /*
14503  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14504  */
14505 static void quirk_ssc_force_disable(struct drm_device *dev)
14506 {
14507         struct drm_i915_private *dev_priv = dev->dev_private;
14508         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14509         DRM_INFO("applying lvds SSC disable quirk\n");
14510 }
14511
14512 /*
14513  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14514  * brightness value
14515  */
14516 static void quirk_invert_brightness(struct drm_device *dev)
14517 {
14518         struct drm_i915_private *dev_priv = dev->dev_private;
14519         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14520         DRM_INFO("applying inverted panel brightness quirk\n");
14521 }
14522
14523 /* Some VBT's incorrectly indicate no backlight is present */
14524 static void quirk_backlight_present(struct drm_device *dev)
14525 {
14526         struct drm_i915_private *dev_priv = dev->dev_private;
14527         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14528         DRM_INFO("applying backlight present quirk\n");
14529 }
14530
14531 struct intel_quirk {
14532         int device;
14533         int subsystem_vendor;
14534         int subsystem_device;
14535         void (*hook)(struct drm_device *dev);
14536 };
14537
14538 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14539 struct intel_dmi_quirk {
14540         void (*hook)(struct drm_device *dev);
14541         const struct dmi_system_id (*dmi_id_list)[];
14542 };
14543
14544 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14545 {
14546         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14547         return 1;
14548 }
14549
14550 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14551         {
14552                 .dmi_id_list = &(const struct dmi_system_id[]) {
14553                         {
14554                                 .callback = intel_dmi_reverse_brightness,
14555                                 .ident = "NCR Corporation",
14556                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14557                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14558                                 },
14559                         },
14560                         { }  /* terminating entry */
14561                 },
14562                 .hook = quirk_invert_brightness,
14563         },
14564 };
14565
14566 static struct intel_quirk intel_quirks[] = {
14567         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14568         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14569
14570         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14571         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14572
14573         /* 830 needs to leave pipe A & dpll A up */
14574         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14575
14576         /* 830 needs to leave pipe B & dpll B up */
14577         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14578
14579         /* Lenovo U160 cannot use SSC on LVDS */
14580         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14581
14582         /* Sony Vaio Y cannot use SSC on LVDS */
14583         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14584
14585         /* Acer Aspire 5734Z must invert backlight brightness */
14586         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14587
14588         /* Acer/eMachines G725 */
14589         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14590
14591         /* Acer/eMachines e725 */
14592         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14593
14594         /* Acer/Packard Bell NCL20 */
14595         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14596
14597         /* Acer Aspire 4736Z */
14598         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14599
14600         /* Acer Aspire 5336 */
14601         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14602
14603         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14604         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14605
14606         /* Acer C720 Chromebook (Core i3 4005U) */
14607         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14608
14609         /* Apple Macbook 2,1 (Core 2 T7400) */
14610         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14611
14612         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14613         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14614
14615         /* HP Chromebook 14 (Celeron 2955U) */
14616         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14617
14618         /* Dell Chromebook 11 */
14619         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14620 };
14621
14622 static void intel_init_quirks(struct drm_device *dev)
14623 {
14624         struct pci_dev *d = dev->pdev;
14625         int i;
14626
14627         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14628                 struct intel_quirk *q = &intel_quirks[i];
14629
14630                 if (d->device == q->device &&
14631                     (d->subsystem_vendor == q->subsystem_vendor ||
14632                      q->subsystem_vendor == PCI_ANY_ID) &&
14633                     (d->subsystem_device == q->subsystem_device ||
14634                      q->subsystem_device == PCI_ANY_ID))
14635                         q->hook(dev);
14636         }
14637         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14638                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14639                         intel_dmi_quirks[i].hook(dev);
14640         }
14641 }
14642
14643 /* Disable the VGA plane that we never use */
14644 static void i915_disable_vga(struct drm_device *dev)
14645 {
14646         struct drm_i915_private *dev_priv = dev->dev_private;
14647         u8 sr1;
14648         u32 vga_reg = i915_vgacntrl_reg(dev);
14649
14650         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14651         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14652         outb(SR01, VGA_SR_INDEX);
14653         sr1 = inb(VGA_SR_DATA);
14654         outb(sr1 | 1<<5, VGA_SR_DATA);
14655         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14656         udelay(300);
14657
14658         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14659         POSTING_READ(vga_reg);
14660 }
14661
14662 void intel_modeset_init_hw(struct drm_device *dev)
14663 {
14664         intel_prepare_ddi(dev);
14665
14666         if (IS_VALLEYVIEW(dev))
14667                 vlv_update_cdclk(dev);
14668
14669         intel_init_clock_gating(dev);
14670
14671         intel_enable_gt_powersave(dev);
14672 }
14673
14674 void intel_modeset_init(struct drm_device *dev)
14675 {
14676         struct drm_i915_private *dev_priv = dev->dev_private;
14677         int sprite, ret;
14678         enum pipe pipe;
14679         struct intel_crtc *crtc;
14680
14681         drm_mode_config_init(dev);
14682
14683         dev->mode_config.min_width = 0;
14684         dev->mode_config.min_height = 0;
14685
14686         dev->mode_config.preferred_depth = 24;
14687         dev->mode_config.prefer_shadow = 1;
14688
14689         dev->mode_config.allow_fb_modifiers = true;
14690
14691         dev->mode_config.funcs = &intel_mode_funcs;
14692
14693         intel_init_quirks(dev);
14694
14695         intel_init_pm(dev);
14696
14697         if (INTEL_INFO(dev)->num_pipes == 0)
14698                 return;
14699
14700         intel_init_display(dev);
14701         intel_init_audio(dev);
14702
14703         if (IS_GEN2(dev)) {
14704                 dev->mode_config.max_width = 2048;
14705                 dev->mode_config.max_height = 2048;
14706         } else if (IS_GEN3(dev)) {
14707                 dev->mode_config.max_width = 4096;
14708                 dev->mode_config.max_height = 4096;
14709         } else {
14710                 dev->mode_config.max_width = 8192;
14711                 dev->mode_config.max_height = 8192;
14712         }
14713
14714         if (IS_845G(dev) || IS_I865G(dev)) {
14715                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14716                 dev->mode_config.cursor_height = 1023;
14717         } else if (IS_GEN2(dev)) {
14718                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14719                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14720         } else {
14721                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14722                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14723         }
14724
14725         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14726
14727         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14728                       INTEL_INFO(dev)->num_pipes,
14729                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14730
14731         for_each_pipe(dev_priv, pipe) {
14732                 intel_crtc_init(dev, pipe);
14733                 for_each_sprite(dev_priv, pipe, sprite) {
14734                         ret = intel_plane_init(dev, pipe, sprite);
14735                         if (ret)
14736                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14737                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14738                 }
14739         }
14740
14741         intel_init_dpio(dev);
14742
14743         intel_shared_dpll_init(dev);
14744
14745         /* Just disable it once at startup */
14746         i915_disable_vga(dev);
14747         intel_setup_outputs(dev);
14748
14749         /* Just in case the BIOS is doing something questionable. */
14750         intel_fbc_disable(dev);
14751
14752         drm_modeset_lock_all(dev);
14753         intel_modeset_setup_hw_state(dev, false);
14754         drm_modeset_unlock_all(dev);
14755
14756         for_each_intel_crtc(dev, crtc) {
14757                 if (!crtc->active)
14758                         continue;
14759
14760                 /*
14761                  * Note that reserving the BIOS fb up front prevents us
14762                  * from stuffing other stolen allocations like the ring
14763                  * on top.  This prevents some ugliness at boot time, and
14764                  * can even allow for smooth boot transitions if the BIOS
14765                  * fb is large enough for the active pipe configuration.
14766                  */
14767                 if (dev_priv->display.get_initial_plane_config) {
14768                         dev_priv->display.get_initial_plane_config(crtc,
14769                                                            &crtc->plane_config);
14770                         /*
14771                          * If the fb is shared between multiple heads, we'll
14772                          * just get the first one.
14773                          */
14774                         intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14775                 }
14776         }
14777 }
14778
14779 static void intel_enable_pipe_a(struct drm_device *dev)
14780 {
14781         struct intel_connector *connector;
14782         struct drm_connector *crt = NULL;
14783         struct intel_load_detect_pipe load_detect_temp;
14784         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14785
14786         /* We can't just switch on the pipe A, we need to set things up with a
14787          * proper mode and output configuration. As a gross hack, enable pipe A
14788          * by enabling the load detect pipe once. */
14789         for_each_intel_connector(dev, connector) {
14790                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14791                         crt = &connector->base;
14792                         break;
14793                 }
14794         }
14795
14796         if (!crt)
14797                 return;
14798
14799         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14800                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14801 }
14802
14803 static bool
14804 intel_check_plane_mapping(struct intel_crtc *crtc)
14805 {
14806         struct drm_device *dev = crtc->base.dev;
14807         struct drm_i915_private *dev_priv = dev->dev_private;
14808         u32 reg, val;
14809
14810         if (INTEL_INFO(dev)->num_pipes == 1)
14811                 return true;
14812
14813         reg = DSPCNTR(!crtc->plane);
14814         val = I915_READ(reg);
14815
14816         if ((val & DISPLAY_PLANE_ENABLE) &&
14817             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14818                 return false;
14819
14820         return true;
14821 }
14822
14823 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14824 {
14825         struct drm_device *dev = crtc->base.dev;
14826         struct drm_i915_private *dev_priv = dev->dev_private;
14827         u32 reg;
14828
14829         /* Clear any frame start delays used for debugging left by the BIOS */
14830         reg = PIPECONF(crtc->config->cpu_transcoder);
14831         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14832
14833         /* restore vblank interrupts to correct state */
14834         drm_crtc_vblank_reset(&crtc->base);
14835         if (crtc->active) {
14836                 update_scanline_offset(crtc);
14837                 drm_crtc_vblank_on(&crtc->base);
14838         }
14839
14840         /* We need to sanitize the plane -> pipe mapping first because this will
14841          * disable the crtc (and hence change the state) if it is wrong. Note
14842          * that gen4+ has a fixed plane -> pipe mapping.  */
14843         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14844                 struct intel_connector *connector;
14845                 bool plane;
14846
14847                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14848                               crtc->base.base.id);
14849
14850                 /* Pipe has the wrong plane attached and the plane is active.
14851                  * Temporarily change the plane mapping and disable everything
14852                  * ...  */
14853                 plane = crtc->plane;
14854                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14855                 crtc->plane = !plane;
14856                 intel_crtc_disable_planes(&crtc->base);
14857                 dev_priv->display.crtc_disable(&crtc->base);
14858                 crtc->plane = plane;
14859
14860                 /* ... and break all links. */
14861                 for_each_intel_connector(dev, connector) {
14862                         if (connector->encoder->base.crtc != &crtc->base)
14863                                 continue;
14864
14865                         connector->base.dpms = DRM_MODE_DPMS_OFF;
14866                         connector->base.encoder = NULL;
14867                 }
14868                 /* multiple connectors may have the same encoder:
14869                  *  handle them and break crtc link separately */
14870                 for_each_intel_connector(dev, connector)
14871                         if (connector->encoder->base.crtc == &crtc->base) {
14872                                 connector->encoder->base.crtc = NULL;
14873                                 connector->encoder->connectors_active = false;
14874                         }
14875
14876                 WARN_ON(crtc->active);
14877                 crtc->base.state->enable = false;
14878                 crtc->base.state->active = false;
14879                 crtc->base.enabled = false;
14880         }
14881
14882         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14883             crtc->pipe == PIPE_A && !crtc->active) {
14884                 /* BIOS forgot to enable pipe A, this mostly happens after
14885                  * resume. Force-enable the pipe to fix this, the update_dpms
14886                  * call below we restore the pipe to the right state, but leave
14887                  * the required bits on. */
14888                 intel_enable_pipe_a(dev);
14889         }
14890
14891         /* Adjust the state of the output pipe according to whether we
14892          * have active connectors/encoders. */
14893         intel_crtc_update_dpms(&crtc->base);
14894
14895         if (crtc->active != crtc->base.state->enable) {
14896                 struct intel_encoder *encoder;
14897
14898                 /* This can happen either due to bugs in the get_hw_state
14899                  * functions or because the pipe is force-enabled due to the
14900                  * pipe A quirk. */
14901                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14902                               crtc->base.base.id,
14903                               crtc->base.state->enable ? "enabled" : "disabled",
14904                               crtc->active ? "enabled" : "disabled");
14905
14906                 crtc->base.state->enable = crtc->active;
14907                 crtc->base.state->active = crtc->active;
14908                 crtc->base.enabled = crtc->active;
14909
14910                 /* Because we only establish the connector -> encoder ->
14911                  * crtc links if something is active, this means the
14912                  * crtc is now deactivated. Break the links. connector
14913                  * -> encoder links are only establish when things are
14914                  *  actually up, hence no need to break them. */
14915                 WARN_ON(crtc->active);
14916
14917                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14918                         WARN_ON(encoder->connectors_active);
14919                         encoder->base.crtc = NULL;
14920                 }
14921         }
14922
14923         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14924                 /*
14925                  * We start out with underrun reporting disabled to avoid races.
14926                  * For correct bookkeeping mark this on active crtcs.
14927                  *
14928                  * Also on gmch platforms we dont have any hardware bits to
14929                  * disable the underrun reporting. Which means we need to start
14930                  * out with underrun reporting disabled also on inactive pipes,
14931                  * since otherwise we'll complain about the garbage we read when
14932                  * e.g. coming up after runtime pm.
14933                  *
14934                  * No protection against concurrent access is required - at
14935                  * worst a fifo underrun happens which also sets this to false.
14936                  */
14937                 crtc->cpu_fifo_underrun_disabled = true;
14938                 crtc->pch_fifo_underrun_disabled = true;
14939         }
14940 }
14941
14942 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14943 {
14944         struct intel_connector *connector;
14945         struct drm_device *dev = encoder->base.dev;
14946
14947         /* We need to check both for a crtc link (meaning that the
14948          * encoder is active and trying to read from a pipe) and the
14949          * pipe itself being active. */
14950         bool has_active_crtc = encoder->base.crtc &&
14951                 to_intel_crtc(encoder->base.crtc)->active;
14952
14953         if (encoder->connectors_active && !has_active_crtc) {
14954                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14955                               encoder->base.base.id,
14956                               encoder->base.name);
14957
14958                 /* Connector is active, but has no active pipe. This is
14959                  * fallout from our resume register restoring. Disable
14960                  * the encoder manually again. */
14961                 if (encoder->base.crtc) {
14962                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14963                                       encoder->base.base.id,
14964                                       encoder->base.name);
14965                         encoder->disable(encoder);
14966                         if (encoder->post_disable)
14967                                 encoder->post_disable(encoder);
14968                 }
14969                 encoder->base.crtc = NULL;
14970                 encoder->connectors_active = false;
14971
14972                 /* Inconsistent output/port/pipe state happens presumably due to
14973                  * a bug in one of the get_hw_state functions. Or someplace else
14974                  * in our code, like the register restore mess on resume. Clamp
14975                  * things to off as a safer default. */
14976                 for_each_intel_connector(dev, connector) {
14977                         if (connector->encoder != encoder)
14978                                 continue;
14979                         connector->base.dpms = DRM_MODE_DPMS_OFF;
14980                         connector->base.encoder = NULL;
14981                 }
14982         }
14983         /* Enabled encoders without active connectors will be fixed in
14984          * the crtc fixup. */
14985 }
14986
14987 void i915_redisable_vga_power_on(struct drm_device *dev)
14988 {
14989         struct drm_i915_private *dev_priv = dev->dev_private;
14990         u32 vga_reg = i915_vgacntrl_reg(dev);
14991
14992         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14993                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14994                 i915_disable_vga(dev);
14995         }
14996 }
14997
14998 void i915_redisable_vga(struct drm_device *dev)
14999 {
15000         struct drm_i915_private *dev_priv = dev->dev_private;
15001
15002         /* This function can be called both from intel_modeset_setup_hw_state or
15003          * at a very early point in our resume sequence, where the power well
15004          * structures are not yet restored. Since this function is at a very
15005          * paranoid "someone might have enabled VGA while we were not looking"
15006          * level, just check if the power well is enabled instead of trying to
15007          * follow the "don't touch the power well if we don't need it" policy
15008          * the rest of the driver uses. */
15009         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15010                 return;
15011
15012         i915_redisable_vga_power_on(dev);
15013 }
15014
15015 static bool primary_get_hw_state(struct intel_crtc *crtc)
15016 {
15017         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15018
15019         if (!crtc->active)
15020                 return false;
15021
15022         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15023 }
15024
15025 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15026 {
15027         struct drm_i915_private *dev_priv = dev->dev_private;
15028         enum pipe pipe;
15029         struct intel_crtc *crtc;
15030         struct intel_encoder *encoder;
15031         struct intel_connector *connector;
15032         int i;
15033
15034         for_each_intel_crtc(dev, crtc) {
15035                 struct drm_plane *primary = crtc->base.primary;
15036                 struct intel_plane_state *plane_state;
15037
15038                 memset(crtc->config, 0, sizeof(*crtc->config));
15039
15040                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15041
15042                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15043                                                                  crtc->config);
15044
15045                 crtc->base.state->enable = crtc->active;
15046                 crtc->base.state->active = crtc->active;
15047                 crtc->base.enabled = crtc->active;
15048
15049                 plane_state = to_intel_plane_state(primary->state);
15050                 plane_state->visible = primary_get_hw_state(crtc);
15051
15052                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15053                               crtc->base.base.id,
15054                               crtc->active ? "enabled" : "disabled");
15055         }
15056
15057         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15058                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15059
15060                 pll->on = pll->get_hw_state(dev_priv, pll,
15061                                             &pll->config.hw_state);
15062                 pll->active = 0;
15063                 pll->config.crtc_mask = 0;
15064                 for_each_intel_crtc(dev, crtc) {
15065                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15066                                 pll->active++;
15067                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15068                         }
15069                 }
15070
15071                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15072                               pll->name, pll->config.crtc_mask, pll->on);
15073
15074                 if (pll->config.crtc_mask)
15075                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15076         }
15077
15078         for_each_intel_encoder(dev, encoder) {
15079                 pipe = 0;
15080
15081                 if (encoder->get_hw_state(encoder, &pipe)) {
15082                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15083                         encoder->base.crtc = &crtc->base;
15084                         encoder->get_config(encoder, crtc->config);
15085                 } else {
15086                         encoder->base.crtc = NULL;
15087                 }
15088
15089                 encoder->connectors_active = false;
15090                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15091                               encoder->base.base.id,
15092                               encoder->base.name,
15093                               encoder->base.crtc ? "enabled" : "disabled",
15094                               pipe_name(pipe));
15095         }
15096
15097         for_each_intel_connector(dev, connector) {
15098                 if (connector->get_hw_state(connector)) {
15099                         connector->base.dpms = DRM_MODE_DPMS_ON;
15100                         connector->encoder->connectors_active = true;
15101                         connector->base.encoder = &connector->encoder->base;
15102                 } else {
15103                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15104                         connector->base.encoder = NULL;
15105                 }
15106                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15107                               connector->base.base.id,
15108                               connector->base.name,
15109                               connector->base.encoder ? "enabled" : "disabled");
15110         }
15111 }
15112
15113 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15114  * and i915 state tracking structures. */
15115 void intel_modeset_setup_hw_state(struct drm_device *dev,
15116                                   bool force_restore)
15117 {
15118         struct drm_i915_private *dev_priv = dev->dev_private;
15119         enum pipe pipe;
15120         struct intel_crtc *crtc;
15121         struct intel_encoder *encoder;
15122         int i;
15123
15124         intel_modeset_readout_hw_state(dev);
15125
15126         /*
15127          * Now that we have the config, copy it to each CRTC struct
15128          * Note that this could go away if we move to using crtc_config
15129          * checking everywhere.
15130          */
15131         for_each_intel_crtc(dev, crtc) {
15132                 if (crtc->active && i915.fastboot) {
15133                         intel_mode_from_pipe_config(&crtc->base.mode,
15134                                                     crtc->config);
15135                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15136                                       crtc->base.base.id);
15137                         drm_mode_debug_printmodeline(&crtc->base.mode);
15138                 }
15139         }
15140
15141         /* HW state is read out, now we need to sanitize this mess. */
15142         for_each_intel_encoder(dev, encoder) {
15143                 intel_sanitize_encoder(encoder);
15144         }
15145
15146         for_each_pipe(dev_priv, pipe) {
15147                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15148                 intel_sanitize_crtc(crtc);
15149                 intel_dump_pipe_config(crtc, crtc->config,
15150                                        "[setup_hw_state]");
15151         }
15152
15153         intel_modeset_update_connector_atomic_state(dev);
15154
15155         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15156                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15157
15158                 if (!pll->on || pll->active)
15159                         continue;
15160
15161                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15162
15163                 pll->disable(dev_priv, pll);
15164                 pll->on = false;
15165         }
15166
15167         if (IS_GEN9(dev))
15168                 skl_wm_get_hw_state(dev);
15169         else if (HAS_PCH_SPLIT(dev))
15170                 ilk_wm_get_hw_state(dev);
15171
15172         if (force_restore) {
15173                 i915_redisable_vga(dev);
15174
15175                 /*
15176                  * We need to use raw interfaces for restoring state to avoid
15177                  * checking (bogus) intermediate states.
15178                  */
15179                 for_each_pipe(dev_priv, pipe) {
15180                         struct drm_crtc *crtc =
15181                                 dev_priv->pipe_to_crtc_mapping[pipe];
15182
15183                         intel_crtc_restore_mode(crtc);
15184                 }
15185         } else {
15186                 intel_modeset_update_staged_output_state(dev);
15187         }
15188
15189         intel_modeset_check_state(dev);
15190 }
15191
15192 void intel_modeset_gem_init(struct drm_device *dev)
15193 {
15194         struct drm_i915_private *dev_priv = dev->dev_private;
15195         struct drm_crtc *c;
15196         struct drm_i915_gem_object *obj;
15197         int ret;
15198
15199         mutex_lock(&dev->struct_mutex);
15200         intel_init_gt_powersave(dev);
15201         mutex_unlock(&dev->struct_mutex);
15202
15203         /*
15204          * There may be no VBT; and if the BIOS enabled SSC we can
15205          * just keep using it to avoid unnecessary flicker.  Whereas if the
15206          * BIOS isn't using it, don't assume it will work even if the VBT
15207          * indicates as much.
15208          */
15209         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15210                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15211                                                 DREF_SSC1_ENABLE);
15212
15213         intel_modeset_init_hw(dev);
15214
15215         intel_setup_overlay(dev);
15216
15217         /*
15218          * Make sure any fbs we allocated at startup are properly
15219          * pinned & fenced.  When we do the allocation it's too early
15220          * for this.
15221          */
15222         for_each_crtc(dev, c) {
15223                 obj = intel_fb_obj(c->primary->fb);
15224                 if (obj == NULL)
15225                         continue;
15226
15227                 mutex_lock(&dev->struct_mutex);
15228                 ret = intel_pin_and_fence_fb_obj(c->primary,
15229                                                  c->primary->fb,
15230                                                  c->primary->state,
15231                                                  NULL);
15232                 mutex_unlock(&dev->struct_mutex);
15233                 if (ret) {
15234                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15235                                   to_intel_crtc(c)->pipe);
15236                         drm_framebuffer_unreference(c->primary->fb);
15237                         c->primary->fb = NULL;
15238                         update_state_fb(c->primary);
15239                 }
15240         }
15241
15242         intel_backlight_register(dev);
15243 }
15244
15245 void intel_connector_unregister(struct intel_connector *intel_connector)
15246 {
15247         struct drm_connector *connector = &intel_connector->base;
15248
15249         intel_panel_destroy_backlight(connector);
15250         drm_connector_unregister(connector);
15251 }
15252
15253 void intel_modeset_cleanup(struct drm_device *dev)
15254 {
15255         struct drm_i915_private *dev_priv = dev->dev_private;
15256         struct drm_connector *connector;
15257
15258         intel_disable_gt_powersave(dev);
15259
15260         intel_backlight_unregister(dev);
15261
15262         /*
15263          * Interrupts and polling as the first thing to avoid creating havoc.
15264          * Too much stuff here (turning of connectors, ...) would
15265          * experience fancy races otherwise.
15266          */
15267         intel_irq_uninstall(dev_priv);
15268
15269         /*
15270          * Due to the hpd irq storm handling the hotplug work can re-arm the
15271          * poll handlers. Hence disable polling after hpd handling is shut down.
15272          */
15273         drm_kms_helper_poll_fini(dev);
15274
15275         mutex_lock(&dev->struct_mutex);
15276
15277         intel_unregister_dsm_handler();
15278
15279         intel_fbc_disable(dev);
15280
15281         mutex_unlock(&dev->struct_mutex);
15282
15283         /* flush any delayed tasks or pending work */
15284         flush_scheduled_work();
15285
15286         /* destroy the backlight and sysfs files before encoders/connectors */
15287         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15288                 struct intel_connector *intel_connector;
15289
15290                 intel_connector = to_intel_connector(connector);
15291                 intel_connector->unregister(intel_connector);
15292         }
15293
15294         drm_mode_config_cleanup(dev);
15295
15296         intel_cleanup_overlay(dev);
15297
15298         mutex_lock(&dev->struct_mutex);
15299         intel_cleanup_gt_powersave(dev);
15300         mutex_unlock(&dev->struct_mutex);
15301 }
15302
15303 /*
15304  * Return which encoder is currently attached for connector.
15305  */
15306 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15307 {
15308         return &intel_attached_encoder(connector)->base;
15309 }
15310
15311 void intel_connector_attach_encoder(struct intel_connector *connector,
15312                                     struct intel_encoder *encoder)
15313 {
15314         connector->encoder = encoder;
15315         drm_mode_connector_attach_encoder(&connector->base,
15316                                           &encoder->base);
15317 }
15318
15319 /*
15320  * set vga decode state - true == enable VGA decode
15321  */
15322 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15323 {
15324         struct drm_i915_private *dev_priv = dev->dev_private;
15325         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15326         u16 gmch_ctrl;
15327
15328         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15329                 DRM_ERROR("failed to read control word\n");
15330                 return -EIO;
15331         }
15332
15333         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15334                 return 0;
15335
15336         if (state)
15337                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15338         else
15339                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15340
15341         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15342                 DRM_ERROR("failed to write control word\n");
15343                 return -EIO;
15344         }
15345
15346         return 0;
15347 }
15348
15349 struct intel_display_error_state {
15350
15351         u32 power_well_driver;
15352
15353         int num_transcoders;
15354
15355         struct intel_cursor_error_state {
15356                 u32 control;
15357                 u32 position;
15358                 u32 base;
15359                 u32 size;
15360         } cursor[I915_MAX_PIPES];
15361
15362         struct intel_pipe_error_state {
15363                 bool power_domain_on;
15364                 u32 source;
15365                 u32 stat;
15366         } pipe[I915_MAX_PIPES];
15367
15368         struct intel_plane_error_state {
15369                 u32 control;
15370                 u32 stride;
15371                 u32 size;
15372                 u32 pos;
15373                 u32 addr;
15374                 u32 surface;
15375                 u32 tile_offset;
15376         } plane[I915_MAX_PIPES];
15377
15378         struct intel_transcoder_error_state {
15379                 bool power_domain_on;
15380                 enum transcoder cpu_transcoder;
15381
15382                 u32 conf;
15383
15384                 u32 htotal;
15385                 u32 hblank;
15386                 u32 hsync;
15387                 u32 vtotal;
15388                 u32 vblank;
15389                 u32 vsync;
15390         } transcoder[4];
15391 };
15392
15393 struct intel_display_error_state *
15394 intel_display_capture_error_state(struct drm_device *dev)
15395 {
15396         struct drm_i915_private *dev_priv = dev->dev_private;
15397         struct intel_display_error_state *error;
15398         int transcoders[] = {
15399                 TRANSCODER_A,
15400                 TRANSCODER_B,
15401                 TRANSCODER_C,
15402                 TRANSCODER_EDP,
15403         };
15404         int i;
15405
15406         if (INTEL_INFO(dev)->num_pipes == 0)
15407                 return NULL;
15408
15409         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15410         if (error == NULL)
15411                 return NULL;
15412
15413         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15414                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15415
15416         for_each_pipe(dev_priv, i) {
15417                 error->pipe[i].power_domain_on =
15418                         __intel_display_power_is_enabled(dev_priv,
15419                                                          POWER_DOMAIN_PIPE(i));
15420                 if (!error->pipe[i].power_domain_on)
15421                         continue;
15422
15423                 error->cursor[i].control = I915_READ(CURCNTR(i));
15424                 error->cursor[i].position = I915_READ(CURPOS(i));
15425                 error->cursor[i].base = I915_READ(CURBASE(i));
15426
15427                 error->plane[i].control = I915_READ(DSPCNTR(i));
15428                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15429                 if (INTEL_INFO(dev)->gen <= 3) {
15430                         error->plane[i].size = I915_READ(DSPSIZE(i));
15431                         error->plane[i].pos = I915_READ(DSPPOS(i));
15432                 }
15433                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15434                         error->plane[i].addr = I915_READ(DSPADDR(i));
15435                 if (INTEL_INFO(dev)->gen >= 4) {
15436                         error->plane[i].surface = I915_READ(DSPSURF(i));
15437                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15438                 }
15439
15440                 error->pipe[i].source = I915_READ(PIPESRC(i));
15441
15442                 if (HAS_GMCH_DISPLAY(dev))
15443                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15444         }
15445
15446         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15447         if (HAS_DDI(dev_priv->dev))
15448                 error->num_transcoders++; /* Account for eDP. */
15449
15450         for (i = 0; i < error->num_transcoders; i++) {
15451                 enum transcoder cpu_transcoder = transcoders[i];
15452
15453                 error->transcoder[i].power_domain_on =
15454                         __intel_display_power_is_enabled(dev_priv,
15455                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15456                 if (!error->transcoder[i].power_domain_on)
15457                         continue;
15458
15459                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15460
15461                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15462                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15463                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15464                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15465                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15466                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15467                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15468         }
15469
15470         return error;
15471 }
15472
15473 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15474
15475 void
15476 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15477                                 struct drm_device *dev,
15478                                 struct intel_display_error_state *error)
15479 {
15480         struct drm_i915_private *dev_priv = dev->dev_private;
15481         int i;
15482
15483         if (!error)
15484                 return;
15485
15486         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15487         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15488                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15489                            error->power_well_driver);
15490         for_each_pipe(dev_priv, i) {
15491                 err_printf(m, "Pipe [%d]:\n", i);
15492                 err_printf(m, "  Power: %s\n",
15493                            error->pipe[i].power_domain_on ? "on" : "off");
15494                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15495                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15496
15497                 err_printf(m, "Plane [%d]:\n", i);
15498                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15499                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15500                 if (INTEL_INFO(dev)->gen <= 3) {
15501                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15502                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15503                 }
15504                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15505                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15506                 if (INTEL_INFO(dev)->gen >= 4) {
15507                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15508                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15509                 }
15510
15511                 err_printf(m, "Cursor [%d]:\n", i);
15512                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15513                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15514                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15515         }
15516
15517         for (i = 0; i < error->num_transcoders; i++) {
15518                 err_printf(m, "CPU transcoder: %c\n",
15519                            transcoder_name(error->transcoder[i].cpu_transcoder));
15520                 err_printf(m, "  Power: %s\n",
15521                            error->transcoder[i].power_domain_on ? "on" : "off");
15522                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15523                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15524                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15525                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15526                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15527                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15528                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15529         }
15530 }
15531
15532 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15533 {
15534         struct intel_crtc *crtc;
15535
15536         for_each_intel_crtc(dev, crtc) {
15537                 struct intel_unpin_work *work;
15538
15539                 spin_lock_irq(&dev->event_lock);
15540
15541                 work = crtc->unpin_work;
15542
15543                 if (work && work->event &&
15544                     work->event->base.file_priv == file) {
15545                         kfree(work->event);
15546                         work->event = NULL;
15547                 }
15548
15549                 spin_unlock_irq(&dev->event_lock);
15550         }
15551 }