5e21b31198249349dc5e69265dbe20c8b0a23d02
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "drm_dp_helper.h"
37
38 #include "drm_crtc_helper.h"
39
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41
42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
43 static void intel_update_watermarks(struct drm_device *dev);
44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
45
46 typedef struct {
47     /* given values */
48     int n;
49     int m1, m2;
50     int p1, p2;
51     /* derived values */
52     int dot;
53     int vco;
54     int m;
55     int p;
56 } intel_clock_t;
57
58 typedef struct {
59     int min, max;
60 } intel_range_t;
61
62 typedef struct {
63     int dot_limit;
64     int p2_slow, p2_fast;
65 } intel_p2_t;
66
67 #define INTEL_P2_NUM                  2
68 typedef struct intel_limit intel_limit_t;
69 struct intel_limit {
70     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
71     intel_p2_t      p2;
72     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
73                       int, int, intel_clock_t *);
74 };
75
76 #define I8XX_DOT_MIN              25000
77 #define I8XX_DOT_MAX             350000
78 #define I8XX_VCO_MIN             930000
79 #define I8XX_VCO_MAX            1400000
80 #define I8XX_N_MIN                    3
81 #define I8XX_N_MAX                   16
82 #define I8XX_M_MIN                   96
83 #define I8XX_M_MAX                  140
84 #define I8XX_M1_MIN                  18
85 #define I8XX_M1_MAX                  26
86 #define I8XX_M2_MIN                   6
87 #define I8XX_M2_MAX                  16
88 #define I8XX_P_MIN                    4
89 #define I8XX_P_MAX                  128
90 #define I8XX_P1_MIN                   2
91 #define I8XX_P1_MAX                  33
92 #define I8XX_P1_LVDS_MIN              1
93 #define I8XX_P1_LVDS_MAX              6
94 #define I8XX_P2_SLOW                  4
95 #define I8XX_P2_FAST                  2
96 #define I8XX_P2_LVDS_SLOW             14
97 #define I8XX_P2_LVDS_FAST             7
98 #define I8XX_P2_SLOW_LIMIT       165000
99
100 #define I9XX_DOT_MIN              20000
101 #define I9XX_DOT_MAX             400000
102 #define I9XX_VCO_MIN            1400000
103 #define I9XX_VCO_MAX            2800000
104 #define PINEVIEW_VCO_MIN                1700000
105 #define PINEVIEW_VCO_MAX                3500000
106 #define I9XX_N_MIN                    1
107 #define I9XX_N_MAX                    6
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN                3
110 #define PINEVIEW_N_MAX                6
111 #define I9XX_M_MIN                   70
112 #define I9XX_M_MAX                  120
113 #define PINEVIEW_M_MIN                2
114 #define PINEVIEW_M_MAX              256
115 #define I9XX_M1_MIN                  10
116 #define I9XX_M1_MAX                  22
117 #define I9XX_M2_MIN                   5
118 #define I9XX_M2_MAX                   9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN               0
121 #define PINEVIEW_M1_MAX               0
122 #define PINEVIEW_M2_MIN               0
123 #define PINEVIEW_M2_MAX               254
124 #define I9XX_P_SDVO_DAC_MIN           5
125 #define I9XX_P_SDVO_DAC_MAX          80
126 #define I9XX_P_LVDS_MIN               7
127 #define I9XX_P_LVDS_MAX              98
128 #define PINEVIEW_P_LVDS_MIN                   7
129 #define PINEVIEW_P_LVDS_MAX                  112
130 #define I9XX_P1_MIN                   1
131 #define I9XX_P1_MAX                   8
132 #define I9XX_P2_SDVO_DAC_SLOW                10
133 #define I9XX_P2_SDVO_DAC_FAST                 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
135 #define I9XX_P2_LVDS_SLOW                    14
136 #define I9XX_P2_LVDS_FAST                     7
137 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
138
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN           25000
141 #define G4X_DOT_SDVO_MAX           270000
142 #define G4X_VCO_MIN                1750000
143 #define G4X_VCO_MAX                3500000
144 #define G4X_N_SDVO_MIN             1
145 #define G4X_N_SDVO_MAX             4
146 #define G4X_M_SDVO_MIN             104
147 #define G4X_M_SDVO_MAX             138
148 #define G4X_M1_SDVO_MIN            17
149 #define G4X_M1_SDVO_MAX            23
150 #define G4X_M2_SDVO_MIN            5
151 #define G4X_M2_SDVO_MAX            11
152 #define G4X_P_SDVO_MIN             10
153 #define G4X_P_SDVO_MAX             30
154 #define G4X_P1_SDVO_MIN            1
155 #define G4X_P1_SDVO_MAX            3
156 #define G4X_P2_SDVO_SLOW           10
157 #define G4X_P2_SDVO_FAST           10
158 #define G4X_P2_SDVO_LIMIT          270000
159
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN           22000
162 #define G4X_DOT_HDMI_DAC_MAX           400000
163 #define G4X_N_HDMI_DAC_MIN             1
164 #define G4X_N_HDMI_DAC_MAX             4
165 #define G4X_M_HDMI_DAC_MIN             104
166 #define G4X_M_HDMI_DAC_MAX             138
167 #define G4X_M1_HDMI_DAC_MIN            16
168 #define G4X_M1_HDMI_DAC_MAX            23
169 #define G4X_M2_HDMI_DAC_MIN            5
170 #define G4X_M2_HDMI_DAC_MAX            11
171 #define G4X_P_HDMI_DAC_MIN             5
172 #define G4X_P_HDMI_DAC_MAX             80
173 #define G4X_P1_HDMI_DAC_MIN            1
174 #define G4X_P1_HDMI_DAC_MAX            8
175 #define G4X_P2_HDMI_DAC_SLOW           10
176 #define G4X_P2_HDMI_DAC_FAST           5
177 #define G4X_P2_HDMI_DAC_LIMIT          165000
178
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
197
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
216
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN           161670
219 #define G4X_DOT_DISPLAY_PORT_MAX           227000
220 #define G4X_N_DISPLAY_PORT_MIN             1
221 #define G4X_N_DISPLAY_PORT_MAX             2
222 #define G4X_M_DISPLAY_PORT_MIN             97
223 #define G4X_M_DISPLAY_PORT_MAX             108
224 #define G4X_M1_DISPLAY_PORT_MIN            0x10
225 #define G4X_M1_DISPLAY_PORT_MAX            0x12
226 #define G4X_M2_DISPLAY_PORT_MIN            0x05
227 #define G4X_M2_DISPLAY_PORT_MAX            0x06
228 #define G4X_P_DISPLAY_PORT_MIN             10
229 #define G4X_P_DISPLAY_PORT_MAX             20
230 #define G4X_P1_DISPLAY_PORT_MIN            1
231 #define G4X_P1_DISPLAY_PORT_MAX            2
232 #define G4X_P2_DISPLAY_PORT_SLOW           10
233 #define G4X_P2_DISPLAY_PORT_FAST           10
234 #define G4X_P2_DISPLAY_PORT_LIMIT          0
235
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238    N/M1/M2, so here the range value for them is (actual_value-2).
239  */
240 #define IRONLAKE_DOT_MIN         25000
241 #define IRONLAKE_DOT_MAX         350000
242 #define IRONLAKE_VCO_MIN         1760000
243 #define IRONLAKE_VCO_MAX         3510000
244 #define IRONLAKE_M1_MIN          12
245 #define IRONLAKE_M1_MAX          22
246 #define IRONLAKE_M2_MIN          5
247 #define IRONLAKE_M2_MAX          9
248 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
249
250 /* We have parameter ranges for different type of outputs. */
251
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN      1
254 #define IRONLAKE_DAC_N_MAX      5
255 #define IRONLAKE_DAC_M_MIN      79
256 #define IRONLAKE_DAC_M_MAX      127
257 #define IRONLAKE_DAC_P_MIN      5
258 #define IRONLAKE_DAC_P_MAX      80
259 #define IRONLAKE_DAC_P1_MIN     1
260 #define IRONLAKE_DAC_P1_MAX     8
261 #define IRONLAKE_DAC_P2_SLOW    10
262 #define IRONLAKE_DAC_P2_FAST    5
263
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN   1
266 #define IRONLAKE_LVDS_S_N_MAX   3
267 #define IRONLAKE_LVDS_S_M_MIN   79
268 #define IRONLAKE_LVDS_S_M_MAX   118
269 #define IRONLAKE_LVDS_S_P_MIN   28
270 #define IRONLAKE_LVDS_S_P_MAX   112
271 #define IRONLAKE_LVDS_S_P1_MIN  2
272 #define IRONLAKE_LVDS_S_P1_MAX  8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
275
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN   1
278 #define IRONLAKE_LVDS_D_N_MAX   3
279 #define IRONLAKE_LVDS_D_M_MIN   79
280 #define IRONLAKE_LVDS_D_M_MAX   127
281 #define IRONLAKE_LVDS_D_P_MIN   14
282 #define IRONLAKE_LVDS_D_P_MAX   56
283 #define IRONLAKE_LVDS_D_P1_MIN  2
284 #define IRONLAKE_LVDS_D_P1_MAX  8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
287
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
299
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
311
312 /* DisplayPort */
313 #define IRONLAKE_DP_N_MIN               1
314 #define IRONLAKE_DP_N_MAX               2
315 #define IRONLAKE_DP_M_MIN               81
316 #define IRONLAKE_DP_M_MAX               90
317 #define IRONLAKE_DP_P_MIN               10
318 #define IRONLAKE_DP_P_MAX               20
319 #define IRONLAKE_DP_P2_FAST             10
320 #define IRONLAKE_DP_P2_SLOW             10
321 #define IRONLAKE_DP_P2_LIMIT            0
322 #define IRONLAKE_DP_P1_MIN              1
323 #define IRONLAKE_DP_P1_MAX              2
324
325 static bool
326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
327                     int target, int refclk, intel_clock_t *best_clock);
328 static bool
329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
330                         int target, int refclk, intel_clock_t *best_clock);
331
332 static bool
333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
334                       int target, int refclk, intel_clock_t *best_clock);
335 static bool
336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
337                            int target, int refclk, intel_clock_t *best_clock);
338
339 static const intel_limit_t intel_limits_i8xx_dvo = {
340         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
341         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
342         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
343         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
344         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
345         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
346         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
347         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
348         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
349                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
350         .find_pll = intel_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_i8xx_lvds = {
354         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
355         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
356         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
357         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
358         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
359         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
360         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
361         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
362         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
363                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
364         .find_pll = intel_find_best_PLL,
365 };
366         
367 static const intel_limit_t intel_limits_i9xx_sdvo = {
368         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
369         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
370         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
371         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
372         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
373         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
374         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
375         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
376         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
377                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
378         .find_pll = intel_find_best_PLL,
379 };
380
381 static const intel_limit_t intel_limits_i9xx_lvds = {
382         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
383         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
384         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
385         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
386         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
387         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
388         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
389         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
390         /* The single-channel range is 25-112Mhz, and dual-channel
391          * is 80-224Mhz.  Prefer single channel as much as possible.
392          */
393         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
394                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
395         .find_pll = intel_find_best_PLL,
396 };
397
398     /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo = {
400         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
401         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
402         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
403         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
404         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
405         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
406         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
407         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
408         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
409                  .p2_slow = G4X_P2_SDVO_SLOW,
410                  .p2_fast = G4X_P2_SDVO_FAST
411         },
412         .find_pll = intel_g4x_find_best_PLL,
413 };
414
415 static const intel_limit_t intel_limits_g4x_hdmi = {
416         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
418         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
419         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
420         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
421         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
422         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
423         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
424         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
425                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
426                  .p2_fast = G4X_P2_HDMI_DAC_FAST
427         },
428         .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
432         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
433                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
434         .vco = { .min = G4X_VCO_MIN,
435                  .max = G4X_VCO_MAX },
436         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
437                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
438         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
439                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
440         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
441                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
442         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
443                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
444         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
445                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
446         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
447                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
448         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
449                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
450                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
451         },
452         .find_pll = intel_g4x_find_best_PLL,
453 };
454
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
456         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
457                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
458         .vco = { .min = G4X_VCO_MIN,
459                  .max = G4X_VCO_MAX },
460         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
461                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
462         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
463                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
464         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
465                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
466         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
467                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
468         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
469                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
470         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
471                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
472         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
473                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
474                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
475         },
476         .find_pll = intel_g4x_find_best_PLL,
477 };
478
479 static const intel_limit_t intel_limits_g4x_display_port = {
480         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
481                  .max = G4X_DOT_DISPLAY_PORT_MAX },
482         .vco = { .min = G4X_VCO_MIN,
483                  .max = G4X_VCO_MAX},
484         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
485                  .max = G4X_N_DISPLAY_PORT_MAX },
486         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
487                  .max = G4X_M_DISPLAY_PORT_MAX },
488         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
489                  .max = G4X_M1_DISPLAY_PORT_MAX },
490         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
491                  .max = G4X_M2_DISPLAY_PORT_MAX },
492         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
493                  .max = G4X_P_DISPLAY_PORT_MAX },
494         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
495                  .max = G4X_P1_DISPLAY_PORT_MAX},
496         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
497                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
498                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
499         .find_pll = intel_find_pll_g4x_dp,
500 };
501
502 static const intel_limit_t intel_limits_pineview_sdvo = {
503         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
504         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
505         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
506         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
507         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
508         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
509         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
510         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
511         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
512                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
513         .find_pll = intel_find_best_PLL,
514 };
515
516 static const intel_limit_t intel_limits_pineview_lvds = {
517         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
518         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
519         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
520         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
521         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
522         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
523         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
524         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
525         /* Pineview only supports single-channel mode. */
526         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
527                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
528         .find_pll = intel_find_best_PLL,
529 };
530
531 static const intel_limit_t intel_limits_ironlake_dac = {
532         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
533         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
534         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
535         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
536         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
537         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
538         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
539         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
540         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
541                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
542                  .p2_fast = IRONLAKE_DAC_P2_FAST },
543         .find_pll = intel_g4x_find_best_PLL,
544 };
545
546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
547         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
548         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
549         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
550         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
551         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
552         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
553         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
554         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
555         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
556                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
557                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
558         .find_pll = intel_g4x_find_best_PLL,
559 };
560
561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
562         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
563         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
564         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
565         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
566         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
567         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
568         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
569         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
570         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
571                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
572                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
573         .find_pll = intel_g4x_find_best_PLL,
574 };
575
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
577         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
578         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
579         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
580         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
581         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
582         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
583         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
584         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
585         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
586                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
587                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
588         .find_pll = intel_g4x_find_best_PLL,
589 };
590
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
592         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
593         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
594         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
595         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
596         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
597         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
598         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
599         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
600         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
601                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
602                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
603         .find_pll = intel_g4x_find_best_PLL,
604 };
605
606 static const intel_limit_t intel_limits_ironlake_display_port = {
607         .dot = { .min = IRONLAKE_DOT_MIN,
608                  .max = IRONLAKE_DOT_MAX },
609         .vco = { .min = IRONLAKE_VCO_MIN,
610                  .max = IRONLAKE_VCO_MAX},
611         .n   = { .min = IRONLAKE_DP_N_MIN,
612                  .max = IRONLAKE_DP_N_MAX },
613         .m   = { .min = IRONLAKE_DP_M_MIN,
614                  .max = IRONLAKE_DP_M_MAX },
615         .m1  = { .min = IRONLAKE_M1_MIN,
616                  .max = IRONLAKE_M1_MAX },
617         .m2  = { .min = IRONLAKE_M2_MIN,
618                  .max = IRONLAKE_M2_MAX },
619         .p   = { .min = IRONLAKE_DP_P_MIN,
620                  .max = IRONLAKE_DP_P_MAX },
621         .p1  = { .min = IRONLAKE_DP_P1_MIN,
622                  .max = IRONLAKE_DP_P1_MAX},
623         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
624                  .p2_slow = IRONLAKE_DP_P2_SLOW,
625                  .p2_fast = IRONLAKE_DP_P2_FAST },
626         .find_pll = intel_find_pll_ironlake_dp,
627 };
628
629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
630 {
631         struct drm_device *dev = crtc->dev;
632         struct drm_i915_private *dev_priv = dev->dev_private;
633         const intel_limit_t *limit;
634         int refclk = 120;
635
636         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
638                         refclk = 100;
639
640                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
641                     LVDS_CLKB_POWER_UP) {
642                         /* LVDS dual channel */
643                         if (refclk == 100)
644                                 limit = &intel_limits_ironlake_dual_lvds_100m;
645                         else
646                                 limit = &intel_limits_ironlake_dual_lvds;
647                 } else {
648                         if (refclk == 100)
649                                 limit = &intel_limits_ironlake_single_lvds_100m;
650                         else
651                                 limit = &intel_limits_ironlake_single_lvds;
652                 }
653         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
654                         HAS_eDP)
655                 limit = &intel_limits_ironlake_display_port;
656         else
657                 limit = &intel_limits_ironlake_dac;
658
659         return limit;
660 }
661
662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
663 {
664         struct drm_device *dev = crtc->dev;
665         struct drm_i915_private *dev_priv = dev->dev_private;
666         const intel_limit_t *limit;
667
668         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
669                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
670                     LVDS_CLKB_POWER_UP)
671                         /* LVDS with dual channel */
672                         limit = &intel_limits_g4x_dual_channel_lvds;
673                 else
674                         /* LVDS with dual channel */
675                         limit = &intel_limits_g4x_single_channel_lvds;
676         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
677                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
678                 limit = &intel_limits_g4x_hdmi;
679         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
680                 limit = &intel_limits_g4x_sdvo;
681         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
682                 limit = &intel_limits_g4x_display_port;
683         } else /* The option is for other outputs */
684                 limit = &intel_limits_i9xx_sdvo;
685
686         return limit;
687 }
688
689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
690 {
691         struct drm_device *dev = crtc->dev;
692         const intel_limit_t *limit;
693
694         if (HAS_PCH_SPLIT(dev))
695                 limit = intel_ironlake_limit(crtc);
696         else if (IS_G4X(dev)) {
697                 limit = intel_g4x_limit(crtc);
698         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
699                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
700                         limit = &intel_limits_i9xx_lvds;
701                 else
702                         limit = &intel_limits_i9xx_sdvo;
703         } else if (IS_PINEVIEW(dev)) {
704                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705                         limit = &intel_limits_pineview_lvds;
706                 else
707                         limit = &intel_limits_pineview_sdvo;
708         } else {
709                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710                         limit = &intel_limits_i8xx_lvds;
711                 else
712                         limit = &intel_limits_i8xx_dvo;
713         }
714         return limit;
715 }
716
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk, intel_clock_t *clock)
719 {
720         clock->m = clock->m2 + 2;
721         clock->p = clock->p1 * clock->p2;
722         clock->vco = refclk * clock->m / clock->n;
723         clock->dot = clock->vco / clock->p;
724 }
725
726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
727 {
728         if (IS_PINEVIEW(dev)) {
729                 pineview_clock(refclk, clock);
730                 return;
731         }
732         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
733         clock->p = clock->p1 * clock->p2;
734         clock->vco = refclk * clock->m / (clock->n + 2);
735         clock->dot = clock->vco / clock->p;
736 }
737
738 /**
739  * Returns whether any output on the specified pipe is of the specified type
740  */
741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742 {
743     struct drm_device *dev = crtc->dev;
744     struct drm_mode_config *mode_config = &dev->mode_config;
745     struct drm_encoder *l_entry;
746
747     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
748             if (l_entry && l_entry->crtc == crtc) {
749                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
750                     if (intel_encoder->type == type)
751                             return true;
752             }
753     }
754     return false;
755 }
756
757 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
758 /**
759  * Returns whether the given set of divisors are valid for a given refclk with
760  * the given connectors.
761  */
762
763 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
764 {
765         const intel_limit_t *limit = intel_limit (crtc);
766         struct drm_device *dev = crtc->dev;
767
768         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
769                 INTELPllInvalid ("p1 out of range\n");
770         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
771                 INTELPllInvalid ("p out of range\n");
772         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
773                 INTELPllInvalid ("m2 out of range\n");
774         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
775                 INTELPllInvalid ("m1 out of range\n");
776         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
777                 INTELPllInvalid ("m1 <= m2\n");
778         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
779                 INTELPllInvalid ("m out of range\n");
780         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
781                 INTELPllInvalid ("n out of range\n");
782         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
783                 INTELPllInvalid ("vco out of range\n");
784         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785          * connector, etc., rather than just a single range.
786          */
787         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
788                 INTELPllInvalid ("dot out of range\n");
789
790         return true;
791 }
792
793 static bool
794 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
795                     int target, int refclk, intel_clock_t *best_clock)
796
797 {
798         struct drm_device *dev = crtc->dev;
799         struct drm_i915_private *dev_priv = dev->dev_private;
800         intel_clock_t clock;
801         int err = target;
802
803         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
804             (I915_READ(LVDS)) != 0) {
805                 /*
806                  * For LVDS, if the panel is on, just rely on its current
807                  * settings for dual-channel.  We haven't figured out how to
808                  * reliably set up different single/dual channel state, if we
809                  * even can.
810                  */
811                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
812                     LVDS_CLKB_POWER_UP)
813                         clock.p2 = limit->p2.p2_fast;
814                 else
815                         clock.p2 = limit->p2.p2_slow;
816         } else {
817                 if (target < limit->p2.dot_limit)
818                         clock.p2 = limit->p2.p2_slow;
819                 else
820                         clock.p2 = limit->p2.p2_fast;
821         }
822
823         memset (best_clock, 0, sizeof (*best_clock));
824
825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826              clock.m1++) {
827                 for (clock.m2 = limit->m2.min;
828                      clock.m2 <= limit->m2.max; clock.m2++) {
829                         /* m1 is always 0 in Pineview */
830                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
831                                 break;
832                         for (clock.n = limit->n.min;
833                              clock.n <= limit->n.max; clock.n++) {
834                                 for (clock.p1 = limit->p1.min;
835                                         clock.p1 <= limit->p1.max; clock.p1++) {
836                                         int this_err;
837
838                                         intel_clock(dev, refclk, &clock);
839
840                                         if (!intel_PLL_is_valid(crtc, &clock))
841                                                 continue;
842
843                                         this_err = abs(clock.dot - target);
844                                         if (this_err < err) {
845                                                 *best_clock = clock;
846                                                 err = this_err;
847                                         }
848                                 }
849                         }
850                 }
851         }
852
853         return (err != target);
854 }
855
856 static bool
857 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
858                         int target, int refclk, intel_clock_t *best_clock)
859 {
860         struct drm_device *dev = crtc->dev;
861         struct drm_i915_private *dev_priv = dev->dev_private;
862         intel_clock_t clock;
863         int max_n;
864         bool found;
865         /* approximately equals target * 0.00585 */
866         int err_most = (target >> 8) + (target >> 9);
867         found = false;
868
869         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
870                 int lvds_reg;
871
872                 if (HAS_PCH_SPLIT(dev))
873                         lvds_reg = PCH_LVDS;
874                 else
875                         lvds_reg = LVDS;
876                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
877                     LVDS_CLKB_POWER_UP)
878                         clock.p2 = limit->p2.p2_fast;
879                 else
880                         clock.p2 = limit->p2.p2_slow;
881         } else {
882                 if (target < limit->p2.dot_limit)
883                         clock.p2 = limit->p2.p2_slow;
884                 else
885                         clock.p2 = limit->p2.p2_fast;
886         }
887
888         memset(best_clock, 0, sizeof(*best_clock));
889         max_n = limit->n.max;
890         /* based on hardware requirement, prefer smaller n to precision */
891         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
892                 /* based on hardware requirement, prefere larger m1,m2 */
893                 for (clock.m1 = limit->m1.max;
894                      clock.m1 >= limit->m1.min; clock.m1--) {
895                         for (clock.m2 = limit->m2.max;
896                              clock.m2 >= limit->m2.min; clock.m2--) {
897                                 for (clock.p1 = limit->p1.max;
898                                      clock.p1 >= limit->p1.min; clock.p1--) {
899                                         int this_err;
900
901                                         intel_clock(dev, refclk, &clock);
902                                         if (!intel_PLL_is_valid(crtc, &clock))
903                                                 continue;
904                                         this_err = abs(clock.dot - target) ;
905                                         if (this_err < err_most) {
906                                                 *best_clock = clock;
907                                                 err_most = this_err;
908                                                 max_n = clock.n;
909                                                 found = true;
910                                         }
911                                 }
912                         }
913                 }
914         }
915         return found;
916 }
917
918 static bool
919 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
920                            int target, int refclk, intel_clock_t *best_clock)
921 {
922         struct drm_device *dev = crtc->dev;
923         intel_clock_t clock;
924
925         /* return directly when it is eDP */
926         if (HAS_eDP)
927                 return true;
928
929         if (target < 200000) {
930                 clock.n = 1;
931                 clock.p1 = 2;
932                 clock.p2 = 10;
933                 clock.m1 = 12;
934                 clock.m2 = 9;
935         } else {
936                 clock.n = 2;
937                 clock.p1 = 1;
938                 clock.p2 = 10;
939                 clock.m1 = 14;
940                 clock.m2 = 8;
941         }
942         intel_clock(dev, refclk, &clock);
943         memcpy(best_clock, &clock, sizeof(intel_clock_t));
944         return true;
945 }
946
947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
948 static bool
949 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
950                       int target, int refclk, intel_clock_t *best_clock)
951 {
952     intel_clock_t clock;
953     if (target < 200000) {
954         clock.p1 = 2;
955         clock.p2 = 10;
956         clock.n = 2;
957         clock.m1 = 23;
958         clock.m2 = 8;
959     } else {
960         clock.p1 = 1;
961         clock.p2 = 10;
962         clock.n = 1;
963         clock.m1 = 14;
964         clock.m2 = 2;
965     }
966     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
967     clock.p = (clock.p1 * clock.p2);
968     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
969     clock.vco = 0;
970     memcpy(best_clock, &clock, sizeof(intel_clock_t));
971     return true;
972 }
973
974 void
975 intel_wait_for_vblank(struct drm_device *dev)
976 {
977         /* Wait for 20ms, i.e. one cycle at 50hz. */
978         msleep(20);
979 }
980
981 /* Parameters have changed, update FBC info */
982 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
983 {
984         struct drm_device *dev = crtc->dev;
985         struct drm_i915_private *dev_priv = dev->dev_private;
986         struct drm_framebuffer *fb = crtc->fb;
987         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
988         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
990         int plane, i;
991         u32 fbc_ctl, fbc_ctl2;
992
993         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
994
995         if (fb->pitch < dev_priv->cfb_pitch)
996                 dev_priv->cfb_pitch = fb->pitch;
997
998         /* FBC_CTL wants 64B units */
999         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1000         dev_priv->cfb_fence = obj_priv->fence_reg;
1001         dev_priv->cfb_plane = intel_crtc->plane;
1002         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1003
1004         /* Clear old tags */
1005         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1006                 I915_WRITE(FBC_TAG + (i * 4), 0);
1007
1008         /* Set it up... */
1009         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1010         if (obj_priv->tiling_mode != I915_TILING_NONE)
1011                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1012         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1013         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1014
1015         /* enable it... */
1016         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1017         if (IS_I945GM(dev))
1018                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1019         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1020         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1021         if (obj_priv->tiling_mode != I915_TILING_NONE)
1022                 fbc_ctl |= dev_priv->cfb_fence;
1023         I915_WRITE(FBC_CONTROL, fbc_ctl);
1024
1025         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1026                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1027 }
1028
1029 void i8xx_disable_fbc(struct drm_device *dev)
1030 {
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1033         u32 fbc_ctl;
1034
1035         if (!I915_HAS_FBC(dev))
1036                 return;
1037
1038         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1039                 return; /* Already off, just return */
1040
1041         /* Disable compression */
1042         fbc_ctl = I915_READ(FBC_CONTROL);
1043         fbc_ctl &= ~FBC_CTL_EN;
1044         I915_WRITE(FBC_CONTROL, fbc_ctl);
1045
1046         /* Wait for compressing bit to clear */
1047         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1048                 if (time_after(jiffies, timeout)) {
1049                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1050                         break;
1051                 }
1052                 ; /* do nothing */
1053         }
1054
1055         intel_wait_for_vblank(dev);
1056
1057         DRM_DEBUG_KMS("disabled FBC\n");
1058 }
1059
1060 static bool i8xx_fbc_enabled(struct drm_device *dev)
1061 {
1062         struct drm_i915_private *dev_priv = dev->dev_private;
1063
1064         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1065 }
1066
1067 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1068 {
1069         struct drm_device *dev = crtc->dev;
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         struct drm_framebuffer *fb = crtc->fb;
1072         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1073         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1075         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1076                      DPFC_CTL_PLANEB);
1077         unsigned long stall_watermark = 200;
1078         u32 dpfc_ctl;
1079
1080         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1081         dev_priv->cfb_fence = obj_priv->fence_reg;
1082         dev_priv->cfb_plane = intel_crtc->plane;
1083
1084         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1085         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1086                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1087                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1088         } else {
1089                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1090         }
1091
1092         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1093         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1094                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1095                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1096         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1097
1098         /* enable it... */
1099         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1100
1101         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1102 }
1103
1104 void g4x_disable_fbc(struct drm_device *dev)
1105 {
1106         struct drm_i915_private *dev_priv = dev->dev_private;
1107         u32 dpfc_ctl;
1108
1109         /* Disable compression */
1110         dpfc_ctl = I915_READ(DPFC_CONTROL);
1111         dpfc_ctl &= ~DPFC_CTL_EN;
1112         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1113         intel_wait_for_vblank(dev);
1114
1115         DRM_DEBUG_KMS("disabled FBC\n");
1116 }
1117
1118 static bool g4x_fbc_enabled(struct drm_device *dev)
1119 {
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121
1122         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1123 }
1124
1125 bool intel_fbc_enabled(struct drm_device *dev)
1126 {
1127         struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129         if (!dev_priv->display.fbc_enabled)
1130                 return false;
1131
1132         return dev_priv->display.fbc_enabled(dev);
1133 }
1134
1135 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1136 {
1137         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1138
1139         if (!dev_priv->display.enable_fbc)
1140                 return;
1141
1142         dev_priv->display.enable_fbc(crtc, interval);
1143 }
1144
1145 void intel_disable_fbc(struct drm_device *dev)
1146 {
1147         struct drm_i915_private *dev_priv = dev->dev_private;
1148
1149         if (!dev_priv->display.disable_fbc)
1150                 return;
1151
1152         dev_priv->display.disable_fbc(dev);
1153 }
1154
1155 /**
1156  * intel_update_fbc - enable/disable FBC as needed
1157  * @crtc: CRTC to point the compressor at
1158  * @mode: mode in use
1159  *
1160  * Set up the framebuffer compression hardware at mode set time.  We
1161  * enable it if possible:
1162  *   - plane A only (on pre-965)
1163  *   - no pixel mulitply/line duplication
1164  *   - no alpha buffer discard
1165  *   - no dual wide
1166  *   - framebuffer <= 2048 in width, 1536 in height
1167  *
1168  * We can't assume that any compression will take place (worst case),
1169  * so the compressed buffer has to be the same size as the uncompressed
1170  * one.  It also must reside (along with the line length buffer) in
1171  * stolen memory.
1172  *
1173  * We need to enable/disable FBC on a global basis.
1174  */
1175 static void intel_update_fbc(struct drm_crtc *crtc,
1176                              struct drm_display_mode *mode)
1177 {
1178         struct drm_device *dev = crtc->dev;
1179         struct drm_i915_private *dev_priv = dev->dev_private;
1180         struct drm_framebuffer *fb = crtc->fb;
1181         struct intel_framebuffer *intel_fb;
1182         struct drm_i915_gem_object *obj_priv;
1183         struct drm_crtc *tmp_crtc;
1184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1185         int plane = intel_crtc->plane;
1186         int crtcs_enabled = 0;
1187
1188         DRM_DEBUG_KMS("\n");
1189
1190         if (!i915_powersave)
1191                 return;
1192
1193         if (!I915_HAS_FBC(dev))
1194                 return;
1195
1196         if (!crtc->fb)
1197                 return;
1198
1199         intel_fb = to_intel_framebuffer(fb);
1200         obj_priv = to_intel_bo(intel_fb->obj);
1201
1202         /*
1203          * If FBC is already on, we just have to verify that we can
1204          * keep it that way...
1205          * Need to disable if:
1206          *   - more than one pipe is active
1207          *   - changing FBC params (stride, fence, mode)
1208          *   - new fb is too large to fit in compressed buffer
1209          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1210          */
1211         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1212                 if (tmp_crtc->enabled)
1213                         crtcs_enabled++;
1214         }
1215         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1216         if (crtcs_enabled > 1) {
1217                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1218                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1219                 goto out_disable;
1220         }
1221         if (intel_fb->obj->size > dev_priv->cfb_size) {
1222                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1223                                 "compression\n");
1224                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1225                 goto out_disable;
1226         }
1227         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1228             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1229                 DRM_DEBUG_KMS("mode incompatible with compression, "
1230                                 "disabling\n");
1231                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1232                 goto out_disable;
1233         }
1234         if ((mode->hdisplay > 2048) ||
1235             (mode->vdisplay > 1536)) {
1236                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1237                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1238                 goto out_disable;
1239         }
1240         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1241                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1242                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1243                 goto out_disable;
1244         }
1245         if (obj_priv->tiling_mode != I915_TILING_X) {
1246                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1247                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1248                 goto out_disable;
1249         }
1250
1251         if (intel_fbc_enabled(dev)) {
1252                 /* We can re-enable it in this case, but need to update pitch */
1253                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1254                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1255                     (plane != dev_priv->cfb_plane))
1256                         intel_disable_fbc(dev);
1257         }
1258
1259         /* Now try to turn it back on if possible */
1260         if (!intel_fbc_enabled(dev))
1261                 intel_enable_fbc(crtc, 500);
1262
1263         return;
1264
1265 out_disable:
1266         /* Multiple disables should be harmless */
1267         if (intel_fbc_enabled(dev)) {
1268                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1269                 intel_disable_fbc(dev);
1270         }
1271 }
1272
1273 int
1274 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1275 {
1276         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1277         u32 alignment;
1278         int ret;
1279
1280         switch (obj_priv->tiling_mode) {
1281         case I915_TILING_NONE:
1282                 alignment = 64 * 1024;
1283                 break;
1284         case I915_TILING_X:
1285                 /* pin() will align the object as required by fence */
1286                 alignment = 0;
1287                 break;
1288         case I915_TILING_Y:
1289                 /* FIXME: Is this true? */
1290                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1291                 return -EINVAL;
1292         default:
1293                 BUG();
1294         }
1295
1296         ret = i915_gem_object_pin(obj, alignment);
1297         if (ret != 0)
1298                 return ret;
1299
1300         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1301          * fence, whereas 965+ only requires a fence if using
1302          * framebuffer compression.  For simplicity, we always install
1303          * a fence as the cost is not that onerous.
1304          */
1305         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1306             obj_priv->tiling_mode != I915_TILING_NONE) {
1307                 ret = i915_gem_object_get_fence_reg(obj);
1308                 if (ret != 0) {
1309                         i915_gem_object_unpin(obj);
1310                         return ret;
1311                 }
1312         }
1313
1314         return 0;
1315 }
1316
1317 static int
1318 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1319                     struct drm_framebuffer *old_fb)
1320 {
1321         struct drm_device *dev = crtc->dev;
1322         struct drm_i915_private *dev_priv = dev->dev_private;
1323         struct drm_i915_master_private *master_priv;
1324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1325         struct intel_framebuffer *intel_fb;
1326         struct drm_i915_gem_object *obj_priv;
1327         struct drm_gem_object *obj;
1328         int pipe = intel_crtc->pipe;
1329         int plane = intel_crtc->plane;
1330         unsigned long Start, Offset;
1331         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1332         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1333         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1334         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1335         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1336         u32 dspcntr;
1337         int ret;
1338
1339         /* no fb bound */
1340         if (!crtc->fb) {
1341                 DRM_DEBUG_KMS("No FB bound\n");
1342                 return 0;
1343         }
1344
1345         switch (plane) {
1346         case 0:
1347         case 1:
1348                 break;
1349         default:
1350                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1351                 return -EINVAL;
1352         }
1353
1354         intel_fb = to_intel_framebuffer(crtc->fb);
1355         obj = intel_fb->obj;
1356         obj_priv = to_intel_bo(obj);
1357
1358         mutex_lock(&dev->struct_mutex);
1359         ret = intel_pin_and_fence_fb_obj(dev, obj);
1360         if (ret != 0) {
1361                 mutex_unlock(&dev->struct_mutex);
1362                 return ret;
1363         }
1364
1365         ret = i915_gem_object_set_to_display_plane(obj);
1366         if (ret != 0) {
1367                 i915_gem_object_unpin(obj);
1368                 mutex_unlock(&dev->struct_mutex);
1369                 return ret;
1370         }
1371
1372         dspcntr = I915_READ(dspcntr_reg);
1373         /* Mask out pixel format bits in case we change it */
1374         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1375         switch (crtc->fb->bits_per_pixel) {
1376         case 8:
1377                 dspcntr |= DISPPLANE_8BPP;
1378                 break;
1379         case 16:
1380                 if (crtc->fb->depth == 15)
1381                         dspcntr |= DISPPLANE_15_16BPP;
1382                 else
1383                         dspcntr |= DISPPLANE_16BPP;
1384                 break;
1385         case 24:
1386         case 32:
1387                 if (crtc->fb->depth == 30)
1388                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1389                 else
1390                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1391                 break;
1392         default:
1393                 DRM_ERROR("Unknown color depth\n");
1394                 i915_gem_object_unpin(obj);
1395                 mutex_unlock(&dev->struct_mutex);
1396                 return -EINVAL;
1397         }
1398         if (IS_I965G(dev)) {
1399                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1400                         dspcntr |= DISPPLANE_TILED;
1401                 else
1402                         dspcntr &= ~DISPPLANE_TILED;
1403         }
1404
1405         if (HAS_PCH_SPLIT(dev))
1406                 /* must disable */
1407                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1408
1409         I915_WRITE(dspcntr_reg, dspcntr);
1410
1411         Start = obj_priv->gtt_offset;
1412         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1413
1414         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1415                       Start, Offset, x, y, crtc->fb->pitch);
1416         I915_WRITE(dspstride, crtc->fb->pitch);
1417         if (IS_I965G(dev)) {
1418                 I915_WRITE(dspbase, Offset);
1419                 I915_READ(dspbase);
1420                 I915_WRITE(dspsurf, Start);
1421                 I915_READ(dspsurf);
1422                 I915_WRITE(dsptileoff, (y << 16) | x);
1423         } else {
1424                 I915_WRITE(dspbase, Start + Offset);
1425                 I915_READ(dspbase);
1426         }
1427
1428         if ((IS_I965G(dev) || plane == 0))
1429                 intel_update_fbc(crtc, &crtc->mode);
1430
1431         intel_wait_for_vblank(dev);
1432
1433         if (old_fb) {
1434                 intel_fb = to_intel_framebuffer(old_fb);
1435                 obj_priv = to_intel_bo(intel_fb->obj);
1436                 i915_gem_object_unpin(intel_fb->obj);
1437         }
1438         intel_increase_pllclock(crtc, true);
1439
1440         mutex_unlock(&dev->struct_mutex);
1441
1442         if (!dev->primary->master)
1443                 return 0;
1444
1445         master_priv = dev->primary->master->driver_priv;
1446         if (!master_priv->sarea_priv)
1447                 return 0;
1448
1449         if (pipe) {
1450                 master_priv->sarea_priv->pipeB_x = x;
1451                 master_priv->sarea_priv->pipeB_y = y;
1452         } else {
1453                 master_priv->sarea_priv->pipeA_x = x;
1454                 master_priv->sarea_priv->pipeA_y = y;
1455         }
1456
1457         return 0;
1458 }
1459
1460 /* Disable the VGA plane that we never use */
1461 static void i915_disable_vga (struct drm_device *dev)
1462 {
1463         struct drm_i915_private *dev_priv = dev->dev_private;
1464         u8 sr1;
1465         u32 vga_reg;
1466
1467         if (HAS_PCH_SPLIT(dev))
1468                 vga_reg = CPU_VGACNTRL;
1469         else
1470                 vga_reg = VGACNTRL;
1471
1472         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1473                 return;
1474
1475         I915_WRITE8(VGA_SR_INDEX, 1);
1476         sr1 = I915_READ8(VGA_SR_DATA);
1477         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1478         udelay(100);
1479
1480         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1481 }
1482
1483 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1484 {
1485         struct drm_device *dev = crtc->dev;
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487         u32 dpa_ctl;
1488
1489         DRM_DEBUG_KMS("\n");
1490         dpa_ctl = I915_READ(DP_A);
1491         dpa_ctl &= ~DP_PLL_ENABLE;
1492         I915_WRITE(DP_A, dpa_ctl);
1493 }
1494
1495 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1496 {
1497         struct drm_device *dev = crtc->dev;
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499         u32 dpa_ctl;
1500
1501         dpa_ctl = I915_READ(DP_A);
1502         dpa_ctl |= DP_PLL_ENABLE;
1503         I915_WRITE(DP_A, dpa_ctl);
1504         udelay(200);
1505 }
1506
1507
1508 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1509 {
1510         struct drm_device *dev = crtc->dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         u32 dpa_ctl;
1513
1514         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1515         dpa_ctl = I915_READ(DP_A);
1516         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1517
1518         if (clock < 200000) {
1519                 u32 temp;
1520                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1521                 /* workaround for 160Mhz:
1522                    1) program 0x4600c bits 15:0 = 0x8124
1523                    2) program 0x46010 bit 0 = 1
1524                    3) program 0x46034 bit 24 = 1
1525                    4) program 0x64000 bit 14 = 1
1526                    */
1527                 temp = I915_READ(0x4600c);
1528                 temp &= 0xffff0000;
1529                 I915_WRITE(0x4600c, temp | 0x8124);
1530
1531                 temp = I915_READ(0x46010);
1532                 I915_WRITE(0x46010, temp | 1);
1533
1534                 temp = I915_READ(0x46034);
1535                 I915_WRITE(0x46034, temp | (1 << 24));
1536         } else {
1537                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1538         }
1539         I915_WRITE(DP_A, dpa_ctl);
1540
1541         udelay(500);
1542 }
1543
1544 /* The FDI link training functions for ILK/Ibexpeak. */
1545 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1546 {
1547         struct drm_device *dev = crtc->dev;
1548         struct drm_i915_private *dev_priv = dev->dev_private;
1549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1550         int pipe = intel_crtc->pipe;
1551         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1552         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1553         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1554         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1555         u32 temp, tries = 0;
1556
1557         /* enable CPU FDI TX and PCH FDI RX */
1558         temp = I915_READ(fdi_tx_reg);
1559         temp |= FDI_TX_ENABLE;
1560         temp &= ~(7 << 19);
1561         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1562         temp &= ~FDI_LINK_TRAIN_NONE;
1563         temp |= FDI_LINK_TRAIN_PATTERN_1;
1564         I915_WRITE(fdi_tx_reg, temp);
1565         I915_READ(fdi_tx_reg);
1566
1567         temp = I915_READ(fdi_rx_reg);
1568         temp &= ~FDI_LINK_TRAIN_NONE;
1569         temp |= FDI_LINK_TRAIN_PATTERN_1;
1570         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1571         I915_READ(fdi_rx_reg);
1572         udelay(150);
1573
1574         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1575            for train result */
1576         temp = I915_READ(fdi_rx_imr_reg);
1577         temp &= ~FDI_RX_SYMBOL_LOCK;
1578         temp &= ~FDI_RX_BIT_LOCK;
1579         I915_WRITE(fdi_rx_imr_reg, temp);
1580         I915_READ(fdi_rx_imr_reg);
1581         udelay(150);
1582
1583         for (;;) {
1584                 temp = I915_READ(fdi_rx_iir_reg);
1585                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1586
1587                 if ((temp & FDI_RX_BIT_LOCK)) {
1588                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1589                         I915_WRITE(fdi_rx_iir_reg,
1590                                    temp | FDI_RX_BIT_LOCK);
1591                         break;
1592                 }
1593
1594                 tries++;
1595
1596                 if (tries > 5) {
1597                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1598                         break;
1599                 }
1600         }
1601
1602         /* Train 2 */
1603         temp = I915_READ(fdi_tx_reg);
1604         temp &= ~FDI_LINK_TRAIN_NONE;
1605         temp |= FDI_LINK_TRAIN_PATTERN_2;
1606         I915_WRITE(fdi_tx_reg, temp);
1607
1608         temp = I915_READ(fdi_rx_reg);
1609         temp &= ~FDI_LINK_TRAIN_NONE;
1610         temp |= FDI_LINK_TRAIN_PATTERN_2;
1611         I915_WRITE(fdi_rx_reg, temp);
1612         udelay(150);
1613
1614         tries = 0;
1615
1616         for (;;) {
1617                 temp = I915_READ(fdi_rx_iir_reg);
1618                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1619
1620                 if (temp & FDI_RX_SYMBOL_LOCK) {
1621                         I915_WRITE(fdi_rx_iir_reg,
1622                                    temp | FDI_RX_SYMBOL_LOCK);
1623                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1624                         break;
1625                 }
1626
1627                 tries++;
1628
1629                 if (tries > 5) {
1630                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1631                         break;
1632                 }
1633         }
1634
1635         DRM_DEBUG_KMS("FDI train done\n");
1636 }
1637
1638 static int snb_b_fdi_train_param [] = {
1639         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1640         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1641         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1642         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1643 };
1644
1645 /* The FDI link training functions for SNB/Cougarpoint. */
1646 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1647 {
1648         struct drm_device *dev = crtc->dev;
1649         struct drm_i915_private *dev_priv = dev->dev_private;
1650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1651         int pipe = intel_crtc->pipe;
1652         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1653         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1654         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1655         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1656         u32 temp, i;
1657
1658         /* enable CPU FDI TX and PCH FDI RX */
1659         temp = I915_READ(fdi_tx_reg);
1660         temp |= FDI_TX_ENABLE;
1661         temp &= ~(7 << 19);
1662         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1663         temp &= ~FDI_LINK_TRAIN_NONE;
1664         temp |= FDI_LINK_TRAIN_PATTERN_1;
1665         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1666         /* SNB-B */
1667         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1668         I915_WRITE(fdi_tx_reg, temp);
1669         I915_READ(fdi_tx_reg);
1670
1671         temp = I915_READ(fdi_rx_reg);
1672         if (HAS_PCH_CPT(dev)) {
1673                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1674                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1675         } else {
1676                 temp &= ~FDI_LINK_TRAIN_NONE;
1677                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1678         }
1679         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1680         I915_READ(fdi_rx_reg);
1681         udelay(150);
1682
1683         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1684            for train result */
1685         temp = I915_READ(fdi_rx_imr_reg);
1686         temp &= ~FDI_RX_SYMBOL_LOCK;
1687         temp &= ~FDI_RX_BIT_LOCK;
1688         I915_WRITE(fdi_rx_imr_reg, temp);
1689         I915_READ(fdi_rx_imr_reg);
1690         udelay(150);
1691
1692         for (i = 0; i < 4; i++ ) {
1693                 temp = I915_READ(fdi_tx_reg);
1694                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1695                 temp |= snb_b_fdi_train_param[i];
1696                 I915_WRITE(fdi_tx_reg, temp);
1697                 udelay(500);
1698
1699                 temp = I915_READ(fdi_rx_iir_reg);
1700                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1701
1702                 if (temp & FDI_RX_BIT_LOCK) {
1703                         I915_WRITE(fdi_rx_iir_reg,
1704                                    temp | FDI_RX_BIT_LOCK);
1705                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1706                         break;
1707                 }
1708         }
1709         if (i == 4)
1710                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1711
1712         /* Train 2 */
1713         temp = I915_READ(fdi_tx_reg);
1714         temp &= ~FDI_LINK_TRAIN_NONE;
1715         temp |= FDI_LINK_TRAIN_PATTERN_2;
1716         if (IS_GEN6(dev)) {
1717                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1718                 /* SNB-B */
1719                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1720         }
1721         I915_WRITE(fdi_tx_reg, temp);
1722
1723         temp = I915_READ(fdi_rx_reg);
1724         if (HAS_PCH_CPT(dev)) {
1725                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1726                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1727         } else {
1728                 temp &= ~FDI_LINK_TRAIN_NONE;
1729                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1730         }
1731         I915_WRITE(fdi_rx_reg, temp);
1732         udelay(150);
1733
1734         for (i = 0; i < 4; i++ ) {
1735                 temp = I915_READ(fdi_tx_reg);
1736                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1737                 temp |= snb_b_fdi_train_param[i];
1738                 I915_WRITE(fdi_tx_reg, temp);
1739                 udelay(500);
1740
1741                 temp = I915_READ(fdi_rx_iir_reg);
1742                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1743
1744                 if (temp & FDI_RX_SYMBOL_LOCK) {
1745                         I915_WRITE(fdi_rx_iir_reg,
1746                                    temp | FDI_RX_SYMBOL_LOCK);
1747                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1748                         break;
1749                 }
1750         }
1751         if (i == 4)
1752                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1753
1754         DRM_DEBUG_KMS("FDI train done.\n");
1755 }
1756
1757 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1758 {
1759         struct drm_device *dev = crtc->dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1762         int pipe = intel_crtc->pipe;
1763         int plane = intel_crtc->plane;
1764         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1765         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1766         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1767         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1768         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1769         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1770         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1771         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1772         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1773         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1774         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1775         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1776         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1777         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1778         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1779         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1780         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1781         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1782         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1783         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1784         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1785         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1786         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1787         u32 temp;
1788         int n;
1789         u32 pipe_bpc;
1790
1791         temp = I915_READ(pipeconf_reg);
1792         pipe_bpc = temp & PIPE_BPC_MASK;
1793
1794         /* XXX: When our outputs are all unaware of DPMS modes other than off
1795          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1796          */
1797         switch (mode) {
1798         case DRM_MODE_DPMS_ON:
1799         case DRM_MODE_DPMS_STANDBY:
1800         case DRM_MODE_DPMS_SUSPEND:
1801                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1802
1803                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1804                         temp = I915_READ(PCH_LVDS);
1805                         if ((temp & LVDS_PORT_EN) == 0) {
1806                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1807                                 POSTING_READ(PCH_LVDS);
1808                         }
1809                 }
1810
1811                 if (HAS_eDP) {
1812                         /* enable eDP PLL */
1813                         ironlake_enable_pll_edp(crtc);
1814                 } else {
1815
1816                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1817                         temp = I915_READ(fdi_rx_reg);
1818                         /*
1819                          * make the BPC in FDI Rx be consistent with that in
1820                          * pipeconf reg.
1821                          */
1822                         temp &= ~(0x7 << 16);
1823                         temp |= (pipe_bpc << 11);
1824                         temp &= ~(7 << 19);
1825                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1826                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1827                         I915_READ(fdi_rx_reg);
1828                         udelay(200);
1829
1830                         /* Switch from Rawclk to PCDclk */
1831                         temp = I915_READ(fdi_rx_reg);
1832                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1833                         I915_READ(fdi_rx_reg);
1834                         udelay(200);
1835
1836                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1837                         temp = I915_READ(fdi_tx_reg);
1838                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1839                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1840                                 I915_READ(fdi_tx_reg);
1841                                 udelay(100);
1842                         }
1843                 }
1844
1845                 /* Enable panel fitting for LVDS */
1846                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1847                         temp = I915_READ(pf_ctl_reg);
1848                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1849
1850                         /* currently full aspect */
1851                         I915_WRITE(pf_win_pos, 0);
1852
1853                         I915_WRITE(pf_win_size,
1854                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1855                                    (dev_priv->panel_fixed_mode->vdisplay));
1856                 }
1857
1858                 /* Enable CPU pipe */
1859                 temp = I915_READ(pipeconf_reg);
1860                 if ((temp & PIPEACONF_ENABLE) == 0) {
1861                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1862                         I915_READ(pipeconf_reg);
1863                         udelay(100);
1864                 }
1865
1866                 /* configure and enable CPU plane */
1867                 temp = I915_READ(dspcntr_reg);
1868                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1869                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1870                         /* Flush the plane changes */
1871                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1872                 }
1873
1874                 if (!HAS_eDP) {
1875                         /* For PCH output, training FDI link */
1876                         if (IS_GEN6(dev))
1877                                 gen6_fdi_link_train(crtc);
1878                         else
1879                                 ironlake_fdi_link_train(crtc);
1880
1881                         /* enable PCH DPLL */
1882                         temp = I915_READ(pch_dpll_reg);
1883                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1884                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1885                                 I915_READ(pch_dpll_reg);
1886                         }
1887                         udelay(200);
1888
1889                         if (HAS_PCH_CPT(dev)) {
1890                                 /* Be sure PCH DPLL SEL is set */
1891                                 temp = I915_READ(PCH_DPLL_SEL);
1892                                 if (trans_dpll_sel == 0 &&
1893                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1894                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1895                                 else if (trans_dpll_sel == 1 &&
1896                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1897                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1898                                 I915_WRITE(PCH_DPLL_SEL, temp);
1899                                 I915_READ(PCH_DPLL_SEL);
1900                         }
1901
1902                         /* set transcoder timing */
1903                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1904                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1905                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1906
1907                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1908                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1909                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1910
1911                         /* enable normal train */
1912                         temp = I915_READ(fdi_tx_reg);
1913                         temp &= ~FDI_LINK_TRAIN_NONE;
1914                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1915                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1916                         I915_READ(fdi_tx_reg);
1917
1918                         temp = I915_READ(fdi_rx_reg);
1919                         if (HAS_PCH_CPT(dev)) {
1920                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1921                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1922                         } else {
1923                                 temp &= ~FDI_LINK_TRAIN_NONE;
1924                                 temp |= FDI_LINK_TRAIN_NONE;
1925                         }
1926                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1927                         I915_READ(fdi_rx_reg);
1928
1929                         /* wait one idle pattern time */
1930                         udelay(100);
1931
1932                         /* For PCH DP, enable TRANS_DP_CTL */
1933                         if (HAS_PCH_CPT(dev) &&
1934                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1935                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1936                                 int reg;
1937
1938                                 reg = I915_READ(trans_dp_ctl);
1939                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
1940                                 reg = TRANS_DP_OUTPUT_ENABLE |
1941                                       TRANS_DP_ENH_FRAMING |
1942                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
1943                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
1944
1945                                 switch (intel_trans_dp_port_sel(crtc)) {
1946                                 case PCH_DP_B:
1947                                         reg |= TRANS_DP_PORT_SEL_B;
1948                                         break;
1949                                 case PCH_DP_C:
1950                                         reg |= TRANS_DP_PORT_SEL_C;
1951                                         break;
1952                                 case PCH_DP_D:
1953                                         reg |= TRANS_DP_PORT_SEL_D;
1954                                         break;
1955                                 default:
1956                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1957                                         reg |= TRANS_DP_PORT_SEL_B;
1958                                         break;
1959                                 }
1960
1961                                 I915_WRITE(trans_dp_ctl, reg);
1962                                 POSTING_READ(trans_dp_ctl);
1963                         }
1964
1965                         /* enable PCH transcoder */
1966                         temp = I915_READ(transconf_reg);
1967                         /*
1968                          * make the BPC in transcoder be consistent with
1969                          * that in pipeconf reg.
1970                          */
1971                         temp &= ~PIPE_BPC_MASK;
1972                         temp |= pipe_bpc;
1973                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1974                         I915_READ(transconf_reg);
1975
1976                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1977                                 ;
1978
1979                 }
1980
1981                 intel_crtc_load_lut(crtc);
1982
1983         break;
1984         case DRM_MODE_DPMS_OFF:
1985                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1986
1987                 drm_vblank_off(dev, pipe);
1988                 /* Disable display plane */
1989                 temp = I915_READ(dspcntr_reg);
1990                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1991                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1992                         /* Flush the plane changes */
1993                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1994                         I915_READ(dspbase_reg);
1995                 }
1996
1997                 i915_disable_vga(dev);
1998
1999                 /* disable cpu pipe, disable after all planes disabled */
2000                 temp = I915_READ(pipeconf_reg);
2001                 if ((temp & PIPEACONF_ENABLE) != 0) {
2002                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2003                         I915_READ(pipeconf_reg);
2004                         n = 0;
2005                         /* wait for cpu pipe off, pipe state */
2006                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2007                                 n++;
2008                                 if (n < 60) {
2009                                         udelay(500);
2010                                         continue;
2011                                 } else {
2012                                         DRM_DEBUG_KMS("pipe %d off delay\n",
2013                                                                 pipe);
2014                                         break;
2015                                 }
2016                         }
2017                 } else
2018                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2019
2020                 udelay(100);
2021
2022                 /* Disable PF */
2023                 temp = I915_READ(pf_ctl_reg);
2024                 if ((temp & PF_ENABLE) != 0) {
2025                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2026                         I915_READ(pf_ctl_reg);
2027                 }
2028                 I915_WRITE(pf_win_size, 0);
2029                 POSTING_READ(pf_win_size);
2030
2031
2032                 /* disable CPU FDI tx and PCH FDI rx */
2033                 temp = I915_READ(fdi_tx_reg);
2034                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2035                 I915_READ(fdi_tx_reg);
2036
2037                 temp = I915_READ(fdi_rx_reg);
2038                 /* BPC in FDI rx is consistent with that in pipeconf */
2039                 temp &= ~(0x07 << 16);
2040                 temp |= (pipe_bpc << 11);
2041                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2042                 I915_READ(fdi_rx_reg);
2043
2044                 udelay(100);
2045
2046                 /* still set train pattern 1 */
2047                 temp = I915_READ(fdi_tx_reg);
2048                 temp &= ~FDI_LINK_TRAIN_NONE;
2049                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2050                 I915_WRITE(fdi_tx_reg, temp);
2051                 POSTING_READ(fdi_tx_reg);
2052
2053                 temp = I915_READ(fdi_rx_reg);
2054                 if (HAS_PCH_CPT(dev)) {
2055                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2056                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2057                 } else {
2058                         temp &= ~FDI_LINK_TRAIN_NONE;
2059                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2060                 }
2061                 I915_WRITE(fdi_rx_reg, temp);
2062                 POSTING_READ(fdi_rx_reg);
2063
2064                 udelay(100);
2065
2066                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2067                         temp = I915_READ(PCH_LVDS);
2068                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2069                         I915_READ(PCH_LVDS);
2070                         udelay(100);
2071                 }
2072
2073                 /* disable PCH transcoder */
2074                 temp = I915_READ(transconf_reg);
2075                 if ((temp & TRANS_ENABLE) != 0) {
2076                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2077                         I915_READ(transconf_reg);
2078                         n = 0;
2079                         /* wait for PCH transcoder off, transcoder state */
2080                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2081                                 n++;
2082                                 if (n < 60) {
2083                                         udelay(500);
2084                                         continue;
2085                                 } else {
2086                                         DRM_DEBUG_KMS("transcoder %d off "
2087                                                         "delay\n", pipe);
2088                                         break;
2089                                 }
2090                         }
2091                 }
2092
2093                 temp = I915_READ(transconf_reg);
2094                 /* BPC in transcoder is consistent with that in pipeconf */
2095                 temp &= ~PIPE_BPC_MASK;
2096                 temp |= pipe_bpc;
2097                 I915_WRITE(transconf_reg, temp);
2098                 I915_READ(transconf_reg);
2099                 udelay(100);
2100
2101                 if (HAS_PCH_CPT(dev)) {
2102                         /* disable TRANS_DP_CTL */
2103                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2104                         int reg;
2105
2106                         reg = I915_READ(trans_dp_ctl);
2107                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2108                         I915_WRITE(trans_dp_ctl, reg);
2109                         POSTING_READ(trans_dp_ctl);
2110
2111                         /* disable DPLL_SEL */
2112                         temp = I915_READ(PCH_DPLL_SEL);
2113                         if (trans_dpll_sel == 0)
2114                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2115                         else
2116                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2117                         I915_WRITE(PCH_DPLL_SEL, temp);
2118                         I915_READ(PCH_DPLL_SEL);
2119
2120                 }
2121
2122                 /* disable PCH DPLL */
2123                 temp = I915_READ(pch_dpll_reg);
2124                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2125                 I915_READ(pch_dpll_reg);
2126
2127                 if (HAS_eDP) {
2128                         ironlake_disable_pll_edp(crtc);
2129                 }
2130
2131                 /* Switch from PCDclk to Rawclk */
2132                 temp = I915_READ(fdi_rx_reg);
2133                 temp &= ~FDI_SEL_PCDCLK;
2134                 I915_WRITE(fdi_rx_reg, temp);
2135                 I915_READ(fdi_rx_reg);
2136
2137                 /* Disable CPU FDI TX PLL */
2138                 temp = I915_READ(fdi_tx_reg);
2139                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2140                 I915_READ(fdi_tx_reg);
2141                 udelay(100);
2142
2143                 temp = I915_READ(fdi_rx_reg);
2144                 temp &= ~FDI_RX_PLL_ENABLE;
2145                 I915_WRITE(fdi_rx_reg, temp);
2146                 I915_READ(fdi_rx_reg);
2147
2148                 /* Wait for the clocks to turn off. */
2149                 udelay(100);
2150                 break;
2151         }
2152 }
2153
2154 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2155 {
2156         struct intel_overlay *overlay;
2157         int ret;
2158
2159         if (!enable && intel_crtc->overlay) {
2160                 overlay = intel_crtc->overlay;
2161                 mutex_lock(&overlay->dev->struct_mutex);
2162                 for (;;) {
2163                         ret = intel_overlay_switch_off(overlay);
2164                         if (ret == 0)
2165                                 break;
2166
2167                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2168                         if (ret != 0) {
2169                                 /* overlay doesn't react anymore. Usually
2170                                  * results in a black screen and an unkillable
2171                                  * X server. */
2172                                 BUG();
2173                                 overlay->hw_wedged = HW_WEDGED;
2174                                 break;
2175                         }
2176                 }
2177                 mutex_unlock(&overlay->dev->struct_mutex);
2178         }
2179         /* Let userspace switch the overlay on again. In most cases userspace
2180          * has to recompute where to put it anyway. */
2181
2182         return;
2183 }
2184
2185 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2186 {
2187         struct drm_device *dev = crtc->dev;
2188         struct drm_i915_private *dev_priv = dev->dev_private;
2189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2190         int pipe = intel_crtc->pipe;
2191         int plane = intel_crtc->plane;
2192         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2193         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2194         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2195         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2196         u32 temp;
2197
2198         /* XXX: When our outputs are all unaware of DPMS modes other than off
2199          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2200          */
2201         switch (mode) {
2202         case DRM_MODE_DPMS_ON:
2203         case DRM_MODE_DPMS_STANDBY:
2204         case DRM_MODE_DPMS_SUSPEND:
2205                 intel_update_watermarks(dev);
2206
2207                 /* Enable the DPLL */
2208                 temp = I915_READ(dpll_reg);
2209                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2210                         I915_WRITE(dpll_reg, temp);
2211                         I915_READ(dpll_reg);
2212                         /* Wait for the clocks to stabilize. */
2213                         udelay(150);
2214                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2215                         I915_READ(dpll_reg);
2216                         /* Wait for the clocks to stabilize. */
2217                         udelay(150);
2218                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2219                         I915_READ(dpll_reg);
2220                         /* Wait for the clocks to stabilize. */
2221                         udelay(150);
2222                 }
2223
2224                 /* Enable the pipe */
2225                 temp = I915_READ(pipeconf_reg);
2226                 if ((temp & PIPEACONF_ENABLE) == 0)
2227                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2228
2229                 /* Enable the plane */
2230                 temp = I915_READ(dspcntr_reg);
2231                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2232                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2233                         /* Flush the plane changes */
2234                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2235                 }
2236
2237                 intel_crtc_load_lut(crtc);
2238
2239                 if ((IS_I965G(dev) || plane == 0))
2240                         intel_update_fbc(crtc, &crtc->mode);
2241
2242                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2243                 intel_crtc_dpms_overlay(intel_crtc, true);
2244         break;
2245         case DRM_MODE_DPMS_OFF:
2246                 intel_update_watermarks(dev);
2247
2248                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2249                 intel_crtc_dpms_overlay(intel_crtc, false);
2250                 drm_vblank_off(dev, pipe);
2251
2252                 if (dev_priv->cfb_plane == plane &&
2253                     dev_priv->display.disable_fbc)
2254                         dev_priv->display.disable_fbc(dev);
2255
2256                 /* Disable the VGA plane that we never use */
2257                 i915_disable_vga(dev);
2258
2259                 /* Disable display plane */
2260                 temp = I915_READ(dspcntr_reg);
2261                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2262                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2263                         /* Flush the plane changes */
2264                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2265                         I915_READ(dspbase_reg);
2266                 }
2267
2268                 if (!IS_I9XX(dev)) {
2269                         /* Wait for vblank for the disable to take effect */
2270                         intel_wait_for_vblank(dev);
2271                 }
2272
2273                 /* Don't disable pipe A or pipe A PLLs if needed */
2274                 if (pipeconf_reg == PIPEACONF &&
2275                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2276                         goto skip_pipe_off;
2277
2278                 /* Next, disable display pipes */
2279                 temp = I915_READ(pipeconf_reg);
2280                 if ((temp & PIPEACONF_ENABLE) != 0) {
2281                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2282                         I915_READ(pipeconf_reg);
2283                 }
2284
2285                 /* Wait for vblank for the disable to take effect. */
2286                 intel_wait_for_vblank(dev);
2287
2288                 temp = I915_READ(dpll_reg);
2289                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2290                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2291                         I915_READ(dpll_reg);
2292                 }
2293         skip_pipe_off:
2294                 /* Wait for the clocks to turn off. */
2295                 udelay(150);
2296                 break;
2297         }
2298 }
2299
2300 /**
2301  * Sets the power management mode of the pipe and plane.
2302  *
2303  * This code should probably grow support for turning the cursor off and back
2304  * on appropriately at the same time as we're turning the pipe off/on.
2305  */
2306 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2307 {
2308         struct drm_device *dev = crtc->dev;
2309         struct drm_i915_private *dev_priv = dev->dev_private;
2310         struct drm_i915_master_private *master_priv;
2311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2312         int pipe = intel_crtc->pipe;
2313         bool enabled;
2314
2315         dev_priv->display.dpms(crtc, mode);
2316
2317         intel_crtc->dpms_mode = mode;
2318
2319         if (!dev->primary->master)
2320                 return;
2321
2322         master_priv = dev->primary->master->driver_priv;
2323         if (!master_priv->sarea_priv)
2324                 return;
2325
2326         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2327
2328         switch (pipe) {
2329         case 0:
2330                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2331                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2332                 break;
2333         case 1:
2334                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2335                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2336                 break;
2337         default:
2338                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2339                 break;
2340         }
2341 }
2342
2343 static void intel_crtc_prepare (struct drm_crtc *crtc)
2344 {
2345         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2346         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2347 }
2348
2349 static void intel_crtc_commit (struct drm_crtc *crtc)
2350 {
2351         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2352         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2353 }
2354
2355 void intel_encoder_prepare (struct drm_encoder *encoder)
2356 {
2357         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2358         /* lvds has its own version of prepare see intel_lvds_prepare */
2359         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2360 }
2361
2362 void intel_encoder_commit (struct drm_encoder *encoder)
2363 {
2364         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2365         /* lvds has its own version of commit see intel_lvds_commit */
2366         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2367 }
2368
2369 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2370                                   struct drm_display_mode *mode,
2371                                   struct drm_display_mode *adjusted_mode)
2372 {
2373         struct drm_device *dev = crtc->dev;
2374         if (HAS_PCH_SPLIT(dev)) {
2375                 /* FDI link clock is fixed at 2.7G */
2376                 if (mode->clock * 3 > 27000 * 4)
2377                         return MODE_CLOCK_HIGH;
2378         }
2379         return true;
2380 }
2381
2382 static int i945_get_display_clock_speed(struct drm_device *dev)
2383 {
2384         return 400000;
2385 }
2386
2387 static int i915_get_display_clock_speed(struct drm_device *dev)
2388 {
2389         return 333000;
2390 }
2391
2392 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2393 {
2394         return 200000;
2395 }
2396
2397 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2398 {
2399         u16 gcfgc = 0;
2400
2401         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2402
2403         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2404                 return 133000;
2405         else {
2406                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2407                 case GC_DISPLAY_CLOCK_333_MHZ:
2408                         return 333000;
2409                 default:
2410                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2411                         return 190000;
2412                 }
2413         }
2414 }
2415
2416 static int i865_get_display_clock_speed(struct drm_device *dev)
2417 {
2418         return 266000;
2419 }
2420
2421 static int i855_get_display_clock_speed(struct drm_device *dev)
2422 {
2423         u16 hpllcc = 0;
2424         /* Assume that the hardware is in the high speed state.  This
2425          * should be the default.
2426          */
2427         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2428         case GC_CLOCK_133_200:
2429         case GC_CLOCK_100_200:
2430                 return 200000;
2431         case GC_CLOCK_166_250:
2432                 return 250000;
2433         case GC_CLOCK_100_133:
2434                 return 133000;
2435         }
2436
2437         /* Shouldn't happen */
2438         return 0;
2439 }
2440
2441 static int i830_get_display_clock_speed(struct drm_device *dev)
2442 {
2443         return 133000;
2444 }
2445
2446 /**
2447  * Return the pipe currently connected to the panel fitter,
2448  * or -1 if the panel fitter is not present or not in use
2449  */
2450 int intel_panel_fitter_pipe (struct drm_device *dev)
2451 {
2452         struct drm_i915_private *dev_priv = dev->dev_private;
2453         u32  pfit_control;
2454
2455         /* i830 doesn't have a panel fitter */
2456         if (IS_I830(dev))
2457                 return -1;
2458
2459         pfit_control = I915_READ(PFIT_CONTROL);
2460
2461         /* See if the panel fitter is in use */
2462         if ((pfit_control & PFIT_ENABLE) == 0)
2463                 return -1;
2464
2465         /* 965 can place panel fitter on either pipe */
2466         if (IS_I965G(dev))
2467                 return (pfit_control >> 29) & 0x3;
2468
2469         /* older chips can only use pipe 1 */
2470         return 1;
2471 }
2472
2473 struct fdi_m_n {
2474         u32        tu;
2475         u32        gmch_m;
2476         u32        gmch_n;
2477         u32        link_m;
2478         u32        link_n;
2479 };
2480
2481 static void
2482 fdi_reduce_ratio(u32 *num, u32 *den)
2483 {
2484         while (*num > 0xffffff || *den > 0xffffff) {
2485                 *num >>= 1;
2486                 *den >>= 1;
2487         }
2488 }
2489
2490 #define DATA_N 0x800000
2491 #define LINK_N 0x80000
2492
2493 static void
2494 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2495                      int link_clock, struct fdi_m_n *m_n)
2496 {
2497         u64 temp;
2498
2499         m_n->tu = 64; /* default size */
2500
2501         temp = (u64) DATA_N * pixel_clock;
2502         temp = div_u64(temp, link_clock);
2503         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2504         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2505         m_n->gmch_n = DATA_N;
2506         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2507
2508         temp = (u64) LINK_N * pixel_clock;
2509         m_n->link_m = div_u64(temp, link_clock);
2510         m_n->link_n = LINK_N;
2511         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2512 }
2513
2514
2515 struct intel_watermark_params {
2516         unsigned long fifo_size;
2517         unsigned long max_wm;
2518         unsigned long default_wm;
2519         unsigned long guard_size;
2520         unsigned long cacheline_size;
2521 };
2522
2523 /* Pineview has different values for various configs */
2524 static struct intel_watermark_params pineview_display_wm = {
2525         PINEVIEW_DISPLAY_FIFO,
2526         PINEVIEW_MAX_WM,
2527         PINEVIEW_DFT_WM,
2528         PINEVIEW_GUARD_WM,
2529         PINEVIEW_FIFO_LINE_SIZE
2530 };
2531 static struct intel_watermark_params pineview_display_hplloff_wm = {
2532         PINEVIEW_DISPLAY_FIFO,
2533         PINEVIEW_MAX_WM,
2534         PINEVIEW_DFT_HPLLOFF_WM,
2535         PINEVIEW_GUARD_WM,
2536         PINEVIEW_FIFO_LINE_SIZE
2537 };
2538 static struct intel_watermark_params pineview_cursor_wm = {
2539         PINEVIEW_CURSOR_FIFO,
2540         PINEVIEW_CURSOR_MAX_WM,
2541         PINEVIEW_CURSOR_DFT_WM,
2542         PINEVIEW_CURSOR_GUARD_WM,
2543         PINEVIEW_FIFO_LINE_SIZE,
2544 };
2545 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2546         PINEVIEW_CURSOR_FIFO,
2547         PINEVIEW_CURSOR_MAX_WM,
2548         PINEVIEW_CURSOR_DFT_WM,
2549         PINEVIEW_CURSOR_GUARD_WM,
2550         PINEVIEW_FIFO_LINE_SIZE
2551 };
2552 static struct intel_watermark_params g4x_wm_info = {
2553         G4X_FIFO_SIZE,
2554         G4X_MAX_WM,
2555         G4X_MAX_WM,
2556         2,
2557         G4X_FIFO_LINE_SIZE,
2558 };
2559 static struct intel_watermark_params i945_wm_info = {
2560         I945_FIFO_SIZE,
2561         I915_MAX_WM,
2562         1,
2563         2,
2564         I915_FIFO_LINE_SIZE
2565 };
2566 static struct intel_watermark_params i915_wm_info = {
2567         I915_FIFO_SIZE,
2568         I915_MAX_WM,
2569         1,
2570         2,
2571         I915_FIFO_LINE_SIZE
2572 };
2573 static struct intel_watermark_params i855_wm_info = {
2574         I855GM_FIFO_SIZE,
2575         I915_MAX_WM,
2576         1,
2577         2,
2578         I830_FIFO_LINE_SIZE
2579 };
2580 static struct intel_watermark_params i830_wm_info = {
2581         I830_FIFO_SIZE,
2582         I915_MAX_WM,
2583         1,
2584         2,
2585         I830_FIFO_LINE_SIZE
2586 };
2587
2588 static struct intel_watermark_params ironlake_display_wm_info = {
2589         ILK_DISPLAY_FIFO,
2590         ILK_DISPLAY_MAXWM,
2591         ILK_DISPLAY_DFTWM,
2592         2,
2593         ILK_FIFO_LINE_SIZE
2594 };
2595
2596 static struct intel_watermark_params ironlake_display_srwm_info = {
2597         ILK_DISPLAY_SR_FIFO,
2598         ILK_DISPLAY_MAX_SRWM,
2599         ILK_DISPLAY_DFT_SRWM,
2600         2,
2601         ILK_FIFO_LINE_SIZE
2602 };
2603
2604 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2605         ILK_CURSOR_SR_FIFO,
2606         ILK_CURSOR_MAX_SRWM,
2607         ILK_CURSOR_DFT_SRWM,
2608         2,
2609         ILK_FIFO_LINE_SIZE
2610 };
2611
2612 /**
2613  * intel_calculate_wm - calculate watermark level
2614  * @clock_in_khz: pixel clock
2615  * @wm: chip FIFO params
2616  * @pixel_size: display pixel size
2617  * @latency_ns: memory latency for the platform
2618  *
2619  * Calculate the watermark level (the level at which the display plane will
2620  * start fetching from memory again).  Each chip has a different display
2621  * FIFO size and allocation, so the caller needs to figure that out and pass
2622  * in the correct intel_watermark_params structure.
2623  *
2624  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2625  * on the pixel size.  When it reaches the watermark level, it'll start
2626  * fetching FIFO line sized based chunks from memory until the FIFO fills
2627  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2628  * will occur, and a display engine hang could result.
2629  */
2630 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2631                                         struct intel_watermark_params *wm,
2632                                         int pixel_size,
2633                                         unsigned long latency_ns)
2634 {
2635         long entries_required, wm_size;
2636
2637         /*
2638          * Note: we need to make sure we don't overflow for various clock &
2639          * latency values.
2640          * clocks go from a few thousand to several hundred thousand.
2641          * latency is usually a few thousand
2642          */
2643         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2644                 1000;
2645         entries_required /= wm->cacheline_size;
2646
2647         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2648
2649         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2650
2651         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2652
2653         /* Don't promote wm_size to unsigned... */
2654         if (wm_size > (long)wm->max_wm)
2655                 wm_size = wm->max_wm;
2656         if (wm_size <= 0)
2657                 wm_size = wm->default_wm;
2658         return wm_size;
2659 }
2660
2661 struct cxsr_latency {
2662         int is_desktop;
2663         int is_ddr3;
2664         unsigned long fsb_freq;
2665         unsigned long mem_freq;
2666         unsigned long display_sr;
2667         unsigned long display_hpll_disable;
2668         unsigned long cursor_sr;
2669         unsigned long cursor_hpll_disable;
2670 };
2671
2672 static struct cxsr_latency cxsr_latency_table[] = {
2673         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2674         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2675         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2676         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2677         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2678
2679         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2680         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2681         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2682         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2683         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2684
2685         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2686         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2687         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2688         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2689         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2690
2691         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2692         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2693         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2694         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2695         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2696
2697         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2698         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2699         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2700         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2701         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2702
2703         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2704         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2705         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2706         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2707         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2708 };
2709
2710 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3, 
2711                                                    int fsb, int mem)
2712 {
2713         int i;
2714         struct cxsr_latency *latency;
2715
2716         if (fsb == 0 || mem == 0)
2717                 return NULL;
2718
2719         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2720                 latency = &cxsr_latency_table[i];
2721                 if (is_desktop == latency->is_desktop &&
2722                     is_ddr3 == latency->is_ddr3 &&
2723                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2724                         return latency;
2725         }
2726
2727         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2728
2729         return NULL;
2730 }
2731
2732 static void pineview_disable_cxsr(struct drm_device *dev)
2733 {
2734         struct drm_i915_private *dev_priv = dev->dev_private;
2735         u32 reg;
2736
2737         /* deactivate cxsr */
2738         reg = I915_READ(DSPFW3);
2739         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2740         I915_WRITE(DSPFW3, reg);
2741         DRM_INFO("Big FIFO is disabled\n");
2742 }
2743
2744 /*
2745  * Latency for FIFO fetches is dependent on several factors:
2746  *   - memory configuration (speed, channels)
2747  *   - chipset
2748  *   - current MCH state
2749  * It can be fairly high in some situations, so here we assume a fairly
2750  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2751  * set this value too high, the FIFO will fetch frequently to stay full)
2752  * and power consumption (set it too low to save power and we might see
2753  * FIFO underruns and display "flicker").
2754  *
2755  * A value of 5us seems to be a good balance; safe for very low end
2756  * platforms but not overly aggressive on lower latency configs.
2757  */
2758 static const int latency_ns = 5000;
2759
2760 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2761 {
2762         struct drm_i915_private *dev_priv = dev->dev_private;
2763         uint32_t dsparb = I915_READ(DSPARB);
2764         int size;
2765
2766         if (plane == 0)
2767                 size = dsparb & 0x7f;
2768         else
2769                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2770                         (dsparb & 0x7f);
2771
2772         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2773                         plane ? "B" : "A", size);
2774
2775         return size;
2776 }
2777
2778 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2779 {
2780         struct drm_i915_private *dev_priv = dev->dev_private;
2781         uint32_t dsparb = I915_READ(DSPARB);
2782         int size;
2783
2784         if (plane == 0)
2785                 size = dsparb & 0x1ff;
2786         else
2787                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2788                         (dsparb & 0x1ff);
2789         size >>= 1; /* Convert to cachelines */
2790
2791         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2792                         plane ? "B" : "A", size);
2793
2794         return size;
2795 }
2796
2797 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2798 {
2799         struct drm_i915_private *dev_priv = dev->dev_private;
2800         uint32_t dsparb = I915_READ(DSPARB);
2801         int size;
2802
2803         size = dsparb & 0x7f;
2804         size >>= 2; /* Convert to cachelines */
2805
2806         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2807                         plane ? "B" : "A",
2808                   size);
2809
2810         return size;
2811 }
2812
2813 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2814 {
2815         struct drm_i915_private *dev_priv = dev->dev_private;
2816         uint32_t dsparb = I915_READ(DSPARB);
2817         int size;
2818
2819         size = dsparb & 0x7f;
2820         size >>= 1; /* Convert to cachelines */
2821
2822         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2823                         plane ? "B" : "A", size);
2824
2825         return size;
2826 }
2827
2828 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2829                           int planeb_clock, int sr_hdisplay, int pixel_size)
2830 {
2831         struct drm_i915_private *dev_priv = dev->dev_private;
2832         u32 reg;
2833         unsigned long wm;
2834         struct cxsr_latency *latency;
2835         int sr_clock;
2836
2837         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 
2838                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2839         if (!latency) {
2840                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2841                 pineview_disable_cxsr(dev);
2842                 return;
2843         }
2844
2845         if (!planea_clock || !planeb_clock) {
2846                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2847
2848                 /* Display SR */
2849                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2850                                         pixel_size, latency->display_sr);
2851                 reg = I915_READ(DSPFW1);
2852                 reg &= ~DSPFW_SR_MASK;
2853                 reg |= wm << DSPFW_SR_SHIFT;
2854                 I915_WRITE(DSPFW1, reg);
2855                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2856
2857                 /* cursor SR */
2858                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2859                                         pixel_size, latency->cursor_sr);
2860                 reg = I915_READ(DSPFW3);
2861                 reg &= ~DSPFW_CURSOR_SR_MASK;
2862                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2863                 I915_WRITE(DSPFW3, reg);
2864
2865                 /* Display HPLL off SR */
2866                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2867                                         pixel_size, latency->display_hpll_disable);
2868                 reg = I915_READ(DSPFW3);
2869                 reg &= ~DSPFW_HPLL_SR_MASK;
2870                 reg |= wm & DSPFW_HPLL_SR_MASK;
2871                 I915_WRITE(DSPFW3, reg);
2872
2873                 /* cursor HPLL off SR */
2874                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2875                                         pixel_size, latency->cursor_hpll_disable);
2876                 reg = I915_READ(DSPFW3);
2877                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2878                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2879                 I915_WRITE(DSPFW3, reg);
2880                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2881
2882                 /* activate cxsr */
2883                 reg = I915_READ(DSPFW3);
2884                 reg |= PINEVIEW_SELF_REFRESH_EN;
2885                 I915_WRITE(DSPFW3, reg);
2886                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2887         } else {
2888                 pineview_disable_cxsr(dev);
2889                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2890         }
2891 }
2892
2893 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2894                           int planeb_clock, int sr_hdisplay, int pixel_size)
2895 {
2896         struct drm_i915_private *dev_priv = dev->dev_private;
2897         int total_size, cacheline_size;
2898         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2899         struct intel_watermark_params planea_params, planeb_params;
2900         unsigned long line_time_us;
2901         int sr_clock, sr_entries = 0, entries_required;
2902
2903         /* Create copies of the base settings for each pipe */
2904         planea_params = planeb_params = g4x_wm_info;
2905
2906         /* Grab a couple of global values before we overwrite them */
2907         total_size = planea_params.fifo_size;
2908         cacheline_size = planea_params.cacheline_size;
2909
2910         /*
2911          * Note: we need to make sure we don't overflow for various clock &
2912          * latency values.
2913          * clocks go from a few thousand to several hundred thousand.
2914          * latency is usually a few thousand
2915          */
2916         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2917                 1000;
2918         entries_required /= G4X_FIFO_LINE_SIZE;
2919         planea_wm = entries_required + planea_params.guard_size;
2920
2921         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2922                 1000;
2923         entries_required /= G4X_FIFO_LINE_SIZE;
2924         planeb_wm = entries_required + planeb_params.guard_size;
2925
2926         cursora_wm = cursorb_wm = 16;
2927         cursor_sr = 32;
2928
2929         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2930
2931         /* Calc sr entries for one plane configs */
2932         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2933                 /* self-refresh has much higher latency */
2934                 static const int sr_latency_ns = 12000;
2935
2936                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2937                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2938
2939                 /* Use ns/us then divide to preserve precision */
2940                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2941                               pixel_size * sr_hdisplay) / 1000;
2942                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2943                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2944                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2945         } else {
2946                 /* Turn off self refresh if both pipes are enabled */
2947                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2948                                         & ~FW_BLC_SELF_EN);
2949         }
2950
2951         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2952                   planea_wm, planeb_wm, sr_entries);
2953
2954         planea_wm &= 0x3f;
2955         planeb_wm &= 0x3f;
2956
2957         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2958                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2959                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2960         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2961                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2962         /* HPLL off in SR has some issues on G4x... disable it */
2963         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2964                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2965 }
2966
2967 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2968                            int planeb_clock, int sr_hdisplay, int pixel_size)
2969 {
2970         struct drm_i915_private *dev_priv = dev->dev_private;
2971         unsigned long line_time_us;
2972         int sr_clock, sr_entries, srwm = 1;
2973
2974         /* Calc sr entries for one plane configs */
2975         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2976                 /* self-refresh has much higher latency */
2977                 static const int sr_latency_ns = 12000;
2978
2979                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2980                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2981
2982                 /* Use ns/us then divide to preserve precision */
2983                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2984                               pixel_size * sr_hdisplay) / 1000;
2985                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2986                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2987                 srwm = I945_FIFO_SIZE - sr_entries;
2988                 if (srwm < 0)
2989                         srwm = 1;
2990                 srwm &= 0x3f;
2991                 if (IS_I965GM(dev))
2992                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2993         } else {
2994                 /* Turn off self refresh if both pipes are enabled */
2995                 if (IS_I965GM(dev))
2996                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2997                                    & ~FW_BLC_SELF_EN);
2998         }
2999
3000         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3001                       srwm);
3002
3003         /* 965 has limitations... */
3004         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3005                    (8 << 0));
3006         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3007 }
3008
3009 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3010                            int planeb_clock, int sr_hdisplay, int pixel_size)
3011 {
3012         struct drm_i915_private *dev_priv = dev->dev_private;
3013         uint32_t fwater_lo;
3014         uint32_t fwater_hi;
3015         int total_size, cacheline_size, cwm, srwm = 1;
3016         int planea_wm, planeb_wm;
3017         struct intel_watermark_params planea_params, planeb_params;
3018         unsigned long line_time_us;
3019         int sr_clock, sr_entries = 0;
3020
3021         /* Create copies of the base settings for each pipe */
3022         if (IS_I965GM(dev) || IS_I945GM(dev))
3023                 planea_params = planeb_params = i945_wm_info;
3024         else if (IS_I9XX(dev))
3025                 planea_params = planeb_params = i915_wm_info;
3026         else
3027                 planea_params = planeb_params = i855_wm_info;
3028
3029         /* Grab a couple of global values before we overwrite them */
3030         total_size = planea_params.fifo_size;
3031         cacheline_size = planea_params.cacheline_size;
3032
3033         /* Update per-plane FIFO sizes */
3034         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3035         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3036
3037         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3038                                        pixel_size, latency_ns);
3039         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3040                                        pixel_size, latency_ns);
3041         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3042
3043         /*
3044          * Overlay gets an aggressive default since video jitter is bad.
3045          */
3046         cwm = 2;
3047
3048         /* Calc sr entries for one plane configs */
3049         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3050             (!planea_clock || !planeb_clock)) {
3051                 /* self-refresh has much higher latency */
3052                 static const int sr_latency_ns = 6000;
3053
3054                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3055                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3056
3057                 /* Use ns/us then divide to preserve precision */
3058                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3059                               pixel_size * sr_hdisplay) / 1000;
3060                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3061                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3062                 srwm = total_size - sr_entries;
3063                 if (srwm < 0)
3064                         srwm = 1;
3065
3066                 if (IS_I945G(dev) || IS_I945GM(dev))
3067                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3068                 else if (IS_I915GM(dev)) {
3069                         /* 915M has a smaller SRWM field */
3070                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3071                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3072                 }
3073         } else {
3074                 /* Turn off self refresh if both pipes are enabled */
3075                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3076                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3077                                    & ~FW_BLC_SELF_EN);
3078                 } else if (IS_I915GM(dev)) {
3079                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3080                 }
3081         }
3082
3083         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3084                   planea_wm, planeb_wm, cwm, srwm);
3085
3086         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3087         fwater_hi = (cwm & 0x1f);
3088
3089         /* Set request length to 8 cachelines per fetch */
3090         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3091         fwater_hi = fwater_hi | (1 << 8);
3092
3093         I915_WRITE(FW_BLC, fwater_lo);
3094         I915_WRITE(FW_BLC2, fwater_hi);
3095 }
3096
3097 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3098                            int unused2, int pixel_size)
3099 {
3100         struct drm_i915_private *dev_priv = dev->dev_private;
3101         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3102         int planea_wm;
3103
3104         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3105
3106         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3107                                        pixel_size, latency_ns);
3108         fwater_lo |= (3<<8) | planea_wm;
3109
3110         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3111
3112         I915_WRITE(FW_BLC, fwater_lo);
3113 }
3114
3115 #define ILK_LP0_PLANE_LATENCY           700
3116
3117 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3118                        int planeb_clock, int sr_hdisplay, int pixel_size)
3119 {
3120         struct drm_i915_private *dev_priv = dev->dev_private;
3121         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3122         int sr_wm, cursor_wm;
3123         unsigned long line_time_us;
3124         int sr_clock, entries_required;
3125         u32 reg_value;
3126
3127         /* Calculate and update the watermark for plane A */
3128         if (planea_clock) {
3129                 entries_required = ((planea_clock / 1000) * pixel_size *
3130                                      ILK_LP0_PLANE_LATENCY) / 1000;
3131                 entries_required = DIV_ROUND_UP(entries_required,
3132                                    ironlake_display_wm_info.cacheline_size);
3133                 planea_wm = entries_required +
3134                             ironlake_display_wm_info.guard_size;
3135
3136                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3137                         planea_wm = ironlake_display_wm_info.max_wm;
3138
3139                 cursora_wm = 16;
3140                 reg_value = I915_READ(WM0_PIPEA_ILK);
3141                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3142                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3143                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3144                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3145                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3146                                 "cursor: %d\n", planea_wm, cursora_wm);
3147         }
3148         /* Calculate and update the watermark for plane B */
3149         if (planeb_clock) {
3150                 entries_required = ((planeb_clock / 1000) * pixel_size *
3151                                      ILK_LP0_PLANE_LATENCY) / 1000;
3152                 entries_required = DIV_ROUND_UP(entries_required,
3153                                    ironlake_display_wm_info.cacheline_size);
3154                 planeb_wm = entries_required +
3155                             ironlake_display_wm_info.guard_size;
3156
3157                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3158                         planeb_wm = ironlake_display_wm_info.max_wm;
3159
3160                 cursorb_wm = 16;
3161                 reg_value = I915_READ(WM0_PIPEB_ILK);
3162                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3163                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3164                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3165                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3166                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3167                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3168         }
3169
3170         /*
3171          * Calculate and update the self-refresh watermark only when one
3172          * display plane is used.
3173          */
3174         if (!planea_clock || !planeb_clock) {
3175                 int line_count;
3176                 /* Read the self-refresh latency. The unit is 0.5us */
3177                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3178
3179                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3180                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3181
3182                 /* Use ns/us then divide to preserve precision */
3183                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3184                                / 1000;
3185
3186                 /* calculate the self-refresh watermark for display plane */
3187                 entries_required = line_count * sr_hdisplay * pixel_size;
3188                 entries_required = DIV_ROUND_UP(entries_required,
3189                                    ironlake_display_srwm_info.cacheline_size);
3190                 sr_wm = entries_required +
3191                         ironlake_display_srwm_info.guard_size;
3192
3193                 /* calculate the self-refresh watermark for display cursor */
3194                 entries_required = line_count * pixel_size * 64;
3195                 entries_required = DIV_ROUND_UP(entries_required,
3196                                    ironlake_cursor_srwm_info.cacheline_size);
3197                 cursor_wm = entries_required +
3198                             ironlake_cursor_srwm_info.guard_size;
3199
3200                 /* configure watermark and enable self-refresh */
3201                 reg_value = I915_READ(WM1_LP_ILK);
3202                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3203                                WM1_LP_CURSOR_MASK);
3204                 reg_value |= WM1_LP_SR_EN |
3205                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3206                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3207
3208                 I915_WRITE(WM1_LP_ILK, reg_value);
3209                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3210                                 "cursor %d\n", sr_wm, cursor_wm);
3211
3212         } else {
3213                 /* Turn off self refresh if both pipes are enabled */
3214                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3215         }
3216 }
3217 /**
3218  * intel_update_watermarks - update FIFO watermark values based on current modes
3219  *
3220  * Calculate watermark values for the various WM regs based on current mode
3221  * and plane configuration.
3222  *
3223  * There are several cases to deal with here:
3224  *   - normal (i.e. non-self-refresh)
3225  *   - self-refresh (SR) mode
3226  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3227  *   - lines are small relative to FIFO size (buffer can hold more than 2
3228  *     lines), so need to account for TLB latency
3229  *
3230  *   The normal calculation is:
3231  *     watermark = dotclock * bytes per pixel * latency
3232  *   where latency is platform & configuration dependent (we assume pessimal
3233  *   values here).
3234  *
3235  *   The SR calculation is:
3236  *     watermark = (trunc(latency/line time)+1) * surface width *
3237  *       bytes per pixel
3238  *   where
3239  *     line time = htotal / dotclock
3240  *   and latency is assumed to be high, as above.
3241  *
3242  * The final value programmed to the register should always be rounded up,
3243  * and include an extra 2 entries to account for clock crossings.
3244  *
3245  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3246  * to set the non-SR watermarks to 8.
3247   */
3248 static void intel_update_watermarks(struct drm_device *dev)
3249 {
3250         struct drm_i915_private *dev_priv = dev->dev_private;
3251         struct drm_crtc *crtc;
3252         struct intel_crtc *intel_crtc;
3253         int sr_hdisplay = 0;
3254         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3255         int enabled = 0, pixel_size = 0;
3256
3257         if (!dev_priv->display.update_wm)
3258                 return;
3259
3260         /* Get the clock config from both planes */
3261         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3262                 intel_crtc = to_intel_crtc(crtc);
3263                 if (crtc->enabled) {
3264                         enabled++;
3265                         if (intel_crtc->plane == 0) {
3266                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3267                                           intel_crtc->pipe, crtc->mode.clock);
3268                                 planea_clock = crtc->mode.clock;
3269                         } else {
3270                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3271                                           intel_crtc->pipe, crtc->mode.clock);
3272                                 planeb_clock = crtc->mode.clock;
3273                         }
3274                         sr_hdisplay = crtc->mode.hdisplay;
3275                         sr_clock = crtc->mode.clock;
3276                         if (crtc->fb)
3277                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3278                         else
3279                                 pixel_size = 4; /* by default */
3280                 }
3281         }
3282
3283         if (enabled <= 0)
3284                 return;
3285
3286         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3287                                     sr_hdisplay, pixel_size);
3288 }
3289
3290 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3291                                struct drm_display_mode *mode,
3292                                struct drm_display_mode *adjusted_mode,
3293                                int x, int y,
3294                                struct drm_framebuffer *old_fb)
3295 {
3296         struct drm_device *dev = crtc->dev;
3297         struct drm_i915_private *dev_priv = dev->dev_private;
3298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3299         int pipe = intel_crtc->pipe;
3300         int plane = intel_crtc->plane;
3301         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3302         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3303         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3304         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3305         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3306         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3307         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3308         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3309         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3310         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3311         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3312         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3313         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3314         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3315         int refclk, num_connectors = 0;
3316         intel_clock_t clock, reduced_clock;
3317         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3318         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3319         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3320         bool is_edp = false;
3321         struct drm_mode_config *mode_config = &dev->mode_config;
3322         struct drm_encoder *encoder;
3323         struct intel_encoder *intel_encoder = NULL;
3324         const intel_limit_t *limit;
3325         int ret;
3326         struct fdi_m_n m_n = {0};
3327         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3328         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3329         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3330         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3331         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3332         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3333         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3334         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3335         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3336         int lvds_reg = LVDS;
3337         u32 temp;
3338         int sdvo_pixel_multiply;
3339         int target_clock;
3340
3341         drm_vblank_pre_modeset(dev, pipe);
3342
3343         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3344
3345                 if (!encoder || encoder->crtc != crtc)
3346                         continue;
3347
3348                 intel_encoder = enc_to_intel_encoder(encoder);
3349
3350                 switch (intel_encoder->type) {
3351                 case INTEL_OUTPUT_LVDS:
3352                         is_lvds = true;
3353                         break;
3354                 case INTEL_OUTPUT_SDVO:
3355                 case INTEL_OUTPUT_HDMI:
3356                         is_sdvo = true;
3357                         if (intel_encoder->needs_tv_clock)
3358                                 is_tv = true;
3359                         break;
3360                 case INTEL_OUTPUT_DVO:
3361                         is_dvo = true;
3362                         break;
3363                 case INTEL_OUTPUT_TVOUT:
3364                         is_tv = true;
3365                         break;
3366                 case INTEL_OUTPUT_ANALOG:
3367                         is_crt = true;
3368                         break;
3369                 case INTEL_OUTPUT_DISPLAYPORT:
3370                         is_dp = true;
3371                         break;
3372                 case INTEL_OUTPUT_EDP:
3373                         is_edp = true;
3374                         break;
3375                 }
3376
3377                 num_connectors++;
3378         }
3379
3380         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3381                 refclk = dev_priv->lvds_ssc_freq * 1000;
3382                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3383                                         refclk / 1000);
3384         } else if (IS_I9XX(dev)) {
3385                 refclk = 96000;
3386                 if (HAS_PCH_SPLIT(dev))
3387                         refclk = 120000; /* 120Mhz refclk */
3388         } else {
3389                 refclk = 48000;
3390         }
3391         
3392
3393         /*
3394          * Returns a set of divisors for the desired target clock with the given
3395          * refclk, or FALSE.  The returned values represent the clock equation:
3396          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3397          */
3398         limit = intel_limit(crtc);
3399         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3400         if (!ok) {
3401                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3402                 drm_vblank_post_modeset(dev, pipe);
3403                 return -EINVAL;
3404         }
3405
3406         if (is_lvds && dev_priv->lvds_downclock_avail) {
3407                 has_reduced_clock = limit->find_pll(limit, crtc,
3408                                                             dev_priv->lvds_downclock,
3409                                                             refclk,
3410                                                             &reduced_clock);
3411                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3412