drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  35 };
  36
  37 static const u8 index_to_dp_signal_levels[] = {
  38         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  39         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  40         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  41         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  42         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  43         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  44         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  45         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  46         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  47         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  48 };
  49
  50 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  51  * them for both DP and FDI transports, allowing those ports to
  52  * automatically adapt to HDMI connections as well
  53  */
  54 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  55         { 0x00FFFFFF, 0x0006000E, 0x0 },
  56         { 0x00D75FFF, 0x0005000A, 0x0 },
  57         { 0x00C30FFF, 0x00040006, 0x0 },
  58         { 0x80AAAFFF, 0x000B0000, 0x0 },
  59         { 0x00FFFFFF, 0x0005000A, 0x0 },
  60         { 0x00D75FFF, 0x000C0004, 0x0 },
  61         { 0x80C30FFF, 0x000B0000, 0x0 },
  62         { 0x00FFFFFF, 0x00040006, 0x0 },
  63         { 0x80D75FFF, 0x000B0000, 0x0 },
  64 };
  65
  66 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  67         { 0x00FFFFFF, 0x0007000E, 0x0 },
  68         { 0x00D75FFF, 0x000F000A, 0x0 },
  69         { 0x00C30FFF, 0x00060006, 0x0 },
  70         { 0x00AAAFFF, 0x001E0000, 0x0 },
  71         { 0x00FFFFFF, 0x000F000A, 0x0 },
  72         { 0x00D75FFF, 0x00160004, 0x0 },
  73         { 0x00C30FFF, 0x001E0000, 0x0 },
  74         { 0x00FFFFFF, 0x00060006, 0x0 },
  75         { 0x00D75FFF, 0x001E0000, 0x0 },
  76 };
  77
  78 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  79                                         /* Idx  NT mV d T mV d  db      */
  80         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  81         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  82         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  83         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  84         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  85         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  86         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  87         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  88         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  89         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  90         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  91         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  92 };
  93
  94 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  95         { 0x00FFFFFF, 0x00000012, 0x0 },
  96         { 0x00EBAFFF, 0x00020011, 0x0 },
  97         { 0x00C71FFF, 0x0006000F, 0x0 },
  98         { 0x00AAAFFF, 0x000E000A, 0x0 },
  99         { 0x00FFFFFF, 0x00020011, 0x0 },
 100         { 0x00DB6FFF, 0x0005000F, 0x0 },
 101         { 0x00BEEFFF, 0x000A000C, 0x0 },
 102         { 0x00FFFFFF, 0x0005000F, 0x0 },
 103         { 0x00DB6FFF, 0x000A000C, 0x0 },
 104 };
 105
 106 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 107         { 0x00FFFFFF, 0x0007000E, 0x0 },
 108         { 0x00D75FFF, 0x000E000A, 0x0 },
 109         { 0x00BEFFFF, 0x00140006, 0x0 },
 110         { 0x80B2CFFF, 0x001B0002, 0x0 },
 111         { 0x00FFFFFF, 0x000E000A, 0x0 },
 112         { 0x00DB6FFF, 0x00160005, 0x0 },
 113         { 0x80C71FFF, 0x001A0002, 0x0 },
 114         { 0x00F7DFFF, 0x00180004, 0x0 },
 115         { 0x80D75FFF, 0x001B0002, 0x0 },
 116 };
 117
 118 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 119         { 0x00FFFFFF, 0x0001000E, 0x0 },
 120         { 0x00D75FFF, 0x0004000A, 0x0 },
 121         { 0x00C30FFF, 0x00070006, 0x0 },
 122         { 0x00AAAFFF, 0x000C0000, 0x0 },
 123         { 0x00FFFFFF, 0x0004000A, 0x0 },
 124         { 0x00D75FFF, 0x00090004, 0x0 },
 125         { 0x00C30FFF, 0x000C0000, 0x0 },
 126         { 0x00FFFFFF, 0x00070006, 0x0 },
 127         { 0x00D75FFF, 0x000C0000, 0x0 },
 128 };
 129
 130 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 131                                         /* Idx  NT mV d T mV df db      */
 132         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 133         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 134         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 135         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 136         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 137         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 138         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 139         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 140         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 141         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 142 };
 143
 144 /* Skylake H and S */
 145 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 146         { 0x00002016, 0x000000A0, 0x0 },
 147         { 0x00005012, 0x0000009B, 0x0 },
 148         { 0x00007011, 0x00000088, 0x0 },
 149         { 0x80009010, 0x000000C0, 0x1 },
 150         { 0x00002016, 0x0000009B, 0x0 },
 151         { 0x00005012, 0x00000088, 0x0 },
 152         { 0x80007011, 0x000000C0, 0x1 },
 153         { 0x00002016, 0x000000DF, 0x0 },
 154         { 0x80005012, 0x000000C0, 0x1 },
 155 };
 156
 157 /* Skylake U */
 158 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 159         { 0x0000201B, 0x000000A2, 0x0 },
 160         { 0x00005012, 0x00000088, 0x0 },
 161         { 0x80007011, 0x000000CD, 0x1 },
 162         { 0x80009010, 0x000000C0, 0x1 },
 163         { 0x0000201B, 0x0000009D, 0x0 },
 164         { 0x80005012, 0x000000C0, 0x1 },
 165         { 0x80007011, 0x000000C0, 0x1 },
 166         { 0x00002016, 0x00000088, 0x0 },
 167         { 0x80005012, 0x000000C0, 0x1 },
 168 };
 169
 170 /* Skylake Y */
 171 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 172         { 0x00000018, 0x000000A2, 0x0 },
 173         { 0x00005012, 0x00000088, 0x0 },
 174         { 0x80007011, 0x000000CD, 0x3 },
 175         { 0x80009010, 0x000000C0, 0x3 },
 176         { 0x00000018, 0x0000009D, 0x0 },
 177         { 0x80005012, 0x000000C0, 0x3 },
 178         { 0x80007011, 0x000000C0, 0x3 },
 179         { 0x00000018, 0x00000088, 0x0 },
 180         { 0x80005012, 0x000000C0, 0x3 },
 181 };
 182
 183 /* Kabylake H and S */
 184 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 185         { 0x00002016, 0x000000A0, 0x0 },
 186         { 0x00005012, 0x0000009B, 0x0 },
 187         { 0x00007011, 0x00000088, 0x0 },
 188         { 0x80009010, 0x000000C0, 0x1 },
 189         { 0x00002016, 0x0000009B, 0x0 },
 190         { 0x00005012, 0x00000088, 0x0 },
 191         { 0x80007011, 0x000000C0, 0x1 },
 192         { 0x00002016, 0x00000097, 0x0 },
 193         { 0x80005012, 0x000000C0, 0x1 },
 194 };
 195
 196 /* Kabylake U */
 197 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 198         { 0x0000201B, 0x000000A1, 0x0 },
 199         { 0x00005012, 0x00000088, 0x0 },
 200         { 0x80007011, 0x000000CD, 0x3 },
 201         { 0x80009010, 0x000000C0, 0x3 },
 202         { 0x0000201B, 0x0000009D, 0x0 },
 203         { 0x80005012, 0x000000C0, 0x3 },
 204         { 0x80007011, 0x000000C0, 0x3 },
 205         { 0x00002016, 0x0000004F, 0x0 },
 206         { 0x80005012, 0x000000C0, 0x3 },
 207 };
 208
 209 /* Kabylake Y */
 210 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 211         { 0x00001017, 0x000000A1, 0x0 },
 212         { 0x00005012, 0x00000088, 0x0 },
 213         { 0x80007011, 0x000000CD, 0x3 },
 214         { 0x8000800F, 0x000000C0, 0x3 },
 215         { 0x00001017, 0x0000009D, 0x0 },
 216         { 0x80005012, 0x000000C0, 0x3 },
 217         { 0x80007011, 0x000000C0, 0x3 },
 218         { 0x00001017, 0x0000004C, 0x0 },
 219         { 0x80005012, 0x000000C0, 0x3 },
 220 };
 221
 222 /*
 223  * Skylake/Kabylake H and S
 224  * eDP 1.4 low vswing translation parameters
 225  */
 226 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 227         { 0x00000018, 0x000000A8, 0x0 },
 228         { 0x00004013, 0x000000A9, 0x0 },
 229         { 0x00007011, 0x000000A2, 0x0 },
 230         { 0x00009010, 0x0000009C, 0x0 },
 231         { 0x00000018, 0x000000A9, 0x0 },
 232         { 0x00006013, 0x000000A2, 0x0 },
 233         { 0x00007011, 0x000000A6, 0x0 },
 234         { 0x00000018, 0x000000AB, 0x0 },
 235         { 0x00007013, 0x0000009F, 0x0 },
 236         { 0x00000018, 0x000000DF, 0x0 },
 237 };
 238
 239 /*
 240  * Skylake/Kabylake U
 241  * eDP 1.4 low vswing translation parameters
 242  */
 243 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 244         { 0x00000018, 0x000000A8, 0x0 },
 245         { 0x00004013, 0x000000A9, 0x0 },
 246         { 0x00007011, 0x000000A2, 0x0 },
 247         { 0x00009010, 0x0000009C, 0x0 },
 248         { 0x00000018, 0x000000A9, 0x0 },
 249         { 0x00006013, 0x000000A2, 0x0 },
 250         { 0x00007011, 0x000000A6, 0x0 },
 251         { 0x00002016, 0x000000AB, 0x0 },
 252         { 0x00005013, 0x0000009F, 0x0 },
 253         { 0x00000018, 0x000000DF, 0x0 },
 254 };
 255
 256 /*
 257  * Skylake/Kabylake Y
 258  * eDP 1.4 low vswing translation parameters
 259  */
 260 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 261         { 0x00000018, 0x000000A8, 0x0 },
 262         { 0x00004013, 0x000000AB, 0x0 },
 263         { 0x00007011, 0x000000A4, 0x0 },
 264         { 0x00009010, 0x000000DF, 0x0 },
 265         { 0x00000018, 0x000000AA, 0x0 },
 266         { 0x00006013, 0x000000A4, 0x0 },
 267         { 0x00007011, 0x0000009D, 0x0 },
 268         { 0x00000018, 0x000000A0, 0x0 },
 269         { 0x00006012, 0x000000DF, 0x0 },
 270         { 0x00000018, 0x0000008A, 0x0 },
 271 };
 272
 273 /* Skylake/Kabylake U, H and S */
 274 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 275         { 0x00000018, 0x000000AC, 0x0 },
 276         { 0x00005012, 0x0000009D, 0x0 },
 277         { 0x00007011, 0x00000088, 0x0 },
 278         { 0x00000018, 0x000000A1, 0x0 },
 279         { 0x00000018, 0x00000098, 0x0 },
 280         { 0x00004013, 0x00000088, 0x0 },
 281         { 0x80006012, 0x000000CD, 0x1 },
 282         { 0x00000018, 0x000000DF, 0x0 },
 283         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 284         { 0x80003015, 0x000000C0, 0x1 },
 285         { 0x80000018, 0x000000C0, 0x1 },
 286 };
 287
 288 /* Skylake/Kabylake Y */
 289 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 290         { 0x00000018, 0x000000A1, 0x0 },
 291         { 0x00005012, 0x000000DF, 0x0 },
 292         { 0x80007011, 0x000000CB, 0x3 },
 293         { 0x00000018, 0x000000A4, 0x0 },
 294         { 0x00000018, 0x0000009D, 0x0 },
 295         { 0x00004013, 0x00000080, 0x0 },
 296         { 0x80006013, 0x000000C0, 0x3 },
 297         { 0x00000018, 0x0000008A, 0x0 },
 298         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 299         { 0x80003015, 0x000000C0, 0x3 },
 300         { 0x80000018, 0x000000C0, 0x3 },
 301 };
 302
 303 struct bxt_ddi_buf_trans {
 304         u32 margin;     /* swing value */
 305         u32 scale;      /* scale value */
 306         u32 enable;     /* scale enable */
 307         u32 deemphasis;
 308         bool default_index; /* true if the entry represents default value */
 309 };
 310
 311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 312                                         /* Idx  NT mV diff      db  */
 313         { 52,  0x9A, 0, 128, true  },   /* 0:   400             0   */
 314         { 78,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 315         { 104, 0x9A, 0, 64,  false },   /* 2:   400             6   */
 316         { 154, 0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 317         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 318         { 116, 0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 319         { 154, 0x9A, 0, 64,  false },   /* 6:   600             6   */
 320         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 321         { 154, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 322         { 154, 0x9A, 1, 128, false },   /* 9:   1200            0   */
 323 };
 324
 325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 326                                         /* Idx  NT mV diff      db  */
 327         { 26, 0, 0, 128, false },       /* 0:   200             0   */
 328         { 38, 0, 0, 112, false },       /* 1:   200             1.5 */
 329         { 48, 0, 0, 96,  false },       /* 2:   200             4   */
 330         { 54, 0, 0, 69,  false },       /* 3:   200             6   */
 331         { 32, 0, 0, 128, false },       /* 4:   250             0   */
 332         { 48, 0, 0, 104, false },       /* 5:   250             1.5 */
 333         { 54, 0, 0, 85,  false },       /* 6:   250             4   */
 334         { 43, 0, 0, 128, false },       /* 7:   300             0   */
 335         { 54, 0, 0, 101, false },       /* 8:   300             1.5 */
 336         { 48, 0, 0, 128, false },       /* 9:   300             0   */
 337 };
 338
 339 /* BSpec has 2 recommended values - entries 0 and 8.
 340  * Using the entry with higher vswing.
 341  */
 342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 343                                         /* Idx  NT mV diff      db  */
 344         { 52,  0x9A, 0, 128, false },   /* 0:   400             0   */
 345         { 52,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 346         { 52,  0x9A, 0, 64,  false },   /* 2:   400             6   */
 347         { 42,  0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 348         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 349         { 77,  0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 350         { 77,  0x9A, 0, 64,  false },   /* 6:   600             6   */
 351         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 352         { 102, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 353         { 154, 0x9A, 1, 128, true },    /* 9:   1200            0   */
 354 };
 355
 356 struct cnl_ddi_buf_trans {
 357         u32 dw2_swing_sel;
 358         u32 dw7_n_scalar;
 359         u32 dw4_cursor_coeff;
 360         u32 dw4_post_cursor_2;
 361         u32 dw4_post_cursor_1;
 362 };
 363
 364 /* Voltage Swing Programming for VccIO 0.85V for DP */
 365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 366                                                 /* NT mV Trans mV db    */
 367         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 368         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 369         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 370         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 371         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 372         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 373         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 374         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 375         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 376         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 377 };
 378
 379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 381                                                 /* NT mV Trans mV db    */
 382         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 383         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 384         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 385         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 386         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 387         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 388         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 389 };
 390
 391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 393                                                 /* NT mV Trans mV db    */
 394         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 395         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 396         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 397         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 398         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 399         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 400         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 401         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 402         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 403 };
 404
 405 /* Voltage Swing Programming for VccIO 0.95V for DP */
 406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 407                                                 /* NT mV Trans mV db    */
 408         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 409         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 410         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 411         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 412         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 413         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 414         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 415         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 416         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 417         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 418 };
 419
 420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 422                                                 /* NT mV Trans mV db    */
 423         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 425         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 426         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 427         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 428         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 429         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 430         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 431         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 432         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 433         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 434 };
 435
 436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 438                                                 /* NT mV Trans mV db    */
 439         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 440         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 441         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 442         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 443         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 444         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 445         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 446         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 447         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 448         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 449 };
 450
 451 /* Voltage Swing Programming for VccIO 1.05V for DP */
 452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 453                                                 /* NT mV Trans mV db    */
 454         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 455         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 456         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 457         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 458         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 459         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 460         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 461         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 462         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 463         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 464 };
 465
 466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 468                                                 /* NT mV Trans mV db    */
 469         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 471         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 472         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 473         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 474         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 475         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 476         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 477         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 478         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 479         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 480 };
 481
 482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 484                                                 /* NT mV Trans mV db    */
 485         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 486         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 487         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 488         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 489         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 490         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 491         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 492         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 493         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 494 };
 495
 496 enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
 497 {
 498         switch (encoder->type) {
 499         case INTEL_OUTPUT_DP_MST:
 500                 return enc_to_mst(&encoder->base)->primary->port;
 501         case INTEL_OUTPUT_DP:
 502         case INTEL_OUTPUT_EDP:
 503         case INTEL_OUTPUT_HDMI:
 504         case INTEL_OUTPUT_UNKNOWN:
 505                 return enc_to_dig_port(&encoder->base)->port;
 506         case INTEL_OUTPUT_ANALOG:
 507                 return PORT_E;
 508         default:
 509                 MISSING_CASE(encoder->type);
 510                 return PORT_A;
 511         }
 512 }
 513
 514 static const struct ddi_buf_trans *
 515 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 516 {
 517         if (dev_priv->vbt.edp.low_vswing) {
 518                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 519                 return bdw_ddi_translations_edp;
 520         } else {
 521                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 522                 return bdw_ddi_translations_dp;
 523         }
 524 }
 525
 526 static const struct ddi_buf_trans *
 527 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 528 {
 529         if (IS_SKL_ULX(dev_priv)) {
 530                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 531                 return skl_y_ddi_translations_dp;
 532         } else if (IS_SKL_ULT(dev_priv)) {
 533                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 534                 return skl_u_ddi_translations_dp;
 535         } else {
 536                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 537                 return skl_ddi_translations_dp;
 538         }
 539 }
 540
 541 static const struct ddi_buf_trans *
 542 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 543 {
 544         if (IS_KBL_ULX(dev_priv)) {
 545                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 546                 return kbl_y_ddi_translations_dp;
 547         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 548                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 549                 return kbl_u_ddi_translations_dp;
 550         } else {
 551                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 552                 return kbl_ddi_translations_dp;
 553         }
 554 }
 555
 556 static const struct ddi_buf_trans *
 557 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 558 {
 559         if (dev_priv->vbt.edp.low_vswing) {
 560                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 561                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 562                         return skl_y_ddi_translations_edp;
 563                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 564                            IS_CFL_ULT(dev_priv)) {
 565                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 566                         return skl_u_ddi_translations_edp;
 567                 } else {
 568                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 569                         return skl_ddi_translations_edp;
 570                 }
 571         }
 572
 573         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 574                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 575         else
 576                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 577 }
 578
 579 static const struct ddi_buf_trans *
 580 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 581 {
 582         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 583                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 584                 return skl_y_ddi_translations_hdmi;
 585         } else {
 586                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 587                 return skl_ddi_translations_hdmi;
 588         }
 589 }
 590
 591 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 592 {
 593         int n_hdmi_entries;
 594         int hdmi_level;
 595         int hdmi_default_entry;
 596
 597         hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 598
 599         if (IS_GEN9_LP(dev_priv))
 600                 return hdmi_level;
 601
 602         if (IS_GEN9_BC(dev_priv)) {
 603                 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 604                 hdmi_default_entry = 8;
 605         } else if (IS_BROADWELL(dev_priv)) {
 606                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 607                 hdmi_default_entry = 7;
 608         } else if (IS_HASWELL(dev_priv)) {
 609                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 610                 hdmi_default_entry = 6;
 611         } else {
 612                 WARN(1, "ddi translation table missing\n");
 613                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 614                 hdmi_default_entry = 7;
 615         }
 616
 617         /* Choose a good default if VBT is badly populated */
 618         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 619             hdmi_level >= n_hdmi_entries)
 620                 hdmi_level = hdmi_default_entry;
 621
 622         return hdmi_level;
 623 }
 624
 625 static const struct ddi_buf_trans *
 626 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 627                            int *n_entries)
 628 {
 629         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 630                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 631         } else if (IS_SKYLAKE(dev_priv)) {
 632                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 633         } else if (IS_BROADWELL(dev_priv)) {
 634                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 635                 return  bdw_ddi_translations_dp;
 636         } else if (IS_HASWELL(dev_priv)) {
 637                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 638                 return hsw_ddi_translations_dp;
 639         }
 640
 641         *n_entries = 0;
 642         return NULL;
 643 }
 644
 645 static const struct ddi_buf_trans *
 646 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 647                             int *n_entries)
 648 {
 649         if (IS_GEN9_BC(dev_priv)) {
 650                 return skl_get_buf_trans_edp(dev_priv, n_entries);
 651         } else if (IS_BROADWELL(dev_priv)) {
 652                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 653         } else if (IS_HASWELL(dev_priv)) {
 654                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 655                 return hsw_ddi_translations_dp;
 656         }
 657
 658         *n_entries = 0;
 659         return NULL;
 660 }
 661
 662 static const struct ddi_buf_trans *
 663 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 664                             int *n_entries)
 665 {
 666         if (IS_BROADWELL(dev_priv)) {
 667                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 668                 return hsw_ddi_translations_fdi;
 669         } else if (IS_HASWELL(dev_priv)) {
 670                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 671                 return hsw_ddi_translations_fdi;
 672         }
 673
 674         *n_entries = 0;
 675         return NULL;
 676 }
 677
 678 /*
 679  * Starting with Haswell, DDI port buffers must be programmed with correct
 680  * values in advance. This function programs the correct values for
 681  * DP/eDP/FDI use cases.
 682  */
 683 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
 684 {
 685         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 686         u32 iboost_bit = 0;
 687         int i, n_entries;
 688         enum port port = intel_ddi_get_encoder_port(encoder);
 689         const struct ddi_buf_trans *ddi_translations;
 690
 691         if (IS_GEN9_LP(dev_priv))
 692                 return;
 693
 694         switch (encoder->type) {
 695         case INTEL_OUTPUT_EDP:
 696                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
 697                                                                &n_entries);
 698                 break;
 699         case INTEL_OUTPUT_DP:
 700                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
 701                                                               &n_entries);
 702                 break;
 703         case INTEL_OUTPUT_ANALOG:
 704                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 705                                                                &n_entries);
 706                 break;
 707         default:
 708                 MISSING_CASE(encoder->type);
 709                 return;
 710         }
 711
 712         if (IS_GEN9_BC(dev_priv)) {
 713                 /* If we're boosting the current, set bit 31 of trans1 */
 714                 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 715                         iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 716
 717                 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
 718                             port != PORT_A && port != PORT_E &&
 719                             n_entries > 9))
 720                         n_entries = 9;
 721         }
 722
 723         for (i = 0; i < n_entries; i++) {
 724                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 725                            ddi_translations[i].trans1 | iboost_bit);
 726                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 727                            ddi_translations[i].trans2);
 728         }
 729 }
 730
 731 /*
 732  * Starting with Haswell, DDI port buffers must be programmed with correct
 733  * values in advance. This function programs the correct values for
 734  * HDMI/DVI use cases.
 735  */
 736 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
 737 {
 738         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 739         u32 iboost_bit = 0;
 740         int n_hdmi_entries, hdmi_level;
 741         enum port port = intel_ddi_get_encoder_port(encoder);
 742         const struct ddi_buf_trans *ddi_translations_hdmi;
 743
 744         if (IS_GEN9_LP(dev_priv))
 745                 return;
 746
 747         hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
 748
 749         if (IS_GEN9_BC(dev_priv)) {
 750                 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 751
 752                 /* If we're boosting the current, set bit 31 of trans1 */
 753                 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 754                         iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 755         } else if (IS_BROADWELL(dev_priv)) {
 756                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 757                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 758         } else if (IS_HASWELL(dev_priv)) {
 759                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 760                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 761         } else {
 762                 WARN(1, "ddi translation table missing\n");
 763                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 764                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 765         }
 766
 767         /* Entry 9 is for HDMI: */
 768         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 769                    ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
 770         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 771                    ddi_translations_hdmi[hdmi_level].trans2);
 772 }
 773
 774 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 775                                     enum port port)
 776 {
 777         i915_reg_t reg = DDI_BUF_CTL(port);
 778         int i;
 779
 780         for (i = 0; i < 16; i++) {
 781                 udelay(1);
 782                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 783                         return;
 784         }
 785         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 786 }
 787
 788 static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
 789 {
 790         switch (pll->id) {
 791         case DPLL_ID_WRPLL1:
 792                 return PORT_CLK_SEL_WRPLL1;
 793         case DPLL_ID_WRPLL2:
 794                 return PORT_CLK_SEL_WRPLL2;
 795         case DPLL_ID_SPLL:
 796                 return PORT_CLK_SEL_SPLL;
 797         case DPLL_ID_LCPLL_810:
 798                 return PORT_CLK_SEL_LCPLL_810;
 799         case DPLL_ID_LCPLL_1350:
 800                 return PORT_CLK_SEL_LCPLL_1350;
 801         case DPLL_ID_LCPLL_2700:
 802                 return PORT_CLK_SEL_LCPLL_2700;
 803         default:
 804                 MISSING_CASE(pll->id);
 805                 return PORT_CLK_SEL_NONE;
 806         }
 807 }
 808
 809 /* Starting with Haswell, different DDI ports can work in FDI mode for
 810  * connection to the PCH-located connectors. For this, it is necessary to train
 811  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 812  *
 813  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 814  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 815  * DDI A (which is used for eDP)
 816  */
 817
 818 void hsw_fdi_link_train(struct intel_crtc *crtc,
 819                         const struct intel_crtc_state *crtc_state)
 820 {
 821         struct drm_device *dev = crtc->base.dev;
 822         struct drm_i915_private *dev_priv = to_i915(dev);
 823         struct intel_encoder *encoder;
 824         u32 temp, i, rx_ctl_val, ddi_pll_sel;
 825
 826         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
 827                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
 828                 intel_prepare_dp_ddi_buffers(encoder);
 829         }
 830
 831         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 832          * mode set "sequence for CRT port" document:
 833          * - TP1 to TP2 time with the default value
 834          * - FDI delay to 90h
 835          *
 836          * WaFDIAutoLinkSetTimingOverrride:hsw
 837          */
 838         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
 839                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 840                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 841
 842         /* Enable the PCH Receiver FDI PLL */
 843         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 844                      FDI_RX_PLL_ENABLE |
 845                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
 846         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 847         POSTING_READ(FDI_RX_CTL(PIPE_A));
 848         udelay(220);
 849
 850         /* Switch from Rawclk to PCDclk */
 851         rx_ctl_val |= FDI_PCDCLK;
 852         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 853
 854         /* Configure Port Clock Select */
 855         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
 856         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
 857         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
 858
 859         /* Start the training iterating through available voltages and emphasis,
 860          * testing each value twice. */
 861         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 862                 /* Configure DP_TP_CTL with auto-training */
 863                 I915_WRITE(DP_TP_CTL(PORT_E),
 864                                         DP_TP_CTL_FDI_AUTOTRAIN |
 865                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 866                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 867                                         DP_TP_CTL_ENABLE);
 868
 869                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 870                  * DDI E does not support port reversal, the functionality is
 871                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 872                  * port reversal bit */
 873                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 874                            DDI_BUF_CTL_ENABLE |
 875                            ((crtc_state->fdi_lanes - 1) << 1) |
 876                            DDI_BUF_TRANS_SELECT(i / 2));
 877                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 878
 879                 udelay(600);
 880
 881                 /* Program PCH FDI Receiver TU */
 882                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
 883
 884                 /* Enable PCH FDI Receiver with auto-training */
 885                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 886                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 887                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 888
 889                 /* Wait for FDI receiver lane calibration */
 890                 udelay(30);
 891
 892                 /* Unset FDI_RX_MISC pwrdn lanes */
 893                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 894                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 895                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 896                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 897
 898                 /* Wait for FDI auto training time */
 899                 udelay(5);
 900
 901                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 902                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 903                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 904                         break;
 905                 }
 906
 907                 /*
 908                  * Leave things enabled even if we failed to train FDI.
 909                  * Results in less fireworks from the state checker.
 910                  */
 911                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
 912                         DRM_ERROR("FDI link training failed!\n");
 913                         break;
 914                 }
 915
 916                 rx_ctl_val &= ~FDI_RX_ENABLE;
 917                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 918                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 919
 920                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 921                 temp &= ~DDI_BUF_CTL_ENABLE;
 922                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 923                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 924
 925                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 926                 temp = I915_READ(DP_TP_CTL(PORT_E));
 927                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 928                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 929                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 930                 POSTING_READ(DP_TP_CTL(PORT_E));
 931
 932                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 933
 934                 /* Reset FDI_RX_MISC pwrdn lanes */
 935                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 936                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 937                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 938                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 939                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 940         }
 941
 942         /* Enable normal pixel sending for FDI */
 943         I915_WRITE(DP_TP_CTL(PORT_E),
 944                    DP_TP_CTL_FDI_AUTOTRAIN |
 945                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 946                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 947                    DP_TP_CTL_ENABLE);
 948 }
 949
 950 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 951 {
 952         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 953         struct intel_digital_port *intel_dig_port =
 954                 enc_to_dig_port(&encoder->base);
 955
 956         intel_dp->DP = intel_dig_port->saved_port_bits |
 957                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 958         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 959 }
 960
 961 static struct intel_encoder *
 962 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
 963 {
 964         struct drm_device *dev = crtc->base.dev;
 965         struct intel_encoder *encoder, *ret = NULL;
 966         int num_encoders = 0;
 967
 968         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
 969                 ret = encoder;
 970                 num_encoders++;
 971         }
 972
 973         if (num_encoders != 1)
 974                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 975                      pipe_name(crtc->pipe));
 976
 977         BUG_ON(ret == NULL);
 978         return ret;
 979 }
 980
 981 /* Finds the only possible encoder associated with the given CRTC. */
 982 struct intel_encoder *
 983 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
 984 {
 985         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 986         struct intel_encoder *ret = NULL;
 987         struct drm_atomic_state *state;
 988         struct drm_connector *connector;
 989         struct drm_connector_state *connector_state;
 990         int num_encoders = 0;
 991         int i;
 992
 993         state = crtc_state->base.state;
 994
 995         for_each_new_connector_in_state(state, connector, connector_state, i) {
 996                 if (connector_state->crtc != crtc_state->base.crtc)
 997                         continue;
 998
 999                 ret = to_intel_encoder(connector_state->best_encoder);
1000                 num_encoders++;
1001         }
1002
1003         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1004              pipe_name(crtc->pipe));
1005
1006         BUG_ON(ret == NULL);
1007         return ret;
1008 }
1009
1010 #define LC_FREQ 2700
1011
1012 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1013                                    i915_reg_t reg)
1014 {
1015         int refclk = LC_FREQ;
1016         int n, p, r;
1017         u32 wrpll;
1018
1019         wrpll = I915_READ(reg);
1020         switch (wrpll & WRPLL_PLL_REF_MASK) {
1021         case WRPLL_PLL_SSC:
1022         case WRPLL_PLL_NON_SSC:
1023                 /*
1024                  * We could calculate spread here, but our checking
1025                  * code only cares about 5% accuracy, and spread is a max of
1026                  * 0.5% downspread.
1027                  */
1028                 refclk = 135;
1029                 break;
1030         case WRPLL_PLL_LCPLL:
1031                 refclk = LC_FREQ;
1032                 break;
1033         default:
1034                 WARN(1, "bad wrpll refclk\n");
1035                 return 0;
1036         }
1037
1038         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1039         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1040         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1041
1042         /* Convert to KHz, p & r have a fixed point portion */
1043         return (refclk * n * 100) / (p * r);
1044 }
1045
1046 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1047                                uint32_t dpll)
1048 {
1049         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1050         uint32_t cfgcr1_val, cfgcr2_val;
1051         uint32_t p0, p1, p2, dco_freq;
1052
1053         cfgcr1_reg = DPLL_CFGCR1(dpll);
1054         cfgcr2_reg = DPLL_CFGCR2(dpll);
1055
1056         cfgcr1_val = I915_READ(cfgcr1_reg);
1057         cfgcr2_val = I915_READ(cfgcr2_reg);
1058
1059         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1060         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1061
1062         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1063                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1064         else
1065                 p1 = 1;
1066
1067
1068         switch (p0) {
1069         case DPLL_CFGCR2_PDIV_1:
1070                 p0 = 1;
1071                 break;
1072         case DPLL_CFGCR2_PDIV_2:
1073                 p0 = 2;
1074                 break;
1075         case DPLL_CFGCR2_PDIV_3:
1076                 p0 = 3;
1077                 break;
1078         case DPLL_CFGCR2_PDIV_7:
1079                 p0 = 7;
1080                 break;
1081         }
1082
1083         switch (p2) {
1084         case DPLL_CFGCR2_KDIV_5:
1085                 p2 = 5;
1086                 break;
1087         case DPLL_CFGCR2_KDIV_2:
1088                 p2 = 2;
1089                 break;
1090         case DPLL_CFGCR2_KDIV_3:
1091                 p2 = 3;
1092                 break;
1093         case DPLL_CFGCR2_KDIV_1:
1094                 p2 = 1;
1095                 break;
1096         }
1097
1098         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1099
1100         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1101                 1000) / 0x8000;
1102
1103         return dco_freq / (p0 * p1 * p2 * 5);
1104 }
1105
1106 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1107 {
1108         int dotclock;
1109
1110         if (pipe_config->has_pch_encoder)
1111                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1112                                                     &pipe_config->fdi_m_n);
1113         else if (intel_crtc_has_dp_encoder(pipe_config))
1114                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1115                                                     &pipe_config->dp_m_n);
1116         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1117                 dotclock = pipe_config->port_clock * 2 / 3;
1118         else
1119                 dotclock = pipe_config->port_clock;
1120
1121         if (pipe_config->pixel_multiplier)
1122                 dotclock /= pipe_config->pixel_multiplier;
1123
1124         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1125 }
1126
1127 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1128                                 struct intel_crtc_state *pipe_config)
1129 {
1130         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1131         int link_clock = 0;
1132         uint32_t dpll_ctl1, dpll;
1133
1134         dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1135
1136         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1137
1138         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1139                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1140         } else {
1141                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1142                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1143
1144                 switch (link_clock) {
1145                 case DPLL_CTRL1_LINK_RATE_810:
1146                         link_clock = 81000;
1147                         break;
1148                 case DPLL_CTRL1_LINK_RATE_1080:
1149                         link_clock = 108000;
1150                         break;
1151                 case DPLL_CTRL1_LINK_RATE_1350:
1152                         link_clock = 135000;
1153                         break;
1154                 case DPLL_CTRL1_LINK_RATE_1620:
1155                         link_clock = 162000;
1156                         break;
1157                 case DPLL_CTRL1_LINK_RATE_2160:
1158                         link_clock = 216000;
1159                         break;
1160                 case DPLL_CTRL1_LINK_RATE_2700:
1161                         link_clock = 270000;
1162                         break;
1163                 default:
1164                         WARN(1, "Unsupported link rate\n");
1165                         break;
1166                 }
1167                 link_clock *= 2;
1168         }
1169
1170         pipe_config->port_clock = link_clock;
1171
1172         ddi_dotclock_get(pipe_config);
1173 }
1174
1175 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1176                               struct intel_crtc_state *pipe_config)
1177 {
1178         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1179         int link_clock = 0;
1180         u32 val, pll;
1181
1182         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1183         switch (val & PORT_CLK_SEL_MASK) {
1184         case PORT_CLK_SEL_LCPLL_810:
1185                 link_clock = 81000;
1186                 break;
1187         case PORT_CLK_SEL_LCPLL_1350:
1188                 link_clock = 135000;
1189                 break;
1190         case PORT_CLK_SEL_LCPLL_2700:
1191                 link_clock = 270000;
1192                 break;
1193         case PORT_CLK_SEL_WRPLL1:
1194                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1195                 break;
1196         case PORT_CLK_SEL_WRPLL2:
1197                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1198                 break;
1199         case PORT_CLK_SEL_SPLL:
1200                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1201                 if (pll == SPLL_PLL_FREQ_810MHz)
1202                         link_clock = 81000;
1203                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1204                         link_clock = 135000;
1205                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1206                         link_clock = 270000;
1207                 else {
1208                         WARN(1, "bad spll freq\n");
1209                         return;
1210                 }
1211                 break;
1212         default:
1213                 WARN(1, "bad port clock sel\n");
1214                 return;
1215         }
1216
1217         pipe_config->port_clock = link_clock * 2;
1218
1219         ddi_dotclock_get(pipe_config);
1220 }
1221
1222 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1223                                 enum intel_dpll_id dpll)
1224 {
1225         struct intel_shared_dpll *pll;
1226         struct intel_dpll_hw_state *state;
1227         struct dpll clock;
1228
1229         /* For DDI ports we always use a shared PLL. */
1230         if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1231                 return 0;
1232
1233         pll = &dev_priv->shared_dplls[dpll];
1234         state = &pll->state.hw_state;
1235
1236         clock.m1 = 2;
1237         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1238         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1239                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1240         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1241         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1242         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1243
1244         return chv_calc_dpll_params(100000, &clock);
1245 }
1246
1247 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1248                                 struct intel_crtc_state *pipe_config)
1249 {
1250         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1251         enum port port = intel_ddi_get_encoder_port(encoder);
1252         uint32_t dpll = port;
1253
1254         pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1255
1256         ddi_dotclock_get(pipe_config);
1257 }
1258
1259 void intel_ddi_clock_get(struct intel_encoder *encoder,
1260                          struct intel_crtc_state *pipe_config)
1261 {
1262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1263
1264         if (INTEL_GEN(dev_priv) <= 8)
1265                 hsw_ddi_clock_get(encoder, pipe_config);
1266         else if (IS_GEN9_BC(dev_priv))
1267                 skl_ddi_clock_get(encoder, pipe_config);
1268         else if (IS_GEN9_LP(dev_priv))
1269                 bxt_ddi_clock_get(encoder, pipe_config);
1270 }
1271
1272 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1273 {
1274         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1275         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1276         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1277         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1278         int type = encoder->type;
1279         uint32_t temp;
1280
1281         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1282                 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1283
1284                 temp = TRANS_MSA_SYNC_CLK;
1285                 switch (crtc_state->pipe_bpp) {
1286                 case 18:
1287                         temp |= TRANS_MSA_6_BPC;
1288                         break;
1289                 case 24:
1290                         temp |= TRANS_MSA_8_BPC;
1291                         break;
1292                 case 30:
1293                         temp |= TRANS_MSA_10_BPC;
1294                         break;
1295                 case 36:
1296                         temp |= TRANS_MSA_12_BPC;
1297                         break;
1298                 default:
1299                         BUG();
1300                 }
1301                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1302         }
1303 }
1304
1305 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1306                                     bool state)
1307 {
1308         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1309         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1310         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1311         uint32_t temp;
1312         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1313         if (state == true)
1314                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1315         else
1316                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1317         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1318 }
1319
1320 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1321 {
1322         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1323         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1324         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1325         enum pipe pipe = crtc->pipe;
1326         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1327         enum port port = intel_ddi_get_encoder_port(encoder);
1328         int type = encoder->type;
1329         uint32_t temp;
1330
1331         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1332         temp = TRANS_DDI_FUNC_ENABLE;
1333         temp |= TRANS_DDI_SELECT_PORT(port);
1334
1335         switch (crtc_state->pipe_bpp) {
1336         case 18:
1337                 temp |= TRANS_DDI_BPC_6;
1338                 break;
1339         case 24:
1340                 temp |= TRANS_DDI_BPC_8;
1341                 break;
1342         case 30:
1343                 temp |= TRANS_DDI_BPC_10;
1344                 break;
1345         case 36:
1346                 temp |= TRANS_DDI_BPC_12;
1347                 break;
1348         default:
1349                 BUG();
1350         }
1351
1352         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1353                 temp |= TRANS_DDI_PVSYNC;
1354         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1355                 temp |= TRANS_DDI_PHSYNC;
1356
1357         if (cpu_transcoder == TRANSCODER_EDP) {
1358                 switch (pipe) {
1359                 case PIPE_A:
1360                         /* On Haswell, can only use the always-on power well for
1361                          * eDP when not using the panel fitter, and when not
1362                          * using motion blur mitigation (which we don't
1363                          * support). */
1364                         if (IS_HASWELL(dev_priv) &&
1365                             (crtc_state->pch_pfit.enabled ||
1366                              crtc_state->pch_pfit.force_thru))
1367                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1368                         else
1369                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1370                         break;
1371                 case PIPE_B:
1372                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1373                         break;
1374                 case PIPE_C:
1375                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1376                         break;
1377                 default:
1378                         BUG();
1379                         break;
1380                 }
1381         }
1382
1383         if (type == INTEL_OUTPUT_HDMI) {
1384                 if (crtc_state->has_hdmi_sink)
1385                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1386                 else
1387                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1388
1389                 if (crtc_state->hdmi_scrambling)
1390                         temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1391                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1392                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1393         } else if (type == INTEL_OUTPUT_ANALOG) {
1394                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1395                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1396         } else if (type == INTEL_OUTPUT_DP ||
1397                    type == INTEL_OUTPUT_EDP) {
1398                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1399                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1400         } else if (type == INTEL_OUTPUT_DP_MST) {
1401                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1402                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1403         } else {
1404                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1405                      encoder->type, pipe_name(pipe));
1406         }
1407
1408         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1409 }
1410
1411 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1412                                        enum transcoder cpu_transcoder)
1413 {
1414         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1415         uint32_t val = I915_READ(reg);
1416
1417         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1418         val |= TRANS_DDI_PORT_NONE;
1419         I915_WRITE(reg, val);
1420 }
1421
1422 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1423 {
1424         struct drm_device *dev = intel_connector->base.dev;
1425         struct drm_i915_private *dev_priv = to_i915(dev);
1426         struct intel_encoder *encoder = intel_connector->encoder;
1427         int type = intel_connector->base.connector_type;
1428         enum port port = intel_ddi_get_encoder_port(encoder);
1429         enum pipe pipe = 0;
1430         enum transcoder cpu_transcoder;
1431         uint32_t tmp;
1432         bool ret;
1433
1434         if (!intel_display_power_get_if_enabled(dev_priv,
1435                                                 encoder->power_domain))
1436                 return false;
1437
1438         if (!encoder->get_hw_state(encoder, &pipe)) {
1439                 ret = false;
1440                 goto out;
1441         }
1442
1443         if (port == PORT_A)
1444                 cpu_transcoder = TRANSCODER_EDP;
1445         else
1446                 cpu_transcoder = (enum transcoder) pipe;
1447
1448         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1449
1450         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1451         case TRANS_DDI_MODE_SELECT_HDMI:
1452         case TRANS_DDI_MODE_SELECT_DVI:
1453                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1454                 break;
1455
1456         case TRANS_DDI_MODE_SELECT_DP_SST:
1457                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1458                       type == DRM_MODE_CONNECTOR_DisplayPort;
1459                 break;
1460
1461         case TRANS_DDI_MODE_SELECT_DP_MST:
1462                 /* if the transcoder is in MST state then
1463                  * connector isn't connected */
1464                 ret = false;
1465                 break;
1466
1467         case TRANS_DDI_MODE_SELECT_FDI:
1468                 ret = type == DRM_MODE_CONNECTOR_VGA;
1469                 break;
1470
1471         default:
1472                 ret = false;
1473                 break;
1474         }
1475
1476 out:
1477         intel_display_power_put(dev_priv, encoder->power_domain);
1478
1479         return ret;
1480 }
1481
1482 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1483                             enum pipe *pipe)
1484 {
1485         struct drm_device *dev = encoder->base.dev;
1486         struct drm_i915_private *dev_priv = to_i915(dev);
1487         enum port port = intel_ddi_get_encoder_port(encoder);
1488         u32 tmp;
1489         int i;
1490         bool ret;
1491
1492         if (!intel_display_power_get_if_enabled(dev_priv,
1493                                                 encoder->power_domain))
1494                 return false;
1495
1496         ret = false;
1497
1498         tmp = I915_READ(DDI_BUF_CTL(port));
1499
1500         if (!(tmp & DDI_BUF_CTL_ENABLE))
1501                 goto out;
1502
1503         if (port == PORT_A) {
1504                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1505
1506                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1507                 case TRANS_DDI_EDP_INPUT_A_ON:
1508                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1509                         *pipe = PIPE_A;
1510                         break;
1511                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1512                         *pipe = PIPE_B;
1513                         break;
1514                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1515                         *pipe = PIPE_C;
1516                         break;
1517                 }
1518
1519                 ret = true;
1520
1521                 goto out;
1522         }
1523
1524         for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1525                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1526
1527                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1528                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1529                             TRANS_DDI_MODE_SELECT_DP_MST)
1530                                 goto out;
1531
1532                         *pipe = i;
1533                         ret = true;
1534
1535                         goto out;
1536                 }
1537         }
1538
1539         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1540
1541 out:
1542         if (ret && IS_GEN9_LP(dev_priv)) {
1543                 tmp = I915_READ(BXT_PHY_CTL(port));
1544                 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1545                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1546                         DRM_ERROR("Port %c enabled but PHY powered down? "
1547                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
1548         }
1549
1550         intel_display_power_put(dev_priv, encoder->power_domain);
1551
1552         return ret;
1553 }
1554
1555 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1556 {
1557         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1558         enum pipe pipe;
1559
1560         if (intel_ddi_get_hw_state(encoder, &pipe))
1561                 return BIT_ULL(dig_port->ddi_io_power_domain);
1562
1563         return 0;
1564 }
1565
1566 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1567 {
1568         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1569         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1570         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1571         enum port port = intel_ddi_get_encoder_port(encoder);
1572         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1573
1574         if (cpu_transcoder != TRANSCODER_EDP)
1575                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1576                            TRANS_CLK_SEL_PORT(port));
1577 }
1578
1579 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1580 {
1581         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1582         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1583
1584         if (cpu_transcoder != TRANSCODER_EDP)
1585                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1586                            TRANS_CLK_SEL_DISABLED);
1587 }
1588
1589 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1590                                 enum port port, uint8_t iboost)
1591 {
1592         u32 tmp;
1593
1594         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1595         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1596         if (iboost)
1597                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1598         else
1599                 tmp |= BALANCE_LEG_DISABLE(port);
1600         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1601 }
1602
1603 static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1604 {
1605         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1606         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1607         enum port port = intel_dig_port->port;
1608         int type = encoder->type;
1609         const struct ddi_buf_trans *ddi_translations;
1610         uint8_t iboost;
1611         uint8_t dp_iboost, hdmi_iboost;
1612         int n_entries;
1613
1614         /* VBT may override standard boost values */
1615         dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1616         hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1617
1618         if (type == INTEL_OUTPUT_DP) {
1619                 if (dp_iboost) {
1620                         iboost = dp_iboost;
1621                 } else {
1622                         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
1623                                 ddi_translations = kbl_get_buf_trans_dp(dev_priv,
1624                                                                         &n_entries);
1625                         else
1626                                 ddi_translations = skl_get_buf_trans_dp(dev_priv,
1627                                                                         &n_entries);
1628                         iboost = ddi_translations[level].i_boost;
1629                 }
1630         } else if (type == INTEL_OUTPUT_EDP) {
1631                 if (dp_iboost) {
1632                         iboost = dp_iboost;
1633                 } else {
1634                         ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1635
1636                         if (WARN_ON(port != PORT_A &&
1637                                     port != PORT_E && n_entries > 9))
1638                                 n_entries = 9;
1639
1640                         iboost = ddi_translations[level].i_boost;
1641                 }
1642         } else if (type == INTEL_OUTPUT_HDMI) {
1643                 if (hdmi_iboost) {
1644                         iboost = hdmi_iboost;
1645                 } else {
1646                         ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1647                         iboost = ddi_translations[level].i_boost;
1648                 }
1649         } else {
1650                 return;
1651         }
1652
1653         /* Make sure that the requested I_boost is valid */
1654         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1655                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1656                 return;
1657         }
1658
1659         _skl_ddi_set_iboost(dev_priv, port, iboost);
1660
1661         if (port == PORT_A && intel_dig_port->max_lanes == 4)
1662                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1663 }
1664
1665 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1666                                     u32 level, enum port port, int type)
1667 {
1668         const struct bxt_ddi_buf_trans *ddi_translations;
1669         u32 n_entries, i;
1670
1671         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1672                 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1673                 ddi_translations = bxt_ddi_translations_edp;
1674         } else if (type == INTEL_OUTPUT_DP
1675                         || type == INTEL_OUTPUT_EDP) {
1676                 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1677                 ddi_translations = bxt_ddi_translations_dp;
1678         } else if (type == INTEL_OUTPUT_HDMI) {
1679                 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1680                 ddi_translations = bxt_ddi_translations_hdmi;
1681         } else {
1682                 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1683                                 type);
1684                 return;
1685         }
1686
1687         /* Check if default value has to be used */
1688         if (level >= n_entries ||
1689             (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1690                 for (i = 0; i < n_entries; i++) {
1691                         if (ddi_translations[i].default_index) {
1692                                 level = i;
1693                                 break;
1694                         }
1695                 }
1696         }
1697
1698         bxt_ddi_phy_set_signal_level(dev_priv, port,
1699                                      ddi_translations[level].margin,
1700                                      ddi_translations[level].scale,
1701                                      ddi_translations[level].enable,
1702                                      ddi_translations[level].deemphasis);
1703 }
1704
1705 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1706 {
1707         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1708         int n_entries;
1709
1710         if (encoder->type == INTEL_OUTPUT_EDP)
1711                 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1712         else
1713                 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1714
1715         if (WARN_ON(n_entries < 1))
1716                 n_entries = 1;
1717         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1718                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1719
1720         return index_to_dp_signal_levels[n_entries - 1] &
1721                 DP_TRAIN_VOLTAGE_SWING_MASK;
1722 }
1723
1724 static const struct cnl_ddi_buf_trans *
1725 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
1726                        u32 voltage, int *n_entries)
1727 {
1728         if (voltage == VOLTAGE_INFO_0_85V) {
1729                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
1730                 return cnl_ddi_translations_hdmi_0_85V;
1731         } else if (voltage == VOLTAGE_INFO_0_95V) {
1732                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
1733                 return cnl_ddi_translations_hdmi_0_95V;
1734         } else if (voltage == VOLTAGE_INFO_1_05V) {
1735                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
1736                 return cnl_ddi_translations_hdmi_1_05V;
1737         }
1738         return NULL;
1739 }
1740
1741 static const struct cnl_ddi_buf_trans *
1742 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
1743                      u32 voltage, int *n_entries)
1744 {
1745         if (voltage == VOLTAGE_INFO_0_85V) {
1746                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
1747                 return cnl_ddi_translations_dp_0_85V;
1748         } else if (voltage == VOLTAGE_INFO_0_95V) {
1749                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
1750                 return cnl_ddi_translations_dp_0_95V;
1751         } else if (voltage == VOLTAGE_INFO_1_05V) {
1752                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1753                 return cnl_ddi_translations_dp_1_05V;
1754         }
1755         return NULL;
1756 }
1757
1758 static const struct cnl_ddi_buf_trans *
1759 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
1760                       u32 voltage, int *n_entries)
1761 {
1762         if (dev_priv->vbt.edp.low_vswing) {
1763                 if (voltage == VOLTAGE_INFO_0_85V) {
1764                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1765                         return cnl_ddi_translations_edp_0_85V;
1766                 } else if (voltage == VOLTAGE_INFO_0_95V) {
1767                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1768                         return cnl_ddi_translations_edp_0_95V;
1769                 } else if (voltage == VOLTAGE_INFO_1_05V) {
1770                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1771                         return cnl_ddi_translations_edp_1_05V;
1772                 }
1773                 return NULL;
1774         } else {
1775                 return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
1776         }
1777 }
1778
1779 static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
1780                                     u32 level, enum port port, int type)
1781 {
1782         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
1783         u32 n_entries, val, voltage;
1784         int ln;
1785
1786         /*
1787          * Values for each port type are listed in
1788          * voltage swing programming tables.
1789          * Vccio voltage found in PORT_COMP_DW3.
1790          */
1791         voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1792
1793         if (type == INTEL_OUTPUT_HDMI) {
1794                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
1795                                                           voltage, &n_entries);
1796         } else if (type == INTEL_OUTPUT_DP) {
1797                 ddi_translations = cnl_get_buf_trans_dp(dev_priv,
1798                                                         voltage, &n_entries);
1799         } else if (type == INTEL_OUTPUT_EDP) {
1800                 ddi_translations = cnl_get_buf_trans_edp(dev_priv,
1801                                                          voltage, &n_entries);
1802         }
1803
1804         if (ddi_translations == NULL) {
1805                 MISSING_CASE(voltage);
1806                 return;
1807         }
1808
1809         if (level >= n_entries) {
1810                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
1811                 level = n_entries - 1;
1812         }
1813
1814         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1815         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1816         val &= ~SCALING_MODE_SEL_MASK;
1817         val |= SCALING_MODE_SEL(2);
1818         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1819
1820         /* Program PORT_TX_DW2 */
1821         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1822         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1823                  RCOMP_SCALAR_MASK);
1824         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1825         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1826         /* Rcomp scalar is fixed as 0x98 for every table entry */
1827         val |= RCOMP_SCALAR(0x98);
1828         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1829
1830         /* Program PORT_TX_DW4 */
1831         /* We cannot write to GRP. It would overrite individual loadgen */
1832         for (ln = 0; ln < 4; ln++) {
1833                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1834                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1835                          CURSOR_COEFF_MASK);
1836                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1837                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1838                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1839                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1840         }
1841
1842         /* Program PORT_TX_DW5 */
1843         /* All DW5 values are fixed for every table entry */
1844         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1845         val &= ~RTERM_SELECT_MASK;
1846         val |= RTERM_SELECT(6);
1847         val |= TAP3_DISABLE;
1848         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1849
1850         /* Program PORT_TX_DW7 */
1851         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1852         val &= ~N_SCALAR_MASK;
1853         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1854         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1855 }
1856
1857 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
1858 {
1859         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1860         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1861         enum port port = intel_ddi_get_encoder_port(encoder);
1862         int type = encoder->type;
1863         int width = 0;
1864         int rate = 0;
1865         u32 val;
1866         int ln = 0;
1867
1868         if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
1869                 width = intel_dp->lane_count;
1870                 rate = intel_dp->link_rate;
1871         } else {
1872                 width = 4;
1873                 /* Rate is always < than 6GHz for HDMI */
1874         }
1875
1876         /*
1877          * 1. If port type is eDP or DP,
1878          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1879          * else clear to 0b.
1880          */
1881         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
1882         if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
1883                 val |= COMMON_KEEPER_EN;
1884         else
1885                 val &= ~COMMON_KEEPER_EN;
1886         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
1887
1888         /* 2. Program loadgen select */
1889         /*
1890          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
1891          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1892          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1893          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1894          */
1895         for (ln = 0; ln <= 3; ln++) {
1896                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1897                 val &= ~LOADGEN_SELECT;
1898
1899                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
1900                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
1901                         val |= LOADGEN_SELECT;
1902                 }
1903                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1904         }
1905
1906         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1907         val = I915_READ(CNL_PORT_CL1CM_DW5);
1908         val |= SUS_CLOCK_CONFIG;
1909         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
1910
1911         /* 4. Clear training enable to change swing values */
1912         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1913         val &= ~TX_TRAINING_EN;
1914         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1915
1916         /* 5. Program swing and de-emphasis */
1917         cnl_ddi_vswing_program(dev_priv, level, port, type);
1918
1919         /* 6. Set training enable to trigger update */
1920         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1921         val |= TX_TRAINING_EN;
1922         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1923 }
1924
1925 static uint32_t translate_signal_level(int signal_levels)
1926 {
1927         int i;
1928
1929         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1930                 if (index_to_dp_signal_levels[i] == signal_levels)
1931                         return i;
1932         }
1933
1934         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1935              signal_levels);
1936
1937         return 0;
1938 }
1939
1940 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1941 {
1942         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1943         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
1944         struct intel_encoder *encoder = &dport->base;
1945         uint8_t train_set = intel_dp->train_set[0];
1946         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1947                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1948         enum port port = dport->port;
1949         uint32_t level;
1950
1951         level = translate_signal_level(signal_levels);
1952
1953         if (IS_GEN9_BC(dev_priv))
1954                 skl_ddi_set_iboost(encoder, level);
1955         else if (IS_GEN9_LP(dev_priv))
1956                 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
1957         else if (IS_CANNONLAKE(dev_priv)) {
1958                 cnl_ddi_vswing_sequence(encoder, level);
1959                 /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
1960                 return 0;
1961         }
1962         return DDI_BUF_TRANS_SELECT(level);
1963 }
1964
1965 static void intel_ddi_clk_select(struct intel_encoder *encoder,
1966                                  struct intel_shared_dpll *pll)
1967 {
1968         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1969         enum port port = intel_ddi_get_encoder_port(encoder);
1970         uint32_t val;
1971
1972         if (WARN_ON(!pll))
1973                 return;
1974
1975         if (IS_CANNONLAKE(dev_priv)) {
1976                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
1977                 val = I915_READ(DPCLKA_CFGCR0);
1978                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
1979                 I915_WRITE(DPCLKA_CFGCR0, val);
1980
1981                 /*
1982                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
1983                  * This step and the step before must be done with separate
1984                  * register writes.
1985                  */
1986                 val = I915_READ(DPCLKA_CFGCR0);
1987                 val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
1988                          DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
1989                 I915_WRITE(DPCLKA_CFGCR0, val);
1990         } else if (IS_GEN9_BC(dev_priv)) {
1991                 /* DDI -> PLL mapping  */
1992                 val = I915_READ(DPLL_CTRL2);
1993
1994                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1995                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1996                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
1997                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1998
1999                 I915_WRITE(DPLL_CTRL2, val);
2000
2001         } else if (INTEL_INFO(dev_priv)->gen < 9) {
2002                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2003         }
2004 }
2005
2006 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2007                                     int link_rate, uint32_t lane_count,
2008                                     struct intel_shared_dpll *pll,
2009                                     bool link_mst)
2010 {
2011         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2012         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2013         enum port port = intel_ddi_get_encoder_port(encoder);
2014         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2015
2016         WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
2017
2018         intel_dp_set_link_params(intel_dp, link_rate, lane_count,
2019                                  link_mst);
2020         if (encoder->type == INTEL_OUTPUT_EDP)
2021                 intel_edp_panel_on(intel_dp);
2022
2023         intel_ddi_clk_select(encoder, pll);
2024
2025         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2026
2027         intel_prepare_dp_ddi_buffers(encoder);
2028         intel_ddi_init_dp_buf_reg(encoder);
2029         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2030         intel_dp_start_link_train(intel_dp);
2031         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2032                 intel_dp_stop_link_train(intel_dp);
2033 }
2034
2035 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2036                                       bool has_hdmi_sink,
2037                                       const struct intel_crtc_state *crtc_state,
2038                                       const struct drm_connector_state *conn_state,
2039                                       struct intel_shared_dpll *pll)
2040 {
2041         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2042         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2043         struct drm_encoder *drm_encoder = &encoder->base;
2044         enum port port = intel_ddi_get_encoder_port(encoder);
2045         int level = intel_ddi_hdmi_level(dev_priv, port);
2046         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2047
2048         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2049         intel_ddi_clk_select(encoder, pll);
2050
2051         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2052
2053         intel_prepare_hdmi_ddi_buffers(encoder);
2054         if (IS_GEN9_BC(dev_priv))
2055                 skl_ddi_set_iboost(encoder, level);
2056         else if (IS_GEN9_LP(dev_priv))
2057                 bxt_ddi_vswing_sequence(dev_priv, level, port,
2058                                         INTEL_OUTPUT_HDMI);
2059         else if (IS_CANNONLAKE(dev_priv))
2060                 cnl_ddi_vswing_sequence(encoder, level);
2061
2062         intel_hdmi->set_infoframes(drm_encoder,
2063                                    has_hdmi_sink,
2064                                    crtc_state, conn_state);
2065 }
2066
2067 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2068                                  struct intel_crtc_state *pipe_config,
2069                                  struct drm_connector_state *conn_state)
2070 {
2071         int type = encoder->type;
2072
2073         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2074                 intel_ddi_pre_enable_dp(encoder,
2075                                         pipe_config->port_clock,
2076                                         pipe_config->lane_count,
2077                                         pipe_config->shared_dpll,
2078                                         intel_crtc_has_type(pipe_config,
2079                                                             INTEL_OUTPUT_DP_MST));
2080         }
2081         if (type == INTEL_OUTPUT_HDMI) {
2082                 intel_ddi_pre_enable_hdmi(encoder,
2083                                           pipe_config->has_hdmi_sink,
2084                                           pipe_config, conn_state,
2085                                           pipe_config->shared_dpll);
2086         }
2087 }
2088
2089 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
2090                                    struct intel_crtc_state *old_crtc_state,
2091                                    struct drm_connector_state *old_conn_state)
2092 {
2093         struct drm_encoder *encoder = &intel_encoder->base;
2094         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2095         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2096         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2097         struct intel_dp *intel_dp = NULL;
2098         int type = intel_encoder->type;
2099         uint32_t val;
2100         bool wait = false;
2101
2102         /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
2103
2104         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2105                 intel_dp = enc_to_intel_dp(encoder);
2106                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2107         }
2108
2109         val = I915_READ(DDI_BUF_CTL(port));
2110         if (val & DDI_BUF_CTL_ENABLE) {
2111                 val &= ~DDI_BUF_CTL_ENABLE;
2112                 I915_WRITE(DDI_BUF_CTL(port), val);
2113                 wait = true;
2114         }
2115
2116         val = I915_READ(DP_TP_CTL(port));
2117         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2118         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2119         I915_WRITE(DP_TP_CTL(port), val);
2120
2121         if (wait)
2122                 intel_wait_ddi_buf_idle(dev_priv, port);
2123
2124         if (intel_dp) {
2125                 intel_edp_panel_vdd_on(intel_dp);
2126                 intel_edp_panel_off(intel_dp);
2127         }
2128
2129         if (dig_port)
2130                 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2131
2132         if (IS_CANNONLAKE(dev_priv))
2133                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2134                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2135         else if (IS_GEN9_BC(dev_priv))
2136                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2137                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
2138         else if (INTEL_GEN(dev_priv) < 9)
2139                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2140
2141         if (type == INTEL_OUTPUT_HDMI) {
2142                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2143
2144                 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2145         }
2146 }
2147
2148 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2149                                 struct intel_crtc_state *old_crtc_state,
2150                                 struct drm_connector_state *old_conn_state)
2151 {
2152         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2153         uint32_t val;
2154
2155         /*
2156          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2157          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2158          * step 13 is the correct place for it. Step 18 is where it was
2159          * originally before the BUN.
2160          */
2161         val = I915_READ(FDI_RX_CTL(PIPE_A));
2162         val &= ~FDI_RX_ENABLE;
2163         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2164
2165         intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
2166
2167         val = I915_READ(FDI_RX_MISC(PIPE_A));
2168         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2169         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2170         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2171
2172         val = I915_READ(FDI_RX_CTL(PIPE_A));
2173         val &= ~FDI_PCDCLK;
2174         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2175
2176         val = I915_READ(FDI_RX_CTL(PIPE_A));
2177         val &= ~FDI_RX_PLL_ENABLE;
2178         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2179 }
2180
2181 static void intel_enable_ddi(struct intel_encoder *intel_encoder,
2182                              struct intel_crtc_state *pipe_config,
2183                              struct drm_connector_state *conn_state)
2184 {
2185         struct drm_encoder *encoder = &intel_encoder->base;
2186         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2187         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2188         int type = intel_encoder->type;
2189
2190         if (type == INTEL_OUTPUT_HDMI) {
2191                 struct intel_digital_port *intel_dig_port =
2192                         enc_to_dig_port(encoder);
2193                 bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
2194                 bool scrambling = pipe_config->hdmi_scrambling;
2195
2196                 intel_hdmi_handle_sink_scrambling(intel_encoder,
2197                                                   conn_state->connector,
2198                                                   clock_ratio, scrambling);
2199
2200                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2201                  * are ignored so nothing special needs to be done besides
2202                  * enabling the port.
2203                  */
2204                 I915_WRITE(DDI_BUF_CTL(port),
2205                            intel_dig_port->saved_port_bits |
2206                            DDI_BUF_CTL_ENABLE);
2207         } else if (type == INTEL_OUTPUT_EDP) {
2208                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2209
2210                 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2211                         intel_dp_stop_link_train(intel_dp);
2212
2213                 intel_edp_backlight_on(pipe_config, conn_state);
2214                 intel_psr_enable(intel_dp);
2215                 intel_edp_drrs_enable(intel_dp, pipe_config);
2216         }
2217
2218         if (pipe_config->has_audio)
2219                 intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
2220 }
2221
2222 static void intel_disable_ddi(struct intel_encoder *intel_encoder,
2223                               struct intel_crtc_state *old_crtc_state,
2224                               struct drm_connector_state *old_conn_state)
2225 {
2226         struct drm_encoder *encoder = &intel_encoder->base;
2227         int type = intel_encoder->type;
2228
2229         if (old_crtc_state->has_audio)
2230                 intel_audio_codec_disable(intel_encoder);
2231
2232         if (type == INTEL_OUTPUT_HDMI) {
2233                 intel_hdmi_handle_sink_scrambling(intel_encoder,
2234                                                   old_conn_state->connector,
2235                                                   false, false);
2236         }
2237
2238         if (type == INTEL_OUTPUT_EDP) {
2239                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2240
2241                 intel_edp_drrs_disable(intel_dp, old_crtc_state);
2242                 intel_psr_disable(intel_dp);
2243                 intel_edp_backlight_off(old_conn_state);
2244         }
2245 }
2246
2247 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2248                                    struct intel_crtc_state *pipe_config,
2249                                    struct drm_connector_state *conn_state)
2250 {
2251         uint8_t mask = pipe_config->lane_lat_optim_mask;
2252
2253         bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
2254 }
2255
2256 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2257 {
2258         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2259         struct drm_i915_private *dev_priv =
2260                 to_i915(intel_dig_port->base.base.dev);
2261         enum port port = intel_dig_port->port;
2262         uint32_t val;
2263         bool wait = false;
2264
2265         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2266                 val = I915_READ(DDI_BUF_CTL(port));
2267                 if (val & DDI_BUF_CTL_ENABLE) {
2268                         val &= ~DDI_BUF_CTL_ENABLE;
2269                         I915_WRITE(DDI_BUF_CTL(port), val);
2270                         wait = true;
2271                 }
2272
2273                 val = I915_READ(DP_TP_CTL(port));
2274                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2275                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2276                 I915_WRITE(DP_TP_CTL(port), val);
2277                 POSTING_READ(DP_TP_CTL(port));
2278
2279                 if (wait)
2280                         intel_wait_ddi_buf_idle(dev_priv, port);
2281         }
2282
2283         val = DP_TP_CTL_ENABLE |
2284               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2285         if (intel_dp->link_mst)
2286                 val |= DP_TP_CTL_MODE_MST;
2287         else {
2288                 val |= DP_TP_CTL_MODE_SST;
2289                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2290                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2291         }
2292         I915_WRITE(DP_TP_CTL(port), val);
2293         POSTING_READ(DP_TP_CTL(port));
2294
2295         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2296         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2297         POSTING_READ(DDI_BUF_CTL(port));
2298
2299         udelay(600);
2300 }
2301
2302 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2303                                  struct intel_crtc *intel_crtc)
2304 {
2305         u32 temp;
2306
2307         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2308                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2309                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2310                         return true;
2311         }
2312         return false;
2313 }
2314
2315 void intel_ddi_get_config(struct intel_encoder *encoder,
2316                           struct intel_crtc_state *pipe_config)
2317 {
2318         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2319         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2320         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2321         struct intel_hdmi *intel_hdmi;
2322         u32 temp, flags = 0;
2323
2324         /* XXX: DSI transcoder paranoia */
2325         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2326                 return;
2327
2328         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2329         if (temp & TRANS_DDI_PHSYNC)
2330                 flags |= DRM_MODE_FLAG_PHSYNC;
2331         else
2332                 flags |= DRM_MODE_FLAG_NHSYNC;
2333         if (temp & TRANS_DDI_PVSYNC)
2334                 flags |= DRM_MODE_FLAG_PVSYNC;
2335         else
2336                 flags |= DRM_MODE_FLAG_NVSYNC;
2337
2338         pipe_config->base.adjusted_mode.flags |= flags;
2339
2340         switch (temp & TRANS_DDI_BPC_MASK) {
2341         case TRANS_DDI_BPC_6:
2342                 pipe_config->pipe_bpp = 18;
2343                 break;
2344         case TRANS_DDI_BPC_8:
2345                 pipe_config->pipe_bpp = 24;
2346                 break;
2347         case TRANS_DDI_BPC_10:
2348                 pipe_config->pipe_bpp = 30;
2349                 break;
2350         case TRANS_DDI_BPC_12:
2351                 pipe_config->pipe_bpp = 36;
2352                 break;
2353         default:
2354                 break;
2355         }
2356
2357         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2358         case TRANS_DDI_MODE_SELECT_HDMI:
2359                 pipe_config->has_hdmi_sink = true;
2360                 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2361
2362                 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
2363                         pipe_config->has_infoframe = true;
2364
2365                 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2366                         TRANS_DDI_HDMI_SCRAMBLING_MASK)
2367                         pipe_config->hdmi_scrambling = true;
2368                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2369                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2370                 /* fall through */
2371         case TRANS_DDI_MODE_SELECT_DVI:
2372                 pipe_config->lane_count = 4;
2373                 break;
2374         case TRANS_DDI_MODE_SELECT_FDI:
2375                 break;
2376         case TRANS_DDI_MODE_SELECT_DP_SST:
2377         case TRANS_DDI_MODE_SELECT_DP_MST:
2378                 pipe_config->lane_count =
2379                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2380                 intel_dp_get_m_n(intel_crtc, pipe_config);
2381                 break;
2382         default:
2383                 break;
2384         }
2385
2386         pipe_config->has_audio =
2387                 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
2388
2389         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2390             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2391                 /*
2392                  * This is a big fat ugly hack.
2393                  *
2394                  * Some machines in UEFI boot mode provide us a VBT that has 18
2395                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2396                  * unknown we fail to light up. Yet the same BIOS boots up with
2397                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2398                  * max, not what it tells us to use.
2399                  *
2400                  * Note: This will still be broken if the eDP panel is not lit
2401                  * up by the BIOS, and thus we can't get the mode at module
2402                  * load.
2403                  */
2404                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2405                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2406                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2407         }
2408
2409         intel_ddi_clock_get(encoder, pipe_config);
2410
2411         if (IS_GEN9_LP(dev_priv))
2412                 pipe_config->lane_lat_optim_mask =
2413                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2414 }
2415
2416 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2417                                      struct intel_crtc_state *pipe_config,
2418                                      struct drm_connector_state *conn_state)
2419 {
2420         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2421         int type = encoder->type;
2422         int port = intel_ddi_get_encoder_port(encoder);
2423         int ret;
2424
2425         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2426
2427         if (port == PORT_A)
2428                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2429
2430         if (type == INTEL_OUTPUT_HDMI)
2431                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
2432         else
2433                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2434
2435         if (IS_GEN9_LP(dev_priv) && ret)
2436                 pipe_config->lane_lat_optim_mask =
2437                         bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2438                                                              pipe_config->lane_count);
2439
2440         return ret;
2441
2442 }
2443
2444 static const struct drm_encoder_funcs intel_ddi_funcs = {
2445         .reset = intel_dp_encoder_reset,
2446         .destroy = intel_dp_encoder_destroy,
2447 };
2448
2449 static struct intel_connector *
2450 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2451 {
2452         struct intel_connector *connector;
2453         enum port port = intel_dig_port->port;
2454
2455         connector = intel_connector_alloc();
2456         if (!connector)
2457                 return NULL;
2458
2459         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2460         if (!intel_dp_init_connector(intel_dig_port, connector)) {
2461                 kfree(connector);
2462                 return NULL;
2463         }
2464
2465         return connector;
2466 }
2467
2468 static struct intel_connector *
2469 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2470 {
2471         struct intel_connector *connector;
2472         enum port port = intel_dig_port->port;
2473
2474         connector = intel_connector_alloc();
2475         if (!connector)
2476                 return NULL;
2477
2478         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2479         intel_hdmi_init_connector(intel_dig_port, connector);
2480
2481         return connector;
2482 }
2483
2484 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
2485 {
2486         struct intel_digital_port *intel_dig_port;
2487         struct intel_encoder *intel_encoder;
2488         struct drm_encoder *encoder;
2489         bool init_hdmi, init_dp, init_lspcon = false;
2490         int max_lanes;
2491
2492         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2493                 switch (port) {
2494                 case PORT_A:
2495                         max_lanes = 4;
2496                         break;
2497                 case PORT_E:
2498                         max_lanes = 0;
2499                         break;
2500                 default:
2501                         max_lanes = 4;
2502                         break;
2503                 }
2504         } else {
2505                 switch (port) {
2506                 case PORT_A:
2507                         max_lanes = 2;
2508                         break;
2509                 case PORT_E:
2510                         max_lanes = 2;
2511                         break;
2512                 default:
2513                         max_lanes = 4;
2514                         break;
2515                 }
2516         }
2517
2518         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2519                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2520         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2521
2522         if (intel_bios_is_lspcon_present(dev_priv, port)) {
2523                 /*
2524                  * Lspcon device needs to be driven with DP connector
2525                  * with special detection sequence. So make sure DP
2526                  * is initialized before lspcon.
2527                  */
2528                 init_dp = true;
2529                 init_lspcon = true;
2530                 init_hdmi = false;
2531                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2532         }
2533
2534         if (!init_dp && !init_hdmi) {
2535                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2536                               port_name(port));
2537                 return;
2538         }
2539
2540         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2541         if (!intel_dig_port)
2542                 return;
2543
2544         intel_encoder = &intel_dig_port->base;
2545         encoder = &intel_encoder->base;
2546
2547         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
2548                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2549
2550         intel_encoder->compute_config = intel_ddi_compute_config;
2551         intel_encoder->enable = intel_enable_ddi;
2552         if (IS_GEN9_LP(dev_priv))
2553                 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2554         intel_encoder->pre_enable = intel_ddi_pre_enable;
2555         intel_encoder->disable = intel_disable_ddi;
2556         intel_encoder->post_disable = intel_ddi_post_disable;
2557         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2558         intel_encoder->get_config = intel_ddi_get_config;
2559         intel_encoder->suspend = intel_dp_encoder_suspend;
2560         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
2561
2562         intel_dig_port->port = port;
2563         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2564                                           (DDI_BUF_PORT_REVERSAL |
2565                                            DDI_A_4_LANES);
2566
2567         switch (port) {
2568         case PORT_A:
2569                 intel_dig_port->ddi_io_power_domain =
2570                         POWER_DOMAIN_PORT_DDI_A_IO;
2571                 break;
2572         case PORT_B:
2573                 intel_dig_port->ddi_io_power_domain =
2574                         POWER_DOMAIN_PORT_DDI_B_IO;
2575                 break;
2576         case PORT_C:
2577                 intel_dig_port->ddi_io_power_domain =
2578                         POWER_DOMAIN_PORT_DDI_C_IO;
2579                 break;
2580         case PORT_D:
2581                 intel_dig_port->ddi_io_power_domain =
2582                         POWER_DOMAIN_PORT_DDI_D_IO;
2583                 break;
2584         case PORT_E:
2585                 intel_dig_port->ddi_io_power_domain =
2586                         POWER_DOMAIN_PORT_DDI_E_IO;
2587                 break;
2588         default:
2589                 MISSING_CASE(port);
2590         }
2591
2592         /*
2593          * Bspec says that DDI_A_4_LANES is the only supported configuration
2594          * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
2595          * wasn't lit up at boot.  Force this bit on in our internal
2596          * configuration so that we use the proper lane count for our
2597          * calculations.
2598          */
2599         if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
2600                 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2601                         DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2602                         intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2603                         max_lanes = 4;
2604                 }
2605         }
2606
2607         intel_dig_port->max_lanes = max_lanes;
2608
2609         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2610         intel_encoder->power_domain = intel_port_to_power_domain(port);
2611         intel_encoder->port = port;
2612         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2613         intel_encoder->cloneable = 0;
2614
2615         if (init_dp) {
2616                 if (!intel_ddi_init_dp_connector(intel_dig_port))
2617                         goto err;
2618
2619                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2620                 dev_priv->hotplug.irq_port[port] = intel_dig_port;
2621         }
2622
2623         /* In theory we don't need the encoder->type check, but leave it just in
2624          * case we have some really bad VBTs... */
2625         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2626                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2627                         goto err;
2628         }
2629
2630         if (init_lspcon) {
2631                 if (lspcon_init(intel_dig_port))
2632                         /* TODO: handle hdmi info frame part */
2633                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2634                                 port_name(port));
2635                 else
2636                         /*
2637                          * LSPCON init faied, but DP init was success, so
2638                          * lets try to drive as DP++ port.
2639                          */
2640                         DRM_ERROR("LSPCON init failed on port %c\n",
2641                                 port_name(port));
2642         }
2643
2644         return;
2645
2646 err:
2647         drm_encoder_cleanup(encoder);
2648         kfree(intel_dig_port);
2649 }