2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <drm/drm_scdc_helper.h>
30 #include "intel_drv.h"
31 #include "intel_dsi.h"
33 struct ddi_buf_trans {
34 u32 trans1; /* balance leg enable, de-emph level */
35 u32 trans2; /* vref sel, vswing */
36 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
39 static const u8 index_to_dp_signal_levels[] = {
40 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
41 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
42 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
43 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
44 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
45 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
46 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
47 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
49 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
52 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
53 * them for both DP and FDI transports, allowing those ports to
54 * automatically adapt to HDMI connections as well
56 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
57 { 0x00FFFFFF, 0x0006000E, 0x0 },
58 { 0x00D75FFF, 0x0005000A, 0x0 },
59 { 0x00C30FFF, 0x00040006, 0x0 },
60 { 0x80AAAFFF, 0x000B0000, 0x0 },
61 { 0x00FFFFFF, 0x0005000A, 0x0 },
62 { 0x00D75FFF, 0x000C0004, 0x0 },
63 { 0x80C30FFF, 0x000B0000, 0x0 },
64 { 0x00FFFFFF, 0x00040006, 0x0 },
65 { 0x80D75FFF, 0x000B0000, 0x0 },
68 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
69 { 0x00FFFFFF, 0x0007000E, 0x0 },
70 { 0x00D75FFF, 0x000F000A, 0x0 },
71 { 0x00C30FFF, 0x00060006, 0x0 },
72 { 0x00AAAFFF, 0x001E0000, 0x0 },
73 { 0x00FFFFFF, 0x000F000A, 0x0 },
74 { 0x00D75FFF, 0x00160004, 0x0 },
75 { 0x00C30FFF, 0x001E0000, 0x0 },
76 { 0x00FFFFFF, 0x00060006, 0x0 },
77 { 0x00D75FFF, 0x001E0000, 0x0 },
80 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
81 /* Idx NT mV d T mV d db */
82 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
83 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
84 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
85 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
86 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
87 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
88 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
89 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
90 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
91 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
92 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
93 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
96 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
97 { 0x00FFFFFF, 0x00000012, 0x0 },
98 { 0x00EBAFFF, 0x00020011, 0x0 },
99 { 0x00C71FFF, 0x0006000F, 0x0 },
100 { 0x00AAAFFF, 0x000E000A, 0x0 },
101 { 0x00FFFFFF, 0x00020011, 0x0 },
102 { 0x00DB6FFF, 0x0005000F, 0x0 },
103 { 0x00BEEFFF, 0x000A000C, 0x0 },
104 { 0x00FFFFFF, 0x0005000F, 0x0 },
105 { 0x00DB6FFF, 0x000A000C, 0x0 },
108 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
109 { 0x00FFFFFF, 0x0007000E, 0x0 },
110 { 0x00D75FFF, 0x000E000A, 0x0 },
111 { 0x00BEFFFF, 0x00140006, 0x0 },
112 { 0x80B2CFFF, 0x001B0002, 0x0 },
113 { 0x00FFFFFF, 0x000E000A, 0x0 },
114 { 0x00DB6FFF, 0x00160005, 0x0 },
115 { 0x80C71FFF, 0x001A0002, 0x0 },
116 { 0x00F7DFFF, 0x00180004, 0x0 },
117 { 0x80D75FFF, 0x001B0002, 0x0 },
120 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
121 { 0x00FFFFFF, 0x0001000E, 0x0 },
122 { 0x00D75FFF, 0x0004000A, 0x0 },
123 { 0x00C30FFF, 0x00070006, 0x0 },
124 { 0x00AAAFFF, 0x000C0000, 0x0 },
125 { 0x00FFFFFF, 0x0004000A, 0x0 },
126 { 0x00D75FFF, 0x00090004, 0x0 },
127 { 0x00C30FFF, 0x000C0000, 0x0 },
128 { 0x00FFFFFF, 0x00070006, 0x0 },
129 { 0x00D75FFF, 0x000C0000, 0x0 },
132 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
133 /* Idx NT mV d T mV df db */
134 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
135 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
136 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
137 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
138 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
139 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
140 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
141 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
142 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
143 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
146 /* Skylake H and S */
147 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
148 { 0x00002016, 0x000000A0, 0x0 },
149 { 0x00005012, 0x0000009B, 0x0 },
150 { 0x00007011, 0x00000088, 0x0 },
151 { 0x80009010, 0x000000C0, 0x1 },
152 { 0x00002016, 0x0000009B, 0x0 },
153 { 0x00005012, 0x00000088, 0x0 },
154 { 0x80007011, 0x000000C0, 0x1 },
155 { 0x00002016, 0x000000DF, 0x0 },
156 { 0x80005012, 0x000000C0, 0x1 },
160 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
161 { 0x0000201B, 0x000000A2, 0x0 },
162 { 0x00005012, 0x00000088, 0x0 },
163 { 0x80007011, 0x000000CD, 0x1 },
164 { 0x80009010, 0x000000C0, 0x1 },
165 { 0x0000201B, 0x0000009D, 0x0 },
166 { 0x80005012, 0x000000C0, 0x1 },
167 { 0x80007011, 0x000000C0, 0x1 },
168 { 0x00002016, 0x00000088, 0x0 },
169 { 0x80005012, 0x000000C0, 0x1 },
173 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
174 { 0x00000018, 0x000000A2, 0x0 },
175 { 0x00005012, 0x00000088, 0x0 },
176 { 0x80007011, 0x000000CD, 0x3 },
177 { 0x80009010, 0x000000C0, 0x3 },
178 { 0x00000018, 0x0000009D, 0x0 },
179 { 0x80005012, 0x000000C0, 0x3 },
180 { 0x80007011, 0x000000C0, 0x3 },
181 { 0x00000018, 0x00000088, 0x0 },
182 { 0x80005012, 0x000000C0, 0x3 },
185 /* Kabylake H and S */
186 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
187 { 0x00002016, 0x000000A0, 0x0 },
188 { 0x00005012, 0x0000009B, 0x0 },
189 { 0x00007011, 0x00000088, 0x0 },
190 { 0x80009010, 0x000000C0, 0x1 },
191 { 0x00002016, 0x0000009B, 0x0 },
192 { 0x00005012, 0x00000088, 0x0 },
193 { 0x80007011, 0x000000C0, 0x1 },
194 { 0x00002016, 0x00000097, 0x0 },
195 { 0x80005012, 0x000000C0, 0x1 },
199 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
200 { 0x0000201B, 0x000000A1, 0x0 },
201 { 0x00005012, 0x00000088, 0x0 },
202 { 0x80007011, 0x000000CD, 0x3 },
203 { 0x80009010, 0x000000C0, 0x3 },
204 { 0x0000201B, 0x0000009D, 0x0 },
205 { 0x80005012, 0x000000C0, 0x3 },
206 { 0x80007011, 0x000000C0, 0x3 },
207 { 0x00002016, 0x0000004F, 0x0 },
208 { 0x80005012, 0x000000C0, 0x3 },
212 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
213 { 0x00001017, 0x000000A1, 0x0 },
214 { 0x00005012, 0x00000088, 0x0 },
215 { 0x80007011, 0x000000CD, 0x3 },
216 { 0x8000800F, 0x000000C0, 0x3 },
217 { 0x00001017, 0x0000009D, 0x0 },
218 { 0x80005012, 0x000000C0, 0x3 },
219 { 0x80007011, 0x000000C0, 0x3 },
220 { 0x00001017, 0x0000004C, 0x0 },
221 { 0x80005012, 0x000000C0, 0x3 },
225 * Skylake/Kabylake H and S
226 * eDP 1.4 low vswing translation parameters
228 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
229 { 0x00000018, 0x000000A8, 0x0 },
230 { 0x00004013, 0x000000A9, 0x0 },
231 { 0x00007011, 0x000000A2, 0x0 },
232 { 0x00009010, 0x0000009C, 0x0 },
233 { 0x00000018, 0x000000A9, 0x0 },
234 { 0x00006013, 0x000000A2, 0x0 },
235 { 0x00007011, 0x000000A6, 0x0 },
236 { 0x00000018, 0x000000AB, 0x0 },
237 { 0x00007013, 0x0000009F, 0x0 },
238 { 0x00000018, 0x000000DF, 0x0 },
243 * eDP 1.4 low vswing translation parameters
245 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
246 { 0x00000018, 0x000000A8, 0x0 },
247 { 0x00004013, 0x000000A9, 0x0 },
248 { 0x00007011, 0x000000A2, 0x0 },
249 { 0x00009010, 0x0000009C, 0x0 },
250 { 0x00000018, 0x000000A9, 0x0 },
251 { 0x00006013, 0x000000A2, 0x0 },
252 { 0x00007011, 0x000000A6, 0x0 },
253 { 0x00002016, 0x000000AB, 0x0 },
254 { 0x00005013, 0x0000009F, 0x0 },
255 { 0x00000018, 0x000000DF, 0x0 },
260 * eDP 1.4 low vswing translation parameters
262 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
263 { 0x00000018, 0x000000A8, 0x0 },
264 { 0x00004013, 0x000000AB, 0x0 },
265 { 0x00007011, 0x000000A4, 0x0 },
266 { 0x00009010, 0x000000DF, 0x0 },
267 { 0x00000018, 0x000000AA, 0x0 },
268 { 0x00006013, 0x000000A4, 0x0 },
269 { 0x00007011, 0x0000009D, 0x0 },
270 { 0x00000018, 0x000000A0, 0x0 },
271 { 0x00006012, 0x000000DF, 0x0 },
272 { 0x00000018, 0x0000008A, 0x0 },
275 /* Skylake/Kabylake U, H and S */
276 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
277 { 0x00000018, 0x000000AC, 0x0 },
278 { 0x00005012, 0x0000009D, 0x0 },
279 { 0x00007011, 0x00000088, 0x0 },
280 { 0x00000018, 0x000000A1, 0x0 },
281 { 0x00000018, 0x00000098, 0x0 },
282 { 0x00004013, 0x00000088, 0x0 },
283 { 0x80006012, 0x000000CD, 0x1 },
284 { 0x00000018, 0x000000DF, 0x0 },
285 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
286 { 0x80003015, 0x000000C0, 0x1 },
287 { 0x80000018, 0x000000C0, 0x1 },
290 /* Skylake/Kabylake Y */
291 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
292 { 0x00000018, 0x000000A1, 0x0 },
293 { 0x00005012, 0x000000DF, 0x0 },
294 { 0x80007011, 0x000000CB, 0x3 },
295 { 0x00000018, 0x000000A4, 0x0 },
296 { 0x00000018, 0x0000009D, 0x0 },
297 { 0x00004013, 0x00000080, 0x0 },
298 { 0x80006013, 0x000000C0, 0x3 },
299 { 0x00000018, 0x0000008A, 0x0 },
300 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
301 { 0x80003015, 0x000000C0, 0x3 },
302 { 0x80000018, 0x000000C0, 0x3 },
305 struct bxt_ddi_buf_trans {
306 u8 margin; /* swing value */
307 u8 scale; /* scale value */
308 u8 enable; /* scale enable */
312 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
313 /* Idx NT mV diff db */
314 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
315 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
316 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
317 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
318 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
319 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
320 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
321 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
322 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
323 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
326 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
327 /* Idx NT mV diff db */
328 { 26, 0, 0, 128, }, /* 0: 200 0 */
329 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
330 { 48, 0, 0, 96, }, /* 2: 200 4 */
331 { 54, 0, 0, 69, }, /* 3: 200 6 */
332 { 32, 0, 0, 128, }, /* 4: 250 0 */
333 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
334 { 54, 0, 0, 85, }, /* 6: 250 4 */
335 { 43, 0, 0, 128, }, /* 7: 300 0 */
336 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
337 { 48, 0, 0, 128, }, /* 9: 300 0 */
340 /* BSpec has 2 recommended values - entries 0 and 8.
341 * Using the entry with higher vswing.
343 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
344 /* Idx NT mV diff db */
345 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
346 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
347 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
348 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
349 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
350 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
351 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
352 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
353 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
354 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
357 struct cnl_ddi_buf_trans {
361 u8 dw4_post_cursor_2;
362 u8 dw4_post_cursor_1;
365 /* Voltage Swing Programming for VccIO 0.85V for DP */
366 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
367 /* NT mV Trans mV db */
368 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
369 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
370 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
371 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
372 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
373 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
374 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
375 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
376 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
377 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
380 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
381 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
382 /* NT mV Trans mV db */
383 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
384 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
385 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
386 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
387 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
388 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
389 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
392 /* Voltage Swing Programming for VccIO 0.85V for eDP */
393 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
394 /* NT mV Trans mV db */
395 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
396 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
397 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
398 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
399 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
400 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
401 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
402 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
403 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
406 /* Voltage Swing Programming for VccIO 0.95V for DP */
407 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
408 /* NT mV Trans mV db */
409 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
410 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
411 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
412 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
413 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
414 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
415 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
416 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
417 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
418 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
421 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
422 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
423 /* NT mV Trans mV db */
424 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
425 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
426 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
427 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
428 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
429 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
430 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
431 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
432 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
433 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
434 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
437 /* Voltage Swing Programming for VccIO 0.95V for eDP */
438 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
439 /* NT mV Trans mV db */
440 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
441 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
442 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
443 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
444 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
445 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
446 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
447 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
448 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
449 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
452 /* Voltage Swing Programming for VccIO 1.05V for DP */
453 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
454 /* NT mV Trans mV db */
455 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
456 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
457 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
458 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
459 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
460 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
461 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
462 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
463 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
464 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
467 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
468 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
469 /* NT mV Trans mV db */
470 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
471 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
472 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
473 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
474 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
475 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
476 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
477 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
478 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
479 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
480 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
483 /* Voltage Swing Programming for VccIO 1.05V for eDP */
484 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
485 /* NT mV Trans mV db */
486 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
487 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
488 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
489 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
490 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
491 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
492 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
493 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
494 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
497 /* icl_combo_phy_ddi_translations */
498 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
499 /* NT mV Trans mV db */
500 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
501 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
502 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
503 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
504 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
505 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
506 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
507 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
508 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
509 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
512 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
513 /* NT mV Trans mV db */
514 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
515 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
516 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
517 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
518 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
519 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
520 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
521 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
522 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
523 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
526 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
527 /* NT mV Trans mV db */
528 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
529 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
530 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
531 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
532 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
533 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
534 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
535 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
536 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
537 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
540 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
541 /* NT mV Trans mV db */
542 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
543 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
544 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
545 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
546 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
547 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
548 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
551 struct icl_mg_phy_ddi_buf_trans {
552 u32 cri_txdeemph_override_5_0;
553 u32 cri_txdeemph_override_11_6;
554 u32 cri_txdeemph_override_17_12;
557 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
558 /* Voltage swing pre-emphasis */
559 { 0x0, 0x1B, 0x00 }, /* 0 0 */
560 { 0x0, 0x23, 0x08 }, /* 0 1 */
561 { 0x0, 0x2D, 0x12 }, /* 0 2 */
562 { 0x0, 0x00, 0x00 }, /* 0 3 */
563 { 0x0, 0x23, 0x00 }, /* 1 0 */
564 { 0x0, 0x2B, 0x09 }, /* 1 1 */
565 { 0x0, 0x2E, 0x11 }, /* 1 2 */
566 { 0x0, 0x2F, 0x00 }, /* 2 0 */
567 { 0x0, 0x33, 0x0C }, /* 2 1 */
568 { 0x0, 0x00, 0x00 }, /* 3 0 */
571 static const struct ddi_buf_trans *
572 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
574 if (dev_priv->vbt.edp.low_vswing) {
575 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
576 return bdw_ddi_translations_edp;
578 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
579 return bdw_ddi_translations_dp;
583 static const struct ddi_buf_trans *
584 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
586 if (IS_SKL_ULX(dev_priv)) {
587 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
588 return skl_y_ddi_translations_dp;
589 } else if (IS_SKL_ULT(dev_priv)) {
590 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
591 return skl_u_ddi_translations_dp;
593 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
594 return skl_ddi_translations_dp;
598 static const struct ddi_buf_trans *
599 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
601 if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
602 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
603 return kbl_y_ddi_translations_dp;
604 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
605 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
606 return kbl_u_ddi_translations_dp;
608 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
609 return kbl_ddi_translations_dp;
613 static const struct ddi_buf_trans *
614 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
616 if (dev_priv->vbt.edp.low_vswing) {
617 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
618 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
619 return skl_y_ddi_translations_edp;
620 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
621 IS_CFL_ULT(dev_priv)) {
622 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
623 return skl_u_ddi_translations_edp;
625 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
626 return skl_ddi_translations_edp;
630 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
631 return kbl_get_buf_trans_dp(dev_priv, n_entries);
633 return skl_get_buf_trans_dp(dev_priv, n_entries);
636 static const struct ddi_buf_trans *
637 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
639 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
640 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
641 return skl_y_ddi_translations_hdmi;
643 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
644 return skl_ddi_translations_hdmi;
648 static int skl_buf_trans_num_entries(enum port port, int n_entries)
650 /* Only DDIA and DDIE can select the 10th register with DP */
651 if (port == PORT_A || port == PORT_E)
652 return min(n_entries, 10);
654 return min(n_entries, 9);
657 static const struct ddi_buf_trans *
658 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
659 enum port port, int *n_entries)
661 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
662 const struct ddi_buf_trans *ddi_translations =
663 kbl_get_buf_trans_dp(dev_priv, n_entries);
664 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
665 return ddi_translations;
666 } else if (IS_SKYLAKE(dev_priv)) {
667 const struct ddi_buf_trans *ddi_translations =
668 skl_get_buf_trans_dp(dev_priv, n_entries);
669 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
670 return ddi_translations;
671 } else if (IS_BROADWELL(dev_priv)) {
672 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
673 return bdw_ddi_translations_dp;
674 } else if (IS_HASWELL(dev_priv)) {
675 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
676 return hsw_ddi_translations_dp;
683 static const struct ddi_buf_trans *
684 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
685 enum port port, int *n_entries)
687 if (IS_GEN9_BC(dev_priv)) {
688 const struct ddi_buf_trans *ddi_translations =
689 skl_get_buf_trans_edp(dev_priv, n_entries);
690 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
691 return ddi_translations;
692 } else if (IS_BROADWELL(dev_priv)) {
693 return bdw_get_buf_trans_edp(dev_priv, n_entries);
694 } else if (IS_HASWELL(dev_priv)) {
695 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
696 return hsw_ddi_translations_dp;
703 static const struct ddi_buf_trans *
704 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
707 if (IS_BROADWELL(dev_priv)) {
708 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
709 return bdw_ddi_translations_fdi;
710 } else if (IS_HASWELL(dev_priv)) {
711 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
712 return hsw_ddi_translations_fdi;
719 static const struct ddi_buf_trans *
720 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
723 if (IS_GEN9_BC(dev_priv)) {
724 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
725 } else if (IS_BROADWELL(dev_priv)) {
726 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
727 return bdw_ddi_translations_hdmi;
728 } else if (IS_HASWELL(dev_priv)) {
729 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
730 return hsw_ddi_translations_hdmi;
737 static const struct bxt_ddi_buf_trans *
738 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
740 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
741 return bxt_ddi_translations_dp;
744 static const struct bxt_ddi_buf_trans *
745 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
747 if (dev_priv->vbt.edp.low_vswing) {
748 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
749 return bxt_ddi_translations_edp;
752 return bxt_get_buf_trans_dp(dev_priv, n_entries);
755 static const struct bxt_ddi_buf_trans *
756 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
758 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
759 return bxt_ddi_translations_hdmi;
762 static const struct cnl_ddi_buf_trans *
763 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
765 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
767 if (voltage == VOLTAGE_INFO_0_85V) {
768 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
769 return cnl_ddi_translations_hdmi_0_85V;
770 } else if (voltage == VOLTAGE_INFO_0_95V) {
771 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
772 return cnl_ddi_translations_hdmi_0_95V;
773 } else if (voltage == VOLTAGE_INFO_1_05V) {
774 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
775 return cnl_ddi_translations_hdmi_1_05V;
777 *n_entries = 1; /* shut up gcc */
778 MISSING_CASE(voltage);
783 static const struct cnl_ddi_buf_trans *
784 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
786 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
788 if (voltage == VOLTAGE_INFO_0_85V) {
789 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
790 return cnl_ddi_translations_dp_0_85V;
791 } else if (voltage == VOLTAGE_INFO_0_95V) {
792 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
793 return cnl_ddi_translations_dp_0_95V;
794 } else if (voltage == VOLTAGE_INFO_1_05V) {
795 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
796 return cnl_ddi_translations_dp_1_05V;
798 *n_entries = 1; /* shut up gcc */
799 MISSING_CASE(voltage);
804 static const struct cnl_ddi_buf_trans *
805 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
807 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
809 if (dev_priv->vbt.edp.low_vswing) {
810 if (voltage == VOLTAGE_INFO_0_85V) {
811 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
812 return cnl_ddi_translations_edp_0_85V;
813 } else if (voltage == VOLTAGE_INFO_0_95V) {
814 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
815 return cnl_ddi_translations_edp_0_95V;
816 } else if (voltage == VOLTAGE_INFO_1_05V) {
817 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
818 return cnl_ddi_translations_edp_1_05V;
820 *n_entries = 1; /* shut up gcc */
821 MISSING_CASE(voltage);
825 return cnl_get_buf_trans_dp(dev_priv, n_entries);
829 static const struct cnl_ddi_buf_trans *
830 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
831 int type, int rate, int *n_entries)
833 if (type == INTEL_OUTPUT_HDMI) {
834 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
835 return icl_combo_phy_ddi_translations_hdmi;
836 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
837 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
838 return icl_combo_phy_ddi_translations_edp_hbr3;
839 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
840 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
841 return icl_combo_phy_ddi_translations_edp_hbr2;
844 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
845 return icl_combo_phy_ddi_translations_dp_hbr2;
848 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
850 int n_entries, level, default_entry;
852 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
854 if (IS_ICELAKE(dev_priv)) {
855 if (intel_port_is_combophy(dev_priv, port))
856 icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
859 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
860 default_entry = n_entries - 1;
861 } else if (IS_CANNONLAKE(dev_priv)) {
862 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
863 default_entry = n_entries - 1;
864 } else if (IS_GEN9_LP(dev_priv)) {
865 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
866 default_entry = n_entries - 1;
867 } else if (IS_GEN9_BC(dev_priv)) {
868 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
870 } else if (IS_BROADWELL(dev_priv)) {
871 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
873 } else if (IS_HASWELL(dev_priv)) {
874 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
877 WARN(1, "ddi translation table missing\n");
881 /* Choose a good default if VBT is badly populated */
882 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
883 level = default_entry;
885 if (WARN_ON_ONCE(n_entries == 0))
887 if (WARN_ON_ONCE(level >= n_entries))
888 level = n_entries - 1;
894 * Starting with Haswell, DDI port buffers must be programmed with correct
895 * values in advance. This function programs the correct values for
896 * DP/eDP/FDI use cases.
898 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
899 const struct intel_crtc_state *crtc_state)
901 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
904 enum port port = encoder->port;
905 const struct ddi_buf_trans *ddi_translations;
907 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
908 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
910 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
911 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
914 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
917 /* If we're boosting the current, set bit 31 of trans1 */
918 if (IS_GEN9_BC(dev_priv) &&
919 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
920 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
922 for (i = 0; i < n_entries; i++) {
923 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
924 ddi_translations[i].trans1 | iboost_bit);
925 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
926 ddi_translations[i].trans2);
931 * Starting with Haswell, DDI port buffers must be programmed with correct
932 * values in advance. This function programs the correct values for
933 * HDMI/DVI use cases.
935 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
938 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
941 enum port port = encoder->port;
942 const struct ddi_buf_trans *ddi_translations;
944 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
946 if (WARN_ON_ONCE(!ddi_translations))
948 if (WARN_ON_ONCE(level >= n_entries))
949 level = n_entries - 1;
951 /* If we're boosting the current, set bit 31 of trans1 */
952 if (IS_GEN9_BC(dev_priv) &&
953 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
954 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
956 /* Entry 9 is for HDMI: */
957 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
958 ddi_translations[level].trans1 | iboost_bit);
959 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
960 ddi_translations[level].trans2);
963 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
966 i915_reg_t reg = DDI_BUF_CTL(port);
969 for (i = 0; i < 16; i++) {
971 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
974 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
977 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
979 switch (pll->info->id) {
981 return PORT_CLK_SEL_WRPLL1;
983 return PORT_CLK_SEL_WRPLL2;
985 return PORT_CLK_SEL_SPLL;
986 case DPLL_ID_LCPLL_810:
987 return PORT_CLK_SEL_LCPLL_810;
988 case DPLL_ID_LCPLL_1350:
989 return PORT_CLK_SEL_LCPLL_1350;
990 case DPLL_ID_LCPLL_2700:
991 return PORT_CLK_SEL_LCPLL_2700;
993 MISSING_CASE(pll->info->id);
994 return PORT_CLK_SEL_NONE;
998 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
999 const struct intel_crtc_state *crtc_state)
1001 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1002 int clock = crtc_state->port_clock;
1003 const enum intel_dpll_id id = pll->info->id;
1008 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1009 * here, so do warn if this get passed in
1012 return DDI_CLK_SEL_NONE;
1013 case DPLL_ID_ICL_TBTPLL:
1016 return DDI_CLK_SEL_TBT_162;
1018 return DDI_CLK_SEL_TBT_270;
1020 return DDI_CLK_SEL_TBT_540;
1022 return DDI_CLK_SEL_TBT_810;
1024 MISSING_CASE(clock);
1025 return DDI_CLK_SEL_NONE;
1027 case DPLL_ID_ICL_MGPLL1:
1028 case DPLL_ID_ICL_MGPLL2:
1029 case DPLL_ID_ICL_MGPLL3:
1030 case DPLL_ID_ICL_MGPLL4:
1031 return DDI_CLK_SEL_MG;
1035 /* Starting with Haswell, different DDI ports can work in FDI mode for
1036 * connection to the PCH-located connectors. For this, it is necessary to train
1037 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1039 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1040 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1041 * DDI A (which is used for eDP)
1044 void hsw_fdi_link_train(struct intel_crtc *crtc,
1045 const struct intel_crtc_state *crtc_state)
1047 struct drm_device *dev = crtc->base.dev;
1048 struct drm_i915_private *dev_priv = to_i915(dev);
1049 struct intel_encoder *encoder;
1050 u32 temp, i, rx_ctl_val, ddi_pll_sel;
1052 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1053 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1054 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1057 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1058 * mode set "sequence for CRT port" document:
1059 * - TP1 to TP2 time with the default value
1060 * - FDI delay to 90h
1062 * WaFDIAutoLinkSetTimingOverrride:hsw
1064 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1065 FDI_RX_PWRDN_LANE0_VAL(2) |
1066 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1068 /* Enable the PCH Receiver FDI PLL */
1069 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1071 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1072 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1073 POSTING_READ(FDI_RX_CTL(PIPE_A));
1076 /* Switch from Rawclk to PCDclk */
1077 rx_ctl_val |= FDI_PCDCLK;
1078 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1080 /* Configure Port Clock Select */
1081 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1082 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1083 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1085 /* Start the training iterating through available voltages and emphasis,
1086 * testing each value twice. */
1087 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1088 /* Configure DP_TP_CTL with auto-training */
1089 I915_WRITE(DP_TP_CTL(PORT_E),
1090 DP_TP_CTL_FDI_AUTOTRAIN |
1091 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1092 DP_TP_CTL_LINK_TRAIN_PAT1 |
1095 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1096 * DDI E does not support port reversal, the functionality is
1097 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1098 * port reversal bit */
1099 I915_WRITE(DDI_BUF_CTL(PORT_E),
1100 DDI_BUF_CTL_ENABLE |
1101 ((crtc_state->fdi_lanes - 1) << 1) |
1102 DDI_BUF_TRANS_SELECT(i / 2));
1103 POSTING_READ(DDI_BUF_CTL(PORT_E));
1107 /* Program PCH FDI Receiver TU */
1108 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1110 /* Enable PCH FDI Receiver with auto-training */
1111 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1112 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1113 POSTING_READ(FDI_RX_CTL(PIPE_A));
1115 /* Wait for FDI receiver lane calibration */
1118 /* Unset FDI_RX_MISC pwrdn lanes */
1119 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1120 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1121 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1122 POSTING_READ(FDI_RX_MISC(PIPE_A));
1124 /* Wait for FDI auto training time */
1127 temp = I915_READ(DP_TP_STATUS(PORT_E));
1128 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1129 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1134 * Leave things enabled even if we failed to train FDI.
1135 * Results in less fireworks from the state checker.
1137 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1138 DRM_ERROR("FDI link training failed!\n");
1142 rx_ctl_val &= ~FDI_RX_ENABLE;
1143 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1144 POSTING_READ(FDI_RX_CTL(PIPE_A));
1146 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1147 temp &= ~DDI_BUF_CTL_ENABLE;
1148 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1149 POSTING_READ(DDI_BUF_CTL(PORT_E));
1151 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1152 temp = I915_READ(DP_TP_CTL(PORT_E));
1153 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1154 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1155 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1156 POSTING_READ(DP_TP_CTL(PORT_E));
1158 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1160 /* Reset FDI_RX_MISC pwrdn lanes */
1161 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1162 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1163 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1164 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1165 POSTING_READ(FDI_RX_MISC(PIPE_A));
1168 /* Enable normal pixel sending for FDI */
1169 I915_WRITE(DP_TP_CTL(PORT_E),
1170 DP_TP_CTL_FDI_AUTOTRAIN |
1171 DP_TP_CTL_LINK_TRAIN_NORMAL |
1172 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1176 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1178 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1179 struct intel_digital_port *intel_dig_port =
1180 enc_to_dig_port(&encoder->base);
1182 intel_dp->DP = intel_dig_port->saved_port_bits |
1183 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1184 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1187 static struct intel_encoder *
1188 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1190 struct drm_device *dev = crtc->base.dev;
1191 struct intel_encoder *encoder, *ret = NULL;
1192 int num_encoders = 0;
1194 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1199 if (num_encoders != 1)
1200 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1201 pipe_name(crtc->pipe));
1203 BUG_ON(ret == NULL);
1207 #define LC_FREQ 2700
1209 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1212 int refclk = LC_FREQ;
1216 wrpll = I915_READ(reg);
1217 switch (wrpll & WRPLL_PLL_REF_MASK) {
1219 case WRPLL_PLL_NON_SSC:
1221 * We could calculate spread here, but our checking
1222 * code only cares about 5% accuracy, and spread is a max of
1227 case WRPLL_PLL_LCPLL:
1231 WARN(1, "bad wrpll refclk\n");
1235 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1236 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1237 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1239 /* Convert to KHz, p & r have a fixed point portion */
1240 return (refclk * n * 100) / (p * r);
1243 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1244 enum intel_dpll_id pll_id)
1246 i915_reg_t cfgcr1_reg, cfgcr2_reg;
1247 u32 cfgcr1_val, cfgcr2_val;
1248 u32 p0, p1, p2, dco_freq;
1250 cfgcr1_reg = DPLL_CFGCR1(pll_id);
1251 cfgcr2_reg = DPLL_CFGCR2(pll_id);
1253 cfgcr1_val = I915_READ(cfgcr1_reg);
1254 cfgcr2_val = I915_READ(cfgcr2_reg);
1256 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1257 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1259 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1260 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1266 case DPLL_CFGCR2_PDIV_1:
1269 case DPLL_CFGCR2_PDIV_2:
1272 case DPLL_CFGCR2_PDIV_3:
1275 case DPLL_CFGCR2_PDIV_7:
1281 case DPLL_CFGCR2_KDIV_5:
1284 case DPLL_CFGCR2_KDIV_2:
1287 case DPLL_CFGCR2_KDIV_3:
1290 case DPLL_CFGCR2_KDIV_1:
1295 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1297 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1300 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1303 return dco_freq / (p0 * p1 * p2 * 5);
1306 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1307 enum intel_dpll_id pll_id)
1310 u32 p0, p1, p2, dco_freq, ref_clock;
1312 if (INTEL_GEN(dev_priv) >= 11) {
1313 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1314 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1316 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1317 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1320 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1321 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1323 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1324 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1325 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1331 case DPLL_CFGCR1_PDIV_2:
1334 case DPLL_CFGCR1_PDIV_3:
1337 case DPLL_CFGCR1_PDIV_5:
1340 case DPLL_CFGCR1_PDIV_7:
1346 case DPLL_CFGCR1_KDIV_1:
1349 case DPLL_CFGCR1_KDIV_2:
1352 case DPLL_CFGCR1_KDIV_4:
1357 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1359 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1361 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1362 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1364 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1367 return dco_freq / (p0 * p1 * p2 * 5);
1370 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1373 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1376 case DDI_CLK_SEL_NONE:
1378 case DDI_CLK_SEL_TBT_162:
1380 case DDI_CLK_SEL_TBT_270:
1382 case DDI_CLK_SEL_TBT_540:
1384 case DDI_CLK_SEL_TBT_810:
1392 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1395 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
1396 u32 mg_pll_div0, mg_clktop_hsclkctl;
1397 u32 m1, m2_int, m2_frac, div1, div2, refclk;
1400 refclk = dev_priv->cdclk.hw.ref;
1402 mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));
1403 mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));
1405 m1 = I915_READ(MG_PLL_DIV1(tc_port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1406 m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1407 m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1408 (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1409 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1411 switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1412 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1415 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1418 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1421 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1425 MISSING_CASE(mg_clktop_hsclkctl);
1429 div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1430 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1431 /* div2 value of 0 is same as 1 means no div */
1436 * Adjust the original formula to delay the division by 2^22 in order to
1437 * minimize possible rounding errors.
1439 tmp = (u64)m1 * m2_int * refclk +
1440 (((u64)m1 * m2_frac * refclk) >> 22);
1441 tmp = div_u64(tmp, 5 * div1 * div2);
1446 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1450 if (pipe_config->has_pch_encoder)
1451 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1452 &pipe_config->fdi_m_n);
1453 else if (intel_crtc_has_dp_encoder(pipe_config))
1454 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1455 &pipe_config->dp_m_n);
1456 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1457 dotclock = pipe_config->port_clock * 2 / 3;
1459 dotclock = pipe_config->port_clock;
1461 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1464 if (pipe_config->pixel_multiplier)
1465 dotclock /= pipe_config->pixel_multiplier;
1467 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1470 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1471 struct intel_crtc_state *pipe_config)
1473 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1474 enum port port = encoder->port;
1478 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1479 if (intel_port_is_combophy(dev_priv, port)) {
1480 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1481 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1483 link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1486 if (pll_id == DPLL_ID_ICL_TBTPLL)
1487 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1489 link_clock = icl_calc_mg_pll_link(dev_priv, port);
1492 pipe_config->port_clock = link_clock;
1493 ddi_dotclock_get(pipe_config);
1496 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1497 struct intel_crtc_state *pipe_config)
1499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1502 enum intel_dpll_id pll_id;
1504 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1506 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1508 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1509 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1511 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1513 switch (link_clock) {
1514 case DPLL_CFGCR0_LINK_RATE_810:
1517 case DPLL_CFGCR0_LINK_RATE_1080:
1518 link_clock = 108000;
1520 case DPLL_CFGCR0_LINK_RATE_1350:
1521 link_clock = 135000;
1523 case DPLL_CFGCR0_LINK_RATE_1620:
1524 link_clock = 162000;
1526 case DPLL_CFGCR0_LINK_RATE_2160:
1527 link_clock = 216000;
1529 case DPLL_CFGCR0_LINK_RATE_2700:
1530 link_clock = 270000;
1532 case DPLL_CFGCR0_LINK_RATE_3240:
1533 link_clock = 324000;
1535 case DPLL_CFGCR0_LINK_RATE_4050:
1536 link_clock = 405000;
1539 WARN(1, "Unsupported link rate\n");
1545 pipe_config->port_clock = link_clock;
1547 ddi_dotclock_get(pipe_config);
1550 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1551 struct intel_crtc_state *pipe_config)
1553 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1556 enum intel_dpll_id pll_id;
1558 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1560 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1562 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1563 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1565 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1566 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1568 switch (link_clock) {
1569 case DPLL_CTRL1_LINK_RATE_810:
1572 case DPLL_CTRL1_LINK_RATE_1080:
1573 link_clock = 108000;
1575 case DPLL_CTRL1_LINK_RATE_1350:
1576 link_clock = 135000;
1578 case DPLL_CTRL1_LINK_RATE_1620:
1579 link_clock = 162000;
1581 case DPLL_CTRL1_LINK_RATE_2160:
1582 link_clock = 216000;
1584 case DPLL_CTRL1_LINK_RATE_2700:
1585 link_clock = 270000;
1588 WARN(1, "Unsupported link rate\n");
1594 pipe_config->port_clock = link_clock;
1596 ddi_dotclock_get(pipe_config);
1599 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1600 struct intel_crtc_state *pipe_config)
1602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1606 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1607 switch (val & PORT_CLK_SEL_MASK) {
1608 case PORT_CLK_SEL_LCPLL_810:
1611 case PORT_CLK_SEL_LCPLL_1350:
1612 link_clock = 135000;
1614 case PORT_CLK_SEL_LCPLL_2700:
1615 link_clock = 270000;
1617 case PORT_CLK_SEL_WRPLL1:
1618 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1620 case PORT_CLK_SEL_WRPLL2:
1621 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1623 case PORT_CLK_SEL_SPLL:
1624 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1625 if (pll == SPLL_PLL_FREQ_810MHz)
1627 else if (pll == SPLL_PLL_FREQ_1350MHz)
1628 link_clock = 135000;
1629 else if (pll == SPLL_PLL_FREQ_2700MHz)
1630 link_clock = 270000;
1632 WARN(1, "bad spll freq\n");
1637 WARN(1, "bad port clock sel\n");
1641 pipe_config->port_clock = link_clock * 2;
1643 ddi_dotclock_get(pipe_config);
1646 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1648 struct intel_dpll_hw_state *state;
1651 /* For DDI ports we always use a shared PLL. */
1652 if (WARN_ON(!crtc_state->shared_dpll))
1655 state = &crtc_state->dpll_hw_state;
1658 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1659 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1660 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1661 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1662 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1663 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1665 return chv_calc_dpll_params(100000, &clock);
1668 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1669 struct intel_crtc_state *pipe_config)
1671 pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1673 ddi_dotclock_get(pipe_config);
1676 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1677 struct intel_crtc_state *pipe_config)
1679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1681 if (IS_ICELAKE(dev_priv))
1682 icl_ddi_clock_get(encoder, pipe_config);
1683 else if (IS_CANNONLAKE(dev_priv))
1684 cnl_ddi_clock_get(encoder, pipe_config);
1685 else if (IS_GEN9_LP(dev_priv))
1686 bxt_ddi_clock_get(encoder, pipe_config);
1687 else if (IS_GEN9_BC(dev_priv))
1688 skl_ddi_clock_get(encoder, pipe_config);
1689 else if (INTEL_GEN(dev_priv) <= 8)
1690 hsw_ddi_clock_get(encoder, pipe_config);
1693 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1695 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1696 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1697 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1700 if (!intel_crtc_has_dp_encoder(crtc_state))
1703 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1705 temp = TRANS_MSA_SYNC_CLK;
1707 if (crtc_state->limited_color_range)
1708 temp |= TRANS_MSA_CEA_RANGE;
1710 switch (crtc_state->pipe_bpp) {
1712 temp |= TRANS_MSA_6_BPC;
1715 temp |= TRANS_MSA_8_BPC;
1718 temp |= TRANS_MSA_10_BPC;
1721 temp |= TRANS_MSA_12_BPC;
1724 MISSING_CASE(crtc_state->pipe_bpp);
1729 * As per DP 1.2 spec section 2.3.4.3 while sending
1730 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1731 * colorspace information. The output colorspace encoding is BT601.
1733 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1734 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1735 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1738 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1741 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1742 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1743 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1746 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1748 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1750 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1751 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1754 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1756 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1757 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1758 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1759 enum pipe pipe = crtc->pipe;
1760 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1761 enum port port = encoder->port;
1764 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1765 temp = TRANS_DDI_FUNC_ENABLE;
1766 temp |= TRANS_DDI_SELECT_PORT(port);
1768 switch (crtc_state->pipe_bpp) {
1770 temp |= TRANS_DDI_BPC_6;
1773 temp |= TRANS_DDI_BPC_8;
1776 temp |= TRANS_DDI_BPC_10;
1779 temp |= TRANS_DDI_BPC_12;
1785 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1786 temp |= TRANS_DDI_PVSYNC;
1787 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1788 temp |= TRANS_DDI_PHSYNC;
1790 if (cpu_transcoder == TRANSCODER_EDP) {
1793 /* On Haswell, can only use the always-on power well for
1794 * eDP when not using the panel fitter, and when not
1795 * using motion blur mitigation (which we don't
1797 if (IS_HASWELL(dev_priv) &&
1798 (crtc_state->pch_pfit.enabled ||
1799 crtc_state->pch_pfit.force_thru))
1800 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1802 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1805 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1808 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1816 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1817 if (crtc_state->has_hdmi_sink)
1818 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1820 temp |= TRANS_DDI_MODE_SELECT_DVI;
1822 if (crtc_state->hdmi_scrambling)
1823 temp |= TRANS_DDI_HDMI_SCRAMBLING;
1824 if (crtc_state->hdmi_high_tmds_clock_ratio)
1825 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1826 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1827 temp |= TRANS_DDI_MODE_SELECT_FDI;
1828 temp |= (crtc_state->fdi_lanes - 1) << 1;
1829 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1830 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1831 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1833 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1834 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1837 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1840 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1842 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1843 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1844 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1845 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1846 u32 val = I915_READ(reg);
1848 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1849 val |= TRANS_DDI_PORT_NONE;
1850 I915_WRITE(reg, val);
1852 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1853 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1854 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1855 /* Quirk time at 100ms for reliable operation */
1860 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1863 struct drm_device *dev = intel_encoder->base.dev;
1864 struct drm_i915_private *dev_priv = to_i915(dev);
1865 intel_wakeref_t wakeref;
1870 wakeref = intel_display_power_get_if_enabled(dev_priv,
1871 intel_encoder->power_domain);
1872 if (WARN_ON(!wakeref))
1875 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1880 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1882 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1884 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1885 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1887 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1891 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1893 struct drm_device *dev = intel_connector->base.dev;
1894 struct drm_i915_private *dev_priv = to_i915(dev);
1895 struct intel_encoder *encoder = intel_connector->encoder;
1896 int type = intel_connector->base.connector_type;
1897 enum port port = encoder->port;
1898 enum transcoder cpu_transcoder;
1899 intel_wakeref_t wakeref;
1904 wakeref = intel_display_power_get_if_enabled(dev_priv,
1905 encoder->power_domain);
1909 if (!encoder->get_hw_state(encoder, &pipe)) {
1915 cpu_transcoder = TRANSCODER_EDP;
1917 cpu_transcoder = (enum transcoder) pipe;
1919 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1921 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1922 case TRANS_DDI_MODE_SELECT_HDMI:
1923 case TRANS_DDI_MODE_SELECT_DVI:
1924 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1927 case TRANS_DDI_MODE_SELECT_DP_SST:
1928 ret = type == DRM_MODE_CONNECTOR_eDP ||
1929 type == DRM_MODE_CONNECTOR_DisplayPort;
1932 case TRANS_DDI_MODE_SELECT_DP_MST:
1933 /* if the transcoder is in MST state then
1934 * connector isn't connected */
1938 case TRANS_DDI_MODE_SELECT_FDI:
1939 ret = type == DRM_MODE_CONNECTOR_VGA;
1948 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1953 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1954 u8 *pipe_mask, bool *is_dp_mst)
1956 struct drm_device *dev = encoder->base.dev;
1957 struct drm_i915_private *dev_priv = to_i915(dev);
1958 enum port port = encoder->port;
1959 intel_wakeref_t wakeref;
1967 wakeref = intel_display_power_get_if_enabled(dev_priv,
1968 encoder->power_domain);
1972 tmp = I915_READ(DDI_BUF_CTL(port));
1973 if (!(tmp & DDI_BUF_CTL_ENABLE))
1976 if (port == PORT_A) {
1977 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1979 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1981 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1983 case TRANS_DDI_EDP_INPUT_A_ON:
1984 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1985 *pipe_mask = BIT(PIPE_A);
1987 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1988 *pipe_mask = BIT(PIPE_B);
1990 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1991 *pipe_mask = BIT(PIPE_C);
1999 for_each_pipe(dev_priv, p) {
2000 enum transcoder cpu_transcoder = (enum transcoder)p;
2002 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2004 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
2007 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2008 TRANS_DDI_MODE_SELECT_DP_MST)
2009 mst_pipe_mask |= BIT(p);
2011 *pipe_mask |= BIT(p);
2015 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2018 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2019 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2020 port_name(port), *pipe_mask);
2021 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2024 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2025 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2026 port_name(port), *pipe_mask, mst_pipe_mask);
2028 *is_dp_mst = mst_pipe_mask;
2031 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2032 tmp = I915_READ(BXT_PHY_CTL(port));
2033 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2034 BXT_PHY_LANE_POWERDOWN_ACK |
2035 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2036 DRM_ERROR("Port %c enabled but PHY powered down? "
2037 "(PHY_CTL %08x)\n", port_name(port), tmp);
2040 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2043 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2049 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2051 if (is_mst || !pipe_mask)
2054 *pipe = ffs(pipe_mask) - 1;
2059 static inline enum intel_display_power_domain
2060 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2062 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2063 * DC states enabled at the same time, while for driver initiated AUX
2064 * transfers we need the same AUX IOs to be powered but with DC states
2065 * disabled. Accordingly use the AUX power domain here which leaves DC
2067 * However, for non-A AUX ports the corresponding non-EDP transcoders
2068 * would have already enabled power well 2 and DC_OFF. This means we can
2069 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2070 * specific AUX_IO reference without powering up any extra wells.
2071 * Note that PSR is enabled only on Port A even though this function
2072 * returns the correct domain for other ports too.
2074 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2075 intel_aux_power_domain(dig_port);
2078 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2079 struct intel_crtc_state *crtc_state)
2081 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2082 struct intel_digital_port *dig_port;
2086 * TODO: Add support for MST encoders. Atm, the following should never
2087 * happen since fake-MST encoders don't set their get_power_domains()
2090 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2093 dig_port = enc_to_dig_port(&encoder->base);
2094 domains = BIT_ULL(dig_port->ddi_io_power_domain);
2097 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2100 if (intel_crtc_has_dp_encoder(crtc_state) ||
2101 intel_port_is_tc(dev_priv, encoder->port))
2102 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
2105 * VDSC power is needed when DSC is enabled
2107 if (crtc_state->dsc_params.compression_enable)
2108 domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
2113 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2115 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2116 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2117 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2118 enum port port = encoder->port;
2119 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2121 if (cpu_transcoder != TRANSCODER_EDP)
2122 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2123 TRANS_CLK_SEL_PORT(port));
2126 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2128 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2129 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2131 if (cpu_transcoder != TRANSCODER_EDP)
2132 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2133 TRANS_CLK_SEL_DISABLED);
2136 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2137 enum port port, u8 iboost)
2141 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2142 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2144 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2146 tmp |= BALANCE_LEG_DISABLE(port);
2147 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2150 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2151 int level, enum intel_output_type type)
2153 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2155 enum port port = encoder->port;
2158 if (type == INTEL_OUTPUT_HDMI)
2159 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2161 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2164 const struct ddi_buf_trans *ddi_translations;
2167 if (type == INTEL_OUTPUT_HDMI)
2168 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2169 else if (type == INTEL_OUTPUT_EDP)
2170 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2172 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2174 if (WARN_ON_ONCE(!ddi_translations))
2176 if (WARN_ON_ONCE(level >= n_entries))
2177 level = n_entries - 1;
2179 iboost = ddi_translations[level].i_boost;
2182 /* Make sure that the requested I_boost is valid */
2183 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2184 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2188 _skl_ddi_set_iboost(dev_priv, port, iboost);
2190 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2191 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2194 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2195 int level, enum intel_output_type type)
2197 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2198 const struct bxt_ddi_buf_trans *ddi_translations;
2199 enum port port = encoder->port;
2202 if (type == INTEL_OUTPUT_HDMI)
2203 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2204 else if (type == INTEL_OUTPUT_EDP)
2205 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2207 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2209 if (WARN_ON_ONCE(!ddi_translations))
2211 if (WARN_ON_ONCE(level >= n_entries))
2212 level = n_entries - 1;
2214 bxt_ddi_phy_set_signal_level(dev_priv, port,
2215 ddi_translations[level].margin,
2216 ddi_translations[level].scale,
2217 ddi_translations[level].enable,
2218 ddi_translations[level].deemphasis);
2221 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2223 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2224 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2225 enum port port = encoder->port;
2228 if (IS_ICELAKE(dev_priv)) {
2229 if (intel_port_is_combophy(dev_priv, port))
2230 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2231 intel_dp->link_rate, &n_entries);
2233 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2234 } else if (IS_CANNONLAKE(dev_priv)) {
2235 if (encoder->type == INTEL_OUTPUT_EDP)
2236 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2238 cnl_get_buf_trans_dp(dev_priv, &n_entries);
2239 } else if (IS_GEN9_LP(dev_priv)) {
2240 if (encoder->type == INTEL_OUTPUT_EDP)
2241 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2243 bxt_get_buf_trans_dp(dev_priv, &n_entries);
2245 if (encoder->type == INTEL_OUTPUT_EDP)
2246 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2248 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2251 if (WARN_ON(n_entries < 1))
2253 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2254 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2256 return index_to_dp_signal_levels[n_entries - 1] &
2257 DP_TRAIN_VOLTAGE_SWING_MASK;
2261 * We assume that the full set of pre-emphasis values can be
2262 * used on all DDI platforms. Should that change we need to
2263 * rethink this code.
2265 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2267 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2268 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2269 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2270 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2271 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2272 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2273 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2274 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2276 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2280 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2281 int level, enum intel_output_type type)
2283 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2284 const struct cnl_ddi_buf_trans *ddi_translations;
2285 enum port port = encoder->port;
2289 if (type == INTEL_OUTPUT_HDMI)
2290 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2291 else if (type == INTEL_OUTPUT_EDP)
2292 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2294 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2296 if (WARN_ON_ONCE(!ddi_translations))
2298 if (WARN_ON_ONCE(level >= n_entries))
2299 level = n_entries - 1;
2301 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2302 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2303 val &= ~SCALING_MODE_SEL_MASK;
2304 val |= SCALING_MODE_SEL(2);
2305 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2307 /* Program PORT_TX_DW2 */
2308 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2309 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2311 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2312 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2313 /* Rcomp scalar is fixed as 0x98 for every table entry */
2314 val |= RCOMP_SCALAR(0x98);
2315 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2317 /* Program PORT_TX_DW4 */
2318 /* We cannot write to GRP. It would overrite individual loadgen */
2319 for (ln = 0; ln < 4; ln++) {
2320 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2321 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2323 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2324 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2325 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2326 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2329 /* Program PORT_TX_DW5 */
2330 /* All DW5 values are fixed for every table entry */
2331 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2332 val &= ~RTERM_SELECT_MASK;
2333 val |= RTERM_SELECT(6);
2334 val |= TAP3_DISABLE;
2335 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2337 /* Program PORT_TX_DW7 */
2338 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2339 val &= ~N_SCALAR_MASK;
2340 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2341 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2344 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2345 int level, enum intel_output_type type)
2347 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2348 enum port port = encoder->port;
2349 int width, rate, ln;
2352 if (type == INTEL_OUTPUT_HDMI) {
2354 rate = 0; /* Rate is always < than 6GHz for HDMI */
2356 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2358 width = intel_dp->lane_count;
2359 rate = intel_dp->link_rate;
2363 * 1. If port type is eDP or DP,
2364 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2367 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2368 if (type != INTEL_OUTPUT_HDMI)
2369 val |= COMMON_KEEPER_EN;
2371 val &= ~COMMON_KEEPER_EN;
2372 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2374 /* 2. Program loadgen select */
2376 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2377 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2378 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2379 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2381 for (ln = 0; ln <= 3; ln++) {
2382 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2383 val &= ~LOADGEN_SELECT;
2385 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2386 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2387 val |= LOADGEN_SELECT;
2389 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2392 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2393 val = I915_READ(CNL_PORT_CL1CM_DW5);
2394 val |= SUS_CLOCK_CONFIG;
2395 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2397 /* 4. Clear training enable to change swing values */
2398 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2399 val &= ~TX_TRAINING_EN;
2400 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2402 /* 5. Program swing and de-emphasis */
2403 cnl_ddi_vswing_program(encoder, level, type);
2405 /* 6. Set training enable to trigger update */
2406 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2407 val |= TX_TRAINING_EN;
2408 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2411 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2412 u32 level, enum port port, int type,
2415 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2419 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2421 if (!ddi_translations)
2424 if (level >= n_entries) {
2425 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2426 level = n_entries - 1;
2429 /* Set PORT_TX_DW5 */
2430 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2431 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2432 TAP2_DISABLE | TAP3_DISABLE);
2433 val |= SCALING_MODE_SEL(0x2);
2434 val |= RTERM_SELECT(0x6);
2435 val |= TAP3_DISABLE;
2436 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2438 /* Program PORT_TX_DW2 */
2439 val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2440 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2442 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2443 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2444 /* Program Rcomp scalar for every table entry */
2445 val |= RCOMP_SCALAR(0x98);
2446 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2448 /* Program PORT_TX_DW4 */
2449 /* We cannot write to GRP. It would overwrite individual loadgen. */
2450 for (ln = 0; ln <= 3; ln++) {
2451 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2452 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2454 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2455 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2456 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2457 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2460 /* Program PORT_TX_DW7 */
2461 val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2462 val &= ~N_SCALAR_MASK;
2463 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2464 I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
2467 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2469 enum intel_output_type type)
2471 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2472 enum port port = encoder->port;
2478 if (type == INTEL_OUTPUT_HDMI) {
2480 /* Rate is always < than 6GHz for HDMI */
2482 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2484 width = intel_dp->lane_count;
2485 rate = intel_dp->link_rate;
2489 * 1. If port type is eDP or DP,
2490 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2493 val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2494 if (type == INTEL_OUTPUT_HDMI)
2495 val &= ~COMMON_KEEPER_EN;
2497 val |= COMMON_KEEPER_EN;
2498 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2500 /* 2. Program loadgen select */
2502 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2503 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2504 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2505 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2507 for (ln = 0; ln <= 3; ln++) {
2508 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2509 val &= ~LOADGEN_SELECT;
2511 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2512 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2513 val |= LOADGEN_SELECT;
2515 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2518 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2519 val = I915_READ(ICL_PORT_CL_DW5(port));
2520 val |= SUS_CLOCK_CONFIG;
2521 I915_WRITE(ICL_PORT_CL_DW5(port), val);
2523 /* 4. Clear training enable to change swing values */
2524 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2525 val &= ~TX_TRAINING_EN;
2526 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2528 /* 5. Program swing and de-emphasis */
2529 icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
2531 /* 6. Set training enable to trigger update */
2532 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2533 val |= TX_TRAINING_EN;
2534 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2537 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2541 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2542 enum port port = encoder->port;
2543 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2547 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2548 ddi_translations = icl_mg_phy_ddi_translations;
2549 /* The table does not have values for level 3 and level 9. */
2550 if (level >= n_entries || level == 3 || level == 9) {
2551 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2552 level, n_entries - 2);
2553 level = n_entries - 2;
2556 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2557 for (ln = 0; ln < 2; ln++) {
2558 val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
2559 val &= ~CRI_USE_FS32;
2560 I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
2562 val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
2563 val &= ~CRI_USE_FS32;
2564 I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
2567 /* Program MG_TX_SWINGCTRL with values from vswing table */
2568 for (ln = 0; ln < 2; ln++) {
2569 val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
2570 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2571 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2572 ddi_translations[level].cri_txdeemph_override_17_12);
2573 I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
2575 val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
2576 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2577 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2578 ddi_translations[level].cri_txdeemph_override_17_12);
2579 I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
2582 /* Program MG_TX_DRVCTRL with values from vswing table */
2583 for (ln = 0; ln < 2; ln++) {
2584 val = I915_READ(MG_TX1_DRVCTRL(port, ln));
2585 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2586 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2587 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2588 ddi_translations[level].cri_txdeemph_override_5_0) |
2589 CRI_TXDEEMPH_OVERRIDE_11_6(
2590 ddi_translations[level].cri_txdeemph_override_11_6) |
2591 CRI_TXDEEMPH_OVERRIDE_EN;
2592 I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
2594 val = I915_READ(MG_TX2_DRVCTRL(port, ln));
2595 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2596 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2597 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2598 ddi_translations[level].cri_txdeemph_override_5_0) |
2599 CRI_TXDEEMPH_OVERRIDE_11_6(
2600 ddi_translations[level].cri_txdeemph_override_11_6) |
2601 CRI_TXDEEMPH_OVERRIDE_EN;
2602 I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
2604 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2608 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2609 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2610 * values from table for which TX1 and TX2 enabled.
2612 for (ln = 0; ln < 2; ln++) {
2613 val = I915_READ(MG_CLKHUB(port, ln));
2614 if (link_clock < 300000)
2615 val |= CFG_LOW_RATE_LKREN_EN;
2617 val &= ~CFG_LOW_RATE_LKREN_EN;
2618 I915_WRITE(MG_CLKHUB(port, ln), val);
2621 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2622 for (ln = 0; ln < 2; ln++) {
2623 val = I915_READ(MG_TX1_DCC(port, ln));
2624 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2625 if (link_clock <= 500000) {
2626 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2628 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2629 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2631 I915_WRITE(MG_TX1_DCC(port, ln), val);
2633 val = I915_READ(MG_TX2_DCC(port, ln));
2634 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2635 if (link_clock <= 500000) {
2636 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2638 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2639 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2641 I915_WRITE(MG_TX2_DCC(port, ln), val);
2644 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2645 for (ln = 0; ln < 2; ln++) {
2646 val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
2647 val |= CRI_CALCINIT;
2648 I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
2650 val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
2651 val |= CRI_CALCINIT;
2652 I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
2656 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2659 enum intel_output_type type)
2661 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2662 enum port port = encoder->port;
2664 if (intel_port_is_combophy(dev_priv, port))
2665 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2667 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2670 static u32 translate_signal_level(int signal_levels)
2674 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2675 if (index_to_dp_signal_levels[i] == signal_levels)
2679 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2685 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2687 u8 train_set = intel_dp->train_set[0];
2688 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2689 DP_TRAIN_PRE_EMPHASIS_MASK);
2691 return translate_signal_level(signal_levels);
2694 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2696 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2697 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2698 struct intel_encoder *encoder = &dport->base;
2699 int level = intel_ddi_dp_level(intel_dp);
2701 if (IS_ICELAKE(dev_priv))
2702 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2703 level, encoder->type);
2704 else if (IS_CANNONLAKE(dev_priv))
2705 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2707 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2712 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2714 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2715 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2716 struct intel_encoder *encoder = &dport->base;
2717 int level = intel_ddi_dp_level(intel_dp);
2719 if (IS_GEN9_BC(dev_priv))
2720 skl_ddi_set_iboost(encoder, level, encoder->type);
2722 return DDI_BUF_TRANS_SELECT(level);
2726 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2729 if (intel_port_is_combophy(dev_priv, port)) {
2730 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2731 } else if (intel_port_is_tc(dev_priv, port)) {
2732 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2734 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2740 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2741 const struct intel_crtc_state *crtc_state)
2743 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2744 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2745 enum port port = encoder->port;
2748 mutex_lock(&dev_priv->dpll_lock);
2750 val = I915_READ(DPCLKA_CFGCR0_ICL);
2751 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2753 if (intel_port_is_combophy(dev_priv, port)) {
2754 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2755 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2756 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2757 POSTING_READ(DPCLKA_CFGCR0_ICL);
2760 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2761 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2763 mutex_unlock(&dev_priv->dpll_lock);
2766 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2768 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2769 enum port port = encoder->port;
2772 mutex_lock(&dev_priv->dpll_lock);
2774 val = I915_READ(DPCLKA_CFGCR0_ICL);
2775 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2776 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2778 mutex_unlock(&dev_priv->dpll_lock);
2781 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2783 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2787 bool ddi_clk_needed;
2790 * In case of DP MST, we sanitize the primary encoder only, not the
2793 if (encoder->type == INTEL_OUTPUT_DP_MST)
2796 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2800 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2802 * In the unlikely case that BIOS enables DP in MST mode, just
2803 * warn since our MST HW readout is incomplete.
2805 if (WARN_ON(is_mst))
2809 port_mask = BIT(encoder->port);
2810 ddi_clk_needed = encoder->base.crtc;
2812 if (encoder->type == INTEL_OUTPUT_DSI) {
2813 struct intel_encoder *other_encoder;
2815 port_mask = intel_dsi_encoder_ports(encoder);
2817 * Sanity check that we haven't incorrectly registered another
2818 * encoder using any of the ports of this DSI encoder.
2820 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2821 if (other_encoder == encoder)
2824 if (WARN_ON(port_mask & BIT(other_encoder->port)))
2828 * DSI ports should have their DDI clock ungated when disabled
2829 * and gated when enabled.
2831 ddi_clk_needed = !encoder->base.crtc;
2834 val = I915_READ(DPCLKA_CFGCR0_ICL);
2835 for_each_port_masked(port, port_mask) {
2836 bool ddi_clk_ungated = !(val &
2837 icl_dpclka_cfgcr0_clk_off(dev_priv,
2840 if (ddi_clk_needed == ddi_clk_ungated)
2844 * Punt on the case now where clock is gated, but it would
2845 * be needed by the port. Something else is really broken then.
2847 if (WARN_ON(ddi_clk_needed))
2850 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2852 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2853 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2857 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2858 const struct intel_crtc_state *crtc_state)
2860 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2861 enum port port = encoder->port;
2863 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2868 mutex_lock(&dev_priv->dpll_lock);
2870 if (IS_ICELAKE(dev_priv)) {
2871 if (!intel_port_is_combophy(dev_priv, port))
2872 I915_WRITE(DDI_CLK_SEL(port),
2873 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2874 } else if (IS_CANNONLAKE(dev_priv)) {
2875 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2876 val = I915_READ(DPCLKA_CFGCR0);
2877 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2878 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2879 I915_WRITE(DPCLKA_CFGCR0, val);
2882 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2883 * This step and the step before must be done with separate
2886 val = I915_READ(DPCLKA_CFGCR0);
2887 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2888 I915_WRITE(DPCLKA_CFGCR0, val);
2889 } else if (IS_GEN9_BC(dev_priv)) {
2890 /* DDI -> PLL mapping */
2891 val = I915_READ(DPLL_CTRL2);
2893 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2894 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2895 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2896 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2898 I915_WRITE(DPLL_CTRL2, val);
2900 } else if (INTEL_GEN(dev_priv) < 9) {
2901 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2904 mutex_unlock(&dev_priv->dpll_lock);
2907 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2909 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2910 enum port port = encoder->port;
2912 if (IS_ICELAKE(dev_priv)) {
2913 if (!intel_port_is_combophy(dev_priv, port))
2914 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2915 } else if (IS_CANNONLAKE(dev_priv)) {
2916 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2917 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2918 } else if (IS_GEN9_BC(dev_priv)) {
2919 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2920 DPLL_CTRL2_DDI_CLK_OFF(port));
2921 } else if (INTEL_GEN(dev_priv) < 9) {
2922 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2926 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2928 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2929 enum port port = dig_port->base.port;
2930 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2931 i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2935 if (tc_port == PORT_TC_NONE)
2938 for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2939 val = I915_READ(mg_regs[i]);
2940 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2941 MG_DP_MODE_CFG_TRPWR_GATING |
2942 MG_DP_MODE_CFG_CLNPWR_GATING |
2943 MG_DP_MODE_CFG_DIGPWR_GATING |
2944 MG_DP_MODE_CFG_GAONPWR_GATING;
2945 I915_WRITE(mg_regs[i], val);
2948 val = I915_READ(MG_MISC_SUS0(tc_port));
2949 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2950 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2951 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2952 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2953 MG_MISC_SUS0_CFG_TRPWR_GATING |
2954 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2955 MG_MISC_SUS0_CFG_DGPWR_GATING;
2956 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2959 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2961 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2962 enum port port = dig_port->base.port;
2963 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2964 i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2968 if (tc_port == PORT_TC_NONE)
2971 for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2972 val = I915_READ(mg_regs[i]);
2973 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2974 MG_DP_MODE_CFG_TRPWR_GATING |
2975 MG_DP_MODE_CFG_CLNPWR_GATING |
2976 MG_DP_MODE_CFG_DIGPWR_GATING |
2977 MG_DP_MODE_CFG_GAONPWR_GATING);
2978 I915_WRITE(mg_regs[i], val);
2981 val = I915_READ(MG_MISC_SUS0(tc_port));
2982 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2983 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2984 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2985 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2986 MG_MISC_SUS0_CFG_TRPWR_GATING |
2987 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2988 MG_MISC_SUS0_CFG_DGPWR_GATING);
2989 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2992 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2994 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2995 enum port port = intel_dig_port->base.port;
2996 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2997 u32 ln0, ln1, lane_info;
2999 if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
3002 ln0 = I915_READ(MG_DP_MODE(port, 0));
3003 ln1 = I915_READ(MG_DP_MODE(port, 1));
3005 switch (intel_dig_port->tc_type) {
3007 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3008 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3010 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
3011 DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
3012 DP_LANE_ASSIGNMENT_SHIFT(tc_port);
3014 switch (lane_info) {
3019 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3022 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3023 MG_DP_MODE_CFG_DP_X2_MODE;
3026 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3029 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3030 MG_DP_MODE_CFG_DP_X2_MODE;
3033 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3034 MG_DP_MODE_CFG_DP_X2_MODE;
3035 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3036 MG_DP_MODE_CFG_DP_X2_MODE;
3039 MISSING_CASE(lane_info);
3043 case TC_PORT_LEGACY:
3044 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3045 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3049 MISSING_CASE(intel_dig_port->tc_type);
3053 I915_WRITE(MG_DP_MODE(port, 0), ln0);
3054 I915_WRITE(MG_DP_MODE(port, 1), ln1);
3057 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3058 const struct intel_crtc_state *crtc_state)
3060 if (!crtc_state->fec_enable)
3063 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3064 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3067 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3068 const struct intel_crtc_state *crtc_state)
3070 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3071 enum port port = encoder->port;
3074 if (!crtc_state->fec_enable)
3077 val = I915_READ(DP_TP_CTL(port));
3078 val |= DP_TP_CTL_FEC_ENABLE;
3079 I915_WRITE(DP_TP_CTL(port), val);
3081 if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
3082 DP_TP_STATUS_FEC_ENABLE_LIVE,
3083 DP_TP_STATUS_FEC_ENABLE_LIVE,
3085 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3088 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3089 const struct intel_crtc_state *crtc_state)
3091 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3092 enum port port = encoder->port;
3095 if (!crtc_state->fec_enable)
3098 val = I915_READ(DP_TP_CTL(port));
3099 val &= ~DP_TP_CTL_FEC_ENABLE;
3100 I915_WRITE(DP_TP_CTL(port), val);
3101 POSTING_READ(DP_TP_CTL(port));
3104 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3105 const struct intel_crtc_state *crtc_state,
3106 const struct drm_connector_state *conn_state)
3108 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3110 enum port port = encoder->port;
3111 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3112 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3113 int level = intel_ddi_dp_level(intel_dp);
3115 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3117 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3118 crtc_state->lane_count, is_mst);
3120 intel_edp_panel_on(intel_dp);
3122 intel_ddi_clk_select(encoder, crtc_state);
3124 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3126 icl_program_mg_dp_mode(dig_port);
3127 icl_disable_phy_clock_gating(dig_port);
3129 if (IS_ICELAKE(dev_priv))
3130 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3131 level, encoder->type);
3132 else if (IS_CANNONLAKE(dev_priv))
3133 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3134 else if (IS_GEN9_LP(dev_priv))
3135 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3137 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3139 intel_ddi_init_dp_buf_reg(encoder);
3141 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3142 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3144 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3145 intel_dp_start_link_train(intel_dp);
3146 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3147 intel_dp_stop_link_train(intel_dp);
3149 intel_ddi_enable_fec(encoder, crtc_state);
3151 icl_enable_phy_clock_gating(dig_port);
3154 intel_ddi_enable_pipe_clock(crtc_state);
3156 intel_dsc_enable(encoder, crtc_state);
3159 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3160 const struct intel_crtc_state *crtc_state,
3161 const struct drm_connector_state *conn_state)
3163 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3164 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3165 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3166 enum port port = encoder->port;
3167 int level = intel_ddi_hdmi_level(dev_priv, port);
3168 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3170 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3171 intel_ddi_clk_select(encoder, crtc_state);
3173 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3175 icl_program_mg_dp_mode(dig_port);
3176 icl_disable_phy_clock_gating(dig_port);
3178 if (IS_ICELAKE(dev_priv))
3179 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3180 level, INTEL_OUTPUT_HDMI);
3181 else if (IS_CANNONLAKE(dev_priv))
3182 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3183 else if (IS_GEN9_LP(dev_priv))
3184 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3186 intel_prepare_hdmi_ddi_buffers(encoder, level);
3188 icl_enable_phy_clock_gating(dig_port);
3190 if (IS_GEN9_BC(dev_priv))
3191 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3193 intel_ddi_enable_pipe_clock(crtc_state);
3195 intel_dig_port->set_infoframes(encoder,
3196 crtc_state->has_infoframe,
3197 crtc_state, conn_state);
3200 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3201 const struct intel_crtc_state *crtc_state,
3202 const struct drm_connector_state *conn_state)
3204 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3205 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3206 enum pipe pipe = crtc->pipe;
3209 * When called from DP MST code:
3210 * - conn_state will be NULL
3211 * - encoder will be the main encoder (ie. mst->primary)
3212 * - the main connector associated with this port
3213 * won't be active or linked to a crtc
3214 * - crtc_state will be the state of the first stream to
3215 * be activated on this port, and it may not be the same
3216 * stream that will be deactivated last, but each stream
3217 * should have a state that is identical when it comes to
3218 * the DP link parameteres
3221 WARN_ON(crtc_state->has_pch_encoder);
3223 if (INTEL_GEN(dev_priv) >= 11)
3224 icl_map_plls_to_ports(encoder, crtc_state);
3226 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3228 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3229 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3231 struct intel_lspcon *lspcon =
3232 enc_to_intel_lspcon(&encoder->base);
3234 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3235 if (lspcon->active) {
3236 struct intel_digital_port *dig_port =
3237 enc_to_dig_port(&encoder->base);
3239 dig_port->set_infoframes(encoder,
3240 crtc_state->has_infoframe,
3241 crtc_state, conn_state);
3246 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3247 const struct intel_crtc_state *crtc_state)
3249 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3250 enum port port = encoder->port;
3254 val = I915_READ(DDI_BUF_CTL(port));
3255 if (val & DDI_BUF_CTL_ENABLE) {
3256 val &= ~DDI_BUF_CTL_ENABLE;
3257 I915_WRITE(DDI_BUF_CTL(port), val);
3261 val = I915_READ(DP_TP_CTL(port));
3262 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3263 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3264 I915_WRITE(DP_TP_CTL(port), val);
3266 /* Disable FEC in DP Sink */
3267 intel_ddi_disable_fec_state(encoder, crtc_state);
3270 intel_wait_ddi_buf_idle(dev_priv, port);
3273 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3274 const struct intel_crtc_state *old_crtc_state,
3275 const struct drm_connector_state *old_conn_state)
3277 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3278 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3279 struct intel_dp *intel_dp = &dig_port->dp;
3280 bool is_mst = intel_crtc_has_type(old_crtc_state,
3281 INTEL_OUTPUT_DP_MST);
3284 intel_ddi_disable_pipe_clock(old_crtc_state);
3286 * Power down sink before disabling the port, otherwise we end
3287 * up getting interrupts from the sink on detecting link loss.
3289 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3292 intel_disable_ddi_buf(encoder, old_crtc_state);
3294 intel_edp_panel_vdd_on(intel_dp);
3295 intel_edp_panel_off(intel_dp);
3297 intel_display_power_put_unchecked(dev_priv,
3298 dig_port->ddi_io_power_domain);
3300 intel_ddi_clk_disable(encoder);
3303 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3304 const struct intel_crtc_state *old_crtc_state,
3305 const struct drm_connector_state *old_conn_state)
3307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3308 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3309 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3311 dig_port->set_infoframes(encoder, false,
3312 old_crtc_state, old_conn_state);
3314 intel_ddi_disable_pipe_clock(old_crtc_state);
3316 intel_disable_ddi_buf(encoder, old_crtc_state);
3318 intel_display_power_put_unchecked(dev_priv,
3319 dig_port->ddi_io_power_domain);
3321 intel_ddi_clk_disable(encoder);
3323 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3326 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3327 const struct intel_crtc_state *old_crtc_state,
3328 const struct drm_connector_state *old_conn_state)
3330 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3333 * When called from DP MST code:
3334 * - old_conn_state will be NULL
3335 * - encoder will be the main encoder (ie. mst->primary)
3336 * - the main connector associated with this port
3337 * won't be active or linked to a crtc
3338 * - old_crtc_state will be the state of the last stream to
3339 * be deactivated on this port, and it may not be the same
3340 * stream that was activated last, but each stream
3341 * should have a state that is identical when it comes to
3342 * the DP link parameteres
3345 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3346 intel_ddi_post_disable_hdmi(encoder,
3347 old_crtc_state, old_conn_state);
3349 intel_ddi_post_disable_dp(encoder,
3350 old_crtc_state, old_conn_state);
3352 if (INTEL_GEN(dev_priv) >= 11)
3353 icl_unmap_plls_to_ports(encoder);
3356 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3357 const struct intel_crtc_state *old_crtc_state,
3358 const struct drm_connector_state *old_conn_state)
3360 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3364 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3365 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3366 * step 13 is the correct place for it. Step 18 is where it was
3367 * originally before the BUN.
3369 val = I915_READ(FDI_RX_CTL(PIPE_A));
3370 val &= ~FDI_RX_ENABLE;
3371 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3373 intel_disable_ddi_buf(encoder, old_crtc_state);
3374 intel_ddi_clk_disable(encoder);
3376 val = I915_READ(FDI_RX_MISC(PIPE_A));
3377 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3378 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3379 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3381 val = I915_READ(FDI_RX_CTL(PIPE_A));
3383 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3385 val = I915_READ(FDI_RX_CTL(PIPE_A));
3386 val &= ~FDI_RX_PLL_ENABLE;
3387 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3390 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3391 const struct intel_crtc_state *crtc_state,
3392 const struct drm_connector_state *conn_state)
3394 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3395 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3396 enum port port = encoder->port;
3398 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3399 intel_dp_stop_link_train(intel_dp);
3401 intel_edp_backlight_on(crtc_state, conn_state);
3402 intel_psr_enable(intel_dp, crtc_state);
3403 intel_edp_drrs_enable(intel_dp, crtc_state);
3405 if (crtc_state->has_audio)
3406 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3410 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3413 static const i915_reg_t regs[] = {
3414 [PORT_A] = CHICKEN_TRANS_EDP,
3415 [PORT_B] = CHICKEN_TRANS_A,
3416 [PORT_C] = CHICKEN_TRANS_B,
3417 [PORT_D] = CHICKEN_TRANS_C,
3418 [PORT_E] = CHICKEN_TRANS_A,
3421 WARN_ON(INTEL_GEN(dev_priv) < 9);
3423 if (WARN_ON(port < PORT_A || port > PORT_E))
3429 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3430 const struct intel_crtc_state *crtc_state,
3431 const struct drm_connector_state *conn_state)
3433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3434 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3435 struct drm_connector *connector = conn_state->connector;
3436 enum port port = encoder->port;
3438 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3439 crtc_state->hdmi_high_tmds_clock_ratio,
3440 crtc_state->hdmi_scrambling))
3441 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3442 connector->base.id, connector->name);
3444 /* Display WA #1143: skl,kbl,cfl */
3445 if (IS_GEN9_BC(dev_priv)) {
3447 * For some reason these chicken bits have been
3448 * stuffed into a transcoder register, event though
3449 * the bits affect a specific DDI port rather than
3450 * a specific transcoder.
3452 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3455 val = I915_READ(reg);
3458 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3459 DDIE_TRAINING_OVERRIDE_VALUE;
3461 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3462 DDI_TRAINING_OVERRIDE_VALUE;
3464 I915_WRITE(reg, val);
3470 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3471 DDIE_TRAINING_OVERRIDE_VALUE);
3473 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3474 DDI_TRAINING_OVERRIDE_VALUE);
3476 I915_WRITE(reg, val);
3479 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3480 * are ignored so nothing special needs to be done besides
3481 * enabling the port.
3483 I915_WRITE(DDI_BUF_CTL(port),
3484 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3486 if (crtc_state->has_audio)
3487 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3490 static void intel_enable_ddi(struct intel_encoder *encoder,
3491 const struct intel_crtc_state *crtc_state,
3492 const struct drm_connector_state *conn_state)
3494 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3495 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3497 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3499 /* Enable hdcp if it's desired */
3500 if (conn_state->content_protection ==
3501 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3502 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3505 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3506 const struct intel_crtc_state *old_crtc_state,
3507 const struct drm_connector_state *old_conn_state)
3509 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3511 intel_dp->link_trained = false;
3513 if (old_crtc_state->has_audio)
3514 intel_audio_codec_disable(encoder,
3515 old_crtc_state, old_conn_state);
3517 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3518 intel_psr_disable(intel_dp, old_crtc_state);
3519 intel_edp_backlight_off(old_conn_state);
3520 /* Disable the decompression in DP Sink */
3521 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3525 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3526 const struct intel_crtc_state *old_crtc_state,
3527 const struct drm_connector_state *old_conn_state)
3529 struct drm_connector *connector = old_conn_state->connector;
3531 if (old_crtc_state->has_audio)
3532 intel_audio_codec_disable(encoder,
3533 old_crtc_state, old_conn_state);
3535 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3537 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3538 connector->base.id, connector->name);
3541 static void intel_disable_ddi(struct intel_encoder *encoder,
3542 const struct intel_crtc_state *old_crtc_state,
3543 const struct drm_connector_state *old_conn_state)
3545 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3547 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3548 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3550 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3553 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3554 const struct intel_crtc_state *crtc_state,
3555 const struct drm_connector_state *conn_state)
3557 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3559 intel_psr_enable(intel_dp, crtc_state);
3560 intel_edp_drrs_enable(intel_dp, crtc_state);
3562 intel_panel_update_backlight(encoder, crtc_state, conn_state);
3565 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3566 const struct intel_crtc_state *crtc_state,
3567 const struct drm_connector_state *conn_state)
3569 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3570 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3573 static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3574 const struct intel_crtc_state *pipe_config,
3577 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3578 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3579 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3580 u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3581 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3583 val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3584 switch (pipe_config->lane_count) {
3586 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3587 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3590 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3591 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3594 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3597 MISSING_CASE(pipe_config->lane_count);
3599 I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3603 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3604 const struct intel_crtc_state *crtc_state,
3605 const struct drm_connector_state *conn_state)
3607 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3608 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3609 enum port port = encoder->port;
3611 if (intel_crtc_has_dp_encoder(crtc_state) ||
3612 intel_port_is_tc(dev_priv, encoder->port))
3613 intel_display_power_get(dev_priv,
3614 intel_ddi_main_link_aux_domain(dig_port));
3616 if (IS_GEN9_LP(dev_priv))
3617 bxt_ddi_phy_set_lane_optim_mask(encoder,
3618 crtc_state->lane_lat_optim_mask);
3621 * Program the lane count for static/dynamic connections on Type-C ports.
3622 * Skip this step for TBT.
3624 if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3625 dig_port->tc_type == TC_PORT_TBT)
3628 intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3632 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3633 const struct intel_crtc_state *crtc_state,
3634 const struct drm_connector_state *conn_state)
3636 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3637 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3639 if (intel_crtc_has_dp_encoder(crtc_state) ||
3640 intel_port_is_tc(dev_priv, encoder->port))
3641 intel_display_power_put_unchecked(dev_priv,
3642 intel_ddi_main_link_aux_domain(dig_port));
3645 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3647 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3648 struct drm_i915_private *dev_priv =
3649 to_i915(intel_dig_port->base.base.dev);
3650 enum port port = intel_dig_port->base.port;
3654 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3655 val = I915_READ(DDI_BUF_CTL(port));
3656 if (val & DDI_BUF_CTL_ENABLE) {
3657 val &= ~DDI_BUF_CTL_ENABLE;
3658 I915_WRITE(DDI_BUF_CTL(port), val);
3662 val = I915_READ(DP_TP_CTL(port));
3663 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3664 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3665 I915_WRITE(DP_TP_CTL(port), val);
3666 POSTING_READ(DP_TP_CTL(port));
3669 intel_wait_ddi_buf_idle(dev_priv, port);
3672 val = DP_TP_CTL_ENABLE |
3673 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3674 if (intel_dp->link_mst)
3675 val |= DP_TP_CTL_MODE_MST;
3677 val |= DP_TP_CTL_MODE_SST;
3678 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3679 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3681 I915_WRITE(DP_TP_CTL(port), val);
3682 POSTING_READ(DP_TP_CTL(port));
3684 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3685 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3686 POSTING_READ(DDI_BUF_CTL(port));
3691 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3692 enum transcoder cpu_transcoder)
3694 if (cpu_transcoder == TRANSCODER_EDP)
3697 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3700 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3701 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3704 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3705 struct intel_crtc_state *crtc_state)
3707 if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
3708 crtc_state->min_voltage_level = 1;
3709 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3710 crtc_state->min_voltage_level = 2;
3713 void intel_ddi_get_config(struct intel_encoder *encoder,
3714 struct intel_crtc_state *pipe_config)
3716 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3717 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3718 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3719 struct intel_digital_port *intel_dig_port;
3720 u32 temp, flags = 0;
3722 /* XXX: DSI transcoder paranoia */
3723 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3726 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3727 if (temp & TRANS_DDI_PHSYNC)
3728 flags |= DRM_MODE_FLAG_PHSYNC;
3730 flags |= DRM_MODE_FLAG_NHSYNC;
3731 if (temp & TRANS_DDI_PVSYNC)
3732 flags |= DRM_MODE_FLAG_PVSYNC;
3734 flags |= DRM_MODE_FLAG_NVSYNC;
3736 pipe_config->base.adjusted_mode.flags |= flags;
3738 switch (temp & TRANS_DDI_BPC_MASK) {
3739 case TRANS_DDI_BPC_6:
3740 pipe_config->pipe_bpp = 18;
3742 case TRANS_DDI_BPC_8:
3743 pipe_config->pipe_bpp = 24;
3745 case TRANS_DDI_BPC_10:
3746 pipe_config->pipe_bpp = 30;
3748 case TRANS_DDI_BPC_12:
3749 pipe_config->pipe_bpp = 36;
3755 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3756 case TRANS_DDI_MODE_SELECT_HDMI:
3757 pipe_config->has_hdmi_sink = true;
3758 intel_dig_port = enc_to_dig_port(&encoder->base);
3760 if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
3761 pipe_config->has_infoframe = true;
3763 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3764 pipe_config->hdmi_scrambling = true;
3765 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3766 pipe_config->hdmi_high_tmds_clock_ratio = true;
3768 case TRANS_DDI_MODE_SELECT_DVI:
3769 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3770 pipe_config->lane_count = 4;
3772 case TRANS_DDI_MODE_SELECT_FDI:
3773 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3775 case TRANS_DDI_MODE_SELECT_DP_SST:
3776 if (encoder->type == INTEL_OUTPUT_EDP)
3777 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3779 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3780 pipe_config->lane_count =
3781 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3782 intel_dp_get_m_n(intel_crtc, pipe_config);
3784 case TRANS_DDI_MODE_SELECT_DP_MST:
3785 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3786 pipe_config->lane_count =
3787 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3788 intel_dp_get_m_n(intel_crtc, pipe_config);
3794 pipe_config->has_audio =
3795 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3797 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3798 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3800 * This is a big fat ugly hack.
3802 * Some machines in UEFI boot mode provide us a VBT that has 18
3803 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3804 * unknown we fail to light up. Yet the same BIOS boots up with
3805 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3806 * max, not what it tells us to use.
3808 * Note: This will still be broken if the eDP panel is not lit
3809 * up by the BIOS, and thus we can't get the mode at module
3812 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3813 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3814 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3817 intel_ddi_clock_get(encoder, pipe_config);
3819 if (IS_GEN9_LP(dev_priv))
3820 pipe_config->lane_lat_optim_mask =
3821 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3823 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3826 static enum intel_output_type
3827 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3828 struct intel_crtc_state *crtc_state,
3829 struct drm_connector_state *conn_state)
3831 switch (conn_state->connector->connector_type) {
3832 case DRM_MODE_CONNECTOR_HDMIA:
3833 return INTEL_OUTPUT_HDMI;
3834 case DRM_MODE_CONNECTOR_eDP:
3835 return INTEL_OUTPUT_EDP;
3836 case DRM_MODE_CONNECTOR_DisplayPort:
3837 return INTEL_OUTPUT_DP;
3839 MISSING_CASE(conn_state->connector->connector_type);
3840 return INTEL_OUTPUT_UNUSED;
3844 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3845 struct intel_crtc_state *pipe_config,
3846 struct drm_connector_state *conn_state)
3848 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3849 enum port port = encoder->port;
3853 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3855 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3856 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3858 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3860 if (IS_GEN9_LP(dev_priv) && ret)
3861 pipe_config->lane_lat_optim_mask =
3862 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3864 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3870 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3872 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3873 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3875 intel_dp_encoder_suspend(encoder);
3878 * TODO: disconnect also from USB DP alternate mode once we have a
3879 * way to handle the modeset restore in that mode during resume
3880 * even if the sink has disappeared while being suspended.
3882 if (dig_port->tc_legacy_port)
3883 icl_tc_phy_disconnect(i915, dig_port);
3886 static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3888 struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3889 struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3891 if (intel_port_is_tc(i915, dig_port->base.port))
3892 intel_digital_port_connected(&dig_port->base);
3894 intel_dp_encoder_reset(drm_encoder);
3897 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3899 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3900 struct drm_i915_private *i915 = to_i915(encoder->dev);
3902 intel_dp_encoder_flush_work(encoder);
3904 if (intel_port_is_tc(i915, dig_port->base.port))
3905 icl_tc_phy_disconnect(i915, dig_port);
3907 drm_encoder_cleanup(encoder);
3911 static const struct drm_encoder_funcs intel_ddi_funcs = {
3912 .reset = intel_ddi_encoder_reset,
3913 .destroy = intel_ddi_encoder_destroy,
3916 static struct intel_connector *
3917 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3919 struct intel_connector *connector;
3920 enum port port = intel_dig_port->base.port;
3922 connector = intel_connector_alloc();
3926 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3927 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3935 static int modeset_pipe(struct drm_crtc *crtc,
3936 struct drm_modeset_acquire_ctx *ctx)
3938 struct drm_atomic_state *state;
3939 struct drm_crtc_state *crtc_state;
3942 state = drm_atomic_state_alloc(crtc->dev);
3946 state->acquire_ctx = ctx;
3948 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3949 if (IS_ERR(crtc_state)) {
3950 ret = PTR_ERR(crtc_state);
3954 crtc_state->mode_changed = true;
3956 ret = drm_atomic_add_affected_connectors(state, crtc);
3960 ret = drm_atomic_add_affected_planes(state, crtc);
3964 ret = drm_atomic_commit(state);
3971 drm_atomic_state_put(state);
3976 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3977 struct drm_modeset_acquire_ctx *ctx)
3979 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3980 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3981 struct intel_connector *connector = hdmi->attached_connector;
3982 struct i2c_adapter *adapter =
3983 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3984 struct drm_connector_state *conn_state;
3985 struct intel_crtc_state *crtc_state;
3986 struct intel_crtc *crtc;
3990 if (!connector || connector->base.status != connector_status_connected)
3993 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3998 conn_state = connector->base.state;
4000 crtc = to_intel_crtc(conn_state->crtc);
4004 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4008 crtc_state = to_intel_crtc_state(crtc->base.state);
4010 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4012 if (!crtc_state->base.active)
4015 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4016 !crtc_state->hdmi_scrambling)
4019 if (conn_state->commit &&
4020 !try_wait_for_completion(&conn_state->commit->hw_done))
4023 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4025 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4029 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4030 crtc_state->hdmi_high_tmds_clock_ratio &&
4031 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4032 crtc_state->hdmi_scrambling)
4036 * HDMI 2.0 says that one should not send scrambled data
4037 * prior to configuring the sink scrambling, and that
4038 * TMDS clock/data transmission should be suspended when
4039 * changing the TMDS clock rate in the sink. So let's
4040 * just do a full modeset here, even though some sinks
4041 * would be perfectly happy if were to just reconfigure
4042 * the SCDC settings on the fly.
4044 return modeset_pipe(&crtc->base, ctx);
4047 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4048 struct intel_connector *connector)
4050 struct drm_modeset_acquire_ctx ctx;
4054 changed = intel_encoder_hotplug(encoder, connector);
4056 drm_modeset_acquire_init(&ctx, 0);
4059 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4060 ret = intel_hdmi_reset_link(encoder, &ctx);
4062 ret = intel_dp_retrain_link(encoder, &ctx);
4064 if (ret == -EDEADLK) {
4065 drm_modeset_backoff(&ctx);
4072 drm_modeset_drop_locks(&ctx);
4073 drm_modeset_acquire_fini(&ctx);
4074 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4079 static struct intel_connector *
4080 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4082 struct intel_connector *connector;
4083 enum port port = intel_dig_port->base.port;
4085 connector = intel_connector_alloc();
4089 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4090 intel_hdmi_init_connector(intel_dig_port, connector);
4095 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4097 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4099 if (dport->base.port != PORT_A)
4102 if (dport->saved_port_bits & DDI_A_4_LANES)
4105 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4106 * supported configuration
4108 if (IS_GEN9_LP(dev_priv))
4111 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4112 * one who does also have a full A/E split called
4113 * DDI_F what makes DDI_E useless. However for this
4114 * case let's trust VBT info.
4116 if (IS_CANNONLAKE(dev_priv) &&
4117 !intel_bios_is_port_present(dev_priv, PORT_E))
4124 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4126 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4127 enum port port = intel_dport->base.port;
4130 if (INTEL_GEN(dev_priv) >= 11)
4133 if (port == PORT_A || port == PORT_E) {
4134 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4135 max_lanes = port == PORT_A ? 4 : 0;
4137 /* Both A and E share 2 lanes */
4142 * Some BIOS might fail to set this bit on port A if eDP
4143 * wasn't lit up at boot. Force this bit set when needed
4144 * so we use the proper lane count for our calculations.
4146 if (intel_ddi_a_force_4_lanes(intel_dport)) {
4147 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4148 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4155 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4157 struct ddi_vbt_port_info *port_info =
4158 &dev_priv->vbt.ddi_port_info[port];
4159 struct intel_digital_port *intel_dig_port;
4160 struct intel_encoder *intel_encoder;
4161 struct drm_encoder *encoder;
4162 bool init_hdmi, init_dp, init_lspcon = false;
4165 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4166 init_dp = port_info->supports_dp;
4168 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4170 * Lspcon device needs to be driven with DP connector
4171 * with special detection sequence. So make sure DP
4172 * is initialized before lspcon.
4177 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4180 if (!init_dp && !init_hdmi) {
4181 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4186 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4187 if (!intel_dig_port)
4190 intel_encoder = &intel_dig_port->base;
4191 encoder = &intel_encoder->base;
4193 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4194 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4196 intel_encoder->hotplug = intel_ddi_hotplug;
4197 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4198 intel_encoder->compute_config = intel_ddi_compute_config;
4199 intel_encoder->enable = intel_enable_ddi;
4200 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4201 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4202 intel_encoder->pre_enable = intel_ddi_pre_enable;
4203 intel_encoder->disable = intel_disable_ddi;
4204 intel_encoder->post_disable = intel_ddi_post_disable;
4205 intel_encoder->update_pipe = intel_ddi_update_pipe;
4206 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4207 intel_encoder->get_config = intel_ddi_get_config;
4208 intel_encoder->suspend = intel_ddi_encoder_suspend;
4209 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4210 intel_encoder->type = INTEL_OUTPUT_DDI;
4211 intel_encoder->power_domain = intel_port_to_power_domain(port);
4212 intel_encoder->port = port;
4213 intel_encoder->cloneable = 0;
4214 for_each_pipe(dev_priv, pipe)
4215 intel_encoder->crtc_mask |= BIT(pipe);
4217 if (INTEL_GEN(dev_priv) >= 11)
4218 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4219 DDI_BUF_PORT_REVERSAL;
4221 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4222 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4223 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4224 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4225 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4227 intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
4228 !port_info->supports_typec_usb &&
4229 !port_info->supports_tbt;
4233 intel_dig_port->ddi_io_power_domain =
4234 POWER_DOMAIN_PORT_DDI_A_IO;
4237 intel_dig_port->ddi_io_power_domain =
4238 POWER_DOMAIN_PORT_DDI_B_IO;
4241 intel_dig_port->ddi_io_power_domain =
4242 POWER_DOMAIN_PORT_DDI_C_IO;
4245 intel_dig_port->ddi_io_power_domain =
4246 POWER_DOMAIN_PORT_DDI_D_IO;
4249 intel_dig_port->ddi_io_power_domain =
4250 POWER_DOMAIN_PORT_DDI_E_IO;
4253 intel_dig_port->ddi_io_power_domain =
4254 POWER_DOMAIN_PORT_DDI_F_IO;
4261 if (!intel_ddi_init_dp_connector(intel_dig_port))
4264 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4267 /* In theory we don't need the encoder->type check, but leave it just in
4268 * case we have some really bad VBTs... */
4269 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4270 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4275 if (lspcon_init(intel_dig_port))
4276 /* TODO: handle hdmi info frame part */
4277 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4281 * LSPCON init faied, but DP init was success, so
4282 * lets try to drive as DP++ port.
4284 DRM_ERROR("LSPCON init failed on port %c\n",
4288 intel_infoframe_init(intel_dig_port);
4290 if (intel_port_is_tc(dev_priv, port))
4291 intel_digital_port_connected(intel_encoder);
4296 drm_encoder_cleanup(encoder);
4297 kfree(intel_dig_port);