drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "intel_dsi.h"
  32
  33 struct ddi_buf_trans {
  34         u32 trans1;     /* balance leg enable, de-emph level */
  35         u32 trans2;     /* vref sel, vswing */
  36         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  37 };
  38
  39 static const u8 index_to_dp_signal_levels[] = {
  40         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  41         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  42         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  43         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  44         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  45         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  46         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  47         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  48         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  49         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  50 };
  51
  52 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  53  * them for both DP and FDI transports, allowing those ports to
  54  * automatically adapt to HDMI connections as well
  55  */
  56 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  57         { 0x00FFFFFF, 0x0006000E, 0x0 },
  58         { 0x00D75FFF, 0x0005000A, 0x0 },
  59         { 0x00C30FFF, 0x00040006, 0x0 },
  60         { 0x80AAAFFF, 0x000B0000, 0x0 },
  61         { 0x00FFFFFF, 0x0005000A, 0x0 },
  62         { 0x00D75FFF, 0x000C0004, 0x0 },
  63         { 0x80C30FFF, 0x000B0000, 0x0 },
  64         { 0x00FFFFFF, 0x00040006, 0x0 },
  65         { 0x80D75FFF, 0x000B0000, 0x0 },
  66 };
  67
  68 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  69         { 0x00FFFFFF, 0x0007000E, 0x0 },
  70         { 0x00D75FFF, 0x000F000A, 0x0 },
  71         { 0x00C30FFF, 0x00060006, 0x0 },
  72         { 0x00AAAFFF, 0x001E0000, 0x0 },
  73         { 0x00FFFFFF, 0x000F000A, 0x0 },
  74         { 0x00D75FFF, 0x00160004, 0x0 },
  75         { 0x00C30FFF, 0x001E0000, 0x0 },
  76         { 0x00FFFFFF, 0x00060006, 0x0 },
  77         { 0x00D75FFF, 0x001E0000, 0x0 },
  78 };
  79
  80 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  81                                         /* Idx  NT mV d T mV d  db      */
  82         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  83         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  84         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  85         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  86         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  87         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  88         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  89         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  90         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  91         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  92         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  93         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  94 };
  95
  96 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  97         { 0x00FFFFFF, 0x00000012, 0x0 },
  98         { 0x00EBAFFF, 0x00020011, 0x0 },
  99         { 0x00C71FFF, 0x0006000F, 0x0 },
 100         { 0x00AAAFFF, 0x000E000A, 0x0 },
 101         { 0x00FFFFFF, 0x00020011, 0x0 },
 102         { 0x00DB6FFF, 0x0005000F, 0x0 },
 103         { 0x00BEEFFF, 0x000A000C, 0x0 },
 104         { 0x00FFFFFF, 0x0005000F, 0x0 },
 105         { 0x00DB6FFF, 0x000A000C, 0x0 },
 106 };
 107
 108 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 109         { 0x00FFFFFF, 0x0007000E, 0x0 },
 110         { 0x00D75FFF, 0x000E000A, 0x0 },
 111         { 0x00BEFFFF, 0x00140006, 0x0 },
 112         { 0x80B2CFFF, 0x001B0002, 0x0 },
 113         { 0x00FFFFFF, 0x000E000A, 0x0 },
 114         { 0x00DB6FFF, 0x00160005, 0x0 },
 115         { 0x80C71FFF, 0x001A0002, 0x0 },
 116         { 0x00F7DFFF, 0x00180004, 0x0 },
 117         { 0x80D75FFF, 0x001B0002, 0x0 },
 118 };
 119
 120 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 121         { 0x00FFFFFF, 0x0001000E, 0x0 },
 122         { 0x00D75FFF, 0x0004000A, 0x0 },
 123         { 0x00C30FFF, 0x00070006, 0x0 },
 124         { 0x00AAAFFF, 0x000C0000, 0x0 },
 125         { 0x00FFFFFF, 0x0004000A, 0x0 },
 126         { 0x00D75FFF, 0x00090004, 0x0 },
 127         { 0x00C30FFF, 0x000C0000, 0x0 },
 128         { 0x00FFFFFF, 0x00070006, 0x0 },
 129         { 0x00D75FFF, 0x000C0000, 0x0 },
 130 };
 131
 132 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 133                                         /* Idx  NT mV d T mV df db      */
 134         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 135         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 136         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 137         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 138         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 139         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 140         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 141         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 142         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 143         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 144 };
 145
 146 /* Skylake H and S */
 147 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 148         { 0x00002016, 0x000000A0, 0x0 },
 149         { 0x00005012, 0x0000009B, 0x0 },
 150         { 0x00007011, 0x00000088, 0x0 },
 151         { 0x80009010, 0x000000C0, 0x1 },
 152         { 0x00002016, 0x0000009B, 0x0 },
 153         { 0x00005012, 0x00000088, 0x0 },
 154         { 0x80007011, 0x000000C0, 0x1 },
 155         { 0x00002016, 0x000000DF, 0x0 },
 156         { 0x80005012, 0x000000C0, 0x1 },
 157 };
 158
 159 /* Skylake U */
 160 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 161         { 0x0000201B, 0x000000A2, 0x0 },
 162         { 0x00005012, 0x00000088, 0x0 },
 163         { 0x80007011, 0x000000CD, 0x1 },
 164         { 0x80009010, 0x000000C0, 0x1 },
 165         { 0x0000201B, 0x0000009D, 0x0 },
 166         { 0x80005012, 0x000000C0, 0x1 },
 167         { 0x80007011, 0x000000C0, 0x1 },
 168         { 0x00002016, 0x00000088, 0x0 },
 169         { 0x80005012, 0x000000C0, 0x1 },
 170 };
 171
 172 /* Skylake Y */
 173 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 174         { 0x00000018, 0x000000A2, 0x0 },
 175         { 0x00005012, 0x00000088, 0x0 },
 176         { 0x80007011, 0x000000CD, 0x3 },
 177         { 0x80009010, 0x000000C0, 0x3 },
 178         { 0x00000018, 0x0000009D, 0x0 },
 179         { 0x80005012, 0x000000C0, 0x3 },
 180         { 0x80007011, 0x000000C0, 0x3 },
 181         { 0x00000018, 0x00000088, 0x0 },
 182         { 0x80005012, 0x000000C0, 0x3 },
 183 };
 184
 185 /* Kabylake H and S */
 186 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 187         { 0x00002016, 0x000000A0, 0x0 },
 188         { 0x00005012, 0x0000009B, 0x0 },
 189         { 0x00007011, 0x00000088, 0x0 },
 190         { 0x80009010, 0x000000C0, 0x1 },
 191         { 0x00002016, 0x0000009B, 0x0 },
 192         { 0x00005012, 0x00000088, 0x0 },
 193         { 0x80007011, 0x000000C0, 0x1 },
 194         { 0x00002016, 0x00000097, 0x0 },
 195         { 0x80005012, 0x000000C0, 0x1 },
 196 };
 197
 198 /* Kabylake U */
 199 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 200         { 0x0000201B, 0x000000A1, 0x0 },
 201         { 0x00005012, 0x00000088, 0x0 },
 202         { 0x80007011, 0x000000CD, 0x3 },
 203         { 0x80009010, 0x000000C0, 0x3 },
 204         { 0x0000201B, 0x0000009D, 0x0 },
 205         { 0x80005012, 0x000000C0, 0x3 },
 206         { 0x80007011, 0x000000C0, 0x3 },
 207         { 0x00002016, 0x0000004F, 0x0 },
 208         { 0x80005012, 0x000000C0, 0x3 },
 209 };
 210
 211 /* Kabylake Y */
 212 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 213         { 0x00001017, 0x000000A1, 0x0 },
 214         { 0x00005012, 0x00000088, 0x0 },
 215         { 0x80007011, 0x000000CD, 0x3 },
 216         { 0x8000800F, 0x000000C0, 0x3 },
 217         { 0x00001017, 0x0000009D, 0x0 },
 218         { 0x80005012, 0x000000C0, 0x3 },
 219         { 0x80007011, 0x000000C0, 0x3 },
 220         { 0x00001017, 0x0000004C, 0x0 },
 221         { 0x80005012, 0x000000C0, 0x3 },
 222 };
 223
 224 /*
 225  * Skylake/Kabylake H and S
 226  * eDP 1.4 low vswing translation parameters
 227  */
 228 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 229         { 0x00000018, 0x000000A8, 0x0 },
 230         { 0x00004013, 0x000000A9, 0x0 },
 231         { 0x00007011, 0x000000A2, 0x0 },
 232         { 0x00009010, 0x0000009C, 0x0 },
 233         { 0x00000018, 0x000000A9, 0x0 },
 234         { 0x00006013, 0x000000A2, 0x0 },
 235         { 0x00007011, 0x000000A6, 0x0 },
 236         { 0x00000018, 0x000000AB, 0x0 },
 237         { 0x00007013, 0x0000009F, 0x0 },
 238         { 0x00000018, 0x000000DF, 0x0 },
 239 };
 240
 241 /*
 242  * Skylake/Kabylake U
 243  * eDP 1.4 low vswing translation parameters
 244  */
 245 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 246         { 0x00000018, 0x000000A8, 0x0 },
 247         { 0x00004013, 0x000000A9, 0x0 },
 248         { 0x00007011, 0x000000A2, 0x0 },
 249         { 0x00009010, 0x0000009C, 0x0 },
 250         { 0x00000018, 0x000000A9, 0x0 },
 251         { 0x00006013, 0x000000A2, 0x0 },
 252         { 0x00007011, 0x000000A6, 0x0 },
 253         { 0x00002016, 0x000000AB, 0x0 },
 254         { 0x00005013, 0x0000009F, 0x0 },
 255         { 0x00000018, 0x000000DF, 0x0 },
 256 };
 257
 258 /*
 259  * Skylake/Kabylake Y
 260  * eDP 1.4 low vswing translation parameters
 261  */
 262 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 263         { 0x00000018, 0x000000A8, 0x0 },
 264         { 0x00004013, 0x000000AB, 0x0 },
 265         { 0x00007011, 0x000000A4, 0x0 },
 266         { 0x00009010, 0x000000DF, 0x0 },
 267         { 0x00000018, 0x000000AA, 0x0 },
 268         { 0x00006013, 0x000000A4, 0x0 },
 269         { 0x00007011, 0x0000009D, 0x0 },
 270         { 0x00000018, 0x000000A0, 0x0 },
 271         { 0x00006012, 0x000000DF, 0x0 },
 272         { 0x00000018, 0x0000008A, 0x0 },
 273 };
 274
 275 /* Skylake/Kabylake U, H and S */
 276 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 277         { 0x00000018, 0x000000AC, 0x0 },
 278         { 0x00005012, 0x0000009D, 0x0 },
 279         { 0x00007011, 0x00000088, 0x0 },
 280         { 0x00000018, 0x000000A1, 0x0 },
 281         { 0x00000018, 0x00000098, 0x0 },
 282         { 0x00004013, 0x00000088, 0x0 },
 283         { 0x80006012, 0x000000CD, 0x1 },
 284         { 0x00000018, 0x000000DF, 0x0 },
 285         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 286         { 0x80003015, 0x000000C0, 0x1 },
 287         { 0x80000018, 0x000000C0, 0x1 },
 288 };
 289
 290 /* Skylake/Kabylake Y */
 291 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 292         { 0x00000018, 0x000000A1, 0x0 },
 293         { 0x00005012, 0x000000DF, 0x0 },
 294         { 0x80007011, 0x000000CB, 0x3 },
 295         { 0x00000018, 0x000000A4, 0x0 },
 296         { 0x00000018, 0x0000009D, 0x0 },
 297         { 0x00004013, 0x00000080, 0x0 },
 298         { 0x80006013, 0x000000C0, 0x3 },
 299         { 0x00000018, 0x0000008A, 0x0 },
 300         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 301         { 0x80003015, 0x000000C0, 0x3 },
 302         { 0x80000018, 0x000000C0, 0x3 },
 303 };
 304
 305 struct bxt_ddi_buf_trans {
 306         u8 margin;      /* swing value */
 307         u8 scale;       /* scale value */
 308         u8 enable;      /* scale enable */
 309         u8 deemphasis;
 310 };
 311
 312 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 313                                         /* Idx  NT mV diff      db  */
 314         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 315         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 316         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 317         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 318         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 319         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 320         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 321         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 322         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 323         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 324 };
 325
 326 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 327                                         /* Idx  NT mV diff      db  */
 328         { 26, 0, 0, 128, },     /* 0:   200             0   */
 329         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 330         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 331         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 332         { 32, 0, 0, 128, },     /* 4:   250             0   */
 333         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 334         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 335         { 43, 0, 0, 128, },     /* 7:   300             0   */
 336         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 337         { 48, 0, 0, 128, },     /* 9:   300             0   */
 338 };
 339
 340 /* BSpec has 2 recommended values - entries 0 and 8.
 341  * Using the entry with higher vswing.
 342  */
 343 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 344                                         /* Idx  NT mV diff      db  */
 345         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 346         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 347         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 348         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 349         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 350         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 351         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 352         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 353         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 354         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 355 };
 356
 357 struct cnl_ddi_buf_trans {
 358         u8 dw2_swing_sel;
 359         u8 dw7_n_scalar;
 360         u8 dw4_cursor_coeff;
 361         u8 dw4_post_cursor_2;
 362         u8 dw4_post_cursor_1;
 363 };
 364
 365 /* Voltage Swing Programming for VccIO 0.85V for DP */
 366 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 367                                                 /* NT mV Trans mV db    */
 368         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 369         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 370         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 371         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 372         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 373         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 374         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 375         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 376         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 377         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 378 };
 379
 380 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 381 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 382                                                 /* NT mV Trans mV db    */
 383         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 384         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 385         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 386         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 387         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 388         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 389         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 390 };
 391
 392 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 393 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 394                                                 /* NT mV Trans mV db    */
 395         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 396         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 397         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 398         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 399         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 400         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 401         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 402         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 403         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 404 };
 405
 406 /* Voltage Swing Programming for VccIO 0.95V for DP */
 407 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 408                                                 /* NT mV Trans mV db    */
 409         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 410         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 411         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 412         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 413         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 414         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 415         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 416         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 417         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 418         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 419 };
 420
 421 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 422 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 423                                                 /* NT mV Trans mV db    */
 424         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 425         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 426         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 427         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 428         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 429         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 430         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 431         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 432         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 433         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 434         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 435 };
 436
 437 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 438 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 439                                                 /* NT mV Trans mV db    */
 440         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 441         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 442         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 443         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 444         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 445         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 446         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 447         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 448         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 449         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 450 };
 451
 452 /* Voltage Swing Programming for VccIO 1.05V for DP */
 453 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 454                                                 /* NT mV Trans mV db    */
 455         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 456         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 457         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 458         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 459         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 460         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 461         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 462         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 463         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 464         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 465 };
 466
 467 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 468 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 469                                                 /* NT mV Trans mV db    */
 470         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 471         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 472         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 473         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 474         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 475         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 476         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 477         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 478         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 479         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 480         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 481 };
 482
 483 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 484 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 485                                                 /* NT mV Trans mV db    */
 486         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 487         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 488         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 489         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 490         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 491         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 492         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 493         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 494         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 495 };
 496
 497 /* icl_combo_phy_ddi_translations */
 498 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 499                                                 /* NT mV Trans mV db    */
 500         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 501         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 502         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 503         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 504         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 505         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 506         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 507         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 508         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 509         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 510 };
 511
 512 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 513                                                 /* NT mV Trans mV db    */
 514         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 515         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 516         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 517         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 518         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 519         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 520         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 521         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 522         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 523         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 524 };
 525
 526 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 527                                                 /* NT mV Trans mV db    */
 528         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 529         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 530         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 531         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 532         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 533         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 534         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 535         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 536         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 537         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 538 };
 539
 540 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 541                                                 /* NT mV Trans mV db    */
 542         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 543         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 544         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 545         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 546         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 547         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 548         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 549 };
 550
 551 struct icl_mg_phy_ddi_buf_trans {
 552         u32 cri_txdeemph_override_5_0;
 553         u32 cri_txdeemph_override_11_6;
 554         u32 cri_txdeemph_override_17_12;
 555 };
 556
 557 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 558                                 /* Voltage swing  pre-emphasis */
 559         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 560         { 0x0, 0x23, 0x08 },    /* 0              1   */
 561         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 562         { 0x0, 0x00, 0x00 },    /* 0              3   */
 563         { 0x0, 0x23, 0x00 },    /* 1              0   */
 564         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 565         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 566         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 567         { 0x0, 0x33, 0x0C },    /* 2              1   */
 568         { 0x0, 0x00, 0x00 },    /* 3              0   */
 569 };
 570
 571 static const struct ddi_buf_trans *
 572 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 573 {
 574         if (dev_priv->vbt.edp.low_vswing) {
 575                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 576                 return bdw_ddi_translations_edp;
 577         } else {
 578                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 579                 return bdw_ddi_translations_dp;
 580         }
 581 }
 582
 583 static const struct ddi_buf_trans *
 584 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 585 {
 586         if (IS_SKL_ULX(dev_priv)) {
 587                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 588                 return skl_y_ddi_translations_dp;
 589         } else if (IS_SKL_ULT(dev_priv)) {
 590                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 591                 return skl_u_ddi_translations_dp;
 592         } else {
 593                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 594                 return skl_ddi_translations_dp;
 595         }
 596 }
 597
 598 static const struct ddi_buf_trans *
 599 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 600 {
 601         if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 602                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 603                 return kbl_y_ddi_translations_dp;
 604         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 605                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 606                 return kbl_u_ddi_translations_dp;
 607         } else {
 608                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 609                 return kbl_ddi_translations_dp;
 610         }
 611 }
 612
 613 static const struct ddi_buf_trans *
 614 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 615 {
 616         if (dev_priv->vbt.edp.low_vswing) {
 617                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 618                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 619                         return skl_y_ddi_translations_edp;
 620                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 621                            IS_CFL_ULT(dev_priv)) {
 622                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 623                         return skl_u_ddi_translations_edp;
 624                 } else {
 625                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 626                         return skl_ddi_translations_edp;
 627                 }
 628         }
 629
 630         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 631                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 632         else
 633                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 634 }
 635
 636 static const struct ddi_buf_trans *
 637 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 638 {
 639         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 640                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 641                 return skl_y_ddi_translations_hdmi;
 642         } else {
 643                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 644                 return skl_ddi_translations_hdmi;
 645         }
 646 }
 647
 648 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 649 {
 650         /* Only DDIA and DDIE can select the 10th register with DP */
 651         if (port == PORT_A || port == PORT_E)
 652                 return min(n_entries, 10);
 653         else
 654                 return min(n_entries, 9);
 655 }
 656
 657 static const struct ddi_buf_trans *
 658 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 659                            enum port port, int *n_entries)
 660 {
 661         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 662                 const struct ddi_buf_trans *ddi_translations =
 663                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 664                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 665                 return ddi_translations;
 666         } else if (IS_SKYLAKE(dev_priv)) {
 667                 const struct ddi_buf_trans *ddi_translations =
 668                         skl_get_buf_trans_dp(dev_priv, n_entries);
 669                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 670                 return ddi_translations;
 671         } else if (IS_BROADWELL(dev_priv)) {
 672                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 673                 return  bdw_ddi_translations_dp;
 674         } else if (IS_HASWELL(dev_priv)) {
 675                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 676                 return hsw_ddi_translations_dp;
 677         }
 678
 679         *n_entries = 0;
 680         return NULL;
 681 }
 682
 683 static const struct ddi_buf_trans *
 684 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 685                             enum port port, int *n_entries)
 686 {
 687         if (IS_GEN9_BC(dev_priv)) {
 688                 const struct ddi_buf_trans *ddi_translations =
 689                         skl_get_buf_trans_edp(dev_priv, n_entries);
 690                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 691                 return ddi_translations;
 692         } else if (IS_BROADWELL(dev_priv)) {
 693                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 694         } else if (IS_HASWELL(dev_priv)) {
 695                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 696                 return hsw_ddi_translations_dp;
 697         }
 698
 699         *n_entries = 0;
 700         return NULL;
 701 }
 702
 703 static const struct ddi_buf_trans *
 704 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 705                             int *n_entries)
 706 {
 707         if (IS_BROADWELL(dev_priv)) {
 708                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 709                 return bdw_ddi_translations_fdi;
 710         } else if (IS_HASWELL(dev_priv)) {
 711                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 712                 return hsw_ddi_translations_fdi;
 713         }
 714
 715         *n_entries = 0;
 716         return NULL;
 717 }
 718
 719 static const struct ddi_buf_trans *
 720 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 721                              int *n_entries)
 722 {
 723         if (IS_GEN9_BC(dev_priv)) {
 724                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 725         } else if (IS_BROADWELL(dev_priv)) {
 726                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 727                 return bdw_ddi_translations_hdmi;
 728         } else if (IS_HASWELL(dev_priv)) {
 729                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 730                 return hsw_ddi_translations_hdmi;
 731         }
 732
 733         *n_entries = 0;
 734         return NULL;
 735 }
 736
 737 static const struct bxt_ddi_buf_trans *
 738 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 739 {
 740         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 741         return bxt_ddi_translations_dp;
 742 }
 743
 744 static const struct bxt_ddi_buf_trans *
 745 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 746 {
 747         if (dev_priv->vbt.edp.low_vswing) {
 748                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 749                 return bxt_ddi_translations_edp;
 750         }
 751
 752         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 753 }
 754
 755 static const struct bxt_ddi_buf_trans *
 756 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 757 {
 758         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 759         return bxt_ddi_translations_hdmi;
 760 }
 761
 762 static const struct cnl_ddi_buf_trans *
 763 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 764 {
 765         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 766
 767         if (voltage == VOLTAGE_INFO_0_85V) {
 768                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 769                 return cnl_ddi_translations_hdmi_0_85V;
 770         } else if (voltage == VOLTAGE_INFO_0_95V) {
 771                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 772                 return cnl_ddi_translations_hdmi_0_95V;
 773         } else if (voltage == VOLTAGE_INFO_1_05V) {
 774                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 775                 return cnl_ddi_translations_hdmi_1_05V;
 776         } else {
 777                 *n_entries = 1; /* shut up gcc */
 778                 MISSING_CASE(voltage);
 779         }
 780         return NULL;
 781 }
 782
 783 static const struct cnl_ddi_buf_trans *
 784 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 785 {
 786         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 787
 788         if (voltage == VOLTAGE_INFO_0_85V) {
 789                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 790                 return cnl_ddi_translations_dp_0_85V;
 791         } else if (voltage == VOLTAGE_INFO_0_95V) {
 792                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 793                 return cnl_ddi_translations_dp_0_95V;
 794         } else if (voltage == VOLTAGE_INFO_1_05V) {
 795                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 796                 return cnl_ddi_translations_dp_1_05V;
 797         } else {
 798                 *n_entries = 1; /* shut up gcc */
 799                 MISSING_CASE(voltage);
 800         }
 801         return NULL;
 802 }
 803
 804 static const struct cnl_ddi_buf_trans *
 805 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 806 {
 807         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 808
 809         if (dev_priv->vbt.edp.low_vswing) {
 810                 if (voltage == VOLTAGE_INFO_0_85V) {
 811                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 812                         return cnl_ddi_translations_edp_0_85V;
 813                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 814                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 815                         return cnl_ddi_translations_edp_0_95V;
 816                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 817                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 818                         return cnl_ddi_translations_edp_1_05V;
 819                 } else {
 820                         *n_entries = 1; /* shut up gcc */
 821                         MISSING_CASE(voltage);
 822                 }
 823                 return NULL;
 824         } else {
 825                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 826         }
 827 }
 828
 829 static const struct cnl_ddi_buf_trans *
 830 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 831                         int type, int rate, int *n_entries)
 832 {
 833         if (type == INTEL_OUTPUT_HDMI) {
 834                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 835                 return icl_combo_phy_ddi_translations_hdmi;
 836         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 837                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 838                 return icl_combo_phy_ddi_translations_edp_hbr3;
 839         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 840                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 841                 return icl_combo_phy_ddi_translations_edp_hbr2;
 842         }
 843
 844         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 845         return icl_combo_phy_ddi_translations_dp_hbr2;
 846 }
 847
 848 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 849 {
 850         int n_entries, level, default_entry;
 851
 852         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 853
 854         if (INTEL_GEN(dev_priv) >= 11) {
 855                 if (intel_port_is_combophy(dev_priv, port))
 856                         icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
 857                                                 0, &n_entries);
 858                 else
 859                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 860                 default_entry = n_entries - 1;
 861         } else if (IS_CANNONLAKE(dev_priv)) {
 862                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 863                 default_entry = n_entries - 1;
 864         } else if (IS_GEN9_LP(dev_priv)) {
 865                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 866                 default_entry = n_entries - 1;
 867         } else if (IS_GEN9_BC(dev_priv)) {
 868                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 869                 default_entry = 8;
 870         } else if (IS_BROADWELL(dev_priv)) {
 871                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 872                 default_entry = 7;
 873         } else if (IS_HASWELL(dev_priv)) {
 874                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 875                 default_entry = 6;
 876         } else {
 877                 WARN(1, "ddi translation table missing\n");
 878                 return 0;
 879         }
 880
 881         /* Choose a good default if VBT is badly populated */
 882         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 883                 level = default_entry;
 884
 885         if (WARN_ON_ONCE(n_entries == 0))
 886                 return 0;
 887         if (WARN_ON_ONCE(level >= n_entries))
 888                 level = n_entries - 1;
 889
 890         return level;
 891 }
 892
 893 /*
 894  * Starting with Haswell, DDI port buffers must be programmed with correct
 895  * values in advance. This function programs the correct values for
 896  * DP/eDP/FDI use cases.
 897  */
 898 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 899                                          const struct intel_crtc_state *crtc_state)
 900 {
 901         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 902         u32 iboost_bit = 0;
 903         int i, n_entries;
 904         enum port port = encoder->port;
 905         const struct ddi_buf_trans *ddi_translations;
 906
 907         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 908                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 909                                                                &n_entries);
 910         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 911                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 912                                                                &n_entries);
 913         else
 914                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 915                                                               &n_entries);
 916
 917         /* If we're boosting the current, set bit 31 of trans1 */
 918         if (IS_GEN9_BC(dev_priv) &&
 919             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 920                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 921
 922         for (i = 0; i < n_entries; i++) {
 923                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 924                            ddi_translations[i].trans1 | iboost_bit);
 925                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 926                            ddi_translations[i].trans2);
 927         }
 928 }
 929
 930 /*
 931  * Starting with Haswell, DDI port buffers must be programmed with correct
 932  * values in advance. This function programs the correct values for
 933  * HDMI/DVI use cases.
 934  */
 935 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 936                                            int level)
 937 {
 938         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 939         u32 iboost_bit = 0;
 940         int n_entries;
 941         enum port port = encoder->port;
 942         const struct ddi_buf_trans *ddi_translations;
 943
 944         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 945
 946         if (WARN_ON_ONCE(!ddi_translations))
 947                 return;
 948         if (WARN_ON_ONCE(level >= n_entries))
 949                 level = n_entries - 1;
 950
 951         /* If we're boosting the current, set bit 31 of trans1 */
 952         if (IS_GEN9_BC(dev_priv) &&
 953             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 954                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 955
 956         /* Entry 9 is for HDMI: */
 957         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 958                    ddi_translations[level].trans1 | iboost_bit);
 959         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 960                    ddi_translations[level].trans2);
 961 }
 962
 963 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 964                                     enum port port)
 965 {
 966         i915_reg_t reg = DDI_BUF_CTL(port);
 967         int i;
 968
 969         for (i = 0; i < 16; i++) {
 970                 udelay(1);
 971                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 972                         return;
 973         }
 974         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 975 }
 976
 977 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 978 {
 979         switch (pll->info->id) {
 980         case DPLL_ID_WRPLL1:
 981                 return PORT_CLK_SEL_WRPLL1;
 982         case DPLL_ID_WRPLL2:
 983                 return PORT_CLK_SEL_WRPLL2;
 984         case DPLL_ID_SPLL:
 985                 return PORT_CLK_SEL_SPLL;
 986         case DPLL_ID_LCPLL_810:
 987                 return PORT_CLK_SEL_LCPLL_810;
 988         case DPLL_ID_LCPLL_1350:
 989                 return PORT_CLK_SEL_LCPLL_1350;
 990         case DPLL_ID_LCPLL_2700:
 991                 return PORT_CLK_SEL_LCPLL_2700;
 992         default:
 993                 MISSING_CASE(pll->info->id);
 994                 return PORT_CLK_SEL_NONE;
 995         }
 996 }
 997
 998 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 999                                   const struct intel_crtc_state *crtc_state)
1000 {
1001         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1002         int clock = crtc_state->port_clock;
1003         const enum intel_dpll_id id = pll->info->id;
1004
1005         switch (id) {
1006         default:
1007                 /*
1008                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1009                  * here, so do warn if this get passed in
1010                  */
1011                 MISSING_CASE(id);
1012                 return DDI_CLK_SEL_NONE;
1013         case DPLL_ID_ICL_TBTPLL:
1014                 switch (clock) {
1015                 case 162000:
1016                         return DDI_CLK_SEL_TBT_162;
1017                 case 270000:
1018                         return DDI_CLK_SEL_TBT_270;
1019                 case 540000:
1020                         return DDI_CLK_SEL_TBT_540;
1021                 case 810000:
1022                         return DDI_CLK_SEL_TBT_810;
1023                 default:
1024                         MISSING_CASE(clock);
1025                         return DDI_CLK_SEL_NONE;
1026                 }
1027         case DPLL_ID_ICL_MGPLL1:
1028         case DPLL_ID_ICL_MGPLL2:
1029         case DPLL_ID_ICL_MGPLL3:
1030         case DPLL_ID_ICL_MGPLL4:
1031                 return DDI_CLK_SEL_MG;
1032         }
1033 }
1034
1035 /* Starting with Haswell, different DDI ports can work in FDI mode for
1036  * connection to the PCH-located connectors. For this, it is necessary to train
1037  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1038  *
1039  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1040  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1041  * DDI A (which is used for eDP)
1042  */
1043
1044 void hsw_fdi_link_train(struct intel_crtc *crtc,
1045                         const struct intel_crtc_state *crtc_state)
1046 {
1047         struct drm_device *dev = crtc->base.dev;
1048         struct drm_i915_private *dev_priv = to_i915(dev);
1049         struct intel_encoder *encoder;
1050         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1051
1052         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1053                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1054                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1055         }
1056
1057         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1058          * mode set "sequence for CRT port" document:
1059          * - TP1 to TP2 time with the default value
1060          * - FDI delay to 90h
1061          *
1062          * WaFDIAutoLinkSetTimingOverrride:hsw
1063          */
1064         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1065                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1066                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1067
1068         /* Enable the PCH Receiver FDI PLL */
1069         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1070                      FDI_RX_PLL_ENABLE |
1071                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1072         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1073         POSTING_READ(FDI_RX_CTL(PIPE_A));
1074         udelay(220);
1075
1076         /* Switch from Rawclk to PCDclk */
1077         rx_ctl_val |= FDI_PCDCLK;
1078         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1079
1080         /* Configure Port Clock Select */
1081         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1082         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1083         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1084
1085         /* Start the training iterating through available voltages and emphasis,
1086          * testing each value twice. */
1087         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1088                 /* Configure DP_TP_CTL with auto-training */
1089                 I915_WRITE(DP_TP_CTL(PORT_E),
1090                                         DP_TP_CTL_FDI_AUTOTRAIN |
1091                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1092                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1093                                         DP_TP_CTL_ENABLE);
1094
1095                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1096                  * DDI E does not support port reversal, the functionality is
1097                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1098                  * port reversal bit */
1099                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1100                            DDI_BUF_CTL_ENABLE |
1101                            ((crtc_state->fdi_lanes - 1) << 1) |
1102                            DDI_BUF_TRANS_SELECT(i / 2));
1103                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1104
1105                 udelay(600);
1106
1107                 /* Program PCH FDI Receiver TU */
1108                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1109
1110                 /* Enable PCH FDI Receiver with auto-training */
1111                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1112                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1113                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1114
1115                 /* Wait for FDI receiver lane calibration */
1116                 udelay(30);
1117
1118                 /* Unset FDI_RX_MISC pwrdn lanes */
1119                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1120                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1121                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1122                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1123
1124                 /* Wait for FDI auto training time */
1125                 udelay(5);
1126
1127                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1128                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1129                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1130                         break;
1131                 }
1132
1133                 /*
1134                  * Leave things enabled even if we failed to train FDI.
1135                  * Results in less fireworks from the state checker.
1136                  */
1137                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1138                         DRM_ERROR("FDI link training failed!\n");
1139                         break;
1140                 }
1141
1142                 rx_ctl_val &= ~FDI_RX_ENABLE;
1143                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1144                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1145
1146                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1147                 temp &= ~DDI_BUF_CTL_ENABLE;
1148                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1149                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1150
1151                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1152                 temp = I915_READ(DP_TP_CTL(PORT_E));
1153                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1154                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1155                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1156                 POSTING_READ(DP_TP_CTL(PORT_E));
1157
1158                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1159
1160                 /* Reset FDI_RX_MISC pwrdn lanes */
1161                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1162                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1163                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1164                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1165                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1166         }
1167
1168         /* Enable normal pixel sending for FDI */
1169         I915_WRITE(DP_TP_CTL(PORT_E),
1170                    DP_TP_CTL_FDI_AUTOTRAIN |
1171                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1172                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1173                    DP_TP_CTL_ENABLE);
1174 }
1175
1176 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1177 {
1178         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1179         struct intel_digital_port *intel_dig_port =
1180                 enc_to_dig_port(&encoder->base);
1181
1182         intel_dp->DP = intel_dig_port->saved_port_bits |
1183                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1184         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1185 }
1186
1187 static struct intel_encoder *
1188 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1189 {
1190         struct drm_device *dev = crtc->base.dev;
1191         struct intel_encoder *encoder, *ret = NULL;
1192         int num_encoders = 0;
1193
1194         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1195                 ret = encoder;
1196                 num_encoders++;
1197         }
1198
1199         if (num_encoders != 1)
1200                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1201                      pipe_name(crtc->pipe));
1202
1203         BUG_ON(ret == NULL);
1204         return ret;
1205 }
1206
1207 #define LC_FREQ 2700
1208
1209 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1210                                    i915_reg_t reg)
1211 {
1212         int refclk = LC_FREQ;
1213         int n, p, r;
1214         u32 wrpll;
1215
1216         wrpll = I915_READ(reg);
1217         switch (wrpll & WRPLL_PLL_REF_MASK) {
1218         case WRPLL_PLL_SSC:
1219         case WRPLL_PLL_NON_SSC:
1220                 /*
1221                  * We could calculate spread here, but our checking
1222                  * code only cares about 5% accuracy, and spread is a max of
1223                  * 0.5% downspread.
1224                  */
1225                 refclk = 135;
1226                 break;
1227         case WRPLL_PLL_LCPLL:
1228                 refclk = LC_FREQ;
1229                 break;
1230         default:
1231                 WARN(1, "bad wrpll refclk\n");
1232                 return 0;
1233         }
1234
1235         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1236         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1237         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1238
1239         /* Convert to KHz, p & r have a fixed point portion */
1240         return (refclk * n * 100) / (p * r);
1241 }
1242
1243 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1244                                enum intel_dpll_id pll_id)
1245 {
1246         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1247         u32 cfgcr1_val, cfgcr2_val;
1248         u32 p0, p1, p2, dco_freq;
1249
1250         cfgcr1_reg = DPLL_CFGCR1(pll_id);
1251         cfgcr2_reg = DPLL_CFGCR2(pll_id);
1252
1253         cfgcr1_val = I915_READ(cfgcr1_reg);
1254         cfgcr2_val = I915_READ(cfgcr2_reg);
1255
1256         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1257         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1258
1259         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1260                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1261         else
1262                 p1 = 1;
1263
1264
1265         switch (p0) {
1266         case DPLL_CFGCR2_PDIV_1:
1267                 p0 = 1;
1268                 break;
1269         case DPLL_CFGCR2_PDIV_2:
1270                 p0 = 2;
1271                 break;
1272         case DPLL_CFGCR2_PDIV_3:
1273                 p0 = 3;
1274                 break;
1275         case DPLL_CFGCR2_PDIV_7:
1276                 p0 = 7;
1277                 break;
1278         }
1279
1280         switch (p2) {
1281         case DPLL_CFGCR2_KDIV_5:
1282                 p2 = 5;
1283                 break;
1284         case DPLL_CFGCR2_KDIV_2:
1285                 p2 = 2;
1286                 break;
1287         case DPLL_CFGCR2_KDIV_3:
1288                 p2 = 3;
1289                 break;
1290         case DPLL_CFGCR2_KDIV_1:
1291                 p2 = 1;
1292                 break;
1293         }
1294
1295         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1296
1297         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1298                 1000) / 0x8000;
1299
1300         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1301                 return 0;
1302
1303         return dco_freq / (p0 * p1 * p2 * 5);
1304 }
1305
1306 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1307                         enum intel_dpll_id pll_id)
1308 {
1309         u32 cfgcr0, cfgcr1;
1310         u32 p0, p1, p2, dco_freq, ref_clock;
1311
1312         if (INTEL_GEN(dev_priv) >= 11) {
1313                 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1314                 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1315         } else {
1316                 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1317                 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1318         }
1319
1320         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1321         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1322
1323         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1324                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1325                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1326         else
1327                 p1 = 1;
1328
1329
1330         switch (p0) {
1331         case DPLL_CFGCR1_PDIV_2:
1332                 p0 = 2;
1333                 break;
1334         case DPLL_CFGCR1_PDIV_3:
1335                 p0 = 3;
1336                 break;
1337         case DPLL_CFGCR1_PDIV_5:
1338                 p0 = 5;
1339                 break;
1340         case DPLL_CFGCR1_PDIV_7:
1341                 p0 = 7;
1342                 break;
1343         }
1344
1345         switch (p2) {
1346         case DPLL_CFGCR1_KDIV_1:
1347                 p2 = 1;
1348                 break;
1349         case DPLL_CFGCR1_KDIV_2:
1350                 p2 = 2;
1351                 break;
1352         case DPLL_CFGCR1_KDIV_3:
1353                 p2 = 3;
1354                 break;
1355         }
1356
1357         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1358
1359         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1360
1361         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1362                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1363
1364         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1365                 return 0;
1366
1367         return dco_freq / (p0 * p1 * p2 * 5);
1368 }
1369
1370 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1371                                  enum port port)
1372 {
1373         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1374
1375         switch (val) {
1376         case DDI_CLK_SEL_NONE:
1377                 return 0;
1378         case DDI_CLK_SEL_TBT_162:
1379                 return 162000;
1380         case DDI_CLK_SEL_TBT_270:
1381                 return 270000;
1382         case DDI_CLK_SEL_TBT_540:
1383                 return 540000;
1384         case DDI_CLK_SEL_TBT_810:
1385                 return 810000;
1386         default:
1387                 MISSING_CASE(val);
1388                 return 0;
1389         }
1390 }
1391
1392 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1393                                 enum port port)
1394 {
1395         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
1396         u32 mg_pll_div0, mg_clktop_hsclkctl;
1397         u32 m1, m2_int, m2_frac, div1, div2, refclk;
1398         u64 tmp;
1399
1400         refclk = dev_priv->cdclk.hw.ref;
1401
1402         mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));
1403         mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));
1404
1405         m1 = I915_READ(MG_PLL_DIV1(tc_port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1406         m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1407         m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1408                   (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1409                   MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1410
1411         switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1412         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1413                 div1 = 2;
1414                 break;
1415         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1416                 div1 = 3;
1417                 break;
1418         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1419                 div1 = 5;
1420                 break;
1421         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1422                 div1 = 7;
1423                 break;
1424         default:
1425                 MISSING_CASE(mg_clktop_hsclkctl);
1426                 return 0;
1427         }
1428
1429         div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1430                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1431         /* div2 value of 0 is same as 1 means no div */
1432         if (div2 == 0)
1433                 div2 = 1;
1434
1435         /*
1436          * Adjust the original formula to delay the division by 2^22 in order to
1437          * minimize possible rounding errors.
1438          */
1439         tmp = (u64)m1 * m2_int * refclk +
1440               (((u64)m1 * m2_frac * refclk) >> 22);
1441         tmp = div_u64(tmp, 5 * div1 * div2);
1442
1443         return tmp;
1444 }
1445
1446 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1447 {
1448         int dotclock;
1449
1450         if (pipe_config->has_pch_encoder)
1451                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1452                                                     &pipe_config->fdi_m_n);
1453         else if (intel_crtc_has_dp_encoder(pipe_config))
1454                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1455                                                     &pipe_config->dp_m_n);
1456         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1457                 dotclock = pipe_config->port_clock * 2 / 3;
1458         else
1459                 dotclock = pipe_config->port_clock;
1460
1461         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1462                 dotclock *= 2;
1463
1464         if (pipe_config->pixel_multiplier)
1465                 dotclock /= pipe_config->pixel_multiplier;
1466
1467         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1468 }
1469
1470 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1471                               struct intel_crtc_state *pipe_config)
1472 {
1473         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1474         enum port port = encoder->port;
1475         int link_clock = 0;
1476         u32 pll_id;
1477
1478         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1479         if (intel_port_is_combophy(dev_priv, port)) {
1480                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1481         } else {
1482                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1483                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1484                 else
1485                         link_clock = icl_calc_mg_pll_link(dev_priv, port);
1486         }
1487
1488         pipe_config->port_clock = link_clock;
1489         ddi_dotclock_get(pipe_config);
1490 }
1491
1492 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1493                               struct intel_crtc_state *pipe_config)
1494 {
1495         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1496         int link_clock = 0;
1497         u32 cfgcr0;
1498         enum intel_dpll_id pll_id;
1499
1500         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1501
1502         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1503
1504         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1505                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1506         } else {
1507                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1508
1509                 switch (link_clock) {
1510                 case DPLL_CFGCR0_LINK_RATE_810:
1511                         link_clock = 81000;
1512                         break;
1513                 case DPLL_CFGCR0_LINK_RATE_1080:
1514                         link_clock = 108000;
1515                         break;
1516                 case DPLL_CFGCR0_LINK_RATE_1350:
1517                         link_clock = 135000;
1518                         break;
1519                 case DPLL_CFGCR0_LINK_RATE_1620:
1520                         link_clock = 162000;
1521                         break;
1522                 case DPLL_CFGCR0_LINK_RATE_2160:
1523                         link_clock = 216000;
1524                         break;
1525                 case DPLL_CFGCR0_LINK_RATE_2700:
1526                         link_clock = 270000;
1527                         break;
1528                 case DPLL_CFGCR0_LINK_RATE_3240:
1529                         link_clock = 324000;
1530                         break;
1531                 case DPLL_CFGCR0_LINK_RATE_4050:
1532                         link_clock = 405000;
1533                         break;
1534                 default:
1535                         WARN(1, "Unsupported link rate\n");
1536                         break;
1537                 }
1538                 link_clock *= 2;
1539         }
1540
1541         pipe_config->port_clock = link_clock;
1542
1543         ddi_dotclock_get(pipe_config);
1544 }
1545
1546 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1547                                 struct intel_crtc_state *pipe_config)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1550         int link_clock = 0;
1551         u32 dpll_ctl1;
1552         enum intel_dpll_id pll_id;
1553
1554         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1555
1556         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1557
1558         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1559                 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1560         } else {
1561                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1562                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1563
1564                 switch (link_clock) {
1565                 case DPLL_CTRL1_LINK_RATE_810:
1566                         link_clock = 81000;
1567                         break;
1568                 case DPLL_CTRL1_LINK_RATE_1080:
1569                         link_clock = 108000;
1570                         break;
1571                 case DPLL_CTRL1_LINK_RATE_1350:
1572                         link_clock = 135000;
1573                         break;
1574                 case DPLL_CTRL1_LINK_RATE_1620:
1575                         link_clock = 162000;
1576                         break;
1577                 case DPLL_CTRL1_LINK_RATE_2160:
1578                         link_clock = 216000;
1579                         break;
1580                 case DPLL_CTRL1_LINK_RATE_2700:
1581                         link_clock = 270000;
1582                         break;
1583                 default:
1584                         WARN(1, "Unsupported link rate\n");
1585                         break;
1586                 }
1587                 link_clock *= 2;
1588         }
1589
1590         pipe_config->port_clock = link_clock;
1591
1592         ddi_dotclock_get(pipe_config);
1593 }
1594
1595 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1596                               struct intel_crtc_state *pipe_config)
1597 {
1598         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1599         int link_clock = 0;
1600         u32 val, pll;
1601
1602         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1603         switch (val & PORT_CLK_SEL_MASK) {
1604         case PORT_CLK_SEL_LCPLL_810:
1605                 link_clock = 81000;
1606                 break;
1607         case PORT_CLK_SEL_LCPLL_1350:
1608                 link_clock = 135000;
1609                 break;
1610         case PORT_CLK_SEL_LCPLL_2700:
1611                 link_clock = 270000;
1612                 break;
1613         case PORT_CLK_SEL_WRPLL1:
1614                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1615                 break;
1616         case PORT_CLK_SEL_WRPLL2:
1617                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1618                 break;
1619         case PORT_CLK_SEL_SPLL:
1620                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1621                 if (pll == SPLL_PLL_FREQ_810MHz)
1622                         link_clock = 81000;
1623                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1624                         link_clock = 135000;
1625                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1626                         link_clock = 270000;
1627                 else {
1628                         WARN(1, "bad spll freq\n");
1629                         return;
1630                 }
1631                 break;
1632         default:
1633                 WARN(1, "bad port clock sel\n");
1634                 return;
1635         }
1636
1637         pipe_config->port_clock = link_clock * 2;
1638
1639         ddi_dotclock_get(pipe_config);
1640 }
1641
1642 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1643 {
1644         struct intel_dpll_hw_state *state;
1645         struct dpll clock;
1646
1647         /* For DDI ports we always use a shared PLL. */
1648         if (WARN_ON(!crtc_state->shared_dpll))
1649                 return 0;
1650
1651         state = &crtc_state->dpll_hw_state;
1652
1653         clock.m1 = 2;
1654         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1655         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1656                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1657         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1658         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1659         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1660
1661         return chv_calc_dpll_params(100000, &clock);
1662 }
1663
1664 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1665                               struct intel_crtc_state *pipe_config)
1666 {
1667         pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1668
1669         ddi_dotclock_get(pipe_config);
1670 }
1671
1672 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1673                                 struct intel_crtc_state *pipe_config)
1674 {
1675         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1676
1677         if (INTEL_GEN(dev_priv) >= 11)
1678                 icl_ddi_clock_get(encoder, pipe_config);
1679         else if (IS_CANNONLAKE(dev_priv))
1680                 cnl_ddi_clock_get(encoder, pipe_config);
1681         else if (IS_GEN9_LP(dev_priv))
1682                 bxt_ddi_clock_get(encoder, pipe_config);
1683         else if (IS_GEN9_BC(dev_priv))
1684                 skl_ddi_clock_get(encoder, pipe_config);
1685         else if (INTEL_GEN(dev_priv) <= 8)
1686                 hsw_ddi_clock_get(encoder, pipe_config);
1687 }
1688
1689 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1690 {
1691         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1692         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1693         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1694         u32 temp;
1695
1696         if (!intel_crtc_has_dp_encoder(crtc_state))
1697                 return;
1698
1699         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1700
1701         temp = TRANS_MSA_SYNC_CLK;
1702
1703         if (crtc_state->limited_color_range)
1704                 temp |= TRANS_MSA_CEA_RANGE;
1705
1706         switch (crtc_state->pipe_bpp) {
1707         case 18:
1708                 temp |= TRANS_MSA_6_BPC;
1709                 break;
1710         case 24:
1711                 temp |= TRANS_MSA_8_BPC;
1712                 break;
1713         case 30:
1714                 temp |= TRANS_MSA_10_BPC;
1715                 break;
1716         case 36:
1717                 temp |= TRANS_MSA_12_BPC;
1718                 break;
1719         default:
1720                 MISSING_CASE(crtc_state->pipe_bpp);
1721                 break;
1722         }
1723
1724         /*
1725          * As per DP 1.2 spec section 2.3.4.3 while sending
1726          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1727          * colorspace information. The output colorspace encoding is BT601.
1728          */
1729         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1730                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1731         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1732 }
1733
1734 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1735                                     bool state)
1736 {
1737         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1738         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1739         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1740         u32 temp;
1741
1742         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1743         if (state == true)
1744                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1745         else
1746                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1747         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1748 }
1749
1750 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1751 {
1752         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1753         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1754         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1755         enum pipe pipe = crtc->pipe;
1756         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1757         enum port port = encoder->port;
1758         u32 temp;
1759
1760         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1761         temp = TRANS_DDI_FUNC_ENABLE;
1762         temp |= TRANS_DDI_SELECT_PORT(port);
1763
1764         switch (crtc_state->pipe_bpp) {
1765         case 18:
1766                 temp |= TRANS_DDI_BPC_6;
1767                 break;
1768         case 24:
1769                 temp |= TRANS_DDI_BPC_8;
1770                 break;
1771         case 30:
1772                 temp |= TRANS_DDI_BPC_10;
1773                 break;
1774         case 36:
1775                 temp |= TRANS_DDI_BPC_12;
1776                 break;
1777         default:
1778                 BUG();
1779         }
1780
1781         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1782                 temp |= TRANS_DDI_PVSYNC;
1783         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1784                 temp |= TRANS_DDI_PHSYNC;
1785
1786         if (cpu_transcoder == TRANSCODER_EDP) {
1787                 switch (pipe) {
1788                 case PIPE_A:
1789                         /* On Haswell, can only use the always-on power well for
1790                          * eDP when not using the panel fitter, and when not
1791                          * using motion blur mitigation (which we don't
1792                          * support). */
1793                         if (IS_HASWELL(dev_priv) &&
1794                             (crtc_state->pch_pfit.enabled ||
1795                              crtc_state->pch_pfit.force_thru))
1796                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1797                         else
1798                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1799                         break;
1800                 case PIPE_B:
1801                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1802                         break;
1803                 case PIPE_C:
1804                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1805                         break;
1806                 default:
1807                         BUG();
1808                         break;
1809                 }
1810         }
1811
1812         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1813                 if (crtc_state->has_hdmi_sink)
1814                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1815                 else
1816                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1817
1818                 if (crtc_state->hdmi_scrambling)
1819                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1820                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1821                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1822         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1823                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1824                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1825         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1826                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1827                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1828         } else {
1829                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1830                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1831         }
1832
1833         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1834 }
1835
1836 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1837 {
1838         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1839         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1840         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1841         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1842         u32 val = I915_READ(reg);
1843
1844         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1845         val |= TRANS_DDI_PORT_NONE;
1846         I915_WRITE(reg, val);
1847
1848         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1849             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1850                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1851                 /* Quirk time at 100ms for reliable operation */
1852                 msleep(100);
1853         }
1854 }
1855
1856 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1857                                      bool enable)
1858 {
1859         struct drm_device *dev = intel_encoder->base.dev;
1860         struct drm_i915_private *dev_priv = to_i915(dev);
1861         intel_wakeref_t wakeref;
1862         enum pipe pipe = 0;
1863         int ret = 0;
1864         u32 tmp;
1865
1866         wakeref = intel_display_power_get_if_enabled(dev_priv,
1867                                                      intel_encoder->power_domain);
1868         if (WARN_ON(!wakeref))
1869                 return -ENXIO;
1870
1871         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1872                 ret = -EIO;
1873                 goto out;
1874         }
1875
1876         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1877         if (enable)
1878                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1879         else
1880                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1881         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1882 out:
1883         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1884         return ret;
1885 }
1886
1887 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1888 {
1889         struct drm_device *dev = intel_connector->base.dev;
1890         struct drm_i915_private *dev_priv = to_i915(dev);
1891         struct intel_encoder *encoder = intel_connector->encoder;
1892         int type = intel_connector->base.connector_type;
1893         enum port port = encoder->port;
1894         enum transcoder cpu_transcoder;
1895         intel_wakeref_t wakeref;
1896         enum pipe pipe = 0;
1897         u32 tmp;
1898         bool ret;
1899
1900         wakeref = intel_display_power_get_if_enabled(dev_priv,
1901                                                      encoder->power_domain);
1902         if (!wakeref)
1903                 return false;
1904
1905         if (!encoder->get_hw_state(encoder, &pipe)) {
1906                 ret = false;
1907                 goto out;
1908         }
1909
1910         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
1911                 cpu_transcoder = TRANSCODER_EDP;
1912         else
1913                 cpu_transcoder = (enum transcoder) pipe;
1914
1915         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1916
1917         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1918         case TRANS_DDI_MODE_SELECT_HDMI:
1919         case TRANS_DDI_MODE_SELECT_DVI:
1920                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1921                 break;
1922
1923         case TRANS_DDI_MODE_SELECT_DP_SST:
1924                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1925                       type == DRM_MODE_CONNECTOR_DisplayPort;
1926                 break;
1927
1928         case TRANS_DDI_MODE_SELECT_DP_MST:
1929                 /* if the transcoder is in MST state then
1930                  * connector isn't connected */
1931                 ret = false;
1932                 break;
1933
1934         case TRANS_DDI_MODE_SELECT_FDI:
1935                 ret = type == DRM_MODE_CONNECTOR_VGA;
1936                 break;
1937
1938         default:
1939                 ret = false;
1940                 break;
1941         }
1942
1943 out:
1944         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1945
1946         return ret;
1947 }
1948
1949 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1950                                         u8 *pipe_mask, bool *is_dp_mst)
1951 {
1952         struct drm_device *dev = encoder->base.dev;
1953         struct drm_i915_private *dev_priv = to_i915(dev);
1954         enum port port = encoder->port;
1955         intel_wakeref_t wakeref;
1956         enum pipe p;
1957         u32 tmp;
1958         u8 mst_pipe_mask;
1959
1960         *pipe_mask = 0;
1961         *is_dp_mst = false;
1962
1963         wakeref = intel_display_power_get_if_enabled(dev_priv,
1964                                                      encoder->power_domain);
1965         if (!wakeref)
1966                 return;
1967
1968         tmp = I915_READ(DDI_BUF_CTL(port));
1969         if (!(tmp & DDI_BUF_CTL_ENABLE))
1970                 goto out;
1971
1972         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
1973                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1974
1975                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1976                 default:
1977                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1978                         /* fallthrough */
1979                 case TRANS_DDI_EDP_INPUT_A_ON:
1980                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1981                         *pipe_mask = BIT(PIPE_A);
1982                         break;
1983                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1984                         *pipe_mask = BIT(PIPE_B);
1985                         break;
1986                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1987                         *pipe_mask = BIT(PIPE_C);
1988                         break;
1989                 }
1990
1991                 goto out;
1992         }
1993
1994         mst_pipe_mask = 0;
1995         for_each_pipe(dev_priv, p) {
1996                 enum transcoder cpu_transcoder = (enum transcoder)p;
1997
1998                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1999
2000                 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
2001                         continue;
2002
2003                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2004                     TRANS_DDI_MODE_SELECT_DP_MST)
2005                         mst_pipe_mask |= BIT(p);
2006
2007                 *pipe_mask |= BIT(p);
2008         }
2009
2010         if (!*pipe_mask)
2011                 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2012                               port_name(port));
2013
2014         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2015                 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2016                               port_name(port), *pipe_mask);
2017                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2018         }
2019
2020         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2021                 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2022                               port_name(port), *pipe_mask, mst_pipe_mask);
2023         else
2024                 *is_dp_mst = mst_pipe_mask;
2025
2026 out:
2027         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2028                 tmp = I915_READ(BXT_PHY_CTL(port));
2029                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2030                             BXT_PHY_LANE_POWERDOWN_ACK |
2031                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2032                         DRM_ERROR("Port %c enabled but PHY powered down? "
2033                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
2034         }
2035
2036         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2037 }
2038
2039 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2040                             enum pipe *pipe)
2041 {
2042         u8 pipe_mask;
2043         bool is_mst;
2044
2045         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2046
2047         if (is_mst || !pipe_mask)
2048                 return false;
2049
2050         *pipe = ffs(pipe_mask) - 1;
2051
2052         return true;
2053 }
2054
2055 static inline enum intel_display_power_domain
2056 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2057 {
2058         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2059          * DC states enabled at the same time, while for driver initiated AUX
2060          * transfers we need the same AUX IOs to be powered but with DC states
2061          * disabled. Accordingly use the AUX power domain here which leaves DC
2062          * states enabled.
2063          * However, for non-A AUX ports the corresponding non-EDP transcoders
2064          * would have already enabled power well 2 and DC_OFF. This means we can
2065          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2066          * specific AUX_IO reference without powering up any extra wells.
2067          * Note that PSR is enabled only on Port A even though this function
2068          * returns the correct domain for other ports too.
2069          */
2070         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2071                                               intel_aux_power_domain(dig_port);
2072 }
2073
2074 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2075                                        struct intel_crtc_state *crtc_state)
2076 {
2077         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2078         struct intel_digital_port *dig_port;
2079         u64 domains;
2080
2081         /*
2082          * TODO: Add support for MST encoders. Atm, the following should never
2083          * happen since fake-MST encoders don't set their get_power_domains()
2084          * hook.
2085          */
2086         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2087                 return 0;
2088
2089         dig_port = enc_to_dig_port(&encoder->base);
2090         domains = BIT_ULL(dig_port->ddi_io_power_domain);
2091
2092         /*
2093          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2094          * ports.
2095          */
2096         if (intel_crtc_has_dp_encoder(crtc_state) ||
2097             intel_port_is_tc(dev_priv, encoder->port))
2098                 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
2099
2100         /*
2101          * VDSC power is needed when DSC is enabled
2102          */
2103         if (crtc_state->dsc_params.compression_enable)
2104                 domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
2105
2106         return domains;
2107 }
2108
2109 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2110 {
2111         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2112         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2113         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2114         enum port port = encoder->port;
2115         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2116
2117         if (cpu_transcoder != TRANSCODER_EDP)
2118                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2119                            TRANS_CLK_SEL_PORT(port));
2120 }
2121
2122 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2123 {
2124         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2125         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2126
2127         if (cpu_transcoder != TRANSCODER_EDP)
2128                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2129                            TRANS_CLK_SEL_DISABLED);
2130 }
2131
2132 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2133                                 enum port port, u8 iboost)
2134 {
2135         u32 tmp;
2136
2137         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2138         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2139         if (iboost)
2140                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2141         else
2142                 tmp |= BALANCE_LEG_DISABLE(port);
2143         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2144 }
2145
2146 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2147                                int level, enum intel_output_type type)
2148 {
2149         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2150         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2151         enum port port = encoder->port;
2152         u8 iboost;
2153
2154         if (type == INTEL_OUTPUT_HDMI)
2155                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2156         else
2157                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2158
2159         if (iboost == 0) {
2160                 const struct ddi_buf_trans *ddi_translations;
2161                 int n_entries;
2162
2163                 if (type == INTEL_OUTPUT_HDMI)
2164                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2165                 else if (type == INTEL_OUTPUT_EDP)
2166                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2167                 else
2168                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2169
2170                 if (WARN_ON_ONCE(!ddi_translations))
2171                         return;
2172                 if (WARN_ON_ONCE(level >= n_entries))
2173                         level = n_entries - 1;
2174
2175                 iboost = ddi_translations[level].i_boost;
2176         }
2177
2178         /* Make sure that the requested I_boost is valid */
2179         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2180                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2181                 return;
2182         }
2183
2184         _skl_ddi_set_iboost(dev_priv, port, iboost);
2185
2186         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2187                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2188 }
2189
2190 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2191                                     int level, enum intel_output_type type)
2192 {
2193         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2194         const struct bxt_ddi_buf_trans *ddi_translations;
2195         enum port port = encoder->port;
2196         int n_entries;
2197
2198         if (type == INTEL_OUTPUT_HDMI)
2199                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2200         else if (type == INTEL_OUTPUT_EDP)
2201                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2202         else
2203                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2204
2205         if (WARN_ON_ONCE(!ddi_translations))
2206                 return;
2207         if (WARN_ON_ONCE(level >= n_entries))
2208                 level = n_entries - 1;
2209
2210         bxt_ddi_phy_set_signal_level(dev_priv, port,
2211                                      ddi_translations[level].margin,
2212                                      ddi_translations[level].scale,
2213                                      ddi_translations[level].enable,
2214                                      ddi_translations[level].deemphasis);
2215 }
2216
2217 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2218 {
2219         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2220         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2221         enum port port = encoder->port;
2222         int n_entries;
2223
2224         if (INTEL_GEN(dev_priv) >= 11) {
2225                 if (intel_port_is_combophy(dev_priv, port))
2226                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2227                                                 intel_dp->link_rate, &n_entries);
2228                 else
2229                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2230         } else if (IS_CANNONLAKE(dev_priv)) {
2231                 if (encoder->type == INTEL_OUTPUT_EDP)
2232                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2233                 else
2234                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2235         } else if (IS_GEN9_LP(dev_priv)) {
2236                 if (encoder->type == INTEL_OUTPUT_EDP)
2237                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2238                 else
2239                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2240         } else {
2241                 if (encoder->type == INTEL_OUTPUT_EDP)
2242                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2243                 else
2244                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2245         }
2246
2247         if (WARN_ON(n_entries < 1))
2248                 n_entries = 1;
2249         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2250                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2251
2252         return index_to_dp_signal_levels[n_entries - 1] &
2253                 DP_TRAIN_VOLTAGE_SWING_MASK;
2254 }
2255
2256 /*
2257  * We assume that the full set of pre-emphasis values can be
2258  * used on all DDI platforms. Should that change we need to
2259  * rethink this code.
2260  */
2261 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2262 {
2263         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2264         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2265                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2266         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2267                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2268         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2269                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2270         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2271         default:
2272                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2273         }
2274 }
2275
2276 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2277                                    int level, enum intel_output_type type)
2278 {
2279         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2280         const struct cnl_ddi_buf_trans *ddi_translations;
2281         enum port port = encoder->port;
2282         int n_entries, ln;
2283         u32 val;
2284
2285         if (type == INTEL_OUTPUT_HDMI)
2286                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2287         else if (type == INTEL_OUTPUT_EDP)
2288                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2289         else
2290                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2291
2292         if (WARN_ON_ONCE(!ddi_translations))
2293                 return;
2294         if (WARN_ON_ONCE(level >= n_entries))
2295                 level = n_entries - 1;
2296
2297         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2298         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2299         val &= ~SCALING_MODE_SEL_MASK;
2300         val |= SCALING_MODE_SEL(2);
2301         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2302
2303         /* Program PORT_TX_DW2 */
2304         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2305         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2306                  RCOMP_SCALAR_MASK);
2307         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2308         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2309         /* Rcomp scalar is fixed as 0x98 for every table entry */
2310         val |= RCOMP_SCALAR(0x98);
2311         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2312
2313         /* Program PORT_TX_DW4 */
2314         /* We cannot write to GRP. It would overrite individual loadgen */
2315         for (ln = 0; ln < 4; ln++) {
2316                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2317                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2318                          CURSOR_COEFF_MASK);
2319                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2320                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2321                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2322                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2323         }
2324
2325         /* Program PORT_TX_DW5 */
2326         /* All DW5 values are fixed for every table entry */
2327         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2328         val &= ~RTERM_SELECT_MASK;
2329         val |= RTERM_SELECT(6);
2330         val |= TAP3_DISABLE;
2331         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2332
2333         /* Program PORT_TX_DW7 */
2334         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2335         val &= ~N_SCALAR_MASK;
2336         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2337         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2338 }
2339
2340 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2341                                     int level, enum intel_output_type type)
2342 {
2343         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2344         enum port port = encoder->port;
2345         int width, rate, ln;
2346         u32 val;
2347
2348         if (type == INTEL_OUTPUT_HDMI) {
2349                 width = 4;
2350                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2351         } else {
2352                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2353
2354                 width = intel_dp->lane_count;
2355                 rate = intel_dp->link_rate;
2356         }
2357
2358         /*
2359          * 1. If port type is eDP or DP,
2360          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2361          * else clear to 0b.
2362          */
2363         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2364         if (type != INTEL_OUTPUT_HDMI)
2365                 val |= COMMON_KEEPER_EN;
2366         else
2367                 val &= ~COMMON_KEEPER_EN;
2368         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2369
2370         /* 2. Program loadgen select */
2371         /*
2372          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2373          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2374          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2375          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2376          */
2377         for (ln = 0; ln <= 3; ln++) {
2378                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2379                 val &= ~LOADGEN_SELECT;
2380
2381                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2382                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2383                         val |= LOADGEN_SELECT;
2384                 }
2385                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2386         }
2387
2388         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2389         val = I915_READ(CNL_PORT_CL1CM_DW5);
2390         val |= SUS_CLOCK_CONFIG;
2391         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2392
2393         /* 4. Clear training enable to change swing values */
2394         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2395         val &= ~TX_TRAINING_EN;
2396         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2397
2398         /* 5. Program swing and de-emphasis */
2399         cnl_ddi_vswing_program(encoder, level, type);
2400
2401         /* 6. Set training enable to trigger update */
2402         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2403         val |= TX_TRAINING_EN;
2404         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2405 }
2406
2407 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2408                                         u32 level, enum port port, int type,
2409                                         int rate)
2410 {
2411         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2412         u32 n_entries, val;
2413         int ln;
2414
2415         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2416                                                    rate, &n_entries);
2417         if (!ddi_translations)
2418                 return;
2419
2420         if (level >= n_entries) {
2421                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2422                 level = n_entries - 1;
2423         }
2424
2425         /* Set PORT_TX_DW5 */
2426         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2427         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2428                   TAP2_DISABLE | TAP3_DISABLE);
2429         val |= SCALING_MODE_SEL(0x2);
2430         val |= RTERM_SELECT(0x6);
2431         val |= TAP3_DISABLE;
2432         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2433
2434         /* Program PORT_TX_DW2 */
2435         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2436         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2437                  RCOMP_SCALAR_MASK);
2438         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2439         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2440         /* Program Rcomp scalar for every table entry */
2441         val |= RCOMP_SCALAR(0x98);
2442         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2443
2444         /* Program PORT_TX_DW4 */
2445         /* We cannot write to GRP. It would overwrite individual loadgen. */
2446         for (ln = 0; ln <= 3; ln++) {
2447                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
2448                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2449                          CURSOR_COEFF_MASK);
2450                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2451                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2452                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2453                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
2454         }
2455
2456         /* Program PORT_TX_DW7 */
2457         val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2458         val &= ~N_SCALAR_MASK;
2459         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2460         I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
2461 }
2462
2463 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2464                                               u32 level,
2465                                               enum intel_output_type type)
2466 {
2467         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2468         enum port port = encoder->port;
2469         int width = 0;
2470         int rate = 0;
2471         u32 val;
2472         int ln = 0;
2473
2474         if (type == INTEL_OUTPUT_HDMI) {
2475                 width = 4;
2476                 /* Rate is always < than 6GHz for HDMI */
2477         } else {
2478                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2479
2480                 width = intel_dp->lane_count;
2481                 rate = intel_dp->link_rate;
2482         }
2483
2484         /*
2485          * 1. If port type is eDP or DP,
2486          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2487          * else clear to 0b.
2488          */
2489         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2490         if (type == INTEL_OUTPUT_HDMI)
2491                 val &= ~COMMON_KEEPER_EN;
2492         else
2493                 val |= COMMON_KEEPER_EN;
2494         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2495
2496         /* 2. Program loadgen select */
2497         /*
2498          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2499          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2500          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2501          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2502          */
2503         for (ln = 0; ln <= 3; ln++) {
2504                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
2505                 val &= ~LOADGEN_SELECT;
2506
2507                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2508                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2509                         val |= LOADGEN_SELECT;
2510                 }
2511                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
2512         }
2513
2514         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2515         val = I915_READ(ICL_PORT_CL_DW5(port));
2516         val |= SUS_CLOCK_CONFIG;
2517         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2518
2519         /* 4. Clear training enable to change swing values */
2520         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2521         val &= ~TX_TRAINING_EN;
2522         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2523
2524         /* 5. Program swing and de-emphasis */
2525         icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
2526
2527         /* 6. Set training enable to trigger update */
2528         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2529         val |= TX_TRAINING_EN;
2530         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2531 }
2532
2533 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2534                                            int link_clock,
2535                                            u32 level)
2536 {
2537         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2538         enum port port = encoder->port;
2539         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2540         u32 n_entries, val;
2541         int ln;
2542
2543         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2544         ddi_translations = icl_mg_phy_ddi_translations;
2545         /* The table does not have values for level 3 and level 9. */
2546         if (level >= n_entries || level == 3 || level == 9) {
2547                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2548                               level, n_entries - 2);
2549                 level = n_entries - 2;
2550         }
2551
2552         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2553         for (ln = 0; ln < 2; ln++) {
2554                 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
2555                 val &= ~CRI_USE_FS32;
2556                 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
2557
2558                 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
2559                 val &= ~CRI_USE_FS32;
2560                 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
2561         }
2562
2563         /* Program MG_TX_SWINGCTRL with values from vswing table */
2564         for (ln = 0; ln < 2; ln++) {
2565                 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
2566                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2567                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2568                         ddi_translations[level].cri_txdeemph_override_17_12);
2569                 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
2570
2571                 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
2572                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2573                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2574                         ddi_translations[level].cri_txdeemph_override_17_12);
2575                 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
2576         }
2577
2578         /* Program MG_TX_DRVCTRL with values from vswing table */
2579         for (ln = 0; ln < 2; ln++) {
2580                 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
2581                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2582                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2583                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2584                         ddi_translations[level].cri_txdeemph_override_5_0) |
2585                         CRI_TXDEEMPH_OVERRIDE_11_6(
2586                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2587                         CRI_TXDEEMPH_OVERRIDE_EN;
2588                 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
2589
2590                 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
2591                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2592                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2593                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2594                         ddi_translations[level].cri_txdeemph_override_5_0) |
2595                         CRI_TXDEEMPH_OVERRIDE_11_6(
2596                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2597                         CRI_TXDEEMPH_OVERRIDE_EN;
2598                 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
2599
2600                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2601         }
2602
2603         /*
2604          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2605          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2606          * values from table for which TX1 and TX2 enabled.
2607          */
2608         for (ln = 0; ln < 2; ln++) {
2609                 val = I915_READ(MG_CLKHUB(ln, port));
2610                 if (link_clock < 300000)
2611                         val |= CFG_LOW_RATE_LKREN_EN;
2612                 else
2613                         val &= ~CFG_LOW_RATE_LKREN_EN;
2614                 I915_WRITE(MG_CLKHUB(ln, port), val);
2615         }
2616
2617         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2618         for (ln = 0; ln < 2; ln++) {
2619                 val = I915_READ(MG_TX1_DCC(ln, port));
2620                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2621                 if (link_clock <= 500000) {
2622                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2623                 } else {
2624                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2625                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2626                 }
2627                 I915_WRITE(MG_TX1_DCC(ln, port), val);
2628
2629                 val = I915_READ(MG_TX2_DCC(ln, port));
2630                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2631                 if (link_clock <= 500000) {
2632                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2633                 } else {
2634                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2635                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2636                 }
2637                 I915_WRITE(MG_TX2_DCC(ln, port), val);
2638         }
2639
2640         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2641         for (ln = 0; ln < 2; ln++) {
2642                 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
2643                 val |= CRI_CALCINIT;
2644                 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
2645
2646                 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
2647                 val |= CRI_CALCINIT;
2648                 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
2649         }
2650 }
2651
2652 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2653                                     int link_clock,
2654                                     u32 level,
2655                                     enum intel_output_type type)
2656 {
2657         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2658         enum port port = encoder->port;
2659
2660         if (intel_port_is_combophy(dev_priv, port))
2661                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2662         else
2663                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2664 }
2665
2666 static u32 translate_signal_level(int signal_levels)
2667 {
2668         int i;
2669
2670         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2671                 if (index_to_dp_signal_levels[i] == signal_levels)
2672                         return i;
2673         }
2674
2675         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2676              signal_levels);
2677
2678         return 0;
2679 }
2680
2681 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2682 {
2683         u8 train_set = intel_dp->train_set[0];
2684         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2685                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2686
2687         return translate_signal_level(signal_levels);
2688 }
2689
2690 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2691 {
2692         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2693         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2694         struct intel_encoder *encoder = &dport->base;
2695         int level = intel_ddi_dp_level(intel_dp);
2696
2697         if (INTEL_GEN(dev_priv) >= 11)
2698                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2699                                         level, encoder->type);
2700         else if (IS_CANNONLAKE(dev_priv))
2701                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2702         else
2703                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2704
2705         return 0;
2706 }
2707
2708 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2709 {
2710         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2711         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2712         struct intel_encoder *encoder = &dport->base;
2713         int level = intel_ddi_dp_level(intel_dp);
2714
2715         if (IS_GEN9_BC(dev_priv))
2716                 skl_ddi_set_iboost(encoder, level, encoder->type);
2717
2718         return DDI_BUF_TRANS_SELECT(level);
2719 }
2720
2721 static inline
2722 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2723                               enum port port)
2724 {
2725         if (intel_port_is_combophy(dev_priv, port)) {
2726                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2727         } else if (intel_port_is_tc(dev_priv, port)) {
2728                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2729
2730                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2731         }
2732
2733         return 0;
2734 }
2735
2736 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2737                                   const struct intel_crtc_state *crtc_state)
2738 {
2739         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2740         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2741         enum port port = encoder->port;
2742         u32 val;
2743
2744         mutex_lock(&dev_priv->dpll_lock);
2745
2746         val = I915_READ(DPCLKA_CFGCR0_ICL);
2747         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2748
2749         if (intel_port_is_combophy(dev_priv, port)) {
2750                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2751                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2752                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2753                 POSTING_READ(DPCLKA_CFGCR0_ICL);
2754         }
2755
2756         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2757         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2758
2759         mutex_unlock(&dev_priv->dpll_lock);
2760 }
2761
2762 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2763 {
2764         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2765         enum port port = encoder->port;
2766         u32 val;
2767
2768         mutex_lock(&dev_priv->dpll_lock);
2769
2770         val = I915_READ(DPCLKA_CFGCR0_ICL);
2771         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2772         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2773
2774         mutex_unlock(&dev_priv->dpll_lock);
2775 }
2776
2777 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2778 {
2779         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2780         u32 val;
2781         enum port port;
2782         u32 port_mask;
2783         bool ddi_clk_needed;
2784
2785         /*
2786          * In case of DP MST, we sanitize the primary encoder only, not the
2787          * virtual ones.
2788          */
2789         if (encoder->type == INTEL_OUTPUT_DP_MST)
2790                 return;
2791
2792         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2793                 u8 pipe_mask;
2794                 bool is_mst;
2795
2796                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2797                 /*
2798                  * In the unlikely case that BIOS enables DP in MST mode, just
2799                  * warn since our MST HW readout is incomplete.
2800                  */
2801                 if (WARN_ON(is_mst))
2802                         return;
2803         }
2804
2805         port_mask = BIT(encoder->port);
2806         ddi_clk_needed = encoder->base.crtc;
2807
2808         if (encoder->type == INTEL_OUTPUT_DSI) {
2809                 struct intel_encoder *other_encoder;
2810
2811                 port_mask = intel_dsi_encoder_ports(encoder);
2812                 /*
2813                  * Sanity check that we haven't incorrectly registered another
2814                  * encoder using any of the ports of this DSI encoder.
2815                  */
2816                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2817                         if (other_encoder == encoder)
2818                                 continue;
2819
2820                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
2821                                 return;
2822                 }
2823                 /*
2824                  * DSI ports should have their DDI clock ungated when disabled
2825                  * and gated when enabled.
2826                  */
2827                 ddi_clk_needed = !encoder->base.crtc;
2828         }
2829
2830         val = I915_READ(DPCLKA_CFGCR0_ICL);
2831         for_each_port_masked(port, port_mask) {
2832                 bool ddi_clk_ungated = !(val &
2833                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
2834                                                                    port));
2835
2836                 if (ddi_clk_needed == ddi_clk_ungated)
2837                         continue;
2838
2839                 /*
2840                  * Punt on the case now where clock is gated, but it would
2841                  * be needed by the port. Something else is really broken then.
2842                  */
2843                 if (WARN_ON(ddi_clk_needed))
2844                         continue;
2845
2846                 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2847                          port_name(port));
2848                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2849                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2850         }
2851 }
2852
2853 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2854                                  const struct intel_crtc_state *crtc_state)
2855 {
2856         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2857         enum port port = encoder->port;
2858         u32 val;
2859         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2860
2861         if (WARN_ON(!pll))
2862                 return;
2863
2864         mutex_lock(&dev_priv->dpll_lock);
2865
2866         if (INTEL_GEN(dev_priv) >= 11) {
2867                 if (!intel_port_is_combophy(dev_priv, port))
2868                         I915_WRITE(DDI_CLK_SEL(port),
2869                                    icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2870         } else if (IS_CANNONLAKE(dev_priv)) {
2871                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2872                 val = I915_READ(DPCLKA_CFGCR0);
2873                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2874                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2875                 I915_WRITE(DPCLKA_CFGCR0, val);
2876
2877                 /*
2878                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2879                  * This step and the step before must be done with separate
2880                  * register writes.
2881                  */
2882                 val = I915_READ(DPCLKA_CFGCR0);
2883                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2884                 I915_WRITE(DPCLKA_CFGCR0, val);
2885         } else if (IS_GEN9_BC(dev_priv)) {
2886                 /* DDI -> PLL mapping  */
2887                 val = I915_READ(DPLL_CTRL2);
2888
2889                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2890                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2891                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2892                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2893
2894                 I915_WRITE(DPLL_CTRL2, val);
2895
2896         } else if (INTEL_GEN(dev_priv) < 9) {
2897                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2898         }
2899
2900         mutex_unlock(&dev_priv->dpll_lock);
2901 }
2902
2903 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2904 {
2905         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2906         enum port port = encoder->port;
2907
2908         if (INTEL_GEN(dev_priv) >= 11) {
2909                 if (!intel_port_is_combophy(dev_priv, port))
2910                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2911         } else if (IS_CANNONLAKE(dev_priv)) {
2912                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2913                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2914         } else if (IS_GEN9_BC(dev_priv)) {
2915                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2916                            DPLL_CTRL2_DDI_CLK_OFF(port));
2917         } else if (INTEL_GEN(dev_priv) < 9) {
2918                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2919         }
2920 }
2921
2922 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2923 {
2924         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2925         enum port port = dig_port->base.port;
2926         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2927         i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) };
2928         u32 val;
2929         int i;
2930
2931         if (tc_port == PORT_TC_NONE)
2932                 return;
2933
2934         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2935                 val = I915_READ(mg_regs[i]);
2936                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2937                        MG_DP_MODE_CFG_TRPWR_GATING |
2938                        MG_DP_MODE_CFG_CLNPWR_GATING |
2939                        MG_DP_MODE_CFG_DIGPWR_GATING |
2940                        MG_DP_MODE_CFG_GAONPWR_GATING;
2941                 I915_WRITE(mg_regs[i], val);
2942         }
2943
2944         val = I915_READ(MG_MISC_SUS0(tc_port));
2945         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2946                MG_MISC_SUS0_CFG_TR2PWR_GATING |
2947                MG_MISC_SUS0_CFG_CL2PWR_GATING |
2948                MG_MISC_SUS0_CFG_GAONPWR_GATING |
2949                MG_MISC_SUS0_CFG_TRPWR_GATING |
2950                MG_MISC_SUS0_CFG_CL1PWR_GATING |
2951                MG_MISC_SUS0_CFG_DGPWR_GATING;
2952         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2953 }
2954
2955 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2956 {
2957         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2958         enum port port = dig_port->base.port;
2959         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2960         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2961         u32 val;
2962         int i;
2963
2964         if (tc_port == PORT_TC_NONE)
2965                 return;
2966
2967         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2968                 val = I915_READ(mg_regs[i]);
2969                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2970                          MG_DP_MODE_CFG_TRPWR_GATING |
2971                          MG_DP_MODE_CFG_CLNPWR_GATING |
2972                          MG_DP_MODE_CFG_DIGPWR_GATING |
2973                          MG_DP_MODE_CFG_GAONPWR_GATING);
2974                 I915_WRITE(mg_regs[i], val);
2975         }
2976
2977         val = I915_READ(MG_MISC_SUS0(tc_port));
2978         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2979                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
2980                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
2981                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
2982                  MG_MISC_SUS0_CFG_TRPWR_GATING |
2983                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
2984                  MG_MISC_SUS0_CFG_DGPWR_GATING);
2985         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2986 }
2987
2988 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2989 {
2990         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2991         enum port port = intel_dig_port->base.port;
2992         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2993         u32 ln0, ln1, lane_info;
2994
2995         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
2996                 return;
2997
2998         ln0 = I915_READ(MG_DP_MODE(0, port));
2999         ln1 = I915_READ(MG_DP_MODE(1, port));
3000
3001         switch (intel_dig_port->tc_type) {
3002         case TC_PORT_TYPEC:
3003                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3004                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3005
3006                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
3007                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
3008                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
3009
3010                 switch (lane_info) {
3011                 case 0x1:
3012                 case 0x4:
3013                         break;
3014                 case 0x2:
3015                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3016                         break;
3017                 case 0x3:
3018                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3019                                MG_DP_MODE_CFG_DP_X2_MODE;
3020                         break;
3021                 case 0x8:
3022                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3023                         break;
3024                 case 0xC:
3025                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3026                                MG_DP_MODE_CFG_DP_X2_MODE;
3027                         break;
3028                 case 0xF:
3029                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3030                                MG_DP_MODE_CFG_DP_X2_MODE;
3031                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3032                                MG_DP_MODE_CFG_DP_X2_MODE;
3033                         break;
3034                 default:
3035                         MISSING_CASE(lane_info);
3036                 }
3037                 break;
3038
3039         case TC_PORT_LEGACY:
3040                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3041                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3042                 break;
3043
3044         default:
3045                 MISSING_CASE(intel_dig_port->tc_type);
3046                 return;
3047         }
3048
3049         I915_WRITE(MG_DP_MODE(0, port), ln0);
3050         I915_WRITE(MG_DP_MODE(1, port), ln1);
3051 }
3052
3053 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3054                                         const struct intel_crtc_state *crtc_state)
3055 {
3056         if (!crtc_state->fec_enable)
3057                 return;
3058
3059         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3060                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3061 }
3062
3063 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3064                                  const struct intel_crtc_state *crtc_state)
3065 {
3066         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3067         enum port port = encoder->port;
3068         u32 val;
3069
3070         if (!crtc_state->fec_enable)
3071                 return;
3072
3073         val = I915_READ(DP_TP_CTL(port));
3074         val |= DP_TP_CTL_FEC_ENABLE;
3075         I915_WRITE(DP_TP_CTL(port), val);
3076
3077         if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
3078                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3079                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3080                                     1))
3081                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3082 }
3083
3084 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3085                                         const struct intel_crtc_state *crtc_state)
3086 {
3087         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3088         enum port port = encoder->port;
3089         u32 val;
3090
3091         if (!crtc_state->fec_enable)
3092                 return;
3093
3094         val = I915_READ(DP_TP_CTL(port));
3095         val &= ~DP_TP_CTL_FEC_ENABLE;
3096         I915_WRITE(DP_TP_CTL(port), val);
3097         POSTING_READ(DP_TP_CTL(port));
3098 }
3099
3100 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3101                                     const struct intel_crtc_state *crtc_state,
3102                                     const struct drm_connector_state *conn_state)
3103 {
3104         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3105         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3106         enum port port = encoder->port;
3107         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3108         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3109         int level = intel_ddi_dp_level(intel_dp);
3110
3111         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3112
3113         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3114                                  crtc_state->lane_count, is_mst);
3115
3116         intel_edp_panel_on(intel_dp);
3117
3118         intel_ddi_clk_select(encoder, crtc_state);
3119
3120         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3121
3122         icl_program_mg_dp_mode(dig_port);
3123         icl_disable_phy_clock_gating(dig_port);
3124
3125         if (INTEL_GEN(dev_priv) >= 11)
3126                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3127                                         level, encoder->type);
3128         else if (IS_CANNONLAKE(dev_priv))
3129                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3130         else if (IS_GEN9_LP(dev_priv))
3131                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3132         else
3133                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3134
3135         intel_ddi_init_dp_buf_reg(encoder);
3136         if (!is_mst)
3137                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3138         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3139                                               true);
3140         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3141         intel_dp_start_link_train(intel_dp);
3142         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3143                 intel_dp_stop_link_train(intel_dp);
3144
3145         intel_ddi_enable_fec(encoder, crtc_state);
3146
3147         icl_enable_phy_clock_gating(dig_port);
3148
3149         if (!is_mst)
3150                 intel_ddi_enable_pipe_clock(crtc_state);
3151
3152         intel_dsc_enable(encoder, crtc_state);
3153 }
3154
3155 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3156                                       const struct intel_crtc_state *crtc_state,
3157                                       const struct drm_connector_state *conn_state)
3158 {
3159         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3160         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3161         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3162         enum port port = encoder->port;
3163         int level = intel_ddi_hdmi_level(dev_priv, port);
3164         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3165
3166         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3167         intel_ddi_clk_select(encoder, crtc_state);
3168
3169         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3170
3171         icl_program_mg_dp_mode(dig_port);
3172         icl_disable_phy_clock_gating(dig_port);
3173
3174         if (INTEL_GEN(dev_priv) >= 11)
3175                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3176                                         level, INTEL_OUTPUT_HDMI);
3177         else if (IS_CANNONLAKE(dev_priv))
3178                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3179         else if (IS_GEN9_LP(dev_priv))
3180                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3181         else
3182                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3183
3184         icl_enable_phy_clock_gating(dig_port);
3185
3186         if (IS_GEN9_BC(dev_priv))
3187                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3188
3189         intel_ddi_enable_pipe_clock(crtc_state);
3190
3191         intel_dig_port->set_infoframes(encoder,
3192                                        crtc_state->has_infoframe,
3193                                        crtc_state, conn_state);
3194 }
3195
3196 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3197                                  const struct intel_crtc_state *crtc_state,
3198                                  const struct drm_connector_state *conn_state)
3199 {
3200         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3201         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3202         enum pipe pipe = crtc->pipe;
3203
3204         /*
3205          * When called from DP MST code:
3206          * - conn_state will be NULL
3207          * - encoder will be the main encoder (ie. mst->primary)
3208          * - the main connector associated with this port
3209          *   won't be active or linked to a crtc
3210          * - crtc_state will be the state of the first stream to
3211          *   be activated on this port, and it may not be the same
3212          *   stream that will be deactivated last, but each stream
3213          *   should have a state that is identical when it comes to
3214          *   the DP link parameteres
3215          */
3216
3217         WARN_ON(crtc_state->has_pch_encoder);
3218
3219         if (INTEL_GEN(dev_priv) >= 11)
3220                 icl_map_plls_to_ports(encoder, crtc_state);
3221
3222         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3223
3224         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3225                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3226         } else {
3227                 struct intel_lspcon *lspcon =
3228                                 enc_to_intel_lspcon(&encoder->base);
3229
3230                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3231                 if (lspcon->active) {
3232                         struct intel_digital_port *dig_port =
3233                                         enc_to_dig_port(&encoder->base);
3234
3235                         dig_port->set_infoframes(encoder,
3236                                                  crtc_state->has_infoframe,
3237                                                  crtc_state, conn_state);
3238                 }
3239         }
3240 }
3241
3242 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3243                                   const struct intel_crtc_state *crtc_state)
3244 {
3245         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3246         enum port port = encoder->port;
3247         bool wait = false;
3248         u32 val;
3249
3250         val = I915_READ(DDI_BUF_CTL(port));
3251         if (val & DDI_BUF_CTL_ENABLE) {
3252                 val &= ~DDI_BUF_CTL_ENABLE;
3253                 I915_WRITE(DDI_BUF_CTL(port), val);
3254                 wait = true;
3255         }
3256
3257         val = I915_READ(DP_TP_CTL(port));
3258         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3259         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3260         I915_WRITE(DP_TP_CTL(port), val);
3261
3262         /* Disable FEC in DP Sink */
3263         intel_ddi_disable_fec_state(encoder, crtc_state);
3264
3265         if (wait)
3266                 intel_wait_ddi_buf_idle(dev_priv, port);
3267 }
3268
3269 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3270                                       const struct intel_crtc_state *old_crtc_state,
3271                                       const struct drm_connector_state *old_conn_state)
3272 {
3273         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3274         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3275         struct intel_dp *intel_dp = &dig_port->dp;
3276         bool is_mst = intel_crtc_has_type(old_crtc_state,
3277                                           INTEL_OUTPUT_DP_MST);
3278
3279         if (!is_mst) {
3280                 intel_ddi_disable_pipe_clock(old_crtc_state);
3281                 /*
3282                  * Power down sink before disabling the port, otherwise we end
3283                  * up getting interrupts from the sink on detecting link loss.
3284                  */
3285                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3286         }
3287
3288         intel_disable_ddi_buf(encoder, old_crtc_state);
3289
3290         intel_edp_panel_vdd_on(intel_dp);
3291         intel_edp_panel_off(intel_dp);
3292
3293         intel_display_power_put_unchecked(dev_priv,
3294                                           dig_port->ddi_io_power_domain);
3295
3296         intel_ddi_clk_disable(encoder);
3297 }
3298
3299 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3300                                         const struct intel_crtc_state *old_crtc_state,
3301                                         const struct drm_connector_state *old_conn_state)
3302 {
3303         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3304         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3305         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3306
3307         dig_port->set_infoframes(encoder, false,
3308                                  old_crtc_state, old_conn_state);
3309
3310         intel_ddi_disable_pipe_clock(old_crtc_state);
3311
3312         intel_disable_ddi_buf(encoder, old_crtc_state);
3313
3314         intel_display_power_put_unchecked(dev_priv,
3315                                           dig_port->ddi_io_power_domain);
3316
3317         intel_ddi_clk_disable(encoder);
3318
3319         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3320 }
3321
3322 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3323                                    const struct intel_crtc_state *old_crtc_state,
3324                                    const struct drm_connector_state *old_conn_state)
3325 {
3326         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3327
3328         /*
3329          * When called from DP MST code:
3330          * - old_conn_state will be NULL
3331          * - encoder will be the main encoder (ie. mst->primary)
3332          * - the main connector associated with this port
3333          *   won't be active or linked to a crtc
3334          * - old_crtc_state will be the state of the last stream to
3335          *   be deactivated on this port, and it may not be the same
3336          *   stream that was activated last, but each stream
3337          *   should have a state that is identical when it comes to
3338          *   the DP link parameteres
3339          */
3340
3341         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3342                 intel_ddi_post_disable_hdmi(encoder,
3343                                             old_crtc_state, old_conn_state);
3344         else
3345                 intel_ddi_post_disable_dp(encoder,
3346                                           old_crtc_state, old_conn_state);
3347
3348         if (INTEL_GEN(dev_priv) >= 11)
3349                 icl_unmap_plls_to_ports(encoder);
3350 }
3351
3352 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3353                                 const struct intel_crtc_state *old_crtc_state,
3354                                 const struct drm_connector_state *old_conn_state)
3355 {
3356         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3357         u32 val;
3358
3359         /*
3360          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3361          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3362          * step 13 is the correct place for it. Step 18 is where it was
3363          * originally before the BUN.
3364          */
3365         val = I915_READ(FDI_RX_CTL(PIPE_A));
3366         val &= ~FDI_RX_ENABLE;
3367         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3368
3369         intel_disable_ddi_buf(encoder, old_crtc_state);
3370         intel_ddi_clk_disable(encoder);
3371
3372         val = I915_READ(FDI_RX_MISC(PIPE_A));
3373         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3374         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3375         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3376
3377         val = I915_READ(FDI_RX_CTL(PIPE_A));
3378         val &= ~FDI_PCDCLK;
3379         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3380
3381         val = I915_READ(FDI_RX_CTL(PIPE_A));
3382         val &= ~FDI_RX_PLL_ENABLE;
3383         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3384 }
3385
3386 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3387                                 const struct intel_crtc_state *crtc_state,
3388                                 const struct drm_connector_state *conn_state)
3389 {
3390         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3391         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3392         enum port port = encoder->port;
3393
3394         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3395                 intel_dp_stop_link_train(intel_dp);
3396
3397         intel_edp_backlight_on(crtc_state, conn_state);
3398         intel_psr_enable(intel_dp, crtc_state);
3399         intel_edp_drrs_enable(intel_dp, crtc_state);
3400
3401         if (crtc_state->has_audio)
3402                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3403 }
3404
3405 static i915_reg_t
3406 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3407                                enum port port)
3408 {
3409         static const i915_reg_t regs[] = {
3410                 [PORT_A] = CHICKEN_TRANS_EDP,
3411                 [PORT_B] = CHICKEN_TRANS_A,
3412                 [PORT_C] = CHICKEN_TRANS_B,
3413                 [PORT_D] = CHICKEN_TRANS_C,
3414                 [PORT_E] = CHICKEN_TRANS_A,
3415         };
3416
3417         WARN_ON(INTEL_GEN(dev_priv) < 9);
3418
3419         if (WARN_ON(port < PORT_A || port > PORT_E))
3420                 port = PORT_A;
3421
3422         return regs[port];
3423 }
3424
3425 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3426                                   const struct intel_crtc_state *crtc_state,
3427                                   const struct drm_connector_state *conn_state)
3428 {
3429         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3430         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3431         struct drm_connector *connector = conn_state->connector;
3432         enum port port = encoder->port;
3433
3434         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3435                                                crtc_state->hdmi_high_tmds_clock_ratio,
3436                                                crtc_state->hdmi_scrambling))
3437                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3438                           connector->base.id, connector->name);
3439
3440         /* Display WA #1143: skl,kbl,cfl */
3441         if (IS_GEN9_BC(dev_priv)) {
3442                 /*
3443                  * For some reason these chicken bits have been
3444                  * stuffed into a transcoder register, event though
3445                  * the bits affect a specific DDI port rather than
3446                  * a specific transcoder.
3447                  */
3448                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3449                 u32 val;
3450
3451                 val = I915_READ(reg);
3452
3453                 if (port == PORT_E)
3454                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3455                                 DDIE_TRAINING_OVERRIDE_VALUE;
3456                 else
3457                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3458                                 DDI_TRAINING_OVERRIDE_VALUE;
3459
3460                 I915_WRITE(reg, val);
3461                 POSTING_READ(reg);
3462
3463                 udelay(1);
3464
3465                 if (port == PORT_E)
3466                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3467                                  DDIE_TRAINING_OVERRIDE_VALUE);
3468                 else
3469                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3470                                  DDI_TRAINING_OVERRIDE_VALUE);
3471
3472                 I915_WRITE(reg, val);
3473         }
3474
3475         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3476          * are ignored so nothing special needs to be done besides
3477          * enabling the port.
3478          */
3479         I915_WRITE(DDI_BUF_CTL(port),
3480                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3481
3482         if (crtc_state->has_audio)
3483                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3484 }
3485
3486 static void intel_enable_ddi(struct intel_encoder *encoder,
3487                              const struct intel_crtc_state *crtc_state,
3488                              const struct drm_connector_state *conn_state)
3489 {
3490         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3491                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3492         else
3493                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3494
3495         /* Enable hdcp if it's desired */
3496         if (conn_state->content_protection ==
3497             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3498                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3499 }
3500
3501 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3502                                  const struct intel_crtc_state *old_crtc_state,
3503                                  const struct drm_connector_state *old_conn_state)
3504 {
3505         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3506
3507         intel_dp->link_trained = false;
3508
3509         if (old_crtc_state->has_audio)
3510                 intel_audio_codec_disable(encoder,
3511                                           old_crtc_state, old_conn_state);
3512
3513         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3514         intel_psr_disable(intel_dp, old_crtc_state);
3515         intel_edp_backlight_off(old_conn_state);
3516         /* Disable the decompression in DP Sink */
3517         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3518                                               false);
3519 }
3520
3521 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3522                                    const struct intel_crtc_state *old_crtc_state,
3523                                    const struct drm_connector_state *old_conn_state)
3524 {
3525         struct drm_connector *connector = old_conn_state->connector;
3526
3527         if (old_crtc_state->has_audio)
3528                 intel_audio_codec_disable(encoder,
3529                                           old_crtc_state, old_conn_state);
3530
3531         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3532                                                false, false))
3533                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3534                               connector->base.id, connector->name);
3535 }
3536
3537 static void intel_disable_ddi(struct intel_encoder *encoder,
3538                               const struct intel_crtc_state *old_crtc_state,
3539                               const struct drm_connector_state *old_conn_state)
3540 {
3541         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3542
3543         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3544                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3545         else
3546                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3547 }
3548
3549 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3550                                      const struct intel_crtc_state *crtc_state,
3551                                      const struct drm_connector_state *conn_state)
3552 {
3553         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3554
3555         intel_psr_update(intel_dp, crtc_state);
3556         intel_edp_drrs_enable(intel_dp, crtc_state);
3557
3558         intel_panel_update_backlight(encoder, crtc_state, conn_state);
3559 }
3560
3561 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3562                                   const struct intel_crtc_state *crtc_state,
3563                                   const struct drm_connector_state *conn_state)
3564 {
3565         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3566                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3567
3568         if (conn_state->content_protection ==
3569             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3570                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3571         else if (conn_state->content_protection ==
3572                  DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
3573                 intel_hdcp_disable(to_intel_connector(conn_state->connector));
3574 }
3575
3576 static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3577                                          const struct intel_crtc_state *pipe_config,
3578                                          enum port port)
3579 {
3580         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3581         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3582         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3583         u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3584         bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3585
3586         val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3587         switch (pipe_config->lane_count) {
3588         case 1:
3589                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3590                 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3591                 break;
3592         case 2:
3593                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3594                 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3595                 break;
3596         case 4:
3597                 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3598                 break;
3599         default:
3600                 MISSING_CASE(pipe_config->lane_count);
3601         }
3602         I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3603 }
3604
3605 static void
3606 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3607                          const struct intel_crtc_state *crtc_state,
3608                          const struct drm_connector_state *conn_state)
3609 {
3610         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3611         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3612         enum port port = encoder->port;
3613
3614         if (intel_crtc_has_dp_encoder(crtc_state) ||
3615             intel_port_is_tc(dev_priv, encoder->port))
3616                 intel_display_power_get(dev_priv,
3617                                         intel_ddi_main_link_aux_domain(dig_port));
3618
3619         if (IS_GEN9_LP(dev_priv))
3620                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3621                                                 crtc_state->lane_lat_optim_mask);
3622
3623         /*
3624          * Program the lane count for static/dynamic connections on Type-C ports.
3625          * Skip this step for TBT.
3626          */
3627         if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3628             dig_port->tc_type == TC_PORT_TBT)
3629                 return;
3630
3631         intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3632 }
3633
3634 static void
3635 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3636                            const struct intel_crtc_state *crtc_state,
3637                            const struct drm_connector_state *conn_state)
3638 {
3639         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3640         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3641
3642         if (intel_crtc_has_dp_encoder(crtc_state) ||
3643             intel_port_is_tc(dev_priv, encoder->port))
3644                 intel_display_power_put_unchecked(dev_priv,
3645                                                   intel_ddi_main_link_aux_domain(dig_port));
3646 }
3647
3648 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3649 {
3650         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3651         struct drm_i915_private *dev_priv =
3652                 to_i915(intel_dig_port->base.base.dev);
3653         enum port port = intel_dig_port->base.port;
3654         u32 val;
3655         bool wait = false;
3656
3657         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3658                 val = I915_READ(DDI_BUF_CTL(port));
3659                 if (val & DDI_BUF_CTL_ENABLE) {
3660                         val &= ~DDI_BUF_CTL_ENABLE;
3661                         I915_WRITE(DDI_BUF_CTL(port), val);
3662                         wait = true;
3663                 }
3664
3665                 val = I915_READ(DP_TP_CTL(port));
3666                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3667                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3668                 I915_WRITE(DP_TP_CTL(port), val);
3669                 POSTING_READ(DP_TP_CTL(port));
3670
3671                 if (wait)
3672                         intel_wait_ddi_buf_idle(dev_priv, port);
3673         }
3674
3675         val = DP_TP_CTL_ENABLE |
3676               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3677         if (intel_dp->link_mst)
3678                 val |= DP_TP_CTL_MODE_MST;
3679         else {
3680                 val |= DP_TP_CTL_MODE_SST;
3681                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3682                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3683         }
3684         I915_WRITE(DP_TP_CTL(port), val);
3685         POSTING_READ(DP_TP_CTL(port));
3686
3687         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3688         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3689         POSTING_READ(DDI_BUF_CTL(port));
3690
3691         udelay(600);
3692 }
3693
3694 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3695                                        enum transcoder cpu_transcoder)
3696 {
3697         if (cpu_transcoder == TRANSCODER_EDP)
3698                 return false;
3699
3700         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3701                 return false;
3702
3703         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3704                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3705 }
3706
3707 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3708                                          struct intel_crtc_state *crtc_state)
3709 {
3710         if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3711                 crtc_state->min_voltage_level = 1;
3712         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3713                 crtc_state->min_voltage_level = 2;
3714 }
3715
3716 void intel_ddi_get_config(struct intel_encoder *encoder,
3717                           struct intel_crtc_state *pipe_config)
3718 {
3719         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3720         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3721         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3722         struct intel_digital_port *intel_dig_port;
3723         u32 temp, flags = 0;
3724
3725         /* XXX: DSI transcoder paranoia */
3726         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3727                 return;
3728
3729         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3730         if (temp & TRANS_DDI_PHSYNC)
3731                 flags |= DRM_MODE_FLAG_PHSYNC;
3732         else
3733                 flags |= DRM_MODE_FLAG_NHSYNC;
3734         if (temp & TRANS_DDI_PVSYNC)
3735                 flags |= DRM_MODE_FLAG_PVSYNC;
3736         else
3737                 flags |= DRM_MODE_FLAG_NVSYNC;
3738
3739         pipe_config->base.adjusted_mode.flags |= flags;
3740
3741         switch (temp & TRANS_DDI_BPC_MASK) {
3742         case TRANS_DDI_BPC_6:
3743                 pipe_config->pipe_bpp = 18;
3744                 break;
3745         case TRANS_DDI_BPC_8:
3746                 pipe_config->pipe_bpp = 24;
3747                 break;
3748         case TRANS_DDI_BPC_10:
3749                 pipe_config->pipe_bpp = 30;
3750                 break;
3751         case TRANS_DDI_BPC_12:
3752                 pipe_config->pipe_bpp = 36;
3753                 break;
3754         default:
3755                 break;
3756         }
3757
3758         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3759         case TRANS_DDI_MODE_SELECT_HDMI:
3760                 pipe_config->has_hdmi_sink = true;
3761                 intel_dig_port = enc_to_dig_port(&encoder->base);
3762
3763                 pipe_config->infoframes.enable |=
3764                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3765
3766                 if (pipe_config->infoframes.enable)
3767                         pipe_config->has_infoframe = true;
3768
3769                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3770                         pipe_config->hdmi_scrambling = true;
3771                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3772                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3773                 /* fall through */
3774         case TRANS_DDI_MODE_SELECT_DVI:
3775                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3776                 pipe_config->lane_count = 4;
3777                 break;
3778         case TRANS_DDI_MODE_SELECT_FDI:
3779                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3780                 break;
3781         case TRANS_DDI_MODE_SELECT_DP_SST:
3782                 if (encoder->type == INTEL_OUTPUT_EDP)
3783                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3784                 else
3785                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3786                 pipe_config->lane_count =
3787                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3788                 intel_dp_get_m_n(intel_crtc, pipe_config);
3789                 break;
3790         case TRANS_DDI_MODE_SELECT_DP_MST:
3791                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3792                 pipe_config->lane_count =
3793                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3794                 intel_dp_get_m_n(intel_crtc, pipe_config);
3795                 break;
3796         default:
3797                 break;
3798         }
3799
3800         pipe_config->has_audio =
3801                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3802
3803         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3804             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3805                 /*
3806                  * This is a big fat ugly hack.
3807                  *
3808                  * Some machines in UEFI boot mode provide us a VBT that has 18
3809                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3810                  * unknown we fail to light up. Yet the same BIOS boots up with
3811                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3812                  * max, not what it tells us to use.
3813                  *
3814                  * Note: This will still be broken if the eDP panel is not lit
3815                  * up by the BIOS, and thus we can't get the mode at module
3816                  * load.
3817                  */
3818                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3819                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3820                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3821         }
3822
3823         intel_ddi_clock_get(encoder, pipe_config);
3824
3825         if (IS_GEN9_LP(dev_priv))
3826                 pipe_config->lane_lat_optim_mask =
3827                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3828
3829         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3830
3831         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3832
3833         intel_read_infoframe(encoder, pipe_config,
3834                              HDMI_INFOFRAME_TYPE_AVI,
3835                              &pipe_config->infoframes.avi);
3836         intel_read_infoframe(encoder, pipe_config,
3837                              HDMI_INFOFRAME_TYPE_SPD,
3838                              &pipe_config->infoframes.spd);
3839         intel_read_infoframe(encoder, pipe_config,
3840                              HDMI_INFOFRAME_TYPE_VENDOR,
3841                              &pipe_config->infoframes.hdmi);
3842 }
3843
3844 static enum intel_output_type
3845 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3846                               struct intel_crtc_state *crtc_state,
3847                               struct drm_connector_state *conn_state)
3848 {
3849         switch (conn_state->connector->connector_type) {
3850         case DRM_MODE_CONNECTOR_HDMIA:
3851                 return INTEL_OUTPUT_HDMI;
3852         case DRM_MODE_CONNECTOR_eDP:
3853                 return INTEL_OUTPUT_EDP;
3854         case DRM_MODE_CONNECTOR_DisplayPort:
3855                 return INTEL_OUTPUT_DP;
3856         default:
3857                 MISSING_CASE(conn_state->connector->connector_type);
3858                 return INTEL_OUTPUT_UNUSED;
3859         }
3860 }
3861
3862 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3863                                     struct intel_crtc_state *pipe_config,
3864                                     struct drm_connector_state *conn_state)
3865 {
3866         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3867         enum port port = encoder->port;
3868         int ret;
3869
3870         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
3871                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3872
3873         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3874                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3875         else
3876                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3877
3878         if (IS_GEN9_LP(dev_priv) && ret)
3879                 pipe_config->lane_lat_optim_mask =
3880                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3881
3882         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3883
3884         return ret;
3885
3886 }
3887
3888 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3889 {
3890         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3891         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3892
3893         intel_dp_encoder_suspend(encoder);
3894
3895         /*
3896          * TODO: disconnect also from USB DP alternate mode once we have a
3897          * way to handle the modeset restore in that mode during resume
3898          * even if the sink has disappeared while being suspended.
3899          */
3900         if (dig_port->tc_legacy_port)
3901                 icl_tc_phy_disconnect(i915, dig_port);
3902 }
3903
3904 static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3905 {
3906         struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3907         struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3908
3909         if (intel_port_is_tc(i915, dig_port->base.port))
3910                 intel_digital_port_connected(&dig_port->base);
3911
3912         intel_dp_encoder_reset(drm_encoder);
3913 }
3914
3915 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3916 {
3917         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3918         struct drm_i915_private *i915 = to_i915(encoder->dev);
3919
3920         intel_dp_encoder_flush_work(encoder);
3921
3922         if (intel_port_is_tc(i915, dig_port->base.port))
3923                 icl_tc_phy_disconnect(i915, dig_port);
3924
3925         drm_encoder_cleanup(encoder);
3926         kfree(dig_port);
3927 }
3928
3929 static const struct drm_encoder_funcs intel_ddi_funcs = {
3930         .reset = intel_ddi_encoder_reset,
3931         .destroy = intel_ddi_encoder_destroy,
3932 };
3933
3934 static struct intel_connector *
3935 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3936 {
3937         struct intel_connector *connector;
3938         enum port port = intel_dig_port->base.port;
3939
3940         connector = intel_connector_alloc();
3941         if (!connector)
3942                 return NULL;
3943
3944         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3945         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3946                 kfree(connector);
3947                 return NULL;
3948         }
3949
3950         return connector;
3951 }
3952
3953 static int modeset_pipe(struct drm_crtc *crtc,
3954                         struct drm_modeset_acquire_ctx *ctx)
3955 {
3956         struct drm_atomic_state *state;
3957         struct drm_crtc_state *crtc_state;
3958         int ret;
3959
3960         state = drm_atomic_state_alloc(crtc->dev);
3961         if (!state)
3962                 return -ENOMEM;
3963
3964         state->acquire_ctx = ctx;
3965
3966         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3967         if (IS_ERR(crtc_state)) {
3968                 ret = PTR_ERR(crtc_state);
3969                 goto out;
3970         }
3971
3972         crtc_state->connectors_changed = true;
3973
3974         ret = drm_atomic_commit(state);
3975 out:
3976         drm_atomic_state_put(state);
3977
3978         return ret;
3979 }
3980
3981 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3982                                  struct drm_modeset_acquire_ctx *ctx)
3983 {
3984         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3985         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3986         struct intel_connector *connector = hdmi->attached_connector;
3987         struct i2c_adapter *adapter =
3988                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3989         struct drm_connector_state *conn_state;
3990         struct intel_crtc_state *crtc_state;
3991         struct intel_crtc *crtc;
3992         u8 config;
3993         int ret;
3994
3995         if (!connector || connector->base.status != connector_status_connected)
3996                 return 0;
3997
3998         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3999                                ctx);
4000         if (ret)
4001                 return ret;
4002
4003         conn_state = connector->base.state;
4004
4005         crtc = to_intel_crtc(conn_state->crtc);
4006         if (!crtc)
4007                 return 0;
4008
4009         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4010         if (ret)
4011                 return ret;
4012
4013         crtc_state = to_intel_crtc_state(crtc->base.state);
4014
4015         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4016
4017         if (!crtc_state->base.active)
4018                 return 0;
4019
4020         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4021             !crtc_state->hdmi_scrambling)
4022                 return 0;
4023
4024         if (conn_state->commit &&
4025             !try_wait_for_completion(&conn_state->commit->hw_done))
4026                 return 0;
4027
4028         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4029         if (ret < 0) {
4030                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4031                 return 0;
4032         }
4033
4034         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4035             crtc_state->hdmi_high_tmds_clock_ratio &&
4036             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4037             crtc_state->hdmi_scrambling)
4038                 return 0;
4039
4040         /*
4041          * HDMI 2.0 says that one should not send scrambled data
4042          * prior to configuring the sink scrambling, and that
4043          * TMDS clock/data transmission should be suspended when
4044          * changing the TMDS clock rate in the sink. So let's
4045          * just do a full modeset here, even though some sinks
4046          * would be perfectly happy if were to just reconfigure
4047          * the SCDC settings on the fly.
4048          */
4049         return modeset_pipe(&crtc->base, ctx);
4050 }
4051
4052 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4053                               struct intel_connector *connector)
4054 {
4055         struct drm_modeset_acquire_ctx ctx;
4056         bool changed;
4057         int ret;
4058
4059         changed = intel_encoder_hotplug(encoder, connector);
4060
4061         drm_modeset_acquire_init(&ctx, 0);
4062
4063         for (;;) {
4064                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4065                         ret = intel_hdmi_reset_link(encoder, &ctx);
4066                 else
4067                         ret = intel_dp_retrain_link(encoder, &ctx);
4068
4069                 if (ret == -EDEADLK) {
4070                         drm_modeset_backoff(&ctx);
4071                         continue;
4072                 }
4073
4074                 break;
4075         }
4076
4077         drm_modeset_drop_locks(&ctx);
4078         drm_modeset_acquire_fini(&ctx);
4079         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4080
4081         return changed;
4082 }
4083
4084 static struct intel_connector *
4085 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4086 {
4087         struct intel_connector *connector;
4088         enum port port = intel_dig_port->base.port;
4089
4090         connector = intel_connector_alloc();
4091         if (!connector)
4092                 return NULL;
4093
4094         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4095         intel_hdmi_init_connector(intel_dig_port, connector);
4096
4097         return connector;
4098 }
4099
4100 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4101 {
4102         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4103
4104         if (dport->base.port != PORT_A)
4105                 return false;
4106
4107         if (dport->saved_port_bits & DDI_A_4_LANES)
4108                 return false;
4109
4110         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4111          *                     supported configuration
4112          */
4113         if (IS_GEN9_LP(dev_priv))
4114                 return true;
4115
4116         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4117          *             one who does also have a full A/E split called
4118          *             DDI_F what makes DDI_E useless. However for this
4119          *             case let's trust VBT info.
4120          */
4121         if (IS_CANNONLAKE(dev_priv) &&
4122             !intel_bios_is_port_present(dev_priv, PORT_E))
4123                 return true;
4124
4125         return false;
4126 }
4127
4128 static int
4129 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4130 {
4131         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4132         enum port port = intel_dport->base.port;
4133         int max_lanes = 4;
4134
4135         if (INTEL_GEN(dev_priv) >= 11)
4136                 return max_lanes;
4137
4138         if (port == PORT_A || port == PORT_E) {
4139                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4140                         max_lanes = port == PORT_A ? 4 : 0;
4141                 else
4142                         /* Both A and E share 2 lanes */
4143                         max_lanes = 2;
4144         }
4145
4146         /*
4147          * Some BIOS might fail to set this bit on port A if eDP
4148          * wasn't lit up at boot.  Force this bit set when needed
4149          * so we use the proper lane count for our calculations.
4150          */
4151         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4152                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4153                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4154                 max_lanes = 4;
4155         }
4156
4157         return max_lanes;
4158 }
4159
4160 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4161 {
4162         struct ddi_vbt_port_info *port_info =
4163                 &dev_priv->vbt.ddi_port_info[port];
4164         struct intel_digital_port *intel_dig_port;
4165         struct intel_encoder *intel_encoder;
4166         struct drm_encoder *encoder;
4167         bool init_hdmi, init_dp, init_lspcon = false;
4168         enum pipe pipe;
4169
4170         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4171         init_dp = port_info->supports_dp;
4172
4173         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4174                 /*
4175                  * Lspcon device needs to be driven with DP connector
4176                  * with special detection sequence. So make sure DP
4177                  * is initialized before lspcon.
4178                  */
4179                 init_dp = true;
4180                 init_lspcon = true;
4181                 init_hdmi = false;
4182                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4183         }
4184
4185         if (!init_dp && !init_hdmi) {
4186                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4187                               port_name(port));
4188                 return;
4189         }
4190
4191         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4192         if (!intel_dig_port)
4193                 return;
4194
4195         intel_encoder = &intel_dig_port->base;
4196         encoder = &intel_encoder->base;
4197
4198         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4199                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4200
4201         intel_encoder->hotplug = intel_ddi_hotplug;
4202         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4203         intel_encoder->compute_config = intel_ddi_compute_config;
4204         intel_encoder->enable = intel_enable_ddi;
4205         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4206         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4207         intel_encoder->pre_enable = intel_ddi_pre_enable;
4208         intel_encoder->disable = intel_disable_ddi;
4209         intel_encoder->post_disable = intel_ddi_post_disable;
4210         intel_encoder->update_pipe = intel_ddi_update_pipe;
4211         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4212         intel_encoder->get_config = intel_ddi_get_config;
4213         intel_encoder->suspend = intel_ddi_encoder_suspend;
4214         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4215         intel_encoder->type = INTEL_OUTPUT_DDI;
4216         intel_encoder->power_domain = intel_port_to_power_domain(port);
4217         intel_encoder->port = port;
4218         intel_encoder->cloneable = 0;
4219         for_each_pipe(dev_priv, pipe)
4220                 intel_encoder->crtc_mask |= BIT(pipe);
4221
4222         if (INTEL_GEN(dev_priv) >= 11)
4223                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4224                         DDI_BUF_PORT_REVERSAL;
4225         else
4226                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4227                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4228         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4229         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4230         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4231
4232         intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
4233                                          !port_info->supports_typec_usb &&
4234                                          !port_info->supports_tbt;
4235
4236         switch (port) {
4237         case PORT_A:
4238                 intel_dig_port->ddi_io_power_domain =
4239                         POWER_DOMAIN_PORT_DDI_A_IO;
4240                 break;
4241         case PORT_B:
4242                 intel_dig_port->ddi_io_power_domain =
4243                         POWER_DOMAIN_PORT_DDI_B_IO;
4244                 break;
4245         case PORT_C:
4246                 intel_dig_port->ddi_io_power_domain =
4247                         POWER_DOMAIN_PORT_DDI_C_IO;
4248                 break;
4249         case PORT_D:
4250                 intel_dig_port->ddi_io_power_domain =
4251                         POWER_DOMAIN_PORT_DDI_D_IO;
4252                 break;
4253         case PORT_E:
4254                 intel_dig_port->ddi_io_power_domain =
4255                         POWER_DOMAIN_PORT_DDI_E_IO;
4256                 break;
4257         case PORT_F:
4258                 intel_dig_port->ddi_io_power_domain =
4259                         POWER_DOMAIN_PORT_DDI_F_IO;
4260                 break;
4261         default:
4262                 MISSING_CASE(port);
4263         }
4264
4265         if (init_dp) {
4266                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4267                         goto err;
4268
4269                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4270         }
4271
4272         /* In theory we don't need the encoder->type check, but leave it just in
4273          * case we have some really bad VBTs... */
4274         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4275                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4276                         goto err;
4277         }
4278
4279         if (init_lspcon) {
4280                 if (lspcon_init(intel_dig_port))
4281                         /* TODO: handle hdmi info frame part */
4282                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4283                                 port_name(port));
4284                 else
4285                         /*
4286                          * LSPCON init faied, but DP init was success, so
4287                          * lets try to drive as DP++ port.
4288                          */
4289                         DRM_ERROR("LSPCON init failed on port %c\n",
4290                                 port_name(port));
4291         }
4292
4293         intel_infoframe_init(intel_dig_port);
4294
4295         if (intel_port_is_tc(dev_priv, port))
4296                 intel_digital_port_connected(intel_encoder);
4297
4298         return;
4299
4300 err:
4301         drm_encoder_cleanup(encoder);
4302         kfree(intel_dig_port);
4303 }