drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "intel_dsi.h"
  32
  33 struct ddi_buf_trans {
  34         u32 trans1;     /* balance leg enable, de-emph level */
  35         u32 trans2;     /* vref sel, vswing */
  36         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  37 };
  38
  39 static const u8 index_to_dp_signal_levels[] = {
  40         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  41         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  42         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  43         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  44         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  45         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  46         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  47         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  48         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  49         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  50 };
  51
  52 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  53  * them for both DP and FDI transports, allowing those ports to
  54  * automatically adapt to HDMI connections as well
  55  */
  56 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  57         { 0x00FFFFFF, 0x0006000E, 0x0 },
  58         { 0x00D75FFF, 0x0005000A, 0x0 },
  59         { 0x00C30FFF, 0x00040006, 0x0 },
  60         { 0x80AAAFFF, 0x000B0000, 0x0 },
  61         { 0x00FFFFFF, 0x0005000A, 0x0 },
  62         { 0x00D75FFF, 0x000C0004, 0x0 },
  63         { 0x80C30FFF, 0x000B0000, 0x0 },
  64         { 0x00FFFFFF, 0x00040006, 0x0 },
  65         { 0x80D75FFF, 0x000B0000, 0x0 },
  66 };
  67
  68 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  69         { 0x00FFFFFF, 0x0007000E, 0x0 },
  70         { 0x00D75FFF, 0x000F000A, 0x0 },
  71         { 0x00C30FFF, 0x00060006, 0x0 },
  72         { 0x00AAAFFF, 0x001E0000, 0x0 },
  73         { 0x00FFFFFF, 0x000F000A, 0x0 },
  74         { 0x00D75FFF, 0x00160004, 0x0 },
  75         { 0x00C30FFF, 0x001E0000, 0x0 },
  76         { 0x00FFFFFF, 0x00060006, 0x0 },
  77         { 0x00D75FFF, 0x001E0000, 0x0 },
  78 };
  79
  80 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  81                                         /* Idx  NT mV d T mV d  db      */
  82         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  83         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  84         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  85         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  86         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  87         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  88         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  89         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  90         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  91         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  92         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  93         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  94 };
  95
  96 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  97         { 0x00FFFFFF, 0x00000012, 0x0 },
  98         { 0x00EBAFFF, 0x00020011, 0x0 },
  99         { 0x00C71FFF, 0x0006000F, 0x0 },
 100         { 0x00AAAFFF, 0x000E000A, 0x0 },
 101         { 0x00FFFFFF, 0x00020011, 0x0 },
 102         { 0x00DB6FFF, 0x0005000F, 0x0 },
 103         { 0x00BEEFFF, 0x000A000C, 0x0 },
 104         { 0x00FFFFFF, 0x0005000F, 0x0 },
 105         { 0x00DB6FFF, 0x000A000C, 0x0 },
 106 };
 107
 108 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 109         { 0x00FFFFFF, 0x0007000E, 0x0 },
 110         { 0x00D75FFF, 0x000E000A, 0x0 },
 111         { 0x00BEFFFF, 0x00140006, 0x0 },
 112         { 0x80B2CFFF, 0x001B0002, 0x0 },
 113         { 0x00FFFFFF, 0x000E000A, 0x0 },
 114         { 0x00DB6FFF, 0x00160005, 0x0 },
 115         { 0x80C71FFF, 0x001A0002, 0x0 },
 116         { 0x00F7DFFF, 0x00180004, 0x0 },
 117         { 0x80D75FFF, 0x001B0002, 0x0 },
 118 };
 119
 120 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 121         { 0x00FFFFFF, 0x0001000E, 0x0 },
 122         { 0x00D75FFF, 0x0004000A, 0x0 },
 123         { 0x00C30FFF, 0x00070006, 0x0 },
 124         { 0x00AAAFFF, 0x000C0000, 0x0 },
 125         { 0x00FFFFFF, 0x0004000A, 0x0 },
 126         { 0x00D75FFF, 0x00090004, 0x0 },
 127         { 0x00C30FFF, 0x000C0000, 0x0 },
 128         { 0x00FFFFFF, 0x00070006, 0x0 },
 129         { 0x00D75FFF, 0x000C0000, 0x0 },
 130 };
 131
 132 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 133                                         /* Idx  NT mV d T mV df db      */
 134         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 135         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 136         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 137         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 138         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 139         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 140         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 141         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 142         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 143         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 144 };
 145
 146 /* Skylake H and S */
 147 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 148         { 0x00002016, 0x000000A0, 0x0 },
 149         { 0x00005012, 0x0000009B, 0x0 },
 150         { 0x00007011, 0x00000088, 0x0 },
 151         { 0x80009010, 0x000000C0, 0x1 },
 152         { 0x00002016, 0x0000009B, 0x0 },
 153         { 0x00005012, 0x00000088, 0x0 },
 154         { 0x80007011, 0x000000C0, 0x1 },
 155         { 0x00002016, 0x000000DF, 0x0 },
 156         { 0x80005012, 0x000000C0, 0x1 },
 157 };
 158
 159 /* Skylake U */
 160 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 161         { 0x0000201B, 0x000000A2, 0x0 },
 162         { 0x00005012, 0x00000088, 0x0 },
 163         { 0x80007011, 0x000000CD, 0x1 },
 164         { 0x80009010, 0x000000C0, 0x1 },
 165         { 0x0000201B, 0x0000009D, 0x0 },
 166         { 0x80005012, 0x000000C0, 0x1 },
 167         { 0x80007011, 0x000000C0, 0x1 },
 168         { 0x00002016, 0x00000088, 0x0 },
 169         { 0x80005012, 0x000000C0, 0x1 },
 170 };
 171
 172 /* Skylake Y */
 173 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 174         { 0x00000018, 0x000000A2, 0x0 },
 175         { 0x00005012, 0x00000088, 0x0 },
 176         { 0x80007011, 0x000000CD, 0x3 },
 177         { 0x80009010, 0x000000C0, 0x3 },
 178         { 0x00000018, 0x0000009D, 0x0 },
 179         { 0x80005012, 0x000000C0, 0x3 },
 180         { 0x80007011, 0x000000C0, 0x3 },
 181         { 0x00000018, 0x00000088, 0x0 },
 182         { 0x80005012, 0x000000C0, 0x3 },
 183 };
 184
 185 /* Kabylake H and S */
 186 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 187         { 0x00002016, 0x000000A0, 0x0 },
 188         { 0x00005012, 0x0000009B, 0x0 },
 189         { 0x00007011, 0x00000088, 0x0 },
 190         { 0x80009010, 0x000000C0, 0x1 },
 191         { 0x00002016, 0x0000009B, 0x0 },
 192         { 0x00005012, 0x00000088, 0x0 },
 193         { 0x80007011, 0x000000C0, 0x1 },
 194         { 0x00002016, 0x00000097, 0x0 },
 195         { 0x80005012, 0x000000C0, 0x1 },
 196 };
 197
 198 /* Kabylake U */
 199 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 200         { 0x0000201B, 0x000000A1, 0x0 },
 201         { 0x00005012, 0x00000088, 0x0 },
 202         { 0x80007011, 0x000000CD, 0x3 },
 203         { 0x80009010, 0x000000C0, 0x3 },
 204         { 0x0000201B, 0x0000009D, 0x0 },
 205         { 0x80005012, 0x000000C0, 0x3 },
 206         { 0x80007011, 0x000000C0, 0x3 },
 207         { 0x00002016, 0x0000004F, 0x0 },
 208         { 0x80005012, 0x000000C0, 0x3 },
 209 };
 210
 211 /* Kabylake Y */
 212 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 213         { 0x00001017, 0x000000A1, 0x0 },
 214         { 0x00005012, 0x00000088, 0x0 },
 215         { 0x80007011, 0x000000CD, 0x3 },
 216         { 0x8000800F, 0x000000C0, 0x3 },
 217         { 0x00001017, 0x0000009D, 0x0 },
 218         { 0x80005012, 0x000000C0, 0x3 },
 219         { 0x80007011, 0x000000C0, 0x3 },
 220         { 0x00001017, 0x0000004C, 0x0 },
 221         { 0x80005012, 0x000000C0, 0x3 },
 222 };
 223
 224 /*
 225  * Skylake/Kabylake H and S
 226  * eDP 1.4 low vswing translation parameters
 227  */
 228 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 229         { 0x00000018, 0x000000A8, 0x0 },
 230         { 0x00004013, 0x000000A9, 0x0 },
 231         { 0x00007011, 0x000000A2, 0x0 },
 232         { 0x00009010, 0x0000009C, 0x0 },
 233         { 0x00000018, 0x000000A9, 0x0 },
 234         { 0x00006013, 0x000000A2, 0x0 },
 235         { 0x00007011, 0x000000A6, 0x0 },
 236         { 0x00000018, 0x000000AB, 0x0 },
 237         { 0x00007013, 0x0000009F, 0x0 },
 238         { 0x00000018, 0x000000DF, 0x0 },
 239 };
 240
 241 /*
 242  * Skylake/Kabylake U
 243  * eDP 1.4 low vswing translation parameters
 244  */
 245 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 246         { 0x00000018, 0x000000A8, 0x0 },
 247         { 0x00004013, 0x000000A9, 0x0 },
 248         { 0x00007011, 0x000000A2, 0x0 },
 249         { 0x00009010, 0x0000009C, 0x0 },
 250         { 0x00000018, 0x000000A9, 0x0 },
 251         { 0x00006013, 0x000000A2, 0x0 },
 252         { 0x00007011, 0x000000A6, 0x0 },
 253         { 0x00002016, 0x000000AB, 0x0 },
 254         { 0x00005013, 0x0000009F, 0x0 },
 255         { 0x00000018, 0x000000DF, 0x0 },
 256 };
 257
 258 /*
 259  * Skylake/Kabylake Y
 260  * eDP 1.4 low vswing translation parameters
 261  */
 262 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 263         { 0x00000018, 0x000000A8, 0x0 },
 264         { 0x00004013, 0x000000AB, 0x0 },
 265         { 0x00007011, 0x000000A4, 0x0 },
 266         { 0x00009010, 0x000000DF, 0x0 },
 267         { 0x00000018, 0x000000AA, 0x0 },
 268         { 0x00006013, 0x000000A4, 0x0 },
 269         { 0x00007011, 0x0000009D, 0x0 },
 270         { 0x00000018, 0x000000A0, 0x0 },
 271         { 0x00006012, 0x000000DF, 0x0 },
 272         { 0x00000018, 0x0000008A, 0x0 },
 273 };
 274
 275 /* Skylake/Kabylake U, H and S */
 276 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 277         { 0x00000018, 0x000000AC, 0x0 },
 278         { 0x00005012, 0x0000009D, 0x0 },
 279         { 0x00007011, 0x00000088, 0x0 },
 280         { 0x00000018, 0x000000A1, 0x0 },
 281         { 0x00000018, 0x00000098, 0x0 },
 282         { 0x00004013, 0x00000088, 0x0 },
 283         { 0x80006012, 0x000000CD, 0x1 },
 284         { 0x00000018, 0x000000DF, 0x0 },
 285         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 286         { 0x80003015, 0x000000C0, 0x1 },
 287         { 0x80000018, 0x000000C0, 0x1 },
 288 };
 289
 290 /* Skylake/Kabylake Y */
 291 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 292         { 0x00000018, 0x000000A1, 0x0 },
 293         { 0x00005012, 0x000000DF, 0x0 },
 294         { 0x80007011, 0x000000CB, 0x3 },
 295         { 0x00000018, 0x000000A4, 0x0 },
 296         { 0x00000018, 0x0000009D, 0x0 },
 297         { 0x00004013, 0x00000080, 0x0 },
 298         { 0x80006013, 0x000000C0, 0x3 },
 299         { 0x00000018, 0x0000008A, 0x0 },
 300         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 301         { 0x80003015, 0x000000C0, 0x3 },
 302         { 0x80000018, 0x000000C0, 0x3 },
 303 };
 304
 305 struct bxt_ddi_buf_trans {
 306         u8 margin;      /* swing value */
 307         u8 scale;       /* scale value */
 308         u8 enable;      /* scale enable */
 309         u8 deemphasis;
 310 };
 311
 312 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 313                                         /* Idx  NT mV diff      db  */
 314         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 315         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 316         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 317         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 318         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 319         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 320         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 321         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 322         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 323         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 324 };
 325
 326 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 327                                         /* Idx  NT mV diff      db  */
 328         { 26, 0, 0, 128, },     /* 0:   200             0   */
 329         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 330         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 331         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 332         { 32, 0, 0, 128, },     /* 4:   250             0   */
 333         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 334         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 335         { 43, 0, 0, 128, },     /* 7:   300             0   */
 336         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 337         { 48, 0, 0, 128, },     /* 9:   300             0   */
 338 };
 339
 340 /* BSpec has 2 recommended values - entries 0 and 8.
 341  * Using the entry with higher vswing.
 342  */
 343 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 344                                         /* Idx  NT mV diff      db  */
 345         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 346         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 347         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 348         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 349         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 350         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 351         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 352         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 353         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 354         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 355 };
 356
 357 struct cnl_ddi_buf_trans {
 358         u8 dw2_swing_sel;
 359         u8 dw7_n_scalar;
 360         u8 dw4_cursor_coeff;
 361         u8 dw4_post_cursor_2;
 362         u8 dw4_post_cursor_1;
 363 };
 364
 365 /* Voltage Swing Programming for VccIO 0.85V for DP */
 366 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 367                                                 /* NT mV Trans mV db    */
 368         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 369         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 370         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 371         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 372         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 373         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 374         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 375         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 376         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 377         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 378 };
 379
 380 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 381 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 382                                                 /* NT mV Trans mV db    */
 383         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 384         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 385         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 386         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 387         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 388         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 389         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 390 };
 391
 392 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 393 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 394                                                 /* NT mV Trans mV db    */
 395         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 396         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 397         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 398         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 399         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 400         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 401         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 402         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 403         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 404 };
 405
 406 /* Voltage Swing Programming for VccIO 0.95V for DP */
 407 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 408                                                 /* NT mV Trans mV db    */
 409         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 410         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 411         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 412         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 413         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 414         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 415         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 416         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 417         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 418         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 419 };
 420
 421 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 422 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 423                                                 /* NT mV Trans mV db    */
 424         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 425         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 426         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 427         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 428         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 429         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 430         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 431         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 432         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 433         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 434         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 435 };
 436
 437 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 438 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 439                                                 /* NT mV Trans mV db    */
 440         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 441         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 442         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 443         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 444         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 445         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 446         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 447         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 448         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 449         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 450 };
 451
 452 /* Voltage Swing Programming for VccIO 1.05V for DP */
 453 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 454                                                 /* NT mV Trans mV db    */
 455         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 456         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 457         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 458         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 459         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 460         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 461         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 462         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 463         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 464         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 465 };
 466
 467 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 468 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 469                                                 /* NT mV Trans mV db    */
 470         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 471         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 472         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 473         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 474         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 475         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 476         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 477         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 478         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 479         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 480         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 481 };
 482
 483 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 484 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 485                                                 /* NT mV Trans mV db    */
 486         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 487         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 488         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 489         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 490         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 491         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 492         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 493         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 494         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 495 };
 496
 497 /* icl_combo_phy_ddi_translations */
 498 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 499                                                 /* NT mV Trans mV db    */
 500         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 501         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 502         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 503         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 504         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 505         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 506         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 507         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 508         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 509         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 510 };
 511
 512 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 513                                                 /* NT mV Trans mV db    */
 514         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 515         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 516         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 517         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 518         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 519         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 520         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 521         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 522         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 523         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 524 };
 525
 526 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 527                                                 /* NT mV Trans mV db    */
 528         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 529         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 530         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 531         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 532         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 533         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 534         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 535         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 536         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 537         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 538 };
 539
 540 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 541                                                 /* NT mV Trans mV db    */
 542         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 543         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 544         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 545         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 546         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 547         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 548         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 549 };
 550
 551 struct icl_mg_phy_ddi_buf_trans {
 552         u32 cri_txdeemph_override_5_0;
 553         u32 cri_txdeemph_override_11_6;
 554         u32 cri_txdeemph_override_17_12;
 555 };
 556
 557 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 558                                 /* Voltage swing  pre-emphasis */
 559         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 560         { 0x0, 0x23, 0x08 },    /* 0              1   */
 561         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 562         { 0x0, 0x00, 0x00 },    /* 0              3   */
 563         { 0x0, 0x23, 0x00 },    /* 1              0   */
 564         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 565         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 566         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 567         { 0x0, 0x33, 0x0C },    /* 2              1   */
 568         { 0x0, 0x00, 0x00 },    /* 3              0   */
 569 };
 570
 571 static const struct ddi_buf_trans *
 572 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 573 {
 574         if (dev_priv->vbt.edp.low_vswing) {
 575                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 576                 return bdw_ddi_translations_edp;
 577         } else {
 578                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 579                 return bdw_ddi_translations_dp;
 580         }
 581 }
 582
 583 static const struct ddi_buf_trans *
 584 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 585 {
 586         if (IS_SKL_ULX(dev_priv)) {
 587                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 588                 return skl_y_ddi_translations_dp;
 589         } else if (IS_SKL_ULT(dev_priv)) {
 590                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 591                 return skl_u_ddi_translations_dp;
 592         } else {
 593                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 594                 return skl_ddi_translations_dp;
 595         }
 596 }
 597
 598 static const struct ddi_buf_trans *
 599 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 600 {
 601         if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 602                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 603                 return kbl_y_ddi_translations_dp;
 604         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 605                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 606                 return kbl_u_ddi_translations_dp;
 607         } else {
 608                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 609                 return kbl_ddi_translations_dp;
 610         }
 611 }
 612
 613 static const struct ddi_buf_trans *
 614 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 615 {
 616         if (dev_priv->vbt.edp.low_vswing) {
 617                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 618                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 619                         return skl_y_ddi_translations_edp;
 620                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 621                            IS_CFL_ULT(dev_priv)) {
 622                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 623                         return skl_u_ddi_translations_edp;
 624                 } else {
 625                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 626                         return skl_ddi_translations_edp;
 627                 }
 628         }
 629
 630         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 631                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 632         else
 633                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 634 }
 635
 636 static const struct ddi_buf_trans *
 637 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 638 {
 639         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 640                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 641                 return skl_y_ddi_translations_hdmi;
 642         } else {
 643                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 644                 return skl_ddi_translations_hdmi;
 645         }
 646 }
 647
 648 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 649 {
 650         /* Only DDIA and DDIE can select the 10th register with DP */
 651         if (port == PORT_A || port == PORT_E)
 652                 return min(n_entries, 10);
 653         else
 654                 return min(n_entries, 9);
 655 }
 656
 657 static const struct ddi_buf_trans *
 658 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 659                            enum port port, int *n_entries)
 660 {
 661         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 662                 const struct ddi_buf_trans *ddi_translations =
 663                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 664                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 665                 return ddi_translations;
 666         } else if (IS_SKYLAKE(dev_priv)) {
 667                 const struct ddi_buf_trans *ddi_translations =
 668                         skl_get_buf_trans_dp(dev_priv, n_entries);
 669                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 670                 return ddi_translations;
 671         } else if (IS_BROADWELL(dev_priv)) {
 672                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 673                 return  bdw_ddi_translations_dp;
 674         } else if (IS_HASWELL(dev_priv)) {
 675                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 676                 return hsw_ddi_translations_dp;
 677         }
 678
 679         *n_entries = 0;
 680         return NULL;
 681 }
 682
 683 static const struct ddi_buf_trans *
 684 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 685                             enum port port, int *n_entries)
 686 {
 687         if (IS_GEN9_BC(dev_priv)) {
 688                 const struct ddi_buf_trans *ddi_translations =
 689                         skl_get_buf_trans_edp(dev_priv, n_entries);
 690                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 691                 return ddi_translations;
 692         } else if (IS_BROADWELL(dev_priv)) {
 693                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 694         } else if (IS_HASWELL(dev_priv)) {
 695                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 696                 return hsw_ddi_translations_dp;
 697         }
 698
 699         *n_entries = 0;
 700         return NULL;
 701 }
 702
 703 static const struct ddi_buf_trans *
 704 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 705                             int *n_entries)
 706 {
 707         if (IS_BROADWELL(dev_priv)) {
 708                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 709                 return bdw_ddi_translations_fdi;
 710         } else if (IS_HASWELL(dev_priv)) {
 711                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 712                 return hsw_ddi_translations_fdi;
 713         }
 714
 715         *n_entries = 0;
 716         return NULL;
 717 }
 718
 719 static const struct ddi_buf_trans *
 720 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 721                              int *n_entries)
 722 {
 723         if (IS_GEN9_BC(dev_priv)) {
 724                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 725         } else if (IS_BROADWELL(dev_priv)) {
 726                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 727                 return bdw_ddi_translations_hdmi;
 728         } else if (IS_HASWELL(dev_priv)) {
 729                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 730                 return hsw_ddi_translations_hdmi;
 731         }
 732
 733         *n_entries = 0;
 734         return NULL;
 735 }
 736
 737 static const struct bxt_ddi_buf_trans *
 738 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 739 {
 740         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 741         return bxt_ddi_translations_dp;
 742 }
 743
 744 static const struct bxt_ddi_buf_trans *
 745 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 746 {
 747         if (dev_priv->vbt.edp.low_vswing) {
 748                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 749                 return bxt_ddi_translations_edp;
 750         }
 751
 752         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 753 }
 754
 755 static const struct bxt_ddi_buf_trans *
 756 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 757 {
 758         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 759         return bxt_ddi_translations_hdmi;
 760 }
 761
 762 static const struct cnl_ddi_buf_trans *
 763 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 764 {
 765         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 766
 767         if (voltage == VOLTAGE_INFO_0_85V) {
 768                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 769                 return cnl_ddi_translations_hdmi_0_85V;
 770         } else if (voltage == VOLTAGE_INFO_0_95V) {
 771                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 772                 return cnl_ddi_translations_hdmi_0_95V;
 773         } else if (voltage == VOLTAGE_INFO_1_05V) {
 774                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 775                 return cnl_ddi_translations_hdmi_1_05V;
 776         } else {
 777                 *n_entries = 1; /* shut up gcc */
 778                 MISSING_CASE(voltage);
 779         }
 780         return NULL;
 781 }
 782
 783 static const struct cnl_ddi_buf_trans *
 784 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 785 {
 786         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 787
 788         if (voltage == VOLTAGE_INFO_0_85V) {
 789                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 790                 return cnl_ddi_translations_dp_0_85V;
 791         } else if (voltage == VOLTAGE_INFO_0_95V) {
 792                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 793                 return cnl_ddi_translations_dp_0_95V;
 794         } else if (voltage == VOLTAGE_INFO_1_05V) {
 795                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 796                 return cnl_ddi_translations_dp_1_05V;
 797         } else {
 798                 *n_entries = 1; /* shut up gcc */
 799                 MISSING_CASE(voltage);
 800         }
 801         return NULL;
 802 }
 803
 804 static const struct cnl_ddi_buf_trans *
 805 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 806 {
 807         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 808
 809         if (dev_priv->vbt.edp.low_vswing) {
 810                 if (voltage == VOLTAGE_INFO_0_85V) {
 811                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 812                         return cnl_ddi_translations_edp_0_85V;
 813                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 814                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 815                         return cnl_ddi_translations_edp_0_95V;
 816                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 817                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 818                         return cnl_ddi_translations_edp_1_05V;
 819                 } else {
 820                         *n_entries = 1; /* shut up gcc */
 821                         MISSING_CASE(voltage);
 822                 }
 823                 return NULL;
 824         } else {
 825                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 826         }
 827 }
 828
 829 static const struct cnl_ddi_buf_trans *
 830 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 831                         int type, int rate, int *n_entries)
 832 {
 833         if (type == INTEL_OUTPUT_HDMI) {
 834                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 835                 return icl_combo_phy_ddi_translations_hdmi;
 836         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 837                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 838                 return icl_combo_phy_ddi_translations_edp_hbr3;
 839         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 840                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 841                 return icl_combo_phy_ddi_translations_edp_hbr2;
 842         }
 843
 844         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 845         return icl_combo_phy_ddi_translations_dp_hbr2;
 846 }
 847
 848 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 849 {
 850         int n_entries, level, default_entry;
 851
 852         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 853
 854         if (INTEL_GEN(dev_priv) >= 11) {
 855                 if (intel_port_is_combophy(dev_priv, port))
 856                         icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
 857                                                 0, &n_entries);
 858                 else
 859                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 860                 default_entry = n_entries - 1;
 861         } else if (IS_CANNONLAKE(dev_priv)) {
 862                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 863                 default_entry = n_entries - 1;
 864         } else if (IS_GEN9_LP(dev_priv)) {
 865                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 866                 default_entry = n_entries - 1;
 867         } else if (IS_GEN9_BC(dev_priv)) {
 868                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 869                 default_entry = 8;
 870         } else if (IS_BROADWELL(dev_priv)) {
 871                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 872                 default_entry = 7;
 873         } else if (IS_HASWELL(dev_priv)) {
 874                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 875                 default_entry = 6;
 876         } else {
 877                 WARN(1, "ddi translation table missing\n");
 878                 return 0;
 879         }
 880
 881         /* Choose a good default if VBT is badly populated */
 882         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 883                 level = default_entry;
 884
 885         if (WARN_ON_ONCE(n_entries == 0))
 886                 return 0;
 887         if (WARN_ON_ONCE(level >= n_entries))
 888                 level = n_entries - 1;
 889
 890         return level;
 891 }
 892
 893 /*
 894  * Starting with Haswell, DDI port buffers must be programmed with correct
 895  * values in advance. This function programs the correct values for
 896  * DP/eDP/FDI use cases.
 897  */
 898 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 899                                          const struct intel_crtc_state *crtc_state)
 900 {
 901         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 902         u32 iboost_bit = 0;
 903         int i, n_entries;
 904         enum port port = encoder->port;
 905         const struct ddi_buf_trans *ddi_translations;
 906
 907         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 908                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 909                                                                &n_entries);
 910         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 911                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 912                                                                &n_entries);
 913         else
 914                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 915                                                               &n_entries);
 916
 917         /* If we're boosting the current, set bit 31 of trans1 */
 918         if (IS_GEN9_BC(dev_priv) &&
 919             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 920                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 921
 922         for (i = 0; i < n_entries; i++) {
 923                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 924                            ddi_translations[i].trans1 | iboost_bit);
 925                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 926                            ddi_translations[i].trans2);
 927         }
 928 }
 929
 930 /*
 931  * Starting with Haswell, DDI port buffers must be programmed with correct
 932  * values in advance. This function programs the correct values for
 933  * HDMI/DVI use cases.
 934  */
 935 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 936                                            int level)
 937 {
 938         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 939         u32 iboost_bit = 0;
 940         int n_entries;
 941         enum port port = encoder->port;
 942         const struct ddi_buf_trans *ddi_translations;
 943
 944         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 945
 946         if (WARN_ON_ONCE(!ddi_translations))
 947                 return;
 948         if (WARN_ON_ONCE(level >= n_entries))
 949                 level = n_entries - 1;
 950
 951         /* If we're boosting the current, set bit 31 of trans1 */
 952         if (IS_GEN9_BC(dev_priv) &&
 953             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 954                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 955
 956         /* Entry 9 is for HDMI: */
 957         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 958                    ddi_translations[level].trans1 | iboost_bit);
 959         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 960                    ddi_translations[level].trans2);
 961 }
 962
 963 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 964                                     enum port port)
 965 {
 966         i915_reg_t reg = DDI_BUF_CTL(port);
 967         int i;
 968
 969         for (i = 0; i < 16; i++) {
 970                 udelay(1);
 971                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 972                         return;
 973         }
 974         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 975 }
 976
 977 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 978 {
 979         switch (pll->info->id) {
 980         case DPLL_ID_WRPLL1:
 981                 return PORT_CLK_SEL_WRPLL1;
 982         case DPLL_ID_WRPLL2:
 983                 return PORT_CLK_SEL_WRPLL2;
 984         case DPLL_ID_SPLL:
 985                 return PORT_CLK_SEL_SPLL;
 986         case DPLL_ID_LCPLL_810:
 987                 return PORT_CLK_SEL_LCPLL_810;
 988         case DPLL_ID_LCPLL_1350:
 989                 return PORT_CLK_SEL_LCPLL_1350;
 990         case DPLL_ID_LCPLL_2700:
 991                 return PORT_CLK_SEL_LCPLL_2700;
 992         default:
 993                 MISSING_CASE(pll->info->id);
 994                 return PORT_CLK_SEL_NONE;
 995         }
 996 }
 997
 998 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 999                                   const struct intel_crtc_state *crtc_state)
1000 {
1001         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1002         int clock = crtc_state->port_clock;
1003         const enum intel_dpll_id id = pll->info->id;
1004
1005         switch (id) {
1006         default:
1007                 /*
1008                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1009                  * here, so do warn if this get passed in
1010                  */
1011                 MISSING_CASE(id);
1012                 return DDI_CLK_SEL_NONE;
1013         case DPLL_ID_ICL_TBTPLL:
1014                 switch (clock) {
1015                 case 162000:
1016                         return DDI_CLK_SEL_TBT_162;
1017                 case 270000:
1018                         return DDI_CLK_SEL_TBT_270;
1019                 case 540000:
1020                         return DDI_CLK_SEL_TBT_540;
1021                 case 810000:
1022                         return DDI_CLK_SEL_TBT_810;
1023                 default:
1024                         MISSING_CASE(clock);
1025                         return DDI_CLK_SEL_NONE;
1026                 }
1027         case DPLL_ID_ICL_MGPLL1:
1028         case DPLL_ID_ICL_MGPLL2:
1029         case DPLL_ID_ICL_MGPLL3:
1030         case DPLL_ID_ICL_MGPLL4:
1031                 return DDI_CLK_SEL_MG;
1032         }
1033 }
1034
1035 /* Starting with Haswell, different DDI ports can work in FDI mode for
1036  * connection to the PCH-located connectors. For this, it is necessary to train
1037  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1038  *
1039  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1040  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1041  * DDI A (which is used for eDP)
1042  */
1043
1044 void hsw_fdi_link_train(struct intel_crtc *crtc,
1045                         const struct intel_crtc_state *crtc_state)
1046 {
1047         struct drm_device *dev = crtc->base.dev;
1048         struct drm_i915_private *dev_priv = to_i915(dev);
1049         struct intel_encoder *encoder;
1050         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1051
1052         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1053                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1054                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1055         }
1056
1057         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1058          * mode set "sequence for CRT port" document:
1059          * - TP1 to TP2 time with the default value
1060          * - FDI delay to 90h
1061          *
1062          * WaFDIAutoLinkSetTimingOverrride:hsw
1063          */
1064         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1065                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1066                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1067
1068         /* Enable the PCH Receiver FDI PLL */
1069         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1070                      FDI_RX_PLL_ENABLE |
1071                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1072         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1073         POSTING_READ(FDI_RX_CTL(PIPE_A));
1074         udelay(220);
1075
1076         /* Switch from Rawclk to PCDclk */
1077         rx_ctl_val |= FDI_PCDCLK;
1078         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1079
1080         /* Configure Port Clock Select */
1081         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1082         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1083         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1084
1085         /* Start the training iterating through available voltages and emphasis,
1086          * testing each value twice. */
1087         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1088                 /* Configure DP_TP_CTL with auto-training */
1089                 I915_WRITE(DP_TP_CTL(PORT_E),
1090                                         DP_TP_CTL_FDI_AUTOTRAIN |
1091                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1092                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1093                                         DP_TP_CTL_ENABLE);
1094
1095                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1096                  * DDI E does not support port reversal, the functionality is
1097                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1098                  * port reversal bit */
1099                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1100                            DDI_BUF_CTL_ENABLE |
1101                            ((crtc_state->fdi_lanes - 1) << 1) |
1102                            DDI_BUF_TRANS_SELECT(i / 2));
1103                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1104
1105                 udelay(600);
1106
1107                 /* Program PCH FDI Receiver TU */
1108                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1109
1110                 /* Enable PCH FDI Receiver with auto-training */
1111                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1112                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1113                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1114
1115                 /* Wait for FDI receiver lane calibration */
1116                 udelay(30);
1117
1118                 /* Unset FDI_RX_MISC pwrdn lanes */
1119                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1120                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1121                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1122                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1123
1124                 /* Wait for FDI auto training time */
1125                 udelay(5);
1126
1127                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1128                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1129                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1130                         break;
1131                 }
1132
1133                 /*
1134                  * Leave things enabled even if we failed to train FDI.
1135                  * Results in less fireworks from the state checker.
1136                  */
1137                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1138                         DRM_ERROR("FDI link training failed!\n");
1139                         break;
1140                 }
1141
1142                 rx_ctl_val &= ~FDI_RX_ENABLE;
1143                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1144                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1145
1146                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1147                 temp &= ~DDI_BUF_CTL_ENABLE;
1148                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1149                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1150
1151                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1152                 temp = I915_READ(DP_TP_CTL(PORT_E));
1153                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1154                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1155                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1156                 POSTING_READ(DP_TP_CTL(PORT_E));
1157
1158                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1159
1160                 /* Reset FDI_RX_MISC pwrdn lanes */
1161                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1162                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1163                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1164                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1165                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1166         }
1167
1168         /* Enable normal pixel sending for FDI */
1169         I915_WRITE(DP_TP_CTL(PORT_E),
1170                    DP_TP_CTL_FDI_AUTOTRAIN |
1171                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1172                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1173                    DP_TP_CTL_ENABLE);
1174 }
1175
1176 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1177 {
1178         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1179         struct intel_digital_port *intel_dig_port =
1180                 enc_to_dig_port(&encoder->base);
1181
1182         intel_dp->DP = intel_dig_port->saved_port_bits |
1183                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1184         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1185 }
1186
1187 static struct intel_encoder *
1188 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1189 {
1190         struct drm_device *dev = crtc->base.dev;
1191         struct intel_encoder *encoder, *ret = NULL;
1192         int num_encoders = 0;
1193
1194         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1195                 ret = encoder;
1196                 num_encoders++;
1197         }
1198
1199         if (num_encoders != 1)
1200                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1201                      pipe_name(crtc->pipe));
1202
1203         BUG_ON(ret == NULL);
1204         return ret;
1205 }
1206
1207 #define LC_FREQ 2700
1208
1209 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1210                                    i915_reg_t reg)
1211 {
1212         int refclk = LC_FREQ;
1213         int n, p, r;
1214         u32 wrpll;
1215
1216         wrpll = I915_READ(reg);
1217         switch (wrpll & WRPLL_PLL_REF_MASK) {
1218         case WRPLL_PLL_SSC:
1219         case WRPLL_PLL_NON_SSC:
1220                 /*
1221                  * We could calculate spread here, but our checking
1222                  * code only cares about 5% accuracy, and spread is a max of
1223                  * 0.5% downspread.
1224                  */
1225                 refclk = 135;
1226                 break;
1227         case WRPLL_PLL_LCPLL:
1228                 refclk = LC_FREQ;
1229                 break;
1230         default:
1231                 WARN(1, "bad wrpll refclk\n");
1232                 return 0;
1233         }
1234
1235         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1236         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1237         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1238
1239         /* Convert to KHz, p & r have a fixed point portion */
1240         return (refclk * n * 100) / (p * r);
1241 }
1242
1243 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1244 {
1245         u32 p0, p1, p2, dco_freq;
1246
1247         p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1248         p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1249
1250         if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1251                 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1252         else
1253                 p1 = 1;
1254
1255
1256         switch (p0) {
1257         case DPLL_CFGCR2_PDIV_1:
1258                 p0 = 1;
1259                 break;
1260         case DPLL_CFGCR2_PDIV_2:
1261                 p0 = 2;
1262                 break;
1263         case DPLL_CFGCR2_PDIV_3:
1264                 p0 = 3;
1265                 break;
1266         case DPLL_CFGCR2_PDIV_7:
1267                 p0 = 7;
1268                 break;
1269         }
1270
1271         switch (p2) {
1272         case DPLL_CFGCR2_KDIV_5:
1273                 p2 = 5;
1274                 break;
1275         case DPLL_CFGCR2_KDIV_2:
1276                 p2 = 2;
1277                 break;
1278         case DPLL_CFGCR2_KDIV_3:
1279                 p2 = 3;
1280                 break;
1281         case DPLL_CFGCR2_KDIV_1:
1282                 p2 = 1;
1283                 break;
1284         }
1285
1286         dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1287                 * 24 * 1000;
1288
1289         dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1290                      * 24 * 1000) / 0x8000;
1291
1292         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1293                 return 0;
1294
1295         return dco_freq / (p0 * p1 * p2 * 5);
1296 }
1297
1298 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1299                         struct intel_dpll_hw_state *pll_state)
1300 {
1301         u32 p0, p1, p2, dco_freq, ref_clock;
1302
1303         p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1304         p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1305
1306         if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1307                 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1308                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1309         else
1310                 p1 = 1;
1311
1312
1313         switch (p0) {
1314         case DPLL_CFGCR1_PDIV_2:
1315                 p0 = 2;
1316                 break;
1317         case DPLL_CFGCR1_PDIV_3:
1318                 p0 = 3;
1319                 break;
1320         case DPLL_CFGCR1_PDIV_5:
1321                 p0 = 5;
1322                 break;
1323         case DPLL_CFGCR1_PDIV_7:
1324                 p0 = 7;
1325                 break;
1326         }
1327
1328         switch (p2) {
1329         case DPLL_CFGCR1_KDIV_1:
1330                 p2 = 1;
1331                 break;
1332         case DPLL_CFGCR1_KDIV_2:
1333                 p2 = 2;
1334                 break;
1335         case DPLL_CFGCR1_KDIV_3:
1336                 p2 = 3;
1337                 break;
1338         }
1339
1340         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1341
1342         dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1343                 * ref_clock;
1344
1345         dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1346                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1347
1348         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1349                 return 0;
1350
1351         return dco_freq / (p0 * p1 * p2 * 5);
1352 }
1353
1354 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1355                                  enum port port)
1356 {
1357         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1358
1359         switch (val) {
1360         case DDI_CLK_SEL_NONE:
1361                 return 0;
1362         case DDI_CLK_SEL_TBT_162:
1363                 return 162000;
1364         case DDI_CLK_SEL_TBT_270:
1365                 return 270000;
1366         case DDI_CLK_SEL_TBT_540:
1367                 return 540000;
1368         case DDI_CLK_SEL_TBT_810:
1369                 return 810000;
1370         default:
1371                 MISSING_CASE(val);
1372                 return 0;
1373         }
1374 }
1375
1376 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1377                                 const struct intel_dpll_hw_state *pll_state)
1378 {
1379         u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1380         u64 tmp;
1381
1382         ref_clock = dev_priv->cdclk.hw.ref;
1383
1384         m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1385         m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1386         m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1387                 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1388                 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1389
1390         switch (pll_state->mg_clktop2_hsclkctl &
1391                 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1392         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1393                 div1 = 2;
1394                 break;
1395         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1396                 div1 = 3;
1397                 break;
1398         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1399                 div1 = 5;
1400                 break;
1401         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1402                 div1 = 7;
1403                 break;
1404         default:
1405                 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1406                 return 0;
1407         }
1408
1409         div2 = (pll_state->mg_clktop2_hsclkctl &
1410                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1411                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1412
1413         /* div2 value of 0 is same as 1 means no div */
1414         if (div2 == 0)
1415                 div2 = 1;
1416
1417         /*
1418          * Adjust the original formula to delay the division by 2^22 in order to
1419          * minimize possible rounding errors.
1420          */
1421         tmp = (u64)m1 * m2_int * ref_clock +
1422               (((u64)m1 * m2_frac * ref_clock) >> 22);
1423         tmp = div_u64(tmp, 5 * div1 * div2);
1424
1425         return tmp;
1426 }
1427
1428 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1429 {
1430         int dotclock;
1431
1432         if (pipe_config->has_pch_encoder)
1433                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1434                                                     &pipe_config->fdi_m_n);
1435         else if (intel_crtc_has_dp_encoder(pipe_config))
1436                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1437                                                     &pipe_config->dp_m_n);
1438         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1439                 dotclock = pipe_config->port_clock * 2 / 3;
1440         else
1441                 dotclock = pipe_config->port_clock;
1442
1443         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1444                 dotclock *= 2;
1445
1446         if (pipe_config->pixel_multiplier)
1447                 dotclock /= pipe_config->pixel_multiplier;
1448
1449         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1450 }
1451
1452 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1453                               struct intel_crtc_state *pipe_config)
1454 {
1455         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1456         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1457         enum port port = encoder->port;
1458         int link_clock;
1459
1460         if (intel_port_is_combophy(dev_priv, port)) {
1461                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1462         } else {
1463                 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1464                                                 pipe_config->shared_dpll);
1465
1466                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1467                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1468                 else
1469                         link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1470         }
1471
1472         pipe_config->port_clock = link_clock;
1473
1474         ddi_dotclock_get(pipe_config);
1475 }
1476
1477 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1478                               struct intel_crtc_state *pipe_config)
1479 {
1480         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1481         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1482         int link_clock;
1483
1484         if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1485                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1486         } else {
1487                 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1488
1489                 switch (link_clock) {
1490                 case DPLL_CFGCR0_LINK_RATE_810:
1491                         link_clock = 81000;
1492                         break;
1493                 case DPLL_CFGCR0_LINK_RATE_1080:
1494                         link_clock = 108000;
1495                         break;
1496                 case DPLL_CFGCR0_LINK_RATE_1350:
1497                         link_clock = 135000;
1498                         break;
1499                 case DPLL_CFGCR0_LINK_RATE_1620:
1500                         link_clock = 162000;
1501                         break;
1502                 case DPLL_CFGCR0_LINK_RATE_2160:
1503                         link_clock = 216000;
1504                         break;
1505                 case DPLL_CFGCR0_LINK_RATE_2700:
1506                         link_clock = 270000;
1507                         break;
1508                 case DPLL_CFGCR0_LINK_RATE_3240:
1509                         link_clock = 324000;
1510                         break;
1511                 case DPLL_CFGCR0_LINK_RATE_4050:
1512                         link_clock = 405000;
1513                         break;
1514                 default:
1515                         WARN(1, "Unsupported link rate\n");
1516                         break;
1517                 }
1518                 link_clock *= 2;
1519         }
1520
1521         pipe_config->port_clock = link_clock;
1522
1523         ddi_dotclock_get(pipe_config);
1524 }
1525
1526 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1527                               struct intel_crtc_state *pipe_config)
1528 {
1529         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1530         int link_clock;
1531
1532         /*
1533          * ctrl1 register is already shifted for each pll, just use 0 to get
1534          * the internal shift for each field
1535          */
1536         if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1537                 link_clock = skl_calc_wrpll_link(pll_state);
1538         } else {
1539                 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1540                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1541
1542                 switch (link_clock) {
1543                 case DPLL_CTRL1_LINK_RATE_810:
1544                         link_clock = 81000;
1545                         break;
1546                 case DPLL_CTRL1_LINK_RATE_1080:
1547                         link_clock = 108000;
1548                         break;
1549                 case DPLL_CTRL1_LINK_RATE_1350:
1550                         link_clock = 135000;
1551                         break;
1552                 case DPLL_CTRL1_LINK_RATE_1620:
1553                         link_clock = 162000;
1554                         break;
1555                 case DPLL_CTRL1_LINK_RATE_2160:
1556                         link_clock = 216000;
1557                         break;
1558                 case DPLL_CTRL1_LINK_RATE_2700:
1559                         link_clock = 270000;
1560                         break;
1561                 default:
1562                         WARN(1, "Unsupported link rate\n");
1563                         break;
1564                 }
1565                 link_clock *= 2;
1566         }
1567
1568         pipe_config->port_clock = link_clock;
1569
1570         ddi_dotclock_get(pipe_config);
1571 }
1572
1573 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1574                               struct intel_crtc_state *pipe_config)
1575 {
1576         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1577         int link_clock = 0;
1578         u32 val, pll;
1579
1580         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1581         switch (val & PORT_CLK_SEL_MASK) {
1582         case PORT_CLK_SEL_LCPLL_810:
1583                 link_clock = 81000;
1584                 break;
1585         case PORT_CLK_SEL_LCPLL_1350:
1586                 link_clock = 135000;
1587                 break;
1588         case PORT_CLK_SEL_LCPLL_2700:
1589                 link_clock = 270000;
1590                 break;
1591         case PORT_CLK_SEL_WRPLL1:
1592                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1593                 break;
1594         case PORT_CLK_SEL_WRPLL2:
1595                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1596                 break;
1597         case PORT_CLK_SEL_SPLL:
1598                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1599                 if (pll == SPLL_PLL_FREQ_810MHz)
1600                         link_clock = 81000;
1601                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1602                         link_clock = 135000;
1603                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1604                         link_clock = 270000;
1605                 else {
1606                         WARN(1, "bad spll freq\n");
1607                         return;
1608                 }
1609                 break;
1610         default:
1611                 WARN(1, "bad port clock sel\n");
1612                 return;
1613         }
1614
1615         pipe_config->port_clock = link_clock * 2;
1616
1617         ddi_dotclock_get(pipe_config);
1618 }
1619
1620 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1621 {
1622         struct dpll clock;
1623
1624         clock.m1 = 2;
1625         clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1626         if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1627                 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1628         clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1629         clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1630         clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1631
1632         return chv_calc_dpll_params(100000, &clock);
1633 }
1634
1635 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1636                               struct intel_crtc_state *pipe_config)
1637 {
1638         pipe_config->port_clock =
1639                 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1640
1641         ddi_dotclock_get(pipe_config);
1642 }
1643
1644 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1645                                 struct intel_crtc_state *pipe_config)
1646 {
1647         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1648
1649         if (INTEL_GEN(dev_priv) >= 11)
1650                 icl_ddi_clock_get(encoder, pipe_config);
1651         else if (IS_CANNONLAKE(dev_priv))
1652                 cnl_ddi_clock_get(encoder, pipe_config);
1653         else if (IS_GEN9_LP(dev_priv))
1654                 bxt_ddi_clock_get(encoder, pipe_config);
1655         else if (IS_GEN9_BC(dev_priv))
1656                 skl_ddi_clock_get(encoder, pipe_config);
1657         else if (INTEL_GEN(dev_priv) <= 8)
1658                 hsw_ddi_clock_get(encoder, pipe_config);
1659 }
1660
1661 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1662 {
1663         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1664         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1665         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1666         u32 temp;
1667
1668         if (!intel_crtc_has_dp_encoder(crtc_state))
1669                 return;
1670
1671         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1672
1673         temp = TRANS_MSA_SYNC_CLK;
1674
1675         if (crtc_state->limited_color_range)
1676                 temp |= TRANS_MSA_CEA_RANGE;
1677
1678         switch (crtc_state->pipe_bpp) {
1679         case 18:
1680                 temp |= TRANS_MSA_6_BPC;
1681                 break;
1682         case 24:
1683                 temp |= TRANS_MSA_8_BPC;
1684                 break;
1685         case 30:
1686                 temp |= TRANS_MSA_10_BPC;
1687                 break;
1688         case 36:
1689                 temp |= TRANS_MSA_12_BPC;
1690                 break;
1691         default:
1692                 MISSING_CASE(crtc_state->pipe_bpp);
1693                 break;
1694         }
1695
1696         /*
1697          * As per DP 1.2 spec section 2.3.4.3 while sending
1698          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1699          * colorspace information. The output colorspace encoding is BT601.
1700          */
1701         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1702                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1703         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1704 }
1705
1706 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1707                                     bool state)
1708 {
1709         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1710         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1711         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1712         u32 temp;
1713
1714         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1715         if (state == true)
1716                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1717         else
1718                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1719         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1720 }
1721
1722 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1723 {
1724         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1725         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1726         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1727         enum pipe pipe = crtc->pipe;
1728         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1729         enum port port = encoder->port;
1730         u32 temp;
1731
1732         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1733         temp = TRANS_DDI_FUNC_ENABLE;
1734         temp |= TRANS_DDI_SELECT_PORT(port);
1735
1736         switch (crtc_state->pipe_bpp) {
1737         case 18:
1738                 temp |= TRANS_DDI_BPC_6;
1739                 break;
1740         case 24:
1741                 temp |= TRANS_DDI_BPC_8;
1742                 break;
1743         case 30:
1744                 temp |= TRANS_DDI_BPC_10;
1745                 break;
1746         case 36:
1747                 temp |= TRANS_DDI_BPC_12;
1748                 break;
1749         default:
1750                 BUG();
1751         }
1752
1753         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1754                 temp |= TRANS_DDI_PVSYNC;
1755         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1756                 temp |= TRANS_DDI_PHSYNC;
1757
1758         if (cpu_transcoder == TRANSCODER_EDP) {
1759                 switch (pipe) {
1760                 case PIPE_A:
1761                         /* On Haswell, can only use the always-on power well for
1762                          * eDP when not using the panel fitter, and when not
1763                          * using motion blur mitigation (which we don't
1764                          * support). */
1765                         if (IS_HASWELL(dev_priv) &&
1766                             (crtc_state->pch_pfit.enabled ||
1767                              crtc_state->pch_pfit.force_thru))
1768                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1769                         else
1770                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1771                         break;
1772                 case PIPE_B:
1773                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1774                         break;
1775                 case PIPE_C:
1776                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1777                         break;
1778                 default:
1779                         BUG();
1780                         break;
1781                 }
1782         }
1783
1784         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1785                 if (crtc_state->has_hdmi_sink)
1786                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1787                 else
1788                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1789
1790                 if (crtc_state->hdmi_scrambling)
1791                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1792                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1793                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1794         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1795                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1796                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1797         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1798                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1799                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1800         } else {
1801                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1802                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1803         }
1804
1805         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1806 }
1807
1808 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1809 {
1810         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1811         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1812         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1813         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1814         u32 val = I915_READ(reg);
1815
1816         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1817         val |= TRANS_DDI_PORT_NONE;
1818         I915_WRITE(reg, val);
1819
1820         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1821             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1822                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1823                 /* Quirk time at 100ms for reliable operation */
1824                 msleep(100);
1825         }
1826 }
1827
1828 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1829                                      bool enable)
1830 {
1831         struct drm_device *dev = intel_encoder->base.dev;
1832         struct drm_i915_private *dev_priv = to_i915(dev);
1833         intel_wakeref_t wakeref;
1834         enum pipe pipe = 0;
1835         int ret = 0;
1836         u32 tmp;
1837
1838         wakeref = intel_display_power_get_if_enabled(dev_priv,
1839                                                      intel_encoder->power_domain);
1840         if (WARN_ON(!wakeref))
1841                 return -ENXIO;
1842
1843         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1844                 ret = -EIO;
1845                 goto out;
1846         }
1847
1848         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1849         if (enable)
1850                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1851         else
1852                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1853         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1854 out:
1855         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1856         return ret;
1857 }
1858
1859 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1860 {
1861         struct drm_device *dev = intel_connector->base.dev;
1862         struct drm_i915_private *dev_priv = to_i915(dev);
1863         struct intel_encoder *encoder = intel_connector->encoder;
1864         int type = intel_connector->base.connector_type;
1865         enum port port = encoder->port;
1866         enum transcoder cpu_transcoder;
1867         intel_wakeref_t wakeref;
1868         enum pipe pipe = 0;
1869         u32 tmp;
1870         bool ret;
1871
1872         wakeref = intel_display_power_get_if_enabled(dev_priv,
1873                                                      encoder->power_domain);
1874         if (!wakeref)
1875                 return false;
1876
1877         if (!encoder->get_hw_state(encoder, &pipe)) {
1878                 ret = false;
1879                 goto out;
1880         }
1881
1882         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
1883                 cpu_transcoder = TRANSCODER_EDP;
1884         else
1885                 cpu_transcoder = (enum transcoder) pipe;
1886
1887         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1888
1889         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1890         case TRANS_DDI_MODE_SELECT_HDMI:
1891         case TRANS_DDI_MODE_SELECT_DVI:
1892                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1893                 break;
1894
1895         case TRANS_DDI_MODE_SELECT_DP_SST:
1896                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1897                       type == DRM_MODE_CONNECTOR_DisplayPort;
1898                 break;
1899
1900         case TRANS_DDI_MODE_SELECT_DP_MST:
1901                 /* if the transcoder is in MST state then
1902                  * connector isn't connected */
1903                 ret = false;
1904                 break;
1905
1906         case TRANS_DDI_MODE_SELECT_FDI:
1907                 ret = type == DRM_MODE_CONNECTOR_VGA;
1908                 break;
1909
1910         default:
1911                 ret = false;
1912                 break;
1913         }
1914
1915 out:
1916         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1917
1918         return ret;
1919 }
1920
1921 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1922                                         u8 *pipe_mask, bool *is_dp_mst)
1923 {
1924         struct drm_device *dev = encoder->base.dev;
1925         struct drm_i915_private *dev_priv = to_i915(dev);
1926         enum port port = encoder->port;
1927         intel_wakeref_t wakeref;
1928         enum pipe p;
1929         u32 tmp;
1930         u8 mst_pipe_mask;
1931
1932         *pipe_mask = 0;
1933         *is_dp_mst = false;
1934
1935         wakeref = intel_display_power_get_if_enabled(dev_priv,
1936                                                      encoder->power_domain);
1937         if (!wakeref)
1938                 return;
1939
1940         tmp = I915_READ(DDI_BUF_CTL(port));
1941         if (!(tmp & DDI_BUF_CTL_ENABLE))
1942                 goto out;
1943
1944         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
1945                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1946
1947                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1948                 default:
1949                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1950                         /* fallthrough */
1951                 case TRANS_DDI_EDP_INPUT_A_ON:
1952                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1953                         *pipe_mask = BIT(PIPE_A);
1954                         break;
1955                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1956                         *pipe_mask = BIT(PIPE_B);
1957                         break;
1958                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1959                         *pipe_mask = BIT(PIPE_C);
1960                         break;
1961                 }
1962
1963                 goto out;
1964         }
1965
1966         mst_pipe_mask = 0;
1967         for_each_pipe(dev_priv, p) {
1968                 enum transcoder cpu_transcoder = (enum transcoder)p;
1969
1970                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1971
1972                 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
1973                         continue;
1974
1975                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1976                     TRANS_DDI_MODE_SELECT_DP_MST)
1977                         mst_pipe_mask |= BIT(p);
1978
1979                 *pipe_mask |= BIT(p);
1980         }
1981
1982         if (!*pipe_mask)
1983                 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
1984                               port_name(port));
1985
1986         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
1987                 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
1988                               port_name(port), *pipe_mask);
1989                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
1990         }
1991
1992         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
1993                 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
1994                               port_name(port), *pipe_mask, mst_pipe_mask);
1995         else
1996                 *is_dp_mst = mst_pipe_mask;
1997
1998 out:
1999         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2000                 tmp = I915_READ(BXT_PHY_CTL(port));
2001                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2002                             BXT_PHY_LANE_POWERDOWN_ACK |
2003                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2004                         DRM_ERROR("Port %c enabled but PHY powered down? "
2005                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
2006         }
2007
2008         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2009 }
2010
2011 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2012                             enum pipe *pipe)
2013 {
2014         u8 pipe_mask;
2015         bool is_mst;
2016
2017         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2018
2019         if (is_mst || !pipe_mask)
2020                 return false;
2021
2022         *pipe = ffs(pipe_mask) - 1;
2023
2024         return true;
2025 }
2026
2027 static inline enum intel_display_power_domain
2028 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2029 {
2030         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2031          * DC states enabled at the same time, while for driver initiated AUX
2032          * transfers we need the same AUX IOs to be powered but with DC states
2033          * disabled. Accordingly use the AUX power domain here which leaves DC
2034          * states enabled.
2035          * However, for non-A AUX ports the corresponding non-EDP transcoders
2036          * would have already enabled power well 2 and DC_OFF. This means we can
2037          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2038          * specific AUX_IO reference without powering up any extra wells.
2039          * Note that PSR is enabled only on Port A even though this function
2040          * returns the correct domain for other ports too.
2041          */
2042         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2043                                               intel_aux_power_domain(dig_port);
2044 }
2045
2046 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2047                                        struct intel_crtc_state *crtc_state)
2048 {
2049         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2050         struct intel_digital_port *dig_port;
2051         u64 domains;
2052
2053         /*
2054          * TODO: Add support for MST encoders. Atm, the following should never
2055          * happen since fake-MST encoders don't set their get_power_domains()
2056          * hook.
2057          */
2058         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2059                 return 0;
2060
2061         dig_port = enc_to_dig_port(&encoder->base);
2062         domains = BIT_ULL(dig_port->ddi_io_power_domain);
2063
2064         /*
2065          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2066          * ports.
2067          */
2068         if (intel_crtc_has_dp_encoder(crtc_state) ||
2069             intel_port_is_tc(dev_priv, encoder->port))
2070                 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
2071
2072         /*
2073          * VDSC power is needed when DSC is enabled
2074          */
2075         if (crtc_state->dsc_params.compression_enable)
2076                 domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
2077
2078         return domains;
2079 }
2080
2081 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2082 {
2083         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2084         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2085         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2086         enum port port = encoder->port;
2087         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2088
2089         if (cpu_transcoder != TRANSCODER_EDP)
2090                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2091                            TRANS_CLK_SEL_PORT(port));
2092 }
2093
2094 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2095 {
2096         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2097         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2098
2099         if (cpu_transcoder != TRANSCODER_EDP)
2100                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2101                            TRANS_CLK_SEL_DISABLED);
2102 }
2103
2104 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2105                                 enum port port, u8 iboost)
2106 {
2107         u32 tmp;
2108
2109         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2110         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2111         if (iboost)
2112                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2113         else
2114                 tmp |= BALANCE_LEG_DISABLE(port);
2115         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2116 }
2117
2118 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2119                                int level, enum intel_output_type type)
2120 {
2121         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2122         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2123         enum port port = encoder->port;
2124         u8 iboost;
2125
2126         if (type == INTEL_OUTPUT_HDMI)
2127                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2128         else
2129                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2130
2131         if (iboost == 0) {
2132                 const struct ddi_buf_trans *ddi_translations;
2133                 int n_entries;
2134
2135                 if (type == INTEL_OUTPUT_HDMI)
2136                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2137                 else if (type == INTEL_OUTPUT_EDP)
2138                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2139                 else
2140                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2141
2142                 if (WARN_ON_ONCE(!ddi_translations))
2143                         return;
2144                 if (WARN_ON_ONCE(level >= n_entries))
2145                         level = n_entries - 1;
2146
2147                 iboost = ddi_translations[level].i_boost;
2148         }
2149
2150         /* Make sure that the requested I_boost is valid */
2151         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2152                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2153                 return;
2154         }
2155
2156         _skl_ddi_set_iboost(dev_priv, port, iboost);
2157
2158         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2159                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2160 }
2161
2162 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2163                                     int level, enum intel_output_type type)
2164 {
2165         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2166         const struct bxt_ddi_buf_trans *ddi_translations;
2167         enum port port = encoder->port;
2168         int n_entries;
2169
2170         if (type == INTEL_OUTPUT_HDMI)
2171                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2172         else if (type == INTEL_OUTPUT_EDP)
2173                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2174         else
2175                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2176
2177         if (WARN_ON_ONCE(!ddi_translations))
2178                 return;
2179         if (WARN_ON_ONCE(level >= n_entries))
2180                 level = n_entries - 1;
2181
2182         bxt_ddi_phy_set_signal_level(dev_priv, port,
2183                                      ddi_translations[level].margin,
2184                                      ddi_translations[level].scale,
2185                                      ddi_translations[level].enable,
2186                                      ddi_translations[level].deemphasis);
2187 }
2188
2189 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2190 {
2191         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2192         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2193         enum port port = encoder->port;
2194         int n_entries;
2195
2196         if (INTEL_GEN(dev_priv) >= 11) {
2197                 if (intel_port_is_combophy(dev_priv, port))
2198                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2199                                                 intel_dp->link_rate, &n_entries);
2200                 else
2201                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2202         } else if (IS_CANNONLAKE(dev_priv)) {
2203                 if (encoder->type == INTEL_OUTPUT_EDP)
2204                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2205                 else
2206                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2207         } else if (IS_GEN9_LP(dev_priv)) {
2208                 if (encoder->type == INTEL_OUTPUT_EDP)
2209                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2210                 else
2211                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2212         } else {
2213                 if (encoder->type == INTEL_OUTPUT_EDP)
2214                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2215                 else
2216                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2217         }
2218
2219         if (WARN_ON(n_entries < 1))
2220                 n_entries = 1;
2221         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2222                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2223
2224         return index_to_dp_signal_levels[n_entries - 1] &
2225                 DP_TRAIN_VOLTAGE_SWING_MASK;
2226 }
2227
2228 /*
2229  * We assume that the full set of pre-emphasis values can be
2230  * used on all DDI platforms. Should that change we need to
2231  * rethink this code.
2232  */
2233 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2234 {
2235         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2236         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2237                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2238         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2239                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2240         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2241                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2242         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2243         default:
2244                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2245         }
2246 }
2247
2248 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2249                                    int level, enum intel_output_type type)
2250 {
2251         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2252         const struct cnl_ddi_buf_trans *ddi_translations;
2253         enum port port = encoder->port;
2254         int n_entries, ln;
2255         u32 val;
2256
2257         if (type == INTEL_OUTPUT_HDMI)
2258                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2259         else if (type == INTEL_OUTPUT_EDP)
2260                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2261         else
2262                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2263
2264         if (WARN_ON_ONCE(!ddi_translations))
2265                 return;
2266         if (WARN_ON_ONCE(level >= n_entries))
2267                 level = n_entries - 1;
2268
2269         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2270         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2271         val &= ~SCALING_MODE_SEL_MASK;
2272         val |= SCALING_MODE_SEL(2);
2273         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2274
2275         /* Program PORT_TX_DW2 */
2276         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2277         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2278                  RCOMP_SCALAR_MASK);
2279         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2280         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2281         /* Rcomp scalar is fixed as 0x98 for every table entry */
2282         val |= RCOMP_SCALAR(0x98);
2283         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2284
2285         /* Program PORT_TX_DW4 */
2286         /* We cannot write to GRP. It would overrite individual loadgen */
2287         for (ln = 0; ln < 4; ln++) {
2288                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2289                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2290                          CURSOR_COEFF_MASK);
2291                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2292                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2293                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2294                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2295         }
2296
2297         /* Program PORT_TX_DW5 */
2298         /* All DW5 values are fixed for every table entry */
2299         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2300         val &= ~RTERM_SELECT_MASK;
2301         val |= RTERM_SELECT(6);
2302         val |= TAP3_DISABLE;
2303         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2304
2305         /* Program PORT_TX_DW7 */
2306         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2307         val &= ~N_SCALAR_MASK;
2308         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2309         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2310 }
2311
2312 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2313                                     int level, enum intel_output_type type)
2314 {
2315         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2316         enum port port = encoder->port;
2317         int width, rate, ln;
2318         u32 val;
2319
2320         if (type == INTEL_OUTPUT_HDMI) {
2321                 width = 4;
2322                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2323         } else {
2324                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2325
2326                 width = intel_dp->lane_count;
2327                 rate = intel_dp->link_rate;
2328         }
2329
2330         /*
2331          * 1. If port type is eDP or DP,
2332          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2333          * else clear to 0b.
2334          */
2335         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2336         if (type != INTEL_OUTPUT_HDMI)
2337                 val |= COMMON_KEEPER_EN;
2338         else
2339                 val &= ~COMMON_KEEPER_EN;
2340         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2341
2342         /* 2. Program loadgen select */
2343         /*
2344          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2345          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2346          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2347          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2348          */
2349         for (ln = 0; ln <= 3; ln++) {
2350                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2351                 val &= ~LOADGEN_SELECT;
2352
2353                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2354                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2355                         val |= LOADGEN_SELECT;
2356                 }
2357                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2358         }
2359
2360         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2361         val = I915_READ(CNL_PORT_CL1CM_DW5);
2362         val |= SUS_CLOCK_CONFIG;
2363         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2364
2365         /* 4. Clear training enable to change swing values */
2366         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2367         val &= ~TX_TRAINING_EN;
2368         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2369
2370         /* 5. Program swing and de-emphasis */
2371         cnl_ddi_vswing_program(encoder, level, type);
2372
2373         /* 6. Set training enable to trigger update */
2374         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2375         val |= TX_TRAINING_EN;
2376         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2377 }
2378
2379 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2380                                         u32 level, enum port port, int type,
2381                                         int rate)
2382 {
2383         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2384         u32 n_entries, val;
2385         int ln;
2386
2387         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2388                                                    rate, &n_entries);
2389         if (!ddi_translations)
2390                 return;
2391
2392         if (level >= n_entries) {
2393                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2394                 level = n_entries - 1;
2395         }
2396
2397         /* Set PORT_TX_DW5 */
2398         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2399         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2400                   TAP2_DISABLE | TAP3_DISABLE);
2401         val |= SCALING_MODE_SEL(0x2);
2402         val |= RTERM_SELECT(0x6);
2403         val |= TAP3_DISABLE;
2404         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2405
2406         /* Program PORT_TX_DW2 */
2407         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2408         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2409                  RCOMP_SCALAR_MASK);
2410         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2411         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2412         /* Program Rcomp scalar for every table entry */
2413         val |= RCOMP_SCALAR(0x98);
2414         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2415
2416         /* Program PORT_TX_DW4 */
2417         /* We cannot write to GRP. It would overwrite individual loadgen. */
2418         for (ln = 0; ln <= 3; ln++) {
2419                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
2420                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2421                          CURSOR_COEFF_MASK);
2422                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2423                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2424                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2425                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
2426         }
2427
2428         /* Program PORT_TX_DW7 */
2429         val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2430         val &= ~N_SCALAR_MASK;
2431         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2432         I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
2433 }
2434
2435 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2436                                               u32 level,
2437                                               enum intel_output_type type)
2438 {
2439         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2440         enum port port = encoder->port;
2441         int width = 0;
2442         int rate = 0;
2443         u32 val;
2444         int ln = 0;
2445
2446         if (type == INTEL_OUTPUT_HDMI) {
2447                 width = 4;
2448                 /* Rate is always < than 6GHz for HDMI */
2449         } else {
2450                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2451
2452                 width = intel_dp->lane_count;
2453                 rate = intel_dp->link_rate;
2454         }
2455
2456         /*
2457          * 1. If port type is eDP or DP,
2458          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2459          * else clear to 0b.
2460          */
2461         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2462         if (type == INTEL_OUTPUT_HDMI)
2463                 val &= ~COMMON_KEEPER_EN;
2464         else
2465                 val |= COMMON_KEEPER_EN;
2466         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2467
2468         /* 2. Program loadgen select */
2469         /*
2470          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2471          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2472          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2473          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2474          */
2475         for (ln = 0; ln <= 3; ln++) {
2476                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
2477                 val &= ~LOADGEN_SELECT;
2478
2479                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2480                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2481                         val |= LOADGEN_SELECT;
2482                 }
2483                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
2484         }
2485
2486         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2487         val = I915_READ(ICL_PORT_CL_DW5(port));
2488         val |= SUS_CLOCK_CONFIG;
2489         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2490
2491         /* 4. Clear training enable to change swing values */
2492         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2493         val &= ~TX_TRAINING_EN;
2494         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2495
2496         /* 5. Program swing and de-emphasis */
2497         icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
2498
2499         /* 6. Set training enable to trigger update */
2500         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2501         val |= TX_TRAINING_EN;
2502         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2503 }
2504
2505 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2506                                            int link_clock,
2507                                            u32 level)
2508 {
2509         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2510         enum port port = encoder->port;
2511         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2512         u32 n_entries, val;
2513         int ln;
2514
2515         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2516         ddi_translations = icl_mg_phy_ddi_translations;
2517         /* The table does not have values for level 3 and level 9. */
2518         if (level >= n_entries || level == 3 || level == 9) {
2519                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2520                               level, n_entries - 2);
2521                 level = n_entries - 2;
2522         }
2523
2524         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2525         for (ln = 0; ln < 2; ln++) {
2526                 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
2527                 val &= ~CRI_USE_FS32;
2528                 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
2529
2530                 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
2531                 val &= ~CRI_USE_FS32;
2532                 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
2533         }
2534
2535         /* Program MG_TX_SWINGCTRL with values from vswing table */
2536         for (ln = 0; ln < 2; ln++) {
2537                 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
2538                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2539                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2540                         ddi_translations[level].cri_txdeemph_override_17_12);
2541                 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
2542
2543                 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
2544                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2545                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2546                         ddi_translations[level].cri_txdeemph_override_17_12);
2547                 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
2548         }
2549
2550         /* Program MG_TX_DRVCTRL with values from vswing table */
2551         for (ln = 0; ln < 2; ln++) {
2552                 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
2553                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2554                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2555                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2556                         ddi_translations[level].cri_txdeemph_override_5_0) |
2557                         CRI_TXDEEMPH_OVERRIDE_11_6(
2558                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2559                         CRI_TXDEEMPH_OVERRIDE_EN;
2560                 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
2561
2562                 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
2563                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2564                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2565                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2566                         ddi_translations[level].cri_txdeemph_override_5_0) |
2567                         CRI_TXDEEMPH_OVERRIDE_11_6(
2568                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2569                         CRI_TXDEEMPH_OVERRIDE_EN;
2570                 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
2571
2572                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2573         }
2574
2575         /*
2576          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2577          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2578          * values from table for which TX1 and TX2 enabled.
2579          */
2580         for (ln = 0; ln < 2; ln++) {
2581                 val = I915_READ(MG_CLKHUB(ln, port));
2582                 if (link_clock < 300000)
2583                         val |= CFG_LOW_RATE_LKREN_EN;
2584                 else
2585                         val &= ~CFG_LOW_RATE_LKREN_EN;
2586                 I915_WRITE(MG_CLKHUB(ln, port), val);
2587         }
2588
2589         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2590         for (ln = 0; ln < 2; ln++) {
2591                 val = I915_READ(MG_TX1_DCC(ln, port));
2592                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2593                 if (link_clock <= 500000) {
2594                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2595                 } else {
2596                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2597                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2598                 }
2599                 I915_WRITE(MG_TX1_DCC(ln, port), val);
2600
2601                 val = I915_READ(MG_TX2_DCC(ln, port));
2602                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2603                 if (link_clock <= 500000) {
2604                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2605                 } else {
2606                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2607                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2608                 }
2609                 I915_WRITE(MG_TX2_DCC(ln, port), val);
2610         }
2611
2612         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2613         for (ln = 0; ln < 2; ln++) {
2614                 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
2615                 val |= CRI_CALCINIT;
2616                 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
2617
2618                 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
2619                 val |= CRI_CALCINIT;
2620                 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
2621         }
2622 }
2623
2624 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2625                                     int link_clock,
2626                                     u32 level,
2627                                     enum intel_output_type type)
2628 {
2629         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2630         enum port port = encoder->port;
2631
2632         if (intel_port_is_combophy(dev_priv, port))
2633                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2634         else
2635                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2636 }
2637
2638 static u32 translate_signal_level(int signal_levels)
2639 {
2640         int i;
2641
2642         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2643                 if (index_to_dp_signal_levels[i] == signal_levels)
2644                         return i;
2645         }
2646
2647         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2648              signal_levels);
2649
2650         return 0;
2651 }
2652
2653 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2654 {
2655         u8 train_set = intel_dp->train_set[0];
2656         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2657                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2658
2659         return translate_signal_level(signal_levels);
2660 }
2661
2662 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2663 {
2664         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2665         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2666         struct intel_encoder *encoder = &dport->base;
2667         int level = intel_ddi_dp_level(intel_dp);
2668
2669         if (INTEL_GEN(dev_priv) >= 11)
2670                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2671                                         level, encoder->type);
2672         else if (IS_CANNONLAKE(dev_priv))
2673                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2674         else
2675                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2676
2677         return 0;
2678 }
2679
2680 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2681 {
2682         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2683         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2684         struct intel_encoder *encoder = &dport->base;
2685         int level = intel_ddi_dp_level(intel_dp);
2686
2687         if (IS_GEN9_BC(dev_priv))
2688                 skl_ddi_set_iboost(encoder, level, encoder->type);
2689
2690         return DDI_BUF_TRANS_SELECT(level);
2691 }
2692
2693 static inline
2694 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2695                               enum port port)
2696 {
2697         if (intel_port_is_combophy(dev_priv, port)) {
2698                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2699         } else if (intel_port_is_tc(dev_priv, port)) {
2700                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2701
2702                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2703         }
2704
2705         return 0;
2706 }
2707
2708 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2709                                   const struct intel_crtc_state *crtc_state)
2710 {
2711         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2712         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2713         enum port port = encoder->port;
2714         u32 val;
2715
2716         mutex_lock(&dev_priv->dpll_lock);
2717
2718         val = I915_READ(DPCLKA_CFGCR0_ICL);
2719         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2720
2721         if (intel_port_is_combophy(dev_priv, port)) {
2722                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2723                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2724                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2725                 POSTING_READ(DPCLKA_CFGCR0_ICL);
2726         }
2727
2728         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2729         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2730
2731         mutex_unlock(&dev_priv->dpll_lock);
2732 }
2733
2734 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2735 {
2736         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2737         enum port port = encoder->port;
2738         u32 val;
2739
2740         mutex_lock(&dev_priv->dpll_lock);
2741
2742         val = I915_READ(DPCLKA_CFGCR0_ICL);
2743         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2744         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2745
2746         mutex_unlock(&dev_priv->dpll_lock);
2747 }
2748
2749 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2750 {
2751         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2752         u32 val;
2753         enum port port;
2754         u32 port_mask;
2755         bool ddi_clk_needed;
2756
2757         /*
2758          * In case of DP MST, we sanitize the primary encoder only, not the
2759          * virtual ones.
2760          */
2761         if (encoder->type == INTEL_OUTPUT_DP_MST)
2762                 return;
2763
2764         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2765                 u8 pipe_mask;
2766                 bool is_mst;
2767
2768                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2769                 /*
2770                  * In the unlikely case that BIOS enables DP in MST mode, just
2771                  * warn since our MST HW readout is incomplete.
2772                  */
2773                 if (WARN_ON(is_mst))
2774                         return;
2775         }
2776
2777         port_mask = BIT(encoder->port);
2778         ddi_clk_needed = encoder->base.crtc;
2779
2780         if (encoder->type == INTEL_OUTPUT_DSI) {
2781                 struct intel_encoder *other_encoder;
2782
2783                 port_mask = intel_dsi_encoder_ports(encoder);
2784                 /*
2785                  * Sanity check that we haven't incorrectly registered another
2786                  * encoder using any of the ports of this DSI encoder.
2787                  */
2788                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2789                         if (other_encoder == encoder)
2790                                 continue;
2791
2792                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
2793                                 return;
2794                 }
2795                 /*
2796                  * DSI ports should have their DDI clock ungated when disabled
2797                  * and gated when enabled.
2798                  */
2799                 ddi_clk_needed = !encoder->base.crtc;
2800         }
2801
2802         val = I915_READ(DPCLKA_CFGCR0_ICL);
2803         for_each_port_masked(port, port_mask) {
2804                 bool ddi_clk_ungated = !(val &
2805                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
2806                                                                    port));
2807
2808                 if (ddi_clk_needed == ddi_clk_ungated)
2809                         continue;
2810
2811                 /*
2812                  * Punt on the case now where clock is gated, but it would
2813                  * be needed by the port. Something else is really broken then.
2814                  */
2815                 if (WARN_ON(ddi_clk_needed))
2816                         continue;
2817
2818                 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2819                          port_name(port));
2820                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2821                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2822         }
2823 }
2824
2825 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2826                                  const struct intel_crtc_state *crtc_state)
2827 {
2828         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2829         enum port port = encoder->port;
2830         u32 val;
2831         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2832
2833         if (WARN_ON(!pll))
2834                 return;
2835
2836         mutex_lock(&dev_priv->dpll_lock);
2837
2838         if (INTEL_GEN(dev_priv) >= 11) {
2839                 if (!intel_port_is_combophy(dev_priv, port))
2840                         I915_WRITE(DDI_CLK_SEL(port),
2841                                    icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2842         } else if (IS_CANNONLAKE(dev_priv)) {
2843                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2844                 val = I915_READ(DPCLKA_CFGCR0);
2845                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2846                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2847                 I915_WRITE(DPCLKA_CFGCR0, val);
2848
2849                 /*
2850                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2851                  * This step and the step before must be done with separate
2852                  * register writes.
2853                  */
2854                 val = I915_READ(DPCLKA_CFGCR0);
2855                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2856                 I915_WRITE(DPCLKA_CFGCR0, val);
2857         } else if (IS_GEN9_BC(dev_priv)) {
2858                 /* DDI -> PLL mapping  */
2859                 val = I915_READ(DPLL_CTRL2);
2860
2861                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2862                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2863                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2864                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2865
2866                 I915_WRITE(DPLL_CTRL2, val);
2867
2868         } else if (INTEL_GEN(dev_priv) < 9) {
2869                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2870         }
2871
2872         mutex_unlock(&dev_priv->dpll_lock);
2873 }
2874
2875 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2876 {
2877         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2878         enum port port = encoder->port;
2879
2880         if (INTEL_GEN(dev_priv) >= 11) {
2881                 if (!intel_port_is_combophy(dev_priv, port))
2882                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2883         } else if (IS_CANNONLAKE(dev_priv)) {
2884                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2885                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2886         } else if (IS_GEN9_BC(dev_priv)) {
2887                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2888                            DPLL_CTRL2_DDI_CLK_OFF(port));
2889         } else if (INTEL_GEN(dev_priv) < 9) {
2890                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2891         }
2892 }
2893
2894 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2895 {
2896         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2897         enum port port = dig_port->base.port;
2898         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2899         i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) };
2900         u32 val;
2901         int i;
2902
2903         if (tc_port == PORT_TC_NONE)
2904                 return;
2905
2906         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2907                 val = I915_READ(mg_regs[i]);
2908                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2909                        MG_DP_MODE_CFG_TRPWR_GATING |
2910                        MG_DP_MODE_CFG_CLNPWR_GATING |
2911                        MG_DP_MODE_CFG_DIGPWR_GATING |
2912                        MG_DP_MODE_CFG_GAONPWR_GATING;
2913                 I915_WRITE(mg_regs[i], val);
2914         }
2915
2916         val = I915_READ(MG_MISC_SUS0(tc_port));
2917         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2918                MG_MISC_SUS0_CFG_TR2PWR_GATING |
2919                MG_MISC_SUS0_CFG_CL2PWR_GATING |
2920                MG_MISC_SUS0_CFG_GAONPWR_GATING |
2921                MG_MISC_SUS0_CFG_TRPWR_GATING |
2922                MG_MISC_SUS0_CFG_CL1PWR_GATING |
2923                MG_MISC_SUS0_CFG_DGPWR_GATING;
2924         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2925 }
2926
2927 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2928 {
2929         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2930         enum port port = dig_port->base.port;
2931         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2932         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2933         u32 val;
2934         int i;
2935
2936         if (tc_port == PORT_TC_NONE)
2937                 return;
2938
2939         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2940                 val = I915_READ(mg_regs[i]);
2941                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2942                          MG_DP_MODE_CFG_TRPWR_GATING |
2943                          MG_DP_MODE_CFG_CLNPWR_GATING |
2944                          MG_DP_MODE_CFG_DIGPWR_GATING |
2945                          MG_DP_MODE_CFG_GAONPWR_GATING);
2946                 I915_WRITE(mg_regs[i], val);
2947         }
2948
2949         val = I915_READ(MG_MISC_SUS0(tc_port));
2950         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2951                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
2952                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
2953                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
2954                  MG_MISC_SUS0_CFG_TRPWR_GATING |
2955                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
2956                  MG_MISC_SUS0_CFG_DGPWR_GATING);
2957         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2958 }
2959
2960 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2961 {
2962         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2963         enum port port = intel_dig_port->base.port;
2964         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2965         u32 ln0, ln1, lane_info;
2966
2967         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
2968                 return;
2969
2970         ln0 = I915_READ(MG_DP_MODE(0, port));
2971         ln1 = I915_READ(MG_DP_MODE(1, port));
2972
2973         switch (intel_dig_port->tc_type) {
2974         case TC_PORT_TYPEC:
2975                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2976                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2977
2978                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
2979                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
2980                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
2981
2982                 switch (lane_info) {
2983                 case 0x1:
2984                 case 0x4:
2985                         break;
2986                 case 0x2:
2987                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2988                         break;
2989                 case 0x3:
2990                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
2991                                MG_DP_MODE_CFG_DP_X2_MODE;
2992                         break;
2993                 case 0x8:
2994                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2995                         break;
2996                 case 0xC:
2997                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
2998                                MG_DP_MODE_CFG_DP_X2_MODE;
2999                         break;
3000                 case 0xF:
3001                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3002                                MG_DP_MODE_CFG_DP_X2_MODE;
3003                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3004                                MG_DP_MODE_CFG_DP_X2_MODE;
3005                         break;
3006                 default:
3007                         MISSING_CASE(lane_info);
3008                 }
3009                 break;
3010
3011         case TC_PORT_LEGACY:
3012                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3013                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3014                 break;
3015
3016         default:
3017                 MISSING_CASE(intel_dig_port->tc_type);
3018                 return;
3019         }
3020
3021         I915_WRITE(MG_DP_MODE(0, port), ln0);
3022         I915_WRITE(MG_DP_MODE(1, port), ln1);
3023 }
3024
3025 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3026                                         const struct intel_crtc_state *crtc_state)
3027 {
3028         if (!crtc_state->fec_enable)
3029                 return;
3030
3031         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3032                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3033 }
3034
3035 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3036                                  const struct intel_crtc_state *crtc_state)
3037 {
3038         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3039         enum port port = encoder->port;
3040         u32 val;
3041
3042         if (!crtc_state->fec_enable)
3043                 return;
3044
3045         val = I915_READ(DP_TP_CTL(port));
3046         val |= DP_TP_CTL_FEC_ENABLE;
3047         I915_WRITE(DP_TP_CTL(port), val);
3048
3049         if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
3050                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3051                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3052                                     1))
3053                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3054 }
3055
3056 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3057                                         const struct intel_crtc_state *crtc_state)
3058 {
3059         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3060         enum port port = encoder->port;
3061         u32 val;
3062
3063         if (!crtc_state->fec_enable)
3064                 return;
3065
3066         val = I915_READ(DP_TP_CTL(port));
3067         val &= ~DP_TP_CTL_FEC_ENABLE;
3068         I915_WRITE(DP_TP_CTL(port), val);
3069         POSTING_READ(DP_TP_CTL(port));
3070 }
3071
3072 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3073                                     const struct intel_crtc_state *crtc_state,
3074                                     const struct drm_connector_state *conn_state)
3075 {
3076         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3077         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3078         enum port port = encoder->port;
3079         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3080         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3081         int level = intel_ddi_dp_level(intel_dp);
3082
3083         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3084
3085         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3086                                  crtc_state->lane_count, is_mst);
3087
3088         intel_edp_panel_on(intel_dp);
3089
3090         intel_ddi_clk_select(encoder, crtc_state);
3091
3092         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3093
3094         icl_program_mg_dp_mode(dig_port);
3095         icl_disable_phy_clock_gating(dig_port);
3096
3097         if (INTEL_GEN(dev_priv) >= 11)
3098                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3099                                         level, encoder->type);
3100         else if (IS_CANNONLAKE(dev_priv))
3101                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3102         else if (IS_GEN9_LP(dev_priv))
3103                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3104         else
3105                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3106
3107         intel_ddi_init_dp_buf_reg(encoder);
3108         if (!is_mst)
3109                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3110         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3111                                               true);
3112         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3113         intel_dp_start_link_train(intel_dp);
3114         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3115                 intel_dp_stop_link_train(intel_dp);
3116
3117         intel_ddi_enable_fec(encoder, crtc_state);
3118
3119         icl_enable_phy_clock_gating(dig_port);
3120
3121         if (!is_mst)
3122                 intel_ddi_enable_pipe_clock(crtc_state);
3123
3124         intel_dsc_enable(encoder, crtc_state);
3125 }
3126
3127 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3128                                       const struct intel_crtc_state *crtc_state,
3129                                       const struct drm_connector_state *conn_state)
3130 {
3131         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3132         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3133         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3134         enum port port = encoder->port;
3135         int level = intel_ddi_hdmi_level(dev_priv, port);
3136         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3137
3138         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3139         intel_ddi_clk_select(encoder, crtc_state);
3140
3141         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3142
3143         icl_program_mg_dp_mode(dig_port);
3144         icl_disable_phy_clock_gating(dig_port);
3145
3146         if (INTEL_GEN(dev_priv) >= 11)
3147                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3148                                         level, INTEL_OUTPUT_HDMI);
3149         else if (IS_CANNONLAKE(dev_priv))
3150                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3151         else if (IS_GEN9_LP(dev_priv))
3152                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3153         else
3154                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3155
3156         icl_enable_phy_clock_gating(dig_port);
3157
3158         if (IS_GEN9_BC(dev_priv))
3159                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3160
3161         intel_ddi_enable_pipe_clock(crtc_state);
3162
3163         intel_dig_port->set_infoframes(encoder,
3164                                        crtc_state->has_infoframe,
3165                                        crtc_state, conn_state);
3166 }
3167
3168 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3169                                  const struct intel_crtc_state *crtc_state,
3170                                  const struct drm_connector_state *conn_state)
3171 {
3172         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3173         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3174         enum pipe pipe = crtc->pipe;
3175
3176         /*
3177          * When called from DP MST code:
3178          * - conn_state will be NULL
3179          * - encoder will be the main encoder (ie. mst->primary)
3180          * - the main connector associated with this port
3181          *   won't be active or linked to a crtc
3182          * - crtc_state will be the state of the first stream to
3183          *   be activated on this port, and it may not be the same
3184          *   stream that will be deactivated last, but each stream
3185          *   should have a state that is identical when it comes to
3186          *   the DP link parameteres
3187          */
3188
3189         WARN_ON(crtc_state->has_pch_encoder);
3190
3191         if (INTEL_GEN(dev_priv) >= 11)
3192                 icl_map_plls_to_ports(encoder, crtc_state);
3193
3194         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3195
3196         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3197                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3198         } else {
3199                 struct intel_lspcon *lspcon =
3200                                 enc_to_intel_lspcon(&encoder->base);
3201
3202                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3203                 if (lspcon->active) {
3204                         struct intel_digital_port *dig_port =
3205                                         enc_to_dig_port(&encoder->base);
3206
3207                         dig_port->set_infoframes(encoder,
3208                                                  crtc_state->has_infoframe,
3209                                                  crtc_state, conn_state);
3210                 }
3211         }
3212 }
3213
3214 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3215                                   const struct intel_crtc_state *crtc_state)
3216 {
3217         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3218         enum port port = encoder->port;
3219         bool wait = false;
3220         u32 val;
3221
3222         val = I915_READ(DDI_BUF_CTL(port));
3223         if (val & DDI_BUF_CTL_ENABLE) {
3224                 val &= ~DDI_BUF_CTL_ENABLE;
3225                 I915_WRITE(DDI_BUF_CTL(port), val);
3226                 wait = true;
3227         }
3228
3229         val = I915_READ(DP_TP_CTL(port));
3230         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3231         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3232         I915_WRITE(DP_TP_CTL(port), val);
3233
3234         /* Disable FEC in DP Sink */
3235         intel_ddi_disable_fec_state(encoder, crtc_state);
3236
3237         if (wait)
3238                 intel_wait_ddi_buf_idle(dev_priv, port);
3239 }
3240
3241 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3242                                       const struct intel_crtc_state *old_crtc_state,
3243                                       const struct drm_connector_state *old_conn_state)
3244 {
3245         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3246         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3247         struct intel_dp *intel_dp = &dig_port->dp;
3248         bool is_mst = intel_crtc_has_type(old_crtc_state,
3249                                           INTEL_OUTPUT_DP_MST);
3250
3251         if (!is_mst) {
3252                 intel_ddi_disable_pipe_clock(old_crtc_state);
3253                 /*
3254                  * Power down sink before disabling the port, otherwise we end
3255                  * up getting interrupts from the sink on detecting link loss.
3256                  */
3257                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3258         }
3259
3260         intel_disable_ddi_buf(encoder, old_crtc_state);
3261
3262         intel_edp_panel_vdd_on(intel_dp);
3263         intel_edp_panel_off(intel_dp);
3264
3265         intel_display_power_put_unchecked(dev_priv,
3266                                           dig_port->ddi_io_power_domain);
3267
3268         intel_ddi_clk_disable(encoder);
3269 }
3270
3271 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3272                                         const struct intel_crtc_state *old_crtc_state,
3273                                         const struct drm_connector_state *old_conn_state)
3274 {
3275         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3276         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3277         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3278
3279         dig_port->set_infoframes(encoder, false,
3280                                  old_crtc_state, old_conn_state);
3281
3282         intel_ddi_disable_pipe_clock(old_crtc_state);
3283
3284         intel_disable_ddi_buf(encoder, old_crtc_state);
3285
3286         intel_display_power_put_unchecked(dev_priv,
3287                                           dig_port->ddi_io_power_domain);
3288
3289         intel_ddi_clk_disable(encoder);
3290
3291         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3292 }
3293
3294 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3295                                    const struct intel_crtc_state *old_crtc_state,
3296                                    const struct drm_connector_state *old_conn_state)
3297 {
3298         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3299
3300         /*
3301          * When called from DP MST code:
3302          * - old_conn_state will be NULL
3303          * - encoder will be the main encoder (ie. mst->primary)
3304          * - the main connector associated with this port
3305          *   won't be active or linked to a crtc
3306          * - old_crtc_state will be the state of the last stream to
3307          *   be deactivated on this port, and it may not be the same
3308          *   stream that was activated last, but each stream
3309          *   should have a state that is identical when it comes to
3310          *   the DP link parameteres
3311          */
3312
3313         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3314                 intel_ddi_post_disable_hdmi(encoder,
3315                                             old_crtc_state, old_conn_state);
3316         else
3317                 intel_ddi_post_disable_dp(encoder,
3318                                           old_crtc_state, old_conn_state);
3319
3320         if (INTEL_GEN(dev_priv) >= 11)
3321                 icl_unmap_plls_to_ports(encoder);
3322 }
3323
3324 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3325                                 const struct intel_crtc_state *old_crtc_state,
3326                                 const struct drm_connector_state *old_conn_state)
3327 {
3328         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3329         u32 val;
3330
3331         /*
3332          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3333          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3334          * step 13 is the correct place for it. Step 18 is where it was
3335          * originally before the BUN.
3336          */
3337         val = I915_READ(FDI_RX_CTL(PIPE_A));
3338         val &= ~FDI_RX_ENABLE;
3339         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3340
3341         intel_disable_ddi_buf(encoder, old_crtc_state);
3342         intel_ddi_clk_disable(encoder);
3343
3344         val = I915_READ(FDI_RX_MISC(PIPE_A));
3345         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3346         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3347         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3348
3349         val = I915_READ(FDI_RX_CTL(PIPE_A));
3350         val &= ~FDI_PCDCLK;
3351         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3352
3353         val = I915_READ(FDI_RX_CTL(PIPE_A));
3354         val &= ~FDI_RX_PLL_ENABLE;
3355         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3356 }
3357
3358 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3359                                 const struct intel_crtc_state *crtc_state,
3360                                 const struct drm_connector_state *conn_state)
3361 {
3362         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3363         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3364         enum port port = encoder->port;
3365
3366         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3367                 intel_dp_stop_link_train(intel_dp);
3368
3369         intel_edp_backlight_on(crtc_state, conn_state);
3370         intel_psr_enable(intel_dp, crtc_state);
3371         intel_edp_drrs_enable(intel_dp, crtc_state);
3372
3373         if (crtc_state->has_audio)
3374                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3375 }
3376
3377 static i915_reg_t
3378 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3379                                enum port port)
3380 {
3381         static const i915_reg_t regs[] = {
3382                 [PORT_A] = CHICKEN_TRANS_EDP,
3383                 [PORT_B] = CHICKEN_TRANS_A,
3384                 [PORT_C] = CHICKEN_TRANS_B,
3385                 [PORT_D] = CHICKEN_TRANS_C,
3386                 [PORT_E] = CHICKEN_TRANS_A,
3387         };
3388
3389         WARN_ON(INTEL_GEN(dev_priv) < 9);
3390
3391         if (WARN_ON(port < PORT_A || port > PORT_E))
3392                 port = PORT_A;
3393
3394         return regs[port];
3395 }
3396
3397 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3398                                   const struct intel_crtc_state *crtc_state,
3399                                   const struct drm_connector_state *conn_state)
3400 {
3401         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3402         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3403         struct drm_connector *connector = conn_state->connector;
3404         enum port port = encoder->port;
3405
3406         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3407                                                crtc_state->hdmi_high_tmds_clock_ratio,
3408                                                crtc_state->hdmi_scrambling))
3409                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3410                           connector->base.id, connector->name);
3411
3412         /* Display WA #1143: skl,kbl,cfl */
3413         if (IS_GEN9_BC(dev_priv)) {
3414                 /*
3415                  * For some reason these chicken bits have been
3416                  * stuffed into a transcoder register, event though
3417                  * the bits affect a specific DDI port rather than
3418                  * a specific transcoder.
3419                  */
3420                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3421                 u32 val;
3422
3423                 val = I915_READ(reg);
3424
3425                 if (port == PORT_E)
3426                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3427                                 DDIE_TRAINING_OVERRIDE_VALUE;
3428                 else
3429                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3430                                 DDI_TRAINING_OVERRIDE_VALUE;
3431
3432                 I915_WRITE(reg, val);
3433                 POSTING_READ(reg);
3434
3435                 udelay(1);
3436
3437                 if (port == PORT_E)
3438                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3439                                  DDIE_TRAINING_OVERRIDE_VALUE);
3440                 else
3441                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3442                                  DDI_TRAINING_OVERRIDE_VALUE);
3443
3444                 I915_WRITE(reg, val);
3445         }
3446
3447         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3448          * are ignored so nothing special needs to be done besides
3449          * enabling the port.
3450          */
3451         I915_WRITE(DDI_BUF_CTL(port),
3452                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3453
3454         if (crtc_state->has_audio)
3455                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3456 }
3457
3458 static void intel_enable_ddi(struct intel_encoder *encoder,
3459                              const struct intel_crtc_state *crtc_state,
3460                              const struct drm_connector_state *conn_state)
3461 {
3462         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3463                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3464         else
3465                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3466
3467         /* Enable hdcp if it's desired */
3468         if (conn_state->content_protection ==
3469             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3470                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3471 }
3472
3473 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3474                                  const struct intel_crtc_state *old_crtc_state,
3475                                  const struct drm_connector_state *old_conn_state)
3476 {
3477         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3478
3479         intel_dp->link_trained = false;
3480
3481         if (old_crtc_state->has_audio)
3482                 intel_audio_codec_disable(encoder,
3483                                           old_crtc_state, old_conn_state);
3484
3485         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3486         intel_psr_disable(intel_dp, old_crtc_state);
3487         intel_edp_backlight_off(old_conn_state);
3488         /* Disable the decompression in DP Sink */
3489         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3490                                               false);
3491 }
3492
3493 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3494                                    const struct intel_crtc_state *old_crtc_state,
3495                                    const struct drm_connector_state *old_conn_state)
3496 {
3497         struct drm_connector *connector = old_conn_state->connector;
3498
3499         if (old_crtc_state->has_audio)
3500                 intel_audio_codec_disable(encoder,
3501                                           old_crtc_state, old_conn_state);
3502
3503         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3504                                                false, false))
3505                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3506                               connector->base.id, connector->name);
3507 }
3508
3509 static void intel_disable_ddi(struct intel_encoder *encoder,
3510                               const struct intel_crtc_state *old_crtc_state,
3511                               const struct drm_connector_state *old_conn_state)
3512 {
3513         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3514
3515         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3516                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3517         else
3518                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3519 }
3520
3521 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3522                                      const struct intel_crtc_state *crtc_state,
3523                                      const struct drm_connector_state *conn_state)
3524 {
3525         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3526
3527         intel_ddi_set_pipe_settings(crtc_state);
3528
3529         intel_psr_update(intel_dp, crtc_state);
3530         intel_edp_drrs_enable(intel_dp, crtc_state);
3531
3532         intel_panel_update_backlight(encoder, crtc_state, conn_state);
3533 }
3534
3535 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3536                                   const struct intel_crtc_state *crtc_state,
3537                                   const struct drm_connector_state *conn_state)
3538 {
3539         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3540                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3541
3542         if (conn_state->content_protection ==
3543             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3544                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3545         else if (conn_state->content_protection ==
3546                  DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
3547                 intel_hdcp_disable(to_intel_connector(conn_state->connector));
3548 }
3549
3550 static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3551                                          const struct intel_crtc_state *pipe_config,
3552                                          enum port port)
3553 {
3554         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3555         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3556         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3557         u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3558         bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3559
3560         val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3561         switch (pipe_config->lane_count) {
3562         case 1:
3563                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3564                 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3565                 break;
3566         case 2:
3567                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3568                 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3569                 break;
3570         case 4:
3571                 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3572                 break;
3573         default:
3574                 MISSING_CASE(pipe_config->lane_count);
3575         }
3576         I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3577 }
3578
3579 static void
3580 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3581                          const struct intel_crtc_state *crtc_state,
3582                          const struct drm_connector_state *conn_state)
3583 {
3584         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3585         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3586         enum port port = encoder->port;
3587
3588         if (intel_crtc_has_dp_encoder(crtc_state) ||
3589             intel_port_is_tc(dev_priv, encoder->port))
3590                 intel_display_power_get(dev_priv,
3591                                         intel_ddi_main_link_aux_domain(dig_port));
3592
3593         if (IS_GEN9_LP(dev_priv))
3594                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3595                                                 crtc_state->lane_lat_optim_mask);
3596
3597         /*
3598          * Program the lane count for static/dynamic connections on Type-C ports.
3599          * Skip this step for TBT.
3600          */
3601         if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3602             dig_port->tc_type == TC_PORT_TBT)
3603                 return;
3604
3605         intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3606 }
3607
3608 static void
3609 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3610                            const struct intel_crtc_state *crtc_state,
3611                            const struct drm_connector_state *conn_state)
3612 {
3613         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3614         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3615
3616         if (intel_crtc_has_dp_encoder(crtc_state) ||
3617             intel_port_is_tc(dev_priv, encoder->port))
3618                 intel_display_power_put_unchecked(dev_priv,
3619                                                   intel_ddi_main_link_aux_domain(dig_port));
3620 }
3621
3622 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3623 {
3624         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3625         struct drm_i915_private *dev_priv =
3626                 to_i915(intel_dig_port->base.base.dev);
3627         enum port port = intel_dig_port->base.port;
3628         u32 val;
3629         bool wait = false;
3630
3631         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3632                 val = I915_READ(DDI_BUF_CTL(port));
3633                 if (val & DDI_BUF_CTL_ENABLE) {
3634                         val &= ~DDI_BUF_CTL_ENABLE;
3635                         I915_WRITE(DDI_BUF_CTL(port), val);
3636                         wait = true;
3637                 }
3638
3639                 val = I915_READ(DP_TP_CTL(port));
3640                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3641                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3642                 I915_WRITE(DP_TP_CTL(port), val);
3643                 POSTING_READ(DP_TP_CTL(port));
3644
3645                 if (wait)
3646                         intel_wait_ddi_buf_idle(dev_priv, port);
3647         }
3648
3649         val = DP_TP_CTL_ENABLE |
3650               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3651         if (intel_dp->link_mst)
3652                 val |= DP_TP_CTL_MODE_MST;
3653         else {
3654                 val |= DP_TP_CTL_MODE_SST;
3655                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3656                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3657         }
3658         I915_WRITE(DP_TP_CTL(port), val);
3659         POSTING_READ(DP_TP_CTL(port));
3660
3661         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3662         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3663         POSTING_READ(DDI_BUF_CTL(port));
3664
3665         udelay(600);
3666 }
3667
3668 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3669                                        enum transcoder cpu_transcoder)
3670 {
3671         if (cpu_transcoder == TRANSCODER_EDP)
3672                 return false;
3673
3674         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3675                 return false;
3676
3677         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3678                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3679 }
3680
3681 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3682                                          struct intel_crtc_state *crtc_state)
3683 {
3684         if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3685                 crtc_state->min_voltage_level = 1;
3686         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3687                 crtc_state->min_voltage_level = 2;
3688 }
3689
3690 void intel_ddi_get_config(struct intel_encoder *encoder,
3691                           struct intel_crtc_state *pipe_config)
3692 {
3693         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3694         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3695         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3696         struct intel_digital_port *intel_dig_port;
3697         u32 temp, flags = 0;
3698
3699         /* XXX: DSI transcoder paranoia */
3700         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3701                 return;
3702
3703         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3704         if (temp & TRANS_DDI_PHSYNC)
3705                 flags |= DRM_MODE_FLAG_PHSYNC;
3706         else
3707                 flags |= DRM_MODE_FLAG_NHSYNC;
3708         if (temp & TRANS_DDI_PVSYNC)
3709                 flags |= DRM_MODE_FLAG_PVSYNC;
3710         else
3711                 flags |= DRM_MODE_FLAG_NVSYNC;
3712
3713         pipe_config->base.adjusted_mode.flags |= flags;
3714
3715         switch (temp & TRANS_DDI_BPC_MASK) {
3716         case TRANS_DDI_BPC_6:
3717                 pipe_config->pipe_bpp = 18;
3718                 break;
3719         case TRANS_DDI_BPC_8:
3720                 pipe_config->pipe_bpp = 24;
3721                 break;
3722         case TRANS_DDI_BPC_10:
3723                 pipe_config->pipe_bpp = 30;
3724                 break;
3725         case TRANS_DDI_BPC_12:
3726                 pipe_config->pipe_bpp = 36;
3727                 break;
3728         default:
3729                 break;
3730         }
3731
3732         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3733         case TRANS_DDI_MODE_SELECT_HDMI:
3734                 pipe_config->has_hdmi_sink = true;
3735                 intel_dig_port = enc_to_dig_port(&encoder->base);
3736
3737                 pipe_config->infoframes.enable |=
3738                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3739
3740                 if (pipe_config->infoframes.enable)
3741                         pipe_config->has_infoframe = true;
3742
3743                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3744                         pipe_config->hdmi_scrambling = true;
3745                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3746                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3747                 /* fall through */
3748         case TRANS_DDI_MODE_SELECT_DVI:
3749                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3750                 pipe_config->lane_count = 4;
3751                 break;
3752         case TRANS_DDI_MODE_SELECT_FDI:
3753                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3754                 break;
3755         case TRANS_DDI_MODE_SELECT_DP_SST:
3756                 if (encoder->type == INTEL_OUTPUT_EDP)
3757                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3758                 else
3759                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3760                 pipe_config->lane_count =
3761                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3762                 intel_dp_get_m_n(intel_crtc, pipe_config);
3763                 break;
3764         case TRANS_DDI_MODE_SELECT_DP_MST:
3765                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3766                 pipe_config->lane_count =
3767                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3768                 intel_dp_get_m_n(intel_crtc, pipe_config);
3769                 break;
3770         default:
3771                 break;
3772         }
3773
3774         pipe_config->has_audio =
3775                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3776
3777         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3778             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3779                 /*
3780                  * This is a big fat ugly hack.
3781                  *
3782                  * Some machines in UEFI boot mode provide us a VBT that has 18
3783                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3784                  * unknown we fail to light up. Yet the same BIOS boots up with
3785                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3786                  * max, not what it tells us to use.
3787                  *
3788                  * Note: This will still be broken if the eDP panel is not lit
3789                  * up by the BIOS, and thus we can't get the mode at module
3790                  * load.
3791                  */
3792                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3793                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3794                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3795         }
3796
3797         intel_ddi_clock_get(encoder, pipe_config);
3798
3799         if (IS_GEN9_LP(dev_priv))
3800                 pipe_config->lane_lat_optim_mask =
3801                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3802
3803         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3804
3805         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3806
3807         intel_read_infoframe(encoder, pipe_config,
3808                              HDMI_INFOFRAME_TYPE_AVI,
3809                              &pipe_config->infoframes.avi);
3810         intel_read_infoframe(encoder, pipe_config,
3811                              HDMI_INFOFRAME_TYPE_SPD,
3812                              &pipe_config->infoframes.spd);
3813         intel_read_infoframe(encoder, pipe_config,
3814                              HDMI_INFOFRAME_TYPE_VENDOR,
3815                              &pipe_config->infoframes.hdmi);
3816 }
3817
3818 static enum intel_output_type
3819 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3820                               struct intel_crtc_state *crtc_state,
3821                               struct drm_connector_state *conn_state)
3822 {
3823         switch (conn_state->connector->connector_type) {
3824         case DRM_MODE_CONNECTOR_HDMIA:
3825                 return INTEL_OUTPUT_HDMI;
3826         case DRM_MODE_CONNECTOR_eDP:
3827                 return INTEL_OUTPUT_EDP;
3828         case DRM_MODE_CONNECTOR_DisplayPort:
3829                 return INTEL_OUTPUT_DP;
3830         default:
3831                 MISSING_CASE(conn_state->connector->connector_type);
3832                 return INTEL_OUTPUT_UNUSED;
3833         }
3834 }
3835
3836 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3837                                     struct intel_crtc_state *pipe_config,
3838                                     struct drm_connector_state *conn_state)
3839 {
3840         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3841         enum port port = encoder->port;
3842         int ret;
3843
3844         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
3845                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3846
3847         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3848                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3849         else
3850                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3851
3852         if (IS_GEN9_LP(dev_priv) && ret)
3853                 pipe_config->lane_lat_optim_mask =
3854                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3855
3856         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3857
3858         return ret;
3859
3860 }
3861
3862 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3863 {
3864         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3865         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3866
3867         intel_dp_encoder_suspend(encoder);
3868
3869         /*
3870          * TODO: disconnect also from USB DP alternate mode once we have a
3871          * way to handle the modeset restore in that mode during resume
3872          * even if the sink has disappeared while being suspended.
3873          */
3874         if (dig_port->tc_legacy_port)
3875                 icl_tc_phy_disconnect(i915, dig_port);
3876 }
3877
3878 static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3879 {
3880         struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3881         struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3882
3883         if (intel_port_is_tc(i915, dig_port->base.port))
3884                 intel_digital_port_connected(&dig_port->base);
3885
3886         intel_dp_encoder_reset(drm_encoder);
3887 }
3888
3889 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3890 {
3891         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3892         struct drm_i915_private *i915 = to_i915(encoder->dev);
3893
3894         intel_dp_encoder_flush_work(encoder);
3895
3896         if (intel_port_is_tc(i915, dig_port->base.port))
3897                 icl_tc_phy_disconnect(i915, dig_port);
3898
3899         drm_encoder_cleanup(encoder);
3900         kfree(dig_port);
3901 }
3902
3903 static const struct drm_encoder_funcs intel_ddi_funcs = {
3904         .reset = intel_ddi_encoder_reset,
3905         .destroy = intel_ddi_encoder_destroy,
3906 };
3907
3908 static struct intel_connector *
3909 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3910 {
3911         struct intel_connector *connector;
3912         enum port port = intel_dig_port->base.port;
3913
3914         connector = intel_connector_alloc();
3915         if (!connector)
3916                 return NULL;
3917
3918         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3919         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3920                 kfree(connector);
3921                 return NULL;
3922         }
3923
3924         return connector;
3925 }
3926
3927 static int modeset_pipe(struct drm_crtc *crtc,
3928                         struct drm_modeset_acquire_ctx *ctx)
3929 {
3930         struct drm_atomic_state *state;
3931         struct drm_crtc_state *crtc_state;
3932         int ret;
3933
3934         state = drm_atomic_state_alloc(crtc->dev);
3935         if (!state)
3936                 return -ENOMEM;
3937
3938         state->acquire_ctx = ctx;
3939
3940         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3941         if (IS_ERR(crtc_state)) {
3942                 ret = PTR_ERR(crtc_state);
3943                 goto out;
3944         }
3945
3946         crtc_state->connectors_changed = true;
3947
3948         ret = drm_atomic_commit(state);
3949 out:
3950         drm_atomic_state_put(state);
3951
3952         return ret;
3953 }
3954
3955 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3956                                  struct drm_modeset_acquire_ctx *ctx)
3957 {
3958         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3959         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3960         struct intel_connector *connector = hdmi->attached_connector;
3961         struct i2c_adapter *adapter =
3962                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3963         struct drm_connector_state *conn_state;
3964         struct intel_crtc_state *crtc_state;
3965         struct intel_crtc *crtc;
3966         u8 config;
3967         int ret;
3968
3969         if (!connector || connector->base.status != connector_status_connected)
3970                 return 0;
3971
3972         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3973                                ctx);
3974         if (ret)
3975                 return ret;
3976
3977         conn_state = connector->base.state;
3978
3979         crtc = to_intel_crtc(conn_state->crtc);
3980         if (!crtc)
3981                 return 0;
3982
3983         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3984         if (ret)
3985                 return ret;
3986
3987         crtc_state = to_intel_crtc_state(crtc->base.state);
3988
3989         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3990
3991         if (!crtc_state->base.active)
3992                 return 0;
3993
3994         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3995             !crtc_state->hdmi_scrambling)
3996                 return 0;
3997
3998         if (conn_state->commit &&
3999             !try_wait_for_completion(&conn_state->commit->hw_done))
4000                 return 0;
4001
4002         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4003         if (ret < 0) {
4004                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4005                 return 0;
4006         }
4007
4008         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4009             crtc_state->hdmi_high_tmds_clock_ratio &&
4010             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4011             crtc_state->hdmi_scrambling)
4012                 return 0;
4013
4014         /*
4015          * HDMI 2.0 says that one should not send scrambled data
4016          * prior to configuring the sink scrambling, and that
4017          * TMDS clock/data transmission should be suspended when
4018          * changing the TMDS clock rate in the sink. So let's
4019          * just do a full modeset here, even though some sinks
4020          * would be perfectly happy if were to just reconfigure
4021          * the SCDC settings on the fly.
4022          */
4023         return modeset_pipe(&crtc->base, ctx);
4024 }
4025
4026 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4027                               struct intel_connector *connector)
4028 {
4029         struct drm_modeset_acquire_ctx ctx;
4030         bool changed;
4031         int ret;
4032
4033         changed = intel_encoder_hotplug(encoder, connector);
4034
4035         drm_modeset_acquire_init(&ctx, 0);
4036
4037         for (;;) {
4038                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4039                         ret = intel_hdmi_reset_link(encoder, &ctx);
4040                 else
4041                         ret = intel_dp_retrain_link(encoder, &ctx);
4042
4043                 if (ret == -EDEADLK) {
4044                         drm_modeset_backoff(&ctx);
4045                         continue;
4046                 }
4047
4048                 break;
4049         }
4050
4051         drm_modeset_drop_locks(&ctx);
4052         drm_modeset_acquire_fini(&ctx);
4053         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4054
4055         return changed;
4056 }
4057
4058 static struct intel_connector *
4059 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4060 {
4061         struct intel_connector *connector;
4062         enum port port = intel_dig_port->base.port;
4063
4064         connector = intel_connector_alloc();
4065         if (!connector)
4066                 return NULL;
4067
4068         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4069         intel_hdmi_init_connector(intel_dig_port, connector);
4070
4071         return connector;
4072 }
4073
4074 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4075 {
4076         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4077
4078         if (dport->base.port != PORT_A)
4079                 return false;
4080
4081         if (dport->saved_port_bits & DDI_A_4_LANES)
4082                 return false;
4083
4084         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4085          *                     supported configuration
4086          */
4087         if (IS_GEN9_LP(dev_priv))
4088                 return true;
4089
4090         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4091          *             one who does also have a full A/E split called
4092          *             DDI_F what makes DDI_E useless. However for this
4093          *             case let's trust VBT info.
4094          */
4095         if (IS_CANNONLAKE(dev_priv) &&
4096             !intel_bios_is_port_present(dev_priv, PORT_E))
4097                 return true;
4098
4099         return false;
4100 }
4101
4102 static int
4103 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4104 {
4105         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4106         enum port port = intel_dport->base.port;
4107         int max_lanes = 4;
4108
4109         if (INTEL_GEN(dev_priv) >= 11)
4110                 return max_lanes;
4111
4112         if (port == PORT_A || port == PORT_E) {
4113                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4114                         max_lanes = port == PORT_A ? 4 : 0;
4115                 else
4116                         /* Both A and E share 2 lanes */
4117                         max_lanes = 2;
4118         }
4119
4120         /*
4121          * Some BIOS might fail to set this bit on port A if eDP
4122          * wasn't lit up at boot.  Force this bit set when needed
4123          * so we use the proper lane count for our calculations.
4124          */
4125         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4126                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4127                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4128                 max_lanes = 4;
4129         }
4130
4131         return max_lanes;
4132 }
4133
4134 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4135 {
4136         struct ddi_vbt_port_info *port_info =
4137                 &dev_priv->vbt.ddi_port_info[port];
4138         struct intel_digital_port *intel_dig_port;
4139         struct intel_encoder *intel_encoder;
4140         struct drm_encoder *encoder;
4141         bool init_hdmi, init_dp, init_lspcon = false;
4142         enum pipe pipe;
4143
4144         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4145         init_dp = port_info->supports_dp;
4146
4147         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4148                 /*
4149                  * Lspcon device needs to be driven with DP connector
4150                  * with special detection sequence. So make sure DP
4151                  * is initialized before lspcon.
4152                  */
4153                 init_dp = true;
4154                 init_lspcon = true;
4155                 init_hdmi = false;
4156                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4157         }
4158
4159         if (!init_dp && !init_hdmi) {
4160                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4161                               port_name(port));
4162                 return;
4163         }
4164
4165         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4166         if (!intel_dig_port)
4167                 return;
4168
4169         intel_encoder = &intel_dig_port->base;
4170         encoder = &intel_encoder->base;
4171
4172         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4173                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4174
4175         intel_encoder->hotplug = intel_ddi_hotplug;
4176         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4177         intel_encoder->compute_config = intel_ddi_compute_config;
4178         intel_encoder->enable = intel_enable_ddi;
4179         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4180         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4181         intel_encoder->pre_enable = intel_ddi_pre_enable;
4182         intel_encoder->disable = intel_disable_ddi;
4183         intel_encoder->post_disable = intel_ddi_post_disable;
4184         intel_encoder->update_pipe = intel_ddi_update_pipe;
4185         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4186         intel_encoder->get_config = intel_ddi_get_config;
4187         intel_encoder->suspend = intel_ddi_encoder_suspend;
4188         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4189         intel_encoder->type = INTEL_OUTPUT_DDI;
4190         intel_encoder->power_domain = intel_port_to_power_domain(port);
4191         intel_encoder->port = port;
4192         intel_encoder->cloneable = 0;
4193         for_each_pipe(dev_priv, pipe)
4194                 intel_encoder->crtc_mask |= BIT(pipe);
4195
4196         if (INTEL_GEN(dev_priv) >= 11)
4197                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4198                         DDI_BUF_PORT_REVERSAL;
4199         else
4200                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4201                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4202         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4203         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4204         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4205
4206         intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
4207                                          !port_info->supports_typec_usb &&
4208                                          !port_info->supports_tbt;
4209
4210         switch (port) {
4211         case PORT_A:
4212                 intel_dig_port->ddi_io_power_domain =
4213                         POWER_DOMAIN_PORT_DDI_A_IO;
4214                 break;
4215         case PORT_B:
4216                 intel_dig_port->ddi_io_power_domain =
4217                         POWER_DOMAIN_PORT_DDI_B_IO;
4218                 break;
4219         case PORT_C:
4220                 intel_dig_port->ddi_io_power_domain =
4221                         POWER_DOMAIN_PORT_DDI_C_IO;
4222                 break;
4223         case PORT_D:
4224                 intel_dig_port->ddi_io_power_domain =
4225                         POWER_DOMAIN_PORT_DDI_D_IO;
4226                 break;
4227         case PORT_E:
4228                 intel_dig_port->ddi_io_power_domain =
4229                         POWER_DOMAIN_PORT_DDI_E_IO;
4230                 break;
4231         case PORT_F:
4232                 intel_dig_port->ddi_io_power_domain =
4233                         POWER_DOMAIN_PORT_DDI_F_IO;
4234                 break;
4235         default:
4236                 MISSING_CASE(port);
4237         }
4238
4239         if (init_dp) {
4240                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4241                         goto err;
4242
4243                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4244         }
4245
4246         /* In theory we don't need the encoder->type check, but leave it just in
4247          * case we have some really bad VBTs... */
4248         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4249                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4250                         goto err;
4251         }
4252
4253         if (init_lspcon) {
4254                 if (lspcon_init(intel_dig_port))
4255                         /* TODO: handle hdmi info frame part */
4256                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4257                                 port_name(port));
4258                 else
4259                         /*
4260                          * LSPCON init faied, but DP init was success, so
4261                          * lets try to drive as DP++ port.
4262                          */
4263                         DRM_ERROR("LSPCON init failed on port %c\n",
4264                                 port_name(port));
4265         }
4266
4267         intel_infoframe_init(intel_dig_port);
4268
4269         if (intel_port_is_tc(dev_priv, port))
4270                 intel_digital_port_connected(intel_encoder);
4271
4272         return;
4273
4274 err:
4275         drm_encoder_cleanup(encoder);
4276         kfree(intel_dig_port);
4277 }