2 * Copyright © 2014 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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24 #include <linux/firmware.h>
29 * DOC: csr support for dmc
31 * Display Context Save and Restore (CSR) firmware support added from gen9
32 * onwards to drive newly added DMC (Display microcontroller) in display
33 * engine to save and restore the state of display engine when it enter into
34 * low-power state and comes back to normal.
37 #define I915_CSR_GLK "i915/glk_dmc_ver1_01.bin"
38 #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
40 #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
41 MODULE_FIRMWARE(I915_CSR_KBL);
42 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
44 #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"
45 MODULE_FIRMWARE(I915_CSR_SKL);
46 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26)
48 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
49 MODULE_FIRMWARE(I915_CSR_BXT);
50 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
52 #define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
57 #define CSR_MAX_FW_SIZE 0x2FFF
58 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
60 struct intel_css_header {
64 /* Includes the DMC specific header in dwords */
67 /* always value would be 0x10000 */
74 uint32_t module_vendor;
76 /* in YYYYMMDD format */
79 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
86 uint32_t modulus_size;
89 uint32_t exponent_size;
92 uint32_t reserved1[12];
98 uint32_t reserved2[8];
101 uint32_t kernel_header_info;
104 struct intel_fw_info {
107 /* Stepping (A, B, C, ..., *). * is a wildcard */
110 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
117 struct intel_package_header {
118 /* DMC container header length in dwords */
119 unsigned char header_len;
121 /* always value would be 0x01 */
122 unsigned char header_ver;
124 unsigned char reserved[10];
126 /* Number of valid entries in the FWInfo array below */
127 uint32_t num_entries;
129 struct intel_fw_info fw_info[20];
132 struct intel_dmc_header {
133 /* always value would be 0x40403E3E */
136 /* DMC binary header length */
137 unsigned char header_len;
140 unsigned char header_ver;
148 /* Firmware program size (excluding header) in dwords */
151 /* Major Minor version */
154 /* Number of valid MMIO cycles present. */
158 uint32_t mmioaddr[8];
161 uint32_t mmiodata[8];
164 unsigned char dfile[32];
166 uint32_t reserved1[2];
169 struct stepping_info {
174 static const struct stepping_info skl_stepping_info[] = {
175 {'A', '0'}, {'B', '0'}, {'C', '0'},
176 {'D', '0'}, {'E', '0'}, {'F', '0'},
177 {'G', '0'}, {'H', '0'}, {'I', '0'},
178 {'J', '0'}, {'K', '0'}
181 static const struct stepping_info bxt_stepping_info[] = {
182 {'A', '0'}, {'A', '1'}, {'A', '2'},
183 {'B', '0'}, {'B', '1'}, {'B', '2'}
186 static const struct stepping_info no_stepping_info = { '*', '*' };
188 static const struct stepping_info *
189 intel_get_stepping_info(struct drm_i915_private *dev_priv)
191 const struct stepping_info *si;
194 if (IS_SKYLAKE(dev_priv)) {
195 size = ARRAY_SIZE(skl_stepping_info);
196 si = skl_stepping_info;
197 } else if (IS_BROXTON(dev_priv)) {
198 size = ARRAY_SIZE(bxt_stepping_info);
199 si = bxt_stepping_info;
204 if (INTEL_REVID(dev_priv) < size)
205 return si + INTEL_REVID(dev_priv);
207 return &no_stepping_info;
210 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
214 mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
216 if (IS_BROXTON(dev_priv))
217 mask |= DC_STATE_DEBUG_MASK_CORES;
219 /* The below bit doesn't need to be cleared ever afterwards */
220 val = I915_READ(DC_STATE_DEBUG);
221 if ((val & mask) != mask) {
223 I915_WRITE(DC_STATE_DEBUG, val);
224 POSTING_READ(DC_STATE_DEBUG);
229 * intel_csr_load_program() - write the firmware from memory to register.
230 * @dev_priv: i915 drm device.
232 * CSR firmware is read from a .bin file and kept in internal memory one time.
233 * Everytime display comes back from low power state this function is called to
234 * copy the firmware from internal memory to registers.
236 void intel_csr_load_program(struct drm_i915_private *dev_priv)
238 u32 *payload = dev_priv->csr.dmc_payload;
241 if (!IS_GEN9(dev_priv)) {
242 DRM_ERROR("No CSR support available for this platform\n");
246 if (!dev_priv->csr.dmc_payload) {
247 DRM_ERROR("Tried to program CSR with empty payload\n");
251 fw_size = dev_priv->csr.dmc_fw_size;
252 for (i = 0; i < fw_size; i++)
253 I915_WRITE(CSR_PROGRAM(i), payload[i]);
255 for (i = 0; i < dev_priv->csr.mmio_count; i++) {
256 I915_WRITE(dev_priv->csr.mmioaddr[i],
257 dev_priv->csr.mmiodata[i]);
260 dev_priv->csr.dc_state = 0;
262 gen9_set_dc_state_debugmask(dev_priv);
265 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
266 const struct firmware *fw)
268 struct intel_css_header *css_header;
269 struct intel_package_header *package_header;
270 struct intel_dmc_header *dmc_header;
271 struct intel_csr *csr = &dev_priv->csr;
272 const struct stepping_info *si = intel_get_stepping_info(dev_priv);
273 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
275 uint32_t *dmc_payload;
276 uint32_t required_version;
281 /* Extract CSS Header information*/
282 css_header = (struct intel_css_header *)fw->data;
283 if (sizeof(struct intel_css_header) !=
284 (css_header->header_len * 4)) {
285 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
286 (css_header->header_len * 4));
290 csr->version = css_header->version;
292 if (IS_GEMINILAKE(dev_priv)) {
293 required_version = GLK_CSR_VERSION_REQUIRED;
294 } else if (IS_KABYLAKE(dev_priv)) {
295 required_version = KBL_CSR_VERSION_REQUIRED;
296 } else if (IS_SKYLAKE(dev_priv)) {
297 required_version = SKL_CSR_VERSION_REQUIRED;
298 } else if (IS_BROXTON(dev_priv)) {
299 required_version = BXT_CSR_VERSION_REQUIRED;
301 MISSING_CASE(INTEL_REVID(dev_priv));
302 required_version = 0;
305 if (csr->version != required_version) {
306 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
307 " please use v%u.%u [" FIRMWARE_URL "].\n",
308 CSR_VERSION_MAJOR(csr->version),
309 CSR_VERSION_MINOR(csr->version),
310 CSR_VERSION_MAJOR(required_version),
311 CSR_VERSION_MINOR(required_version));
315 readcount += sizeof(struct intel_css_header);
317 /* Extract Package Header information*/
318 package_header = (struct intel_package_header *)
319 &fw->data[readcount];
320 if (sizeof(struct intel_package_header) !=
321 (package_header->header_len * 4)) {
322 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
323 (package_header->header_len * 4));
326 readcount += sizeof(struct intel_package_header);
328 /* Search for dmc_offset to find firware binary. */
329 for (i = 0; i < package_header->num_entries; i++) {
330 if (package_header->fw_info[i].substepping == '*' &&
331 si->stepping == package_header->fw_info[i].stepping) {
332 dmc_offset = package_header->fw_info[i].offset;
334 } else if (si->stepping == package_header->fw_info[i].stepping &&
335 si->substepping == package_header->fw_info[i].substepping) {
336 dmc_offset = package_header->fw_info[i].offset;
338 } else if (package_header->fw_info[i].stepping == '*' &&
339 package_header->fw_info[i].substepping == '*')
340 dmc_offset = package_header->fw_info[i].offset;
342 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
343 DRM_ERROR("Firmware not supported for %c stepping\n",
347 readcount += dmc_offset;
349 /* Extract dmc_header information. */
350 dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
351 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
352 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
353 (dmc_header->header_len));
356 readcount += sizeof(struct intel_dmc_header);
358 /* Cache the dmc header info. */
359 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
360 DRM_ERROR("Firmware has wrong mmio count %u\n",
361 dmc_header->mmio_count);
364 csr->mmio_count = dmc_header->mmio_count;
365 for (i = 0; i < dmc_header->mmio_count; i++) {
366 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
367 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
368 DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
369 dmc_header->mmioaddr[i]);
372 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
373 csr->mmiodata[i] = dmc_header->mmiodata[i];
376 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
377 nbytes = dmc_header->fw_size * 4;
378 if (nbytes > CSR_MAX_FW_SIZE) {
379 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
382 csr->dmc_fw_size = dmc_header->fw_size;
384 dmc_payload = kmalloc(nbytes, GFP_KERNEL);
386 DRM_ERROR("Memory allocation failed for dmc payload\n");
390 return memcpy(dmc_payload, &fw->data[readcount], nbytes);
393 static void csr_load_work_fn(struct work_struct *work)
395 struct drm_i915_private *dev_priv;
396 struct intel_csr *csr;
397 const struct firmware *fw = NULL;
400 dev_priv = container_of(work, typeof(*dev_priv), csr.work);
401 csr = &dev_priv->csr;
403 ret = request_firmware(&fw, dev_priv->csr.fw_path,
404 &dev_priv->drm.pdev->dev);
406 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
408 if (dev_priv->csr.dmc_payload) {
409 intel_csr_load_program(dev_priv);
411 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
413 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
414 dev_priv->csr.fw_path,
415 CSR_VERSION_MAJOR(csr->version),
416 CSR_VERSION_MINOR(csr->version));
418 dev_notice(dev_priv->drm.dev,
419 "Failed to load DMC firmware"
420 " [" FIRMWARE_URL "],"
421 " disabling runtime power management.\n");
424 release_firmware(fw);
428 * intel_csr_ucode_init() - initialize the firmware loading.
429 * @dev_priv: i915 drm device.
431 * This function is called at the time of loading the display driver to read
432 * firmware from a .bin file and copied into a internal memory.
434 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
436 struct intel_csr *csr = &dev_priv->csr;
438 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
440 if (!HAS_CSR(dev_priv))
443 if (IS_GEMINILAKE(dev_priv))
444 csr->fw_path = I915_CSR_GLK;
445 else if (IS_KABYLAKE(dev_priv))
446 csr->fw_path = I915_CSR_KBL;
447 else if (IS_SKYLAKE(dev_priv))
448 csr->fw_path = I915_CSR_SKL;
449 else if (IS_BROXTON(dev_priv))
450 csr->fw_path = I915_CSR_BXT;
452 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
456 DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
459 * Obtain a runtime pm reference, until CSR is loaded,
460 * to avoid entering runtime-suspend.
462 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
464 schedule_work(&dev_priv->csr.work);
468 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
469 * @dev_priv: i915 drm device
471 * Prepare the DMC firmware before entering system suspend. This includes
472 * flushing pending work items and releasing any resources acquired during
475 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
477 if (!HAS_CSR(dev_priv))
480 flush_work(&dev_priv->csr.work);
482 /* Drop the reference held in case DMC isn't loaded. */
483 if (!dev_priv->csr.dmc_payload)
484 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
488 * intel_csr_ucode_resume() - init CSR firmware during system resume
489 * @dev_priv: i915 drm device
491 * Reinitialize the DMC firmware during system resume, reacquiring any
492 * resources released in intel_csr_ucode_suspend().
494 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
496 if (!HAS_CSR(dev_priv))
500 * Reacquire the reference to keep RPM disabled in case DMC isn't
503 if (!dev_priv->csr.dmc_payload)
504 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
508 * intel_csr_ucode_fini() - unload the CSR firmware.
509 * @dev_priv: i915 drm device.
511 * Firmmware unloading includes freeing the internal memory and reset the
512 * firmware loading status.
514 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
516 if (!HAS_CSR(dev_priv))
519 intel_csr_ucode_suspend(dev_priv);
521 kfree(dev_priv->csr.dmc_payload);