drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <drm/drm_atomic_helper.h>
  31 #include <drm/drm_crtc.h>
  32 #include <drm/drm_edid.h>
  33 #include <drm/drm_probe_helper.h>
  34 #include "intel_drv.h"
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37
  38 /* Here's the desired hotplug mode */
  39 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  40                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  41                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  42                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  43                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  44                            ADPA_CRT_HOTPLUG_ENABLE)
  45
  46 struct intel_crt {
  47         struct intel_encoder base;
  48         /* DPMS state is stored in the connector, which we need in the
  49          * encoder's enable/disable callbacks */
  50         struct intel_connector *connector;
  51         bool force_hotplug_required;
  52         i915_reg_t adpa_reg;
  53 };
  54
  55 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  56 {
  57         return container_of(encoder, struct intel_crt, base);
  58 }
  59
  60 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  61 {
  62         return intel_encoder_to_crt(intel_attached_encoder(connector));
  63 }
  64
  65 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
  66                             i915_reg_t adpa_reg, enum pipe *pipe)
  67 {
  68         u32 val;
  69
  70         val = I915_READ(adpa_reg);
  71
  72         /* asserts want to know the pipe even if the port is disabled */
  73         if (HAS_PCH_CPT(dev_priv))
  74                 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
  75         else
  76                 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
  77
  78         return val & ADPA_DAC_ENABLE;
  79 }
  80
  81 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  82                                    enum pipe *pipe)
  83 {
  84         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  85         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  86         intel_wakeref_t wakeref;
  87         bool ret;
  88
  89         wakeref = intel_display_power_get_if_enabled(dev_priv,
  90                                                      encoder->power_domain);
  91         if (!wakeref)
  92                 return false;
  93
  94         ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
  95
  96         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
  97
  98         return ret;
  99 }
 100
 101 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 102 {
 103         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 104         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 105         u32 tmp, flags = 0;
 106
 107         tmp = I915_READ(crt->adpa_reg);
 108
 109         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 110                 flags |= DRM_MODE_FLAG_PHSYNC;
 111         else
 112                 flags |= DRM_MODE_FLAG_NHSYNC;
 113
 114         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 115                 flags |= DRM_MODE_FLAG_PVSYNC;
 116         else
 117                 flags |= DRM_MODE_FLAG_NVSYNC;
 118
 119         return flags;
 120 }
 121
 122 static void intel_crt_get_config(struct intel_encoder *encoder,
 123                                  struct intel_crtc_state *pipe_config)
 124 {
 125         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
 126
 127         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 128
 129         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 130 }
 131
 132 static void hsw_crt_get_config(struct intel_encoder *encoder,
 133                                struct intel_crtc_state *pipe_config)
 134 {
 135         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 136
 137         intel_ddi_get_config(encoder, pipe_config);
 138
 139         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 140                                               DRM_MODE_FLAG_NHSYNC |
 141                                               DRM_MODE_FLAG_PVSYNC |
 142                                               DRM_MODE_FLAG_NVSYNC);
 143         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 144
 145         pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 146 }
 147
 148 /* Note: The caller is required to filter out dpms modes not supported by the
 149  * platform. */
 150 static void intel_crt_set_dpms(struct intel_encoder *encoder,
 151                                const struct intel_crtc_state *crtc_state,
 152                                int mode)
 153 {
 154         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 155         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 156         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 157         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 158         u32 adpa;
 159
 160         if (INTEL_GEN(dev_priv) >= 5)
 161                 adpa = ADPA_HOTPLUG_BITS;
 162         else
 163                 adpa = 0;
 164
 165         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 166                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 167         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 168                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 169
 170         /* For CPT allow 3 pipe config, for others just use A or B */
 171         if (HAS_PCH_LPT(dev_priv))
 172                 ; /* Those bits don't exist here */
 173         else if (HAS_PCH_CPT(dev_priv))
 174                 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
 175         else
 176                 adpa |= ADPA_PIPE_SEL(crtc->pipe);
 177
 178         if (!HAS_PCH_SPLIT(dev_priv))
 179                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 180
 181         switch (mode) {
 182         case DRM_MODE_DPMS_ON:
 183                 adpa |= ADPA_DAC_ENABLE;
 184                 break;
 185         case DRM_MODE_DPMS_STANDBY:
 186                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 187                 break;
 188         case DRM_MODE_DPMS_SUSPEND:
 189                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 190                 break;
 191         case DRM_MODE_DPMS_OFF:
 192                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 193                 break;
 194         }
 195
 196         I915_WRITE(crt->adpa_reg, adpa);
 197 }
 198
 199 static void intel_disable_crt(struct intel_encoder *encoder,
 200                               const struct intel_crtc_state *old_crtc_state,
 201                               const struct drm_connector_state *old_conn_state)
 202 {
 203         intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 204 }
 205
 206 static void pch_disable_crt(struct intel_encoder *encoder,
 207                             const struct intel_crtc_state *old_crtc_state,
 208                             const struct drm_connector_state *old_conn_state)
 209 {
 210 }
 211
 212 static void pch_post_disable_crt(struct intel_encoder *encoder,
 213                                  const struct intel_crtc_state *old_crtc_state,
 214                                  const struct drm_connector_state *old_conn_state)
 215 {
 216         intel_disable_crt(encoder, old_crtc_state, old_conn_state);
 217 }
 218
 219 static void hsw_disable_crt(struct intel_encoder *encoder,
 220                             const struct intel_crtc_state *old_crtc_state,
 221                             const struct drm_connector_state *old_conn_state)
 222 {
 223         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 224
 225         WARN_ON(!old_crtc_state->has_pch_encoder);
 226
 227         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 228 }
 229
 230 static void hsw_post_disable_crt(struct intel_encoder *encoder,
 231                                  const struct intel_crtc_state *old_crtc_state,
 232                                  const struct drm_connector_state *old_conn_state)
 233 {
 234         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 235
 236         intel_ddi_disable_pipe_clock(old_crtc_state);
 237
 238         pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
 239
 240         lpt_disable_pch_transcoder(dev_priv);
 241         lpt_disable_iclkip(dev_priv);
 242
 243         intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 244
 245         WARN_ON(!old_crtc_state->has_pch_encoder);
 246
 247         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 248 }
 249
 250 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
 251                                    const struct intel_crtc_state *crtc_state,
 252                                    const struct drm_connector_state *conn_state)
 253 {
 254         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 255
 256         WARN_ON(!crtc_state->has_pch_encoder);
 257
 258         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 259 }
 260
 261 static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 262                                const struct intel_crtc_state *crtc_state,
 263                                const struct drm_connector_state *conn_state)
 264 {
 265         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 266         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 267         enum pipe pipe = crtc->pipe;
 268
 269         WARN_ON(!crtc_state->has_pch_encoder);
 270
 271         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 272
 273         dev_priv->display.fdi_link_train(crtc, crtc_state);
 274
 275         intel_ddi_enable_pipe_clock(crtc_state);
 276 }
 277
 278 static void hsw_enable_crt(struct intel_encoder *encoder,
 279                            const struct intel_crtc_state *crtc_state,
 280                            const struct drm_connector_state *conn_state)
 281 {
 282         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 283         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 284         enum pipe pipe = crtc->pipe;
 285
 286         WARN_ON(!crtc_state->has_pch_encoder);
 287
 288         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 289
 290         intel_wait_for_vblank(dev_priv, pipe);
 291         intel_wait_for_vblank(dev_priv, pipe);
 292         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 293         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 294 }
 295
 296 static void intel_enable_crt(struct intel_encoder *encoder,
 297                              const struct intel_crtc_state *crtc_state,
 298                              const struct drm_connector_state *conn_state)
 299 {
 300         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 301 }
 302
 303 static enum drm_mode_status
 304 intel_crt_mode_valid(struct drm_connector *connector,
 305                      struct drm_display_mode *mode)
 306 {
 307         struct drm_device *dev = connector->dev;
 308         struct drm_i915_private *dev_priv = to_i915(dev);
 309         int max_dotclk = dev_priv->max_dotclk_freq;
 310         int max_clock;
 311
 312         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 313                 return MODE_NO_DBLESCAN;
 314
 315         if (mode->clock < 25000)
 316                 return MODE_CLOCK_LOW;
 317
 318         if (HAS_PCH_LPT(dev_priv))
 319                 max_clock = 180000;
 320         else if (IS_VALLEYVIEW(dev_priv))
 321                 /*
 322                  * 270 MHz due to current DPLL limits,
 323                  * DAC limit supposedly 355 MHz.
 324                  */
 325                 max_clock = 270000;
 326         else if (IS_GEN_RANGE(dev_priv, 3, 4))
 327                 max_clock = 400000;
 328         else
 329                 max_clock = 350000;
 330         if (mode->clock > max_clock)
 331                 return MODE_CLOCK_HIGH;
 332
 333         if (mode->clock > max_dotclk)
 334                 return MODE_CLOCK_HIGH;
 335
 336         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 337         if (HAS_PCH_LPT(dev_priv) &&
 338             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 339                 return MODE_CLOCK_HIGH;
 340
 341         /* HSW/BDW FDI limited to 4k */
 342         if (mode->hdisplay > 4096)
 343                 return MODE_H_ILLEGAL;
 344
 345         return MODE_OK;
 346 }
 347
 348 static int intel_crt_compute_config(struct intel_encoder *encoder,
 349                                     struct intel_crtc_state *pipe_config,
 350                                     struct drm_connector_state *conn_state)
 351 {
 352         struct drm_display_mode *adjusted_mode =
 353                 &pipe_config->base.adjusted_mode;
 354
 355         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 356                 return -EINVAL;
 357
 358         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 359
 360         return 0;
 361 }
 362
 363 static int pch_crt_compute_config(struct intel_encoder *encoder,
 364                                   struct intel_crtc_state *pipe_config,
 365                                   struct drm_connector_state *conn_state)
 366 {
 367         struct drm_display_mode *adjusted_mode =
 368                 &pipe_config->base.adjusted_mode;
 369
 370         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 371                 return -EINVAL;
 372
 373         pipe_config->has_pch_encoder = true;
 374         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 375
 376         return 0;
 377 }
 378
 379 static int hsw_crt_compute_config(struct intel_encoder *encoder,
 380                                   struct intel_crtc_state *pipe_config,
 381                                   struct drm_connector_state *conn_state)
 382 {
 383         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 384         struct drm_display_mode *adjusted_mode =
 385                 &pipe_config->base.adjusted_mode;
 386
 387         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 388                 return -EINVAL;
 389
 390         /* HSW/BDW FDI limited to 4k */
 391         if (adjusted_mode->crtc_hdisplay > 4096 ||
 392             adjusted_mode->crtc_hblank_start > 4096)
 393                 return -EINVAL;
 394
 395         pipe_config->has_pch_encoder = true;
 396         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 397
 398         /* LPT FDI RX only supports 8bpc. */
 399         if (HAS_PCH_LPT(dev_priv)) {
 400                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 401                         DRM_DEBUG_KMS("LPT only supports 24bpp\n");
 402                         return -EINVAL;
 403                 }
 404
 405                 pipe_config->pipe_bpp = 24;
 406         }
 407
 408         /* FDI must always be 2.7 GHz */
 409         pipe_config->port_clock = 135000 * 2;
 410
 411         return 0;
 412 }
 413
 414 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 415 {
 416         struct drm_device *dev = connector->dev;
 417         struct intel_crt *crt = intel_attached_crt(connector);
 418         struct drm_i915_private *dev_priv = to_i915(dev);
 419         u32 adpa;
 420         bool ret;
 421
 422         /* The first time through, trigger an explicit detection cycle */
 423         if (crt->force_hotplug_required) {
 424                 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 425                 u32 save_adpa;
 426
 427                 crt->force_hotplug_required = 0;
 428
 429                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 430                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 431
 432                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 433                 if (turn_off_dac)
 434                         adpa &= ~ADPA_DAC_ENABLE;
 435
 436                 I915_WRITE(crt->adpa_reg, adpa);
 437
 438                 if (intel_wait_for_register(&dev_priv->uncore,
 439                                             crt->adpa_reg,
 440                                             ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 441                                             1000))
 442                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 443
 444                 if (turn_off_dac) {
 445                         I915_WRITE(crt->adpa_reg, save_adpa);
 446                         POSTING_READ(crt->adpa_reg);
 447                 }
 448         }
 449
 450         /* Check the status to see if both blue and green are on now */
 451         adpa = I915_READ(crt->adpa_reg);
 452         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 453                 ret = true;
 454         else
 455                 ret = false;
 456         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 457
 458         return ret;
 459 }
 460
 461 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 462 {
 463         struct drm_device *dev = connector->dev;
 464         struct intel_crt *crt = intel_attached_crt(connector);
 465         struct drm_i915_private *dev_priv = to_i915(dev);
 466         bool reenable_hpd;
 467         u32 adpa;
 468         bool ret;
 469         u32 save_adpa;
 470
 471         /*
 472          * Doing a force trigger causes a hpd interrupt to get sent, which can
 473          * get us stuck in a loop if we're polling:
 474          *  - We enable power wells and reset the ADPA
 475          *  - output_poll_exec does force probe on VGA, triggering a hpd
 476          *  - HPD handler waits for poll to unlock dev->mode_config.mutex
 477          *  - output_poll_exec shuts off the ADPA, unlocks
 478          *    dev->mode_config.mutex
 479          *  - HPD handler runs, resets ADPA and brings us back to the start
 480          *
 481          * Just disable HPD interrupts here to prevent this
 482          */
 483         reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
 484
 485         save_adpa = adpa = I915_READ(crt->adpa_reg);
 486         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 487
 488         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 489
 490         I915_WRITE(crt->adpa_reg, adpa);
 491
 492         if (intel_wait_for_register(&dev_priv->uncore,
 493                                     crt->adpa_reg,
 494                                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 495                                     1000)) {
 496                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 497                 I915_WRITE(crt->adpa_reg, save_adpa);
 498         }
 499
 500         /* Check the status to see if both blue and green are on now */
 501         adpa = I915_READ(crt->adpa_reg);
 502         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 503                 ret = true;
 504         else
 505                 ret = false;
 506
 507         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 508
 509         if (reenable_hpd)
 510                 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
 511
 512         return ret;
 513 }
 514
 515 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 516 {
 517         struct drm_device *dev = connector->dev;
 518         struct drm_i915_private *dev_priv = to_i915(dev);
 519         u32 stat;
 520         bool ret = false;
 521         int i, tries = 0;
 522
 523         if (HAS_PCH_SPLIT(dev_priv))
 524                 return intel_ironlake_crt_detect_hotplug(connector);
 525
 526         if (IS_VALLEYVIEW(dev_priv))
 527                 return valleyview_crt_detect_hotplug(connector);
 528
 529         /*
 530          * On 4 series desktop, CRT detect sequence need to be done twice
 531          * to get a reliable result.
 532          */
 533
 534         if (IS_G45(dev_priv))
 535                 tries = 2;
 536         else
 537                 tries = 1;
 538
 539         for (i = 0; i < tries ; i++) {
 540                 /* turn on the FORCE_DETECT */
 541                 i915_hotplug_interrupt_update(dev_priv,
 542                                               CRT_HOTPLUG_FORCE_DETECT,
 543                                               CRT_HOTPLUG_FORCE_DETECT);
 544                 /* wait for FORCE_DETECT to go off */
 545                 if (intel_wait_for_register(&dev_priv->uncore, PORT_HOTPLUG_EN,
 546                                             CRT_HOTPLUG_FORCE_DETECT, 0,
 547                                             1000))
 548                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 549         }
 550
 551         stat = I915_READ(PORT_HOTPLUG_STAT);
 552         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 553                 ret = true;
 554
 555         /* clear the interrupt we just generated, if any */
 556         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 557
 558         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 559
 560         return ret;
 561 }
 562
 563 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 564                                 struct i2c_adapter *i2c)
 565 {
 566         struct edid *edid;
 567
 568         edid = drm_get_edid(connector, i2c);
 569
 570         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 571                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 572                 intel_gmbus_force_bit(i2c, true);
 573                 edid = drm_get_edid(connector, i2c);
 574                 intel_gmbus_force_bit(i2c, false);
 575         }
 576
 577         return edid;
 578 }
 579
 580 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 581 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 582                                 struct i2c_adapter *adapter)
 583 {
 584         struct edid *edid;
 585         int ret;
 586
 587         edid = intel_crt_get_edid(connector, adapter);
 588         if (!edid)
 589                 return 0;
 590
 591         ret = intel_connector_update_modes(connector, edid);
 592         kfree(edid);
 593
 594         return ret;
 595 }
 596
 597 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 598 {
 599         struct intel_crt *crt = intel_attached_crt(connector);
 600         struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
 601         struct edid *edid;
 602         struct i2c_adapter *i2c;
 603         bool ret = false;
 604
 605         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 606
 607         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 608         edid = intel_crt_get_edid(connector, i2c);
 609
 610         if (edid) {
 611                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 612
 613                 /*
 614                  * This may be a DVI-I connector with a shared DDC
 615                  * link between analog and digital outputs, so we
 616                  * have to check the EDID input spec of the attached device.
 617                  */
 618                 if (!is_digital) {
 619                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 620                         ret = true;
 621                 } else {
 622                         DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 623                 }
 624         } else {
 625                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 626         }
 627
 628         kfree(edid);
 629
 630         return ret;
 631 }
 632
 633 static enum drm_connector_status
 634 intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
 635 {
 636         struct drm_device *dev = crt->base.base.dev;
 637         struct drm_i915_private *dev_priv = to_i915(dev);
 638         u32 save_bclrpat;
 639         u32 save_vtotal;
 640         u32 vtotal, vactive;
 641         u32 vsample;
 642         u32 vblank, vblank_start, vblank_end;
 643         u32 dsl;
 644         i915_reg_t bclrpat_reg, vtotal_reg,
 645                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 646         u8 st00;
 647         enum drm_connector_status status;
 648
 649         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 650
 651         bclrpat_reg = BCLRPAT(pipe);
 652         vtotal_reg = VTOTAL(pipe);
 653         vblank_reg = VBLANK(pipe);
 654         vsync_reg = VSYNC(pipe);
 655         pipeconf_reg = PIPECONF(pipe);
 656         pipe_dsl_reg = PIPEDSL(pipe);
 657
 658         save_bclrpat = I915_READ(bclrpat_reg);
 659         save_vtotal = I915_READ(vtotal_reg);
 660         vblank = I915_READ(vblank_reg);
 661
 662         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 663         vactive = (save_vtotal & 0x7ff) + 1;
 664
 665         vblank_start = (vblank & 0xfff) + 1;
 666         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 667
 668         /* Set the border color to purple. */
 669         I915_WRITE(bclrpat_reg, 0x500050);
 670
 671         if (!IS_GEN(dev_priv, 2)) {
 672                 u32 pipeconf = I915_READ(pipeconf_reg);
 673                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 674                 POSTING_READ(pipeconf_reg);
 675                 /* Wait for next Vblank to substitue
 676                  * border color for Color info */
 677                 intel_wait_for_vblank(dev_priv, pipe);
 678                 st00 = I915_READ8(_VGA_MSR_WRITE);
 679                 status = ((st00 & (1 << 4)) != 0) ?
 680                         connector_status_connected :
 681                         connector_status_disconnected;
 682
 683                 I915_WRITE(pipeconf_reg, pipeconf);
 684         } else {
 685                 bool restore_vblank = false;
 686                 int count, detect;
 687
 688                 /*
 689                 * If there isn't any border, add some.
 690                 * Yes, this will flicker
 691                 */
 692                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 693                         u32 vsync = I915_READ(vsync_reg);
 694                         u32 vsync_start = (vsync & 0xffff) + 1;
 695
 696                         vblank_start = vsync_start;
 697                         I915_WRITE(vblank_reg,
 698                                    (vblank_start - 1) |
 699                                    ((vblank_end - 1) << 16));
 700                         restore_vblank = true;
 701                 }
 702                 /* sample in the vertical border, selecting the larger one */
 703                 if (vblank_start - vactive >= vtotal - vblank_end)
 704                         vsample = (vblank_start + vactive) >> 1;
 705                 else
 706                         vsample = (vtotal + vblank_end) >> 1;
 707
 708                 /*
 709                  * Wait for the border to be displayed
 710                  */
 711                 while (I915_READ(pipe_dsl_reg) >= vactive)
 712                         ;
 713                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 714                         ;
 715                 /*
 716                  * Watch ST00 for an entire scanline
 717                  */
 718                 detect = 0;
 719                 count = 0;
 720                 do {
 721                         count++;
 722                         /* Read the ST00 VGA status register */
 723                         st00 = I915_READ8(_VGA_MSR_WRITE);
 724                         if (st00 & (1 << 4))
 725                                 detect++;
 726                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 727
 728                 /* restore vblank if necessary */
 729                 if (restore_vblank)
 730                         I915_WRITE(vblank_reg, vblank);
 731                 /*
 732                  * If more than 3/4 of the scanline detected a monitor,
 733                  * then it is assumed to be present. This works even on i830,
 734                  * where there isn't any way to force the border color across
 735                  * the screen
 736                  */
 737                 status = detect * 4 > count * 3 ?
 738                          connector_status_connected :
 739                          connector_status_disconnected;
 740         }
 741
 742         /* Restore previous settings */
 743         I915_WRITE(bclrpat_reg, save_bclrpat);
 744
 745         return status;
 746 }
 747
 748 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
 749 {
 750         DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
 751         return 1;
 752 }
 753
 754 static const struct dmi_system_id intel_spurious_crt_detect[] = {
 755         {
 756                 .callback = intel_spurious_crt_detect_dmi_callback,
 757                 .ident = "ACER ZGB",
 758                 .matches = {
 759                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 760                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 761                 },
 762         },
 763         {
 764                 .callback = intel_spurious_crt_detect_dmi_callback,
 765                 .ident = "Intel DZ77BH-55K",
 766                 .matches = {
 767                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
 768                         DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
 769                 },
 770         },
 771         { }
 772 };
 773
 774 static int
 775 intel_crt_detect(struct drm_connector *connector,
 776                  struct drm_modeset_acquire_ctx *ctx,
 777                  bool force)
 778 {
 779         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 780         struct intel_crt *crt = intel_attached_crt(connector);
 781         struct intel_encoder *intel_encoder = &crt->base;
 782         intel_wakeref_t wakeref;
 783         int status, ret;
 784         struct intel_load_detect_pipe tmp;
 785
 786         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 787                       connector->base.id, connector->name,
 788                       force);
 789
 790         if (i915_modparams.load_detect_test) {
 791                 wakeref = intel_display_power_get(dev_priv,
 792                                                   intel_encoder->power_domain);
 793                 goto load_detect;
 794         }
 795
 796         /* Skip machines without VGA that falsely report hotplug events */
 797         if (dmi_check_system(intel_spurious_crt_detect))
 798                 return connector_status_disconnected;
 799
 800         wakeref = intel_display_power_get(dev_priv,
 801                                           intel_encoder->power_domain);
 802
 803         if (I915_HAS_HOTPLUG(dev_priv)) {
 804                 /* We can not rely on the HPD pin always being correctly wired
 805                  * up, for example many KVM do not pass it through, and so
 806                  * only trust an assertion that the monitor is connected.
 807                  */
 808                 if (intel_crt_detect_hotplug(connector)) {
 809                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 810                         status = connector_status_connected;
 811                         goto out;
 812                 } else
 813                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 814         }
 815
 816         if (intel_crt_detect_ddc(connector)) {
 817                 status = connector_status_connected;
 818                 goto out;
 819         }
 820
 821         /* Load detection is broken on HPD capable machines. Whoever wants a
 822          * broken monitor (without edid) to work behind a broken kvm (that fails
 823          * to have the right resistors for HP detection) needs to fix this up.
 824          * For now just bail out. */
 825         if (I915_HAS_HOTPLUG(dev_priv)) {
 826                 status = connector_status_disconnected;
 827                 goto out;
 828         }
 829
 830 load_detect:
 831         if (!force) {
 832                 status = connector->status;
 833                 goto out;
 834         }
 835
 836         /* for pre-945g platforms use load detect */
 837         ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
 838         if (ret > 0) {
 839                 if (intel_crt_detect_ddc(connector))
 840                         status = connector_status_connected;
 841                 else if (INTEL_GEN(dev_priv) < 4)
 842                         status = intel_crt_load_detect(crt,
 843                                 to_intel_crtc(connector->state->crtc)->pipe);
 844                 else if (i915_modparams.load_detect_test)
 845                         status = connector_status_disconnected;
 846                 else
 847                         status = connector_status_unknown;
 848                 intel_release_load_detect_pipe(connector, &tmp, ctx);
 849         } else if (ret == 0) {
 850                 status = connector_status_unknown;
 851         } else {
 852                 status = ret;
 853         }
 854
 855 out:
 856         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 857         return status;
 858 }
 859
 860 static int intel_crt_get_modes(struct drm_connector *connector)
 861 {
 862         struct drm_device *dev = connector->dev;
 863         struct drm_i915_private *dev_priv = to_i915(dev);
 864         struct intel_crt *crt = intel_attached_crt(connector);
 865         struct intel_encoder *intel_encoder = &crt->base;
 866         intel_wakeref_t wakeref;
 867         struct i2c_adapter *i2c;
 868         int ret;
 869
 870         wakeref = intel_display_power_get(dev_priv,
 871                                           intel_encoder->power_domain);
 872
 873         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 874         ret = intel_crt_ddc_get_modes(connector, i2c);
 875         if (ret || !IS_G4X(dev_priv))
 876                 goto out;
 877
 878         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 879         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 880         ret = intel_crt_ddc_get_modes(connector, i2c);
 881
 882 out:
 883         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 884
 885         return ret;
 886 }
 887
 888 void intel_crt_reset(struct drm_encoder *encoder)
 889 {
 890         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 891         struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 892
 893         if (INTEL_GEN(dev_priv) >= 5) {
 894                 u32 adpa;
 895
 896                 adpa = I915_READ(crt->adpa_reg);
 897                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 898                 adpa |= ADPA_HOTPLUG_BITS;
 899                 I915_WRITE(crt->adpa_reg, adpa);
 900                 POSTING_READ(crt->adpa_reg);
 901
 902                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 903                 crt->force_hotplug_required = 1;
 904         }
 905
 906 }
 907
 908 /*
 909  * Routines for controlling stuff on the analog port
 910  */
 911
 912 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 913         .fill_modes = drm_helper_probe_single_connector_modes,
 914         .late_register = intel_connector_register,
 915         .early_unregister = intel_connector_unregister,
 916         .destroy = intel_connector_destroy,
 917         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 918         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 919 };
 920
 921 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 922         .detect_ctx = intel_crt_detect,
 923         .mode_valid = intel_crt_mode_valid,
 924         .get_modes = intel_crt_get_modes,
 925 };
 926
 927 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 928         .reset = intel_crt_reset,
 929         .destroy = intel_encoder_destroy,
 930 };
 931
 932 void intel_crt_init(struct drm_i915_private *dev_priv)
 933 {
 934         struct drm_connector *connector;
 935         struct intel_crt *crt;
 936         struct intel_connector *intel_connector;
 937         i915_reg_t adpa_reg;
 938         u32 adpa;
 939
 940         if (HAS_PCH_SPLIT(dev_priv))
 941                 adpa_reg = PCH_ADPA;
 942         else if (IS_VALLEYVIEW(dev_priv))
 943                 adpa_reg = VLV_ADPA;
 944         else
 945                 adpa_reg = ADPA;
 946
 947         adpa = I915_READ(adpa_reg);
 948         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 949                 /*
 950                  * On some machines (some IVB at least) CRT can be
 951                  * fused off, but there's no known fuse bit to
 952                  * indicate that. On these machine the ADPA register
 953                  * works normally, except the DAC enable bit won't
 954                  * take. So the only way to tell is attempt to enable
 955                  * it and see what happens.
 956                  */
 957                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
 958                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 959                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
 960                         return;
 961                 I915_WRITE(adpa_reg, adpa);
 962         }
 963
 964         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 965         if (!crt)
 966                 return;
 967
 968         intel_connector = intel_connector_alloc();
 969         if (!intel_connector) {
 970                 kfree(crt);
 971                 return;
 972         }
 973
 974         connector = &intel_connector->base;
 975         crt->connector = intel_connector;
 976         drm_connector_init(&dev_priv->drm, &intel_connector->base,
 977                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 978
 979         drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
 980                          DRM_MODE_ENCODER_DAC, "CRT");
 981
 982         intel_connector_attach_encoder(intel_connector, &crt->base);
 983
 984         crt->base.type = INTEL_OUTPUT_ANALOG;
 985         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 986         if (IS_I830(dev_priv))
 987                 crt->base.crtc_mask = (1 << 0);
 988         else
 989                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 990
 991         if (IS_GEN(dev_priv, 2))
 992                 connector->interlace_allowed = 0;
 993         else
 994                 connector->interlace_allowed = 1;
 995         connector->doublescan_allowed = 0;
 996
 997         crt->adpa_reg = adpa_reg;
 998
 999         crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1000
1001         if (I915_HAS_HOTPLUG(dev_priv) &&
1002             !dmi_check_system(intel_spurious_crt_detect)) {
1003                 crt->base.hpd_pin = HPD_CRT;
1004                 crt->base.hotplug = intel_encoder_hotplug;
1005         }
1006
1007         if (HAS_DDI(dev_priv)) {
1008                 crt->base.port = PORT_E;
1009                 crt->base.get_config = hsw_crt_get_config;
1010                 crt->base.get_hw_state = intel_ddi_get_hw_state;
1011                 crt->base.compute_config = hsw_crt_compute_config;
1012                 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1013                 crt->base.pre_enable = hsw_pre_enable_crt;
1014                 crt->base.enable = hsw_enable_crt;
1015                 crt->base.disable = hsw_disable_crt;
1016                 crt->base.post_disable = hsw_post_disable_crt;
1017         } else {
1018                 if (HAS_PCH_SPLIT(dev_priv)) {
1019                         crt->base.compute_config = pch_crt_compute_config;
1020                         crt->base.disable = pch_disable_crt;
1021                         crt->base.post_disable = pch_post_disable_crt;
1022                 } else {
1023                         crt->base.compute_config = intel_crt_compute_config;
1024                         crt->base.disable = intel_disable_crt;
1025                 }
1026                 crt->base.port = PORT_NONE;
1027                 crt->base.get_config = intel_crt_get_config;
1028                 crt->base.get_hw_state = intel_crt_get_hw_state;
1029                 crt->base.enable = intel_enable_crt;
1030         }
1031         intel_connector->get_hw_state = intel_connector_get_hw_state;
1032
1033         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1034
1035         if (!I915_HAS_HOTPLUG(dev_priv))
1036                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1037
1038         /*
1039          * Configure the automatic hotplug detection stuff
1040          */
1041         crt->force_hotplug_required = 0;
1042
1043         /*
1044          * TODO: find a proper way to discover whether we need to set the the
1045          * polarity and link reversal bits or not, instead of relying on the
1046          * BIOS.
1047          */
1048         if (HAS_PCH_LPT(dev_priv)) {
1049                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1050                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
1051
1052                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
1053         }
1054
1055         intel_crt_reset(&crt->base.base);
1056 }