drivers/gpu/drm/i915/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_drv.h"
  25
  26 /**
  27  * DOC: CDCLK / RAWCLK
  28  *
  29  * The display engine uses several different clocks to do its work. There
  30  * are two main clocks involved that aren't directly related to the actual
  31  * pixel clock or any symbol/bit clock of the actual output port. These
  32  * are the core display clock (CDCLK) and RAWCLK.
  33  *
  34  * CDCLK clocks most of the display pipe logic, and thus its frequency
  35  * must be high enough to support the rate at which pixels are flowing
  36  * through the pipes. Downscaling must also be accounted as that increases
  37  * the effective pixel rate.
  38  *
  39  * On several platforms the CDCLK frequency can be changed dynamically
  40  * to minimize power consumption for a given display configuration.
  41  * Typically changes to the CDCLK frequency require all the display pipes
  42  * to be shut down while the frequency is being changed.
  43  *
  44  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  45  * DMC will not change the active CDCLK frequency however, so that part
  46  * will still be performed by the driver directly.
  47  *
  48  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  49  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  50  * really need to know about RAWCLK is its frequency so that various
  51  * dividers can be programmed correctly.
  52  */
  53
  54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  55                                    struct intel_cdclk_state *cdclk_state)
  56 {
  57         cdclk_state->cdclk = 133333;
  58 }
  59
  60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  61                                    struct intel_cdclk_state *cdclk_state)
  62 {
  63         cdclk_state->cdclk = 200000;
  64 }
  65
  66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  67                                    struct intel_cdclk_state *cdclk_state)
  68 {
  69         cdclk_state->cdclk = 266667;
  70 }
  71
  72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  73                                    struct intel_cdclk_state *cdclk_state)
  74 {
  75         cdclk_state->cdclk = 333333;
  76 }
  77
  78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  79                                    struct intel_cdclk_state *cdclk_state)
  80 {
  81         cdclk_state->cdclk = 400000;
  82 }
  83
  84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  85                                    struct intel_cdclk_state *cdclk_state)
  86 {
  87         cdclk_state->cdclk = 450000;
  88 }
  89
  90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  91                            struct intel_cdclk_state *cdclk_state)
  92 {
  93         struct pci_dev *pdev = dev_priv->drm.pdev;
  94         u16 hpllcc = 0;
  95
  96         /*
  97          * 852GM/852GMV only supports 133 MHz and the HPLLCC
  98          * encoding is different :(
  99          * FIXME is this the right way to detect 852GM/852GMV?
 100          */
 101         if (pdev->revision == 0x1) {
 102                 cdclk_state->cdclk = 133333;
 103                 return;
 104         }
 105
 106         pci_bus_read_config_word(pdev->bus,
 107                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 108
 109         /* Assume that the hardware is in the high speed state.  This
 110          * should be the default.
 111          */
 112         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 113         case GC_CLOCK_133_200:
 114         case GC_CLOCK_133_200_2:
 115         case GC_CLOCK_100_200:
 116                 cdclk_state->cdclk = 200000;
 117                 break;
 118         case GC_CLOCK_166_250:
 119                 cdclk_state->cdclk = 250000;
 120                 break;
 121         case GC_CLOCK_100_133:
 122                 cdclk_state->cdclk = 133333;
 123                 break;
 124         case GC_CLOCK_133_266:
 125         case GC_CLOCK_133_266_2:
 126         case GC_CLOCK_166_266:
 127                 cdclk_state->cdclk = 266667;
 128                 break;
 129         }
 130 }
 131
 132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 133                              struct intel_cdclk_state *cdclk_state)
 134 {
 135         struct pci_dev *pdev = dev_priv->drm.pdev;
 136         u16 gcfgc = 0;
 137
 138         pci_read_config_word(pdev, GCFGC, &gcfgc);
 139
 140         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 141                 cdclk_state->cdclk = 133333;
 142                 return;
 143         }
 144
 145         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 146         case GC_DISPLAY_CLOCK_333_320_MHZ:
 147                 cdclk_state->cdclk = 333333;
 148                 break;
 149         default:
 150         case GC_DISPLAY_CLOCK_190_200_MHZ:
 151                 cdclk_state->cdclk = 190000;
 152                 break;
 153         }
 154 }
 155
 156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 157                              struct intel_cdclk_state *cdclk_state)
 158 {
 159         struct pci_dev *pdev = dev_priv->drm.pdev;
 160         u16 gcfgc = 0;
 161
 162         pci_read_config_word(pdev, GCFGC, &gcfgc);
 163
 164         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 165                 cdclk_state->cdclk = 133333;
 166                 return;
 167         }
 168
 169         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 170         case GC_DISPLAY_CLOCK_333_320_MHZ:
 171                 cdclk_state->cdclk = 320000;
 172                 break;
 173         default:
 174         case GC_DISPLAY_CLOCK_190_200_MHZ:
 175                 cdclk_state->cdclk = 200000;
 176                 break;
 177         }
 178 }
 179
 180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 181 {
 182         static const unsigned int blb_vco[8] = {
 183                 [0] = 3200000,
 184                 [1] = 4000000,
 185                 [2] = 5333333,
 186                 [3] = 4800000,
 187                 [4] = 6400000,
 188         };
 189         static const unsigned int pnv_vco[8] = {
 190                 [0] = 3200000,
 191                 [1] = 4000000,
 192                 [2] = 5333333,
 193                 [3] = 4800000,
 194                 [4] = 2666667,
 195         };
 196         static const unsigned int cl_vco[8] = {
 197                 [0] = 3200000,
 198                 [1] = 4000000,
 199                 [2] = 5333333,
 200                 [3] = 6400000,
 201                 [4] = 3333333,
 202                 [5] = 3566667,
 203                 [6] = 4266667,
 204         };
 205         static const unsigned int elk_vco[8] = {
 206                 [0] = 3200000,
 207                 [1] = 4000000,
 208                 [2] = 5333333,
 209                 [3] = 4800000,
 210         };
 211         static const unsigned int ctg_vco[8] = {
 212                 [0] = 3200000,
 213                 [1] = 4000000,
 214                 [2] = 5333333,
 215                 [3] = 6400000,
 216                 [4] = 2666667,
 217                 [5] = 4266667,
 218         };
 219         const unsigned int *vco_table;
 220         unsigned int vco;
 221         uint8_t tmp = 0;
 222
 223         /* FIXME other chipsets? */
 224         if (IS_GM45(dev_priv))
 225                 vco_table = ctg_vco;
 226         else if (IS_G45(dev_priv))
 227                 vco_table = elk_vco;
 228         else if (IS_I965GM(dev_priv))
 229                 vco_table = cl_vco;
 230         else if (IS_PINEVIEW(dev_priv))
 231                 vco_table = pnv_vco;
 232         else if (IS_G33(dev_priv))
 233                 vco_table = blb_vco;
 234         else
 235                 return 0;
 236
 237         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 238
 239         vco = vco_table[tmp & 0x7];
 240         if (vco == 0)
 241                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 242         else
 243                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 244
 245         return vco;
 246 }
 247
 248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 249                           struct intel_cdclk_state *cdclk_state)
 250 {
 251         struct pci_dev *pdev = dev_priv->drm.pdev;
 252         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
 253         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
 254         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
 255         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
 256         const uint8_t *div_table;
 257         unsigned int cdclk_sel;
 258         uint16_t tmp = 0;
 259
 260         cdclk_state->vco = intel_hpll_vco(dev_priv);
 261
 262         pci_read_config_word(pdev, GCFGC, &tmp);
 263
 264         cdclk_sel = (tmp >> 4) & 0x7;
 265
 266         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 267                 goto fail;
 268
 269         switch (cdclk_state->vco) {
 270         case 3200000:
 271                 div_table = div_3200;
 272                 break;
 273         case 4000000:
 274                 div_table = div_4000;
 275                 break;
 276         case 4800000:
 277                 div_table = div_4800;
 278                 break;
 279         case 5333333:
 280                 div_table = div_5333;
 281                 break;
 282         default:
 283                 goto fail;
 284         }
 285
 286         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 287                                                div_table[cdclk_sel]);
 288         return;
 289
 290 fail:
 291         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 292                   cdclk_state->vco, tmp);
 293         cdclk_state->cdclk = 190476;
 294 }
 295
 296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 297                           struct intel_cdclk_state *cdclk_state)
 298 {
 299         struct pci_dev *pdev = dev_priv->drm.pdev;
 300         u16 gcfgc = 0;
 301
 302         pci_read_config_word(pdev, GCFGC, &gcfgc);
 303
 304         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 305         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 306                 cdclk_state->cdclk = 266667;
 307                 break;
 308         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 309                 cdclk_state->cdclk = 333333;
 310                 break;
 311         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 312                 cdclk_state->cdclk = 444444;
 313                 break;
 314         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 315                 cdclk_state->cdclk = 200000;
 316                 break;
 317         default:
 318                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 319         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 320                 cdclk_state->cdclk = 133333;
 321                 break;
 322         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 323                 cdclk_state->cdclk = 166667;
 324                 break;
 325         }
 326 }
 327
 328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 329                              struct intel_cdclk_state *cdclk_state)
 330 {
 331         struct pci_dev *pdev = dev_priv->drm.pdev;
 332         static const uint8_t div_3200[] = { 16, 10,  8 };
 333         static const uint8_t div_4000[] = { 20, 12, 10 };
 334         static const uint8_t div_5333[] = { 24, 16, 14 };
 335         const uint8_t *div_table;
 336         unsigned int cdclk_sel;
 337         uint16_t tmp = 0;
 338
 339         cdclk_state->vco = intel_hpll_vco(dev_priv);
 340
 341         pci_read_config_word(pdev, GCFGC, &tmp);
 342
 343         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 344
 345         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 346                 goto fail;
 347
 348         switch (cdclk_state->vco) {
 349         case 3200000:
 350                 div_table = div_3200;
 351                 break;
 352         case 4000000:
 353                 div_table = div_4000;
 354                 break;
 355         case 5333333:
 356                 div_table = div_5333;
 357                 break;
 358         default:
 359                 goto fail;
 360         }
 361
 362         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 363                                                div_table[cdclk_sel]);
 364         return;
 365
 366 fail:
 367         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 368                   cdclk_state->vco, tmp);
 369         cdclk_state->cdclk = 200000;
 370 }
 371
 372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 373                            struct intel_cdclk_state *cdclk_state)
 374 {
 375         struct pci_dev *pdev = dev_priv->drm.pdev;
 376         unsigned int cdclk_sel;
 377         uint16_t tmp = 0;
 378
 379         cdclk_state->vco = intel_hpll_vco(dev_priv);
 380
 381         pci_read_config_word(pdev, GCFGC, &tmp);
 382
 383         cdclk_sel = (tmp >> 12) & 0x1;
 384
 385         switch (cdclk_state->vco) {
 386         case 2666667:
 387         case 4000000:
 388         case 5333333:
 389                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 390                 break;
 391         case 3200000:
 392                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 393                 break;
 394         default:
 395                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 396                           cdclk_state->vco, tmp);
 397                 cdclk_state->cdclk = 222222;
 398                 break;
 399         }
 400 }
 401
 402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 403                           struct intel_cdclk_state *cdclk_state)
 404 {
 405         uint32_t lcpll = I915_READ(LCPLL_CTL);
 406         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 407
 408         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 409                 cdclk_state->cdclk = 800000;
 410         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 411                 cdclk_state->cdclk = 450000;
 412         else if (freq == LCPLL_CLK_FREQ_450)
 413                 cdclk_state->cdclk = 450000;
 414         else if (IS_HSW_ULT(dev_priv))
 415                 cdclk_state->cdclk = 337500;
 416         else
 417                 cdclk_state->cdclk = 540000;
 418 }
 419
 420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 421 {
 422         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 423                 333333 : 320000;
 424
 425         /*
 426          * We seem to get an unstable or solid color picture at 200MHz.
 427          * Not sure what's wrong. For now use 200MHz only when all pipes
 428          * are off.
 429          */
 430         if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
 431                 return 400000;
 432         else if (min_cdclk > 266667)
 433                 return freq_320;
 434         else if (min_cdclk > 0)
 435                 return 266667;
 436         else
 437                 return 200000;
 438 }
 439
 440 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 441                           struct intel_cdclk_state *cdclk_state)
 442 {
 443         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 444         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 445                                                CCK_DISPLAY_CLOCK_CONTROL,
 446                                                cdclk_state->vco);
 447 }
 448
 449 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 450 {
 451         unsigned int credits, default_credits;
 452
 453         if (IS_CHERRYVIEW(dev_priv))
 454                 default_credits = PFI_CREDIT(12);
 455         else
 456                 default_credits = PFI_CREDIT(8);
 457
 458         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 459                 /* CHV suggested value is 31 or 63 */
 460                 if (IS_CHERRYVIEW(dev_priv))
 461                         credits = PFI_CREDIT_63;
 462                 else
 463                         credits = PFI_CREDIT(15);
 464         } else {
 465                 credits = default_credits;
 466         }
 467
 468         /*
 469          * WA - write default credits before re-programming
 470          * FIXME: should we also set the resend bit here?
 471          */
 472         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 473                    default_credits);
 474
 475         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 476                    credits | PFI_CREDIT_RESEND);
 477
 478         /*
 479          * FIXME is this guaranteed to clear
 480          * immediately or should we poll for it?
 481          */
 482         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 483 }
 484
 485 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 486                           const struct intel_cdclk_state *cdclk_state)
 487 {
 488         int cdclk = cdclk_state->cdclk;
 489         u32 val, cmd;
 490
 491         /* There are cases where we can end up here with power domains
 492          * off and a CDCLK frequency other than the minimum, like when
 493          * issuing a modeset without actually changing any display after
 494          * a system suspend.  So grab the PIPE-A domain, which covers
 495          * the HW blocks needed for the following programming.
 496          */
 497         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 498
 499         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 500                 cmd = 2;
 501         else if (cdclk == 266667)
 502                 cmd = 1;
 503         else
 504                 cmd = 0;
 505
 506         mutex_lock(&dev_priv->pcu_lock);
 507         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 508         val &= ~DSPFREQGUAR_MASK;
 509         val |= (cmd << DSPFREQGUAR_SHIFT);
 510         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 511         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 512                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 513                      50)) {
 514                 DRM_ERROR("timed out waiting for CDclk change\n");
 515         }
 516         mutex_unlock(&dev_priv->pcu_lock);
 517
 518         mutex_lock(&dev_priv->sb_lock);
 519
 520         if (cdclk == 400000) {
 521                 u32 divider;
 522
 523                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 524                                             cdclk) - 1;
 525
 526                 /* adjust cdclk divider */
 527                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 528                 val &= ~CCK_FREQUENCY_VALUES;
 529                 val |= divider;
 530                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 531
 532                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 533                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 534                              50))
 535                         DRM_ERROR("timed out waiting for CDclk change\n");
 536         }
 537
 538         /* adjust self-refresh exit latency value */
 539         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 540         val &= ~0x7f;
 541
 542         /*
 543          * For high bandwidth configs, we set a higher latency in the bunit
 544          * so that the core display fetch happens in time to avoid underruns.
 545          */
 546         if (cdclk == 400000)
 547                 val |= 4500 / 250; /* 4.5 usec */
 548         else
 549                 val |= 3000 / 250; /* 3.0 usec */
 550         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 551
 552         mutex_unlock(&dev_priv->sb_lock);
 553
 554         intel_update_cdclk(dev_priv);
 555
 556         vlv_program_pfi_credits(dev_priv);
 557
 558         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 559 }
 560
 561 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 562                           const struct intel_cdclk_state *cdclk_state)
 563 {
 564         int cdclk = cdclk_state->cdclk;
 565         u32 val, cmd;
 566
 567         switch (cdclk) {
 568         case 333333:
 569         case 320000:
 570         case 266667:
 571         case 200000:
 572                 break;
 573         default:
 574                 MISSING_CASE(cdclk);
 575                 return;
 576         }
 577
 578         /* There are cases where we can end up here with power domains
 579          * off and a CDCLK frequency other than the minimum, like when
 580          * issuing a modeset without actually changing any display after
 581          * a system suspend.  So grab the PIPE-A domain, which covers
 582          * the HW blocks needed for the following programming.
 583          */
 584         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 585
 586         /*
 587          * Specs are full of misinformation, but testing on actual
 588          * hardware has shown that we just need to write the desired
 589          * CCK divider into the Punit register.
 590          */
 591         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 592
 593         mutex_lock(&dev_priv->pcu_lock);
 594         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 595         val &= ~DSPFREQGUAR_MASK_CHV;
 596         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 597         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 598         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 599                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 600                      50)) {
 601                 DRM_ERROR("timed out waiting for CDclk change\n");
 602         }
 603         mutex_unlock(&dev_priv->pcu_lock);
 604
 605         intel_update_cdclk(dev_priv);
 606
 607         vlv_program_pfi_credits(dev_priv);
 608
 609         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 610 }
 611
 612 static int bdw_calc_cdclk(int min_cdclk)
 613 {
 614         if (min_cdclk > 540000)
 615                 return 675000;
 616         else if (min_cdclk > 450000)
 617                 return 540000;
 618         else if (min_cdclk > 337500)
 619                 return 450000;
 620         else
 621                 return 337500;
 622 }
 623
 624 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 625                           struct intel_cdclk_state *cdclk_state)
 626 {
 627         uint32_t lcpll = I915_READ(LCPLL_CTL);
 628         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 629
 630         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 631                 cdclk_state->cdclk = 800000;
 632         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 633                 cdclk_state->cdclk = 450000;
 634         else if (freq == LCPLL_CLK_FREQ_450)
 635                 cdclk_state->cdclk = 450000;
 636         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 637                 cdclk_state->cdclk = 540000;
 638         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 639                 cdclk_state->cdclk = 337500;
 640         else
 641                 cdclk_state->cdclk = 675000;
 642 }
 643
 644 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 645                           const struct intel_cdclk_state *cdclk_state)
 646 {
 647         int cdclk = cdclk_state->cdclk;
 648         uint32_t val, data;
 649         int ret;
 650
 651         if (WARN((I915_READ(LCPLL_CTL) &
 652                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 653                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 654                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 655                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 656                  "trying to change cdclk frequency with cdclk not enabled\n"))
 657                 return;
 658
 659         mutex_lock(&dev_priv->pcu_lock);
 660         ret = sandybridge_pcode_write(dev_priv,
 661                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 662         mutex_unlock(&dev_priv->pcu_lock);
 663         if (ret) {
 664                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 665                 return;
 666         }
 667
 668         val = I915_READ(LCPLL_CTL);
 669         val |= LCPLL_CD_SOURCE_FCLK;
 670         I915_WRITE(LCPLL_CTL, val);
 671
 672         /*
 673          * According to the spec, it should be enough to poll for this 1 us.
 674          * However, extensive testing shows that this can take longer.
 675          */
 676         if (wait_for_us(I915_READ(LCPLL_CTL) &
 677                         LCPLL_CD_SOURCE_FCLK_DONE, 100))
 678                 DRM_ERROR("Switching to FCLK failed\n");
 679
 680         val = I915_READ(LCPLL_CTL);
 681         val &= ~LCPLL_CLK_FREQ_MASK;
 682
 683         switch (cdclk) {
 684         case 450000:
 685                 val |= LCPLL_CLK_FREQ_450;
 686                 data = 0;
 687                 break;
 688         case 540000:
 689                 val |= LCPLL_CLK_FREQ_54O_BDW;
 690                 data = 1;
 691                 break;
 692         case 337500:
 693                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 694                 data = 2;
 695                 break;
 696         case 675000:
 697                 val |= LCPLL_CLK_FREQ_675_BDW;
 698                 data = 3;
 699                 break;
 700         default:
 701                 WARN(1, "invalid cdclk frequency\n");
 702                 return;
 703         }
 704
 705         I915_WRITE(LCPLL_CTL, val);
 706
 707         val = I915_READ(LCPLL_CTL);
 708         val &= ~LCPLL_CD_SOURCE_FCLK;
 709         I915_WRITE(LCPLL_CTL, val);
 710
 711         if (wait_for_us((I915_READ(LCPLL_CTL) &
 712                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 713                 DRM_ERROR("Switching back to LCPLL failed\n");
 714
 715         mutex_lock(&dev_priv->pcu_lock);
 716         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
 717         mutex_unlock(&dev_priv->pcu_lock);
 718
 719         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 720
 721         intel_update_cdclk(dev_priv);
 722
 723         WARN(cdclk != dev_priv->cdclk.hw.cdclk,
 724              "cdclk requested %d kHz but got %d kHz\n",
 725              cdclk, dev_priv->cdclk.hw.cdclk);
 726 }
 727
 728 static int skl_calc_cdclk(int min_cdclk, int vco)
 729 {
 730         if (vco == 8640000) {
 731                 if (min_cdclk > 540000)
 732                         return 617143;
 733                 else if (min_cdclk > 432000)
 734                         return 540000;
 735                 else if (min_cdclk > 308571)
 736                         return 432000;
 737                 else
 738                         return 308571;
 739         } else {
 740                 if (min_cdclk > 540000)
 741                         return 675000;
 742                 else if (min_cdclk > 450000)
 743                         return 540000;
 744                 else if (min_cdclk > 337500)
 745                         return 450000;
 746                 else
 747                         return 337500;
 748         }
 749 }
 750
 751 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 752                              struct intel_cdclk_state *cdclk_state)
 753 {
 754         u32 val;
 755
 756         cdclk_state->ref = 24000;
 757         cdclk_state->vco = 0;
 758
 759         val = I915_READ(LCPLL1_CTL);
 760         if ((val & LCPLL_PLL_ENABLE) == 0)
 761                 return;
 762
 763         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 764                 return;
 765
 766         val = I915_READ(DPLL_CTRL1);
 767
 768         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 769                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 770                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 771                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 772                 return;
 773
 774         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 775         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 776         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 777         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 778         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 779                 cdclk_state->vco = 8100000;
 780                 break;
 781         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 782         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 783                 cdclk_state->vco = 8640000;
 784                 break;
 785         default:
 786                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 787                 break;
 788         }
 789 }
 790
 791 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 792                           struct intel_cdclk_state *cdclk_state)
 793 {
 794         u32 cdctl;
 795
 796         skl_dpll0_update(dev_priv, cdclk_state);
 797
 798         cdclk_state->cdclk = cdclk_state->ref;
 799
 800         if (cdclk_state->vco == 0)
 801                 return;
 802
 803         cdctl = I915_READ(CDCLK_CTL);
 804
 805         if (cdclk_state->vco == 8640000) {
 806                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 807                 case CDCLK_FREQ_450_432:
 808                         cdclk_state->cdclk = 432000;
 809                         break;
 810                 case CDCLK_FREQ_337_308:
 811                         cdclk_state->cdclk = 308571;
 812                         break;
 813                 case CDCLK_FREQ_540:
 814                         cdclk_state->cdclk = 540000;
 815                         break;
 816                 case CDCLK_FREQ_675_617:
 817                         cdclk_state->cdclk = 617143;
 818                         break;
 819                 default:
 820                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 821                         break;
 822                 }
 823         } else {
 824                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 825                 case CDCLK_FREQ_450_432:
 826                         cdclk_state->cdclk = 450000;
 827                         break;
 828                 case CDCLK_FREQ_337_308:
 829                         cdclk_state->cdclk = 337500;
 830                         break;
 831                 case CDCLK_FREQ_540:
 832                         cdclk_state->cdclk = 540000;
 833                         break;
 834                 case CDCLK_FREQ_675_617:
 835                         cdclk_state->cdclk = 675000;
 836                         break;
 837                 default:
 838                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 839                         break;
 840                 }
 841         }
 842 }
 843
 844 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 845 static int skl_cdclk_decimal(int cdclk)
 846 {
 847         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 848 }
 849
 850 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 851                                         int vco)
 852 {
 853         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 854
 855         dev_priv->skl_preferred_vco_freq = vco;
 856
 857         if (changed)
 858                 intel_update_max_cdclk(dev_priv);
 859 }
 860
 861 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 862 {
 863         u32 val;
 864
 865         WARN_ON(vco != 8100000 && vco != 8640000);
 866
 867         /*
 868          * We always enable DPLL0 with the lowest link rate possible, but still
 869          * taking into account the VCO required to operate the eDP panel at the
 870          * desired frequency. The usual DP link rates operate with a VCO of
 871          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 872          * The modeset code is responsible for the selection of the exact link
 873          * rate later on, with the constraint of choosing a frequency that
 874          * works with vco.
 875          */
 876         val = I915_READ(DPLL_CTRL1);
 877
 878         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 879                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 880         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 881         if (vco == 8640000)
 882                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 883                                             SKL_DPLL0);
 884         else
 885                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 886                                             SKL_DPLL0);
 887
 888         I915_WRITE(DPLL_CTRL1, val);
 889         POSTING_READ(DPLL_CTRL1);
 890
 891         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 892
 893         if (intel_wait_for_register(dev_priv,
 894                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
 895                                     5))
 896                 DRM_ERROR("DPLL0 not locked\n");
 897
 898         dev_priv->cdclk.hw.vco = vco;
 899
 900         /* We'll want to keep using the current vco from now on. */
 901         skl_set_preferred_cdclk_vco(dev_priv, vco);
 902 }
 903
 904 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 905 {
 906         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 907         if (intel_wait_for_register(dev_priv,
 908                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
 909                                    1))
 910                 DRM_ERROR("Couldn't disable DPLL0\n");
 911
 912         dev_priv->cdclk.hw.vco = 0;
 913 }
 914
 915 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 916                           const struct intel_cdclk_state *cdclk_state)
 917 {
 918         int cdclk = cdclk_state->cdclk;
 919         int vco = cdclk_state->vco;
 920         u32 freq_select, pcu_ack, cdclk_ctl;
 921         int ret;
 922
 923         WARN_ON((cdclk == 24000) != (vco == 0));
 924
 925         mutex_lock(&dev_priv->pcu_lock);
 926         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
 927                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
 928                                 SKL_CDCLK_READY_FOR_CHANGE,
 929                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
 930         mutex_unlock(&dev_priv->pcu_lock);
 931         if (ret) {
 932                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
 933                           ret);
 934                 return;
 935         }
 936
 937         /* Choose frequency for this cdclk */
 938         switch (cdclk) {
 939         case 450000:
 940         case 432000:
 941                 freq_select = CDCLK_FREQ_450_432;
 942                 pcu_ack = 1;
 943                 break;
 944         case 540000:
 945                 freq_select = CDCLK_FREQ_540;
 946                 pcu_ack = 2;
 947                 break;
 948         case 308571:
 949         case 337500:
 950         default:
 951                 freq_select = CDCLK_FREQ_337_308;
 952                 pcu_ack = 0;
 953                 break;
 954         case 617143:
 955         case 675000:
 956                 freq_select = CDCLK_FREQ_675_617;
 957                 pcu_ack = 3;
 958                 break;
 959         }
 960
 961         if (dev_priv->cdclk.hw.vco != 0 &&
 962             dev_priv->cdclk.hw.vco != vco)
 963                 skl_dpll0_disable(dev_priv);
 964
 965         cdclk_ctl = I915_READ(CDCLK_CTL);
 966
 967         if (dev_priv->cdclk.hw.vco != vco) {
 968                 /* Wa Display #1183: skl,kbl,cfl */
 969                 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
 970                 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
 971                 I915_WRITE(CDCLK_CTL, cdclk_ctl);
 972         }
 973
 974         /* Wa Display #1183: skl,kbl,cfl */
 975         cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
 976         I915_WRITE(CDCLK_CTL, cdclk_ctl);
 977         POSTING_READ(CDCLK_CTL);
 978
 979         if (dev_priv->cdclk.hw.vco != vco)
 980                 skl_dpll0_enable(dev_priv, vco);
 981
 982         /* Wa Display #1183: skl,kbl,cfl */
 983         cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
 984         I915_WRITE(CDCLK_CTL, cdclk_ctl);
 985
 986         cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
 987         I915_WRITE(CDCLK_CTL, cdclk_ctl);
 988
 989         /* Wa Display #1183: skl,kbl,cfl */
 990         cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
 991         I915_WRITE(CDCLK_CTL, cdclk_ctl);
 992         POSTING_READ(CDCLK_CTL);
 993
 994         /* inform PCU of the change */
 995         mutex_lock(&dev_priv->pcu_lock);
 996         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
 997         mutex_unlock(&dev_priv->pcu_lock);
 998
 999         intel_update_cdclk(dev_priv);
1000 }
1001
1002 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1003 {
1004         uint32_t cdctl, expected;
1005
1006         /*
1007          * check if the pre-os initialized the display
1008          * There is SWF18 scratchpad register defined which is set by the
1009          * pre-os which can be used by the OS drivers to check the status
1010          */
1011         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1012                 goto sanitize;
1013
1014         intel_update_cdclk(dev_priv);
1015         /* Is PLL enabled and locked ? */
1016         if (dev_priv->cdclk.hw.vco == 0 ||
1017             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1018                 goto sanitize;
1019
1020         /* DPLL okay; verify the cdclock
1021          *
1022          * Noticed in some instances that the freq selection is correct but
1023          * decimal part is programmed wrong from BIOS where pre-os does not
1024          * enable display. Verify the same as well.
1025          */
1026         cdctl = I915_READ(CDCLK_CTL);
1027         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1028                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1029         if (cdctl == expected)
1030                 /* All well; nothing to sanitize */
1031                 return;
1032
1033 sanitize:
1034         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1035
1036         /* force cdclk programming */
1037         dev_priv->cdclk.hw.cdclk = 0;
1038         /* force full PLL disable + enable */
1039         dev_priv->cdclk.hw.vco = -1;
1040 }
1041
1042 /**
1043  * skl_init_cdclk - Initialize CDCLK on SKL
1044  * @dev_priv: i915 device
1045  *
1046  * Initialize CDCLK for SKL and derivatives. This is generally
1047  * done only during the display core initialization sequence,
1048  * after which the DMC will take care of turning CDCLK off/on
1049  * as needed.
1050  */
1051 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1052 {
1053         struct intel_cdclk_state cdclk_state;
1054
1055         skl_sanitize_cdclk(dev_priv);
1056
1057         if (dev_priv->cdclk.hw.cdclk != 0 &&
1058             dev_priv->cdclk.hw.vco != 0) {
1059                 /*
1060                  * Use the current vco as our initial
1061                  * guess as to what the preferred vco is.
1062                  */
1063                 if (dev_priv->skl_preferred_vco_freq == 0)
1064                         skl_set_preferred_cdclk_vco(dev_priv,
1065                                                     dev_priv->cdclk.hw.vco);
1066                 return;
1067         }
1068
1069         cdclk_state = dev_priv->cdclk.hw;
1070
1071         cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1072         if (cdclk_state.vco == 0)
1073                 cdclk_state.vco = 8100000;
1074         cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1075
1076         skl_set_cdclk(dev_priv, &cdclk_state);
1077 }
1078
1079 /**
1080  * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1081  * @dev_priv: i915 device
1082  *
1083  * Uninitialize CDCLK for SKL and derivatives. This is done only
1084  * during the display core uninitialization sequence.
1085  */
1086 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1087 {
1088         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1089
1090         cdclk_state.cdclk = cdclk_state.ref;
1091         cdclk_state.vco = 0;
1092
1093         skl_set_cdclk(dev_priv, &cdclk_state);
1094 }
1095
1096 static int bxt_calc_cdclk(int min_cdclk)
1097 {
1098         if (min_cdclk > 576000)
1099                 return 624000;
1100         else if (min_cdclk > 384000)
1101                 return 576000;
1102         else if (min_cdclk > 288000)
1103                 return 384000;
1104         else if (min_cdclk > 144000)
1105                 return 288000;
1106         else
1107                 return 144000;
1108 }
1109
1110 static int glk_calc_cdclk(int min_cdclk)
1111 {
1112         if (min_cdclk > 158400)
1113                 return 316800;
1114         else if (min_cdclk > 79200)
1115                 return 158400;
1116         else
1117                 return 79200;
1118 }
1119
1120 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1121 {
1122         int ratio;
1123
1124         if (cdclk == dev_priv->cdclk.hw.ref)
1125                 return 0;
1126
1127         switch (cdclk) {
1128         default:
1129                 MISSING_CASE(cdclk);
1130         case 144000:
1131         case 288000:
1132         case 384000:
1133         case 576000:
1134                 ratio = 60;
1135                 break;
1136         case 624000:
1137                 ratio = 65;
1138                 break;
1139         }
1140
1141         return dev_priv->cdclk.hw.ref * ratio;
1142 }
1143
1144 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1145 {
1146         int ratio;
1147
1148         if (cdclk == dev_priv->cdclk.hw.ref)
1149                 return 0;
1150
1151         switch (cdclk) {
1152         default:
1153                 MISSING_CASE(cdclk);
1154         case  79200:
1155         case 158400:
1156         case 316800:
1157                 ratio = 33;
1158                 break;
1159         }
1160
1161         return dev_priv->cdclk.hw.ref * ratio;
1162 }
1163
1164 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1165                               struct intel_cdclk_state *cdclk_state)
1166 {
1167         u32 val;
1168
1169         cdclk_state->ref = 19200;
1170         cdclk_state->vco = 0;
1171
1172         val = I915_READ(BXT_DE_PLL_ENABLE);
1173         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1174                 return;
1175
1176         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1177                 return;
1178
1179         val = I915_READ(BXT_DE_PLL_CTL);
1180         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1181 }
1182
1183 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1184                           struct intel_cdclk_state *cdclk_state)
1185 {
1186         u32 divider;
1187         int div;
1188
1189         bxt_de_pll_update(dev_priv, cdclk_state);
1190
1191         cdclk_state->cdclk = cdclk_state->ref;
1192
1193         if (cdclk_state->vco == 0)
1194                 return;
1195
1196         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1197
1198         switch (divider) {
1199         case BXT_CDCLK_CD2X_DIV_SEL_1:
1200                 div = 2;
1201                 break;
1202         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1203                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1204                 div = 3;
1205                 break;
1206         case BXT_CDCLK_CD2X_DIV_SEL_2:
1207                 div = 4;
1208                 break;
1209         case BXT_CDCLK_CD2X_DIV_SEL_4:
1210                 div = 8;
1211                 break;
1212         default:
1213                 MISSING_CASE(divider);
1214                 return;
1215         }
1216
1217         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1218 }
1219
1220 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1221 {
1222         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1223
1224         /* Timeout 200us */
1225         if (intel_wait_for_register(dev_priv,
1226                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1227                                     1))
1228                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1229
1230         dev_priv->cdclk.hw.vco = 0;
1231 }
1232
1233 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1234 {
1235         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1236         u32 val;
1237
1238         val = I915_READ(BXT_DE_PLL_CTL);
1239         val &= ~BXT_DE_PLL_RATIO_MASK;
1240         val |= BXT_DE_PLL_RATIO(ratio);
1241         I915_WRITE(BXT_DE_PLL_CTL, val);
1242
1243         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1244
1245         /* Timeout 200us */
1246         if (intel_wait_for_register(dev_priv,
1247                                     BXT_DE_PLL_ENABLE,
1248                                     BXT_DE_PLL_LOCK,
1249                                     BXT_DE_PLL_LOCK,
1250                                     1))
1251                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1252
1253         dev_priv->cdclk.hw.vco = vco;
1254 }
1255
1256 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1257                           const struct intel_cdclk_state *cdclk_state)
1258 {
1259         int cdclk = cdclk_state->cdclk;
1260         int vco = cdclk_state->vco;
1261         u32 val, divider;
1262         int ret;
1263
1264         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1265         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1266         case 8:
1267                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1268                 break;
1269         case 4:
1270                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1271                 break;
1272         case 3:
1273                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1274                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1275                 break;
1276         case 2:
1277                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1278                 break;
1279         default:
1280                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1281                 WARN_ON(vco != 0);
1282
1283                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1284                 break;
1285         }
1286
1287         /* Inform power controller of upcoming frequency change */
1288         mutex_lock(&dev_priv->pcu_lock);
1289         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1290                                       0x80000000);
1291         mutex_unlock(&dev_priv->pcu_lock);
1292
1293         if (ret) {
1294                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1295                           ret, cdclk);
1296                 return;
1297         }
1298
1299         if (dev_priv->cdclk.hw.vco != 0 &&
1300             dev_priv->cdclk.hw.vco != vco)
1301                 bxt_de_pll_disable(dev_priv);
1302
1303         if (dev_priv->cdclk.hw.vco != vco)
1304                 bxt_de_pll_enable(dev_priv, vco);
1305
1306         val = divider | skl_cdclk_decimal(cdclk);
1307         /*
1308          * FIXME if only the cd2x divider needs changing, it could be done
1309          * without shutting off the pipe (if only one pipe is active).
1310          */
1311         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1312         /*
1313          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1314          * enable otherwise.
1315          */
1316         if (cdclk >= 500000)
1317                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1318         I915_WRITE(CDCLK_CTL, val);
1319
1320         mutex_lock(&dev_priv->pcu_lock);
1321         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1322                                       DIV_ROUND_UP(cdclk, 25000));
1323         mutex_unlock(&dev_priv->pcu_lock);
1324
1325         if (ret) {
1326                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1327                           ret, cdclk);
1328                 return;
1329         }
1330
1331         intel_update_cdclk(dev_priv);
1332 }
1333
1334 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1335 {
1336         u32 cdctl, expected;
1337
1338         intel_update_cdclk(dev_priv);
1339
1340         if (dev_priv->cdclk.hw.vco == 0 ||
1341             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1342                 goto sanitize;
1343
1344         /* DPLL okay; verify the cdclock
1345          *
1346          * Some BIOS versions leave an incorrect decimal frequency value and
1347          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1348          * so sanitize this register.
1349          */
1350         cdctl = I915_READ(CDCLK_CTL);
1351         /*
1352          * Let's ignore the pipe field, since BIOS could have configured the
1353          * dividers both synching to an active pipe, or asynchronously
1354          * (PIPE_NONE).
1355          */
1356         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1357
1358         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1359                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1360         /*
1361          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1362          * enable otherwise.
1363          */
1364         if (dev_priv->cdclk.hw.cdclk >= 500000)
1365                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1366
1367         if (cdctl == expected)
1368                 /* All well; nothing to sanitize */
1369                 return;
1370
1371 sanitize:
1372         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1373
1374         /* force cdclk programming */
1375         dev_priv->cdclk.hw.cdclk = 0;
1376
1377         /* force full PLL disable + enable */
1378         dev_priv->cdclk.hw.vco = -1;
1379 }
1380
1381 /**
1382  * bxt_init_cdclk - Initialize CDCLK on BXT
1383  * @dev_priv: i915 device
1384  *
1385  * Initialize CDCLK for BXT and derivatives. This is generally
1386  * done only during the display core initialization sequence,
1387  * after which the DMC will take care of turning CDCLK off/on
1388  * as needed.
1389  */
1390 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1391 {
1392         struct intel_cdclk_state cdclk_state;
1393
1394         bxt_sanitize_cdclk(dev_priv);
1395
1396         if (dev_priv->cdclk.hw.cdclk != 0 &&
1397             dev_priv->cdclk.hw.vco != 0)
1398                 return;
1399
1400         cdclk_state = dev_priv->cdclk.hw;
1401
1402         /*
1403          * FIXME:
1404          * - The initial CDCLK needs to be read from VBT.
1405          *   Need to make this change after VBT has changes for BXT.
1406          */
1407         if (IS_GEMINILAKE(dev_priv)) {
1408                 cdclk_state.cdclk = glk_calc_cdclk(0);
1409                 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1410         } else {
1411                 cdclk_state.cdclk = bxt_calc_cdclk(0);
1412                 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1413         }
1414
1415         bxt_set_cdclk(dev_priv, &cdclk_state);
1416 }
1417
1418 /**
1419  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1420  * @dev_priv: i915 device
1421  *
1422  * Uninitialize CDCLK for BXT and derivatives. This is done only
1423  * during the display core uninitialization sequence.
1424  */
1425 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1426 {
1427         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1428
1429         cdclk_state.cdclk = cdclk_state.ref;
1430         cdclk_state.vco = 0;
1431
1432         bxt_set_cdclk(dev_priv, &cdclk_state);
1433 }
1434
1435 static int cnl_calc_cdclk(int min_cdclk)
1436 {
1437         if (min_cdclk > 336000)
1438                 return 528000;
1439         else if (min_cdclk > 168000)
1440                 return 336000;
1441         else
1442                 return 168000;
1443 }
1444
1445 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1446                                  struct intel_cdclk_state *cdclk_state)
1447 {
1448         u32 val;
1449
1450         if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1451                 cdclk_state->ref = 24000;
1452         else
1453                 cdclk_state->ref = 19200;
1454
1455         cdclk_state->vco = 0;
1456
1457         val = I915_READ(BXT_DE_PLL_ENABLE);
1458         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1459                 return;
1460
1461         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1462                 return;
1463
1464         cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1465 }
1466
1467 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1468                          struct intel_cdclk_state *cdclk_state)
1469 {
1470         u32 divider;
1471         int div;
1472
1473         cnl_cdclk_pll_update(dev_priv, cdclk_state);
1474
1475         cdclk_state->cdclk = cdclk_state->ref;
1476
1477         if (cdclk_state->vco == 0)
1478                 return;
1479
1480         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1481
1482         switch (divider) {
1483         case BXT_CDCLK_CD2X_DIV_SEL_1:
1484                 div = 2;
1485                 break;
1486         case BXT_CDCLK_CD2X_DIV_SEL_2:
1487                 div = 4;
1488                 break;
1489         default:
1490                 MISSING_CASE(divider);
1491                 return;
1492         }
1493
1494         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1495 }
1496
1497 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1498 {
1499         u32 val;
1500
1501         val = I915_READ(BXT_DE_PLL_ENABLE);
1502         val &= ~BXT_DE_PLL_PLL_ENABLE;
1503         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1504
1505         /* Timeout 200us */
1506         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1507                 DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
1508
1509         dev_priv->cdclk.hw.vco = 0;
1510 }
1511
1512 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1513 {
1514         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1515         u32 val;
1516
1517         val = CNL_CDCLK_PLL_RATIO(ratio);
1518         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1519
1520         val |= BXT_DE_PLL_PLL_ENABLE;
1521         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1522
1523         /* Timeout 200us */
1524         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1525                 DRM_ERROR("timout waiting for CDCLK PLL lock\n");
1526
1527         dev_priv->cdclk.hw.vco = vco;
1528 }
1529
1530 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1531                           const struct intel_cdclk_state *cdclk_state)
1532 {
1533         int cdclk = cdclk_state->cdclk;
1534         int vco = cdclk_state->vco;
1535         u32 val, divider, pcu_ack;
1536         int ret;
1537
1538         mutex_lock(&dev_priv->pcu_lock);
1539         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1540                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1541                                 SKL_CDCLK_READY_FOR_CHANGE,
1542                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1543         mutex_unlock(&dev_priv->pcu_lock);
1544         if (ret) {
1545                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1546                           ret);
1547                 return;
1548         }
1549
1550         /* cdclk = vco / 2 / div{1,2} */
1551         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1552         case 4:
1553                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1554                 break;
1555         case 2:
1556                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1557                 break;
1558         default:
1559                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1560                 WARN_ON(vco != 0);
1561
1562                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1563                 break;
1564         }
1565
1566         switch (cdclk) {
1567         case 528000:
1568                 pcu_ack = 2;
1569                 break;
1570         case 336000:
1571                 pcu_ack = 1;
1572                 break;
1573         case 168000:
1574         default:
1575                 pcu_ack = 0;
1576                 break;
1577         }
1578
1579         if (dev_priv->cdclk.hw.vco != 0 &&
1580             dev_priv->cdclk.hw.vco != vco)
1581                 cnl_cdclk_pll_disable(dev_priv);
1582
1583         if (dev_priv->cdclk.hw.vco != vco)
1584                 cnl_cdclk_pll_enable(dev_priv, vco);
1585
1586         val = divider | skl_cdclk_decimal(cdclk);
1587         /*
1588          * FIXME if only the cd2x divider needs changing, it could be done
1589          * without shutting off the pipe (if only one pipe is active).
1590          */
1591         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1592         I915_WRITE(CDCLK_CTL, val);
1593
1594         /* inform PCU of the change */
1595         mutex_lock(&dev_priv->pcu_lock);
1596         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
1597         mutex_unlock(&dev_priv->pcu_lock);
1598
1599         intel_update_cdclk(dev_priv);
1600 }
1601
1602 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1603 {
1604         int ratio;
1605
1606         if (cdclk == dev_priv->cdclk.hw.ref)
1607                 return 0;
1608
1609         switch (cdclk) {
1610         default:
1611                 MISSING_CASE(cdclk);
1612         case 168000:
1613         case 336000:
1614                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1615                 break;
1616         case 528000:
1617                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1618                 break;
1619         }
1620
1621         return dev_priv->cdclk.hw.ref * ratio;
1622 }
1623
1624 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1625 {
1626         u32 cdctl, expected;
1627
1628         intel_update_cdclk(dev_priv);
1629
1630         if (dev_priv->cdclk.hw.vco == 0 ||
1631             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1632                 goto sanitize;
1633
1634         /* DPLL okay; verify the cdclock
1635          *
1636          * Some BIOS versions leave an incorrect decimal frequency value and
1637          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1638          * so sanitize this register.
1639          */
1640         cdctl = I915_READ(CDCLK_CTL);
1641         /*
1642          * Let's ignore the pipe field, since BIOS could have configured the
1643          * dividers both synching to an active pipe, or asynchronously
1644          * (PIPE_NONE).
1645          */
1646         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1647
1648         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1649                    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1650
1651         if (cdctl == expected)
1652                 /* All well; nothing to sanitize */
1653                 return;
1654
1655 sanitize:
1656         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1657
1658         /* force cdclk programming */
1659         dev_priv->cdclk.hw.cdclk = 0;
1660
1661         /* force full PLL disable + enable */
1662         dev_priv->cdclk.hw.vco = -1;
1663 }
1664
1665 /**
1666  * cnl_init_cdclk - Initialize CDCLK on CNL
1667  * @dev_priv: i915 device
1668  *
1669  * Initialize CDCLK for CNL. This is generally
1670  * done only during the display core initialization sequence,
1671  * after which the DMC will take care of turning CDCLK off/on
1672  * as needed.
1673  */
1674 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1675 {
1676         struct intel_cdclk_state cdclk_state;
1677
1678         cnl_sanitize_cdclk(dev_priv);
1679
1680         if (dev_priv->cdclk.hw.cdclk != 0 &&
1681             dev_priv->cdclk.hw.vco != 0)
1682                 return;
1683
1684         cdclk_state = dev_priv->cdclk.hw;
1685
1686         cdclk_state.cdclk = cnl_calc_cdclk(0);
1687         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1688
1689         cnl_set_cdclk(dev_priv, &cdclk_state);
1690 }
1691
1692 /**
1693  * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
1694  * @dev_priv: i915 device
1695  *
1696  * Uninitialize CDCLK for CNL. This is done only
1697  * during the display core uninitialization sequence.
1698  */
1699 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
1700 {
1701         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1702
1703         cdclk_state.cdclk = cdclk_state.ref;
1704         cdclk_state.vco = 0;
1705
1706         cnl_set_cdclk(dev_priv, &cdclk_state);
1707 }
1708
1709 /**
1710  * intel_cdclk_state_compare - Determine if two CDCLK states differ
1711  * @a: first CDCLK state
1712  * @b: second CDCLK state
1713  *
1714  * Returns:
1715  * True if the CDCLK states are identical, false if they differ.
1716  */
1717 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1718                                const struct intel_cdclk_state *b)
1719 {
1720         return memcmp(a, b, sizeof(*a)) == 0;
1721 }
1722
1723 /**
1724  * intel_set_cdclk - Push the CDCLK state to the hardware
1725  * @dev_priv: i915 device
1726  * @cdclk_state: new CDCLK state
1727  *
1728  * Program the hardware based on the passed in CDCLK state,
1729  * if necessary.
1730  */
1731 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1732                      const struct intel_cdclk_state *cdclk_state)
1733 {
1734         if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state))
1735                 return;
1736
1737         if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
1738                 return;
1739
1740         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n",
1741                          cdclk_state->cdclk, cdclk_state->vco,
1742                          cdclk_state->ref);
1743
1744         dev_priv->display.set_cdclk(dev_priv, cdclk_state);
1745 }
1746
1747 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
1748                                      int pixel_rate)
1749 {
1750         if (INTEL_GEN(dev_priv) >= 10)
1751                 /*
1752                  * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
1753                  * once DDI clock voltage requirements are
1754                  * handled correctly.
1755                  */
1756                 return pixel_rate;
1757         else if (IS_GEMINILAKE(dev_priv))
1758                 /*
1759                  * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1760                  * as a temporary workaround. Use a higher cdclk instead. (Note that
1761                  * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1762                  * cdclk.)
1763                  */
1764                 return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
1765         else if (IS_GEN9(dev_priv) ||
1766                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1767                 return pixel_rate;
1768         else if (IS_CHERRYVIEW(dev_priv))
1769                 return DIV_ROUND_UP(pixel_rate * 100, 95);
1770         else
1771                 return DIV_ROUND_UP(pixel_rate * 100, 90);
1772 }
1773
1774 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
1775 {
1776         struct drm_i915_private *dev_priv =
1777                 to_i915(crtc_state->base.crtc->dev);
1778         int min_cdclk;
1779
1780         if (!crtc_state->base.enable)
1781                 return 0;
1782
1783         min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
1784
1785         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1786         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
1787                 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
1788
1789         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1790          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1791          * there may be audio corruption or screen corruption." This cdclk
1792          * restriction for GLK is 316.8 MHz.
1793          */
1794         if (intel_crtc_has_dp_encoder(crtc_state) &&
1795             crtc_state->has_audio &&
1796             crtc_state->port_clock >= 540000 &&
1797             crtc_state->lane_count == 4) {
1798                 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1799                         /* Display WA #1145: glk,cnl */
1800                         min_cdclk = max(316800, min_cdclk);
1801                 } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
1802                         /* Display WA #1144: skl,bxt */
1803                         min_cdclk = max(432000, min_cdclk);
1804                 }
1805         }
1806
1807         /* According to BSpec, "The CD clock frequency must be at least twice
1808          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1809          */
1810         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
1811                 min_cdclk = max(2 * 96000, min_cdclk);
1812
1813         if (min_cdclk > dev_priv->max_cdclk_freq) {
1814                 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
1815                               min_cdclk, dev_priv->max_cdclk_freq);
1816                 return -EINVAL;
1817         }
1818
1819         return min_cdclk;
1820 }
1821
1822 static int intel_compute_min_cdclk(struct drm_atomic_state *state)
1823 {
1824         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1825         struct drm_i915_private *dev_priv = to_i915(state->dev);
1826         struct intel_crtc *crtc;
1827         struct intel_crtc_state *crtc_state;
1828         int min_cdclk, i;
1829         enum pipe pipe;
1830
1831         memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
1832                sizeof(intel_state->min_cdclk));
1833
1834         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
1835                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
1836                 if (min_cdclk < 0)
1837                         return min_cdclk;
1838
1839                 intel_state->min_cdclk[i] = min_cdclk;
1840         }
1841
1842         min_cdclk = 0;
1843         for_each_pipe(dev_priv, pipe)
1844                 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
1845
1846         return min_cdclk;
1847 }
1848
1849 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1850 {
1851         struct drm_i915_private *dev_priv = to_i915(state->dev);
1852         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1853         int min_cdclk, cdclk;
1854
1855         min_cdclk = intel_compute_min_cdclk(state);
1856         if (min_cdclk < 0)
1857                 return min_cdclk;
1858
1859         cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
1860
1861         intel_state->cdclk.logical.cdclk = cdclk;
1862
1863         if (!intel_state->active_crtcs) {
1864                 cdclk = vlv_calc_cdclk(dev_priv, 0);
1865
1866                 intel_state->cdclk.actual.cdclk = cdclk;
1867         } else {
1868                 intel_state->cdclk.actual =
1869                         intel_state->cdclk.logical;
1870         }
1871
1872         return 0;
1873 }
1874
1875 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1876 {
1877         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1878         int min_cdclk, cdclk;
1879
1880         min_cdclk = intel_compute_min_cdclk(state);
1881         if (min_cdclk < 0)
1882                 return min_cdclk;
1883
1884         /*
1885          * FIXME should also account for plane ratio
1886          * once 64bpp pixel formats are supported.
1887          */
1888         cdclk = bdw_calc_cdclk(min_cdclk);
1889
1890         intel_state->cdclk.logical.cdclk = cdclk;
1891
1892         if (!intel_state->active_crtcs) {
1893                 cdclk = bdw_calc_cdclk(0);
1894
1895                 intel_state->cdclk.actual.cdclk = cdclk;
1896         } else {
1897                 intel_state->cdclk.actual =
1898                         intel_state->cdclk.logical;
1899         }
1900
1901         return 0;
1902 }
1903
1904 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1905 {
1906         struct drm_i915_private *dev_priv = to_i915(state->dev);
1907         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1908         int min_cdclk, cdclk, vco;
1909
1910         min_cdclk = intel_compute_min_cdclk(state);
1911         if (min_cdclk < 0)
1912                 return min_cdclk;
1913
1914         vco = intel_state->cdclk.logical.vco;
1915         if (!vco)
1916                 vco = dev_priv->skl_preferred_vco_freq;
1917
1918         /*
1919          * FIXME should also account for plane ratio
1920          * once 64bpp pixel formats are supported.
1921          */
1922         cdclk = skl_calc_cdclk(min_cdclk, vco);
1923
1924         intel_state->cdclk.logical.vco = vco;
1925         intel_state->cdclk.logical.cdclk = cdclk;
1926
1927         if (!intel_state->active_crtcs) {
1928                 cdclk = skl_calc_cdclk(0, vco);
1929
1930                 intel_state->cdclk.actual.vco = vco;
1931                 intel_state->cdclk.actual.cdclk = cdclk;
1932         } else {
1933                 intel_state->cdclk.actual =
1934                         intel_state->cdclk.logical;
1935         }
1936
1937         return 0;
1938 }
1939
1940 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1941 {
1942         struct drm_i915_private *dev_priv = to_i915(state->dev);
1943         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1944         int min_cdclk, cdclk, vco;
1945
1946         min_cdclk = intel_compute_min_cdclk(state);
1947         if (min_cdclk < 0)
1948                 return min_cdclk;
1949
1950         if (IS_GEMINILAKE(dev_priv)) {
1951                 cdclk = glk_calc_cdclk(min_cdclk);
1952                 vco = glk_de_pll_vco(dev_priv, cdclk);
1953         } else {
1954                 cdclk = bxt_calc_cdclk(min_cdclk);
1955                 vco = bxt_de_pll_vco(dev_priv, cdclk);
1956         }
1957
1958         intel_state->cdclk.logical.vco = vco;
1959         intel_state->cdclk.logical.cdclk = cdclk;
1960
1961         if (!intel_state->active_crtcs) {
1962                 if (IS_GEMINILAKE(dev_priv)) {
1963                         cdclk = glk_calc_cdclk(0);
1964                         vco = glk_de_pll_vco(dev_priv, cdclk);
1965                 } else {
1966                         cdclk = bxt_calc_cdclk(0);
1967                         vco = bxt_de_pll_vco(dev_priv, cdclk);
1968                 }
1969
1970                 intel_state->cdclk.actual.vco = vco;
1971                 intel_state->cdclk.actual.cdclk = cdclk;
1972         } else {
1973                 intel_state->cdclk.actual =
1974                         intel_state->cdclk.logical;
1975         }
1976
1977         return 0;
1978 }
1979
1980 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
1981 {
1982         struct drm_i915_private *dev_priv = to_i915(state->dev);
1983         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1984         int min_cdclk, cdclk, vco;
1985
1986         min_cdclk = intel_compute_min_cdclk(state);
1987         if (min_cdclk < 0)
1988                 return min_cdclk;
1989
1990         cdclk = cnl_calc_cdclk(min_cdclk);
1991         vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
1992
1993         intel_state->cdclk.logical.vco = vco;
1994         intel_state->cdclk.logical.cdclk = cdclk;
1995
1996         if (!intel_state->active_crtcs) {
1997                 cdclk = cnl_calc_cdclk(0);
1998                 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
1999
2000                 intel_state->cdclk.actual.vco = vco;
2001                 intel_state->cdclk.actual.cdclk = cdclk;
2002         } else {
2003                 intel_state->cdclk.actual =
2004                         intel_state->cdclk.logical;
2005         }
2006
2007         return 0;
2008 }
2009
2010 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2011 {
2012         int max_cdclk_freq = dev_priv->max_cdclk_freq;
2013
2014         if (INTEL_GEN(dev_priv) >= 10)
2015                 /*
2016                  * FIXME: Allow '2 * max_cdclk_freq'
2017                  * once DDI clock voltage requirements are
2018                  * handled correctly.
2019                  */
2020                 return max_cdclk_freq;
2021         else if (IS_GEMINILAKE(dev_priv))
2022                 /*
2023                  * FIXME: Limiting to 99% as a temporary workaround. See
2024                  * intel_min_cdclk() for details.
2025                  */
2026                 return 2 * max_cdclk_freq * 99 / 100;
2027         else if (IS_GEN9(dev_priv) ||
2028                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2029                 return max_cdclk_freq;
2030         else if (IS_CHERRYVIEW(dev_priv))
2031                 return max_cdclk_freq*95/100;
2032         else if (INTEL_INFO(dev_priv)->gen < 4)
2033                 return 2*max_cdclk_freq*90/100;
2034         else
2035                 return max_cdclk_freq*90/100;
2036 }
2037
2038 /**
2039  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2040  * @dev_priv: i915 device
2041  *
2042  * Determine the maximum CDCLK frequency the platform supports, and also
2043  * derive the maximum dot clock frequency the maximum CDCLK frequency
2044  * allows.
2045  */
2046 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2047 {
2048         if (IS_CANNONLAKE(dev_priv)) {
2049                 dev_priv->max_cdclk_freq = 528000;
2050         } else if (IS_GEN9_BC(dev_priv)) {
2051                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2052                 int max_cdclk, vco;
2053
2054                 vco = dev_priv->skl_preferred_vco_freq;
2055                 WARN_ON(vco != 8100000 && vco != 8640000);
2056
2057                 /*
2058                  * Use the lower (vco 8640) cdclk values as a
2059                  * first guess. skl_calc_cdclk() will correct it
2060                  * if the preferred vco is 8100 instead.
2061                  */
2062                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2063                         max_cdclk = 617143;
2064                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2065                         max_cdclk = 540000;
2066                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2067                         max_cdclk = 432000;
2068                 else
2069                         max_cdclk = 308571;
2070
2071                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2072         } else if (IS_GEMINILAKE(dev_priv)) {
2073                 dev_priv->max_cdclk_freq = 316800;
2074         } else if (IS_BROXTON(dev_priv)) {
2075                 dev_priv->max_cdclk_freq = 624000;
2076         } else if (IS_BROADWELL(dev_priv))  {
2077                 /*
2078                  * FIXME with extra cooling we can allow
2079                  * 540 MHz for ULX and 675 Mhz for ULT.
2080                  * How can we know if extra cooling is
2081                  * available? PCI ID, VTB, something else?
2082                  */
2083                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2084                         dev_priv->max_cdclk_freq = 450000;
2085                 else if (IS_BDW_ULX(dev_priv))
2086                         dev_priv->max_cdclk_freq = 450000;
2087                 else if (IS_BDW_ULT(dev_priv))
2088                         dev_priv->max_cdclk_freq = 540000;
2089                 else
2090                         dev_priv->max_cdclk_freq = 675000;
2091         } else if (IS_CHERRYVIEW(dev_priv)) {
2092                 dev_priv->max_cdclk_freq = 320000;
2093         } else if (IS_VALLEYVIEW(dev_priv)) {
2094                 dev_priv->max_cdclk_freq = 400000;
2095         } else {
2096                 /* otherwise assume cdclk is fixed */
2097                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2098         }
2099
2100         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2101
2102         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2103                          dev_priv->max_cdclk_freq);
2104
2105         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2106                          dev_priv->max_dotclk_freq);
2107 }
2108
2109 /**
2110  * intel_update_cdclk - Determine the current CDCLK frequency
2111  * @dev_priv: i915 device
2112  *
2113  * Determine the current CDCLK frequency.
2114  */
2115 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2116 {
2117         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2118
2119         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
2120                          dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
2121                          dev_priv->cdclk.hw.ref);
2122
2123         /*
2124          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2125          * Programmng [sic] note: bit[9:2] should be programmed to the number
2126          * of cdclk that generates 4MHz reference clock freq which is used to
2127          * generate GMBus clock. This will vary with the cdclk freq.
2128          */
2129         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2130                 I915_WRITE(GMBUSFREQ_VLV,
2131                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2132 }
2133
2134 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2135 {
2136         u32 rawclk;
2137         int divider, fraction;
2138
2139         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2140                 /* 24 MHz */
2141                 divider = 24000;
2142                 fraction = 0;
2143         } else {
2144                 /* 19.2 MHz */
2145                 divider = 19000;
2146                 fraction = 200;
2147         }
2148
2149         rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2150         if (fraction)
2151                 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2152                                                             fraction) - 1);
2153
2154         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2155         return divider + fraction;
2156 }
2157
2158 static int pch_rawclk(struct drm_i915_private *dev_priv)
2159 {
2160         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2161 }
2162
2163 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2164 {
2165         /* RAWCLK_FREQ_VLV register updated from power well code */
2166         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2167                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
2168 }
2169
2170 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2171 {
2172         uint32_t clkcfg;
2173
2174         /* hrawclock is 1/4 the FSB frequency */
2175         clkcfg = I915_READ(CLKCFG);
2176         switch (clkcfg & CLKCFG_FSB_MASK) {
2177         case CLKCFG_FSB_400:
2178                 return 100000;
2179         case CLKCFG_FSB_533:
2180                 return 133333;
2181         case CLKCFG_FSB_667:
2182                 return 166667;
2183         case CLKCFG_FSB_800:
2184                 return 200000;
2185         case CLKCFG_FSB_1067:
2186         case CLKCFG_FSB_1067_ALT:
2187                 return 266667;
2188         case CLKCFG_FSB_1333:
2189         case CLKCFG_FSB_1333_ALT:
2190                 return 333333;
2191         default:
2192                 return 133333;
2193         }
2194 }
2195
2196 /**
2197  * intel_update_rawclk - Determine the current RAWCLK frequency
2198  * @dev_priv: i915 device
2199  *
2200  * Determine the current RAWCLK frequency. RAWCLK is a fixed
2201  * frequency clock so this needs to done only once.
2202  */
2203 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2204 {
2205
2206         if (HAS_PCH_CNP(dev_priv))
2207                 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2208         else if (HAS_PCH_SPLIT(dev_priv))
2209                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2210         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2211                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2212         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2213                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2214         else
2215                 /* no rawclk on other platforms, or no need to know it */
2216                 return;
2217
2218         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2219 }
2220
2221 /**
2222  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2223  * @dev_priv: i915 device
2224  */
2225 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2226 {
2227         if (IS_CHERRYVIEW(dev_priv)) {
2228                 dev_priv->display.set_cdclk = chv_set_cdclk;
2229                 dev_priv->display.modeset_calc_cdclk =
2230                         vlv_modeset_calc_cdclk;
2231         } else if (IS_VALLEYVIEW(dev_priv)) {
2232                 dev_priv->display.set_cdclk = vlv_set_cdclk;
2233                 dev_priv->display.modeset_calc_cdclk =
2234                         vlv_modeset_calc_cdclk;
2235         } else if (IS_BROADWELL(dev_priv)) {
2236                 dev_priv->display.set_cdclk = bdw_set_cdclk;
2237                 dev_priv->display.modeset_calc_cdclk =
2238                         bdw_modeset_calc_cdclk;
2239         } else if (IS_GEN9_LP(dev_priv)) {
2240                 dev_priv->display.set_cdclk = bxt_set_cdclk;
2241                 dev_priv->display.modeset_calc_cdclk =
2242                         bxt_modeset_calc_cdclk;
2243         } else if (IS_GEN9_BC(dev_priv)) {
2244                 dev_priv->display.set_cdclk = skl_set_cdclk;
2245                 dev_priv->display.modeset_calc_cdclk =
2246                         skl_modeset_calc_cdclk;
2247         } else if (IS_CANNONLAKE(dev_priv)) {
2248                 dev_priv->display.set_cdclk = cnl_set_cdclk;
2249                 dev_priv->display.modeset_calc_cdclk =
2250                         cnl_modeset_calc_cdclk;
2251         }
2252
2253         if (IS_CANNONLAKE(dev_priv))
2254                 dev_priv->display.get_cdclk = cnl_get_cdclk;
2255         else if (IS_GEN9_BC(dev_priv))
2256                 dev_priv->display.get_cdclk = skl_get_cdclk;
2257         else if (IS_GEN9_LP(dev_priv))
2258                 dev_priv->display.get_cdclk = bxt_get_cdclk;
2259         else if (IS_BROADWELL(dev_priv))
2260                 dev_priv->display.get_cdclk = bdw_get_cdclk;
2261         else if (IS_HASWELL(dev_priv))
2262                 dev_priv->display.get_cdclk = hsw_get_cdclk;
2263         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2264                 dev_priv->display.get_cdclk = vlv_get_cdclk;
2265         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2266                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2267         else if (IS_GEN5(dev_priv))
2268                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2269         else if (IS_GM45(dev_priv))
2270                 dev_priv->display.get_cdclk = gm45_get_cdclk;
2271         else if (IS_G45(dev_priv))
2272                 dev_priv->display.get_cdclk = g33_get_cdclk;
2273         else if (IS_I965GM(dev_priv))
2274                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2275         else if (IS_I965G(dev_priv))
2276                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2277         else if (IS_PINEVIEW(dev_priv))
2278                 dev_priv->display.get_cdclk = pnv_get_cdclk;
2279         else if (IS_G33(dev_priv))
2280                 dev_priv->display.get_cdclk = g33_get_cdclk;
2281         else if (IS_I945GM(dev_priv))
2282                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2283         else if (IS_I945G(dev_priv))
2284                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2285         else if (IS_I915GM(dev_priv))
2286                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2287         else if (IS_I915G(dev_priv))
2288                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2289         else if (IS_I865G(dev_priv))
2290                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2291         else if (IS_I85X(dev_priv))
2292                 dev_priv->display.get_cdclk = i85x_get_cdclk;
2293         else if (IS_I845G(dev_priv))
2294                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2295         else { /* 830 */
2296                 WARN(!IS_I830(dev_priv),
2297                      "Unknown platform. Assuming 133 MHz CDCLK\n");
2298                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2299         }
2300 }