2 * Copyright © 2006-2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_drv.h"
29 * The display engine uses several different clocks to do its work. There
30 * are two main clocks involved that aren't directly related to the actual
31 * pixel clock or any symbol/bit clock of the actual output port. These
32 * are the core display clock (CDCLK) and RAWCLK.
34 * CDCLK clocks most of the display pipe logic, and thus its frequency
35 * must be high enough to support the rate at which pixels are flowing
36 * through the pipes. Downscaling must also be accounted as that increases
37 * the effective pixel rate.
39 * On several platforms the CDCLK frequency can be changed dynamically
40 * to minimize power consumption for a given display configuration.
41 * Typically changes to the CDCLK frequency require all the display pipes
42 * to be shut down while the frequency is being changed.
44 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
45 * DMC will not change the active CDCLK frequency however, so that part
46 * will still be performed by the driver directly.
48 * RAWCLK is a fixed frequency clock, often used by various auxiliary
49 * blocks such as AUX CH or backlight PWM. Hence the only thing we
50 * really need to know about RAWCLK is its frequency so that various
51 * dividers can be programmed correctly.
54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
55 struct intel_cdclk_state *cdclk_state)
57 cdclk_state->cdclk = 133333;
60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
61 struct intel_cdclk_state *cdclk_state)
63 cdclk_state->cdclk = 200000;
66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
67 struct intel_cdclk_state *cdclk_state)
69 cdclk_state->cdclk = 266667;
72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
73 struct intel_cdclk_state *cdclk_state)
75 cdclk_state->cdclk = 333333;
78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
79 struct intel_cdclk_state *cdclk_state)
81 cdclk_state->cdclk = 400000;
84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
85 struct intel_cdclk_state *cdclk_state)
87 cdclk_state->cdclk = 450000;
90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
91 struct intel_cdclk_state *cdclk_state)
93 struct pci_dev *pdev = dev_priv->drm.pdev;
97 * 852GM/852GMV only supports 133 MHz and the HPLLCC
98 * encoding is different :(
99 * FIXME is this the right way to detect 852GM/852GMV?
101 if (pdev->revision == 0x1) {
102 cdclk_state->cdclk = 133333;
106 pci_bus_read_config_word(pdev->bus,
107 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
109 /* Assume that the hardware is in the high speed state. This
110 * should be the default.
112 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
113 case GC_CLOCK_133_200:
114 case GC_CLOCK_133_200_2:
115 case GC_CLOCK_100_200:
116 cdclk_state->cdclk = 200000;
118 case GC_CLOCK_166_250:
119 cdclk_state->cdclk = 250000;
121 case GC_CLOCK_100_133:
122 cdclk_state->cdclk = 133333;
124 case GC_CLOCK_133_266:
125 case GC_CLOCK_133_266_2:
126 case GC_CLOCK_166_266:
127 cdclk_state->cdclk = 266667;
132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
133 struct intel_cdclk_state *cdclk_state)
135 struct pci_dev *pdev = dev_priv->drm.pdev;
138 pci_read_config_word(pdev, GCFGC, &gcfgc);
140 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
141 cdclk_state->cdclk = 133333;
145 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
146 case GC_DISPLAY_CLOCK_333_320_MHZ:
147 cdclk_state->cdclk = 333333;
150 case GC_DISPLAY_CLOCK_190_200_MHZ:
151 cdclk_state->cdclk = 190000;
156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
157 struct intel_cdclk_state *cdclk_state)
159 struct pci_dev *pdev = dev_priv->drm.pdev;
162 pci_read_config_word(pdev, GCFGC, &gcfgc);
164 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
165 cdclk_state->cdclk = 133333;
169 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
170 case GC_DISPLAY_CLOCK_333_320_MHZ:
171 cdclk_state->cdclk = 320000;
174 case GC_DISPLAY_CLOCK_190_200_MHZ:
175 cdclk_state->cdclk = 200000;
180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
182 static const unsigned int blb_vco[8] = {
189 static const unsigned int pnv_vco[8] = {
196 static const unsigned int cl_vco[8] = {
205 static const unsigned int elk_vco[8] = {
211 static const unsigned int ctg_vco[8] = {
219 const unsigned int *vco_table;
223 /* FIXME other chipsets? */
224 if (IS_GM45(dev_priv))
226 else if (IS_G45(dev_priv))
228 else if (IS_I965GM(dev_priv))
230 else if (IS_PINEVIEW(dev_priv))
232 else if (IS_G33(dev_priv))
237 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
239 vco = vco_table[tmp & 0x7];
241 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
243 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
249 struct intel_cdclk_state *cdclk_state)
251 struct pci_dev *pdev = dev_priv->drm.pdev;
252 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
253 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
254 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
255 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
256 const uint8_t *div_table;
257 unsigned int cdclk_sel;
260 cdclk_state->vco = intel_hpll_vco(dev_priv);
262 pci_read_config_word(pdev, GCFGC, &tmp);
264 cdclk_sel = (tmp >> 4) & 0x7;
266 if (cdclk_sel >= ARRAY_SIZE(div_3200))
269 switch (cdclk_state->vco) {
271 div_table = div_3200;
274 div_table = div_4000;
277 div_table = div_4800;
280 div_table = div_5333;
286 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
287 div_table[cdclk_sel]);
291 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
292 cdclk_state->vco, tmp);
293 cdclk_state->cdclk = 190476;
296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
297 struct intel_cdclk_state *cdclk_state)
299 struct pci_dev *pdev = dev_priv->drm.pdev;
302 pci_read_config_word(pdev, GCFGC, &gcfgc);
304 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
305 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
306 cdclk_state->cdclk = 266667;
308 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
309 cdclk_state->cdclk = 333333;
311 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
312 cdclk_state->cdclk = 444444;
314 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
315 cdclk_state->cdclk = 200000;
318 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
319 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
320 cdclk_state->cdclk = 133333;
322 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
323 cdclk_state->cdclk = 166667;
328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
329 struct intel_cdclk_state *cdclk_state)
331 struct pci_dev *pdev = dev_priv->drm.pdev;
332 static const uint8_t div_3200[] = { 16, 10, 8 };
333 static const uint8_t div_4000[] = { 20, 12, 10 };
334 static const uint8_t div_5333[] = { 24, 16, 14 };
335 const uint8_t *div_table;
336 unsigned int cdclk_sel;
339 cdclk_state->vco = intel_hpll_vco(dev_priv);
341 pci_read_config_word(pdev, GCFGC, &tmp);
343 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
345 if (cdclk_sel >= ARRAY_SIZE(div_3200))
348 switch (cdclk_state->vco) {
350 div_table = div_3200;
353 div_table = div_4000;
356 div_table = div_5333;
362 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
363 div_table[cdclk_sel]);
367 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
368 cdclk_state->vco, tmp);
369 cdclk_state->cdclk = 200000;
372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
373 struct intel_cdclk_state *cdclk_state)
375 struct pci_dev *pdev = dev_priv->drm.pdev;
376 unsigned int cdclk_sel;
379 cdclk_state->vco = intel_hpll_vco(dev_priv);
381 pci_read_config_word(pdev, GCFGC, &tmp);
383 cdclk_sel = (tmp >> 12) & 0x1;
385 switch (cdclk_state->vco) {
389 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
392 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
395 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
396 cdclk_state->vco, tmp);
397 cdclk_state->cdclk = 222222;
402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
403 struct intel_cdclk_state *cdclk_state)
405 uint32_t lcpll = I915_READ(LCPLL_CTL);
406 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
408 if (lcpll & LCPLL_CD_SOURCE_FCLK)
409 cdclk_state->cdclk = 800000;
410 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
411 cdclk_state->cdclk = 450000;
412 else if (freq == LCPLL_CLK_FREQ_450)
413 cdclk_state->cdclk = 450000;
414 else if (IS_HSW_ULT(dev_priv))
415 cdclk_state->cdclk = 337500;
417 cdclk_state->cdclk = 540000;
420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
422 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
426 * We seem to get an unstable or solid color picture at 200MHz.
427 * Not sure what's wrong. For now use 200MHz only when all pipes
430 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
432 else if (min_cdclk > 266667)
434 else if (min_cdclk > 0)
440 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
441 struct intel_cdclk_state *cdclk_state)
443 cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
444 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
445 CCK_DISPLAY_CLOCK_CONTROL,
449 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
451 unsigned int credits, default_credits;
453 if (IS_CHERRYVIEW(dev_priv))
454 default_credits = PFI_CREDIT(12);
456 default_credits = PFI_CREDIT(8);
458 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
459 /* CHV suggested value is 31 or 63 */
460 if (IS_CHERRYVIEW(dev_priv))
461 credits = PFI_CREDIT_63;
463 credits = PFI_CREDIT(15);
465 credits = default_credits;
469 * WA - write default credits before re-programming
470 * FIXME: should we also set the resend bit here?
472 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
475 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
476 credits | PFI_CREDIT_RESEND);
479 * FIXME is this guaranteed to clear
480 * immediately or should we poll for it?
482 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
485 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
486 const struct intel_cdclk_state *cdclk_state)
488 int cdclk = cdclk_state->cdclk;
491 /* There are cases where we can end up here with power domains
492 * off and a CDCLK frequency other than the minimum, like when
493 * issuing a modeset without actually changing any display after
494 * a system suspend. So grab the PIPE-A domain, which covers
495 * the HW blocks needed for the following programming.
497 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
499 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
501 else if (cdclk == 266667)
506 mutex_lock(&dev_priv->pcu_lock);
507 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
508 val &= ~DSPFREQGUAR_MASK;
509 val |= (cmd << DSPFREQGUAR_SHIFT);
510 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
511 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
512 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
514 DRM_ERROR("timed out waiting for CDclk change\n");
516 mutex_unlock(&dev_priv->pcu_lock);
518 mutex_lock(&dev_priv->sb_lock);
520 if (cdclk == 400000) {
523 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
526 /* adjust cdclk divider */
527 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
528 val &= ~CCK_FREQUENCY_VALUES;
530 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
532 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
533 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
535 DRM_ERROR("timed out waiting for CDclk change\n");
538 /* adjust self-refresh exit latency value */
539 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
543 * For high bandwidth configs, we set a higher latency in the bunit
544 * so that the core display fetch happens in time to avoid underruns.
547 val |= 4500 / 250; /* 4.5 usec */
549 val |= 3000 / 250; /* 3.0 usec */
550 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
552 mutex_unlock(&dev_priv->sb_lock);
554 intel_update_cdclk(dev_priv);
556 vlv_program_pfi_credits(dev_priv);
558 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
561 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
562 const struct intel_cdclk_state *cdclk_state)
564 int cdclk = cdclk_state->cdclk;
578 /* There are cases where we can end up here with power domains
579 * off and a CDCLK frequency other than the minimum, like when
580 * issuing a modeset without actually changing any display after
581 * a system suspend. So grab the PIPE-A domain, which covers
582 * the HW blocks needed for the following programming.
584 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
587 * Specs are full of misinformation, but testing on actual
588 * hardware has shown that we just need to write the desired
589 * CCK divider into the Punit register.
591 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
593 mutex_lock(&dev_priv->pcu_lock);
594 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
595 val &= ~DSPFREQGUAR_MASK_CHV;
596 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
597 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
598 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
599 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
601 DRM_ERROR("timed out waiting for CDclk change\n");
603 mutex_unlock(&dev_priv->pcu_lock);
605 intel_update_cdclk(dev_priv);
607 vlv_program_pfi_credits(dev_priv);
609 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
612 static int bdw_calc_cdclk(int min_cdclk)
614 if (min_cdclk > 540000)
616 else if (min_cdclk > 450000)
618 else if (min_cdclk > 337500)
624 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
625 struct intel_cdclk_state *cdclk_state)
627 uint32_t lcpll = I915_READ(LCPLL_CTL);
628 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
630 if (lcpll & LCPLL_CD_SOURCE_FCLK)
631 cdclk_state->cdclk = 800000;
632 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
633 cdclk_state->cdclk = 450000;
634 else if (freq == LCPLL_CLK_FREQ_450)
635 cdclk_state->cdclk = 450000;
636 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
637 cdclk_state->cdclk = 540000;
638 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
639 cdclk_state->cdclk = 337500;
641 cdclk_state->cdclk = 675000;
644 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
645 const struct intel_cdclk_state *cdclk_state)
647 int cdclk = cdclk_state->cdclk;
651 if (WARN((I915_READ(LCPLL_CTL) &
652 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
653 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
654 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
655 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
656 "trying to change cdclk frequency with cdclk not enabled\n"))
659 mutex_lock(&dev_priv->pcu_lock);
660 ret = sandybridge_pcode_write(dev_priv,
661 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
662 mutex_unlock(&dev_priv->pcu_lock);
664 DRM_ERROR("failed to inform pcode about cdclk change\n");
668 val = I915_READ(LCPLL_CTL);
669 val |= LCPLL_CD_SOURCE_FCLK;
670 I915_WRITE(LCPLL_CTL, val);
673 * According to the spec, it should be enough to poll for this 1 us.
674 * However, extensive testing shows that this can take longer.
676 if (wait_for_us(I915_READ(LCPLL_CTL) &
677 LCPLL_CD_SOURCE_FCLK_DONE, 100))
678 DRM_ERROR("Switching to FCLK failed\n");
680 val = I915_READ(LCPLL_CTL);
681 val &= ~LCPLL_CLK_FREQ_MASK;
685 val |= LCPLL_CLK_FREQ_450;
689 val |= LCPLL_CLK_FREQ_54O_BDW;
693 val |= LCPLL_CLK_FREQ_337_5_BDW;
697 val |= LCPLL_CLK_FREQ_675_BDW;
701 WARN(1, "invalid cdclk frequency\n");
705 I915_WRITE(LCPLL_CTL, val);
707 val = I915_READ(LCPLL_CTL);
708 val &= ~LCPLL_CD_SOURCE_FCLK;
709 I915_WRITE(LCPLL_CTL, val);
711 if (wait_for_us((I915_READ(LCPLL_CTL) &
712 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
713 DRM_ERROR("Switching back to LCPLL failed\n");
715 mutex_lock(&dev_priv->pcu_lock);
716 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
717 mutex_unlock(&dev_priv->pcu_lock);
719 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
721 intel_update_cdclk(dev_priv);
723 WARN(cdclk != dev_priv->cdclk.hw.cdclk,
724 "cdclk requested %d kHz but got %d kHz\n",
725 cdclk, dev_priv->cdclk.hw.cdclk);
728 static int skl_calc_cdclk(int min_cdclk, int vco)
730 if (vco == 8640000) {
731 if (min_cdclk > 540000)
733 else if (min_cdclk > 432000)
735 else if (min_cdclk > 308571)
740 if (min_cdclk > 540000)
742 else if (min_cdclk > 450000)
744 else if (min_cdclk > 337500)
751 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
752 struct intel_cdclk_state *cdclk_state)
756 cdclk_state->ref = 24000;
757 cdclk_state->vco = 0;
759 val = I915_READ(LCPLL1_CTL);
760 if ((val & LCPLL_PLL_ENABLE) == 0)
763 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
766 val = I915_READ(DPLL_CTRL1);
768 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
769 DPLL_CTRL1_SSC(SKL_DPLL0) |
770 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
771 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
774 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
775 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
776 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
777 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
778 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
779 cdclk_state->vco = 8100000;
781 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
782 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
783 cdclk_state->vco = 8640000;
786 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
791 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
792 struct intel_cdclk_state *cdclk_state)
796 skl_dpll0_update(dev_priv, cdclk_state);
798 cdclk_state->cdclk = cdclk_state->ref;
800 if (cdclk_state->vco == 0)
803 cdctl = I915_READ(CDCLK_CTL);
805 if (cdclk_state->vco == 8640000) {
806 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
807 case CDCLK_FREQ_450_432:
808 cdclk_state->cdclk = 432000;
810 case CDCLK_FREQ_337_308:
811 cdclk_state->cdclk = 308571;
814 cdclk_state->cdclk = 540000;
816 case CDCLK_FREQ_675_617:
817 cdclk_state->cdclk = 617143;
820 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
824 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
825 case CDCLK_FREQ_450_432:
826 cdclk_state->cdclk = 450000;
828 case CDCLK_FREQ_337_308:
829 cdclk_state->cdclk = 337500;
832 cdclk_state->cdclk = 540000;
834 case CDCLK_FREQ_675_617:
835 cdclk_state->cdclk = 675000;
838 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
844 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
845 static int skl_cdclk_decimal(int cdclk)
847 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
850 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
853 bool changed = dev_priv->skl_preferred_vco_freq != vco;
855 dev_priv->skl_preferred_vco_freq = vco;
858 intel_update_max_cdclk(dev_priv);
861 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
865 WARN_ON(vco != 8100000 && vco != 8640000);
868 * We always enable DPLL0 with the lowest link rate possible, but still
869 * taking into account the VCO required to operate the eDP panel at the
870 * desired frequency. The usual DP link rates operate with a VCO of
871 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
872 * The modeset code is responsible for the selection of the exact link
873 * rate later on, with the constraint of choosing a frequency that
876 val = I915_READ(DPLL_CTRL1);
878 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
879 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
880 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
882 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
885 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
888 I915_WRITE(DPLL_CTRL1, val);
889 POSTING_READ(DPLL_CTRL1);
891 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
893 if (intel_wait_for_register(dev_priv,
894 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
896 DRM_ERROR("DPLL0 not locked\n");
898 dev_priv->cdclk.hw.vco = vco;
900 /* We'll want to keep using the current vco from now on. */
901 skl_set_preferred_cdclk_vco(dev_priv, vco);
904 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
906 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
907 if (intel_wait_for_register(dev_priv,
908 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
910 DRM_ERROR("Couldn't disable DPLL0\n");
912 dev_priv->cdclk.hw.vco = 0;
915 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
916 const struct intel_cdclk_state *cdclk_state)
918 int cdclk = cdclk_state->cdclk;
919 int vco = cdclk_state->vco;
920 u32 freq_select, pcu_ack, cdclk_ctl;
923 WARN_ON((cdclk == 24000) != (vco == 0));
925 mutex_lock(&dev_priv->pcu_lock);
926 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
927 SKL_CDCLK_PREPARE_FOR_CHANGE,
928 SKL_CDCLK_READY_FOR_CHANGE,
929 SKL_CDCLK_READY_FOR_CHANGE, 3);
930 mutex_unlock(&dev_priv->pcu_lock);
932 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
937 /* Choose frequency for this cdclk */
941 freq_select = CDCLK_FREQ_450_432;
945 freq_select = CDCLK_FREQ_540;
951 freq_select = CDCLK_FREQ_337_308;
956 freq_select = CDCLK_FREQ_675_617;
961 if (dev_priv->cdclk.hw.vco != 0 &&
962 dev_priv->cdclk.hw.vco != vco)
963 skl_dpll0_disable(dev_priv);
965 cdclk_ctl = I915_READ(CDCLK_CTL);
967 if (dev_priv->cdclk.hw.vco != vco) {
968 /* Wa Display #1183: skl,kbl,cfl */
969 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
970 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
971 I915_WRITE(CDCLK_CTL, cdclk_ctl);
974 /* Wa Display #1183: skl,kbl,cfl */
975 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
976 I915_WRITE(CDCLK_CTL, cdclk_ctl);
977 POSTING_READ(CDCLK_CTL);
979 if (dev_priv->cdclk.hw.vco != vco)
980 skl_dpll0_enable(dev_priv, vco);
982 /* Wa Display #1183: skl,kbl,cfl */
983 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
984 I915_WRITE(CDCLK_CTL, cdclk_ctl);
986 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
987 I915_WRITE(CDCLK_CTL, cdclk_ctl);
989 /* Wa Display #1183: skl,kbl,cfl */
990 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
991 I915_WRITE(CDCLK_CTL, cdclk_ctl);
992 POSTING_READ(CDCLK_CTL);
994 /* inform PCU of the change */
995 mutex_lock(&dev_priv->pcu_lock);
996 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
997 mutex_unlock(&dev_priv->pcu_lock);
999 intel_update_cdclk(dev_priv);
1002 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1004 uint32_t cdctl, expected;
1007 * check if the pre-os initialized the display
1008 * There is SWF18 scratchpad register defined which is set by the
1009 * pre-os which can be used by the OS drivers to check the status
1011 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1014 intel_update_cdclk(dev_priv);
1015 /* Is PLL enabled and locked ? */
1016 if (dev_priv->cdclk.hw.vco == 0 ||
1017 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1020 /* DPLL okay; verify the cdclock
1022 * Noticed in some instances that the freq selection is correct but
1023 * decimal part is programmed wrong from BIOS where pre-os does not
1024 * enable display. Verify the same as well.
1026 cdctl = I915_READ(CDCLK_CTL);
1027 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1028 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1029 if (cdctl == expected)
1030 /* All well; nothing to sanitize */
1034 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1036 /* force cdclk programming */
1037 dev_priv->cdclk.hw.cdclk = 0;
1038 /* force full PLL disable + enable */
1039 dev_priv->cdclk.hw.vco = -1;
1043 * skl_init_cdclk - Initialize CDCLK on SKL
1044 * @dev_priv: i915 device
1046 * Initialize CDCLK for SKL and derivatives. This is generally
1047 * done only during the display core initialization sequence,
1048 * after which the DMC will take care of turning CDCLK off/on
1051 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1053 struct intel_cdclk_state cdclk_state;
1055 skl_sanitize_cdclk(dev_priv);
1057 if (dev_priv->cdclk.hw.cdclk != 0 &&
1058 dev_priv->cdclk.hw.vco != 0) {
1060 * Use the current vco as our initial
1061 * guess as to what the preferred vco is.
1063 if (dev_priv->skl_preferred_vco_freq == 0)
1064 skl_set_preferred_cdclk_vco(dev_priv,
1065 dev_priv->cdclk.hw.vco);
1069 cdclk_state = dev_priv->cdclk.hw;
1071 cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1072 if (cdclk_state.vco == 0)
1073 cdclk_state.vco = 8100000;
1074 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1076 skl_set_cdclk(dev_priv, &cdclk_state);
1080 * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1081 * @dev_priv: i915 device
1083 * Uninitialize CDCLK for SKL and derivatives. This is done only
1084 * during the display core uninitialization sequence.
1086 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1088 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1090 cdclk_state.cdclk = cdclk_state.ref;
1091 cdclk_state.vco = 0;
1093 skl_set_cdclk(dev_priv, &cdclk_state);
1096 static int bxt_calc_cdclk(int min_cdclk)
1098 if (min_cdclk > 576000)
1100 else if (min_cdclk > 384000)
1102 else if (min_cdclk > 288000)
1104 else if (min_cdclk > 144000)
1110 static int glk_calc_cdclk(int min_cdclk)
1112 if (min_cdclk > 158400)
1114 else if (min_cdclk > 79200)
1120 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1124 if (cdclk == dev_priv->cdclk.hw.ref)
1129 MISSING_CASE(cdclk);
1141 return dev_priv->cdclk.hw.ref * ratio;
1144 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1148 if (cdclk == dev_priv->cdclk.hw.ref)
1153 MISSING_CASE(cdclk);
1161 return dev_priv->cdclk.hw.ref * ratio;
1164 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1165 struct intel_cdclk_state *cdclk_state)
1169 cdclk_state->ref = 19200;
1170 cdclk_state->vco = 0;
1172 val = I915_READ(BXT_DE_PLL_ENABLE);
1173 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1176 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1179 val = I915_READ(BXT_DE_PLL_CTL);
1180 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1183 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1184 struct intel_cdclk_state *cdclk_state)
1189 bxt_de_pll_update(dev_priv, cdclk_state);
1191 cdclk_state->cdclk = cdclk_state->ref;
1193 if (cdclk_state->vco == 0)
1196 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1199 case BXT_CDCLK_CD2X_DIV_SEL_1:
1202 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1203 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1206 case BXT_CDCLK_CD2X_DIV_SEL_2:
1209 case BXT_CDCLK_CD2X_DIV_SEL_4:
1213 MISSING_CASE(divider);
1217 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1220 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1222 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1225 if (intel_wait_for_register(dev_priv,
1226 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1228 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1230 dev_priv->cdclk.hw.vco = 0;
1233 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1235 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1238 val = I915_READ(BXT_DE_PLL_CTL);
1239 val &= ~BXT_DE_PLL_RATIO_MASK;
1240 val |= BXT_DE_PLL_RATIO(ratio);
1241 I915_WRITE(BXT_DE_PLL_CTL, val);
1243 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1246 if (intel_wait_for_register(dev_priv,
1251 DRM_ERROR("timeout waiting for DE PLL lock\n");
1253 dev_priv->cdclk.hw.vco = vco;
1256 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1257 const struct intel_cdclk_state *cdclk_state)
1259 int cdclk = cdclk_state->cdclk;
1260 int vco = cdclk_state->vco;
1264 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1265 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1267 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1270 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1273 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1274 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1277 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1280 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1283 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1287 /* Inform power controller of upcoming frequency change */
1288 mutex_lock(&dev_priv->pcu_lock);
1289 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1291 mutex_unlock(&dev_priv->pcu_lock);
1294 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1299 if (dev_priv->cdclk.hw.vco != 0 &&
1300 dev_priv->cdclk.hw.vco != vco)
1301 bxt_de_pll_disable(dev_priv);
1303 if (dev_priv->cdclk.hw.vco != vco)
1304 bxt_de_pll_enable(dev_priv, vco);
1306 val = divider | skl_cdclk_decimal(cdclk);
1308 * FIXME if only the cd2x divider needs changing, it could be done
1309 * without shutting off the pipe (if only one pipe is active).
1311 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1313 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1316 if (cdclk >= 500000)
1317 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1318 I915_WRITE(CDCLK_CTL, val);
1320 mutex_lock(&dev_priv->pcu_lock);
1321 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1322 DIV_ROUND_UP(cdclk, 25000));
1323 mutex_unlock(&dev_priv->pcu_lock);
1326 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1331 intel_update_cdclk(dev_priv);
1334 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1336 u32 cdctl, expected;
1338 intel_update_cdclk(dev_priv);
1340 if (dev_priv->cdclk.hw.vco == 0 ||
1341 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1344 /* DPLL okay; verify the cdclock
1346 * Some BIOS versions leave an incorrect decimal frequency value and
1347 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1348 * so sanitize this register.
1350 cdctl = I915_READ(CDCLK_CTL);
1352 * Let's ignore the pipe field, since BIOS could have configured the
1353 * dividers both synching to an active pipe, or asynchronously
1356 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1358 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1359 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1361 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1364 if (dev_priv->cdclk.hw.cdclk >= 500000)
1365 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1367 if (cdctl == expected)
1368 /* All well; nothing to sanitize */
1372 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1374 /* force cdclk programming */
1375 dev_priv->cdclk.hw.cdclk = 0;
1377 /* force full PLL disable + enable */
1378 dev_priv->cdclk.hw.vco = -1;
1382 * bxt_init_cdclk - Initialize CDCLK on BXT
1383 * @dev_priv: i915 device
1385 * Initialize CDCLK for BXT and derivatives. This is generally
1386 * done only during the display core initialization sequence,
1387 * after which the DMC will take care of turning CDCLK off/on
1390 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1392 struct intel_cdclk_state cdclk_state;
1394 bxt_sanitize_cdclk(dev_priv);
1396 if (dev_priv->cdclk.hw.cdclk != 0 &&
1397 dev_priv->cdclk.hw.vco != 0)
1400 cdclk_state = dev_priv->cdclk.hw;
1404 * - The initial CDCLK needs to be read from VBT.
1405 * Need to make this change after VBT has changes for BXT.
1407 if (IS_GEMINILAKE(dev_priv)) {
1408 cdclk_state.cdclk = glk_calc_cdclk(0);
1409 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1411 cdclk_state.cdclk = bxt_calc_cdclk(0);
1412 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1415 bxt_set_cdclk(dev_priv, &cdclk_state);
1419 * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1420 * @dev_priv: i915 device
1422 * Uninitialize CDCLK for BXT and derivatives. This is done only
1423 * during the display core uninitialization sequence.
1425 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1427 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1429 cdclk_state.cdclk = cdclk_state.ref;
1430 cdclk_state.vco = 0;
1432 bxt_set_cdclk(dev_priv, &cdclk_state);
1435 static int cnl_calc_cdclk(int min_cdclk)
1437 if (min_cdclk > 336000)
1439 else if (min_cdclk > 168000)
1445 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1446 struct intel_cdclk_state *cdclk_state)
1450 if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1451 cdclk_state->ref = 24000;
1453 cdclk_state->ref = 19200;
1455 cdclk_state->vco = 0;
1457 val = I915_READ(BXT_DE_PLL_ENABLE);
1458 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1461 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1464 cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1467 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1468 struct intel_cdclk_state *cdclk_state)
1473 cnl_cdclk_pll_update(dev_priv, cdclk_state);
1475 cdclk_state->cdclk = cdclk_state->ref;
1477 if (cdclk_state->vco == 0)
1480 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1483 case BXT_CDCLK_CD2X_DIV_SEL_1:
1486 case BXT_CDCLK_CD2X_DIV_SEL_2:
1490 MISSING_CASE(divider);
1494 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1497 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1501 val = I915_READ(BXT_DE_PLL_ENABLE);
1502 val &= ~BXT_DE_PLL_PLL_ENABLE;
1503 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1506 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1507 DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
1509 dev_priv->cdclk.hw.vco = 0;
1512 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1514 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1517 val = CNL_CDCLK_PLL_RATIO(ratio);
1518 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1520 val |= BXT_DE_PLL_PLL_ENABLE;
1521 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1524 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1525 DRM_ERROR("timout waiting for CDCLK PLL lock\n");
1527 dev_priv->cdclk.hw.vco = vco;
1530 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1531 const struct intel_cdclk_state *cdclk_state)
1533 int cdclk = cdclk_state->cdclk;
1534 int vco = cdclk_state->vco;
1535 u32 val, divider, pcu_ack;
1538 mutex_lock(&dev_priv->pcu_lock);
1539 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1540 SKL_CDCLK_PREPARE_FOR_CHANGE,
1541 SKL_CDCLK_READY_FOR_CHANGE,
1542 SKL_CDCLK_READY_FOR_CHANGE, 3);
1543 mutex_unlock(&dev_priv->pcu_lock);
1545 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1550 /* cdclk = vco / 2 / div{1,2} */
1551 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1553 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1556 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1559 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1562 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1579 if (dev_priv->cdclk.hw.vco != 0 &&
1580 dev_priv->cdclk.hw.vco != vco)
1581 cnl_cdclk_pll_disable(dev_priv);
1583 if (dev_priv->cdclk.hw.vco != vco)
1584 cnl_cdclk_pll_enable(dev_priv, vco);
1586 val = divider | skl_cdclk_decimal(cdclk);
1588 * FIXME if only the cd2x divider needs changing, it could be done
1589 * without shutting off the pipe (if only one pipe is active).
1591 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1592 I915_WRITE(CDCLK_CTL, val);
1594 /* inform PCU of the change */
1595 mutex_lock(&dev_priv->pcu_lock);
1596 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
1597 mutex_unlock(&dev_priv->pcu_lock);
1599 intel_update_cdclk(dev_priv);
1602 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1606 if (cdclk == dev_priv->cdclk.hw.ref)
1611 MISSING_CASE(cdclk);
1614 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1617 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1621 return dev_priv->cdclk.hw.ref * ratio;
1624 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1626 u32 cdctl, expected;
1628 intel_update_cdclk(dev_priv);
1630 if (dev_priv->cdclk.hw.vco == 0 ||
1631 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1634 /* DPLL okay; verify the cdclock
1636 * Some BIOS versions leave an incorrect decimal frequency value and
1637 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1638 * so sanitize this register.
1640 cdctl = I915_READ(CDCLK_CTL);
1642 * Let's ignore the pipe field, since BIOS could have configured the
1643 * dividers both synching to an active pipe, or asynchronously
1646 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1648 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1649 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1651 if (cdctl == expected)
1652 /* All well; nothing to sanitize */
1656 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1658 /* force cdclk programming */
1659 dev_priv->cdclk.hw.cdclk = 0;
1661 /* force full PLL disable + enable */
1662 dev_priv->cdclk.hw.vco = -1;
1666 * cnl_init_cdclk - Initialize CDCLK on CNL
1667 * @dev_priv: i915 device
1669 * Initialize CDCLK for CNL. This is generally
1670 * done only during the display core initialization sequence,
1671 * after which the DMC will take care of turning CDCLK off/on
1674 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1676 struct intel_cdclk_state cdclk_state;
1678 cnl_sanitize_cdclk(dev_priv);
1680 if (dev_priv->cdclk.hw.cdclk != 0 &&
1681 dev_priv->cdclk.hw.vco != 0)
1684 cdclk_state = dev_priv->cdclk.hw;
1686 cdclk_state.cdclk = cnl_calc_cdclk(0);
1687 cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1689 cnl_set_cdclk(dev_priv, &cdclk_state);
1693 * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
1694 * @dev_priv: i915 device
1696 * Uninitialize CDCLK for CNL. This is done only
1697 * during the display core uninitialization sequence.
1699 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
1701 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1703 cdclk_state.cdclk = cdclk_state.ref;
1704 cdclk_state.vco = 0;
1706 cnl_set_cdclk(dev_priv, &cdclk_state);
1710 * intel_cdclk_state_compare - Determine if two CDCLK states differ
1711 * @a: first CDCLK state
1712 * @b: second CDCLK state
1715 * True if the CDCLK states are identical, false if they differ.
1717 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1718 const struct intel_cdclk_state *b)
1720 return memcmp(a, b, sizeof(*a)) == 0;
1724 * intel_set_cdclk - Push the CDCLK state to the hardware
1725 * @dev_priv: i915 device
1726 * @cdclk_state: new CDCLK state
1728 * Program the hardware based on the passed in CDCLK state,
1731 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1732 const struct intel_cdclk_state *cdclk_state)
1734 if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state))
1737 if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
1740 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n",
1741 cdclk_state->cdclk, cdclk_state->vco,
1744 dev_priv->display.set_cdclk(dev_priv, cdclk_state);
1747 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
1750 if (INTEL_GEN(dev_priv) >= 10)
1752 * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
1753 * once DDI clock voltage requirements are
1754 * handled correctly.
1757 else if (IS_GEMINILAKE(dev_priv))
1759 * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1760 * as a temporary workaround. Use a higher cdclk instead. (Note that
1761 * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1764 return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
1765 else if (IS_GEN9(dev_priv) ||
1766 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1768 else if (IS_CHERRYVIEW(dev_priv))
1769 return DIV_ROUND_UP(pixel_rate * 100, 95);
1771 return DIV_ROUND_UP(pixel_rate * 100, 90);
1774 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
1776 struct drm_i915_private *dev_priv =
1777 to_i915(crtc_state->base.crtc->dev);
1780 if (!crtc_state->base.enable)
1783 min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
1785 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1786 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
1787 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
1789 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1790 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1791 * there may be audio corruption or screen corruption." This cdclk
1792 * restriction for GLK is 316.8 MHz.
1794 if (intel_crtc_has_dp_encoder(crtc_state) &&
1795 crtc_state->has_audio &&
1796 crtc_state->port_clock >= 540000 &&
1797 crtc_state->lane_count == 4) {
1798 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1799 /* Display WA #1145: glk,cnl */
1800 min_cdclk = max(316800, min_cdclk);
1801 } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
1802 /* Display WA #1144: skl,bxt */
1803 min_cdclk = max(432000, min_cdclk);
1807 /* According to BSpec, "The CD clock frequency must be at least twice
1808 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1810 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
1811 min_cdclk = max(2 * 96000, min_cdclk);
1813 if (min_cdclk > dev_priv->max_cdclk_freq) {
1814 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
1815 min_cdclk, dev_priv->max_cdclk_freq);
1822 static int intel_compute_min_cdclk(struct drm_atomic_state *state)
1824 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1825 struct drm_i915_private *dev_priv = to_i915(state->dev);
1826 struct intel_crtc *crtc;
1827 struct intel_crtc_state *crtc_state;
1831 memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
1832 sizeof(intel_state->min_cdclk));
1834 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
1835 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
1839 intel_state->min_cdclk[i] = min_cdclk;
1843 for_each_pipe(dev_priv, pipe)
1844 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
1849 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1851 struct drm_i915_private *dev_priv = to_i915(state->dev);
1852 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1853 int min_cdclk, cdclk;
1855 min_cdclk = intel_compute_min_cdclk(state);
1859 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
1861 intel_state->cdclk.logical.cdclk = cdclk;
1863 if (!intel_state->active_crtcs) {
1864 cdclk = vlv_calc_cdclk(dev_priv, 0);
1866 intel_state->cdclk.actual.cdclk = cdclk;
1868 intel_state->cdclk.actual =
1869 intel_state->cdclk.logical;
1875 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1877 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1878 int min_cdclk, cdclk;
1880 min_cdclk = intel_compute_min_cdclk(state);
1885 * FIXME should also account for plane ratio
1886 * once 64bpp pixel formats are supported.
1888 cdclk = bdw_calc_cdclk(min_cdclk);
1890 intel_state->cdclk.logical.cdclk = cdclk;
1892 if (!intel_state->active_crtcs) {
1893 cdclk = bdw_calc_cdclk(0);
1895 intel_state->cdclk.actual.cdclk = cdclk;
1897 intel_state->cdclk.actual =
1898 intel_state->cdclk.logical;
1904 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1906 struct drm_i915_private *dev_priv = to_i915(state->dev);
1907 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1908 int min_cdclk, cdclk, vco;
1910 min_cdclk = intel_compute_min_cdclk(state);
1914 vco = intel_state->cdclk.logical.vco;
1916 vco = dev_priv->skl_preferred_vco_freq;
1919 * FIXME should also account for plane ratio
1920 * once 64bpp pixel formats are supported.
1922 cdclk = skl_calc_cdclk(min_cdclk, vco);
1924 intel_state->cdclk.logical.vco = vco;
1925 intel_state->cdclk.logical.cdclk = cdclk;
1927 if (!intel_state->active_crtcs) {
1928 cdclk = skl_calc_cdclk(0, vco);
1930 intel_state->cdclk.actual.vco = vco;
1931 intel_state->cdclk.actual.cdclk = cdclk;
1933 intel_state->cdclk.actual =
1934 intel_state->cdclk.logical;
1940 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1942 struct drm_i915_private *dev_priv = to_i915(state->dev);
1943 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1944 int min_cdclk, cdclk, vco;
1946 min_cdclk = intel_compute_min_cdclk(state);
1950 if (IS_GEMINILAKE(dev_priv)) {
1951 cdclk = glk_calc_cdclk(min_cdclk);
1952 vco = glk_de_pll_vco(dev_priv, cdclk);
1954 cdclk = bxt_calc_cdclk(min_cdclk);
1955 vco = bxt_de_pll_vco(dev_priv, cdclk);
1958 intel_state->cdclk.logical.vco = vco;
1959 intel_state->cdclk.logical.cdclk = cdclk;
1961 if (!intel_state->active_crtcs) {
1962 if (IS_GEMINILAKE(dev_priv)) {
1963 cdclk = glk_calc_cdclk(0);
1964 vco = glk_de_pll_vco(dev_priv, cdclk);
1966 cdclk = bxt_calc_cdclk(0);
1967 vco = bxt_de_pll_vco(dev_priv, cdclk);
1970 intel_state->cdclk.actual.vco = vco;
1971 intel_state->cdclk.actual.cdclk = cdclk;
1973 intel_state->cdclk.actual =
1974 intel_state->cdclk.logical;
1980 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
1982 struct drm_i915_private *dev_priv = to_i915(state->dev);
1983 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1984 int min_cdclk, cdclk, vco;
1986 min_cdclk = intel_compute_min_cdclk(state);
1990 cdclk = cnl_calc_cdclk(min_cdclk);
1991 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
1993 intel_state->cdclk.logical.vco = vco;
1994 intel_state->cdclk.logical.cdclk = cdclk;
1996 if (!intel_state->active_crtcs) {
1997 cdclk = cnl_calc_cdclk(0);
1998 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2000 intel_state->cdclk.actual.vco = vco;
2001 intel_state->cdclk.actual.cdclk = cdclk;
2003 intel_state->cdclk.actual =
2004 intel_state->cdclk.logical;
2010 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2012 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2014 if (INTEL_GEN(dev_priv) >= 10)
2016 * FIXME: Allow '2 * max_cdclk_freq'
2017 * once DDI clock voltage requirements are
2018 * handled correctly.
2020 return max_cdclk_freq;
2021 else if (IS_GEMINILAKE(dev_priv))
2023 * FIXME: Limiting to 99% as a temporary workaround. See
2024 * intel_min_cdclk() for details.
2026 return 2 * max_cdclk_freq * 99 / 100;
2027 else if (IS_GEN9(dev_priv) ||
2028 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2029 return max_cdclk_freq;
2030 else if (IS_CHERRYVIEW(dev_priv))
2031 return max_cdclk_freq*95/100;
2032 else if (INTEL_INFO(dev_priv)->gen < 4)
2033 return 2*max_cdclk_freq*90/100;
2035 return max_cdclk_freq*90/100;
2039 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2040 * @dev_priv: i915 device
2042 * Determine the maximum CDCLK frequency the platform supports, and also
2043 * derive the maximum dot clock frequency the maximum CDCLK frequency
2046 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2048 if (IS_CANNONLAKE(dev_priv)) {
2049 dev_priv->max_cdclk_freq = 528000;
2050 } else if (IS_GEN9_BC(dev_priv)) {
2051 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2054 vco = dev_priv->skl_preferred_vco_freq;
2055 WARN_ON(vco != 8100000 && vco != 8640000);
2058 * Use the lower (vco 8640) cdclk values as a
2059 * first guess. skl_calc_cdclk() will correct it
2060 * if the preferred vco is 8100 instead.
2062 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2064 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2066 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2071 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2072 } else if (IS_GEMINILAKE(dev_priv)) {
2073 dev_priv->max_cdclk_freq = 316800;
2074 } else if (IS_BROXTON(dev_priv)) {
2075 dev_priv->max_cdclk_freq = 624000;
2076 } else if (IS_BROADWELL(dev_priv)) {
2078 * FIXME with extra cooling we can allow
2079 * 540 MHz for ULX and 675 Mhz for ULT.
2080 * How can we know if extra cooling is
2081 * available? PCI ID, VTB, something else?
2083 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2084 dev_priv->max_cdclk_freq = 450000;
2085 else if (IS_BDW_ULX(dev_priv))
2086 dev_priv->max_cdclk_freq = 450000;
2087 else if (IS_BDW_ULT(dev_priv))
2088 dev_priv->max_cdclk_freq = 540000;
2090 dev_priv->max_cdclk_freq = 675000;
2091 } else if (IS_CHERRYVIEW(dev_priv)) {
2092 dev_priv->max_cdclk_freq = 320000;
2093 } else if (IS_VALLEYVIEW(dev_priv)) {
2094 dev_priv->max_cdclk_freq = 400000;
2096 /* otherwise assume cdclk is fixed */
2097 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2100 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2102 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2103 dev_priv->max_cdclk_freq);
2105 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2106 dev_priv->max_dotclk_freq);
2110 * intel_update_cdclk - Determine the current CDCLK frequency
2111 * @dev_priv: i915 device
2113 * Determine the current CDCLK frequency.
2115 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2117 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2119 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
2120 dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
2121 dev_priv->cdclk.hw.ref);
2124 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2125 * Programmng [sic] note: bit[9:2] should be programmed to the number
2126 * of cdclk that generates 4MHz reference clock freq which is used to
2127 * generate GMBus clock. This will vary with the cdclk freq.
2129 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2130 I915_WRITE(GMBUSFREQ_VLV,
2131 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2134 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2137 int divider, fraction;
2139 if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2149 rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2151 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2154 I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2155 return divider + fraction;
2158 static int pch_rawclk(struct drm_i915_private *dev_priv)
2160 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2163 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2165 /* RAWCLK_FREQ_VLV register updated from power well code */
2166 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2167 CCK_DISPLAY_REF_CLOCK_CONTROL);
2170 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2174 /* hrawclock is 1/4 the FSB frequency */
2175 clkcfg = I915_READ(CLKCFG);
2176 switch (clkcfg & CLKCFG_FSB_MASK) {
2177 case CLKCFG_FSB_400:
2179 case CLKCFG_FSB_533:
2181 case CLKCFG_FSB_667:
2183 case CLKCFG_FSB_800:
2185 case CLKCFG_FSB_1067:
2186 case CLKCFG_FSB_1067_ALT:
2188 case CLKCFG_FSB_1333:
2189 case CLKCFG_FSB_1333_ALT:
2197 * intel_update_rawclk - Determine the current RAWCLK frequency
2198 * @dev_priv: i915 device
2200 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2201 * frequency clock so this needs to done only once.
2203 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2206 if (HAS_PCH_CNP(dev_priv))
2207 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2208 else if (HAS_PCH_SPLIT(dev_priv))
2209 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2210 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2211 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2212 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2213 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2215 /* no rawclk on other platforms, or no need to know it */
2218 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2222 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2223 * @dev_priv: i915 device
2225 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2227 if (IS_CHERRYVIEW(dev_priv)) {
2228 dev_priv->display.set_cdclk = chv_set_cdclk;
2229 dev_priv->display.modeset_calc_cdclk =
2230 vlv_modeset_calc_cdclk;
2231 } else if (IS_VALLEYVIEW(dev_priv)) {
2232 dev_priv->display.set_cdclk = vlv_set_cdclk;
2233 dev_priv->display.modeset_calc_cdclk =
2234 vlv_modeset_calc_cdclk;
2235 } else if (IS_BROADWELL(dev_priv)) {
2236 dev_priv->display.set_cdclk = bdw_set_cdclk;
2237 dev_priv->display.modeset_calc_cdclk =
2238 bdw_modeset_calc_cdclk;
2239 } else if (IS_GEN9_LP(dev_priv)) {
2240 dev_priv->display.set_cdclk = bxt_set_cdclk;
2241 dev_priv->display.modeset_calc_cdclk =
2242 bxt_modeset_calc_cdclk;
2243 } else if (IS_GEN9_BC(dev_priv)) {
2244 dev_priv->display.set_cdclk = skl_set_cdclk;
2245 dev_priv->display.modeset_calc_cdclk =
2246 skl_modeset_calc_cdclk;
2247 } else if (IS_CANNONLAKE(dev_priv)) {
2248 dev_priv->display.set_cdclk = cnl_set_cdclk;
2249 dev_priv->display.modeset_calc_cdclk =
2250 cnl_modeset_calc_cdclk;
2253 if (IS_CANNONLAKE(dev_priv))
2254 dev_priv->display.get_cdclk = cnl_get_cdclk;
2255 else if (IS_GEN9_BC(dev_priv))
2256 dev_priv->display.get_cdclk = skl_get_cdclk;
2257 else if (IS_GEN9_LP(dev_priv))
2258 dev_priv->display.get_cdclk = bxt_get_cdclk;
2259 else if (IS_BROADWELL(dev_priv))
2260 dev_priv->display.get_cdclk = bdw_get_cdclk;
2261 else if (IS_HASWELL(dev_priv))
2262 dev_priv->display.get_cdclk = hsw_get_cdclk;
2263 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2264 dev_priv->display.get_cdclk = vlv_get_cdclk;
2265 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2266 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2267 else if (IS_GEN5(dev_priv))
2268 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2269 else if (IS_GM45(dev_priv))
2270 dev_priv->display.get_cdclk = gm45_get_cdclk;
2271 else if (IS_G45(dev_priv))
2272 dev_priv->display.get_cdclk = g33_get_cdclk;
2273 else if (IS_I965GM(dev_priv))
2274 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2275 else if (IS_I965G(dev_priv))
2276 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2277 else if (IS_PINEVIEW(dev_priv))
2278 dev_priv->display.get_cdclk = pnv_get_cdclk;
2279 else if (IS_G33(dev_priv))
2280 dev_priv->display.get_cdclk = g33_get_cdclk;
2281 else if (IS_I945GM(dev_priv))
2282 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2283 else if (IS_I945G(dev_priv))
2284 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2285 else if (IS_I915GM(dev_priv))
2286 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2287 else if (IS_I915G(dev_priv))
2288 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2289 else if (IS_I865G(dev_priv))
2290 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2291 else if (IS_I85X(dev_priv))
2292 dev_priv->display.get_cdclk = i85x_get_cdclk;
2293 else if (IS_I845G(dev_priv))
2294 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2296 WARN(!IS_I830(dev_priv),
2297 "Unknown platform. Assuming 133 MHz CDCLK\n");
2298 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;