drivers/gpu/drm/i915/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_drv.h"
  25
  26 /**
  27  * DOC: CDCLK / RAWCLK
  28  *
  29  * The display engine uses several different clocks to do its work. There
  30  * are two main clocks involved that aren't directly related to the actual
  31  * pixel clock or any symbol/bit clock of the actual output port. These
  32  * are the core display clock (CDCLK) and RAWCLK.
  33  *
  34  * CDCLK clocks most of the display pipe logic, and thus its frequency
  35  * must be high enough to support the rate at which pixels are flowing
  36  * through the pipes. Downscaling must also be accounted as that increases
  37  * the effective pixel rate.
  38  *
  39  * On several platforms the CDCLK frequency can be changed dynamically
  40  * to minimize power consumption for a given display configuration.
  41  * Typically changes to the CDCLK frequency require all the display pipes
  42  * to be shut down while the frequency is being changed.
  43  *
  44  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  45  * DMC will not change the active CDCLK frequency however, so that part
  46  * will still be performed by the driver directly.
  47  *
  48  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  49  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  50  * really need to know about RAWCLK is its frequency so that various
  51  * dividers can be programmed correctly.
  52  */
  53
  54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  55                                    struct intel_cdclk_state *cdclk_state)
  56 {
  57         cdclk_state->cdclk = 133333;
  58 }
  59
  60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  61                                    struct intel_cdclk_state *cdclk_state)
  62 {
  63         cdclk_state->cdclk = 200000;
  64 }
  65
  66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  67                                    struct intel_cdclk_state *cdclk_state)
  68 {
  69         cdclk_state->cdclk = 266667;
  70 }
  71
  72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  73                                    struct intel_cdclk_state *cdclk_state)
  74 {
  75         cdclk_state->cdclk = 333333;
  76 }
  77
  78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  79                                    struct intel_cdclk_state *cdclk_state)
  80 {
  81         cdclk_state->cdclk = 400000;
  82 }
  83
  84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  85                                    struct intel_cdclk_state *cdclk_state)
  86 {
  87         cdclk_state->cdclk = 450000;
  88 }
  89
  90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  91                            struct intel_cdclk_state *cdclk_state)
  92 {
  93         struct pci_dev *pdev = dev_priv->drm.pdev;
  94         u16 hpllcc = 0;
  95
  96         /*
  97          * 852GM/852GMV only supports 133 MHz and the HPLLCC
  98          * encoding is different :(
  99          * FIXME is this the right way to detect 852GM/852GMV?
 100          */
 101         if (pdev->revision == 0x1) {
 102                 cdclk_state->cdclk = 133333;
 103                 return;
 104         }
 105
 106         pci_bus_read_config_word(pdev->bus,
 107                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 108
 109         /* Assume that the hardware is in the high speed state.  This
 110          * should be the default.
 111          */
 112         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 113         case GC_CLOCK_133_200:
 114         case GC_CLOCK_133_200_2:
 115         case GC_CLOCK_100_200:
 116                 cdclk_state->cdclk = 200000;
 117                 break;
 118         case GC_CLOCK_166_250:
 119                 cdclk_state->cdclk = 250000;
 120                 break;
 121         case GC_CLOCK_100_133:
 122                 cdclk_state->cdclk = 133333;
 123                 break;
 124         case GC_CLOCK_133_266:
 125         case GC_CLOCK_133_266_2:
 126         case GC_CLOCK_166_266:
 127                 cdclk_state->cdclk = 266667;
 128                 break;
 129         }
 130 }
 131
 132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 133                              struct intel_cdclk_state *cdclk_state)
 134 {
 135         struct pci_dev *pdev = dev_priv->drm.pdev;
 136         u16 gcfgc = 0;
 137
 138         pci_read_config_word(pdev, GCFGC, &gcfgc);
 139
 140         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 141                 cdclk_state->cdclk = 133333;
 142                 return;
 143         }
 144
 145         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 146         case GC_DISPLAY_CLOCK_333_320_MHZ:
 147                 cdclk_state->cdclk = 333333;
 148                 break;
 149         default:
 150         case GC_DISPLAY_CLOCK_190_200_MHZ:
 151                 cdclk_state->cdclk = 190000;
 152                 break;
 153         }
 154 }
 155
 156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 157                              struct intel_cdclk_state *cdclk_state)
 158 {
 159         struct pci_dev *pdev = dev_priv->drm.pdev;
 160         u16 gcfgc = 0;
 161
 162         pci_read_config_word(pdev, GCFGC, &gcfgc);
 163
 164         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 165                 cdclk_state->cdclk = 133333;
 166                 return;
 167         }
 168
 169         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 170         case GC_DISPLAY_CLOCK_333_320_MHZ:
 171                 cdclk_state->cdclk = 320000;
 172                 break;
 173         default:
 174         case GC_DISPLAY_CLOCK_190_200_MHZ:
 175                 cdclk_state->cdclk = 200000;
 176                 break;
 177         }
 178 }
 179
 180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 181 {
 182         static const unsigned int blb_vco[8] = {
 183                 [0] = 3200000,
 184                 [1] = 4000000,
 185                 [2] = 5333333,
 186                 [3] = 4800000,
 187                 [4] = 6400000,
 188         };
 189         static const unsigned int pnv_vco[8] = {
 190                 [0] = 3200000,
 191                 [1] = 4000000,
 192                 [2] = 5333333,
 193                 [3] = 4800000,
 194                 [4] = 2666667,
 195         };
 196         static const unsigned int cl_vco[8] = {
 197                 [0] = 3200000,
 198                 [1] = 4000000,
 199                 [2] = 5333333,
 200                 [3] = 6400000,
 201                 [4] = 3333333,
 202                 [5] = 3566667,
 203                 [6] = 4266667,
 204         };
 205         static const unsigned int elk_vco[8] = {
 206                 [0] = 3200000,
 207                 [1] = 4000000,
 208                 [2] = 5333333,
 209                 [3] = 4800000,
 210         };
 211         static const unsigned int ctg_vco[8] = {
 212                 [0] = 3200000,
 213                 [1] = 4000000,
 214                 [2] = 5333333,
 215                 [3] = 6400000,
 216                 [4] = 2666667,
 217                 [5] = 4266667,
 218         };
 219         const unsigned int *vco_table;
 220         unsigned int vco;
 221         uint8_t tmp = 0;
 222
 223         /* FIXME other chipsets? */
 224         if (IS_GM45(dev_priv))
 225                 vco_table = ctg_vco;
 226         else if (IS_G45(dev_priv))
 227                 vco_table = elk_vco;
 228         else if (IS_I965GM(dev_priv))
 229                 vco_table = cl_vco;
 230         else if (IS_PINEVIEW(dev_priv))
 231                 vco_table = pnv_vco;
 232         else if (IS_G33(dev_priv))
 233                 vco_table = blb_vco;
 234         else
 235                 return 0;
 236
 237         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 238
 239         vco = vco_table[tmp & 0x7];
 240         if (vco == 0)
 241                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 242         else
 243                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 244
 245         return vco;
 246 }
 247
 248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 249                           struct intel_cdclk_state *cdclk_state)
 250 {
 251         struct pci_dev *pdev = dev_priv->drm.pdev;
 252         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
 253         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
 254         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
 255         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
 256         const uint8_t *div_table;
 257         unsigned int cdclk_sel;
 258         uint16_t tmp = 0;
 259
 260         cdclk_state->vco = intel_hpll_vco(dev_priv);
 261
 262         pci_read_config_word(pdev, GCFGC, &tmp);
 263
 264         cdclk_sel = (tmp >> 4) & 0x7;
 265
 266         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 267                 goto fail;
 268
 269         switch (cdclk_state->vco) {
 270         case 3200000:
 271                 div_table = div_3200;
 272                 break;
 273         case 4000000:
 274                 div_table = div_4000;
 275                 break;
 276         case 4800000:
 277                 div_table = div_4800;
 278                 break;
 279         case 5333333:
 280                 div_table = div_5333;
 281                 break;
 282         default:
 283                 goto fail;
 284         }
 285
 286         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 287                                                div_table[cdclk_sel]);
 288         return;
 289
 290 fail:
 291         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 292                   cdclk_state->vco, tmp);
 293         cdclk_state->cdclk = 190476;
 294 }
 295
 296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 297                           struct intel_cdclk_state *cdclk_state)
 298 {
 299         struct pci_dev *pdev = dev_priv->drm.pdev;
 300         u16 gcfgc = 0;
 301
 302         pci_read_config_word(pdev, GCFGC, &gcfgc);
 303
 304         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 305         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 306                 cdclk_state->cdclk = 266667;
 307                 break;
 308         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 309                 cdclk_state->cdclk = 333333;
 310                 break;
 311         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 312                 cdclk_state->cdclk = 444444;
 313                 break;
 314         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 315                 cdclk_state->cdclk = 200000;
 316                 break;
 317         default:
 318                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 319                 /* fall through */
 320         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 321                 cdclk_state->cdclk = 133333;
 322                 break;
 323         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 324                 cdclk_state->cdclk = 166667;
 325                 break;
 326         }
 327 }
 328
 329 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 330                              struct intel_cdclk_state *cdclk_state)
 331 {
 332         struct pci_dev *pdev = dev_priv->drm.pdev;
 333         static const uint8_t div_3200[] = { 16, 10,  8 };
 334         static const uint8_t div_4000[] = { 20, 12, 10 };
 335         static const uint8_t div_5333[] = { 24, 16, 14 };
 336         const uint8_t *div_table;
 337         unsigned int cdclk_sel;
 338         uint16_t tmp = 0;
 339
 340         cdclk_state->vco = intel_hpll_vco(dev_priv);
 341
 342         pci_read_config_word(pdev, GCFGC, &tmp);
 343
 344         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 345
 346         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 347                 goto fail;
 348
 349         switch (cdclk_state->vco) {
 350         case 3200000:
 351                 div_table = div_3200;
 352                 break;
 353         case 4000000:
 354                 div_table = div_4000;
 355                 break;
 356         case 5333333:
 357                 div_table = div_5333;
 358                 break;
 359         default:
 360                 goto fail;
 361         }
 362
 363         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 364                                                div_table[cdclk_sel]);
 365         return;
 366
 367 fail:
 368         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 369                   cdclk_state->vco, tmp);
 370         cdclk_state->cdclk = 200000;
 371 }
 372
 373 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 374                            struct intel_cdclk_state *cdclk_state)
 375 {
 376         struct pci_dev *pdev = dev_priv->drm.pdev;
 377         unsigned int cdclk_sel;
 378         uint16_t tmp = 0;
 379
 380         cdclk_state->vco = intel_hpll_vco(dev_priv);
 381
 382         pci_read_config_word(pdev, GCFGC, &tmp);
 383
 384         cdclk_sel = (tmp >> 12) & 0x1;
 385
 386         switch (cdclk_state->vco) {
 387         case 2666667:
 388         case 4000000:
 389         case 5333333:
 390                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 391                 break;
 392         case 3200000:
 393                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 394                 break;
 395         default:
 396                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 397                           cdclk_state->vco, tmp);
 398                 cdclk_state->cdclk = 222222;
 399                 break;
 400         }
 401 }
 402
 403 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 404                           struct intel_cdclk_state *cdclk_state)
 405 {
 406         uint32_t lcpll = I915_READ(LCPLL_CTL);
 407         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 408
 409         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 410                 cdclk_state->cdclk = 800000;
 411         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 412                 cdclk_state->cdclk = 450000;
 413         else if (freq == LCPLL_CLK_FREQ_450)
 414                 cdclk_state->cdclk = 450000;
 415         else if (IS_HSW_ULT(dev_priv))
 416                 cdclk_state->cdclk = 337500;
 417         else
 418                 cdclk_state->cdclk = 540000;
 419 }
 420
 421 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 422 {
 423         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 424                 333333 : 320000;
 425
 426         /*
 427          * We seem to get an unstable or solid color picture at 200MHz.
 428          * Not sure what's wrong. For now use 200MHz only when all pipes
 429          * are off.
 430          */
 431         if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
 432                 return 400000;
 433         else if (min_cdclk > 266667)
 434                 return freq_320;
 435         else if (min_cdclk > 0)
 436                 return 266667;
 437         else
 438                 return 200000;
 439 }
 440
 441 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
 442 {
 443         if (IS_VALLEYVIEW(dev_priv)) {
 444                 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 445                         return 2;
 446                 else if (cdclk >= 266667)
 447                         return 1;
 448                 else
 449                         return 0;
 450         } else {
 451                 /*
 452                  * Specs are full of misinformation, but testing on actual
 453                  * hardware has shown that we just need to write the desired
 454                  * CCK divider into the Punit register.
 455                  */
 456                 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 457         }
 458 }
 459
 460 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 461                           struct intel_cdclk_state *cdclk_state)
 462 {
 463         u32 val;
 464
 465         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 466         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 467                                                CCK_DISPLAY_CLOCK_CONTROL,
 468                                                cdclk_state->vco);
 469
 470         mutex_lock(&dev_priv->pcu_lock);
 471         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 472         mutex_unlock(&dev_priv->pcu_lock);
 473
 474         if (IS_VALLEYVIEW(dev_priv))
 475                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
 476                         DSPFREQGUAR_SHIFT;
 477         else
 478                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
 479                         DSPFREQGUAR_SHIFT_CHV;
 480 }
 481
 482 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 483 {
 484         unsigned int credits, default_credits;
 485
 486         if (IS_CHERRYVIEW(dev_priv))
 487                 default_credits = PFI_CREDIT(12);
 488         else
 489                 default_credits = PFI_CREDIT(8);
 490
 491         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 492                 /* CHV suggested value is 31 or 63 */
 493                 if (IS_CHERRYVIEW(dev_priv))
 494                         credits = PFI_CREDIT_63;
 495                 else
 496                         credits = PFI_CREDIT(15);
 497         } else {
 498                 credits = default_credits;
 499         }
 500
 501         /*
 502          * WA - write default credits before re-programming
 503          * FIXME: should we also set the resend bit here?
 504          */
 505         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 506                    default_credits);
 507
 508         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 509                    credits | PFI_CREDIT_RESEND);
 510
 511         /*
 512          * FIXME is this guaranteed to clear
 513          * immediately or should we poll for it?
 514          */
 515         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 516 }
 517
 518 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 519                           const struct intel_cdclk_state *cdclk_state)
 520 {
 521         int cdclk = cdclk_state->cdclk;
 522         u32 val, cmd = cdclk_state->voltage_level;
 523
 524         switch (cdclk) {
 525         case 400000:
 526         case 333333:
 527         case 320000:
 528         case 266667:
 529         case 200000:
 530                 break;
 531         default:
 532                 MISSING_CASE(cdclk);
 533                 return;
 534         }
 535
 536         /* There are cases where we can end up here with power domains
 537          * off and a CDCLK frequency other than the minimum, like when
 538          * issuing a modeset without actually changing any display after
 539          * a system suspend.  So grab the PIPE-A domain, which covers
 540          * the HW blocks needed for the following programming.
 541          */
 542         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 543
 544         mutex_lock(&dev_priv->pcu_lock);
 545         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 546         val &= ~DSPFREQGUAR_MASK;
 547         val |= (cmd << DSPFREQGUAR_SHIFT);
 548         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 549         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 550                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 551                      50)) {
 552                 DRM_ERROR("timed out waiting for CDclk change\n");
 553         }
 554         mutex_unlock(&dev_priv->pcu_lock);
 555
 556         mutex_lock(&dev_priv->sb_lock);
 557
 558         if (cdclk == 400000) {
 559                 u32 divider;
 560
 561                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 562                                             cdclk) - 1;
 563
 564                 /* adjust cdclk divider */
 565                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 566                 val &= ~CCK_FREQUENCY_VALUES;
 567                 val |= divider;
 568                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 569
 570                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 571                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 572                              50))
 573                         DRM_ERROR("timed out waiting for CDclk change\n");
 574         }
 575
 576         /* adjust self-refresh exit latency value */
 577         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 578         val &= ~0x7f;
 579
 580         /*
 581          * For high bandwidth configs, we set a higher latency in the bunit
 582          * so that the core display fetch happens in time to avoid underruns.
 583          */
 584         if (cdclk == 400000)
 585                 val |= 4500 / 250; /* 4.5 usec */
 586         else
 587                 val |= 3000 / 250; /* 3.0 usec */
 588         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 589
 590         mutex_unlock(&dev_priv->sb_lock);
 591
 592         intel_update_cdclk(dev_priv);
 593
 594         vlv_program_pfi_credits(dev_priv);
 595
 596         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 597 }
 598
 599 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 600                           const struct intel_cdclk_state *cdclk_state)
 601 {
 602         int cdclk = cdclk_state->cdclk;
 603         u32 val, cmd = cdclk_state->voltage_level;
 604
 605         switch (cdclk) {
 606         case 333333:
 607         case 320000:
 608         case 266667:
 609         case 200000:
 610                 break;
 611         default:
 612                 MISSING_CASE(cdclk);
 613                 return;
 614         }
 615
 616         /* There are cases where we can end up here with power domains
 617          * off and a CDCLK frequency other than the minimum, like when
 618          * issuing a modeset without actually changing any display after
 619          * a system suspend.  So grab the PIPE-A domain, which covers
 620          * the HW blocks needed for the following programming.
 621          */
 622         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 623
 624         mutex_lock(&dev_priv->pcu_lock);
 625         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 626         val &= ~DSPFREQGUAR_MASK_CHV;
 627         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 628         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 629         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 630                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 631                      50)) {
 632                 DRM_ERROR("timed out waiting for CDclk change\n");
 633         }
 634         mutex_unlock(&dev_priv->pcu_lock);
 635
 636         intel_update_cdclk(dev_priv);
 637
 638         vlv_program_pfi_credits(dev_priv);
 639
 640         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 641 }
 642
 643 static int bdw_calc_cdclk(int min_cdclk)
 644 {
 645         if (min_cdclk > 540000)
 646                 return 675000;
 647         else if (min_cdclk > 450000)
 648                 return 540000;
 649         else if (min_cdclk > 337500)
 650                 return 450000;
 651         else
 652                 return 337500;
 653 }
 654
 655 static u8 bdw_calc_voltage_level(int cdclk)
 656 {
 657         switch (cdclk) {
 658         default:
 659         case 337500:
 660                 return 2;
 661         case 450000:
 662                 return 0;
 663         case 540000:
 664                 return 1;
 665         case 675000:
 666                 return 3;
 667         }
 668 }
 669
 670 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 671                           struct intel_cdclk_state *cdclk_state)
 672 {
 673         uint32_t lcpll = I915_READ(LCPLL_CTL);
 674         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 675
 676         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 677                 cdclk_state->cdclk = 800000;
 678         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 679                 cdclk_state->cdclk = 450000;
 680         else if (freq == LCPLL_CLK_FREQ_450)
 681                 cdclk_state->cdclk = 450000;
 682         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 683                 cdclk_state->cdclk = 540000;
 684         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 685                 cdclk_state->cdclk = 337500;
 686         else
 687                 cdclk_state->cdclk = 675000;
 688
 689         /*
 690          * Can't read this out :( Let's assume it's
 691          * at least what the CDCLK frequency requires.
 692          */
 693         cdclk_state->voltage_level =
 694                 bdw_calc_voltage_level(cdclk_state->cdclk);
 695 }
 696
 697 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 698                           const struct intel_cdclk_state *cdclk_state)
 699 {
 700         int cdclk = cdclk_state->cdclk;
 701         uint32_t val;
 702         int ret;
 703
 704         if (WARN((I915_READ(LCPLL_CTL) &
 705                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 706                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 707                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 708                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 709                  "trying to change cdclk frequency with cdclk not enabled\n"))
 710                 return;
 711
 712         mutex_lock(&dev_priv->pcu_lock);
 713         ret = sandybridge_pcode_write(dev_priv,
 714                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 715         mutex_unlock(&dev_priv->pcu_lock);
 716         if (ret) {
 717                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 718                 return;
 719         }
 720
 721         val = I915_READ(LCPLL_CTL);
 722         val |= LCPLL_CD_SOURCE_FCLK;
 723         I915_WRITE(LCPLL_CTL, val);
 724
 725         /*
 726          * According to the spec, it should be enough to poll for this 1 us.
 727          * However, extensive testing shows that this can take longer.
 728          */
 729         if (wait_for_us(I915_READ(LCPLL_CTL) &
 730                         LCPLL_CD_SOURCE_FCLK_DONE, 100))
 731                 DRM_ERROR("Switching to FCLK failed\n");
 732
 733         val = I915_READ(LCPLL_CTL);
 734         val &= ~LCPLL_CLK_FREQ_MASK;
 735
 736         switch (cdclk) {
 737         default:
 738                 MISSING_CASE(cdclk);
 739                 /* fall through */
 740         case 337500:
 741                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 742                 break;
 743         case 450000:
 744                 val |= LCPLL_CLK_FREQ_450;
 745                 break;
 746         case 540000:
 747                 val |= LCPLL_CLK_FREQ_54O_BDW;
 748                 break;
 749         case 675000:
 750                 val |= LCPLL_CLK_FREQ_675_BDW;
 751                 break;
 752         }
 753
 754         I915_WRITE(LCPLL_CTL, val);
 755
 756         val = I915_READ(LCPLL_CTL);
 757         val &= ~LCPLL_CD_SOURCE_FCLK;
 758         I915_WRITE(LCPLL_CTL, val);
 759
 760         if (wait_for_us((I915_READ(LCPLL_CTL) &
 761                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 762                 DRM_ERROR("Switching back to LCPLL failed\n");
 763
 764         mutex_lock(&dev_priv->pcu_lock);
 765         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
 766                                 cdclk_state->voltage_level);
 767         mutex_unlock(&dev_priv->pcu_lock);
 768
 769         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 770
 771         intel_update_cdclk(dev_priv);
 772 }
 773
 774 static int skl_calc_cdclk(int min_cdclk, int vco)
 775 {
 776         if (vco == 8640000) {
 777                 if (min_cdclk > 540000)
 778                         return 617143;
 779                 else if (min_cdclk > 432000)
 780                         return 540000;
 781                 else if (min_cdclk > 308571)
 782                         return 432000;
 783                 else
 784                         return 308571;
 785         } else {
 786                 if (min_cdclk > 540000)
 787                         return 675000;
 788                 else if (min_cdclk > 450000)
 789                         return 540000;
 790                 else if (min_cdclk > 337500)
 791                         return 450000;
 792                 else
 793                         return 337500;
 794         }
 795 }
 796
 797 static u8 skl_calc_voltage_level(int cdclk)
 798 {
 799         switch (cdclk) {
 800         default:
 801         case 308571:
 802         case 337500:
 803                 return 0;
 804         case 450000:
 805         case 432000:
 806                 return 1;
 807         case 540000:
 808                 return 2;
 809         case 617143:
 810         case 675000:
 811                 return 3;
 812         }
 813 }
 814
 815 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 816                              struct intel_cdclk_state *cdclk_state)
 817 {
 818         u32 val;
 819
 820         cdclk_state->ref = 24000;
 821         cdclk_state->vco = 0;
 822
 823         val = I915_READ(LCPLL1_CTL);
 824         if ((val & LCPLL_PLL_ENABLE) == 0)
 825                 return;
 826
 827         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 828                 return;
 829
 830         val = I915_READ(DPLL_CTRL1);
 831
 832         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 833                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 834                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 835                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 836                 return;
 837
 838         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 839         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 840         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 841         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 842         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 843                 cdclk_state->vco = 8100000;
 844                 break;
 845         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 846         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 847                 cdclk_state->vco = 8640000;
 848                 break;
 849         default:
 850                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 851                 break;
 852         }
 853 }
 854
 855 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 856                           struct intel_cdclk_state *cdclk_state)
 857 {
 858         u32 cdctl;
 859
 860         skl_dpll0_update(dev_priv, cdclk_state);
 861
 862         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
 863
 864         if (cdclk_state->vco == 0)
 865                 goto out;
 866
 867         cdctl = I915_READ(CDCLK_CTL);
 868
 869         if (cdclk_state->vco == 8640000) {
 870                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 871                 case CDCLK_FREQ_450_432:
 872                         cdclk_state->cdclk = 432000;
 873                         break;
 874                 case CDCLK_FREQ_337_308:
 875                         cdclk_state->cdclk = 308571;
 876                         break;
 877                 case CDCLK_FREQ_540:
 878                         cdclk_state->cdclk = 540000;
 879                         break;
 880                 case CDCLK_FREQ_675_617:
 881                         cdclk_state->cdclk = 617143;
 882                         break;
 883                 default:
 884                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 885                         break;
 886                 }
 887         } else {
 888                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 889                 case CDCLK_FREQ_450_432:
 890                         cdclk_state->cdclk = 450000;
 891                         break;
 892                 case CDCLK_FREQ_337_308:
 893                         cdclk_state->cdclk = 337500;
 894                         break;
 895                 case CDCLK_FREQ_540:
 896                         cdclk_state->cdclk = 540000;
 897                         break;
 898                 case CDCLK_FREQ_675_617:
 899                         cdclk_state->cdclk = 675000;
 900                         break;
 901                 default:
 902                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 903                         break;
 904                 }
 905         }
 906
 907  out:
 908         /*
 909          * Can't read this out :( Let's assume it's
 910          * at least what the CDCLK frequency requires.
 911          */
 912         cdclk_state->voltage_level =
 913                 skl_calc_voltage_level(cdclk_state->cdclk);
 914 }
 915
 916 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 917 static int skl_cdclk_decimal(int cdclk)
 918 {
 919         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 920 }
 921
 922 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 923                                         int vco)
 924 {
 925         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 926
 927         dev_priv->skl_preferred_vco_freq = vco;
 928
 929         if (changed)
 930                 intel_update_max_cdclk(dev_priv);
 931 }
 932
 933 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 934 {
 935         u32 val;
 936
 937         WARN_ON(vco != 8100000 && vco != 8640000);
 938
 939         /*
 940          * We always enable DPLL0 with the lowest link rate possible, but still
 941          * taking into account the VCO required to operate the eDP panel at the
 942          * desired frequency. The usual DP link rates operate with a VCO of
 943          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 944          * The modeset code is responsible for the selection of the exact link
 945          * rate later on, with the constraint of choosing a frequency that
 946          * works with vco.
 947          */
 948         val = I915_READ(DPLL_CTRL1);
 949
 950         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 951                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 952         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 953         if (vco == 8640000)
 954                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 955                                             SKL_DPLL0);
 956         else
 957                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 958                                             SKL_DPLL0);
 959
 960         I915_WRITE(DPLL_CTRL1, val);
 961         POSTING_READ(DPLL_CTRL1);
 962
 963         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 964
 965         if (intel_wait_for_register(dev_priv,
 966                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
 967                                     5))
 968                 DRM_ERROR("DPLL0 not locked\n");
 969
 970         dev_priv->cdclk.hw.vco = vco;
 971
 972         /* We'll want to keep using the current vco from now on. */
 973         skl_set_preferred_cdclk_vco(dev_priv, vco);
 974 }
 975
 976 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 977 {
 978         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 979         if (intel_wait_for_register(dev_priv,
 980                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
 981                                    1))
 982                 DRM_ERROR("Couldn't disable DPLL0\n");
 983
 984         dev_priv->cdclk.hw.vco = 0;
 985 }
 986
 987 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 988                           const struct intel_cdclk_state *cdclk_state)
 989 {
 990         int cdclk = cdclk_state->cdclk;
 991         int vco = cdclk_state->vco;
 992         u32 freq_select, cdclk_ctl;
 993         int ret;
 994
 995         /*
 996          * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
 997          * unsupported on SKL. In theory this should never happen since only
 998          * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
 999          * supported on SKL either, see the above WA. WARN whenever trying to
1000          * use the corresponding VCO freq as that always leads to using the
1001          * minimum 308MHz CDCLK.
1002          */
1003         WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000);
1004
1005         mutex_lock(&dev_priv->pcu_lock);
1006         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1007                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1008                                 SKL_CDCLK_READY_FOR_CHANGE,
1009                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1010         mutex_unlock(&dev_priv->pcu_lock);
1011         if (ret) {
1012                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1013                           ret);
1014                 return;
1015         }
1016
1017         /* Choose frequency for this cdclk */
1018         switch (cdclk) {
1019         default:
1020                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1021                 WARN_ON(vco != 0);
1022                 /* fall through */
1023         case 308571:
1024         case 337500:
1025                 freq_select = CDCLK_FREQ_337_308;
1026                 break;
1027         case 450000:
1028         case 432000:
1029                 freq_select = CDCLK_FREQ_450_432;
1030                 break;
1031         case 540000:
1032                 freq_select = CDCLK_FREQ_540;
1033                 break;
1034         case 617143:
1035         case 675000:
1036                 freq_select = CDCLK_FREQ_675_617;
1037                 break;
1038         }
1039
1040         if (dev_priv->cdclk.hw.vco != 0 &&
1041             dev_priv->cdclk.hw.vco != vco)
1042                 skl_dpll0_disable(dev_priv);
1043
1044         cdclk_ctl = I915_READ(CDCLK_CTL);
1045
1046         if (dev_priv->cdclk.hw.vco != vco) {
1047                 /* Wa Display #1183: skl,kbl,cfl */
1048                 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1049                 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1050                 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1051         }
1052
1053         /* Wa Display #1183: skl,kbl,cfl */
1054         cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1055         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1056         POSTING_READ(CDCLK_CTL);
1057
1058         if (dev_priv->cdclk.hw.vco != vco)
1059                 skl_dpll0_enable(dev_priv, vco);
1060
1061         /* Wa Display #1183: skl,kbl,cfl */
1062         cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1063         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1064
1065         cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1066         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1067
1068         /* Wa Display #1183: skl,kbl,cfl */
1069         cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1070         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1071         POSTING_READ(CDCLK_CTL);
1072
1073         /* inform PCU of the change */
1074         mutex_lock(&dev_priv->pcu_lock);
1075         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1076                                 cdclk_state->voltage_level);
1077         mutex_unlock(&dev_priv->pcu_lock);
1078
1079         intel_update_cdclk(dev_priv);
1080 }
1081
1082 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1083 {
1084         uint32_t cdctl, expected;
1085
1086         /*
1087          * check if the pre-os initialized the display
1088          * There is SWF18 scratchpad register defined which is set by the
1089          * pre-os which can be used by the OS drivers to check the status
1090          */
1091         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1092                 goto sanitize;
1093
1094         intel_update_cdclk(dev_priv);
1095         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1096
1097         /* Is PLL enabled and locked ? */
1098         if (dev_priv->cdclk.hw.vco == 0 ||
1099             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1100                 goto sanitize;
1101
1102         /* DPLL okay; verify the cdclock
1103          *
1104          * Noticed in some instances that the freq selection is correct but
1105          * decimal part is programmed wrong from BIOS where pre-os does not
1106          * enable display. Verify the same as well.
1107          */
1108         cdctl = I915_READ(CDCLK_CTL);
1109         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1110                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1111         if (cdctl == expected)
1112                 /* All well; nothing to sanitize */
1113                 return;
1114
1115 sanitize:
1116         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1117
1118         /* force cdclk programming */
1119         dev_priv->cdclk.hw.cdclk = 0;
1120         /* force full PLL disable + enable */
1121         dev_priv->cdclk.hw.vco = -1;
1122 }
1123
1124 /**
1125  * skl_init_cdclk - Initialize CDCLK on SKL
1126  * @dev_priv: i915 device
1127  *
1128  * Initialize CDCLK for SKL and derivatives. This is generally
1129  * done only during the display core initialization sequence,
1130  * after which the DMC will take care of turning CDCLK off/on
1131  * as needed.
1132  */
1133 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1134 {
1135         struct intel_cdclk_state cdclk_state;
1136
1137         skl_sanitize_cdclk(dev_priv);
1138
1139         if (dev_priv->cdclk.hw.cdclk != 0 &&
1140             dev_priv->cdclk.hw.vco != 0) {
1141                 /*
1142                  * Use the current vco as our initial
1143                  * guess as to what the preferred vco is.
1144                  */
1145                 if (dev_priv->skl_preferred_vco_freq == 0)
1146                         skl_set_preferred_cdclk_vco(dev_priv,
1147                                                     dev_priv->cdclk.hw.vco);
1148                 return;
1149         }
1150
1151         cdclk_state = dev_priv->cdclk.hw;
1152
1153         cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1154         if (cdclk_state.vco == 0)
1155                 cdclk_state.vco = 8100000;
1156         cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1157         cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1158
1159         skl_set_cdclk(dev_priv, &cdclk_state);
1160 }
1161
1162 /**
1163  * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1164  * @dev_priv: i915 device
1165  *
1166  * Uninitialize CDCLK for SKL and derivatives. This is done only
1167  * during the display core uninitialization sequence.
1168  */
1169 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1170 {
1171         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1172
1173         cdclk_state.cdclk = cdclk_state.bypass;
1174         cdclk_state.vco = 0;
1175         cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1176
1177         skl_set_cdclk(dev_priv, &cdclk_state);
1178 }
1179
1180 static int bxt_calc_cdclk(int min_cdclk)
1181 {
1182         if (min_cdclk > 576000)
1183                 return 624000;
1184         else if (min_cdclk > 384000)
1185                 return 576000;
1186         else if (min_cdclk > 288000)
1187                 return 384000;
1188         else if (min_cdclk > 144000)
1189                 return 288000;
1190         else
1191                 return 144000;
1192 }
1193
1194 static int glk_calc_cdclk(int min_cdclk)
1195 {
1196         if (min_cdclk > 158400)
1197                 return 316800;
1198         else if (min_cdclk > 79200)
1199                 return 158400;
1200         else
1201                 return 79200;
1202 }
1203
1204 static u8 bxt_calc_voltage_level(int cdclk)
1205 {
1206         return DIV_ROUND_UP(cdclk, 25000);
1207 }
1208
1209 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1210 {
1211         int ratio;
1212
1213         if (cdclk == dev_priv->cdclk.hw.bypass)
1214                 return 0;
1215
1216         switch (cdclk) {
1217         default:
1218                 MISSING_CASE(cdclk);
1219                 /* fall through */
1220         case 144000:
1221         case 288000:
1222         case 384000:
1223         case 576000:
1224                 ratio = 60;
1225                 break;
1226         case 624000:
1227                 ratio = 65;
1228                 break;
1229         }
1230
1231         return dev_priv->cdclk.hw.ref * ratio;
1232 }
1233
1234 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1235 {
1236         int ratio;
1237
1238         if (cdclk == dev_priv->cdclk.hw.bypass)
1239                 return 0;
1240
1241         switch (cdclk) {
1242         default:
1243                 MISSING_CASE(cdclk);
1244                 /* fall through */
1245         case  79200:
1246         case 158400:
1247         case 316800:
1248                 ratio = 33;
1249                 break;
1250         }
1251
1252         return dev_priv->cdclk.hw.ref * ratio;
1253 }
1254
1255 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1256                               struct intel_cdclk_state *cdclk_state)
1257 {
1258         u32 val;
1259
1260         cdclk_state->ref = 19200;
1261         cdclk_state->vco = 0;
1262
1263         val = I915_READ(BXT_DE_PLL_ENABLE);
1264         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1265                 return;
1266
1267         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1268                 return;
1269
1270         val = I915_READ(BXT_DE_PLL_CTL);
1271         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1272 }
1273
1274 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1275                           struct intel_cdclk_state *cdclk_state)
1276 {
1277         u32 divider;
1278         int div;
1279
1280         bxt_de_pll_update(dev_priv, cdclk_state);
1281
1282         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1283
1284         if (cdclk_state->vco == 0)
1285                 goto out;
1286
1287         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1288
1289         switch (divider) {
1290         case BXT_CDCLK_CD2X_DIV_SEL_1:
1291                 div = 2;
1292                 break;
1293         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1294                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1295                 div = 3;
1296                 break;
1297         case BXT_CDCLK_CD2X_DIV_SEL_2:
1298                 div = 4;
1299                 break;
1300         case BXT_CDCLK_CD2X_DIV_SEL_4:
1301                 div = 8;
1302                 break;
1303         default:
1304                 MISSING_CASE(divider);
1305                 return;
1306         }
1307
1308         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1309
1310  out:
1311         /*
1312          * Can't read this out :( Let's assume it's
1313          * at least what the CDCLK frequency requires.
1314          */
1315         cdclk_state->voltage_level =
1316                 bxt_calc_voltage_level(cdclk_state->cdclk);
1317 }
1318
1319 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1320 {
1321         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1322
1323         /* Timeout 200us */
1324         if (intel_wait_for_register(dev_priv,
1325                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1326                                     1))
1327                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1328
1329         dev_priv->cdclk.hw.vco = 0;
1330 }
1331
1332 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1333 {
1334         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1335         u32 val;
1336
1337         val = I915_READ(BXT_DE_PLL_CTL);
1338         val &= ~BXT_DE_PLL_RATIO_MASK;
1339         val |= BXT_DE_PLL_RATIO(ratio);
1340         I915_WRITE(BXT_DE_PLL_CTL, val);
1341
1342         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1343
1344         /* Timeout 200us */
1345         if (intel_wait_for_register(dev_priv,
1346                                     BXT_DE_PLL_ENABLE,
1347                                     BXT_DE_PLL_LOCK,
1348                                     BXT_DE_PLL_LOCK,
1349                                     1))
1350                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1351
1352         dev_priv->cdclk.hw.vco = vco;
1353 }
1354
1355 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1356                           const struct intel_cdclk_state *cdclk_state)
1357 {
1358         int cdclk = cdclk_state->cdclk;
1359         int vco = cdclk_state->vco;
1360         u32 val, divider;
1361         int ret;
1362
1363         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1364         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1365         default:
1366                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1367                 WARN_ON(vco != 0);
1368                 /* fall through */
1369         case 2:
1370                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1371                 break;
1372         case 3:
1373                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1374                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1375                 break;
1376         case 4:
1377                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1378                 break;
1379         case 8:
1380                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1381                 break;
1382         }
1383
1384         /*
1385          * Inform power controller of upcoming frequency change. BSpec
1386          * requires us to wait up to 150usec, but that leads to timeouts;
1387          * the 2ms used here is based on experiment.
1388          */
1389         mutex_lock(&dev_priv->pcu_lock);
1390         ret = sandybridge_pcode_write_timeout(dev_priv,
1391                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1392                                               0x80000000, 150, 2);
1393         mutex_unlock(&dev_priv->pcu_lock);
1394
1395         if (ret) {
1396                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1397                           ret, cdclk);
1398                 return;
1399         }
1400
1401         if (dev_priv->cdclk.hw.vco != 0 &&
1402             dev_priv->cdclk.hw.vco != vco)
1403                 bxt_de_pll_disable(dev_priv);
1404
1405         if (dev_priv->cdclk.hw.vco != vco)
1406                 bxt_de_pll_enable(dev_priv, vco);
1407
1408         val = divider | skl_cdclk_decimal(cdclk);
1409         /*
1410          * FIXME if only the cd2x divider needs changing, it could be done
1411          * without shutting off the pipe (if only one pipe is active).
1412          */
1413         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1414         /*
1415          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1416          * enable otherwise.
1417          */
1418         if (cdclk >= 500000)
1419                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1420         I915_WRITE(CDCLK_CTL, val);
1421
1422         mutex_lock(&dev_priv->pcu_lock);
1423         /*
1424          * The timeout isn't specified, the 2ms used here is based on
1425          * experiment.
1426          * FIXME: Waiting for the request completion could be delayed until
1427          * the next PCODE request based on BSpec.
1428          */
1429         ret = sandybridge_pcode_write_timeout(dev_priv,
1430                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1431                                               cdclk_state->voltage_level, 150, 2);
1432         mutex_unlock(&dev_priv->pcu_lock);
1433
1434         if (ret) {
1435                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1436                           ret, cdclk);
1437                 return;
1438         }
1439
1440         intel_update_cdclk(dev_priv);
1441 }
1442
1443 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1444 {
1445         u32 cdctl, expected;
1446
1447         intel_update_cdclk(dev_priv);
1448         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1449
1450         if (dev_priv->cdclk.hw.vco == 0 ||
1451             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1452                 goto sanitize;
1453
1454         /* DPLL okay; verify the cdclock
1455          *
1456          * Some BIOS versions leave an incorrect decimal frequency value and
1457          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1458          * so sanitize this register.
1459          */
1460         cdctl = I915_READ(CDCLK_CTL);
1461         /*
1462          * Let's ignore the pipe field, since BIOS could have configured the
1463          * dividers both synching to an active pipe, or asynchronously
1464          * (PIPE_NONE).
1465          */
1466         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1467
1468         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1469                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1470         /*
1471          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1472          * enable otherwise.
1473          */
1474         if (dev_priv->cdclk.hw.cdclk >= 500000)
1475                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1476
1477         if (cdctl == expected)
1478                 /* All well; nothing to sanitize */
1479                 return;
1480
1481 sanitize:
1482         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1483
1484         /* force cdclk programming */
1485         dev_priv->cdclk.hw.cdclk = 0;
1486
1487         /* force full PLL disable + enable */
1488         dev_priv->cdclk.hw.vco = -1;
1489 }
1490
1491 /**
1492  * bxt_init_cdclk - Initialize CDCLK on BXT
1493  * @dev_priv: i915 device
1494  *
1495  * Initialize CDCLK for BXT and derivatives. This is generally
1496  * done only during the display core initialization sequence,
1497  * after which the DMC will take care of turning CDCLK off/on
1498  * as needed.
1499  */
1500 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1501 {
1502         struct intel_cdclk_state cdclk_state;
1503
1504         bxt_sanitize_cdclk(dev_priv);
1505
1506         if (dev_priv->cdclk.hw.cdclk != 0 &&
1507             dev_priv->cdclk.hw.vco != 0)
1508                 return;
1509
1510         cdclk_state = dev_priv->cdclk.hw;
1511
1512         /*
1513          * FIXME:
1514          * - The initial CDCLK needs to be read from VBT.
1515          *   Need to make this change after VBT has changes for BXT.
1516          */
1517         if (IS_GEMINILAKE(dev_priv)) {
1518                 cdclk_state.cdclk = glk_calc_cdclk(0);
1519                 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1520         } else {
1521                 cdclk_state.cdclk = bxt_calc_cdclk(0);
1522                 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1523         }
1524         cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1525
1526         bxt_set_cdclk(dev_priv, &cdclk_state);
1527 }
1528
1529 /**
1530  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1531  * @dev_priv: i915 device
1532  *
1533  * Uninitialize CDCLK for BXT and derivatives. This is done only
1534  * during the display core uninitialization sequence.
1535  */
1536 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1537 {
1538         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1539
1540         cdclk_state.cdclk = cdclk_state.bypass;
1541         cdclk_state.vco = 0;
1542         cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1543
1544         bxt_set_cdclk(dev_priv, &cdclk_state);
1545 }
1546
1547 static int cnl_calc_cdclk(int min_cdclk)
1548 {
1549         if (min_cdclk > 336000)
1550                 return 528000;
1551         else if (min_cdclk > 168000)
1552                 return 336000;
1553         else
1554                 return 168000;
1555 }
1556
1557 static u8 cnl_calc_voltage_level(int cdclk)
1558 {
1559         switch (cdclk) {
1560         default:
1561         case 168000:
1562                 return 0;
1563         case 336000:
1564                 return 1;
1565         case 528000:
1566                 return 2;
1567         }
1568 }
1569
1570 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1571                                  struct intel_cdclk_state *cdclk_state)
1572 {
1573         u32 val;
1574
1575         if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1576                 cdclk_state->ref = 24000;
1577         else
1578                 cdclk_state->ref = 19200;
1579
1580         cdclk_state->vco = 0;
1581
1582         val = I915_READ(BXT_DE_PLL_ENABLE);
1583         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1584                 return;
1585
1586         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1587                 return;
1588
1589         cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1590 }
1591
1592 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1593                          struct intel_cdclk_state *cdclk_state)
1594 {
1595         u32 divider;
1596         int div;
1597
1598         cnl_cdclk_pll_update(dev_priv, cdclk_state);
1599
1600         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1601
1602         if (cdclk_state->vco == 0)
1603                 goto out;
1604
1605         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1606
1607         switch (divider) {
1608         case BXT_CDCLK_CD2X_DIV_SEL_1:
1609                 div = 2;
1610                 break;
1611         case BXT_CDCLK_CD2X_DIV_SEL_2:
1612                 div = 4;
1613                 break;
1614         default:
1615                 MISSING_CASE(divider);
1616                 return;
1617         }
1618
1619         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1620
1621  out:
1622         /*
1623          * Can't read this out :( Let's assume it's
1624          * at least what the CDCLK frequency requires.
1625          */
1626         cdclk_state->voltage_level =
1627                 cnl_calc_voltage_level(cdclk_state->cdclk);
1628 }
1629
1630 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1631 {
1632         u32 val;
1633
1634         val = I915_READ(BXT_DE_PLL_ENABLE);
1635         val &= ~BXT_DE_PLL_PLL_ENABLE;
1636         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1637
1638         /* Timeout 200us */
1639         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1640                 DRM_ERROR("timeout waiting for CDCLK PLL unlock\n");
1641
1642         dev_priv->cdclk.hw.vco = 0;
1643 }
1644
1645 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1646 {
1647         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1648         u32 val;
1649
1650         val = CNL_CDCLK_PLL_RATIO(ratio);
1651         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1652
1653         val |= BXT_DE_PLL_PLL_ENABLE;
1654         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1655
1656         /* Timeout 200us */
1657         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1658                 DRM_ERROR("timeout waiting for CDCLK PLL lock\n");
1659
1660         dev_priv->cdclk.hw.vco = vco;
1661 }
1662
1663 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1664                           const struct intel_cdclk_state *cdclk_state)
1665 {
1666         int cdclk = cdclk_state->cdclk;
1667         int vco = cdclk_state->vco;
1668         u32 val, divider;
1669         int ret;
1670
1671         mutex_lock(&dev_priv->pcu_lock);
1672         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1673                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1674                                 SKL_CDCLK_READY_FOR_CHANGE,
1675                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1676         mutex_unlock(&dev_priv->pcu_lock);
1677         if (ret) {
1678                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1679                           ret);
1680                 return;
1681         }
1682
1683         /* cdclk = vco / 2 / div{1,2} */
1684         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1685         default:
1686                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1687                 WARN_ON(vco != 0);
1688                 /* fall through */
1689         case 2:
1690                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1691                 break;
1692         case 4:
1693                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1694                 break;
1695         }
1696
1697         if (dev_priv->cdclk.hw.vco != 0 &&
1698             dev_priv->cdclk.hw.vco != vco)
1699                 cnl_cdclk_pll_disable(dev_priv);
1700
1701         if (dev_priv->cdclk.hw.vco != vco)
1702                 cnl_cdclk_pll_enable(dev_priv, vco);
1703
1704         val = divider | skl_cdclk_decimal(cdclk);
1705         /*
1706          * FIXME if only the cd2x divider needs changing, it could be done
1707          * without shutting off the pipe (if only one pipe is active).
1708          */
1709         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1710         I915_WRITE(CDCLK_CTL, val);
1711
1712         /* inform PCU of the change */
1713         mutex_lock(&dev_priv->pcu_lock);
1714         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1715                                 cdclk_state->voltage_level);
1716         mutex_unlock(&dev_priv->pcu_lock);
1717
1718         intel_update_cdclk(dev_priv);
1719
1720         /*
1721          * Can't read out the voltage level :(
1722          * Let's just assume everything is as expected.
1723          */
1724         dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1725 }
1726
1727 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1728 {
1729         int ratio;
1730
1731         if (cdclk == dev_priv->cdclk.hw.bypass)
1732                 return 0;
1733
1734         switch (cdclk) {
1735         default:
1736                 MISSING_CASE(cdclk);
1737                 /* fall through */
1738         case 168000:
1739         case 336000:
1740                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1741                 break;
1742         case 528000:
1743                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1744                 break;
1745         }
1746
1747         return dev_priv->cdclk.hw.ref * ratio;
1748 }
1749
1750 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1751 {
1752         u32 cdctl, expected;
1753
1754         intel_update_cdclk(dev_priv);
1755         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1756
1757         if (dev_priv->cdclk.hw.vco == 0 ||
1758             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1759                 goto sanitize;
1760
1761         /* DPLL okay; verify the cdclock
1762          *
1763          * Some BIOS versions leave an incorrect decimal frequency value and
1764          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1765          * so sanitize this register.
1766          */
1767         cdctl = I915_READ(CDCLK_CTL);
1768         /*
1769          * Let's ignore the pipe field, since BIOS could have configured the
1770          * dividers both synching to an active pipe, or asynchronously
1771          * (PIPE_NONE).
1772          */
1773         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1774
1775         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1776                    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1777
1778         if (cdctl == expected)
1779                 /* All well; nothing to sanitize */
1780                 return;
1781
1782 sanitize:
1783         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1784
1785         /* force cdclk programming */
1786         dev_priv->cdclk.hw.cdclk = 0;
1787
1788         /* force full PLL disable + enable */
1789         dev_priv->cdclk.hw.vco = -1;
1790 }
1791
1792 static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
1793 {
1794         int ranges_24[] = { 312000, 552000, 648000 };
1795         int ranges_19_38[] = { 307200, 556800, 652800 };
1796         int *ranges;
1797
1798         switch (ref) {
1799         default:
1800                 MISSING_CASE(ref);
1801                 /* fall through */
1802         case 24000:
1803                 ranges = ranges_24;
1804                 break;
1805         case 19200:
1806         case 38400:
1807                 ranges = ranges_19_38;
1808                 break;
1809         }
1810
1811         if (min_cdclk > ranges[1])
1812                 return ranges[2];
1813         else if (min_cdclk > ranges[0])
1814                 return ranges[1];
1815         else
1816                 return ranges[0];
1817 }
1818
1819 static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1820 {
1821         int ratio;
1822
1823         if (cdclk == dev_priv->cdclk.hw.bypass)
1824                 return 0;
1825
1826         switch (cdclk) {
1827         default:
1828                 MISSING_CASE(cdclk);
1829                 /* fall through */
1830         case 307200:
1831         case 556800:
1832         case 652800:
1833                 WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
1834                         dev_priv->cdclk.hw.ref != 38400);
1835                 break;
1836         case 312000:
1837         case 552000:
1838         case 648000:
1839                 WARN_ON(dev_priv->cdclk.hw.ref != 24000);
1840         }
1841
1842         ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
1843
1844         return dev_priv->cdclk.hw.ref * ratio;
1845 }
1846
1847 static void icl_set_cdclk(struct drm_i915_private *dev_priv,
1848                           const struct intel_cdclk_state *cdclk_state)
1849 {
1850         unsigned int cdclk = cdclk_state->cdclk;
1851         unsigned int vco = cdclk_state->vco;
1852         int ret;
1853
1854         mutex_lock(&dev_priv->pcu_lock);
1855         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1856                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1857                                 SKL_CDCLK_READY_FOR_CHANGE,
1858                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1859         mutex_unlock(&dev_priv->pcu_lock);
1860         if (ret) {
1861                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1862                           ret);
1863                 return;
1864         }
1865
1866         if (dev_priv->cdclk.hw.vco != 0 &&
1867             dev_priv->cdclk.hw.vco != vco)
1868                 cnl_cdclk_pll_disable(dev_priv);
1869
1870         if (dev_priv->cdclk.hw.vco != vco)
1871                 cnl_cdclk_pll_enable(dev_priv, vco);
1872
1873         I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
1874                               skl_cdclk_decimal(cdclk));
1875
1876         mutex_lock(&dev_priv->pcu_lock);
1877         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1878                                 cdclk_state->voltage_level);
1879         mutex_unlock(&dev_priv->pcu_lock);
1880
1881         intel_update_cdclk(dev_priv);
1882
1883         /*
1884          * Can't read out the voltage level :(
1885          * Let's just assume everything is as expected.
1886          */
1887         dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1888 }
1889
1890 static u8 icl_calc_voltage_level(int cdclk)
1891 {
1892         switch (cdclk) {
1893         case 50000:
1894         case 307200:
1895         case 312000:
1896                 return 0;
1897         case 556800:
1898         case 552000:
1899                 return 1;
1900         default:
1901                 MISSING_CASE(cdclk);
1902                 /* fall through */
1903         case 652800:
1904         case 648000:
1905                 return 2;
1906         }
1907 }
1908
1909 static void icl_get_cdclk(struct drm_i915_private *dev_priv,
1910                           struct intel_cdclk_state *cdclk_state)
1911 {
1912         u32 val;
1913
1914         cdclk_state->bypass = 50000;
1915
1916         val = I915_READ(SKL_DSSM);
1917         switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
1918         default:
1919                 MISSING_CASE(val);
1920                 /* fall through */
1921         case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1922                 cdclk_state->ref = 24000;
1923                 break;
1924         case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1925                 cdclk_state->ref = 19200;
1926                 break;
1927         case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1928                 cdclk_state->ref = 38400;
1929                 break;
1930         }
1931
1932         val = I915_READ(BXT_DE_PLL_ENABLE);
1933         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1934             (val & BXT_DE_PLL_LOCK) == 0) {
1935                 /*
1936                  * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1937                  * setting it to zero is a way to signal that.
1938                  */
1939                 cdclk_state->vco = 0;
1940                 cdclk_state->cdclk = cdclk_state->bypass;
1941                 goto out;
1942         }
1943
1944         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1945
1946         val = I915_READ(CDCLK_CTL);
1947         WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
1948
1949         cdclk_state->cdclk = cdclk_state->vco / 2;
1950
1951 out:
1952         /*
1953          * Can't read this out :( Let's assume it's
1954          * at least what the CDCLK frequency requires.
1955          */
1956         cdclk_state->voltage_level =
1957                 icl_calc_voltage_level(cdclk_state->cdclk);
1958 }
1959
1960 /**
1961  * icl_init_cdclk - Initialize CDCLK on ICL
1962  * @dev_priv: i915 device
1963  *
1964  * Initialize CDCLK for ICL. This consists mainly of initializing
1965  * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
1966  * is generally done only during the display core initialization sequence, after
1967  * which the DMC will take care of turning CDCLK off/on as needed.
1968  */
1969 void icl_init_cdclk(struct drm_i915_private *dev_priv)
1970 {
1971         struct intel_cdclk_state sanitized_state;
1972         u32 val;
1973
1974         /* This sets dev_priv->cdclk.hw. */
1975         intel_update_cdclk(dev_priv);
1976         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1977
1978         /* This means CDCLK disabled. */
1979         if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1980                 goto sanitize;
1981
1982         val = I915_READ(CDCLK_CTL);
1983
1984         if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
1985                 goto sanitize;
1986
1987         if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
1988             skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
1989                 goto sanitize;
1990
1991         return;
1992
1993 sanitize:
1994         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1995
1996         sanitized_state.ref = dev_priv->cdclk.hw.ref;
1997         sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
1998         sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
1999                                                      sanitized_state.cdclk);
2000         sanitized_state.voltage_level =
2001                                 icl_calc_voltage_level(sanitized_state.cdclk);
2002
2003         icl_set_cdclk(dev_priv, &sanitized_state);
2004 }
2005
2006 /**
2007  * icl_uninit_cdclk - Uninitialize CDCLK on ICL
2008  * @dev_priv: i915 device
2009  *
2010  * Uninitialize CDCLK for ICL. This is done only during the display core
2011  * uninitialization sequence.
2012  */
2013 void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
2014 {
2015         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
2016
2017         cdclk_state.cdclk = cdclk_state.bypass;
2018         cdclk_state.vco = 0;
2019         cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
2020
2021         icl_set_cdclk(dev_priv, &cdclk_state);
2022 }
2023
2024 /**
2025  * cnl_init_cdclk - Initialize CDCLK on CNL
2026  * @dev_priv: i915 device
2027  *
2028  * Initialize CDCLK for CNL. This is generally
2029  * done only during the display core initialization sequence,
2030  * after which the DMC will take care of turning CDCLK off/on
2031  * as needed.
2032  */
2033 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
2034 {
2035         struct intel_cdclk_state cdclk_state;
2036
2037         cnl_sanitize_cdclk(dev_priv);
2038
2039         if (dev_priv->cdclk.hw.cdclk != 0 &&
2040             dev_priv->cdclk.hw.vco != 0)
2041                 return;
2042
2043         cdclk_state = dev_priv->cdclk.hw;
2044
2045         cdclk_state.cdclk = cnl_calc_cdclk(0);
2046         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
2047         cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
2048
2049         cnl_set_cdclk(dev_priv, &cdclk_state);
2050 }
2051
2052 /**
2053  * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
2054  * @dev_priv: i915 device
2055  *
2056  * Uninitialize CDCLK for CNL. This is done only
2057  * during the display core uninitialization sequence.
2058  */
2059 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
2060 {
2061         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
2062
2063         cdclk_state.cdclk = cdclk_state.bypass;
2064         cdclk_state.vco = 0;
2065         cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
2066
2067         cnl_set_cdclk(dev_priv, &cdclk_state);
2068 }
2069
2070 /**
2071  * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
2072  * @a: first CDCLK state
2073  * @b: second CDCLK state
2074  *
2075  * Returns:
2076  * True if the CDCLK states require pipes to be off during reprogramming, false if not.
2077  */
2078 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
2079                                const struct intel_cdclk_state *b)
2080 {
2081         return a->cdclk != b->cdclk ||
2082                 a->vco != b->vco ||
2083                 a->ref != b->ref;
2084 }
2085
2086 /**
2087  * intel_cdclk_changed - Determine if two CDCLK states are different
2088  * @a: first CDCLK state
2089  * @b: second CDCLK state
2090  *
2091  * Returns:
2092  * True if the CDCLK states don't match, false if they do.
2093  */
2094 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
2095                          const struct intel_cdclk_state *b)
2096 {
2097         return intel_cdclk_needs_modeset(a, b) ||
2098                 a->voltage_level != b->voltage_level;
2099 }
2100
2101 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
2102                             const char *context)
2103 {
2104         DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2105                          context, cdclk_state->cdclk, cdclk_state->vco,
2106                          cdclk_state->ref, cdclk_state->bypass,
2107                          cdclk_state->voltage_level);
2108 }
2109
2110 /**
2111  * intel_set_cdclk - Push the CDCLK state to the hardware
2112  * @dev_priv: i915 device
2113  * @cdclk_state: new CDCLK state
2114  *
2115  * Program the hardware based on the passed in CDCLK state,
2116  * if necessary.
2117  */
2118 void intel_set_cdclk(struct drm_i915_private *dev_priv,
2119                      const struct intel_cdclk_state *cdclk_state)
2120 {
2121         if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
2122                 return;
2123
2124         if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
2125                 return;
2126
2127         intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
2128
2129         dev_priv->display.set_cdclk(dev_priv, cdclk_state);
2130
2131         if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
2132                  "cdclk state doesn't match!\n")) {
2133                 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
2134                 intel_dump_cdclk_state(cdclk_state, "[sw state]");
2135         }
2136 }
2137
2138 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
2139                                      int pixel_rate)
2140 {
2141         if (INTEL_GEN(dev_priv) >= 10)
2142                 return DIV_ROUND_UP(pixel_rate, 2);
2143         else if (IS_GEMINILAKE(dev_priv))
2144                 /*
2145                  * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
2146                  * as a temporary workaround. Use a higher cdclk instead. (Note that
2147                  * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
2148                  * cdclk.)
2149                  */
2150                 return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
2151         else if (IS_GEN9(dev_priv) ||
2152                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2153                 return pixel_rate;
2154         else if (IS_CHERRYVIEW(dev_priv))
2155                 return DIV_ROUND_UP(pixel_rate * 100, 95);
2156         else
2157                 return DIV_ROUND_UP(pixel_rate * 100, 90);
2158 }
2159
2160 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2161 {
2162         struct drm_i915_private *dev_priv =
2163                 to_i915(crtc_state->base.crtc->dev);
2164         int min_cdclk;
2165
2166         if (!crtc_state->base.enable)
2167                 return 0;
2168
2169         min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
2170
2171         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2172         if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2173                 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2174
2175         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2176          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2177          * there may be audio corruption or screen corruption." This cdclk
2178          * restriction for GLK is 316.8 MHz.
2179          */
2180         if (intel_crtc_has_dp_encoder(crtc_state) &&
2181             crtc_state->has_audio &&
2182             crtc_state->port_clock >= 540000 &&
2183             crtc_state->lane_count == 4) {
2184                 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2185                         /* Display WA #1145: glk,cnl */
2186                         min_cdclk = max(316800, min_cdclk);
2187                 } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
2188                         /* Display WA #1144: skl,bxt */
2189                         min_cdclk = max(432000, min_cdclk);
2190                 }
2191         }
2192
2193         /*
2194          * According to BSpec, "The CD clock frequency must be at least twice
2195          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2196          *
2197          * FIXME: Check the actual, not default, BCLK being used.
2198          *
2199          * FIXME: This does not depend on ->has_audio because the higher CDCLK
2200          * is required for audio probe, also when there are no audio capable
2201          * displays connected at probe time. This leads to unnecessarily high
2202          * CDCLK when audio is not required.
2203          *
2204          * FIXME: This limit is only applied when there are displays connected
2205          * at probe time. If we probe without displays, we'll still end up using
2206          * the platform minimum CDCLK, failing audio probe.
2207          */
2208         if (INTEL_GEN(dev_priv) >= 9)
2209                 min_cdclk = max(2 * 96000, min_cdclk);
2210
2211         /*
2212          * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2213          * than 320000KHz.
2214          */
2215         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2216             IS_VALLEYVIEW(dev_priv))
2217                 min_cdclk = max(320000, min_cdclk);
2218
2219         if (min_cdclk > dev_priv->max_cdclk_freq) {
2220                 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
2221                               min_cdclk, dev_priv->max_cdclk_freq);
2222                 return -EINVAL;
2223         }
2224
2225         return min_cdclk;
2226 }
2227
2228 static int intel_compute_min_cdclk(struct drm_atomic_state *state)
2229 {
2230         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2231         struct drm_i915_private *dev_priv = to_i915(state->dev);
2232         struct intel_crtc *crtc;
2233         struct intel_crtc_state *crtc_state;
2234         int min_cdclk, i;
2235         enum pipe pipe;
2236
2237         memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
2238                sizeof(intel_state->min_cdclk));
2239
2240         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2241                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2242                 if (min_cdclk < 0)
2243                         return min_cdclk;
2244
2245                 intel_state->min_cdclk[i] = min_cdclk;
2246         }
2247
2248         min_cdclk = 0;
2249         for_each_pipe(dev_priv, pipe)
2250                 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
2251
2252         return min_cdclk;
2253 }
2254
2255 /*
2256  * Note that this functions assumes that 0 is
2257  * the lowest voltage value, and higher values
2258  * correspond to increasingly higher voltages.
2259  *
2260  * Should that relationship no longer hold on
2261  * future platforms this code will need to be
2262  * adjusted.
2263  */
2264 static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
2265 {
2266         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2267         struct intel_crtc *crtc;
2268         struct intel_crtc_state *crtc_state;
2269         u8 min_voltage_level;
2270         int i;
2271         enum pipe pipe;
2272
2273         memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
2274                sizeof(state->min_voltage_level));
2275
2276         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2277                 if (crtc_state->base.enable)
2278                         state->min_voltage_level[i] =
2279                                 crtc_state->min_voltage_level;
2280                 else
2281                         state->min_voltage_level[i] = 0;
2282         }
2283
2284         min_voltage_level = 0;
2285         for_each_pipe(dev_priv, pipe)
2286                 min_voltage_level = max(state->min_voltage_level[pipe],
2287                                         min_voltage_level);
2288
2289         return min_voltage_level;
2290 }
2291
2292 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
2293 {
2294         struct drm_i915_private *dev_priv = to_i915(state->dev);
2295         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2296         int min_cdclk, cdclk;
2297
2298         min_cdclk = intel_compute_min_cdclk(state);
2299         if (min_cdclk < 0)
2300                 return min_cdclk;
2301
2302         cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2303
2304         intel_state->cdclk.logical.cdclk = cdclk;
2305         intel_state->cdclk.logical.voltage_level =
2306                 vlv_calc_voltage_level(dev_priv, cdclk);
2307
2308         if (!intel_state->active_crtcs) {
2309                 cdclk = vlv_calc_cdclk(dev_priv, 0);
2310
2311                 intel_state->cdclk.actual.cdclk = cdclk;
2312                 intel_state->cdclk.actual.voltage_level =
2313                         vlv_calc_voltage_level(dev_priv, cdclk);
2314         } else {
2315                 intel_state->cdclk.actual =
2316                         intel_state->cdclk.logical;
2317         }
2318
2319         return 0;
2320 }
2321
2322 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
2323 {
2324         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2325         int min_cdclk, cdclk;
2326
2327         min_cdclk = intel_compute_min_cdclk(state);
2328         if (min_cdclk < 0)
2329                 return min_cdclk;
2330
2331         /*
2332          * FIXME should also account for plane ratio
2333          * once 64bpp pixel formats are supported.
2334          */
2335         cdclk = bdw_calc_cdclk(min_cdclk);
2336
2337         intel_state->cdclk.logical.cdclk = cdclk;
2338         intel_state->cdclk.logical.voltage_level =
2339                 bdw_calc_voltage_level(cdclk);
2340
2341         if (!intel_state->active_crtcs) {
2342                 cdclk = bdw_calc_cdclk(0);
2343
2344                 intel_state->cdclk.actual.cdclk = cdclk;
2345                 intel_state->cdclk.actual.voltage_level =
2346                         bdw_calc_voltage_level(cdclk);
2347         } else {
2348                 intel_state->cdclk.actual =
2349                         intel_state->cdclk.logical;
2350         }
2351
2352         return 0;
2353 }
2354
2355 static int skl_dpll0_vco(struct intel_atomic_state *intel_state)
2356 {
2357         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
2358         struct intel_crtc *crtc;
2359         struct intel_crtc_state *crtc_state;
2360         int vco, i;
2361
2362         vco = intel_state->cdclk.logical.vco;
2363         if (!vco)
2364                 vco = dev_priv->skl_preferred_vco_freq;
2365
2366         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2367                 if (!crtc_state->base.enable)
2368                         continue;
2369
2370                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2371                         continue;
2372
2373                 /*
2374                  * DPLL0 VCO may need to be adjusted to get the correct
2375                  * clock for eDP. This will affect cdclk as well.
2376                  */
2377                 switch (crtc_state->port_clock / 2) {
2378                 case 108000:
2379                 case 216000:
2380                         vco = 8640000;
2381                         break;
2382                 default:
2383                         vco = 8100000;
2384                         break;
2385                 }
2386         }
2387
2388         return vco;
2389 }
2390
2391 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
2392 {
2393         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2394         int min_cdclk, cdclk, vco;
2395
2396         min_cdclk = intel_compute_min_cdclk(state);
2397         if (min_cdclk < 0)
2398                 return min_cdclk;
2399
2400         vco = skl_dpll0_vco(intel_state);
2401
2402         /*
2403          * FIXME should also account for plane ratio
2404          * once 64bpp pixel formats are supported.
2405          */
2406         cdclk = skl_calc_cdclk(min_cdclk, vco);
2407
2408         intel_state->cdclk.logical.vco = vco;
2409         intel_state->cdclk.logical.cdclk = cdclk;
2410         intel_state->cdclk.logical.voltage_level =
2411                 skl_calc_voltage_level(cdclk);
2412
2413         if (!intel_state->active_crtcs) {
2414                 cdclk = skl_calc_cdclk(0, vco);
2415
2416                 intel_state->cdclk.actual.vco = vco;
2417                 intel_state->cdclk.actual.cdclk = cdclk;
2418                 intel_state->cdclk.actual.voltage_level =
2419                         skl_calc_voltage_level(cdclk);
2420         } else {
2421                 intel_state->cdclk.actual =
2422                         intel_state->cdclk.logical;
2423         }
2424
2425         return 0;
2426 }
2427
2428 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
2429 {
2430         struct drm_i915_private *dev_priv = to_i915(state->dev);
2431         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2432         int min_cdclk, cdclk, vco;
2433
2434         min_cdclk = intel_compute_min_cdclk(state);
2435         if (min_cdclk < 0)
2436                 return min_cdclk;
2437
2438         if (IS_GEMINILAKE(dev_priv)) {
2439                 cdclk = glk_calc_cdclk(min_cdclk);
2440                 vco = glk_de_pll_vco(dev_priv, cdclk);
2441         } else {
2442                 cdclk = bxt_calc_cdclk(min_cdclk);
2443                 vco = bxt_de_pll_vco(dev_priv, cdclk);
2444         }
2445
2446         intel_state->cdclk.logical.vco = vco;
2447         intel_state->cdclk.logical.cdclk = cdclk;
2448         intel_state->cdclk.logical.voltage_level =
2449                 bxt_calc_voltage_level(cdclk);
2450
2451         if (!intel_state->active_crtcs) {
2452                 if (IS_GEMINILAKE(dev_priv)) {
2453                         cdclk = glk_calc_cdclk(0);
2454                         vco = glk_de_pll_vco(dev_priv, cdclk);
2455                 } else {
2456                         cdclk = bxt_calc_cdclk(0);
2457                         vco = bxt_de_pll_vco(dev_priv, cdclk);
2458                 }
2459
2460                 intel_state->cdclk.actual.vco = vco;
2461                 intel_state->cdclk.actual.cdclk = cdclk;
2462                 intel_state->cdclk.actual.voltage_level =
2463                         bxt_calc_voltage_level(cdclk);
2464         } else {
2465                 intel_state->cdclk.actual =
2466                         intel_state->cdclk.logical;
2467         }
2468
2469         return 0;
2470 }
2471
2472 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
2473 {
2474         struct drm_i915_private *dev_priv = to_i915(state->dev);
2475         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2476         int min_cdclk, cdclk, vco;
2477
2478         min_cdclk = intel_compute_min_cdclk(state);
2479         if (min_cdclk < 0)
2480                 return min_cdclk;
2481
2482         cdclk = cnl_calc_cdclk(min_cdclk);
2483         vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2484
2485         intel_state->cdclk.logical.vco = vco;
2486         intel_state->cdclk.logical.cdclk = cdclk;
2487         intel_state->cdclk.logical.voltage_level =
2488                 max(cnl_calc_voltage_level(cdclk),
2489                     cnl_compute_min_voltage_level(intel_state));
2490
2491         if (!intel_state->active_crtcs) {
2492                 cdclk = cnl_calc_cdclk(0);
2493                 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2494
2495                 intel_state->cdclk.actual.vco = vco;
2496                 intel_state->cdclk.actual.cdclk = cdclk;
2497                 intel_state->cdclk.actual.voltage_level =
2498                         cnl_calc_voltage_level(cdclk);
2499         } else {
2500                 intel_state->cdclk.actual =
2501                         intel_state->cdclk.logical;
2502         }
2503
2504         return 0;
2505 }
2506
2507 static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
2508 {
2509         struct drm_i915_private *dev_priv = to_i915(state->dev);
2510         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2511         unsigned int ref = intel_state->cdclk.logical.ref;
2512         int min_cdclk, cdclk, vco;
2513
2514         min_cdclk = intel_compute_min_cdclk(state);
2515         if (min_cdclk < 0)
2516                 return min_cdclk;
2517
2518         cdclk = icl_calc_cdclk(min_cdclk, ref);
2519         vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2520
2521         intel_state->cdclk.logical.vco = vco;
2522         intel_state->cdclk.logical.cdclk = cdclk;
2523         intel_state->cdclk.logical.voltage_level =
2524                 max(icl_calc_voltage_level(cdclk),
2525                     cnl_compute_min_voltage_level(intel_state));
2526
2527         if (!intel_state->active_crtcs) {
2528                 cdclk = icl_calc_cdclk(0, ref);
2529                 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2530
2531                 intel_state->cdclk.actual.vco = vco;
2532                 intel_state->cdclk.actual.cdclk = cdclk;
2533                 intel_state->cdclk.actual.voltage_level =
2534                         icl_calc_voltage_level(cdclk);
2535         } else {
2536                 intel_state->cdclk.actual = intel_state->cdclk.logical;
2537         }
2538
2539         return 0;
2540 }
2541
2542 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2543 {
2544         int max_cdclk_freq = dev_priv->max_cdclk_freq;
2545
2546         if (INTEL_GEN(dev_priv) >= 10)
2547                 return 2 * max_cdclk_freq;
2548         else if (IS_GEMINILAKE(dev_priv))
2549                 /*
2550                  * FIXME: Limiting to 99% as a temporary workaround. See
2551                  * intel_min_cdclk() for details.
2552                  */
2553                 return 2 * max_cdclk_freq * 99 / 100;
2554         else if (IS_GEN9(dev_priv) ||
2555                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2556                 return max_cdclk_freq;
2557         else if (IS_CHERRYVIEW(dev_priv))
2558                 return max_cdclk_freq*95/100;
2559         else if (INTEL_GEN(dev_priv) < 4)
2560                 return 2*max_cdclk_freq*90/100;
2561         else
2562                 return max_cdclk_freq*90/100;
2563 }
2564
2565 /**
2566  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2567  * @dev_priv: i915 device
2568  *
2569  * Determine the maximum CDCLK frequency the platform supports, and also
2570  * derive the maximum dot clock frequency the maximum CDCLK frequency
2571  * allows.
2572  */
2573 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2574 {
2575         if (IS_ICELAKE(dev_priv)) {
2576                 if (dev_priv->cdclk.hw.ref == 24000)
2577                         dev_priv->max_cdclk_freq = 648000;
2578                 else
2579                         dev_priv->max_cdclk_freq = 652800;
2580         } else if (IS_CANNONLAKE(dev_priv)) {
2581                 dev_priv->max_cdclk_freq = 528000;
2582         } else if (IS_GEN9_BC(dev_priv)) {
2583                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2584                 int max_cdclk, vco;
2585
2586                 vco = dev_priv->skl_preferred_vco_freq;
2587                 WARN_ON(vco != 8100000 && vco != 8640000);
2588
2589                 /*
2590                  * Use the lower (vco 8640) cdclk values as a
2591                  * first guess. skl_calc_cdclk() will correct it
2592                  * if the preferred vco is 8100 instead.
2593                  */
2594                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2595                         max_cdclk = 617143;
2596                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2597                         max_cdclk = 540000;
2598                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2599                         max_cdclk = 432000;
2600                 else
2601                         max_cdclk = 308571;
2602
2603                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2604         } else if (IS_GEMINILAKE(dev_priv)) {
2605                 dev_priv->max_cdclk_freq = 316800;
2606         } else if (IS_BROXTON(dev_priv)) {
2607                 dev_priv->max_cdclk_freq = 624000;
2608         } else if (IS_BROADWELL(dev_priv))  {
2609                 /*
2610                  * FIXME with extra cooling we can allow
2611                  * 540 MHz for ULX and 675 Mhz for ULT.
2612                  * How can we know if extra cooling is
2613                  * available? PCI ID, VTB, something else?
2614                  */
2615                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2616                         dev_priv->max_cdclk_freq = 450000;
2617                 else if (IS_BDW_ULX(dev_priv))
2618                         dev_priv->max_cdclk_freq = 450000;
2619                 else if (IS_BDW_ULT(dev_priv))
2620                         dev_priv->max_cdclk_freq = 540000;
2621                 else
2622                         dev_priv->max_cdclk_freq = 675000;
2623         } else if (IS_CHERRYVIEW(dev_priv)) {
2624                 dev_priv->max_cdclk_freq = 320000;
2625         } else if (IS_VALLEYVIEW(dev_priv)) {
2626                 dev_priv->max_cdclk_freq = 400000;
2627         } else {
2628                 /* otherwise assume cdclk is fixed */
2629                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2630         }
2631
2632         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2633
2634         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2635                          dev_priv->max_cdclk_freq);
2636
2637         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2638                          dev_priv->max_dotclk_freq);
2639 }
2640
2641 /**
2642  * intel_update_cdclk - Determine the current CDCLK frequency
2643  * @dev_priv: i915 device
2644  *
2645  * Determine the current CDCLK frequency.
2646  */
2647 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2648 {
2649         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2650
2651         /*
2652          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2653          * Programmng [sic] note: bit[9:2] should be programmed to the number
2654          * of cdclk that generates 4MHz reference clock freq which is used to
2655          * generate GMBus clock. This will vary with the cdclk freq.
2656          */
2657         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2658                 I915_WRITE(GMBUSFREQ_VLV,
2659                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2660 }
2661
2662 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2663 {
2664         u32 rawclk;
2665         int divider, fraction;
2666
2667         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2668                 /* 24 MHz */
2669                 divider = 24000;
2670                 fraction = 0;
2671         } else {
2672                 /* 19.2 MHz */
2673                 divider = 19000;
2674                 fraction = 200;
2675         }
2676
2677         rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2678         if (fraction)
2679                 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2680                                                             fraction) - 1);
2681
2682         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2683         return divider + fraction;
2684 }
2685
2686 static int icp_rawclk(struct drm_i915_private *dev_priv)
2687 {
2688         u32 rawclk;
2689         int divider, numerator, denominator, frequency;
2690
2691         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2692                 frequency = 24000;
2693                 divider = 23;
2694                 numerator = 0;
2695                 denominator = 0;
2696         } else {
2697                 frequency = 19200;
2698                 divider = 18;
2699                 numerator = 1;
2700                 denominator = 4;
2701         }
2702
2703         rawclk = CNP_RAWCLK_DIV(divider) | ICP_RAWCLK_NUM(numerator) |
2704                  ICP_RAWCLK_DEN(denominator);
2705
2706         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2707         return frequency;
2708 }
2709
2710 static int pch_rawclk(struct drm_i915_private *dev_priv)
2711 {
2712         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2713 }
2714
2715 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2716 {
2717         /* RAWCLK_FREQ_VLV register updated from power well code */
2718         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2719                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
2720 }
2721
2722 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2723 {
2724         uint32_t clkcfg;
2725
2726         /* hrawclock is 1/4 the FSB frequency */
2727         clkcfg = I915_READ(CLKCFG);
2728         switch (clkcfg & CLKCFG_FSB_MASK) {
2729         case CLKCFG_FSB_400:
2730                 return 100000;
2731         case CLKCFG_FSB_533:
2732                 return 133333;
2733         case CLKCFG_FSB_667:
2734                 return 166667;
2735         case CLKCFG_FSB_800:
2736                 return 200000;
2737         case CLKCFG_FSB_1067:
2738         case CLKCFG_FSB_1067_ALT:
2739                 return 266667;
2740         case CLKCFG_FSB_1333:
2741         case CLKCFG_FSB_1333_ALT:
2742                 return 333333;
2743         default:
2744                 return 133333;
2745         }
2746 }
2747
2748 /**
2749  * intel_update_rawclk - Determine the current RAWCLK frequency
2750  * @dev_priv: i915 device
2751  *
2752  * Determine the current RAWCLK frequency. RAWCLK is a fixed
2753  * frequency clock so this needs to done only once.
2754  */
2755 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2756 {
2757         if (HAS_PCH_ICP(dev_priv))
2758                 dev_priv->rawclk_freq = icp_rawclk(dev_priv);
2759         else if (HAS_PCH_CNP(dev_priv))
2760                 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2761         else if (HAS_PCH_SPLIT(dev_priv))
2762                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2763         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2764                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2765         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2766                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2767         else
2768                 /* no rawclk on other platforms, or no need to know it */
2769                 return;
2770
2771         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2772 }
2773
2774 /**
2775  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2776  * @dev_priv: i915 device
2777  */
2778 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2779 {
2780         if (IS_CHERRYVIEW(dev_priv)) {
2781                 dev_priv->display.set_cdclk = chv_set_cdclk;
2782                 dev_priv->display.modeset_calc_cdclk =
2783                         vlv_modeset_calc_cdclk;
2784         } else if (IS_VALLEYVIEW(dev_priv)) {
2785                 dev_priv->display.set_cdclk = vlv_set_cdclk;
2786                 dev_priv->display.modeset_calc_cdclk =
2787                         vlv_modeset_calc_cdclk;
2788         } else if (IS_BROADWELL(dev_priv)) {
2789                 dev_priv->display.set_cdclk = bdw_set_cdclk;
2790                 dev_priv->display.modeset_calc_cdclk =
2791                         bdw_modeset_calc_cdclk;
2792         } else if (IS_GEN9_LP(dev_priv)) {
2793                 dev_priv->display.set_cdclk = bxt_set_cdclk;
2794                 dev_priv->display.modeset_calc_cdclk =
2795                         bxt_modeset_calc_cdclk;
2796         } else if (IS_GEN9_BC(dev_priv)) {
2797                 dev_priv->display.set_cdclk = skl_set_cdclk;
2798                 dev_priv->display.modeset_calc_cdclk =
2799                         skl_modeset_calc_cdclk;
2800         } else if (IS_CANNONLAKE(dev_priv)) {
2801                 dev_priv->display.set_cdclk = cnl_set_cdclk;
2802                 dev_priv->display.modeset_calc_cdclk =
2803                         cnl_modeset_calc_cdclk;
2804         } else if (IS_ICELAKE(dev_priv)) {
2805                 dev_priv->display.set_cdclk = icl_set_cdclk;
2806                 dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
2807         }
2808
2809         if (IS_ICELAKE(dev_priv))
2810                 dev_priv->display.get_cdclk = icl_get_cdclk;
2811         else if (IS_CANNONLAKE(dev_priv))
2812                 dev_priv->display.get_cdclk = cnl_get_cdclk;
2813         else if (IS_GEN9_BC(dev_priv))
2814                 dev_priv->display.get_cdclk = skl_get_cdclk;
2815         else if (IS_GEN9_LP(dev_priv))
2816                 dev_priv->display.get_cdclk = bxt_get_cdclk;
2817         else if (IS_BROADWELL(dev_priv))
2818                 dev_priv->display.get_cdclk = bdw_get_cdclk;
2819         else if (IS_HASWELL(dev_priv))
2820                 dev_priv->display.get_cdclk = hsw_get_cdclk;
2821         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2822                 dev_priv->display.get_cdclk = vlv_get_cdclk;
2823         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2824                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2825         else if (IS_GEN5(dev_priv))
2826                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2827         else if (IS_GM45(dev_priv))
2828                 dev_priv->display.get_cdclk = gm45_get_cdclk;
2829         else if (IS_G45(dev_priv))
2830                 dev_priv->display.get_cdclk = g33_get_cdclk;
2831         else if (IS_I965GM(dev_priv))
2832                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2833         else if (IS_I965G(dev_priv))
2834                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2835         else if (IS_PINEVIEW(dev_priv))
2836                 dev_priv->display.get_cdclk = pnv_get_cdclk;
2837         else if (IS_G33(dev_priv))
2838                 dev_priv->display.get_cdclk = g33_get_cdclk;
2839         else if (IS_I945GM(dev_priv))
2840                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2841         else if (IS_I945G(dev_priv))
2842                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2843         else if (IS_I915GM(dev_priv))
2844                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2845         else if (IS_I915G(dev_priv))
2846                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2847         else if (IS_I865G(dev_priv))
2848                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2849         else if (IS_I85X(dev_priv))
2850                 dev_priv->display.get_cdclk = i85x_get_cdclk;
2851         else if (IS_I845G(dev_priv))
2852                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2853         else { /* 830 */
2854                 WARN(!IS_I830(dev_priv),
2855                      "Unknown platform. Assuming 133 MHz CDCLK\n");
2856                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2857         }
2858 }