drivers/gpu/drm/i915/i915_reset.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2008-2018 Intel Corporation
   5  */
   6
   7 #include <linux/sched/mm.h>
   8 #include <linux/stop_machine.h>
   9
  10 #include "i915_drv.h"
  11 #include "i915_gpu_error.h"
  12 #include "i915_reset.h"
  13
  14 #include "intel_guc.h"
  15
  16 #define RESET_MAX_RETRIES 3
  17
  18 /* XXX How to handle concurrent GGTT updates using tiling registers? */
  19 #define RESET_UNDER_STOP_MACHINE 0
  20
  21 static void engine_skip_context(struct i915_request *rq)
  22 {
  23         struct intel_engine_cs *engine = rq->engine;
  24         struct i915_gem_context *hung_ctx = rq->gem_context;
  25
  26         lockdep_assert_held(&engine->timeline.lock);
  27
  28         if (!i915_request_is_active(rq))
  29                 return;
  30
  31         list_for_each_entry_continue(rq, &engine->timeline.requests, link)
  32                 if (rq->gem_context == hung_ctx)
  33                         i915_request_skip(rq, -EIO);
  34 }
  35
  36 static void client_mark_guilty(struct drm_i915_file_private *file_priv,
  37                                const struct i915_gem_context *ctx)
  38 {
  39         unsigned int score;
  40         unsigned long prev_hang;
  41
  42         if (i915_gem_context_is_banned(ctx))
  43                 score = I915_CLIENT_SCORE_CONTEXT_BAN;
  44         else
  45                 score = 0;
  46
  47         prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
  48         if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
  49                 score += I915_CLIENT_SCORE_HANG_FAST;
  50
  51         if (score) {
  52                 atomic_add(score, &file_priv->ban_score);
  53
  54                 DRM_DEBUG_DRIVER("client %s: gained %u ban score, now %u\n",
  55                                  ctx->name, score,
  56                                  atomic_read(&file_priv->ban_score));
  57         }
  58 }
  59
  60 static bool context_mark_guilty(struct i915_gem_context *ctx)
  61 {
  62         unsigned long prev_hang;
  63         bool banned;
  64         int i;
  65
  66         atomic_inc(&ctx->guilty_count);
  67
  68         /* Cool contexts are too cool to be banned! (Used for reset testing.) */
  69         if (!i915_gem_context_is_bannable(ctx))
  70                 return false;
  71
  72         /* Record the timestamp for the last N hangs */
  73         prev_hang = ctx->hang_timestamp[0];
  74         for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp) - 1; i++)
  75                 ctx->hang_timestamp[i] = ctx->hang_timestamp[i + 1];
  76         ctx->hang_timestamp[i] = jiffies;
  77
  78         /* If we have hung N+1 times in rapid succession, we ban the context! */
  79         banned = !i915_gem_context_is_recoverable(ctx);
  80         if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
  81                 banned = true;
  82         if (banned) {
  83                 DRM_DEBUG_DRIVER("context %s: guilty %d, banned\n",
  84                                  ctx->name, atomic_read(&ctx->guilty_count));
  85                 i915_gem_context_set_banned(ctx);
  86         }
  87
  88         if (!IS_ERR_OR_NULL(ctx->file_priv))
  89                 client_mark_guilty(ctx->file_priv, ctx);
  90
  91         return banned;
  92 }
  93
  94 static void context_mark_innocent(struct i915_gem_context *ctx)
  95 {
  96         atomic_inc(&ctx->active_count);
  97 }
  98
  99 void i915_reset_request(struct i915_request *rq, bool guilty)
 100 {
 101         GEM_TRACE("%s rq=%llx:%lld, guilty? %s\n",
 102                   rq->engine->name,
 103                   rq->fence.context,
 104                   rq->fence.seqno,
 105                   yesno(guilty));
 106
 107         lockdep_assert_held(&rq->engine->timeline.lock);
 108         GEM_BUG_ON(i915_request_completed(rq));
 109
 110         if (guilty) {
 111                 i915_request_skip(rq, -EIO);
 112                 if (context_mark_guilty(rq->gem_context))
 113                         engine_skip_context(rq);
 114         } else {
 115                 dma_fence_set_error(&rq->fence, -EAGAIN);
 116                 context_mark_innocent(rq->gem_context);
 117         }
 118 }
 119
 120 static void gen3_stop_engine(struct intel_engine_cs *engine)
 121 {
 122         struct drm_i915_private *dev_priv = engine->i915;
 123         const u32 base = engine->mmio_base;
 124
 125         GEM_TRACE("%s\n", engine->name);
 126
 127         if (intel_engine_stop_cs(engine))
 128                 GEM_TRACE("%s: timed out on STOP_RING\n", engine->name);
 129
 130         I915_WRITE_FW(RING_HEAD(base), I915_READ_FW(RING_TAIL(base)));
 131         POSTING_READ_FW(RING_HEAD(base)); /* paranoia */
 132
 133         I915_WRITE_FW(RING_HEAD(base), 0);
 134         I915_WRITE_FW(RING_TAIL(base), 0);
 135         POSTING_READ_FW(RING_TAIL(base));
 136
 137         /* The ring must be empty before it is disabled */
 138         I915_WRITE_FW(RING_CTL(base), 0);
 139
 140         /* Check acts as a post */
 141         if (I915_READ_FW(RING_HEAD(base)))
 142                 GEM_TRACE("%s: ring head [%x] not parked\n",
 143                           engine->name, I915_READ_FW(RING_HEAD(base)));
 144 }
 145
 146 static void i915_stop_engines(struct drm_i915_private *i915,
 147                               unsigned int engine_mask)
 148 {
 149         struct intel_engine_cs *engine;
 150         enum intel_engine_id id;
 151
 152         if (INTEL_GEN(i915) < 3)
 153                 return;
 154
 155         for_each_engine_masked(engine, i915, engine_mask, id)
 156                 gen3_stop_engine(engine);
 157 }
 158
 159 static bool i915_in_reset(struct pci_dev *pdev)
 160 {
 161         u8 gdrst;
 162
 163         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
 164         return gdrst & GRDOM_RESET_STATUS;
 165 }
 166
 167 static int i915_do_reset(struct drm_i915_private *i915,
 168                          unsigned int engine_mask,
 169                          unsigned int retry)
 170 {
 171         struct pci_dev *pdev = i915->drm.pdev;
 172         int err;
 173
 174         /* Assert reset for at least 20 usec, and wait for acknowledgement. */
 175         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
 176         udelay(50);
 177         err = wait_for_atomic(i915_in_reset(pdev), 50);
 178
 179         /* Clear the reset request. */
 180         pci_write_config_byte(pdev, I915_GDRST, 0);
 181         udelay(50);
 182         if (!err)
 183                 err = wait_for_atomic(!i915_in_reset(pdev), 50);
 184
 185         return err;
 186 }
 187
 188 static bool g4x_reset_complete(struct pci_dev *pdev)
 189 {
 190         u8 gdrst;
 191
 192         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
 193         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 194 }
 195
 196 static int g33_do_reset(struct drm_i915_private *i915,
 197                         unsigned int engine_mask,
 198                         unsigned int retry)
 199 {
 200         struct pci_dev *pdev = i915->drm.pdev;
 201
 202         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
 203         return wait_for_atomic(g4x_reset_complete(pdev), 50);
 204 }
 205
 206 static int g4x_do_reset(struct drm_i915_private *dev_priv,
 207                         unsigned int engine_mask,
 208                         unsigned int retry)
 209 {
 210         struct pci_dev *pdev = dev_priv->drm.pdev;
 211         int ret;
 212
 213         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
 214         I915_WRITE_FW(VDECCLK_GATE_D,
 215                       I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
 216         POSTING_READ_FW(VDECCLK_GATE_D);
 217
 218         pci_write_config_byte(pdev, I915_GDRST,
 219                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 220         ret =  wait_for_atomic(g4x_reset_complete(pdev), 50);
 221         if (ret) {
 222                 DRM_DEBUG_DRIVER("Wait for media reset failed\n");
 223                 goto out;
 224         }
 225
 226         pci_write_config_byte(pdev, I915_GDRST,
 227                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
 228         ret =  wait_for_atomic(g4x_reset_complete(pdev), 50);
 229         if (ret) {
 230                 DRM_DEBUG_DRIVER("Wait for render reset failed\n");
 231                 goto out;
 232         }
 233
 234 out:
 235         pci_write_config_byte(pdev, I915_GDRST, 0);
 236
 237         I915_WRITE_FW(VDECCLK_GATE_D,
 238                       I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
 239         POSTING_READ_FW(VDECCLK_GATE_D);
 240
 241         return ret;
 242 }
 243
 244 static int ironlake_do_reset(struct drm_i915_private *dev_priv,
 245                              unsigned int engine_mask,
 246                              unsigned int retry)
 247 {
 248         struct intel_uncore *uncore = &dev_priv->uncore;
 249         int ret;
 250
 251         intel_uncore_write_fw(uncore, ILK_GDSR,
 252                               ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
 253         ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
 254                                            ILK_GRDOM_RESET_ENABLE, 0,
 255                                            5000, 0,
 256                                            NULL);
 257         if (ret) {
 258                 DRM_DEBUG_DRIVER("Wait for render reset failed\n");
 259                 goto out;
 260         }
 261
 262         intel_uncore_write_fw(uncore, ILK_GDSR,
 263                               ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
 264         ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
 265                                            ILK_GRDOM_RESET_ENABLE, 0,
 266                                            5000, 0,
 267                                            NULL);
 268         if (ret) {
 269                 DRM_DEBUG_DRIVER("Wait for media reset failed\n");
 270                 goto out;
 271         }
 272
 273 out:
 274         intel_uncore_write_fw(uncore, ILK_GDSR, 0);
 275         intel_uncore_posting_read_fw(uncore, ILK_GDSR);
 276         return ret;
 277 }
 278
 279 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
 280 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
 281                                 u32 hw_domain_mask)
 282 {
 283         struct intel_uncore *uncore = &dev_priv->uncore;
 284         int err;
 285
 286         /*
 287          * GEN6_GDRST is not in the gt power well, no need to check
 288          * for fifo space for the write or forcewake the chip for
 289          * the read
 290          */
 291         intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
 292
 293         /* Wait for the device to ack the reset requests */
 294         err = __intel_wait_for_register_fw(uncore,
 295                                            GEN6_GDRST, hw_domain_mask, 0,
 296                                            500, 0,
 297                                            NULL);
 298         if (err)
 299                 DRM_DEBUG_DRIVER("Wait for 0x%08x engines reset failed\n",
 300                                  hw_domain_mask);
 301
 302         return err;
 303 }
 304
 305 static int gen6_reset_engines(struct drm_i915_private *i915,
 306                               unsigned int engine_mask,
 307                               unsigned int retry)
 308 {
 309         struct intel_engine_cs *engine;
 310         const u32 hw_engine_mask[] = {
 311                 [RCS0]  = GEN6_GRDOM_RENDER,
 312                 [BCS0]  = GEN6_GRDOM_BLT,
 313                 [VCS0]  = GEN6_GRDOM_MEDIA,
 314                 [VCS1]  = GEN8_GRDOM_MEDIA2,
 315                 [VECS0] = GEN6_GRDOM_VECS,
 316         };
 317         u32 hw_mask;
 318
 319         if (engine_mask == ALL_ENGINES) {
 320                 hw_mask = GEN6_GRDOM_FULL;
 321         } else {
 322                 unsigned int tmp;
 323
 324                 hw_mask = 0;
 325                 for_each_engine_masked(engine, i915, engine_mask, tmp) {
 326                         GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
 327                         hw_mask |= hw_engine_mask[engine->id];
 328                 }
 329         }
 330
 331         return gen6_hw_domain_reset(i915, hw_mask);
 332 }
 333
 334 static u32 gen11_lock_sfc(struct drm_i915_private *dev_priv,
 335                           struct intel_engine_cs *engine)
 336 {
 337         struct intel_uncore *uncore = &dev_priv->uncore;
 338         u8 vdbox_sfc_access = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
 339         i915_reg_t sfc_forced_lock, sfc_forced_lock_ack;
 340         u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit;
 341         i915_reg_t sfc_usage;
 342         u32 sfc_usage_bit;
 343         u32 sfc_reset_bit;
 344
 345         switch (engine->class) {
 346         case VIDEO_DECODE_CLASS:
 347                 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
 348                         return 0;
 349
 350                 sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
 351                 sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
 352
 353                 sfc_forced_lock_ack = GEN11_VCS_SFC_LOCK_STATUS(engine);
 354                 sfc_forced_lock_ack_bit  = GEN11_VCS_SFC_LOCK_ACK_BIT;
 355
 356                 sfc_usage = GEN11_VCS_SFC_LOCK_STATUS(engine);
 357                 sfc_usage_bit = GEN11_VCS_SFC_USAGE_BIT;
 358                 sfc_reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
 359                 break;
 360
 361         case VIDEO_ENHANCEMENT_CLASS:
 362                 sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
 363                 sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
 364
 365                 sfc_forced_lock_ack = GEN11_VECS_SFC_LOCK_ACK(engine);
 366                 sfc_forced_lock_ack_bit  = GEN11_VECS_SFC_LOCK_ACK_BIT;
 367
 368                 sfc_usage = GEN11_VECS_SFC_USAGE(engine);
 369                 sfc_usage_bit = GEN11_VECS_SFC_USAGE_BIT;
 370                 sfc_reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
 371                 break;
 372
 373         default:
 374                 return 0;
 375         }
 376
 377         /*
 378          * Tell the engine that a software reset is going to happen. The engine
 379          * will then try to force lock the SFC (if currently locked, it will
 380          * remain so until we tell the engine it is safe to unlock; if currently
 381          * unlocked, it will ignore this and all new lock requests). If SFC
 382          * ends up being locked to the engine we want to reset, we have to reset
 383          * it as well (we will unlock it once the reset sequence is completed).
 384          */
 385         intel_uncore_rmw_or_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
 386
 387         if (__intel_wait_for_register_fw(uncore,
 388                                          sfc_forced_lock_ack,
 389                                          sfc_forced_lock_ack_bit,
 390                                          sfc_forced_lock_ack_bit,
 391                                          1000, 0, NULL)) {
 392                 DRM_DEBUG_DRIVER("Wait for SFC forced lock ack failed\n");
 393                 return 0;
 394         }
 395
 396         if (intel_uncore_read_fw(uncore, sfc_usage) & sfc_usage_bit)
 397                 return sfc_reset_bit;
 398
 399         return 0;
 400 }
 401
 402 static void gen11_unlock_sfc(struct drm_i915_private *dev_priv,
 403                              struct intel_engine_cs *engine)
 404 {
 405         u8 vdbox_sfc_access = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
 406         i915_reg_t sfc_forced_lock;
 407         u32 sfc_forced_lock_bit;
 408
 409         switch (engine->class) {
 410         case VIDEO_DECODE_CLASS:
 411                 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
 412                         return;
 413
 414                 sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
 415                 sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
 416                 break;
 417
 418         case VIDEO_ENHANCEMENT_CLASS:
 419                 sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
 420                 sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
 421                 break;
 422
 423         default:
 424                 return;
 425         }
 426
 427         I915_WRITE_FW(sfc_forced_lock,
 428                       I915_READ_FW(sfc_forced_lock) & ~sfc_forced_lock_bit);
 429 }
 430
 431 static int gen11_reset_engines(struct drm_i915_private *i915,
 432                                unsigned int engine_mask,
 433                                unsigned int retry)
 434 {
 435         const u32 hw_engine_mask[] = {
 436                 [RCS0]  = GEN11_GRDOM_RENDER,
 437                 [BCS0]  = GEN11_GRDOM_BLT,
 438                 [VCS0]  = GEN11_GRDOM_MEDIA,
 439                 [VCS1]  = GEN11_GRDOM_MEDIA2,
 440                 [VCS2]  = GEN11_GRDOM_MEDIA3,
 441                 [VCS3]  = GEN11_GRDOM_MEDIA4,
 442                 [VECS0] = GEN11_GRDOM_VECS,
 443                 [VECS1] = GEN11_GRDOM_VECS2,
 444         };
 445         struct intel_engine_cs *engine;
 446         unsigned int tmp;
 447         u32 hw_mask;
 448         int ret;
 449
 450         if (engine_mask == ALL_ENGINES) {
 451                 hw_mask = GEN11_GRDOM_FULL;
 452         } else {
 453                 hw_mask = 0;
 454                 for_each_engine_masked(engine, i915, engine_mask, tmp) {
 455                         GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
 456                         hw_mask |= hw_engine_mask[engine->id];
 457                         hw_mask |= gen11_lock_sfc(i915, engine);
 458                 }
 459         }
 460
 461         ret = gen6_hw_domain_reset(i915, hw_mask);
 462
 463         if (engine_mask != ALL_ENGINES)
 464                 for_each_engine_masked(engine, i915, engine_mask, tmp)
 465                         gen11_unlock_sfc(i915, engine);
 466
 467         return ret;
 468 }
 469
 470 static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
 471 {
 472         struct intel_uncore *uncore = &engine->i915->uncore;
 473         int ret;
 474
 475         intel_uncore_write_fw(uncore, RING_RESET_CTL(engine->mmio_base),
 476                               _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
 477
 478         ret = __intel_wait_for_register_fw(uncore,
 479                                            RING_RESET_CTL(engine->mmio_base),
 480                                            RESET_CTL_READY_TO_RESET,
 481                                            RESET_CTL_READY_TO_RESET,
 482                                            700, 0,
 483                                            NULL);
 484         if (ret)
 485                 DRM_ERROR("%s: reset request timeout\n", engine->name);
 486
 487         return ret;
 488 }
 489
 490 static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
 491 {
 492         struct drm_i915_private *dev_priv = engine->i915;
 493
 494         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
 495                       _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
 496 }
 497
 498 static int gen8_reset_engines(struct drm_i915_private *i915,
 499                               unsigned int engine_mask,
 500                               unsigned int retry)
 501 {
 502         struct intel_engine_cs *engine;
 503         const bool reset_non_ready = retry >= 1;
 504         unsigned int tmp;
 505         int ret;
 506
 507         for_each_engine_masked(engine, i915, engine_mask, tmp) {
 508                 ret = gen8_engine_reset_prepare(engine);
 509                 if (ret && !reset_non_ready)
 510                         goto skip_reset;
 511
 512                 /*
 513                  * If this is not the first failed attempt to prepare,
 514                  * we decide to proceed anyway.
 515                  *
 516                  * By doing so we risk context corruption and with
 517                  * some gens (kbl), possible system hang if reset
 518                  * happens during active bb execution.
 519                  *
 520                  * We rather take context corruption instead of
 521                  * failed reset with a wedged driver/gpu. And
 522                  * active bb execution case should be covered by
 523                  * i915_stop_engines we have before the reset.
 524                  */
 525         }
 526
 527         if (INTEL_GEN(i915) >= 11)
 528                 ret = gen11_reset_engines(i915, engine_mask, retry);
 529         else
 530                 ret = gen6_reset_engines(i915, engine_mask, retry);
 531
 532 skip_reset:
 533         for_each_engine_masked(engine, i915, engine_mask, tmp)
 534                 gen8_engine_reset_cancel(engine);
 535
 536         return ret;
 537 }
 538
 539 typedef int (*reset_func)(struct drm_i915_private *,
 540                           unsigned int engine_mask,
 541                           unsigned int retry);
 542
 543 static reset_func intel_get_gpu_reset(struct drm_i915_private *i915)
 544 {
 545         if (INTEL_GEN(i915) >= 8)
 546                 return gen8_reset_engines;
 547         else if (INTEL_GEN(i915) >= 6)
 548                 return gen6_reset_engines;
 549         else if (INTEL_GEN(i915) >= 5)
 550                 return ironlake_do_reset;
 551         else if (IS_G4X(i915))
 552                 return g4x_do_reset;
 553         else if (IS_G33(i915) || IS_PINEVIEW(i915))
 554                 return g33_do_reset;
 555         else if (INTEL_GEN(i915) >= 3)
 556                 return i915_do_reset;
 557         else
 558                 return NULL;
 559 }
 560
 561 int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask)
 562 {
 563         const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
 564         reset_func reset;
 565         int ret = -ETIMEDOUT;
 566         int retry;
 567
 568         reset = intel_get_gpu_reset(i915);
 569         if (!reset)
 570                 return -ENODEV;
 571
 572         /*
 573          * If the power well sleeps during the reset, the reset
 574          * request may be dropped and never completes (causing -EIO).
 575          */
 576         intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
 577         for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
 578                 /*
 579                  * We stop engines, otherwise we might get failed reset and a
 580                  * dead gpu (on elk). Also as modern gpu as kbl can suffer
 581                  * from system hang if batchbuffer is progressing when
 582                  * the reset is issued, regardless of READY_TO_RESET ack.
 583                  * Thus assume it is best to stop engines on all gens
 584                  * where we have a gpu reset.
 585                  *
 586                  * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
 587                  *
 588                  * WaMediaResetMainRingCleanup:ctg,elk (presumably)
 589                  *
 590                  * FIXME: Wa for more modern gens needs to be validated
 591                  */
 592                 if (retry)
 593                         i915_stop_engines(i915, engine_mask);
 594
 595                 GEM_TRACE("engine_mask=%x\n", engine_mask);
 596                 preempt_disable();
 597                 ret = reset(i915, engine_mask, retry);
 598                 preempt_enable();
 599         }
 600         intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
 601
 602         return ret;
 603 }
 604
 605 bool intel_has_gpu_reset(struct drm_i915_private *i915)
 606 {
 607         if (USES_GUC(i915))
 608                 return false;
 609
 610         if (!i915_modparams.reset)
 611                 return NULL;
 612
 613         return intel_get_gpu_reset(i915);
 614 }
 615
 616 bool intel_has_reset_engine(struct drm_i915_private *i915)
 617 {
 618         return INTEL_INFO(i915)->has_reset_engine && i915_modparams.reset >= 2;
 619 }
 620
 621 int intel_reset_guc(struct drm_i915_private *i915)
 622 {
 623         u32 guc_domain =
 624                 INTEL_GEN(i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
 625         int ret;
 626
 627         GEM_BUG_ON(!HAS_GUC(i915));
 628
 629         intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
 630         ret = gen6_hw_domain_reset(i915, guc_domain);
 631         intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
 632
 633         return ret;
 634 }
 635
 636 /*
 637  * Ensure irq handler finishes, and not run again.
 638  * Also return the active request so that we only search for it once.
 639  */
 640 static void reset_prepare_engine(struct intel_engine_cs *engine)
 641 {
 642         /*
 643          * During the reset sequence, we must prevent the engine from
 644          * entering RC6. As the context state is undefined until we restart
 645          * the engine, if it does enter RC6 during the reset, the state
 646          * written to the powercontext is undefined and so we may lose
 647          * GPU state upon resume, i.e. fail to restart after a reset.
 648          */
 649         intel_uncore_forcewake_get(&engine->i915->uncore, FORCEWAKE_ALL);
 650         engine->reset.prepare(engine);
 651 }
 652
 653 static void revoke_mmaps(struct drm_i915_private *i915)
 654 {
 655         int i;
 656
 657         for (i = 0; i < i915->num_fence_regs; i++) {
 658                 struct drm_vma_offset_node *node;
 659                 struct i915_vma *vma;
 660                 u64 vma_offset;
 661
 662                 vma = READ_ONCE(i915->fence_regs[i].vma);
 663                 if (!vma)
 664                         continue;
 665
 666                 if (!i915_vma_has_userfault(vma))
 667                         continue;
 668
 669                 GEM_BUG_ON(vma->fence != &i915->fence_regs[i]);
 670                 node = &vma->obj->base.vma_node;
 671                 vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;
 672                 unmap_mapping_range(i915->drm.anon_inode->i_mapping,
 673                                     drm_vma_node_offset_addr(node) + vma_offset,
 674                                     vma->size,
 675                                     1);
 676         }
 677 }
 678
 679 static void reset_prepare(struct drm_i915_private *i915)
 680 {
 681         struct intel_engine_cs *engine;
 682         enum intel_engine_id id;
 683
 684         for_each_engine(engine, i915, id)
 685                 reset_prepare_engine(engine);
 686
 687         intel_uc_reset_prepare(i915);
 688 }
 689
 690 static void gt_revoke(struct drm_i915_private *i915)
 691 {
 692         revoke_mmaps(i915);
 693 }
 694
 695 static int gt_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
 696 {
 697         struct intel_engine_cs *engine;
 698         enum intel_engine_id id;
 699         int err;
 700
 701         /*
 702          * Everything depends on having the GTT running, so we need to start
 703          * there.
 704          */
 705         err = i915_ggtt_enable_hw(i915);
 706         if (err)
 707                 return err;
 708
 709         for_each_engine(engine, i915, id)
 710                 intel_engine_reset(engine, stalled_mask & engine->mask);
 711
 712         i915_gem_restore_fences(i915);
 713
 714         return err;
 715 }
 716
 717 static void reset_finish_engine(struct intel_engine_cs *engine)
 718 {
 719         engine->reset.finish(engine);
 720         intel_uncore_forcewake_put(&engine->i915->uncore, FORCEWAKE_ALL);
 721 }
 722
 723 struct i915_gpu_restart {
 724         struct work_struct work;
 725         struct drm_i915_private *i915;
 726 };
 727
 728 static void restart_work(struct work_struct *work)
 729 {
 730         struct i915_gpu_restart *arg = container_of(work, typeof(*arg), work);
 731         struct drm_i915_private *i915 = arg->i915;
 732         struct intel_engine_cs *engine;
 733         enum intel_engine_id id;
 734         intel_wakeref_t wakeref;
 735
 736         wakeref = intel_runtime_pm_get(i915);
 737         mutex_lock(&i915->drm.struct_mutex);
 738         WRITE_ONCE(i915->gpu_error.restart, NULL);
 739
 740         for_each_engine(engine, i915, id) {
 741                 struct i915_request *rq;
 742
 743                 /*
 744                  * Ostensibily, we always want a context loaded for powersaving,
 745                  * so if the engine is idle after the reset, send a request
 746                  * to load our scratch kernel_context.
 747                  */
 748                 if (!intel_engine_is_idle(engine))
 749                         continue;
 750
 751                 rq = i915_request_alloc(engine, i915->kernel_context);
 752                 if (!IS_ERR(rq))
 753                         i915_request_add(rq);
 754         }
 755
 756         mutex_unlock(&i915->drm.struct_mutex);
 757         intel_runtime_pm_put(i915, wakeref);
 758
 759         kfree(arg);
 760 }
 761
 762 static void reset_finish(struct drm_i915_private *i915)
 763 {
 764         struct intel_engine_cs *engine;
 765         enum intel_engine_id id;
 766
 767         for_each_engine(engine, i915, id) {
 768                 reset_finish_engine(engine);
 769                 intel_engine_signal_breadcrumbs(engine);
 770         }
 771 }
 772
 773 static void reset_restart(struct drm_i915_private *i915)
 774 {
 775         struct i915_gpu_restart *arg;
 776
 777         /*
 778          * Following the reset, ensure that we always reload context for
 779          * powersaving, and to correct engine->last_retired_context. Since
 780          * this requires us to submit a request, queue a worker to do that
 781          * task for us to evade any locking here.
 782          */
 783         if (READ_ONCE(i915->gpu_error.restart))
 784                 return;
 785
 786         arg = kmalloc(sizeof(*arg), GFP_KERNEL);
 787         if (arg) {
 788                 arg->i915 = i915;
 789                 INIT_WORK(&arg->work, restart_work);
 790
 791                 WRITE_ONCE(i915->gpu_error.restart, arg);
 792                 queue_work(i915->wq, &arg->work);
 793         }
 794 }
 795
 796 static void nop_submit_request(struct i915_request *request)
 797 {
 798         struct intel_engine_cs *engine = request->engine;
 799         unsigned long flags;
 800
 801         GEM_TRACE("%s fence %llx:%lld -> -EIO\n",
 802                   engine->name, request->fence.context, request->fence.seqno);
 803         dma_fence_set_error(&request->fence, -EIO);
 804
 805         spin_lock_irqsave(&engine->timeline.lock, flags);
 806         __i915_request_submit(request);
 807         i915_request_mark_complete(request);
 808         spin_unlock_irqrestore(&engine->timeline.lock, flags);
 809
 810         intel_engine_queue_breadcrumbs(engine);
 811 }
 812
 813 static void __i915_gem_set_wedged(struct drm_i915_private *i915)
 814 {
 815         struct i915_gpu_error *error = &i915->gpu_error;
 816         struct intel_engine_cs *engine;
 817         enum intel_engine_id id;
 818
 819         if (test_bit(I915_WEDGED, &error->flags))
 820                 return;
 821
 822         if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(i915)) {
 823                 struct drm_printer p = drm_debug_printer(__func__);
 824
 825                 for_each_engine(engine, i915, id)
 826                         intel_engine_dump(engine, &p, "%s\n", engine->name);
 827         }
 828
 829         GEM_TRACE("start\n");
 830
 831         /*
 832          * First, stop submission to hw, but do not yet complete requests by
 833          * rolling the global seqno forward (since this would complete requests
 834          * for which we haven't set the fence error to EIO yet).
 835          */
 836         reset_prepare(i915);
 837
 838         /* Even if the GPU reset fails, it should still stop the engines */
 839         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 840                 intel_gpu_reset(i915, ALL_ENGINES);
 841
 842         for_each_engine(engine, i915, id) {
 843                 engine->submit_request = nop_submit_request;
 844                 engine->schedule = NULL;
 845         }
 846         i915->caps.scheduler = 0;
 847
 848         /*
 849          * Make sure no request can slip through without getting completed by
 850          * either this call here to intel_engine_write_global_seqno, or the one
 851          * in nop_submit_request.
 852          */
 853         synchronize_rcu_expedited();
 854
 855         /* Mark all executing requests as skipped */
 856         for_each_engine(engine, i915, id)
 857                 engine->cancel_requests(engine);
 858
 859         reset_finish(i915);
 860
 861         smp_mb__before_atomic();
 862         set_bit(I915_WEDGED, &error->flags);
 863
 864         GEM_TRACE("end\n");
 865 }
 866
 867 void i915_gem_set_wedged(struct drm_i915_private *i915)
 868 {
 869         struct i915_gpu_error *error = &i915->gpu_error;
 870         intel_wakeref_t wakeref;
 871
 872         mutex_lock(&error->wedge_mutex);
 873         with_intel_runtime_pm(i915, wakeref)
 874                 __i915_gem_set_wedged(i915);
 875         mutex_unlock(&error->wedge_mutex);
 876 }
 877
 878 static bool __i915_gem_unset_wedged(struct drm_i915_private *i915)
 879 {
 880         struct i915_gpu_error *error = &i915->gpu_error;
 881         struct i915_timeline *tl;
 882
 883         if (!test_bit(I915_WEDGED, &error->flags))
 884                 return true;
 885
 886         if (!i915->gt.scratch) /* Never full initialised, recovery impossible */
 887                 return false;
 888
 889         GEM_TRACE("start\n");
 890
 891         /*
 892          * Before unwedging, make sure that all pending operations
 893          * are flushed and errored out - we may have requests waiting upon
 894          * third party fences. We marked all inflight requests as EIO, and
 895          * every execbuf since returned EIO, for consistency we want all
 896          * the currently pending requests to also be marked as EIO, which
 897          * is done inside our nop_submit_request - and so we must wait.
 898          *
 899          * No more can be submitted until we reset the wedged bit.
 900          */
 901         mutex_lock(&i915->gt.timelines.mutex);
 902         list_for_each_entry(tl, &i915->gt.timelines.active_list, link) {
 903                 struct i915_request *rq;
 904
 905                 rq = i915_active_request_get_unlocked(&tl->last_request);
 906                 if (!rq)
 907                         continue;
 908
 909                 /*
 910                  * All internal dependencies (i915_requests) will have
 911                  * been flushed by the set-wedge, but we may be stuck waiting
 912                  * for external fences. These should all be capped to 10s
 913                  * (I915_FENCE_TIMEOUT) so this wait should not be unbounded
 914                  * in the worst case.
 915                  */
 916                 dma_fence_default_wait(&rq->fence, false, MAX_SCHEDULE_TIMEOUT);
 917                 i915_request_put(rq);
 918         }
 919         mutex_unlock(&i915->gt.timelines.mutex);
 920
 921         intel_engines_sanitize(i915, false);
 922
 923         /*
 924          * Undo nop_submit_request. We prevent all new i915 requests from
 925          * being queued (by disallowing execbuf whilst wedged) so having
 926          * waited for all active requests above, we know the system is idle
 927          * and do not have to worry about a thread being inside
 928          * engine->submit_request() as we swap over. So unlike installing
 929          * the nop_submit_request on reset, we can do this from normal
 930          * context and do not require stop_machine().
 931          */
 932         intel_engines_reset_default_submission(i915);
 933
 934         GEM_TRACE("end\n");
 935
 936         smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
 937         clear_bit(I915_WEDGED, &i915->gpu_error.flags);
 938
 939         return true;
 940 }
 941
 942 bool i915_gem_unset_wedged(struct drm_i915_private *i915)
 943 {
 944         struct i915_gpu_error *error = &i915->gpu_error;
 945         bool result;
 946
 947         mutex_lock(&error->wedge_mutex);
 948         result = __i915_gem_unset_wedged(i915);
 949         mutex_unlock(&error->wedge_mutex);
 950
 951         return result;
 952 }
 953
 954 static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
 955 {
 956         int err, i;
 957
 958         gt_revoke(i915);
 959
 960         err = intel_gpu_reset(i915, ALL_ENGINES);
 961         for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
 962                 msleep(10 * (i + 1));
 963                 err = intel_gpu_reset(i915, ALL_ENGINES);
 964         }
 965         if (err)
 966                 return err;
 967
 968         return gt_reset(i915, stalled_mask);
 969 }
 970
 971 /**
 972  * i915_reset - reset chip after a hang
 973  * @i915: #drm_i915_private to reset
 974  * @stalled_mask: mask of the stalled engines with the guilty requests
 975  * @reason: user error message for why we are resetting
 976  *
 977  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
 978  * on failure.
 979  *
 980  * Procedure is fairly simple:
 981  *   - reset the chip using the reset reg
 982  *   - re-init context state
 983  *   - re-init hardware status page
 984  *   - re-init ring buffer
 985  *   - re-init interrupt state
 986  *   - re-init display
 987  */
 988 void i915_reset(struct drm_i915_private *i915,
 989                 unsigned int stalled_mask,
 990                 const char *reason)
 991 {
 992         struct i915_gpu_error *error = &i915->gpu_error;
 993         int ret;
 994
 995         GEM_TRACE("flags=%lx\n", error->flags);
 996
 997         might_sleep();
 998         assert_rpm_wakelock_held(i915);
 999         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1000
1001         /* Clear any previous failed attempts at recovery. Time to try again. */
1002         if (!__i915_gem_unset_wedged(i915))
1003                 return;
1004
1005         if (reason)
1006                 dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
1007         error->reset_count++;
1008
1009         reset_prepare(i915);
1010
1011         if (!intel_has_gpu_reset(i915)) {
1012                 if (i915_modparams.reset)
1013                         dev_err(i915->drm.dev, "GPU reset not supported\n");
1014                 else
1015                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1016                 goto error;
1017         }
1018
1019         if (INTEL_INFO(i915)->gpu_reset_clobbers_display)
1020                 intel_runtime_pm_disable_interrupts(i915);
1021
1022         if (do_reset(i915, stalled_mask)) {
1023                 dev_err(i915->drm.dev, "Failed to reset chip\n");
1024                 goto taint;
1025         }
1026
1027         if (INTEL_INFO(i915)->gpu_reset_clobbers_display)
1028                 intel_runtime_pm_enable_interrupts(i915);
1029
1030         intel_overlay_reset(i915);
1031
1032         /*
1033          * Next we need to restore the context, but we don't use those
1034          * yet either...
1035          *
1036          * Ring buffer needs to be re-initialized in the KMS case, or if X
1037          * was running at the time of the reset (i.e. we weren't VT
1038          * switched away).
1039          */
1040         ret = i915_gem_init_hw(i915);
1041         if (ret) {
1042                 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1043                           ret);
1044                 goto error;
1045         }
1046
1047         i915_queue_hangcheck(i915);
1048
1049 finish:
1050         reset_finish(i915);
1051         if (!__i915_wedged(error))
1052                 reset_restart(i915);
1053         return;
1054
1055 taint:
1056         /*
1057          * History tells us that if we cannot reset the GPU now, we
1058          * never will. This then impacts everything that is run
1059          * subsequently. On failing the reset, we mark the driver
1060          * as wedged, preventing further execution on the GPU.
1061          * We also want to go one step further and add a taint to the
1062          * kernel so that any subsequent faults can be traced back to
1063          * this failure. This is important for CI, where if the
1064          * GPU/driver fails we would like to reboot and restart testing
1065          * rather than continue on into oblivion. For everyone else,
1066          * the system should still plod along, but they have been warned!
1067          */
1068         add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
1069 error:
1070         __i915_gem_set_wedged(i915);
1071         goto finish;
1072 }
1073
1074 static inline int intel_gt_reset_engine(struct drm_i915_private *i915,
1075                                         struct intel_engine_cs *engine)
1076 {
1077         return intel_gpu_reset(i915, engine->mask);
1078 }
1079
1080 /**
1081  * i915_reset_engine - reset GPU engine to recover from a hang
1082  * @engine: engine to reset
1083  * @msg: reason for GPU reset; or NULL for no dev_notice()
1084  *
1085  * Reset a specific GPU engine. Useful if a hang is detected.
1086  * Returns zero on successful reset or otherwise an error code.
1087  *
1088  * Procedure is:
1089  *  - identifies the request that caused the hang and it is dropped
1090  *  - reset engine (which will force the engine to idle)
1091  *  - re-init/configure engine
1092  */
1093 int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
1094 {
1095         struct i915_gpu_error *error = &engine->i915->gpu_error;
1096         int ret;
1097
1098         GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
1099         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
1100
1101         reset_prepare_engine(engine);
1102
1103         if (msg)
1104                 dev_notice(engine->i915->drm.dev,
1105                            "Resetting %s for %s\n", engine->name, msg);
1106         error->reset_engine_count[engine->id]++;
1107
1108         if (!engine->i915->guc.execbuf_client)
1109                 ret = intel_gt_reset_engine(engine->i915, engine);
1110         else
1111                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
1112         if (ret) {
1113                 /* If we fail here, we expect to fallback to a global reset */
1114                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
1115                                  engine->i915->guc.execbuf_client ? "GuC " : "",
1116                                  engine->name, ret);
1117                 goto out;
1118         }
1119
1120         /*
1121          * The request that caused the hang is stuck on elsp, we know the
1122          * active request and can drop it, adjust head to skip the offending
1123          * request to resume executing remaining requests in the queue.
1124          */
1125         intel_engine_reset(engine, true);
1126
1127         /*
1128          * The engine and its registers (and workarounds in case of render)
1129          * have been reset to their default values. Follow the init_ring
1130          * process to program RING_MODE, HWSP and re-enable submission.
1131          */
1132         ret = engine->init_hw(engine);
1133         if (ret)
1134                 goto out;
1135
1136 out:
1137         intel_engine_cancel_stop_cs(engine);
1138         reset_finish_engine(engine);
1139         return ret;
1140 }
1141
1142 static void i915_reset_device(struct drm_i915_private *i915,
1143                               u32 engine_mask,
1144                               const char *reason)
1145 {
1146         struct i915_gpu_error *error = &i915->gpu_error;
1147         struct kobject *kobj = &i915->drm.primary->kdev->kobj;
1148         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1149         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1150         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1151         struct i915_wedge_me w;
1152
1153         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
1154
1155         DRM_DEBUG_DRIVER("resetting chip\n");
1156         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
1157
1158         /* Use a watchdog to ensure that our reset completes */
1159         i915_wedge_on_timeout(&w, i915, 5 * HZ) {
1160                 intel_prepare_reset(i915);
1161
1162                 /* Flush everyone using a resource about to be clobbered */
1163                 synchronize_srcu_expedited(&error->reset_backoff_srcu);
1164
1165                 mutex_lock(&error->wedge_mutex);
1166                 i915_reset(i915, engine_mask, reason);
1167                 mutex_unlock(&error->wedge_mutex);
1168
1169                 intel_finish_reset(i915);
1170         }
1171
1172         if (!test_bit(I915_WEDGED, &error->flags))
1173                 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
1174 }
1175
1176 static void clear_register(struct drm_i915_private *dev_priv, i915_reg_t reg)
1177 {
1178         I915_WRITE(reg, I915_READ(reg));
1179 }
1180
1181 void i915_clear_error_registers(struct drm_i915_private *dev_priv)
1182 {
1183         u32 eir;
1184
1185         if (!IS_GEN(dev_priv, 2))
1186                 clear_register(dev_priv, PGTBL_ER);
1187
1188         if (INTEL_GEN(dev_priv) < 4)
1189                 clear_register(dev_priv, IPEIR(RENDER_RING_BASE));
1190         else
1191                 clear_register(dev_priv, IPEIR_I965);
1192
1193         clear_register(dev_priv, EIR);
1194         eir = I915_READ(EIR);
1195         if (eir) {
1196                 /*
1197                  * some errors might have become stuck,
1198                  * mask them.
1199                  */
1200                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
1201                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1202                 I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT);
1203         }
1204
1205         if (INTEL_GEN(dev_priv) >= 8) {
1206                 I915_WRITE(GEN8_RING_FAULT_REG,
1207                            I915_READ(GEN8_RING_FAULT_REG) & ~RING_FAULT_VALID);
1208                 POSTING_READ(GEN8_RING_FAULT_REG);
1209         } else if (INTEL_GEN(dev_priv) >= 6) {
1210                 struct intel_engine_cs *engine;
1211                 enum intel_engine_id id;
1212
1213                 for_each_engine(engine, dev_priv, id) {
1214                         I915_WRITE(RING_FAULT_REG(engine),
1215                                    I915_READ(RING_FAULT_REG(engine)) &
1216                                    ~RING_FAULT_VALID);
1217                 }
1218                 POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS0]));
1219         }
1220 }
1221
1222 /**
1223  * i915_handle_error - handle a gpu error
1224  * @i915: i915 device private
1225  * @engine_mask: mask representing engines that are hung
1226  * @flags: control flags
1227  * @fmt: Error message format string
1228  *
1229  * Do some basic checking of register state at error time and
1230  * dump it to the syslog.  Also call i915_capture_error_state() to make
1231  * sure we get a record and make it available in debugfs.  Fire a uevent
1232  * so userspace knows something bad happened (should trigger collection
1233  * of a ring dump etc.).
1234  */
1235 void i915_handle_error(struct drm_i915_private *i915,
1236                        u32 engine_mask,
1237                        unsigned long flags,
1238                        const char *fmt, ...)
1239 {
1240         struct i915_gpu_error *error = &i915->gpu_error;
1241         struct intel_engine_cs *engine;
1242         intel_wakeref_t wakeref;
1243         unsigned int tmp;
1244         char error_msg[80];
1245         char *msg = NULL;
1246
1247         if (fmt) {
1248                 va_list args;
1249
1250                 va_start(args, fmt);
1251                 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
1252                 va_end(args);
1253
1254                 msg = error_msg;
1255         }
1256
1257         /*
1258          * In most cases it's guaranteed that we get here with an RPM
1259          * reference held, for example because there is a pending GPU
1260          * request that won't finish until the reset is done. This
1261          * isn't the case at least when we get here by doing a
1262          * simulated reset via debugfs, so get an RPM reference.
1263          */
1264         wakeref = intel_runtime_pm_get(i915);
1265
1266         engine_mask &= INTEL_INFO(i915)->engine_mask;
1267
1268         if (flags & I915_ERROR_CAPTURE) {
1269                 i915_capture_error_state(i915, engine_mask, msg);
1270                 i915_clear_error_registers(i915);
1271         }
1272
1273         /*
1274          * Try engine reset when available. We fall back to full reset if
1275          * single reset fails.
1276          */
1277         if (intel_has_reset_engine(i915) && !__i915_wedged(error)) {
1278                 for_each_engine_masked(engine, i915, engine_mask, tmp) {
1279                         BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
1280                         if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1281                                              &error->flags))
1282                                 continue;
1283
1284                         if (i915_reset_engine(engine, msg) == 0)
1285                                 engine_mask &= ~engine->mask;
1286
1287                         clear_bit(I915_RESET_ENGINE + engine->id,
1288                                   &error->flags);
1289                         wake_up_bit(&error->flags,
1290                                     I915_RESET_ENGINE + engine->id);
1291                 }
1292         }
1293
1294         if (!engine_mask)
1295                 goto out;
1296
1297         /* Full reset needs the mutex, stop any other user trying to do so. */
1298         if (test_and_set_bit(I915_RESET_BACKOFF, &error->flags)) {
1299                 wait_event(error->reset_queue,
1300                            !test_bit(I915_RESET_BACKOFF, &error->flags));
1301                 goto out; /* piggy-back on the other reset */
1302         }
1303
1304         /* Make sure i915_reset_trylock() sees the I915_RESET_BACKOFF */
1305         synchronize_rcu_expedited();
1306
1307         /* Prevent any other reset-engine attempt. */
1308         for_each_engine(engine, i915, tmp) {
1309                 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1310                                         &error->flags))
1311                         wait_on_bit(&error->flags,
1312                                     I915_RESET_ENGINE + engine->id,
1313                                     TASK_UNINTERRUPTIBLE);
1314         }
1315
1316         i915_reset_device(i915, engine_mask, msg);
1317
1318         for_each_engine(engine, i915, tmp) {
1319                 clear_bit(I915_RESET_ENGINE + engine->id,
1320                           &error->flags);
1321         }
1322
1323         clear_bit(I915_RESET_BACKOFF, &error->flags);
1324         wake_up_all(&error->reset_queue);
1325
1326 out:
1327         intel_runtime_pm_put(i915, wakeref);
1328 }
1329
1330 int i915_reset_trylock(struct drm_i915_private *i915)
1331 {
1332         struct i915_gpu_error *error = &i915->gpu_error;
1333         int srcu;
1334
1335         might_lock(&error->reset_backoff_srcu);
1336         might_sleep();
1337
1338         rcu_read_lock();
1339         while (test_bit(I915_RESET_BACKOFF, &error->flags)) {
1340                 rcu_read_unlock();
1341
1342                 if (wait_event_interruptible(error->reset_queue,
1343                                              !test_bit(I915_RESET_BACKOFF,
1344                                                        &error->flags)))
1345                         return -EINTR;
1346
1347                 rcu_read_lock();
1348         }
1349         srcu = srcu_read_lock(&error->reset_backoff_srcu);
1350         rcu_read_unlock();
1351
1352         return srcu;
1353 }
1354
1355 void i915_reset_unlock(struct drm_i915_private *i915, int tag)
1356 __releases(&i915->gpu_error.reset_backoff_srcu)
1357 {
1358         struct i915_gpu_error *error = &i915->gpu_error;
1359
1360         srcu_read_unlock(&error->reset_backoff_srcu, tag);
1361 }
1362
1363 int i915_terminally_wedged(struct drm_i915_private *i915)
1364 {
1365         struct i915_gpu_error *error = &i915->gpu_error;
1366
1367         might_sleep();
1368
1369         if (!__i915_wedged(error))
1370                 return 0;
1371
1372         /* Reset still in progress? Maybe we will recover? */
1373         if (!test_bit(I915_RESET_BACKOFF, &error->flags))
1374                 return -EIO;
1375
1376         /* XXX intel_reset_finish() still takes struct_mutex!!! */
1377         if (mutex_is_locked(&i915->drm.struct_mutex))
1378                 return -EAGAIN;
1379
1380         if (wait_event_interruptible(error->reset_queue,
1381                                      !test_bit(I915_RESET_BACKOFF,
1382                                                &error->flags)))
1383                 return -EINTR;
1384
1385         return __i915_wedged(error) ? -EIO : 0;
1386 }
1387
1388 bool i915_reset_flush(struct drm_i915_private *i915)
1389 {
1390         int err;
1391
1392         cancel_delayed_work_sync(&i915->gpu_error.hangcheck_work);
1393
1394         flush_workqueue(i915->wq);
1395         GEM_BUG_ON(READ_ONCE(i915->gpu_error.restart));
1396
1397         mutex_lock(&i915->drm.struct_mutex);
1398         err = i915_gem_wait_for_idle(i915,
1399                                      I915_WAIT_LOCKED |
1400                                      I915_WAIT_FOR_IDLE_BOOST,
1401                                      MAX_SCHEDULE_TIMEOUT);
1402         mutex_unlock(&i915->drm.struct_mutex);
1403
1404         return !err;
1405 }
1406
1407 static void i915_wedge_me(struct work_struct *work)
1408 {
1409         struct i915_wedge_me *w = container_of(work, typeof(*w), work.work);
1410
1411         dev_err(w->i915->drm.dev,
1412                 "%s timed out, cancelling all in-flight rendering.\n",
1413                 w->name);
1414         i915_gem_set_wedged(w->i915);
1415 }
1416
1417 void __i915_init_wedge(struct i915_wedge_me *w,
1418                        struct drm_i915_private *i915,
1419                        long timeout,
1420                        const char *name)
1421 {
1422         w->i915 = i915;
1423         w->name = name;
1424
1425         INIT_DELAYED_WORK_ONSTACK(&w->work, i915_wedge_me);
1426         schedule_delayed_work(&w->work, timeout);
1427 }
1428
1429 void __i915_fini_wedge(struct i915_wedge_me *w)
1430 {
1431         cancel_delayed_work_sync(&w->work);
1432         destroy_delayed_work_on_stack(&w->work);
1433         w->i915 = NULL;
1434 }