drivers/gpu/drm/i915/i915_oa_sklgt4.c

   1 /*
   2  * Autogenerated file by GPU Top : https://github.com/rib/gputop
   3  * DO NOT EDIT manually!
   4  *
   5  *
   6  * Copyright (c) 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysfs.h>
  30
  31 #include "i915_drv.h"
  32 #include "i915_oa_sklgt4.h"
  33
  34 enum metric_set_id {
  35         METRIC_SET_ID_RENDER_BASIC = 1,
  36         METRIC_SET_ID_COMPUTE_BASIC,
  37         METRIC_SET_ID_RENDER_PIPE_PROFILE,
  38         METRIC_SET_ID_MEMORY_READS,
  39         METRIC_SET_ID_MEMORY_WRITES,
  40         METRIC_SET_ID_COMPUTE_EXTENDED,
  41         METRIC_SET_ID_COMPUTE_L3_CACHE,
  42         METRIC_SET_ID_HDC_AND_SF,
  43         METRIC_SET_ID_L3_1,
  44         METRIC_SET_ID_L3_2,
  45         METRIC_SET_ID_L3_3,
  46         METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
  47         METRIC_SET_ID_SAMPLER,
  48         METRIC_SET_ID_TDL_1,
  49         METRIC_SET_ID_TDL_2,
  50         METRIC_SET_ID_COMPUTE_EXTRA,
  51         METRIC_SET_ID_VME_PIPE,
  52         METRIC_SET_ID_TEST_OA,
  53 };
  54
  55 int i915_oa_n_builtin_metric_sets_sklgt4 = 18;
  56
  57 static const struct i915_oa_reg b_counter_config_render_basic[] = {
  58         { _MMIO(0x2710), 0x00000000 },
  59         { _MMIO(0x2714), 0x00800000 },
  60         { _MMIO(0x2720), 0x00000000 },
  61         { _MMIO(0x2724), 0x00800000 },
  62         { _MMIO(0x2740), 0x00000000 },
  63 };
  64
  65 static const struct i915_oa_reg flex_eu_config_render_basic[] = {
  66         { _MMIO(0xe458), 0x00005004 },
  67         { _MMIO(0xe558), 0x00010003 },
  68         { _MMIO(0xe658), 0x00012011 },
  69         { _MMIO(0xe758), 0x00015014 },
  70         { _MMIO(0xe45c), 0x00051050 },
  71         { _MMIO(0xe55c), 0x00053052 },
  72         { _MMIO(0xe65c), 0x00055054 },
  73 };
  74
  75 static const struct i915_oa_reg mux_config_render_basic[] = {
  76         { _MMIO(0x9888), 0x166c01e0 },
  77         { _MMIO(0x9888), 0x12170280 },
  78         { _MMIO(0x9888), 0x12370280 },
  79         { _MMIO(0x9888), 0x16ec01e0 },
  80         { _MMIO(0x9888), 0x176c01e0 },
  81         { _MMIO(0x9888), 0x11930317 },
  82         { _MMIO(0x9888), 0x159303df },
  83         { _MMIO(0x9888), 0x3f900003 },
  84         { _MMIO(0x9888), 0x1a4e03b0 },
  85         { _MMIO(0x9888), 0x0a6c0053 },
  86         { _MMIO(0x9888), 0x106c0000 },
  87         { _MMIO(0x9888), 0x1c6c0000 },
  88         { _MMIO(0x9888), 0x0a1b4000 },
  89         { _MMIO(0x9888), 0x1c1c0001 },
  90         { _MMIO(0x9888), 0x002f1000 },
  91         { _MMIO(0x9888), 0x042f1000 },
  92         { _MMIO(0x9888), 0x004c4000 },
  93         { _MMIO(0x9888), 0x0a4ca400 },
  94         { _MMIO(0x9888), 0x0c4c0002 },
  95         { _MMIO(0x9888), 0x000d2000 },
  96         { _MMIO(0x9888), 0x060d8000 },
  97         { _MMIO(0x9888), 0x080da000 },
  98         { _MMIO(0x9888), 0x0a0da000 },
  99         { _MMIO(0x9888), 0x0c0f0400 },
 100         { _MMIO(0x9888), 0x0e0f5600 },
 101         { _MMIO(0x9888), 0x100f0001 },
 102         { _MMIO(0x9888), 0x002c8000 },
 103         { _MMIO(0x9888), 0x162caa00 },
 104         { _MMIO(0x9888), 0x062d8000 },
 105         { _MMIO(0x9888), 0x00133000 },
 106         { _MMIO(0x9888), 0x08133000 },
 107         { _MMIO(0x9888), 0x00170020 },
 108         { _MMIO(0x9888), 0x08170021 },
 109         { _MMIO(0x9888), 0x10170000 },
 110         { _MMIO(0x9888), 0x0633c000 },
 111         { _MMIO(0x9888), 0x06370800 },
 112         { _MMIO(0x9888), 0x10370000 },
 113         { _MMIO(0x9888), 0x1ace0230 },
 114         { _MMIO(0x9888), 0x0aec5300 },
 115         { _MMIO(0x9888), 0x10ec0000 },
 116         { _MMIO(0x9888), 0x1cec0000 },
 117         { _MMIO(0x9888), 0x0a9b8000 },
 118         { _MMIO(0x9888), 0x1c9c0002 },
 119         { _MMIO(0x9888), 0x0acc2000 },
 120         { _MMIO(0x9888), 0x0ccc0002 },
 121         { _MMIO(0x9888), 0x088d8000 },
 122         { _MMIO(0x9888), 0x0a8d8000 },
 123         { _MMIO(0x9888), 0x0e8f1000 },
 124         { _MMIO(0x9888), 0x108f0001 },
 125         { _MMIO(0x9888), 0x16ac8800 },
 126         { _MMIO(0x9888), 0x1b4e0020 },
 127         { _MMIO(0x9888), 0x096c5300 },
 128         { _MMIO(0x9888), 0x116c0000 },
 129         { _MMIO(0x9888), 0x1d6c0000 },
 130         { _MMIO(0x9888), 0x091b8000 },
 131         { _MMIO(0x9888), 0x1b1c8000 },
 132         { _MMIO(0x9888), 0x0b4c2000 },
 133         { _MMIO(0x9888), 0x090d8000 },
 134         { _MMIO(0x9888), 0x0f0f1000 },
 135         { _MMIO(0x9888), 0x172c0800 },
 136         { _MMIO(0x9888), 0x0d933031 },
 137         { _MMIO(0x9888), 0x0f933e3f },
 138         { _MMIO(0x9888), 0x01933d00 },
 139         { _MMIO(0x9888), 0x0393073c },
 140         { _MMIO(0x9888), 0x0593000e },
 141         { _MMIO(0x9888), 0x1d930000 },
 142         { _MMIO(0x9888), 0x19930000 },
 143         { _MMIO(0x9888), 0x1b930000 },
 144         { _MMIO(0x9888), 0x1d900157 },
 145         { _MMIO(0x9888), 0x1f900158 },
 146         { _MMIO(0x9888), 0x35900000 },
 147         { _MMIO(0x9888), 0x2b908000 },
 148         { _MMIO(0x9888), 0x2d908000 },
 149         { _MMIO(0x9888), 0x2f908000 },
 150         { _MMIO(0x9888), 0x31908000 },
 151         { _MMIO(0x9888), 0x15908000 },
 152         { _MMIO(0x9888), 0x17908000 },
 153         { _MMIO(0x9888), 0x19908000 },
 154         { _MMIO(0x9888), 0x1b908000 },
 155         { _MMIO(0x9888), 0x1190003f },
 156         { _MMIO(0x9888), 0x5190ff30 },
 157         { _MMIO(0x9888), 0x41900060 },
 158         { _MMIO(0x9888), 0x55903033 },
 159         { _MMIO(0x9888), 0x45901421 },
 160         { _MMIO(0x9888), 0x47900803 },
 161         { _MMIO(0x9888), 0x5790fff1 },
 162         { _MMIO(0x9888), 0x49900001 },
 163         { _MMIO(0x9888), 0x37900000 },
 164         { _MMIO(0x9888), 0x33900000 },
 165         { _MMIO(0x9888), 0x4b900000 },
 166         { _MMIO(0x9888), 0x5990000f },
 167         { _MMIO(0x9888), 0x43900000 },
 168         { _MMIO(0x9888), 0x5390ffff },
 169 };
 170
 171 static int
 172 get_render_basic_mux_config(struct drm_i915_private *dev_priv,
 173                             const struct i915_oa_reg **regs,
 174                             int *lens)
 175 {
 176         int n = 0;
 177
 178         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 179         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 180
 181         regs[n] = mux_config_render_basic;
 182         lens[n] = ARRAY_SIZE(mux_config_render_basic);
 183         n++;
 184
 185         return n;
 186 }
 187
 188 static const struct i915_oa_reg b_counter_config_compute_basic[] = {
 189         { _MMIO(0x2710), 0x00000000 },
 190         { _MMIO(0x2714), 0x00800000 },
 191         { _MMIO(0x2720), 0x00000000 },
 192         { _MMIO(0x2724), 0x00800000 },
 193         { _MMIO(0x2740), 0x00000000 },
 194 };
 195
 196 static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
 197         { _MMIO(0xe458), 0x00005004 },
 198         { _MMIO(0xe558), 0x00000003 },
 199         { _MMIO(0xe658), 0x00002001 },
 200         { _MMIO(0xe758), 0x00778008 },
 201         { _MMIO(0xe45c), 0x00088078 },
 202         { _MMIO(0xe55c), 0x00808708 },
 203         { _MMIO(0xe65c), 0x00a08908 },
 204 };
 205
 206 static const struct i915_oa_reg mux_config_compute_basic[] = {
 207         { _MMIO(0x9888), 0x104f00e0 },
 208         { _MMIO(0x9888), 0x124f1c00 },
 209         { _MMIO(0x9888), 0x106c00e0 },
 210         { _MMIO(0x9888), 0x37906800 },
 211         { _MMIO(0x9888), 0x3f900003 },
 212         { _MMIO(0x9888), 0x004e8000 },
 213         { _MMIO(0x9888), 0x1a4e0820 },
 214         { _MMIO(0x9888), 0x1c4e0002 },
 215         { _MMIO(0x9888), 0x064f0900 },
 216         { _MMIO(0x9888), 0x084f0032 },
 217         { _MMIO(0x9888), 0x0a4f1891 },
 218         { _MMIO(0x9888), 0x0c4f0e00 },
 219         { _MMIO(0x9888), 0x0e4f003c },
 220         { _MMIO(0x9888), 0x004f0d80 },
 221         { _MMIO(0x9888), 0x024f003b },
 222         { _MMIO(0x9888), 0x006c0002 },
 223         { _MMIO(0x9888), 0x086c0100 },
 224         { _MMIO(0x9888), 0x0c6c000c },
 225         { _MMIO(0x9888), 0x0e6c0b00 },
 226         { _MMIO(0x9888), 0x186c0000 },
 227         { _MMIO(0x9888), 0x1c6c0000 },
 228         { _MMIO(0x9888), 0x1e6c0000 },
 229         { _MMIO(0x9888), 0x001b4000 },
 230         { _MMIO(0x9888), 0x081b8000 },
 231         { _MMIO(0x9888), 0x0c1b4000 },
 232         { _MMIO(0x9888), 0x0e1b8000 },
 233         { _MMIO(0x9888), 0x101c8000 },
 234         { _MMIO(0x9888), 0x1a1c8000 },
 235         { _MMIO(0x9888), 0x1c1c0024 },
 236         { _MMIO(0x9888), 0x065b8000 },
 237         { _MMIO(0x9888), 0x085b4000 },
 238         { _MMIO(0x9888), 0x0a5bc000 },
 239         { _MMIO(0x9888), 0x0c5b8000 },
 240         { _MMIO(0x9888), 0x0e5b4000 },
 241         { _MMIO(0x9888), 0x005b8000 },
 242         { _MMIO(0x9888), 0x025b4000 },
 243         { _MMIO(0x9888), 0x1a5c6000 },
 244         { _MMIO(0x9888), 0x1c5c001b },
 245         { _MMIO(0x9888), 0x125c8000 },
 246         { _MMIO(0x9888), 0x145c8000 },
 247         { _MMIO(0x9888), 0x004c8000 },
 248         { _MMIO(0x9888), 0x0a4c2000 },
 249         { _MMIO(0x9888), 0x0c4c0208 },
 250         { _MMIO(0x9888), 0x000da000 },
 251         { _MMIO(0x9888), 0x060d8000 },
 252         { _MMIO(0x9888), 0x080da000 },
 253         { _MMIO(0x9888), 0x0a0da000 },
 254         { _MMIO(0x9888), 0x0c0da000 },
 255         { _MMIO(0x9888), 0x0e0da000 },
 256         { _MMIO(0x9888), 0x020d2000 },
 257         { _MMIO(0x9888), 0x0c0f5400 },
 258         { _MMIO(0x9888), 0x0e0f5500 },
 259         { _MMIO(0x9888), 0x100f0155 },
 260         { _MMIO(0x9888), 0x002c8000 },
 261         { _MMIO(0x9888), 0x0e2cc000 },
 262         { _MMIO(0x9888), 0x162cfb00 },
 263         { _MMIO(0x9888), 0x182c00be },
 264         { _MMIO(0x9888), 0x022cc000 },
 265         { _MMIO(0x9888), 0x042cc000 },
 266         { _MMIO(0x9888), 0x19900157 },
 267         { _MMIO(0x9888), 0x1b900158 },
 268         { _MMIO(0x9888), 0x1d900105 },
 269         { _MMIO(0x9888), 0x1f900103 },
 270         { _MMIO(0x9888), 0x35900000 },
 271         { _MMIO(0x9888), 0x11900fff },
 272         { _MMIO(0x9888), 0x51900000 },
 273         { _MMIO(0x9888), 0x41900800 },
 274         { _MMIO(0x9888), 0x55900000 },
 275         { _MMIO(0x9888), 0x45900821 },
 276         { _MMIO(0x9888), 0x47900802 },
 277         { _MMIO(0x9888), 0x57900000 },
 278         { _MMIO(0x9888), 0x49900802 },
 279         { _MMIO(0x9888), 0x33900000 },
 280         { _MMIO(0x9888), 0x4b900002 },
 281         { _MMIO(0x9888), 0x59900000 },
 282         { _MMIO(0x9888), 0x43900422 },
 283         { _MMIO(0x9888), 0x53905555 },
 284 };
 285
 286 static int
 287 get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
 288                              const struct i915_oa_reg **regs,
 289                              int *lens)
 290 {
 291         int n = 0;
 292
 293         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 294         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 295
 296         regs[n] = mux_config_compute_basic;
 297         lens[n] = ARRAY_SIZE(mux_config_compute_basic);
 298         n++;
 299
 300         return n;
 301 }
 302
 303 static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
 304         { _MMIO(0x2724), 0xf0800000 },
 305         { _MMIO(0x2720), 0x00000000 },
 306         { _MMIO(0x2714), 0xf0800000 },
 307         { _MMIO(0x2710), 0x00000000 },
 308         { _MMIO(0x2740), 0x00000000 },
 309         { _MMIO(0x2770), 0x0007ffea },
 310         { _MMIO(0x2774), 0x00007ffc },
 311         { _MMIO(0x2778), 0x0007affa },
 312         { _MMIO(0x277c), 0x0000f5fd },
 313         { _MMIO(0x2780), 0x00079ffa },
 314         { _MMIO(0x2784), 0x0000f3fb },
 315         { _MMIO(0x2788), 0x0007bf7a },
 316         { _MMIO(0x278c), 0x0000f7e7 },
 317         { _MMIO(0x2790), 0x0007fefa },
 318         { _MMIO(0x2794), 0x0000f7cf },
 319         { _MMIO(0x2798), 0x00077ffa },
 320         { _MMIO(0x279c), 0x0000efdf },
 321         { _MMIO(0x27a0), 0x0006fffa },
 322         { _MMIO(0x27a4), 0x0000cfbf },
 323         { _MMIO(0x27a8), 0x0003fffa },
 324         { _MMIO(0x27ac), 0x00005f7f },
 325 };
 326
 327 static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
 328         { _MMIO(0xe458), 0x00005004 },
 329         { _MMIO(0xe558), 0x00015014 },
 330         { _MMIO(0xe658), 0x00025024 },
 331         { _MMIO(0xe758), 0x00035034 },
 332         { _MMIO(0xe45c), 0x00045044 },
 333         { _MMIO(0xe55c), 0x00055054 },
 334         { _MMIO(0xe65c), 0x00065064 },
 335 };
 336
 337 static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
 338         { _MMIO(0x9888), 0x0c0e001f },
 339         { _MMIO(0x9888), 0x0a0f0000 },
 340         { _MMIO(0x9888), 0x10116800 },
 341         { _MMIO(0x9888), 0x178a03e0 },
 342         { _MMIO(0x9888), 0x11824c00 },
 343         { _MMIO(0x9888), 0x11830020 },
 344         { _MMIO(0x9888), 0x13840020 },
 345         { _MMIO(0x9888), 0x11850019 },
 346         { _MMIO(0x9888), 0x11860007 },
 347         { _MMIO(0x9888), 0x01870c40 },
 348         { _MMIO(0x9888), 0x17880000 },
 349         { _MMIO(0x9888), 0x022f4000 },
 350         { _MMIO(0x9888), 0x0a4c0040 },
 351         { _MMIO(0x9888), 0x0c0d8000 },
 352         { _MMIO(0x9888), 0x040d4000 },
 353         { _MMIO(0x9888), 0x060d2000 },
 354         { _MMIO(0x9888), 0x020e5400 },
 355         { _MMIO(0x9888), 0x000e0000 },
 356         { _MMIO(0x9888), 0x080f0040 },
 357         { _MMIO(0x9888), 0x000f0000 },
 358         { _MMIO(0x9888), 0x100f0000 },
 359         { _MMIO(0x9888), 0x0e0f0040 },
 360         { _MMIO(0x9888), 0x0c2c8000 },
 361         { _MMIO(0x9888), 0x06104000 },
 362         { _MMIO(0x9888), 0x06110012 },
 363         { _MMIO(0x9888), 0x06131000 },
 364         { _MMIO(0x9888), 0x01898000 },
 365         { _MMIO(0x9888), 0x0d890100 },
 366         { _MMIO(0x9888), 0x03898000 },
 367         { _MMIO(0x9888), 0x09808000 },
 368         { _MMIO(0x9888), 0x0b808000 },
 369         { _MMIO(0x9888), 0x0380c000 },
 370         { _MMIO(0x9888), 0x0f8a0075 },
 371         { _MMIO(0x9888), 0x1d8a0000 },
 372         { _MMIO(0x9888), 0x118a8000 },
 373         { _MMIO(0x9888), 0x1b8a4000 },
 374         { _MMIO(0x9888), 0x138a8000 },
 375         { _MMIO(0x9888), 0x1d81a000 },
 376         { _MMIO(0x9888), 0x15818000 },
 377         { _MMIO(0x9888), 0x17818000 },
 378         { _MMIO(0x9888), 0x0b820030 },
 379         { _MMIO(0x9888), 0x07828000 },
 380         { _MMIO(0x9888), 0x0d824000 },
 381         { _MMIO(0x9888), 0x0f828000 },
 382         { _MMIO(0x9888), 0x05824000 },
 383         { _MMIO(0x9888), 0x0d830003 },
 384         { _MMIO(0x9888), 0x0583000c },
 385         { _MMIO(0x9888), 0x09830000 },
 386         { _MMIO(0x9888), 0x03838000 },
 387         { _MMIO(0x9888), 0x07838000 },
 388         { _MMIO(0x9888), 0x0b840980 },
 389         { _MMIO(0x9888), 0x03844d80 },
 390         { _MMIO(0x9888), 0x11840000 },
 391         { _MMIO(0x9888), 0x09848000 },
 392         { _MMIO(0x9888), 0x09850080 },
 393         { _MMIO(0x9888), 0x03850003 },
 394         { _MMIO(0x9888), 0x01850000 },
 395         { _MMIO(0x9888), 0x07860000 },
 396         { _MMIO(0x9888), 0x0f860400 },
 397         { _MMIO(0x9888), 0x09870032 },
 398         { _MMIO(0x9888), 0x01888052 },
 399         { _MMIO(0x9888), 0x11880000 },
 400         { _MMIO(0x9888), 0x09884000 },
 401         { _MMIO(0x9888), 0x1b931001 },
 402         { _MMIO(0x9888), 0x1d930001 },
 403         { _MMIO(0x9888), 0x19934000 },
 404         { _MMIO(0x9888), 0x1b958000 },
 405         { _MMIO(0x9888), 0x1d950094 },
 406         { _MMIO(0x9888), 0x19958000 },
 407         { _MMIO(0x9888), 0x09e58000 },
 408         { _MMIO(0x9888), 0x0be58000 },
 409         { _MMIO(0x9888), 0x03e5c000 },
 410         { _MMIO(0x9888), 0x0592c000 },
 411         { _MMIO(0x9888), 0x0b928000 },
 412         { _MMIO(0x9888), 0x0d924000 },
 413         { _MMIO(0x9888), 0x0f924000 },
 414         { _MMIO(0x9888), 0x11928000 },
 415         { _MMIO(0x9888), 0x1392c000 },
 416         { _MMIO(0x9888), 0x09924000 },
 417         { _MMIO(0x9888), 0x01985000 },
 418         { _MMIO(0x9888), 0x07988000 },
 419         { _MMIO(0x9888), 0x09981000 },
 420         { _MMIO(0x9888), 0x0b982000 },
 421         { _MMIO(0x9888), 0x0d982000 },
 422         { _MMIO(0x9888), 0x0f989000 },
 423         { _MMIO(0x9888), 0x05982000 },
 424         { _MMIO(0x9888), 0x13904000 },
 425         { _MMIO(0x9888), 0x21904000 },
 426         { _MMIO(0x9888), 0x23904000 },
 427         { _MMIO(0x9888), 0x25908000 },
 428         { _MMIO(0x9888), 0x27904000 },
 429         { _MMIO(0x9888), 0x29908000 },
 430         { _MMIO(0x9888), 0x2b904000 },
 431         { _MMIO(0x9888), 0x2f904000 },
 432         { _MMIO(0x9888), 0x31904000 },
 433         { _MMIO(0x9888), 0x15904000 },
 434         { _MMIO(0x9888), 0x17908000 },
 435         { _MMIO(0x9888), 0x19908000 },
 436         { _MMIO(0x9888), 0x1b904000 },
 437         { _MMIO(0x9888), 0x1190c080 },
 438         { _MMIO(0x9888), 0x51901110 },
 439         { _MMIO(0x9888), 0x41900440 },
 440         { _MMIO(0x9888), 0x55901111 },
 441         { _MMIO(0x9888), 0x45900400 },
 442         { _MMIO(0x9888), 0x47900c21 },
 443         { _MMIO(0x9888), 0x57901411 },
 444         { _MMIO(0x9888), 0x49900042 },
 445         { _MMIO(0x9888), 0x37900000 },
 446         { _MMIO(0x9888), 0x33900000 },
 447         { _MMIO(0x9888), 0x4b900024 },
 448         { _MMIO(0x9888), 0x59900001 },
 449         { _MMIO(0x9888), 0x43900841 },
 450         { _MMIO(0x9888), 0x53900411 },
 451 };
 452
 453 static int
 454 get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
 455                                    const struct i915_oa_reg **regs,
 456                                    int *lens)
 457 {
 458         int n = 0;
 459
 460         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 461         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 462
 463         regs[n] = mux_config_render_pipe_profile;
 464         lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
 465         n++;
 466
 467         return n;
 468 }
 469
 470 static const struct i915_oa_reg b_counter_config_memory_reads[] = {
 471         { _MMIO(0x272c), 0xffffffff },
 472         { _MMIO(0x2728), 0xffffffff },
 473         { _MMIO(0x2724), 0xf0800000 },
 474         { _MMIO(0x2720), 0x00000000 },
 475         { _MMIO(0x271c), 0xffffffff },
 476         { _MMIO(0x2718), 0xffffffff },
 477         { _MMIO(0x2714), 0xf0800000 },
 478         { _MMIO(0x2710), 0x00000000 },
 479         { _MMIO(0x274c), 0x86543210 },
 480         { _MMIO(0x2748), 0x86543210 },
 481         { _MMIO(0x2744), 0x00006667 },
 482         { _MMIO(0x2740), 0x00000000 },
 483         { _MMIO(0x275c), 0x86543210 },
 484         { _MMIO(0x2758), 0x86543210 },
 485         { _MMIO(0x2754), 0x00006465 },
 486         { _MMIO(0x2750), 0x00000000 },
 487         { _MMIO(0x2770), 0x0007f81a },
 488         { _MMIO(0x2774), 0x0000fe00 },
 489         { _MMIO(0x2778), 0x0007f82a },
 490         { _MMIO(0x277c), 0x0000fe00 },
 491         { _MMIO(0x2780), 0x0007f872 },
 492         { _MMIO(0x2784), 0x0000fe00 },
 493         { _MMIO(0x2788), 0x0007f8ba },
 494         { _MMIO(0x278c), 0x0000fe00 },
 495         { _MMIO(0x2790), 0x0007f87a },
 496         { _MMIO(0x2794), 0x0000fe00 },
 497         { _MMIO(0x2798), 0x0007f8ea },
 498         { _MMIO(0x279c), 0x0000fe00 },
 499         { _MMIO(0x27a0), 0x0007f8e2 },
 500         { _MMIO(0x27a4), 0x0000fe00 },
 501         { _MMIO(0x27a8), 0x0007f8f2 },
 502         { _MMIO(0x27ac), 0x0000fe00 },
 503 };
 504
 505 static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
 506         { _MMIO(0xe458), 0x00005004 },
 507         { _MMIO(0xe558), 0x00015014 },
 508         { _MMIO(0xe658), 0x00025024 },
 509         { _MMIO(0xe758), 0x00035034 },
 510         { _MMIO(0xe45c), 0x00045044 },
 511         { _MMIO(0xe55c), 0x00055054 },
 512         { _MMIO(0xe65c), 0x00065064 },
 513 };
 514
 515 static const struct i915_oa_reg mux_config_memory_reads[] = {
 516         { _MMIO(0x9888), 0x11810c00 },
 517         { _MMIO(0x9888), 0x1381001a },
 518         { _MMIO(0x9888), 0x37906800 },
 519         { _MMIO(0x9888), 0x3f900064 },
 520         { _MMIO(0x9888), 0x03811300 },
 521         { _MMIO(0x9888), 0x05811b12 },
 522         { _MMIO(0x9888), 0x0781001a },
 523         { _MMIO(0x9888), 0x1f810000 },
 524         { _MMIO(0x9888), 0x17810000 },
 525         { _MMIO(0x9888), 0x19810000 },
 526         { _MMIO(0x9888), 0x1b810000 },
 527         { _MMIO(0x9888), 0x1d810000 },
 528         { _MMIO(0x9888), 0x1b930055 },
 529         { _MMIO(0x9888), 0x03e58000 },
 530         { _MMIO(0x9888), 0x05e5c000 },
 531         { _MMIO(0x9888), 0x07e54000 },
 532         { _MMIO(0x9888), 0x13900150 },
 533         { _MMIO(0x9888), 0x21900151 },
 534         { _MMIO(0x9888), 0x23900152 },
 535         { _MMIO(0x9888), 0x25900153 },
 536         { _MMIO(0x9888), 0x27900154 },
 537         { _MMIO(0x9888), 0x29900155 },
 538         { _MMIO(0x9888), 0x2b900156 },
 539         { _MMIO(0x9888), 0x2d900157 },
 540         { _MMIO(0x9888), 0x2f90015f },
 541         { _MMIO(0x9888), 0x31900105 },
 542         { _MMIO(0x9888), 0x15900103 },
 543         { _MMIO(0x9888), 0x17900101 },
 544         { _MMIO(0x9888), 0x35900000 },
 545         { _MMIO(0x9888), 0x19908000 },
 546         { _MMIO(0x9888), 0x1b908000 },
 547         { _MMIO(0x9888), 0x1d908000 },
 548         { _MMIO(0x9888), 0x1f908000 },
 549         { _MMIO(0x9888), 0x11900000 },
 550         { _MMIO(0x9888), 0x51900000 },
 551         { _MMIO(0x9888), 0x41900c60 },
 552         { _MMIO(0x9888), 0x55900000 },
 553         { _MMIO(0x9888), 0x45900c00 },
 554         { _MMIO(0x9888), 0x47900c63 },
 555         { _MMIO(0x9888), 0x57900000 },
 556         { _MMIO(0x9888), 0x49900c63 },
 557         { _MMIO(0x9888), 0x33900000 },
 558         { _MMIO(0x9888), 0x4b900063 },
 559         { _MMIO(0x9888), 0x59900000 },
 560         { _MMIO(0x9888), 0x43900003 },
 561         { _MMIO(0x9888), 0x53900000 },
 562 };
 563
 564 static int
 565 get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
 566                             const struct i915_oa_reg **regs,
 567                             int *lens)
 568 {
 569         int n = 0;
 570
 571         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 572         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 573
 574         regs[n] = mux_config_memory_reads;
 575         lens[n] = ARRAY_SIZE(mux_config_memory_reads);
 576         n++;
 577
 578         return n;
 579 }
 580
 581 static const struct i915_oa_reg b_counter_config_memory_writes[] = {
 582         { _MMIO(0x272c), 0xffffffff },
 583         { _MMIO(0x2728), 0xffffffff },
 584         { _MMIO(0x2724), 0xf0800000 },
 585         { _MMIO(0x2720), 0x00000000 },
 586         { _MMIO(0x271c), 0xffffffff },
 587         { _MMIO(0x2718), 0xffffffff },
 588         { _MMIO(0x2714), 0xf0800000 },
 589         { _MMIO(0x2710), 0x00000000 },
 590         { _MMIO(0x274c), 0x86543210 },
 591         { _MMIO(0x2748), 0x86543210 },
 592         { _MMIO(0x2744), 0x00006667 },
 593         { _MMIO(0x2740), 0x00000000 },
 594         { _MMIO(0x275c), 0x86543210 },
 595         { _MMIO(0x2758), 0x86543210 },
 596         { _MMIO(0x2754), 0x00006465 },
 597         { _MMIO(0x2750), 0x00000000 },
 598         { _MMIO(0x2770), 0x0007f81a },
 599         { _MMIO(0x2774), 0x0000fe00 },
 600         { _MMIO(0x2778), 0x0007f82a },
 601         { _MMIO(0x277c), 0x0000fe00 },
 602         { _MMIO(0x2780), 0x0007f822 },
 603         { _MMIO(0x2784), 0x0000fe00 },
 604         { _MMIO(0x2788), 0x0007f8ba },
 605         { _MMIO(0x278c), 0x0000fe00 },
 606         { _MMIO(0x2790), 0x0007f87a },
 607         { _MMIO(0x2794), 0x0000fe00 },
 608         { _MMIO(0x2798), 0x0007f8ea },
 609         { _MMIO(0x279c), 0x0000fe00 },
 610         { _MMIO(0x27a0), 0x0007f8e2 },
 611         { _MMIO(0x27a4), 0x0000fe00 },
 612         { _MMIO(0x27a8), 0x0007f8f2 },
 613         { _MMIO(0x27ac), 0x0000fe00 },
 614 };
 615
 616 static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
 617         { _MMIO(0xe458), 0x00005004 },
 618         { _MMIO(0xe558), 0x00015014 },
 619         { _MMIO(0xe658), 0x00025024 },
 620         { _MMIO(0xe758), 0x00035034 },
 621         { _MMIO(0xe45c), 0x00045044 },
 622         { _MMIO(0xe55c), 0x00055054 },
 623         { _MMIO(0xe65c), 0x00065064 },
 624 };
 625
 626 static const struct i915_oa_reg mux_config_memory_writes[] = {
 627         { _MMIO(0x9888), 0x11810c00 },
 628         { _MMIO(0x9888), 0x1381001a },
 629         { _MMIO(0x9888), 0x37906800 },
 630         { _MMIO(0x9888), 0x3f901000 },
 631         { _MMIO(0x9888), 0x03811300 },
 632         { _MMIO(0x9888), 0x05811b12 },
 633         { _MMIO(0x9888), 0x0781001a },
 634         { _MMIO(0x9888), 0x1f810000 },
 635         { _MMIO(0x9888), 0x17810000 },
 636         { _MMIO(0x9888), 0x19810000 },
 637         { _MMIO(0x9888), 0x1b810000 },
 638         { _MMIO(0x9888), 0x1d810000 },
 639         { _MMIO(0x9888), 0x1b930055 },
 640         { _MMIO(0x9888), 0x03e58000 },
 641         { _MMIO(0x9888), 0x05e5c000 },
 642         { _MMIO(0x9888), 0x07e54000 },
 643         { _MMIO(0x9888), 0x13900160 },
 644         { _MMIO(0x9888), 0x21900161 },
 645         { _MMIO(0x9888), 0x23900162 },
 646         { _MMIO(0x9888), 0x25900163 },
 647         { _MMIO(0x9888), 0x27900164 },
 648         { _MMIO(0x9888), 0x29900165 },
 649         { _MMIO(0x9888), 0x2b900166 },
 650         { _MMIO(0x9888), 0x2d900167 },
 651         { _MMIO(0x9888), 0x2f900150 },
 652         { _MMIO(0x9888), 0x31900105 },
 653         { _MMIO(0x9888), 0x15900103 },
 654         { _MMIO(0x9888), 0x17900101 },
 655         { _MMIO(0x9888), 0x35900000 },
 656         { _MMIO(0x9888), 0x19908000 },
 657         { _MMIO(0x9888), 0x1b908000 },
 658         { _MMIO(0x9888), 0x1d908000 },
 659         { _MMIO(0x9888), 0x1f908000 },
 660         { _MMIO(0x9888), 0x11900000 },
 661         { _MMIO(0x9888), 0x51900000 },
 662         { _MMIO(0x9888), 0x41900c60 },
 663         { _MMIO(0x9888), 0x55900000 },
 664         { _MMIO(0x9888), 0x45900c00 },
 665         { _MMIO(0x9888), 0x47900c63 },
 666         { _MMIO(0x9888), 0x57900000 },
 667         { _MMIO(0x9888), 0x49900c63 },
 668         { _MMIO(0x9888), 0x33900000 },
 669         { _MMIO(0x9888), 0x4b900063 },
 670         { _MMIO(0x9888), 0x59900000 },
 671         { _MMIO(0x9888), 0x43900003 },
 672         { _MMIO(0x9888), 0x53900000 },
 673 };
 674
 675 static int
 676 get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
 677                              const struct i915_oa_reg **regs,
 678                              int *lens)
 679 {
 680         int n = 0;
 681
 682         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 683         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 684
 685         regs[n] = mux_config_memory_writes;
 686         lens[n] = ARRAY_SIZE(mux_config_memory_writes);
 687         n++;
 688
 689         return n;
 690 }
 691
 692 static const struct i915_oa_reg b_counter_config_compute_extended[] = {
 693         { _MMIO(0x2724), 0xf0800000 },
 694         { _MMIO(0x2720), 0x00000000 },
 695         { _MMIO(0x2714), 0xf0800000 },
 696         { _MMIO(0x2710), 0x00000000 },
 697         { _MMIO(0x2740), 0x00000000 },
 698         { _MMIO(0x2770), 0x0007fc2a },
 699         { _MMIO(0x2774), 0x0000bf00 },
 700         { _MMIO(0x2778), 0x0007fc6a },
 701         { _MMIO(0x277c), 0x0000bf00 },
 702         { _MMIO(0x2780), 0x0007fc92 },
 703         { _MMIO(0x2784), 0x0000bf00 },
 704         { _MMIO(0x2788), 0x0007fca2 },
 705         { _MMIO(0x278c), 0x0000bf00 },
 706         { _MMIO(0x2790), 0x0007fc32 },
 707         { _MMIO(0x2794), 0x0000bf00 },
 708         { _MMIO(0x2798), 0x0007fc9a },
 709         { _MMIO(0x279c), 0x0000bf00 },
 710         { _MMIO(0x27a0), 0x0007fe6a },
 711         { _MMIO(0x27a4), 0x0000bf00 },
 712         { _MMIO(0x27a8), 0x0007fe7a },
 713         { _MMIO(0x27ac), 0x0000bf00 },
 714 };
 715
 716 static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
 717         { _MMIO(0xe458), 0x00005004 },
 718         { _MMIO(0xe558), 0x00000003 },
 719         { _MMIO(0xe658), 0x00002001 },
 720         { _MMIO(0xe758), 0x00778008 },
 721         { _MMIO(0xe45c), 0x00088078 },
 722         { _MMIO(0xe55c), 0x00808708 },
 723         { _MMIO(0xe65c), 0x00a08908 },
 724 };
 725
 726 static const struct i915_oa_reg mux_config_compute_extended[] = {
 727         { _MMIO(0x9888), 0x106c00e0 },
 728         { _MMIO(0x9888), 0x141c8160 },
 729         { _MMIO(0x9888), 0x161c8015 },
 730         { _MMIO(0x9888), 0x181c0120 },
 731         { _MMIO(0x9888), 0x004e8000 },
 732         { _MMIO(0x9888), 0x0e4e8000 },
 733         { _MMIO(0x9888), 0x184e8000 },
 734         { _MMIO(0x9888), 0x1a4eaaa0 },
 735         { _MMIO(0x9888), 0x1c4e0002 },
 736         { _MMIO(0x9888), 0x024e8000 },
 737         { _MMIO(0x9888), 0x044e8000 },
 738         { _MMIO(0x9888), 0x064e8000 },
 739         { _MMIO(0x9888), 0x084e8000 },
 740         { _MMIO(0x9888), 0x0a4e8000 },
 741         { _MMIO(0x9888), 0x0e6c0b01 },
 742         { _MMIO(0x9888), 0x006c0200 },
 743         { _MMIO(0x9888), 0x026c000c },
 744         { _MMIO(0x9888), 0x1c6c0000 },
 745         { _MMIO(0x9888), 0x1e6c0000 },
 746         { _MMIO(0x9888), 0x1a6c0000 },
 747         { _MMIO(0x9888), 0x0e1bc000 },
 748         { _MMIO(0x9888), 0x001b8000 },
 749         { _MMIO(0x9888), 0x021bc000 },
 750         { _MMIO(0x9888), 0x001c0041 },
 751         { _MMIO(0x9888), 0x061c4200 },
 752         { _MMIO(0x9888), 0x081c4443 },
 753         { _MMIO(0x9888), 0x0a1c4645 },
 754         { _MMIO(0x9888), 0x0c1c7647 },
 755         { _MMIO(0x9888), 0x041c7357 },
 756         { _MMIO(0x9888), 0x1c1c0030 },
 757         { _MMIO(0x9888), 0x101c0000 },
 758         { _MMIO(0x9888), 0x1a1c0000 },
 759         { _MMIO(0x9888), 0x121c8000 },
 760         { _MMIO(0x9888), 0x004c8000 },
 761         { _MMIO(0x9888), 0x0a4caa2a },
 762         { _MMIO(0x9888), 0x0c4c02aa },
 763         { _MMIO(0x9888), 0x084ca000 },
 764         { _MMIO(0x9888), 0x000da000 },
 765         { _MMIO(0x9888), 0x060d8000 },
 766         { _MMIO(0x9888), 0x080da000 },
 767         { _MMIO(0x9888), 0x0a0da000 },
 768         { _MMIO(0x9888), 0x0c0da000 },
 769         { _MMIO(0x9888), 0x0e0da000 },
 770         { _MMIO(0x9888), 0x020da000 },
 771         { _MMIO(0x9888), 0x040da000 },
 772         { _MMIO(0x9888), 0x0c0f5400 },
 773         { _MMIO(0x9888), 0x0e0f5515 },
 774         { _MMIO(0x9888), 0x100f0155 },
 775         { _MMIO(0x9888), 0x002c8000 },
 776         { _MMIO(0x9888), 0x0e2c8000 },
 777         { _MMIO(0x9888), 0x162caa00 },
 778         { _MMIO(0x9888), 0x182c00aa },
 779         { _MMIO(0x9888), 0x022c8000 },
 780         { _MMIO(0x9888), 0x042c8000 },
 781         { _MMIO(0x9888), 0x062c8000 },
 782         { _MMIO(0x9888), 0x082c8000 },
 783         { _MMIO(0x9888), 0x0a2c8000 },
 784         { _MMIO(0x9888), 0x11907fff },
 785         { _MMIO(0x9888), 0x51900000 },
 786         { _MMIO(0x9888), 0x41900040 },
 787         { _MMIO(0x9888), 0x55900000 },
 788         { _MMIO(0x9888), 0x45900802 },
 789         { _MMIO(0x9888), 0x47900842 },
 790         { _MMIO(0x9888), 0x57900000 },
 791         { _MMIO(0x9888), 0x49900842 },
 792         { _MMIO(0x9888), 0x37900000 },
 793         { _MMIO(0x9888), 0x33900000 },
 794         { _MMIO(0x9888), 0x4b900000 },
 795         { _MMIO(0x9888), 0x59900000 },
 796         { _MMIO(0x9888), 0x43900800 },
 797         { _MMIO(0x9888), 0x53900000 },
 798 };
 799
 800 static int
 801 get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
 802                                 const struct i915_oa_reg **regs,
 803                                 int *lens)
 804 {
 805         int n = 0;
 806
 807         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 808         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 809
 810         regs[n] = mux_config_compute_extended;
 811         lens[n] = ARRAY_SIZE(mux_config_compute_extended);
 812         n++;
 813
 814         return n;
 815 }
 816
 817 static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
 818         { _MMIO(0x2710), 0x00000000 },
 819         { _MMIO(0x2714), 0x30800000 },
 820         { _MMIO(0x2720), 0x00000000 },
 821         { _MMIO(0x2724), 0x30800000 },
 822         { _MMIO(0x2740), 0x00000000 },
 823         { _MMIO(0x2770), 0x0007fffa },
 824         { _MMIO(0x2774), 0x0000fefe },
 825         { _MMIO(0x2778), 0x0007fffa },
 826         { _MMIO(0x277c), 0x0000fefd },
 827         { _MMIO(0x2790), 0x0007fffa },
 828         { _MMIO(0x2794), 0x0000fbef },
 829         { _MMIO(0x2798), 0x0007fffa },
 830         { _MMIO(0x279c), 0x0000fbdf },
 831 };
 832
 833 static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
 834         { _MMIO(0xe458), 0x00005004 },
 835         { _MMIO(0xe558), 0x00000003 },
 836         { _MMIO(0xe658), 0x00002001 },
 837         { _MMIO(0xe758), 0x00101100 },
 838         { _MMIO(0xe45c), 0x00201200 },
 839         { _MMIO(0xe55c), 0x00301300 },
 840         { _MMIO(0xe65c), 0x00401400 },
 841 };
 842
 843 static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
 844         { _MMIO(0x9888), 0x166c0760 },
 845         { _MMIO(0x9888), 0x1593001e },
 846         { _MMIO(0x9888), 0x3f900003 },
 847         { _MMIO(0x9888), 0x004e8000 },
 848         { _MMIO(0x9888), 0x0e4e8000 },
 849         { _MMIO(0x9888), 0x184e8000 },
 850         { _MMIO(0x9888), 0x1a4e8020 },
 851         { _MMIO(0x9888), 0x1c4e0002 },
 852         { _MMIO(0x9888), 0x006c0051 },
 853         { _MMIO(0x9888), 0x066c5000 },
 854         { _MMIO(0x9888), 0x086c5c5d },
 855         { _MMIO(0x9888), 0x0e6c5e5f },
 856         { _MMIO(0x9888), 0x106c0000 },
 857         { _MMIO(0x9888), 0x186c0000 },
 858         { _MMIO(0x9888), 0x1c6c0000 },
 859         { _MMIO(0x9888), 0x1e6c0000 },
 860         { _MMIO(0x9888), 0x001b4000 },
 861         { _MMIO(0x9888), 0x061b8000 },
 862         { _MMIO(0x9888), 0x081bc000 },
 863         { _MMIO(0x9888), 0x0e1bc000 },
 864         { _MMIO(0x9888), 0x101c8000 },
 865         { _MMIO(0x9888), 0x1a1ce000 },
 866         { _MMIO(0x9888), 0x1c1c0030 },
 867         { _MMIO(0x9888), 0x004c8000 },
 868         { _MMIO(0x9888), 0x0a4c2a00 },
 869         { _MMIO(0x9888), 0x0c4c0280 },
 870         { _MMIO(0x9888), 0x000d2000 },
 871         { _MMIO(0x9888), 0x060d8000 },
 872         { _MMIO(0x9888), 0x080da000 },
 873         { _MMIO(0x9888), 0x0e0da000 },
 874         { _MMIO(0x9888), 0x0c0f0400 },
 875         { _MMIO(0x9888), 0x0e0f1500 },
 876         { _MMIO(0x9888), 0x100f0140 },
 877         { _MMIO(0x9888), 0x002c8000 },
 878         { _MMIO(0x9888), 0x0e2c8000 },
 879         { _MMIO(0x9888), 0x162c0a00 },
 880         { _MMIO(0x9888), 0x182c00a0 },
 881         { _MMIO(0x9888), 0x03933300 },
 882         { _MMIO(0x9888), 0x05930032 },
 883         { _MMIO(0x9888), 0x11930000 },
 884         { _MMIO(0x9888), 0x1b930000 },
 885         { _MMIO(0x9888), 0x1d900157 },
 886         { _MMIO(0x9888), 0x1f900158 },
 887         { _MMIO(0x9888), 0x35900000 },
 888         { _MMIO(0x9888), 0x19908000 },
 889         { _MMIO(0x9888), 0x1b908000 },
 890         { _MMIO(0x9888), 0x1190030f },
 891         { _MMIO(0x9888), 0x51900000 },
 892         { _MMIO(0x9888), 0x41900000 },
 893         { _MMIO(0x9888), 0x55900000 },
 894         { _MMIO(0x9888), 0x45900021 },
 895         { _MMIO(0x9888), 0x47900000 },
 896         { _MMIO(0x9888), 0x37900000 },
 897         { _MMIO(0x9888), 0x33900000 },
 898         { _MMIO(0x9888), 0x57900000 },
 899         { _MMIO(0x9888), 0x4b900000 },
 900         { _MMIO(0x9888), 0x59900000 },
 901         { _MMIO(0x9888), 0x53905555 },
 902         { _MMIO(0x9888), 0x43900000 },
 903 };
 904
 905 static int
 906 get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
 907                                 const struct i915_oa_reg **regs,
 908                                 int *lens)
 909 {
 910         int n = 0;
 911
 912         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 913         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 914
 915         regs[n] = mux_config_compute_l3_cache;
 916         lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
 917         n++;
 918
 919         return n;
 920 }
 921
 922 static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
 923         { _MMIO(0x2740), 0x00000000 },
 924         { _MMIO(0x2744), 0x00800000 },
 925         { _MMIO(0x2710), 0x00000000 },
 926         { _MMIO(0x2714), 0x10800000 },
 927         { _MMIO(0x2720), 0x00000000 },
 928         { _MMIO(0x2724), 0x00800000 },
 929         { _MMIO(0x2770), 0x00000002 },
 930         { _MMIO(0x2774), 0x0000fdff },
 931 };
 932
 933 static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
 934         { _MMIO(0xe458), 0x00005004 },
 935         { _MMIO(0xe558), 0x00010003 },
 936         { _MMIO(0xe658), 0x00012011 },
 937         { _MMIO(0xe758), 0x00015014 },
 938         { _MMIO(0xe45c), 0x00051050 },
 939         { _MMIO(0xe55c), 0x00053052 },
 940         { _MMIO(0xe65c), 0x00055054 },
 941 };
 942
 943 static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
 944         { _MMIO(0x9888), 0x104f0232 },
 945         { _MMIO(0x9888), 0x124f4640 },
 946         { _MMIO(0x9888), 0x106c0232 },
 947         { _MMIO(0x9888), 0x11834400 },
 948         { _MMIO(0x9888), 0x0a4e8000 },
 949         { _MMIO(0x9888), 0x0c4e8000 },
 950         { _MMIO(0x9888), 0x004f1880 },
 951         { _MMIO(0x9888), 0x024f08bb },
 952         { _MMIO(0x9888), 0x044f001b },
 953         { _MMIO(0x9888), 0x046c0100 },
 954         { _MMIO(0x9888), 0x066c000b },
 955         { _MMIO(0x9888), 0x1a6c0000 },
 956         { _MMIO(0x9888), 0x041b8000 },
 957         { _MMIO(0x9888), 0x061b4000 },
 958         { _MMIO(0x9888), 0x1a1c1800 },
 959         { _MMIO(0x9888), 0x005b8000 },
 960         { _MMIO(0x9888), 0x025bc000 },
 961         { _MMIO(0x9888), 0x045b4000 },
 962         { _MMIO(0x9888), 0x125c8000 },
 963         { _MMIO(0x9888), 0x145c8000 },
 964         { _MMIO(0x9888), 0x165c8000 },
 965         { _MMIO(0x9888), 0x185c8000 },
 966         { _MMIO(0x9888), 0x0a4c00a0 },
 967         { _MMIO(0x9888), 0x000d8000 },
 968         { _MMIO(0x9888), 0x020da000 },
 969         { _MMIO(0x9888), 0x040da000 },
 970         { _MMIO(0x9888), 0x060d2000 },
 971         { _MMIO(0x9888), 0x0c0f5000 },
 972         { _MMIO(0x9888), 0x0e0f0055 },
 973         { _MMIO(0x9888), 0x022cc000 },
 974         { _MMIO(0x9888), 0x042cc000 },
 975         { _MMIO(0x9888), 0x062cc000 },
 976         { _MMIO(0x9888), 0x082cc000 },
 977         { _MMIO(0x9888), 0x0a2c8000 },
 978         { _MMIO(0x9888), 0x0c2c8000 },
 979         { _MMIO(0x9888), 0x0f828000 },
 980         { _MMIO(0x9888), 0x0f8305c0 },
 981         { _MMIO(0x9888), 0x09830000 },
 982         { _MMIO(0x9888), 0x07830000 },
 983         { _MMIO(0x9888), 0x1d950080 },
 984         { _MMIO(0x9888), 0x13928000 },
 985         { _MMIO(0x9888), 0x0f988000 },
 986         { _MMIO(0x9888), 0x31904000 },
 987         { _MMIO(0x9888), 0x1190fc00 },
 988         { _MMIO(0x9888), 0x37900000 },
 989         { _MMIO(0x9888), 0x59900001 },
 990         { _MMIO(0x9888), 0x4b900040 },
 991         { _MMIO(0x9888), 0x51900000 },
 992         { _MMIO(0x9888), 0x41900800 },
 993         { _MMIO(0x9888), 0x43900842 },
 994         { _MMIO(0x9888), 0x53900000 },
 995         { _MMIO(0x9888), 0x45900000 },
 996         { _MMIO(0x9888), 0x33900000 },
 997 };
 998
 999 static int
1000 get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
1001                           const struct i915_oa_reg **regs,
1002                           int *lens)
1003 {
1004         int n = 0;
1005
1006         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1007         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1008
1009         regs[n] = mux_config_hdc_and_sf;
1010         lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
1011         n++;
1012
1013         return n;
1014 }
1015
1016 static const struct i915_oa_reg b_counter_config_l3_1[] = {
1017         { _MMIO(0x2740), 0x00000000 },
1018         { _MMIO(0x2744), 0x00800000 },
1019         { _MMIO(0x2710), 0x00000000 },
1020         { _MMIO(0x2714), 0xf0800000 },
1021         { _MMIO(0x2720), 0x00000000 },
1022         { _MMIO(0x2724), 0xf0800000 },
1023         { _MMIO(0x2770), 0x00100070 },
1024         { _MMIO(0x2774), 0x0000fff1 },
1025         { _MMIO(0x2778), 0x00014002 },
1026         { _MMIO(0x277c), 0x0000c3ff },
1027         { _MMIO(0x2780), 0x00010002 },
1028         { _MMIO(0x2784), 0x0000c7ff },
1029         { _MMIO(0x2788), 0x00004002 },
1030         { _MMIO(0x278c), 0x0000d3ff },
1031         { _MMIO(0x2790), 0x00100700 },
1032         { _MMIO(0x2794), 0x0000ff1f },
1033         { _MMIO(0x2798), 0x00001402 },
1034         { _MMIO(0x279c), 0x0000fc3f },
1035         { _MMIO(0x27a0), 0x00001002 },
1036         { _MMIO(0x27a4), 0x0000fc7f },
1037         { _MMIO(0x27a8), 0x00000402 },
1038         { _MMIO(0x27ac), 0x0000fd3f },
1039 };
1040
1041 static const struct i915_oa_reg flex_eu_config_l3_1[] = {
1042         { _MMIO(0xe458), 0x00005004 },
1043         { _MMIO(0xe558), 0x00010003 },
1044         { _MMIO(0xe658), 0x00012011 },
1045         { _MMIO(0xe758), 0x00015014 },
1046         { _MMIO(0xe45c), 0x00051050 },
1047         { _MMIO(0xe55c), 0x00053052 },
1048         { _MMIO(0xe65c), 0x00055054 },
1049 };
1050
1051 static const struct i915_oa_reg mux_config_l3_1[] = {
1052         { _MMIO(0x9888), 0x126c7b40 },
1053         { _MMIO(0x9888), 0x166c0020 },
1054         { _MMIO(0x9888), 0x0a603444 },
1055         { _MMIO(0x9888), 0x0a613400 },
1056         { _MMIO(0x9888), 0x1a4ea800 },
1057         { _MMIO(0x9888), 0x1c4e0002 },
1058         { _MMIO(0x9888), 0x024e8000 },
1059         { _MMIO(0x9888), 0x044e8000 },
1060         { _MMIO(0x9888), 0x064e8000 },
1061         { _MMIO(0x9888), 0x084e8000 },
1062         { _MMIO(0x9888), 0x0a4e8000 },
1063         { _MMIO(0x9888), 0x064f4000 },
1064         { _MMIO(0x9888), 0x0c6c5327 },
1065         { _MMIO(0x9888), 0x0e6c5425 },
1066         { _MMIO(0x9888), 0x006c2a00 },
1067         { _MMIO(0x9888), 0x026c285b },
1068         { _MMIO(0x9888), 0x046c005c },
1069         { _MMIO(0x9888), 0x106c0000 },
1070         { _MMIO(0x9888), 0x1c6c0000 },
1071         { _MMIO(0x9888), 0x1e6c0000 },
1072         { _MMIO(0x9888), 0x1a6c0800 },
1073         { _MMIO(0x9888), 0x0c1bc000 },
1074         { _MMIO(0x9888), 0x0e1bc000 },
1075         { _MMIO(0x9888), 0x001b8000 },
1076         { _MMIO(0x9888), 0x021bc000 },
1077         { _MMIO(0x9888), 0x041bc000 },
1078         { _MMIO(0x9888), 0x1c1c003c },
1079         { _MMIO(0x9888), 0x121c8000 },
1080         { _MMIO(0x9888), 0x141c8000 },
1081         { _MMIO(0x9888), 0x161c8000 },
1082         { _MMIO(0x9888), 0x181c8000 },
1083         { _MMIO(0x9888), 0x1a1c0800 },
1084         { _MMIO(0x9888), 0x065b4000 },
1085         { _MMIO(0x9888), 0x1a5c1000 },
1086         { _MMIO(0x9888), 0x10600000 },
1087         { _MMIO(0x9888), 0x04600000 },
1088         { _MMIO(0x9888), 0x0c610044 },
1089         { _MMIO(0x9888), 0x10610000 },
1090         { _MMIO(0x9888), 0x06610000 },
1091         { _MMIO(0x9888), 0x0c4c02a8 },
1092         { _MMIO(0x9888), 0x084ca000 },
1093         { _MMIO(0x9888), 0x0a4c002a },
1094         { _MMIO(0x9888), 0x0c0da000 },
1095         { _MMIO(0x9888), 0x0e0da000 },
1096         { _MMIO(0x9888), 0x000d8000 },
1097         { _MMIO(0x9888), 0x020da000 },
1098         { _MMIO(0x9888), 0x040da000 },
1099         { _MMIO(0x9888), 0x060d2000 },
1100         { _MMIO(0x9888), 0x100f0154 },
1101         { _MMIO(0x9888), 0x0c0f5000 },
1102         { _MMIO(0x9888), 0x0e0f0055 },
1103         { _MMIO(0x9888), 0x182c00aa },
1104         { _MMIO(0x9888), 0x022c8000 },
1105         { _MMIO(0x9888), 0x042c8000 },
1106         { _MMIO(0x9888), 0x062c8000 },
1107         { _MMIO(0x9888), 0x082c8000 },
1108         { _MMIO(0x9888), 0x0a2c8000 },
1109         { _MMIO(0x9888), 0x0c2cc000 },
1110         { _MMIO(0x9888), 0x1190ffc0 },
1111         { _MMIO(0x9888), 0x57900000 },
1112         { _MMIO(0x9888), 0x49900420 },
1113         { _MMIO(0x9888), 0x37900000 },
1114         { _MMIO(0x9888), 0x33900000 },
1115         { _MMIO(0x9888), 0x4b900021 },
1116         { _MMIO(0x9888), 0x59900000 },
1117         { _MMIO(0x9888), 0x51900000 },
1118         { _MMIO(0x9888), 0x41900400 },
1119         { _MMIO(0x9888), 0x43900421 },
1120         { _MMIO(0x9888), 0x53900000 },
1121         { _MMIO(0x9888), 0x45900040 },
1122 };
1123
1124 static int
1125 get_l3_1_mux_config(struct drm_i915_private *dev_priv,
1126                     const struct i915_oa_reg **regs,
1127                     int *lens)
1128 {
1129         int n = 0;
1130
1131         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1132         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1133
1134         regs[n] = mux_config_l3_1;
1135         lens[n] = ARRAY_SIZE(mux_config_l3_1);
1136         n++;
1137
1138         return n;
1139 }
1140
1141 static const struct i915_oa_reg b_counter_config_l3_2[] = {
1142         { _MMIO(0x2740), 0x00000000 },
1143         { _MMIO(0x2744), 0x00800000 },
1144         { _MMIO(0x2710), 0x00000000 },
1145         { _MMIO(0x2714), 0xf0800000 },
1146         { _MMIO(0x2720), 0x00000000 },
1147         { _MMIO(0x2724), 0x00800000 },
1148         { _MMIO(0x2770), 0x00100070 },
1149         { _MMIO(0x2774), 0x0000fff1 },
1150         { _MMIO(0x2778), 0x00028002 },
1151         { _MMIO(0x277c), 0x000087ff },
1152         { _MMIO(0x2780), 0x00020002 },
1153         { _MMIO(0x2784), 0x00008fff },
1154         { _MMIO(0x2788), 0x00008002 },
1155         { _MMIO(0x278c), 0x0000a7ff },
1156 };
1157
1158 static const struct i915_oa_reg flex_eu_config_l3_2[] = {
1159         { _MMIO(0xe458), 0x00005004 },
1160         { _MMIO(0xe558), 0x00010003 },
1161         { _MMIO(0xe658), 0x00012011 },
1162         { _MMIO(0xe758), 0x00015014 },
1163         { _MMIO(0xe45c), 0x00051050 },
1164         { _MMIO(0xe55c), 0x00053052 },
1165         { _MMIO(0xe65c), 0x00055054 },
1166 };
1167
1168 static const struct i915_oa_reg mux_config_l3_2[] = {
1169         { _MMIO(0x9888), 0x126c02e0 },
1170         { _MMIO(0x9888), 0x146c0001 },
1171         { _MMIO(0x9888), 0x0a623400 },
1172         { _MMIO(0x9888), 0x044e8000 },
1173         { _MMIO(0x9888), 0x064e8000 },
1174         { _MMIO(0x9888), 0x084e8000 },
1175         { _MMIO(0x9888), 0x0a4e8000 },
1176         { _MMIO(0x9888), 0x064f4000 },
1177         { _MMIO(0x9888), 0x026c3324 },
1178         { _MMIO(0x9888), 0x046c3422 },
1179         { _MMIO(0x9888), 0x106c0000 },
1180         { _MMIO(0x9888), 0x1a6c0000 },
1181         { _MMIO(0x9888), 0x021bc000 },
1182         { _MMIO(0x9888), 0x041bc000 },
1183         { _MMIO(0x9888), 0x141c8000 },
1184         { _MMIO(0x9888), 0x161c8000 },
1185         { _MMIO(0x9888), 0x181c8000 },
1186         { _MMIO(0x9888), 0x1a1c0800 },
1187         { _MMIO(0x9888), 0x065b4000 },
1188         { _MMIO(0x9888), 0x1a5c1000 },
1189         { _MMIO(0x9888), 0x06614000 },
1190         { _MMIO(0x9888), 0x0c620044 },
1191         { _MMIO(0x9888), 0x10620000 },
1192         { _MMIO(0x9888), 0x06620000 },
1193         { _MMIO(0x9888), 0x084c8000 },
1194         { _MMIO(0x9888), 0x0a4c002a },
1195         { _MMIO(0x9888), 0x020da000 },
1196         { _MMIO(0x9888), 0x040da000 },
1197         { _MMIO(0x9888), 0x060d2000 },
1198         { _MMIO(0x9888), 0x0c0f4000 },
1199         { _MMIO(0x9888), 0x0e0f0055 },
1200         { _MMIO(0x9888), 0x042c8000 },
1201         { _MMIO(0x9888), 0x062c8000 },
1202         { _MMIO(0x9888), 0x082c8000 },
1203         { _MMIO(0x9888), 0x0a2c8000 },
1204         { _MMIO(0x9888), 0x0c2cc000 },
1205         { _MMIO(0x9888), 0x1190f800 },
1206         { _MMIO(0x9888), 0x37900000 },
1207         { _MMIO(0x9888), 0x51900000 },
1208         { _MMIO(0x9888), 0x43900000 },
1209         { _MMIO(0x9888), 0x53900000 },
1210         { _MMIO(0x9888), 0x45900000 },
1211         { _MMIO(0x9888), 0x33900000 },
1212 };
1213
1214 static int
1215 get_l3_2_mux_config(struct drm_i915_private *dev_priv,
1216                     const struct i915_oa_reg **regs,
1217                     int *lens)
1218 {
1219         int n = 0;
1220
1221         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1222         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1223
1224         regs[n] = mux_config_l3_2;
1225         lens[n] = ARRAY_SIZE(mux_config_l3_2);
1226         n++;
1227
1228         return n;
1229 }
1230
1231 static const struct i915_oa_reg b_counter_config_l3_3[] = {
1232         { _MMIO(0x2740), 0x00000000 },
1233         { _MMIO(0x2744), 0x00800000 },
1234         { _MMIO(0x2710), 0x00000000 },
1235         { _MMIO(0x2714), 0xf0800000 },
1236         { _MMIO(0x2720), 0x00000000 },
1237         { _MMIO(0x2724), 0x00800000 },
1238         { _MMIO(0x2770), 0x00100070 },
1239         { _MMIO(0x2774), 0x0000fff1 },
1240         { _MMIO(0x2778), 0x00028002 },
1241         { _MMIO(0x277c), 0x000087ff },
1242         { _MMIO(0x2780), 0x00020002 },
1243         { _MMIO(0x2784), 0x00008fff },
1244         { _MMIO(0x2788), 0x00008002 },
1245         { _MMIO(0x278c), 0x0000a7ff },
1246 };
1247
1248 static const struct i915_oa_reg flex_eu_config_l3_3[] = {
1249         { _MMIO(0xe458), 0x00005004 },
1250         { _MMIO(0xe558), 0x00010003 },
1251         { _MMIO(0xe658), 0x00012011 },
1252         { _MMIO(0xe758), 0x00015014 },
1253         { _MMIO(0xe45c), 0x00051050 },
1254         { _MMIO(0xe55c), 0x00053052 },
1255         { _MMIO(0xe65c), 0x00055054 },
1256 };
1257
1258 static const struct i915_oa_reg mux_config_l3_3[] = {
1259         { _MMIO(0x9888), 0x126c4e80 },
1260         { _MMIO(0x9888), 0x146c0000 },
1261         { _MMIO(0x9888), 0x0a633400 },
1262         { _MMIO(0x9888), 0x044e8000 },
1263         { _MMIO(0x9888), 0x064e8000 },
1264         { _MMIO(0x9888), 0x084e8000 },
1265         { _MMIO(0x9888), 0x0a4e8000 },
1266         { _MMIO(0x9888), 0x0c4e8000 },
1267         { _MMIO(0x9888), 0x026c3321 },
1268         { _MMIO(0x9888), 0x046c342f },
1269         { _MMIO(0x9888), 0x106c0000 },
1270         { _MMIO(0x9888), 0x1a6c2000 },
1271         { _MMIO(0x9888), 0x021bc000 },
1272         { _MMIO(0x9888), 0x041bc000 },
1273         { _MMIO(0x9888), 0x061b4000 },
1274         { _MMIO(0x9888), 0x141c8000 },
1275         { _MMIO(0x9888), 0x161c8000 },
1276         { _MMIO(0x9888), 0x181c8000 },
1277         { _MMIO(0x9888), 0x1a1c1800 },
1278         { _MMIO(0x9888), 0x06604000 },
1279         { _MMIO(0x9888), 0x0c630044 },
1280         { _MMIO(0x9888), 0x10630000 },
1281         { _MMIO(0x9888), 0x06630000 },
1282         { _MMIO(0x9888), 0x084c8000 },
1283         { _MMIO(0x9888), 0x0a4c00aa },
1284         { _MMIO(0x9888), 0x020da000 },
1285         { _MMIO(0x9888), 0x040da000 },
1286         { _MMIO(0x9888), 0x060d2000 },
1287         { _MMIO(0x9888), 0x0c0f4000 },
1288         { _MMIO(0x9888), 0x0e0f0055 },
1289         { _MMIO(0x9888), 0x042c8000 },
1290         { _MMIO(0x9888), 0x062c8000 },
1291         { _MMIO(0x9888), 0x082c8000 },
1292         { _MMIO(0x9888), 0x0a2c8000 },
1293         { _MMIO(0x9888), 0x0c2c8000 },
1294         { _MMIO(0x9888), 0x1190f800 },
1295         { _MMIO(0x9888), 0x37900000 },
1296         { _MMIO(0x9888), 0x51900000 },
1297         { _MMIO(0x9888), 0x43900842 },
1298         { _MMIO(0x9888), 0x53900000 },
1299         { _MMIO(0x9888), 0x45900002 },
1300         { _MMIO(0x9888), 0x33900000 },
1301 };
1302
1303 static int
1304 get_l3_3_mux_config(struct drm_i915_private *dev_priv,
1305                     const struct i915_oa_reg **regs,
1306                     int *lens)
1307 {
1308         int n = 0;
1309
1310         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1311         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1312
1313         regs[n] = mux_config_l3_3;
1314         lens[n] = ARRAY_SIZE(mux_config_l3_3);
1315         n++;
1316
1317         return n;
1318 }
1319
1320 static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
1321         { _MMIO(0x2740), 0x00000000 },
1322         { _MMIO(0x2744), 0x00800000 },
1323         { _MMIO(0x2710), 0x00000000 },
1324         { _MMIO(0x2714), 0x30800000 },
1325         { _MMIO(0x2720), 0x00000000 },
1326         { _MMIO(0x2724), 0x00800000 },
1327         { _MMIO(0x2770), 0x00000002 },
1328         { _MMIO(0x2774), 0x0000efff },
1329         { _MMIO(0x2778), 0x00006000 },
1330         { _MMIO(0x277c), 0x0000f3ff },
1331 };
1332
1333 static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
1334         { _MMIO(0xe458), 0x00005004 },
1335         { _MMIO(0xe558), 0x00010003 },
1336         { _MMIO(0xe658), 0x00012011 },
1337         { _MMIO(0xe758), 0x00015014 },
1338         { _MMIO(0xe45c), 0x00051050 },
1339         { _MMIO(0xe55c), 0x00053052 },
1340         { _MMIO(0xe65c), 0x00055054 },
1341 };
1342
1343 static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
1344         { _MMIO(0x9888), 0x102f3800 },
1345         { _MMIO(0x9888), 0x144d0500 },
1346         { _MMIO(0x9888), 0x120d03c0 },
1347         { _MMIO(0x9888), 0x140d03cf },
1348         { _MMIO(0x9888), 0x0c0f0004 },
1349         { _MMIO(0x9888), 0x0c4e4000 },
1350         { _MMIO(0x9888), 0x042f0480 },
1351         { _MMIO(0x9888), 0x082f0000 },
1352         { _MMIO(0x9888), 0x022f0000 },
1353         { _MMIO(0x9888), 0x0a4c0090 },
1354         { _MMIO(0x9888), 0x064d0027 },
1355         { _MMIO(0x9888), 0x004d0000 },
1356         { _MMIO(0x9888), 0x000d0d40 },
1357         { _MMIO(0x9888), 0x020d803f },
1358         { _MMIO(0x9888), 0x040d8023 },
1359         { _MMIO(0x9888), 0x100d0000 },
1360         { _MMIO(0x9888), 0x060d2000 },
1361         { _MMIO(0x9888), 0x020f0010 },
1362         { _MMIO(0x9888), 0x000f0000 },
1363         { _MMIO(0x9888), 0x0e0f0050 },
1364         { _MMIO(0x9888), 0x0a2c8000 },
1365         { _MMIO(0x9888), 0x0c2c8000 },
1366         { _MMIO(0x9888), 0x1190fc00 },
1367         { _MMIO(0x9888), 0x37900000 },
1368         { _MMIO(0x9888), 0x51900000 },
1369         { _MMIO(0x9888), 0x41901400 },
1370         { _MMIO(0x9888), 0x43901485 },
1371         { _MMIO(0x9888), 0x53900000 },
1372         { _MMIO(0x9888), 0x45900001 },
1373         { _MMIO(0x9888), 0x33900000 },
1374 };
1375
1376 static int
1377 get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
1378                                             const struct i915_oa_reg **regs,
1379                                             int *lens)
1380 {
1381         int n = 0;
1382
1383         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1384         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1385
1386         regs[n] = mux_config_rasterizer_and_pixel_backend;
1387         lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
1388         n++;
1389
1390         return n;
1391 }
1392
1393 static const struct i915_oa_reg b_counter_config_sampler[] = {
1394         { _MMIO(0x2740), 0x00000000 },
1395         { _MMIO(0x2744), 0x00800000 },
1396         { _MMIO(0x2710), 0x00000000 },
1397         { _MMIO(0x2714), 0x70800000 },
1398         { _MMIO(0x2720), 0x00000000 },
1399         { _MMIO(0x2724), 0x00800000 },
1400         { _MMIO(0x2770), 0x0000c000 },
1401         { _MMIO(0x2774), 0x0000e7ff },
1402         { _MMIO(0x2778), 0x00003000 },
1403         { _MMIO(0x277c), 0x0000f9ff },
1404         { _MMIO(0x2780), 0x00000c00 },
1405         { _MMIO(0x2784), 0x0000fe7f },
1406 };
1407
1408 static const struct i915_oa_reg flex_eu_config_sampler[] = {
1409         { _MMIO(0xe458), 0x00005004 },
1410         { _MMIO(0xe558), 0x00010003 },
1411         { _MMIO(0xe658), 0x00012011 },
1412         { _MMIO(0xe758), 0x00015014 },
1413         { _MMIO(0xe45c), 0x00051050 },
1414         { _MMIO(0xe55c), 0x00053052 },
1415         { _MMIO(0xe65c), 0x00055054 },
1416 };
1417
1418 static const struct i915_oa_reg mux_config_sampler[] = {
1419         { _MMIO(0x9888), 0x14152c00 },
1420         { _MMIO(0x9888), 0x16150005 },
1421         { _MMIO(0x9888), 0x121600a0 },
1422         { _MMIO(0x9888), 0x14352c00 },
1423         { _MMIO(0x9888), 0x16350005 },
1424         { _MMIO(0x9888), 0x123600a0 },
1425         { _MMIO(0x9888), 0x14552c00 },
1426         { _MMIO(0x9888), 0x16550005 },
1427         { _MMIO(0x9888), 0x125600a0 },
1428         { _MMIO(0x9888), 0x062f6000 },
1429         { _MMIO(0x9888), 0x022f2000 },
1430         { _MMIO(0x9888), 0x0c4c0050 },
1431         { _MMIO(0x9888), 0x0a4c0010 },
1432         { _MMIO(0x9888), 0x0c0d8000 },
1433         { _MMIO(0x9888), 0x0e0da000 },
1434         { _MMIO(0x9888), 0x000d8000 },
1435         { _MMIO(0x9888), 0x020da000 },
1436         { _MMIO(0x9888), 0x040da000 },
1437         { _MMIO(0x9888), 0x060d2000 },
1438         { _MMIO(0x9888), 0x100f0350 },
1439         { _MMIO(0x9888), 0x0c0fb000 },
1440         { _MMIO(0x9888), 0x0e0f00da },
1441         { _MMIO(0x9888), 0x182c0028 },
1442         { _MMIO(0x9888), 0x0a2c8000 },
1443         { _MMIO(0x9888), 0x022dc000 },
1444         { _MMIO(0x9888), 0x042d4000 },
1445         { _MMIO(0x9888), 0x0c138000 },
1446         { _MMIO(0x9888), 0x0e132000 },
1447         { _MMIO(0x9888), 0x0413c000 },
1448         { _MMIO(0x9888), 0x1c140018 },
1449         { _MMIO(0x9888), 0x0c157000 },
1450         { _MMIO(0x9888), 0x0e150078 },
1451         { _MMIO(0x9888), 0x10150000 },
1452         { _MMIO(0x9888), 0x04162180 },
1453         { _MMIO(0x9888), 0x02160000 },
1454         { _MMIO(0x9888), 0x04174000 },
1455         { _MMIO(0x9888), 0x0233a000 },
1456         { _MMIO(0x9888), 0x04333000 },
1457         { _MMIO(0x9888), 0x14348000 },
1458         { _MMIO(0x9888), 0x16348000 },
1459         { _MMIO(0x9888), 0x02357870 },
1460         { _MMIO(0x9888), 0x10350000 },
1461         { _MMIO(0x9888), 0x04360043 },
1462         { _MMIO(0x9888), 0x02360000 },
1463         { _MMIO(0x9888), 0x04371000 },
1464         { _MMIO(0x9888), 0x0e538000 },
1465         { _MMIO(0x9888), 0x00538000 },
1466         { _MMIO(0x9888), 0x06533000 },
1467         { _MMIO(0x9888), 0x1c540020 },
1468         { _MMIO(0x9888), 0x12548000 },
1469         { _MMIO(0x9888), 0x0e557000 },
1470         { _MMIO(0x9888), 0x00557800 },
1471         { _MMIO(0x9888), 0x10550000 },
1472         { _MMIO(0x9888), 0x06560043 },
1473         { _MMIO(0x9888), 0x02560000 },
1474         { _MMIO(0x9888), 0x06571000 },
1475         { _MMIO(0x9888), 0x1190ff80 },
1476         { _MMIO(0x9888), 0x57900000 },
1477         { _MMIO(0x9888), 0x49900000 },
1478         { _MMIO(0x9888), 0x37900000 },
1479         { _MMIO(0x9888), 0x33900000 },
1480         { _MMIO(0x9888), 0x4b900060 },
1481         { _MMIO(0x9888), 0x59900000 },
1482         { _MMIO(0x9888), 0x51900000 },
1483         { _MMIO(0x9888), 0x41900c00 },
1484         { _MMIO(0x9888), 0x43900842 },
1485         { _MMIO(0x9888), 0x53900000 },
1486         { _MMIO(0x9888), 0x45900060 },
1487 };
1488
1489 static int
1490 get_sampler_mux_config(struct drm_i915_private *dev_priv,
1491                        const struct i915_oa_reg **regs,
1492                        int *lens)
1493 {
1494         int n = 0;
1495
1496         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1497         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1498
1499         regs[n] = mux_config_sampler;
1500         lens[n] = ARRAY_SIZE(mux_config_sampler);
1501         n++;
1502
1503         return n;
1504 }
1505
1506 static const struct i915_oa_reg b_counter_config_tdl_1[] = {
1507         { _MMIO(0x2740), 0x00000000 },
1508         { _MMIO(0x2744), 0x00800000 },
1509         { _MMIO(0x2710), 0x00000000 },
1510         { _MMIO(0x2714), 0xf0800000 },
1511         { _MMIO(0x2720), 0x00000000 },
1512         { _MMIO(0x2724), 0x30800000 },
1513         { _MMIO(0x2770), 0x00000002 },
1514         { _MMIO(0x2774), 0x00007fff },
1515         { _MMIO(0x2778), 0x00000000 },
1516         { _MMIO(0x277c), 0x00009fff },
1517         { _MMIO(0x2780), 0x00000002 },
1518         { _MMIO(0x2784), 0x0000efff },
1519         { _MMIO(0x2788), 0x00000000 },
1520         { _MMIO(0x278c), 0x0000f3ff },
1521         { _MMIO(0x2790), 0x00000002 },
1522         { _MMIO(0x2794), 0x0000fdff },
1523         { _MMIO(0x2798), 0x00000000 },
1524         { _MMIO(0x279c), 0x0000fe7f },
1525 };
1526
1527 static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
1528         { _MMIO(0xe458), 0x00005004 },
1529         { _MMIO(0xe558), 0x00010003 },
1530         { _MMIO(0xe658), 0x00012011 },
1531         { _MMIO(0xe758), 0x00015014 },
1532         { _MMIO(0xe45c), 0x00051050 },
1533         { _MMIO(0xe55c), 0x00053052 },
1534         { _MMIO(0xe65c), 0x00055054 },
1535 };
1536
1537 static const struct i915_oa_reg mux_config_tdl_1[] = {
1538         { _MMIO(0x9888), 0x12120000 },
1539         { _MMIO(0x9888), 0x12320000 },
1540         { _MMIO(0x9888), 0x12520000 },
1541         { _MMIO(0x9888), 0x002f8000 },
1542         { _MMIO(0x9888), 0x022f3000 },
1543         { _MMIO(0x9888), 0x0a4c0015 },
1544         { _MMIO(0x9888), 0x0c0d8000 },
1545         { _MMIO(0x9888), 0x0e0da000 },
1546         { _MMIO(0x9888), 0x000d8000 },
1547         { _MMIO(0x9888), 0x020da000 },
1548         { _MMIO(0x9888), 0x040da000 },
1549         { _MMIO(0x9888), 0x060d2000 },
1550         { _MMIO(0x9888), 0x100f03a0 },
1551         { _MMIO(0x9888), 0x0c0ff000 },
1552         { _MMIO(0x9888), 0x0e0f0095 },
1553         { _MMIO(0x9888), 0x062c8000 },
1554         { _MMIO(0x9888), 0x082c8000 },
1555         { _MMIO(0x9888), 0x0a2c8000 },
1556         { _MMIO(0x9888), 0x0c2d8000 },
1557         { _MMIO(0x9888), 0x0e2d4000 },
1558         { _MMIO(0x9888), 0x062d4000 },
1559         { _MMIO(0x9888), 0x02108000 },
1560         { _MMIO(0x9888), 0x0410c000 },
1561         { _MMIO(0x9888), 0x02118000 },
1562         { _MMIO(0x9888), 0x0411c000 },
1563         { _MMIO(0x9888), 0x02121880 },
1564         { _MMIO(0x9888), 0x041219b5 },
1565         { _MMIO(0x9888), 0x00120000 },
1566         { _MMIO(0x9888), 0x02134000 },
1567         { _MMIO(0x9888), 0x04135000 },
1568         { _MMIO(0x9888), 0x0c308000 },
1569         { _MMIO(0x9888), 0x0e304000 },
1570         { _MMIO(0x9888), 0x06304000 },
1571         { _MMIO(0x9888), 0x0c318000 },
1572         { _MMIO(0x9888), 0x0e314000 },
1573         { _MMIO(0x9888), 0x06314000 },
1574         { _MMIO(0x9888), 0x0c321a80 },
1575         { _MMIO(0x9888), 0x0e320033 },
1576         { _MMIO(0x9888), 0x06320031 },
1577         { _MMIO(0x9888), 0x00320000 },
1578         { _MMIO(0x9888), 0x0c334000 },
1579         { _MMIO(0x9888), 0x0e331000 },
1580         { _MMIO(0x9888), 0x06331000 },
1581         { _MMIO(0x9888), 0x0e508000 },
1582         { _MMIO(0x9888), 0x00508000 },
1583         { _MMIO(0x9888), 0x02504000 },
1584         { _MMIO(0x9888), 0x0e518000 },
1585         { _MMIO(0x9888), 0x00518000 },
1586         { _MMIO(0x9888), 0x02514000 },
1587         { _MMIO(0x9888), 0x0e521880 },
1588         { _MMIO(0x9888), 0x00521a80 },
1589         { _MMIO(0x9888), 0x02520033 },
1590         { _MMIO(0x9888), 0x0e534000 },
1591         { _MMIO(0x9888), 0x00534000 },
1592         { _MMIO(0x9888), 0x02531000 },
1593         { _MMIO(0x9888), 0x1190ff80 },
1594         { _MMIO(0x9888), 0x57900000 },
1595         { _MMIO(0x9888), 0x49900800 },
1596         { _MMIO(0x9888), 0x37900000 },
1597         { _MMIO(0x9888), 0x33900000 },
1598         { _MMIO(0x9888), 0x4b900062 },
1599         { _MMIO(0x9888), 0x59900000 },
1600         { _MMIO(0x9888), 0x51900000 },
1601         { _MMIO(0x9888), 0x41900c00 },
1602         { _MMIO(0x9888), 0x43900003 },
1603         { _MMIO(0x9888), 0x53900000 },
1604         { _MMIO(0x9888), 0x45900040 },
1605 };
1606
1607 static int
1608 get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
1609                      const struct i915_oa_reg **regs,
1610                      int *lens)
1611 {
1612         int n = 0;
1613
1614         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1615         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1616
1617         regs[n] = mux_config_tdl_1;
1618         lens[n] = ARRAY_SIZE(mux_config_tdl_1);
1619         n++;
1620
1621         return n;
1622 }
1623
1624 static const struct i915_oa_reg b_counter_config_tdl_2[] = {
1625         { _MMIO(0x2740), 0x00000000 },
1626         { _MMIO(0x2744), 0x00800000 },
1627         { _MMIO(0x2710), 0x00000000 },
1628         { _MMIO(0x2714), 0x00800000 },
1629         { _MMIO(0x2720), 0x00000000 },
1630         { _MMIO(0x2724), 0x00800000 },
1631 };
1632
1633 static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
1634         { _MMIO(0xe458), 0x00005004 },
1635         { _MMIO(0xe558), 0x00010003 },
1636         { _MMIO(0xe658), 0x00012011 },
1637         { _MMIO(0xe758), 0x00015014 },
1638         { _MMIO(0xe45c), 0x00051050 },
1639         { _MMIO(0xe55c), 0x00053052 },
1640         { _MMIO(0xe65c), 0x00055054 },
1641 };
1642
1643 static const struct i915_oa_reg mux_config_tdl_2[] = {
1644         { _MMIO(0x9888), 0x12124d60 },
1645         { _MMIO(0x9888), 0x12322e60 },
1646         { _MMIO(0x9888), 0x12524d60 },
1647         { _MMIO(0x9888), 0x022f3000 },
1648         { _MMIO(0x9888), 0x0a4c0014 },
1649         { _MMIO(0x9888), 0x000d8000 },
1650         { _MMIO(0x9888), 0x020da000 },
1651         { _MMIO(0x9888), 0x040da000 },
1652         { _MMIO(0x9888), 0x060d2000 },
1653         { _MMIO(0x9888), 0x0c0fe000 },
1654         { _MMIO(0x9888), 0x0e0f0097 },
1655         { _MMIO(0x9888), 0x082c8000 },
1656         { _MMIO(0x9888), 0x0a2c8000 },
1657         { _MMIO(0x9888), 0x002d8000 },
1658         { _MMIO(0x9888), 0x062d4000 },
1659         { _MMIO(0x9888), 0x0410c000 },
1660         { _MMIO(0x9888), 0x0411c000 },
1661         { _MMIO(0x9888), 0x04121fb7 },
1662         { _MMIO(0x9888), 0x00120000 },
1663         { _MMIO(0x9888), 0x04135000 },
1664         { _MMIO(0x9888), 0x00308000 },
1665         { _MMIO(0x9888), 0x06304000 },
1666         { _MMIO(0x9888), 0x00318000 },
1667         { _MMIO(0x9888), 0x06314000 },
1668         { _MMIO(0x9888), 0x00321b80 },
1669         { _MMIO(0x9888), 0x0632003f },
1670         { _MMIO(0x9888), 0x00334000 },
1671         { _MMIO(0x9888), 0x06331000 },
1672         { _MMIO(0x9888), 0x0250c000 },
1673         { _MMIO(0x9888), 0x0251c000 },
1674         { _MMIO(0x9888), 0x02521fb7 },
1675         { _MMIO(0x9888), 0x00520000 },
1676         { _MMIO(0x9888), 0x02535000 },
1677         { _MMIO(0x9888), 0x1190fc00 },
1678         { _MMIO(0x9888), 0x37900000 },
1679         { _MMIO(0x9888), 0x51900000 },
1680         { _MMIO(0x9888), 0x41900800 },
1681         { _MMIO(0x9888), 0x43900063 },
1682         { _MMIO(0x9888), 0x53900000 },
1683         { _MMIO(0x9888), 0x45900040 },
1684         { _MMIO(0x9888), 0x33900000 },
1685 };
1686
1687 static int
1688 get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
1689                      const struct i915_oa_reg **regs,
1690                      int *lens)
1691 {
1692         int n = 0;
1693
1694         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1695         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1696
1697         regs[n] = mux_config_tdl_2;
1698         lens[n] = ARRAY_SIZE(mux_config_tdl_2);
1699         n++;
1700
1701         return n;
1702 }
1703
1704 static const struct i915_oa_reg b_counter_config_compute_extra[] = {
1705 };
1706
1707 static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
1708 };
1709
1710 static const struct i915_oa_reg mux_config_compute_extra[] = {
1711         { _MMIO(0x9888), 0x121203e0 },
1712         { _MMIO(0x9888), 0x123203e0 },
1713         { _MMIO(0x9888), 0x125203e0 },
1714         { _MMIO(0x9888), 0x129203e0 },
1715         { _MMIO(0x9888), 0x12b203e0 },
1716         { _MMIO(0x9888), 0x12d203e0 },
1717         { _MMIO(0x9888), 0x131203e0 },
1718         { _MMIO(0x9888), 0x133203e0 },
1719         { _MMIO(0x9888), 0x135203e0 },
1720         { _MMIO(0x9888), 0x1a4ef000 },
1721         { _MMIO(0x9888), 0x1c4e0003 },
1722         { _MMIO(0x9888), 0x024ec000 },
1723         { _MMIO(0x9888), 0x044ec000 },
1724         { _MMIO(0x9888), 0x064ec000 },
1725         { _MMIO(0x9888), 0x022f4000 },
1726         { _MMIO(0x9888), 0x0c4c02a0 },
1727         { _MMIO(0x9888), 0x084ca000 },
1728         { _MMIO(0x9888), 0x0a4c0042 },
1729         { _MMIO(0x9888), 0x0c0d8000 },
1730         { _MMIO(0x9888), 0x0e0da000 },
1731         { _MMIO(0x9888), 0x000d8000 },
1732         { _MMIO(0x9888), 0x020da000 },
1733         { _MMIO(0x9888), 0x040da000 },
1734         { _MMIO(0x9888), 0x060d2000 },
1735         { _MMIO(0x9888), 0x100f0150 },
1736         { _MMIO(0x9888), 0x0c0f5000 },
1737         { _MMIO(0x9888), 0x0e0f006d },
1738         { _MMIO(0x9888), 0x182c00a8 },
1739         { _MMIO(0x9888), 0x022c8000 },
1740         { _MMIO(0x9888), 0x042c8000 },
1741         { _MMIO(0x9888), 0x062c8000 },
1742         { _MMIO(0x9888), 0x0c2c8000 },
1743         { _MMIO(0x9888), 0x042d8000 },
1744         { _MMIO(0x9888), 0x06104000 },
1745         { _MMIO(0x9888), 0x06114000 },
1746         { _MMIO(0x9888), 0x06120033 },
1747         { _MMIO(0x9888), 0x00120000 },
1748         { _MMIO(0x9888), 0x06131000 },
1749         { _MMIO(0x9888), 0x04308000 },
1750         { _MMIO(0x9888), 0x04318000 },
1751         { _MMIO(0x9888), 0x04321980 },
1752         { _MMIO(0x9888), 0x00320000 },
1753         { _MMIO(0x9888), 0x04334000 },
1754         { _MMIO(0x9888), 0x04504000 },
1755         { _MMIO(0x9888), 0x04514000 },
1756         { _MMIO(0x9888), 0x04520033 },
1757         { _MMIO(0x9888), 0x00520000 },
1758         { _MMIO(0x9888), 0x04531000 },
1759         { _MMIO(0x9888), 0x1acef000 },
1760         { _MMIO(0x9888), 0x1cce0003 },
1761         { _MMIO(0x9888), 0x00af8000 },
1762         { _MMIO(0x9888), 0x0ccc02a0 },
1763         { _MMIO(0x9888), 0x0acc0001 },
1764         { _MMIO(0x9888), 0x0c8d8000 },
1765         { _MMIO(0x9888), 0x0e8da000 },
1766         { _MMIO(0x9888), 0x008d8000 },
1767         { _MMIO(0x9888), 0x028da000 },
1768         { _MMIO(0x9888), 0x108f0150 },
1769         { _MMIO(0x9888), 0x0c8fb000 },
1770         { _MMIO(0x9888), 0x0e8f0001 },
1771         { _MMIO(0x9888), 0x18ac00a8 },
1772         { _MMIO(0x9888), 0x06ac8000 },
1773         { _MMIO(0x9888), 0x02ad4000 },
1774         { _MMIO(0x9888), 0x02908000 },
1775         { _MMIO(0x9888), 0x02918000 },
1776         { _MMIO(0x9888), 0x02921980 },
1777         { _MMIO(0x9888), 0x00920000 },
1778         { _MMIO(0x9888), 0x02934000 },
1779         { _MMIO(0x9888), 0x02b04000 },
1780         { _MMIO(0x9888), 0x02b14000 },
1781         { _MMIO(0x9888), 0x02b20033 },
1782         { _MMIO(0x9888), 0x00b20000 },
1783         { _MMIO(0x9888), 0x02b31000 },
1784         { _MMIO(0x9888), 0x00d08000 },
1785         { _MMIO(0x9888), 0x00d18000 },
1786         { _MMIO(0x9888), 0x00d21980 },
1787         { _MMIO(0x9888), 0x00d34000 },
1788         { _MMIO(0x9888), 0x072f8000 },
1789         { _MMIO(0x9888), 0x0d4c0100 },
1790         { _MMIO(0x9888), 0x0d0d8000 },
1791         { _MMIO(0x9888), 0x0f0da000 },
1792         { _MMIO(0x9888), 0x110f01b0 },
1793         { _MMIO(0x9888), 0x192c0080 },
1794         { _MMIO(0x9888), 0x0f2d4000 },
1795         { _MMIO(0x9888), 0x0f108000 },
1796         { _MMIO(0x9888), 0x0f118000 },
1797         { _MMIO(0x9888), 0x0f121980 },
1798         { _MMIO(0x9888), 0x01120000 },
1799         { _MMIO(0x9888), 0x0f134000 },
1800         { _MMIO(0x9888), 0x0f304000 },
1801         { _MMIO(0x9888), 0x0f314000 },
1802         { _MMIO(0x9888), 0x0f320033 },
1803         { _MMIO(0x9888), 0x01320000 },
1804         { _MMIO(0x9888), 0x0f331000 },
1805         { _MMIO(0x9888), 0x0d508000 },
1806         { _MMIO(0x9888), 0x0d518000 },
1807         { _MMIO(0x9888), 0x0d521980 },
1808         { _MMIO(0x9888), 0x01520000 },
1809         { _MMIO(0x9888), 0x0d534000 },
1810         { _MMIO(0x9888), 0x1190ff80 },
1811         { _MMIO(0x9888), 0x57900000 },
1812         { _MMIO(0x9888), 0x49900c00 },
1813         { _MMIO(0x9888), 0x37900000 },
1814         { _MMIO(0x9888), 0x33900000 },
1815         { _MMIO(0x9888), 0x4b900002 },
1816         { _MMIO(0x9888), 0x59900000 },
1817         { _MMIO(0x9888), 0x51901100 },
1818         { _MMIO(0x9888), 0x41901000 },
1819         { _MMIO(0x9888), 0x43901423 },
1820         { _MMIO(0x9888), 0x53903331 },
1821         { _MMIO(0x9888), 0x45900044 },
1822 };
1823
1824 static int
1825 get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
1826                              const struct i915_oa_reg **regs,
1827                              int *lens)
1828 {
1829         int n = 0;
1830
1831         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1832         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1833
1834         regs[n] = mux_config_compute_extra;
1835         lens[n] = ARRAY_SIZE(mux_config_compute_extra);
1836         n++;
1837
1838         return n;
1839 }
1840
1841 static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
1842         { _MMIO(0x2740), 0x00000000 },
1843         { _MMIO(0x2710), 0x00000000 },
1844         { _MMIO(0x2714), 0xf0800000 },
1845         { _MMIO(0x2720), 0x00000000 },
1846         { _MMIO(0x2724), 0x30800000 },
1847         { _MMIO(0x2770), 0x00100030 },
1848         { _MMIO(0x2774), 0x0000fff9 },
1849         { _MMIO(0x2778), 0x00000002 },
1850         { _MMIO(0x277c), 0x0000fffc },
1851         { _MMIO(0x2780), 0x00000002 },
1852         { _MMIO(0x2784), 0x0000fff3 },
1853         { _MMIO(0x2788), 0x00100180 },
1854         { _MMIO(0x278c), 0x0000ffcf },
1855         { _MMIO(0x2790), 0x00000002 },
1856         { _MMIO(0x2794), 0x0000ffcf },
1857         { _MMIO(0x2798), 0x00000002 },
1858         { _MMIO(0x279c), 0x0000ff3f },
1859 };
1860
1861 static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
1862         { _MMIO(0xe458), 0x00005004 },
1863         { _MMIO(0xe558), 0x00008003 },
1864 };
1865
1866 static const struct i915_oa_reg mux_config_vme_pipe[] = {
1867         { _MMIO(0x9888), 0x141a5800 },
1868         { _MMIO(0x9888), 0x161a00c0 },
1869         { _MMIO(0x9888), 0x12180240 },
1870         { _MMIO(0x9888), 0x14180002 },
1871         { _MMIO(0x9888), 0x149a5800 },
1872         { _MMIO(0x9888), 0x169a00c0 },
1873         { _MMIO(0x9888), 0x12980240 },
1874         { _MMIO(0x9888), 0x14980002 },
1875         { _MMIO(0x9888), 0x1a4e3fc0 },
1876         { _MMIO(0x9888), 0x002f1000 },
1877         { _MMIO(0x9888), 0x022f8000 },
1878         { _MMIO(0x9888), 0x042f3000 },
1879         { _MMIO(0x9888), 0x004c4000 },
1880         { _MMIO(0x9888), 0x0a4c9500 },
1881         { _MMIO(0x9888), 0x0c4c002a },
1882         { _MMIO(0x9888), 0x000d2000 },
1883         { _MMIO(0x9888), 0x060d8000 },
1884         { _MMIO(0x9888), 0x080da000 },
1885         { _MMIO(0x9888), 0x0a0da000 },
1886         { _MMIO(0x9888), 0x0c0da000 },
1887         { _MMIO(0x9888), 0x0c0f0400 },
1888         { _MMIO(0x9888), 0x0e0f5500 },
1889         { _MMIO(0x9888), 0x100f0015 },
1890         { _MMIO(0x9888), 0x002c8000 },
1891         { _MMIO(0x9888), 0x0e2c8000 },
1892         { _MMIO(0x9888), 0x162caa00 },
1893         { _MMIO(0x9888), 0x182c000a },
1894         { _MMIO(0x9888), 0x04193000 },
1895         { _MMIO(0x9888), 0x081a28c1 },
1896         { _MMIO(0x9888), 0x001a0000 },
1897         { _MMIO(0x9888), 0x00133000 },
1898         { _MMIO(0x9888), 0x0613c000 },
1899         { _MMIO(0x9888), 0x0813f000 },
1900         { _MMIO(0x9888), 0x00172000 },
1901         { _MMIO(0x9888), 0x06178000 },
1902         { _MMIO(0x9888), 0x0817a000 },
1903         { _MMIO(0x9888), 0x00180037 },
1904         { _MMIO(0x9888), 0x06180940 },
1905         { _MMIO(0x9888), 0x08180000 },
1906         { _MMIO(0x9888), 0x02180000 },
1907         { _MMIO(0x9888), 0x04183000 },
1908         { _MMIO(0x9888), 0x04afc000 },
1909         { _MMIO(0x9888), 0x06af3000 },
1910         { _MMIO(0x9888), 0x0acc4000 },
1911         { _MMIO(0x9888), 0x0ccc0015 },
1912         { _MMIO(0x9888), 0x0a8da000 },
1913         { _MMIO(0x9888), 0x0c8da000 },
1914         { _MMIO(0x9888), 0x0e8f4000 },
1915         { _MMIO(0x9888), 0x108f0015 },
1916         { _MMIO(0x9888), 0x16aca000 },
1917         { _MMIO(0x9888), 0x18ac000a },
1918         { _MMIO(0x9888), 0x06993000 },
1919         { _MMIO(0x9888), 0x0c9a28c1 },
1920         { _MMIO(0x9888), 0x009a0000 },
1921         { _MMIO(0x9888), 0x0a93f000 },
1922         { _MMIO(0x9888), 0x0c93f000 },
1923         { _MMIO(0x9888), 0x0a97a000 },
1924         { _MMIO(0x9888), 0x0c97a000 },
1925         { _MMIO(0x9888), 0x0a980977 },
1926         { _MMIO(0x9888), 0x08980000 },
1927         { _MMIO(0x9888), 0x04980000 },
1928         { _MMIO(0x9888), 0x06983000 },
1929         { _MMIO(0x9888), 0x119000ff },
1930         { _MMIO(0x9888), 0x51900010 },
1931         { _MMIO(0x9888), 0x41900060 },
1932         { _MMIO(0x9888), 0x55900111 },
1933         { _MMIO(0x9888), 0x45900c00 },
1934         { _MMIO(0x9888), 0x47900821 },
1935         { _MMIO(0x9888), 0x57900000 },
1936         { _MMIO(0x9888), 0x49900002 },
1937         { _MMIO(0x9888), 0x37900000 },
1938         { _MMIO(0x9888), 0x33900000 },
1939 };
1940
1941 static int
1942 get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
1943                         const struct i915_oa_reg **regs,
1944                         int *lens)
1945 {
1946         int n = 0;
1947
1948         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1949         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1950
1951         regs[n] = mux_config_vme_pipe;
1952         lens[n] = ARRAY_SIZE(mux_config_vme_pipe);
1953         n++;
1954
1955         return n;
1956 }
1957
1958 static const struct i915_oa_reg b_counter_config_test_oa[] = {
1959         { _MMIO(0x2740), 0x00000000 },
1960         { _MMIO(0x2744), 0x00800000 },
1961         { _MMIO(0x2714), 0xf0800000 },
1962         { _MMIO(0x2710), 0x00000000 },
1963         { _MMIO(0x2724), 0xf0800000 },
1964         { _MMIO(0x2720), 0x00000000 },
1965         { _MMIO(0x2770), 0x00000004 },
1966         { _MMIO(0x2774), 0x00000000 },
1967         { _MMIO(0x2778), 0x00000003 },
1968         { _MMIO(0x277c), 0x00000000 },
1969         { _MMIO(0x2780), 0x00000007 },
1970         { _MMIO(0x2784), 0x00000000 },
1971         { _MMIO(0x2788), 0x00100002 },
1972         { _MMIO(0x278c), 0x0000fff7 },
1973         { _MMIO(0x2790), 0x00100002 },
1974         { _MMIO(0x2794), 0x0000ffcf },
1975         { _MMIO(0x2798), 0x00100082 },
1976         { _MMIO(0x279c), 0x0000ffef },
1977         { _MMIO(0x27a0), 0x001000c2 },
1978         { _MMIO(0x27a4), 0x0000ffe7 },
1979         { _MMIO(0x27a8), 0x00100001 },
1980         { _MMIO(0x27ac), 0x0000ffe7 },
1981 };
1982
1983 static const struct i915_oa_reg flex_eu_config_test_oa[] = {
1984 };
1985
1986 static const struct i915_oa_reg mux_config_test_oa[] = {
1987         { _MMIO(0x9888), 0x11810000 },
1988         { _MMIO(0x9888), 0x07810013 },
1989         { _MMIO(0x9888), 0x1f810000 },
1990         { _MMIO(0x9888), 0x1d810000 },
1991         { _MMIO(0x9888), 0x1b930040 },
1992         { _MMIO(0x9888), 0x07e54000 },
1993         { _MMIO(0x9888), 0x1f908000 },
1994         { _MMIO(0x9888), 0x11900000 },
1995         { _MMIO(0x9888), 0x37900000 },
1996         { _MMIO(0x9888), 0x53900000 },
1997         { _MMIO(0x9888), 0x45900000 },
1998         { _MMIO(0x9888), 0x33900000 },
1999 };
2000
2001 static int
2002 get_test_oa_mux_config(struct drm_i915_private *dev_priv,
2003                        const struct i915_oa_reg **regs,
2004                        int *lens)
2005 {
2006         int n = 0;
2007
2008         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2009         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2010
2011         regs[n] = mux_config_test_oa;
2012         lens[n] = ARRAY_SIZE(mux_config_test_oa);
2013         n++;
2014
2015         return n;
2016 }
2017
2018 int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv)
2019 {
2020         dev_priv->perf.oa.n_mux_configs = 0;
2021         dev_priv->perf.oa.b_counter_regs = NULL;
2022         dev_priv->perf.oa.b_counter_regs_len = 0;
2023         dev_priv->perf.oa.flex_regs = NULL;
2024         dev_priv->perf.oa.flex_regs_len = 0;
2025
2026         switch (dev_priv->perf.oa.metrics_set) {
2027         case METRIC_SET_ID_RENDER_BASIC:
2028                 dev_priv->perf.oa.n_mux_configs =
2029                         get_render_basic_mux_config(dev_priv,
2030                                                     dev_priv->perf.oa.mux_regs,
2031                                                     dev_priv->perf.oa.mux_regs_lens);
2032                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2033                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
2034
2035                         /* EINVAL because *_register_sysfs already checked this
2036                          * and so it wouldn't have been advertised to userspace and
2037                          * so shouldn't have been requested
2038                          */
2039                         return -EINVAL;
2040                 }
2041
2042                 dev_priv->perf.oa.b_counter_regs =
2043                         b_counter_config_render_basic;
2044                 dev_priv->perf.oa.b_counter_regs_len =
2045                         ARRAY_SIZE(b_counter_config_render_basic);
2046
2047                 dev_priv->perf.oa.flex_regs =
2048                         flex_eu_config_render_basic;
2049                 dev_priv->perf.oa.flex_regs_len =
2050                         ARRAY_SIZE(flex_eu_config_render_basic);
2051
2052                 return 0;
2053         case METRIC_SET_ID_COMPUTE_BASIC:
2054                 dev_priv->perf.oa.n_mux_configs =
2055                         get_compute_basic_mux_config(dev_priv,
2056                                                      dev_priv->perf.oa.mux_regs,
2057                                                      dev_priv->perf.oa.mux_regs_lens);
2058                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2059                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
2060
2061                         /* EINVAL because *_register_sysfs already checked this
2062                          * and so it wouldn't have been advertised to userspace and
2063                          * so shouldn't have been requested
2064                          */
2065                         return -EINVAL;
2066                 }
2067
2068                 dev_priv->perf.oa.b_counter_regs =
2069                         b_counter_config_compute_basic;
2070                 dev_priv->perf.oa.b_counter_regs_len =
2071                         ARRAY_SIZE(b_counter_config_compute_basic);
2072
2073                 dev_priv->perf.oa.flex_regs =
2074                         flex_eu_config_compute_basic;
2075                 dev_priv->perf.oa.flex_regs_len =
2076                         ARRAY_SIZE(flex_eu_config_compute_basic);
2077
2078                 return 0;
2079         case METRIC_SET_ID_RENDER_PIPE_PROFILE:
2080                 dev_priv->perf.oa.n_mux_configs =
2081                         get_render_pipe_profile_mux_config(dev_priv,
2082                                                            dev_priv->perf.oa.mux_regs,
2083                                                            dev_priv->perf.oa.mux_regs_lens);
2084                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2085                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
2086
2087                         /* EINVAL because *_register_sysfs already checked this
2088                          * and so it wouldn't have been advertised to userspace and
2089                          * so shouldn't have been requested
2090                          */
2091                         return -EINVAL;
2092                 }
2093
2094                 dev_priv->perf.oa.b_counter_regs =
2095                         b_counter_config_render_pipe_profile;
2096                 dev_priv->perf.oa.b_counter_regs_len =
2097                         ARRAY_SIZE(b_counter_config_render_pipe_profile);
2098
2099                 dev_priv->perf.oa.flex_regs =
2100                         flex_eu_config_render_pipe_profile;
2101                 dev_priv->perf.oa.flex_regs_len =
2102                         ARRAY_SIZE(flex_eu_config_render_pipe_profile);
2103
2104                 return 0;
2105         case METRIC_SET_ID_MEMORY_READS:
2106                 dev_priv->perf.oa.n_mux_configs =
2107                         get_memory_reads_mux_config(dev_priv,
2108                                                     dev_priv->perf.oa.mux_regs,
2109                                                     dev_priv->perf.oa.mux_regs_lens);
2110                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2111                         DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
2112
2113                         /* EINVAL because *_register_sysfs already checked this
2114                          * and so it wouldn't have been advertised to userspace and
2115                          * so shouldn't have been requested
2116                          */
2117                         return -EINVAL;
2118                 }
2119
2120                 dev_priv->perf.oa.b_counter_regs =
2121                         b_counter_config_memory_reads;
2122                 dev_priv->perf.oa.b_counter_regs_len =
2123                         ARRAY_SIZE(b_counter_config_memory_reads);
2124
2125                 dev_priv->perf.oa.flex_regs =
2126                         flex_eu_config_memory_reads;
2127                 dev_priv->perf.oa.flex_regs_len =
2128                         ARRAY_SIZE(flex_eu_config_memory_reads);
2129
2130                 return 0;
2131         case METRIC_SET_ID_MEMORY_WRITES:
2132                 dev_priv->perf.oa.n_mux_configs =
2133                         get_memory_writes_mux_config(dev_priv,
2134                                                      dev_priv->perf.oa.mux_regs,
2135                                                      dev_priv->perf.oa.mux_regs_lens);
2136                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2137                         DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
2138
2139                         /* EINVAL because *_register_sysfs already checked this
2140                          * and so it wouldn't have been advertised to userspace and
2141                          * so shouldn't have been requested
2142                          */
2143                         return -EINVAL;
2144                 }
2145
2146                 dev_priv->perf.oa.b_counter_regs =
2147                         b_counter_config_memory_writes;
2148                 dev_priv->perf.oa.b_counter_regs_len =
2149                         ARRAY_SIZE(b_counter_config_memory_writes);
2150
2151                 dev_priv->perf.oa.flex_regs =
2152                         flex_eu_config_memory_writes;
2153                 dev_priv->perf.oa.flex_regs_len =
2154                         ARRAY_SIZE(flex_eu_config_memory_writes);
2155
2156                 return 0;
2157         case METRIC_SET_ID_COMPUTE_EXTENDED:
2158                 dev_priv->perf.oa.n_mux_configs =
2159                         get_compute_extended_mux_config(dev_priv,
2160                                                         dev_priv->perf.oa.mux_regs,
2161                                                         dev_priv->perf.oa.mux_regs_lens);
2162                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2163                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
2164
2165                         /* EINVAL because *_register_sysfs already checked this
2166                          * and so it wouldn't have been advertised to userspace and
2167                          * so shouldn't have been requested
2168                          */
2169                         return -EINVAL;
2170                 }
2171
2172                 dev_priv->perf.oa.b_counter_regs =
2173                         b_counter_config_compute_extended;
2174                 dev_priv->perf.oa.b_counter_regs_len =
2175                         ARRAY_SIZE(b_counter_config_compute_extended);
2176
2177                 dev_priv->perf.oa.flex_regs =
2178                         flex_eu_config_compute_extended;
2179                 dev_priv->perf.oa.flex_regs_len =
2180                         ARRAY_SIZE(flex_eu_config_compute_extended);
2181
2182                 return 0;
2183         case METRIC_SET_ID_COMPUTE_L3_CACHE:
2184                 dev_priv->perf.oa.n_mux_configs =
2185                         get_compute_l3_cache_mux_config(dev_priv,
2186                                                         dev_priv->perf.oa.mux_regs,
2187                                                         dev_priv->perf.oa.mux_regs_lens);
2188                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2189                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
2190
2191                         /* EINVAL because *_register_sysfs already checked this
2192                          * and so it wouldn't have been advertised to userspace and
2193                          * so shouldn't have been requested
2194                          */
2195                         return -EINVAL;
2196                 }
2197
2198                 dev_priv->perf.oa.b_counter_regs =
2199                         b_counter_config_compute_l3_cache;
2200                 dev_priv->perf.oa.b_counter_regs_len =
2201                         ARRAY_SIZE(b_counter_config_compute_l3_cache);
2202
2203                 dev_priv->perf.oa.flex_regs =
2204                         flex_eu_config_compute_l3_cache;
2205                 dev_priv->perf.oa.flex_regs_len =
2206                         ARRAY_SIZE(flex_eu_config_compute_l3_cache);
2207
2208                 return 0;
2209         case METRIC_SET_ID_HDC_AND_SF:
2210                 dev_priv->perf.oa.n_mux_configs =
2211                         get_hdc_and_sf_mux_config(dev_priv,
2212                                                   dev_priv->perf.oa.mux_regs,
2213                                                   dev_priv->perf.oa.mux_regs_lens);
2214                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2215                         DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
2216
2217                         /* EINVAL because *_register_sysfs already checked this
2218                          * and so it wouldn't have been advertised to userspace and
2219                          * so shouldn't have been requested
2220                          */
2221                         return -EINVAL;
2222                 }
2223
2224                 dev_priv->perf.oa.b_counter_regs =
2225                         b_counter_config_hdc_and_sf;
2226                 dev_priv->perf.oa.b_counter_regs_len =
2227                         ARRAY_SIZE(b_counter_config_hdc_and_sf);
2228
2229                 dev_priv->perf.oa.flex_regs =
2230                         flex_eu_config_hdc_and_sf;
2231                 dev_priv->perf.oa.flex_regs_len =
2232                         ARRAY_SIZE(flex_eu_config_hdc_and_sf);
2233
2234                 return 0;
2235         case METRIC_SET_ID_L3_1:
2236                 dev_priv->perf.oa.n_mux_configs =
2237                         get_l3_1_mux_config(dev_priv,
2238                                             dev_priv->perf.oa.mux_regs,
2239                                             dev_priv->perf.oa.mux_regs_lens);
2240                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2241                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
2242
2243                         /* EINVAL because *_register_sysfs already checked this
2244                          * and so it wouldn't have been advertised to userspace and
2245                          * so shouldn't have been requested
2246                          */
2247                         return -EINVAL;
2248                 }
2249
2250                 dev_priv->perf.oa.b_counter_regs =
2251                         b_counter_config_l3_1;
2252                 dev_priv->perf.oa.b_counter_regs_len =
2253                         ARRAY_SIZE(b_counter_config_l3_1);
2254
2255                 dev_priv->perf.oa.flex_regs =
2256                         flex_eu_config_l3_1;
2257                 dev_priv->perf.oa.flex_regs_len =
2258                         ARRAY_SIZE(flex_eu_config_l3_1);
2259
2260                 return 0;
2261         case METRIC_SET_ID_L3_2:
2262                 dev_priv->perf.oa.n_mux_configs =
2263                         get_l3_2_mux_config(dev_priv,
2264                                             dev_priv->perf.oa.mux_regs,
2265                                             dev_priv->perf.oa.mux_regs_lens);
2266                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2267                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n");
2268
2269                         /* EINVAL because *_register_sysfs already checked this
2270                          * and so it wouldn't have been advertised to userspace and
2271                          * so shouldn't have been requested
2272                          */
2273                         return -EINVAL;
2274                 }
2275
2276                 dev_priv->perf.oa.b_counter_regs =
2277                         b_counter_config_l3_2;
2278                 dev_priv->perf.oa.b_counter_regs_len =
2279                         ARRAY_SIZE(b_counter_config_l3_2);
2280
2281                 dev_priv->perf.oa.flex_regs =
2282                         flex_eu_config_l3_2;
2283                 dev_priv->perf.oa.flex_regs_len =
2284                         ARRAY_SIZE(flex_eu_config_l3_2);
2285
2286                 return 0;
2287         case METRIC_SET_ID_L3_3:
2288                 dev_priv->perf.oa.n_mux_configs =
2289                         get_l3_3_mux_config(dev_priv,
2290                                             dev_priv->perf.oa.mux_regs,
2291                                             dev_priv->perf.oa.mux_regs_lens);
2292                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2293                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n");
2294
2295                         /* EINVAL because *_register_sysfs already checked this
2296                          * and so it wouldn't have been advertised to userspace and
2297                          * so shouldn't have been requested
2298                          */
2299                         return -EINVAL;
2300                 }
2301
2302                 dev_priv->perf.oa.b_counter_regs =
2303                         b_counter_config_l3_3;
2304                 dev_priv->perf.oa.b_counter_regs_len =
2305                         ARRAY_SIZE(b_counter_config_l3_3);
2306
2307                 dev_priv->perf.oa.flex_regs =
2308                         flex_eu_config_l3_3;
2309                 dev_priv->perf.oa.flex_regs_len =
2310                         ARRAY_SIZE(flex_eu_config_l3_3);
2311
2312                 return 0;
2313         case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
2314                 dev_priv->perf.oa.n_mux_configs =
2315                         get_rasterizer_and_pixel_backend_mux_config(dev_priv,
2316                                                                     dev_priv->perf.oa.mux_regs,
2317                                                                     dev_priv->perf.oa.mux_regs_lens);
2318                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2319                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
2320
2321                         /* EINVAL because *_register_sysfs already checked this
2322                          * and so it wouldn't have been advertised to userspace and
2323                          * so shouldn't have been requested
2324                          */
2325                         return -EINVAL;
2326                 }
2327
2328                 dev_priv->perf.oa.b_counter_regs =
2329                         b_counter_config_rasterizer_and_pixel_backend;
2330                 dev_priv->perf.oa.b_counter_regs_len =
2331                         ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
2332
2333                 dev_priv->perf.oa.flex_regs =
2334                         flex_eu_config_rasterizer_and_pixel_backend;
2335                 dev_priv->perf.oa.flex_regs_len =
2336                         ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
2337
2338                 return 0;
2339         case METRIC_SET_ID_SAMPLER:
2340                 dev_priv->perf.oa.n_mux_configs =
2341                         get_sampler_mux_config(dev_priv,
2342                                                dev_priv->perf.oa.mux_regs,
2343                                                dev_priv->perf.oa.mux_regs_lens);
2344                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2345                         DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n");
2346
2347                         /* EINVAL because *_register_sysfs already checked this
2348                          * and so it wouldn't have been advertised to userspace and
2349                          * so shouldn't have been requested
2350                          */
2351                         return -EINVAL;
2352                 }
2353
2354                 dev_priv->perf.oa.b_counter_regs =
2355                         b_counter_config_sampler;
2356                 dev_priv->perf.oa.b_counter_regs_len =
2357                         ARRAY_SIZE(b_counter_config_sampler);
2358
2359                 dev_priv->perf.oa.flex_regs =
2360                         flex_eu_config_sampler;
2361                 dev_priv->perf.oa.flex_regs_len =
2362                         ARRAY_SIZE(flex_eu_config_sampler);
2363
2364                 return 0;
2365         case METRIC_SET_ID_TDL_1:
2366                 dev_priv->perf.oa.n_mux_configs =
2367                         get_tdl_1_mux_config(dev_priv,
2368                                              dev_priv->perf.oa.mux_regs,
2369                                              dev_priv->perf.oa.mux_regs_lens);
2370                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2371                         DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
2372
2373                         /* EINVAL because *_register_sysfs already checked this
2374                          * and so it wouldn't have been advertised to userspace and
2375                          * so shouldn't have been requested
2376                          */
2377                         return -EINVAL;
2378                 }
2379
2380                 dev_priv->perf.oa.b_counter_regs =
2381                         b_counter_config_tdl_1;
2382                 dev_priv->perf.oa.b_counter_regs_len =
2383                         ARRAY_SIZE(b_counter_config_tdl_1);
2384
2385                 dev_priv->perf.oa.flex_regs =
2386                         flex_eu_config_tdl_1;
2387                 dev_priv->perf.oa.flex_regs_len =
2388                         ARRAY_SIZE(flex_eu_config_tdl_1);
2389
2390                 return 0;
2391         case METRIC_SET_ID_TDL_2:
2392                 dev_priv->perf.oa.n_mux_configs =
2393                         get_tdl_2_mux_config(dev_priv,
2394                                              dev_priv->perf.oa.mux_regs,
2395                                              dev_priv->perf.oa.mux_regs_lens);
2396                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2397                         DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
2398
2399                         /* EINVAL because *_register_sysfs already checked this
2400                          * and so it wouldn't have been advertised to userspace and
2401                          * so shouldn't have been requested
2402                          */
2403                         return -EINVAL;
2404                 }
2405
2406                 dev_priv->perf.oa.b_counter_regs =
2407                         b_counter_config_tdl_2;
2408                 dev_priv->perf.oa.b_counter_regs_len =
2409                         ARRAY_SIZE(b_counter_config_tdl_2);
2410
2411                 dev_priv->perf.oa.flex_regs =
2412                         flex_eu_config_tdl_2;
2413                 dev_priv->perf.oa.flex_regs_len =
2414                         ARRAY_SIZE(flex_eu_config_tdl_2);
2415
2416                 return 0;
2417         case METRIC_SET_ID_COMPUTE_EXTRA:
2418                 dev_priv->perf.oa.n_mux_configs =
2419                         get_compute_extra_mux_config(dev_priv,
2420                                                      dev_priv->perf.oa.mux_regs,
2421                                                      dev_priv->perf.oa.mux_regs_lens);
2422                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2423                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
2424
2425                         /* EINVAL because *_register_sysfs already checked this
2426                          * and so it wouldn't have been advertised to userspace and
2427                          * so shouldn't have been requested
2428                          */
2429                         return -EINVAL;
2430                 }
2431
2432                 dev_priv->perf.oa.b_counter_regs =
2433                         b_counter_config_compute_extra;
2434                 dev_priv->perf.oa.b_counter_regs_len =
2435                         ARRAY_SIZE(b_counter_config_compute_extra);
2436
2437                 dev_priv->perf.oa.flex_regs =
2438                         flex_eu_config_compute_extra;
2439                 dev_priv->perf.oa.flex_regs_len =
2440                         ARRAY_SIZE(flex_eu_config_compute_extra);
2441
2442                 return 0;
2443         case METRIC_SET_ID_VME_PIPE:
2444                 dev_priv->perf.oa.n_mux_configs =
2445                         get_vme_pipe_mux_config(dev_priv,
2446                                                 dev_priv->perf.oa.mux_regs,
2447                                                 dev_priv->perf.oa.mux_regs_lens);
2448                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2449                         DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n");
2450
2451                         /* EINVAL because *_register_sysfs already checked this
2452                          * and so it wouldn't have been advertised to userspace and
2453                          * so shouldn't have been requested
2454                          */
2455                         return -EINVAL;
2456                 }
2457
2458                 dev_priv->perf.oa.b_counter_regs =
2459                         b_counter_config_vme_pipe;
2460                 dev_priv->perf.oa.b_counter_regs_len =
2461                         ARRAY_SIZE(b_counter_config_vme_pipe);
2462
2463                 dev_priv->perf.oa.flex_regs =
2464                         flex_eu_config_vme_pipe;
2465                 dev_priv->perf.oa.flex_regs_len =
2466                         ARRAY_SIZE(flex_eu_config_vme_pipe);
2467
2468                 return 0;
2469         case METRIC_SET_ID_TEST_OA:
2470                 dev_priv->perf.oa.n_mux_configs =
2471                         get_test_oa_mux_config(dev_priv,
2472                                                dev_priv->perf.oa.mux_regs,
2473                                                dev_priv->perf.oa.mux_regs_lens);
2474                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2475                         DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
2476
2477                         /* EINVAL because *_register_sysfs already checked this
2478                          * and so it wouldn't have been advertised to userspace and
2479                          * so shouldn't have been requested
2480                          */
2481                         return -EINVAL;
2482                 }
2483
2484                 dev_priv->perf.oa.b_counter_regs =
2485                         b_counter_config_test_oa;
2486                 dev_priv->perf.oa.b_counter_regs_len =
2487                         ARRAY_SIZE(b_counter_config_test_oa);
2488
2489                 dev_priv->perf.oa.flex_regs =
2490                         flex_eu_config_test_oa;
2491                 dev_priv->perf.oa.flex_regs_len =
2492                         ARRAY_SIZE(flex_eu_config_test_oa);
2493
2494                 return 0;
2495         default:
2496                 return -ENODEV;
2497         }
2498 }
2499
2500 static ssize_t
2501 show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2502 {
2503         return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
2504 }
2505
2506 static struct device_attribute dev_attr_render_basic_id = {
2507         .attr = { .name = "id", .mode = 0444 },
2508         .show = show_render_basic_id,
2509         .store = NULL,
2510 };
2511
2512 static struct attribute *attrs_render_basic[] = {
2513         &dev_attr_render_basic_id.attr,
2514         NULL,
2515 };
2516
2517 static struct attribute_group group_render_basic = {
2518         .name = "bad77c24-cc64-480d-99bf-e7b740713800",
2519         .attrs =  attrs_render_basic,
2520 };
2521
2522 static ssize_t
2523 show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2524 {
2525         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
2526 }
2527
2528 static struct device_attribute dev_attr_compute_basic_id = {
2529         .attr = { .name = "id", .mode = 0444 },
2530         .show = show_compute_basic_id,
2531         .store = NULL,
2532 };
2533
2534 static struct attribute *attrs_compute_basic[] = {
2535         &dev_attr_compute_basic_id.attr,
2536         NULL,
2537 };
2538
2539 static struct attribute_group group_compute_basic = {
2540         .name = "7277228f-e7f3-4743-945a-6a2049d11377",
2541         .attrs =  attrs_compute_basic,
2542 };
2543
2544 static ssize_t
2545 show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
2546 {
2547         return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
2548 }
2549
2550 static struct device_attribute dev_attr_render_pipe_profile_id = {
2551         .attr = { .name = "id", .mode = 0444 },
2552         .show = show_render_pipe_profile_id,
2553         .store = NULL,
2554 };
2555
2556 static struct attribute *attrs_render_pipe_profile[] = {
2557         &dev_attr_render_pipe_profile_id.attr,
2558         NULL,
2559 };
2560
2561 static struct attribute_group group_render_pipe_profile = {
2562         .name = "463c668c-3f60-49b6-8f85-d995b635b3b2",
2563         .attrs =  attrs_render_pipe_profile,
2564 };
2565
2566 static ssize_t
2567 show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
2568 {
2569         return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
2570 }
2571
2572 static struct device_attribute dev_attr_memory_reads_id = {
2573         .attr = { .name = "id", .mode = 0444 },
2574         .show = show_memory_reads_id,
2575         .store = NULL,
2576 };
2577
2578 static struct attribute *attrs_memory_reads[] = {
2579         &dev_attr_memory_reads_id.attr,
2580         NULL,
2581 };
2582
2583 static struct attribute_group group_memory_reads = {
2584         .name = "3ae6e74c-72c3-4040-9bd0-7961430b8cc8",
2585         .attrs =  attrs_memory_reads,
2586 };
2587
2588 static ssize_t
2589 show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
2590 {
2591         return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
2592 }
2593
2594 static struct device_attribute dev_attr_memory_writes_id = {
2595         .attr = { .name = "id", .mode = 0444 },
2596         .show = show_memory_writes_id,
2597         .store = NULL,
2598 };
2599
2600 static struct attribute *attrs_memory_writes[] = {
2601         &dev_attr_memory_writes_id.attr,
2602         NULL,
2603 };
2604
2605 static struct attribute_group group_memory_writes = {
2606         .name = "055f256d-4052-467c-8dec-6064a4806433",
2607         .attrs =  attrs_memory_writes,
2608 };
2609
2610 static ssize_t
2611 show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
2612 {
2613         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
2614 }
2615
2616 static struct device_attribute dev_attr_compute_extended_id = {
2617         .attr = { .name = "id", .mode = 0444 },
2618         .show = show_compute_extended_id,
2619         .store = NULL,
2620 };
2621
2622 static struct attribute *attrs_compute_extended[] = {
2623         &dev_attr_compute_extended_id.attr,
2624         NULL,
2625 };
2626
2627 static struct attribute_group group_compute_extended = {
2628         .name = "753972d4-87cd-4460-824d-754463ac5054",
2629         .attrs =  attrs_compute_extended,
2630 };
2631
2632 static ssize_t
2633 show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
2634 {
2635         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
2636 }
2637
2638 static struct device_attribute dev_attr_compute_l3_cache_id = {
2639         .attr = { .name = "id", .mode = 0444 },
2640         .show = show_compute_l3_cache_id,
2641         .store = NULL,
2642 };
2643
2644 static struct attribute *attrs_compute_l3_cache[] = {
2645         &dev_attr_compute_l3_cache_id.attr,
2646         NULL,
2647 };
2648
2649 static struct attribute_group group_compute_l3_cache = {
2650         .name = "4e4392e9-8f73-457b-ab44-b49f7a0c733b",
2651         .attrs =  attrs_compute_l3_cache,
2652 };
2653
2654 static ssize_t
2655 show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
2656 {
2657         return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
2658 }
2659
2660 static struct device_attribute dev_attr_hdc_and_sf_id = {
2661         .attr = { .name = "id", .mode = 0444 },
2662         .show = show_hdc_and_sf_id,
2663         .store = NULL,
2664 };
2665
2666 static struct attribute *attrs_hdc_and_sf[] = {
2667         &dev_attr_hdc_and_sf_id.attr,
2668         NULL,
2669 };
2670
2671 static struct attribute_group group_hdc_and_sf = {
2672         .name = "730d95dd-7da8-4e1c-ab8d-c0eb1e4c1805",
2673         .attrs =  attrs_hdc_and_sf,
2674 };
2675
2676 static ssize_t
2677 show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2678 {
2679         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
2680 }
2681
2682 static struct device_attribute dev_attr_l3_1_id = {
2683         .attr = { .name = "id", .mode = 0444 },
2684         .show = show_l3_1_id,
2685         .store = NULL,
2686 };
2687
2688 static struct attribute *attrs_l3_1[] = {
2689         &dev_attr_l3_1_id.attr,
2690         NULL,
2691 };
2692
2693 static struct attribute_group group_l3_1 = {
2694         .name = "d9e86d70-462b-462a-851e-fd63e8c13d63",
2695         .attrs =  attrs_l3_1,
2696 };
2697
2698 static ssize_t
2699 show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
2700 {
2701         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
2702 }
2703
2704 static struct device_attribute dev_attr_l3_2_id = {
2705         .attr = { .name = "id", .mode = 0444 },
2706         .show = show_l3_2_id,
2707         .store = NULL,
2708 };
2709
2710 static struct attribute *attrs_l3_2[] = {
2711         &dev_attr_l3_2_id.attr,
2712         NULL,
2713 };
2714
2715 static struct attribute_group group_l3_2 = {
2716         .name = "52200424-6ee9-48b3-b7fa-0afcf1975e4d",
2717         .attrs =  attrs_l3_2,
2718 };
2719
2720 static ssize_t
2721 show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
2722 {
2723         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
2724 }
2725
2726 static struct device_attribute dev_attr_l3_3_id = {
2727         .attr = { .name = "id", .mode = 0444 },
2728         .show = show_l3_3_id,
2729         .store = NULL,
2730 };
2731
2732 static struct attribute *attrs_l3_3[] = {
2733         &dev_attr_l3_3_id.attr,
2734         NULL,
2735 };
2736
2737 static struct attribute_group group_l3_3 = {
2738         .name = "1988315f-0a26-44df-acb0-df7ec86b1456",
2739         .attrs =  attrs_l3_3,
2740 };
2741
2742 static ssize_t
2743 show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
2744 {
2745         return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
2746 }
2747
2748 static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
2749         .attr = { .name = "id", .mode = 0444 },
2750         .show = show_rasterizer_and_pixel_backend_id,
2751         .store = NULL,
2752 };
2753
2754 static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
2755         &dev_attr_rasterizer_and_pixel_backend_id.attr,
2756         NULL,
2757 };
2758
2759 static struct attribute_group group_rasterizer_and_pixel_backend = {
2760         .name = "f1f17ca7-286e-4ae5-9d15-9fccad6c665d",
2761         .attrs =  attrs_rasterizer_and_pixel_backend,
2762 };
2763
2764 static ssize_t
2765 show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
2766 {
2767         return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
2768 }
2769
2770 static struct device_attribute dev_attr_sampler_id = {
2771         .attr = { .name = "id", .mode = 0444 },
2772         .show = show_sampler_id,
2773         .store = NULL,
2774 };
2775
2776 static struct attribute *attrs_sampler[] = {
2777         &dev_attr_sampler_id.attr,
2778         NULL,
2779 };
2780
2781 static struct attribute_group group_sampler = {
2782         .name = "00a9e0fb-3d2e-4405-852c-dce6334ffb3b",
2783         .attrs =  attrs_sampler,
2784 };
2785
2786 static ssize_t
2787 show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2788 {
2789         return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
2790 }
2791
2792 static struct device_attribute dev_attr_tdl_1_id = {
2793         .attr = { .name = "id", .mode = 0444 },
2794         .show = show_tdl_1_id,
2795         .store = NULL,
2796 };
2797
2798 static struct attribute *attrs_tdl_1[] = {
2799         &dev_attr_tdl_1_id.attr,
2800         NULL,
2801 };
2802
2803 static struct attribute_group group_tdl_1 = {
2804         .name = "13dcc50a-7ec0-409b-99d6-a3f932cedcb3",
2805         .attrs =  attrs_tdl_1,
2806 };
2807
2808 static ssize_t
2809 show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
2810 {
2811         return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
2812 }
2813
2814 static struct device_attribute dev_attr_tdl_2_id = {
2815         .attr = { .name = "id", .mode = 0444 },
2816         .show = show_tdl_2_id,
2817         .store = NULL,
2818 };
2819
2820 static struct attribute *attrs_tdl_2[] = {
2821         &dev_attr_tdl_2_id.attr,
2822         NULL,
2823 };
2824
2825 static struct attribute_group group_tdl_2 = {
2826         .name = "97875e21-6624-4aee-9191-682feb3eae21",
2827         .attrs =  attrs_tdl_2,
2828 };
2829
2830 static ssize_t
2831 show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
2832 {
2833         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
2834 }
2835
2836 static struct device_attribute dev_attr_compute_extra_id = {
2837         .attr = { .name = "id", .mode = 0444 },
2838         .show = show_compute_extra_id,
2839         .store = NULL,
2840 };
2841
2842 static struct attribute *attrs_compute_extra[] = {
2843         &dev_attr_compute_extra_id.attr,
2844         NULL,
2845 };
2846
2847 static struct attribute_group group_compute_extra = {
2848         .name = "a5aa857d-e8f0-4dfa-8981-ce340fa748fd",
2849         .attrs =  attrs_compute_extra,
2850 };
2851
2852 static ssize_t
2853 show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
2854 {
2855         return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
2856 }
2857
2858 static struct device_attribute dev_attr_vme_pipe_id = {
2859         .attr = { .name = "id", .mode = 0444 },
2860         .show = show_vme_pipe_id,
2861         .store = NULL,
2862 };
2863
2864 static struct attribute *attrs_vme_pipe[] = {
2865         &dev_attr_vme_pipe_id.attr,
2866         NULL,
2867 };
2868
2869 static struct attribute_group group_vme_pipe = {
2870         .name = "0e8d8b86-4ee7-4cdd-aaaa-58adc92cb29e",
2871         .attrs =  attrs_vme_pipe,
2872 };
2873
2874 static ssize_t
2875 show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
2876 {
2877         return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
2878 }
2879
2880 static struct device_attribute dev_attr_test_oa_id = {
2881         .attr = { .name = "id", .mode = 0444 },
2882         .show = show_test_oa_id,
2883         .store = NULL,
2884 };
2885
2886 static struct attribute *attrs_test_oa[] = {
2887         &dev_attr_test_oa_id.attr,
2888         NULL,
2889 };
2890
2891 static struct attribute_group group_test_oa = {
2892         .name = "882fa433-1f4a-4a67-a962-c741888fe5f5",
2893         .attrs =  attrs_test_oa,
2894 };
2895
2896 int
2897 i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv)
2898 {
2899         const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
2900         int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
2901         int ret = 0;
2902
2903         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
2904                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2905                 if (ret)
2906                         goto error_render_basic;
2907         }
2908         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
2909                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2910                 if (ret)
2911                         goto error_compute_basic;
2912         }
2913         if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
2914                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2915                 if (ret)
2916                         goto error_render_pipe_profile;
2917         }
2918         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
2919                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
2920                 if (ret)
2921                         goto error_memory_reads;
2922         }
2923         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
2924                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
2925                 if (ret)
2926                         goto error_memory_writes;
2927         }
2928         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
2929                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
2930                 if (ret)
2931                         goto error_compute_extended;
2932         }
2933         if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
2934                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
2935                 if (ret)
2936                         goto error_compute_l3_cache;
2937         }
2938         if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
2939                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2940                 if (ret)
2941                         goto error_hdc_and_sf;
2942         }
2943         if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2944                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2945                 if (ret)
2946                         goto error_l3_1;
2947         }
2948         if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) {
2949                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
2950                 if (ret)
2951                         goto error_l3_2;
2952         }
2953         if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) {
2954                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
2955                 if (ret)
2956                         goto error_l3_3;
2957         }
2958         if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
2959                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2960                 if (ret)
2961                         goto error_rasterizer_and_pixel_backend;
2962         }
2963         if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) {
2964                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
2965                 if (ret)
2966                         goto error_sampler;
2967         }
2968         if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2969                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2970                 if (ret)
2971                         goto error_tdl_1;
2972         }
2973         if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
2974                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2975                 if (ret)
2976                         goto error_tdl_2;
2977         }
2978         if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
2979                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
2980                 if (ret)
2981                         goto error_compute_extra;
2982         }
2983         if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) {
2984                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
2985                 if (ret)
2986                         goto error_vme_pipe;
2987         }
2988         if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
2989                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
2990                 if (ret)
2991                         goto error_test_oa;
2992         }
2993
2994         return 0;
2995
2996 error_test_oa:
2997         if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
2998                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
2999 error_vme_pipe:
3000         if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
3001                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
3002 error_compute_extra:
3003         if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
3004                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
3005 error_tdl_2:
3006         if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
3007                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
3008 error_tdl_1:
3009         if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
3010                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
3011 error_sampler:
3012         if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
3013                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
3014 error_rasterizer_and_pixel_backend:
3015         if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
3016                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
3017 error_l3_3:
3018         if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
3019                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
3020 error_l3_2:
3021         if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
3022                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
3023 error_l3_1:
3024         if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
3025                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
3026 error_hdc_and_sf:
3027         if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
3028                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
3029 error_compute_l3_cache:
3030         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
3031                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
3032 error_compute_extended:
3033         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
3034                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
3035 error_memory_writes:
3036         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
3037                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
3038 error_memory_reads:
3039         if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
3040                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
3041 error_render_pipe_profile:
3042         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
3043                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
3044 error_compute_basic:
3045         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
3046                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
3047 error_render_basic:
3048         return ret;
3049 }
3050
3051 void
3052 i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv)
3053 {
3054         const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
3055         int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
3056
3057         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
3058                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
3059         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
3060                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
3061         if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
3062                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
3063         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
3064                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
3065         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
3066                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
3067         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
3068                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
3069         if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
3070                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
3071         if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
3072                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
3073         if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
3074                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
3075         if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
3076                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
3077         if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
3078                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
3079         if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
3080                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
3081         if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
3082                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
3083         if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
3084                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
3085         if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
3086                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
3087         if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
3088                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
3089         if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
3090                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
3091         if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
3092                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
3093 }