drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 static inline void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 static inline void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      I915_LEGACY_BLC_EVENT_ENABLE);
 175 }
 176
 177 /**
 178  * i915_pipe_enabled - check if a pipe is enabled
 179  * @dev: DRM device
 180  * @pipe: pipe to check
 181  *
 182  * Reading certain registers when the pipe is disabled can hang the chip.
 183  * Use this routine to make sure the PLL is running and the pipe is active
 184  * before reading such registers if unsure.
 185  */
 186 static int
 187 i915_pipe_enabled(struct drm_device *dev, int pipe)
 188 {
 189         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 190         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 191
 192         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 193                 return 1;
 194
 195         return 0;
 196 }
 197
 198 /* Called from drm generic code, passed a 'crtc', which
 199  * we use as a pipe index
 200  */
 201 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 202 {
 203         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 204         unsigned long high_frame;
 205         unsigned long low_frame;
 206         u32 high1, high2, low, count;
 207
 208         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 209         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 210
 211         if (!i915_pipe_enabled(dev, pipe)) {
 212                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 213                                 "pipe %d\n", pipe);
 214                 return 0;
 215         }
 216
 217         /*
 218          * High & low register fields aren't synchronized, so make sure
 219          * we get a low value that's stable across two reads of the high
 220          * register.
 221          */
 222         do {
 223                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 224                          PIPE_FRAME_HIGH_SHIFT);
 225                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 226                         PIPE_FRAME_LOW_SHIFT);
 227                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 228                          PIPE_FRAME_HIGH_SHIFT);
 229         } while (high1 != high2);
 230
 231         count = (high1 << 8) | low;
 232
 233         return count;
 234 }
 235
 236 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 237 {
 238         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 239         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 240
 241         if (!i915_pipe_enabled(dev, pipe)) {
 242                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 243                                         "pipe %d\n", pipe);
 244                 return 0;
 245         }
 246
 247         return I915_READ(reg);
 248 }
 249
 250 /*
 251  * Handle hotplug events outside the interrupt handler proper.
 252  */
 253 static void i915_hotplug_work_func(struct work_struct *work)
 254 {
 255         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 256                                                     hotplug_work);
 257         struct drm_device *dev = dev_priv->dev;
 258         struct drm_mode_config *mode_config = &dev->mode_config;
 259         struct drm_connector *connector;
 260
 261         if (mode_config->num_connector) {
 262                 list_for_each_entry(connector, &mode_config->connector_list, head) {
 263                         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
 264
 265                         if (intel_encoder->hot_plug)
 266                                 (*intel_encoder->hot_plug) (intel_encoder);
 267                 }
 268         }
 269         /* Just fire off a uevent and let userspace tell us what to do */
 270         drm_sysfs_hotplug_event(dev);
 271 }
 272
 273 static void i915_handle_rps_change(struct drm_device *dev)
 274 {
 275         drm_i915_private_t *dev_priv = dev->dev_private;
 276         u32 busy_up, busy_down, max_avg, min_avg;
 277         u16 rgvswctl;
 278         u8 new_delay = dev_priv->cur_delay;
 279
 280         I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
 281         busy_up = I915_READ(RCPREVBSYTUPAVG);
 282         busy_down = I915_READ(RCPREVBSYTDNAVG);
 283         max_avg = I915_READ(RCBMAXAVG);
 284         min_avg = I915_READ(RCBMINAVG);
 285
 286         /* Handle RCS change request from hw */
 287         if (busy_up > max_avg) {
 288                 if (dev_priv->cur_delay != dev_priv->max_delay)
 289                         new_delay = dev_priv->cur_delay - 1;
 290                 if (new_delay < dev_priv->max_delay)
 291                         new_delay = dev_priv->max_delay;
 292         } else if (busy_down < min_avg) {
 293                 if (dev_priv->cur_delay != dev_priv->min_delay)
 294                         new_delay = dev_priv->cur_delay + 1;
 295                 if (new_delay > dev_priv->min_delay)
 296                         new_delay = dev_priv->min_delay;
 297         }
 298
 299         DRM_DEBUG("rps change requested: %d -> %d\n",
 300                   dev_priv->cur_delay, new_delay);
 301
 302         rgvswctl = I915_READ(MEMSWCTL);
 303         if (rgvswctl & MEMCTL_CMD_STS) {
 304                 DRM_ERROR("gpu busy, RCS change rejected\n");
 305                 return; /* still busy with another command */
 306         }
 307
 308         /* Program the new state */
 309         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
 310                 (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
 311         I915_WRITE(MEMSWCTL, rgvswctl);
 312         POSTING_READ(MEMSWCTL);
 313
 314         rgvswctl |= MEMCTL_CMD_STS;
 315         I915_WRITE(MEMSWCTL, rgvswctl);
 316
 317         dev_priv->cur_delay = new_delay;
 318
 319         DRM_DEBUG("rps changed\n");
 320
 321         return;
 322 }
 323
 324 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 325 {
 326         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 327         int ret = IRQ_NONE;
 328         u32 de_iir, gt_iir, de_ier, pch_iir;
 329         struct drm_i915_master_private *master_priv;
 330
 331         /* disable master interrupt before clearing iir  */
 332         de_ier = I915_READ(DEIER);
 333         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 334         (void)I915_READ(DEIER);
 335
 336         de_iir = I915_READ(DEIIR);
 337         gt_iir = I915_READ(GTIIR);
 338         pch_iir = I915_READ(SDEIIR);
 339
 340         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 341                 goto done;
 342
 343         ret = IRQ_HANDLED;
 344
 345         if (dev->primary->master) {
 346                 master_priv = dev->primary->master->driver_priv;
 347                 if (master_priv->sarea_priv)
 348                         master_priv->sarea_priv->last_dispatch =
 349                                 READ_BREADCRUMB(dev_priv);
 350         }
 351
 352         if (gt_iir & GT_PIPE_NOTIFY) {
 353                 u32 seqno = i915_get_gem_seqno(dev);
 354                 dev_priv->mm.irq_gem_seqno = seqno;
 355                 trace_i915_gem_request_complete(dev, seqno);
 356                 DRM_WAKEUP(&dev_priv->irq_queue);
 357                 dev_priv->hangcheck_count = 0;
 358                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 359         }
 360
 361         if (de_iir & DE_GSE)
 362                 ironlake_opregion_gse_intr(dev);
 363
 364         if (de_iir & DE_PLANEA_FLIP_DONE) {
 365                 intel_prepare_page_flip(dev, 0);
 366                 intel_finish_page_flip(dev, 0);
 367         }
 368
 369         if (de_iir & DE_PLANEB_FLIP_DONE) {
 370                 intel_prepare_page_flip(dev, 1);
 371                 intel_finish_page_flip(dev, 1);
 372         }
 373
 374         if (de_iir & DE_PIPEA_VBLANK)
 375                 drm_handle_vblank(dev, 0);
 376
 377         if (de_iir & DE_PIPEB_VBLANK)
 378                 drm_handle_vblank(dev, 1);
 379
 380         /* check event from PCH */
 381         if ((de_iir & DE_PCH_EVENT) &&
 382             (pch_iir & SDE_HOTPLUG_MASK)) {
 383                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 384         }
 385
 386         if (de_iir & DE_PCU_EVENT) {
 387                 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS));
 388                 i915_handle_rps_change(dev);
 389         }
 390
 391         /* should clear PCH hotplug event before clear CPU irq */
 392         I915_WRITE(SDEIIR, pch_iir);
 393         I915_WRITE(GTIIR, gt_iir);
 394         I915_WRITE(DEIIR, de_iir);
 395
 396 done:
 397         I915_WRITE(DEIER, de_ier);
 398         (void)I915_READ(DEIER);
 399
 400         return ret;
 401 }
 402
 403 /**
 404  * i915_error_work_func - do process context error handling work
 405  * @work: work struct
 406  *
 407  * Fire an error uevent so userspace can see that a hang or error
 408  * was detected.
 409  */
 410 static void i915_error_work_func(struct work_struct *work)
 411 {
 412         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 413                                                     error_work);
 414         struct drm_device *dev = dev_priv->dev;
 415         char *error_event[] = { "ERROR=1", NULL };
 416         char *reset_event[] = { "RESET=1", NULL };
 417         char *reset_done_event[] = { "ERROR=0", NULL };
 418
 419         DRM_DEBUG_DRIVER("generating error event\n");
 420         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 421
 422         if (atomic_read(&dev_priv->mm.wedged)) {
 423                 if (IS_I965G(dev)) {
 424                         DRM_DEBUG_DRIVER("resetting chip\n");
 425                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 426                         if (!i965_reset(dev, GDRST_RENDER)) {
 427                                 atomic_set(&dev_priv->mm.wedged, 0);
 428                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 429                         }
 430                 } else {
 431                         DRM_DEBUG_DRIVER("reboot required\n");
 432                 }
 433         }
 434 }
 435
 436 static struct drm_i915_error_object *
 437 i915_error_object_create(struct drm_device *dev,
 438                          struct drm_gem_object *src)
 439 {
 440         struct drm_i915_error_object *dst;
 441         struct drm_i915_gem_object *src_priv;
 442         int page, page_count;
 443
 444         if (src == NULL)
 445                 return NULL;
 446
 447         src_priv = to_intel_bo(src);
 448         if (src_priv->pages == NULL)
 449                 return NULL;
 450
 451         page_count = src->size / PAGE_SIZE;
 452
 453         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 454         if (dst == NULL)
 455                 return NULL;
 456
 457         for (page = 0; page < page_count; page++) {
 458                 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 459                 unsigned long flags;
 460
 461                 if (d == NULL)
 462                         goto unwind;
 463                 local_irq_save(flags);
 464                 s = kmap_atomic(src_priv->pages[page], KM_IRQ0);
 465                 memcpy(d, s, PAGE_SIZE);
 466                 kunmap_atomic(s, KM_IRQ0);
 467                 local_irq_restore(flags);
 468                 dst->pages[page] = d;
 469         }
 470         dst->page_count = page_count;
 471         dst->gtt_offset = src_priv->gtt_offset;
 472
 473         return dst;
 474
 475 unwind:
 476         while (page--)
 477                 kfree(dst->pages[page]);
 478         kfree(dst);
 479         return NULL;
 480 }
 481
 482 static void
 483 i915_error_object_free(struct drm_i915_error_object *obj)
 484 {
 485         int page;
 486
 487         if (obj == NULL)
 488                 return;
 489
 490         for (page = 0; page < obj->page_count; page++)
 491                 kfree(obj->pages[page]);
 492
 493         kfree(obj);
 494 }
 495
 496 static void
 497 i915_error_state_free(struct drm_device *dev,
 498                       struct drm_i915_error_state *error)
 499 {
 500         i915_error_object_free(error->batchbuffer[0]);
 501         i915_error_object_free(error->batchbuffer[1]);
 502         i915_error_object_free(error->ringbuffer);
 503         kfree(error->active_bo);
 504         kfree(error);
 505 }
 506
 507 static u32
 508 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 509 {
 510         u32 cmd;
 511
 512         if (IS_I830(dev) || IS_845G(dev))
 513                 cmd = MI_BATCH_BUFFER;
 514         else if (IS_I965G(dev))
 515                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 516                        MI_BATCH_NON_SECURE_I965);
 517         else
 518                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 519
 520         return ring[0] == cmd ? ring[1] : 0;
 521 }
 522
 523 static u32
 524 i915_ringbuffer_last_batch(struct drm_device *dev)
 525 {
 526         struct drm_i915_private *dev_priv = dev->dev_private;
 527         u32 head, bbaddr;
 528         u32 *ring;
 529
 530         /* Locate the current position in the ringbuffer and walk back
 531          * to find the most recently dispatched batch buffer.
 532          */
 533         bbaddr = 0;
 534         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 535         ring = (u32 *)(dev_priv->ring.virtual_start + head);
 536
 537         while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
 538                 bbaddr = i915_get_bbaddr(dev, ring);
 539                 if (bbaddr)
 540                         break;
 541         }
 542
 543         if (bbaddr == 0) {
 544                 ring = (u32 *)(dev_priv->ring.virtual_start + dev_priv->ring.Size);
 545                 while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
 546                         bbaddr = i915_get_bbaddr(dev, ring);
 547                         if (bbaddr)
 548                                 break;
 549                 }
 550         }
 551
 552         return bbaddr;
 553 }
 554
 555 /**
 556  * i915_capture_error_state - capture an error record for later analysis
 557  * @dev: drm device
 558  *
 559  * Should be called when an error is detected (either a hang or an error
 560  * interrupt) to capture error state from the time of the error.  Fills
 561  * out a structure which becomes available in debugfs for user level tools
 562  * to pick up.
 563  */
 564 static void i915_capture_error_state(struct drm_device *dev)
 565 {
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567         struct drm_i915_gem_object *obj_priv;
 568         struct drm_i915_error_state *error;
 569         struct drm_gem_object *batchbuffer[2];
 570         unsigned long flags;
 571         u32 bbaddr;
 572         int count;
 573
 574         spin_lock_irqsave(&dev_priv->error_lock, flags);
 575         error = dev_priv->first_error;
 576         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 577         if (error)
 578                 return;
 579
 580         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 581         if (!error) {
 582                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 583                 return;
 584         }
 585
 586         error->seqno = i915_get_gem_seqno(dev);
 587         error->eir = I915_READ(EIR);
 588         error->pgtbl_er = I915_READ(PGTBL_ER);
 589         error->pipeastat = I915_READ(PIPEASTAT);
 590         error->pipebstat = I915_READ(PIPEBSTAT);
 591         error->instpm = I915_READ(INSTPM);
 592         if (!IS_I965G(dev)) {
 593                 error->ipeir = I915_READ(IPEIR);
 594                 error->ipehr = I915_READ(IPEHR);
 595                 error->instdone = I915_READ(INSTDONE);
 596                 error->acthd = I915_READ(ACTHD);
 597                 error->bbaddr = 0;
 598         } else {
 599                 error->ipeir = I915_READ(IPEIR_I965);
 600                 error->ipehr = I915_READ(IPEHR_I965);
 601                 error->instdone = I915_READ(INSTDONE_I965);
 602                 error->instps = I915_READ(INSTPS);
 603                 error->instdone1 = I915_READ(INSTDONE1);
 604                 error->acthd = I915_READ(ACTHD_I965);
 605                 error->bbaddr = I915_READ64(BB_ADDR);
 606         }
 607
 608         bbaddr = i915_ringbuffer_last_batch(dev);
 609
 610         /* Grab the current batchbuffer, most likely to have crashed. */
 611         batchbuffer[0] = NULL;
 612         batchbuffer[1] = NULL;
 613         count = 0;
 614         list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
 615                 struct drm_gem_object *obj = obj_priv->obj;
 616
 617                 if (batchbuffer[0] == NULL &&
 618                     bbaddr >= obj_priv->gtt_offset &&
 619                     bbaddr < obj_priv->gtt_offset + obj->size)
 620                         batchbuffer[0] = obj;
 621
 622                 if (batchbuffer[1] == NULL &&
 623                     error->acthd >= obj_priv->gtt_offset &&
 624                     error->acthd < obj_priv->gtt_offset + obj->size &&
 625                     batchbuffer[0] != obj)
 626                         batchbuffer[1] = obj;
 627
 628                 count++;
 629         }
 630
 631         /* We need to copy these to an anonymous buffer as the simplest
 632          * method to avoid being overwritten by userpace.
 633          */
 634         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 635         error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 636
 637         /* Record the ringbuffer */
 638         error->ringbuffer = i915_error_object_create(dev, dev_priv->ring.ring_obj);
 639
 640         /* Record buffers on the active list. */
 641         error->active_bo = NULL;
 642         error->active_bo_count = 0;
 643
 644         if (count)
 645                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 646                                            GFP_ATOMIC);
 647
 648         if (error->active_bo) {
 649                 int i = 0;
 650                 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
 651                         struct drm_gem_object *obj = obj_priv->obj;
 652
 653                         error->active_bo[i].size = obj->size;
 654                         error->active_bo[i].name = obj->name;
 655                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 656                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 657                         error->active_bo[i].read_domains = obj->read_domains;
 658                         error->active_bo[i].write_domain = obj->write_domain;
 659                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 660                         error->active_bo[i].pinned = 0;
 661                         if (obj_priv->pin_count > 0)
 662                                 error->active_bo[i].pinned = 1;
 663                         if (obj_priv->user_pin_count > 0)
 664                                 error->active_bo[i].pinned = -1;
 665                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 666                         error->active_bo[i].dirty = obj_priv->dirty;
 667                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 668
 669                         if (++i == count)
 670                                 break;
 671                 }
 672                 error->active_bo_count = i;
 673         }
 674
 675         do_gettimeofday(&error->time);
 676
 677         spin_lock_irqsave(&dev_priv->error_lock, flags);
 678         if (dev_priv->first_error == NULL) {
 679                 dev_priv->first_error = error;
 680                 error = NULL;
 681         }
 682         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 683
 684         if (error)
 685                 i915_error_state_free(dev, error);
 686 }
 687
 688 void i915_destroy_error_state(struct drm_device *dev)
 689 {
 690         struct drm_i915_private *dev_priv = dev->dev_private;
 691         struct drm_i915_error_state *error;
 692
 693         spin_lock(&dev_priv->error_lock);
 694         error = dev_priv->first_error;
 695         dev_priv->first_error = NULL;
 696         spin_unlock(&dev_priv->error_lock);
 697
 698         if (error)
 699                 i915_error_state_free(dev, error);
 700 }
 701
 702 /**
 703  * i915_handle_error - handle an error interrupt
 704  * @dev: drm device
 705  *
 706  * Do some basic checking of regsiter state at error interrupt time and
 707  * dump it to the syslog.  Also call i915_capture_error_state() to make
 708  * sure we get a record and make it available in debugfs.  Fire a uevent
 709  * so userspace knows something bad happened (should trigger collection
 710  * of a ring dump etc.).
 711  */
 712 static void i915_handle_error(struct drm_device *dev, bool wedged)
 713 {
 714         struct drm_i915_private *dev_priv = dev->dev_private;
 715         u32 eir = I915_READ(EIR);
 716         u32 pipea_stats = I915_READ(PIPEASTAT);
 717         u32 pipeb_stats = I915_READ(PIPEBSTAT);
 718
 719         i915_capture_error_state(dev);
 720
 721         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 722                eir);
 723
 724         if (IS_G4X(dev)) {
 725                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 726                         u32 ipeir = I915_READ(IPEIR_I965);
 727
 728                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 729                                I915_READ(IPEIR_I965));
 730                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 731                                I915_READ(IPEHR_I965));
 732                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 733                                I915_READ(INSTDONE_I965));
 734                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 735                                I915_READ(INSTPS));
 736                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 737                                I915_READ(INSTDONE1));
 738                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 739                                I915_READ(ACTHD_I965));
 740                         I915_WRITE(IPEIR_I965, ipeir);
 741                         (void)I915_READ(IPEIR_I965);
 742                 }
 743                 if (eir & GM45_ERROR_PAGE_TABLE) {
 744                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 745                         printk(KERN_ERR "page table error\n");
 746                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 747                                pgtbl_err);
 748                         I915_WRITE(PGTBL_ER, pgtbl_err);
 749                         (void)I915_READ(PGTBL_ER);
 750                 }
 751         }
 752
 753         if (IS_I9XX(dev)) {
 754                 if (eir & I915_ERROR_PAGE_TABLE) {
 755                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 756                         printk(KERN_ERR "page table error\n");
 757                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 758                                pgtbl_err);
 759                         I915_WRITE(PGTBL_ER, pgtbl_err);
 760                         (void)I915_READ(PGTBL_ER);
 761                 }
 762         }
 763
 764         if (eir & I915_ERROR_MEMORY_REFRESH) {
 765                 printk(KERN_ERR "memory refresh error\n");
 766                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 767                        pipea_stats);
 768                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 769                        pipeb_stats);
 770                 /* pipestat has already been acked */
 771         }
 772         if (eir & I915_ERROR_INSTRUCTION) {
 773                 printk(KERN_ERR "instruction error\n");
 774                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 775                        I915_READ(INSTPM));
 776                 if (!IS_I965G(dev)) {
 777                         u32 ipeir = I915_READ(IPEIR);
 778
 779                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 780                                I915_READ(IPEIR));
 781                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 782                                I915_READ(IPEHR));
 783                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 784                                I915_READ(INSTDONE));
 785                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 786                                I915_READ(ACTHD));
 787                         I915_WRITE(IPEIR, ipeir);
 788                         (void)I915_READ(IPEIR);
 789                 } else {
 790                         u32 ipeir = I915_READ(IPEIR_I965);
 791
 792                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 793                                I915_READ(IPEIR_I965));
 794                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 795                                I915_READ(IPEHR_I965));
 796                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 797                                I915_READ(INSTDONE_I965));
 798                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 799                                I915_READ(INSTPS));
 800                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 801                                I915_READ(INSTDONE1));
 802                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 803                                I915_READ(ACTHD_I965));
 804                         I915_WRITE(IPEIR_I965, ipeir);
 805                         (void)I915_READ(IPEIR_I965);
 806                 }
 807         }
 808
 809         I915_WRITE(EIR, eir);
 810         (void)I915_READ(EIR);
 811         eir = I915_READ(EIR);
 812         if (eir) {
 813                 /*
 814                  * some errors might have become stuck,
 815                  * mask them.
 816                  */
 817                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 818                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 819                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 820         }
 821
 822         if (wedged) {
 823                 atomic_set(&dev_priv->mm.wedged, 1);
 824
 825                 /*
 826                  * Wakeup waiting processes so they don't hang
 827                  */
 828                 DRM_WAKEUP(&dev_priv->irq_queue);
 829         }
 830
 831         queue_work(dev_priv->wq, &dev_priv->error_work);
 832 }
 833
 834 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 835 {
 836         struct drm_device *dev = (struct drm_device *) arg;
 837         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 838         struct drm_i915_master_private *master_priv;
 839         u32 iir, new_iir;
 840         u32 pipea_stats, pipeb_stats;
 841         u32 vblank_status;
 842         u32 vblank_enable;
 843         int vblank = 0;
 844         unsigned long irqflags;
 845         int irq_received;
 846         int ret = IRQ_NONE;
 847
 848         atomic_inc(&dev_priv->irq_received);
 849
 850         if (HAS_PCH_SPLIT(dev))
 851                 return ironlake_irq_handler(dev);
 852
 853         iir = I915_READ(IIR);
 854
 855         if (IS_I965G(dev)) {
 856                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 857                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 858         } else {
 859                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 860                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 861         }
 862
 863         for (;;) {
 864                 irq_received = iir != 0;
 865
 866                 /* Can't rely on pipestat interrupt bit in iir as it might
 867                  * have been cleared after the pipestat interrupt was received.
 868                  * It doesn't set the bit in iir again, but it still produces
 869                  * interrupts (for non-MSI).
 870                  */
 871                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 872                 pipea_stats = I915_READ(PIPEASTAT);
 873                 pipeb_stats = I915_READ(PIPEBSTAT);
 874
 875                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 876                         i915_handle_error(dev, false);
 877
 878                 /*
 879                  * Clear the PIPE(A|B)STAT regs before the IIR
 880                  */
 881                 if (pipea_stats & 0x8000ffff) {
 882                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 883                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 884                         I915_WRITE(PIPEASTAT, pipea_stats);
 885                         irq_received = 1;
 886                 }
 887
 888                 if (pipeb_stats & 0x8000ffff) {
 889                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 890                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 891                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 892                         irq_received = 1;
 893                 }
 894                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 895
 896                 if (!irq_received)
 897                         break;
 898
 899                 ret = IRQ_HANDLED;
 900
 901                 /* Consume port.  Then clear IIR or we'll miss events */
 902                 if ((I915_HAS_HOTPLUG(dev)) &&
 903                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 904                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 905
 906                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 907                                   hotplug_status);
 908                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 909                                 queue_work(dev_priv->wq,
 910                                            &dev_priv->hotplug_work);
 911
 912                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 913                         I915_READ(PORT_HOTPLUG_STAT);
 914                 }
 915
 916                 I915_WRITE(IIR, iir);
 917                 new_iir = I915_READ(IIR); /* Flush posted writes */
 918
 919                 if (dev->primary->master) {
 920                         master_priv = dev->primary->master->driver_priv;
 921                         if (master_priv->sarea_priv)
 922                                 master_priv->sarea_priv->last_dispatch =
 923                                         READ_BREADCRUMB(dev_priv);
 924                 }
 925
 926                 if (iir & I915_USER_INTERRUPT) {
 927                         u32 seqno = i915_get_gem_seqno(dev);
 928                         dev_priv->mm.irq_gem_seqno = seqno;
 929                         trace_i915_gem_request_complete(dev, seqno);
 930                         DRM_WAKEUP(&dev_priv->irq_queue);
 931                         dev_priv->hangcheck_count = 0;
 932                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 933                 }
 934
 935                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
 936                         intel_prepare_page_flip(dev, 0);
 937
 938                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
 939                         intel_prepare_page_flip(dev, 1);
 940
 941                 if (pipea_stats & vblank_status) {
 942                         vblank++;
 943                         drm_handle_vblank(dev, 0);
 944                         intel_finish_page_flip(dev, 0);
 945                 }
 946
 947                 if (pipeb_stats & vblank_status) {
 948                         vblank++;
 949                         drm_handle_vblank(dev, 1);
 950                         intel_finish_page_flip(dev, 1);
 951                 }
 952
 953                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 954                     (iir & I915_ASLE_INTERRUPT))
 955                         opregion_asle_intr(dev);
 956
 957                 /* With MSI, interrupts are only generated when iir
 958                  * transitions from zero to nonzero.  If another bit got
 959                  * set while we were handling the existing iir bits, then
 960                  * we would never get another interrupt.
 961                  *
 962                  * This is fine on non-MSI as well, as if we hit this path
 963                  * we avoid exiting the interrupt handler only to generate
 964                  * another one.
 965                  *
 966                  * Note that for MSI this could cause a stray interrupt report
 967                  * if an interrupt landed in the time between writing IIR and
 968                  * the posting read.  This should be rare enough to never
 969                  * trigger the 99% of 100,000 interrupts test for disabling
 970                  * stray interrupts.
 971                  */
 972                 iir = new_iir;
 973         }
 974
 975         return ret;
 976 }
 977
 978 static int i915_emit_irq(struct drm_device * dev)
 979 {
 980         drm_i915_private_t *dev_priv = dev->dev_private;
 981         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 982         RING_LOCALS;
 983
 984         i915_kernel_lost_context(dev);
 985
 986         DRM_DEBUG_DRIVER("\n");
 987
 988         dev_priv->counter++;
 989         if (dev_priv->counter > 0x7FFFFFFFUL)
 990                 dev_priv->counter = 1;
 991         if (master_priv->sarea_priv)
 992                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 993
 994         BEGIN_LP_RING(4);
 995         OUT_RING(MI_STORE_DWORD_INDEX);
 996         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 997         OUT_RING(dev_priv->counter);
 998         OUT_RING(MI_USER_INTERRUPT);
 999         ADVANCE_LP_RING();
1000
1001         return dev_priv->counter;
1002 }
1003
1004 void i915_user_irq_get(struct drm_device *dev)
1005 {
1006         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1007         unsigned long irqflags;
1008
1009         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1010         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
1011                 if (HAS_PCH_SPLIT(dev))
1012                         ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
1013                 else
1014                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
1015         }
1016         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1017 }
1018
1019 void i915_user_irq_put(struct drm_device *dev)
1020 {
1021         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1022         unsigned long irqflags;
1023
1024         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1025         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
1026         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
1027                 if (HAS_PCH_SPLIT(dev))
1028                         ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
1029                 else
1030                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
1031         }
1032         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1033 }
1034
1035 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1036 {
1037         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1038
1039         if (dev_priv->trace_irq_seqno == 0)
1040                 i915_user_irq_get(dev);
1041
1042         dev_priv->trace_irq_seqno = seqno;
1043 }
1044
1045 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1046 {
1047         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1048         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1049         int ret = 0;
1050
1051         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1052                   READ_BREADCRUMB(dev_priv));
1053
1054         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1055                 if (master_priv->sarea_priv)
1056                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1057                 return 0;
1058         }
1059
1060         if (master_priv->sarea_priv)
1061                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1062
1063         i915_user_irq_get(dev);
1064         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
1065                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1066         i915_user_irq_put(dev);
1067
1068         if (ret == -EBUSY) {
1069                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1070                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1071         }
1072
1073         return ret;
1074 }
1075
1076 /* Needs the lock as it touches the ring.
1077  */
1078 int i915_irq_emit(struct drm_device *dev, void *data,
1079                          struct drm_file *file_priv)
1080 {
1081         drm_i915_private_t *dev_priv = dev->dev_private;
1082         drm_i915_irq_emit_t *emit = data;
1083         int result;
1084
1085         if (!dev_priv || !dev_priv->ring.virtual_start) {
1086                 DRM_ERROR("called with no initialization\n");
1087                 return -EINVAL;
1088         }
1089
1090         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1091
1092         mutex_lock(&dev->struct_mutex);
1093         result = i915_emit_irq(dev);
1094         mutex_unlock(&dev->struct_mutex);
1095
1096         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1097                 DRM_ERROR("copy_to_user\n");
1098                 return -EFAULT;
1099         }
1100
1101         return 0;
1102 }
1103
1104 /* Doesn't need the hardware lock.
1105  */
1106 int i915_irq_wait(struct drm_device *dev, void *data,
1107                          struct drm_file *file_priv)
1108 {
1109         drm_i915_private_t *dev_priv = dev->dev_private;
1110         drm_i915_irq_wait_t *irqwait = data;
1111
1112         if (!dev_priv) {
1113                 DRM_ERROR("called with no initialization\n");
1114                 return -EINVAL;
1115         }
1116
1117         return i915_wait_irq(dev, irqwait->irq_seq);
1118 }
1119
1120 /* Called from drm generic code, passed 'crtc' which
1121  * we use as a pipe index
1122  */
1123 int i915_enable_vblank(struct drm_device *dev, int pipe)
1124 {
1125         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1126         unsigned long irqflags;
1127         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1128         u32 pipeconf;
1129
1130         pipeconf = I915_READ(pipeconf_reg);
1131         if (!(pipeconf & PIPEACONF_ENABLE))
1132                 return -EINVAL;
1133
1134         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1135         if (HAS_PCH_SPLIT(dev))
1136                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1137                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1138         else if (IS_I965G(dev))
1139                 i915_enable_pipestat(dev_priv, pipe,
1140                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1141         else
1142                 i915_enable_pipestat(dev_priv, pipe,
1143                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1144         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1145         return 0;
1146 }
1147
1148 /* Called from drm generic code, passed 'crtc' which
1149  * we use as a pipe index
1150  */
1151 void i915_disable_vblank(struct drm_device *dev, int pipe)
1152 {
1153         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1154         unsigned long irqflags;
1155
1156         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1157         if (HAS_PCH_SPLIT(dev))
1158                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1159                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1160         else
1161                 i915_disable_pipestat(dev_priv, pipe,
1162                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1163                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1164         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1165 }
1166
1167 void i915_enable_interrupt (struct drm_device *dev)
1168 {
1169         struct drm_i915_private *dev_priv = dev->dev_private;
1170
1171         if (!HAS_PCH_SPLIT(dev))
1172                 opregion_enable_asle(dev);
1173         dev_priv->irq_enabled = 1;
1174 }
1175
1176
1177 /* Set the vblank monitor pipe
1178  */
1179 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1180                          struct drm_file *file_priv)
1181 {
1182         drm_i915_private_t *dev_priv = dev->dev_private;
1183
1184         if (!dev_priv) {
1185                 DRM_ERROR("called with no initialization\n");
1186                 return -EINVAL;
1187         }
1188
1189         return 0;
1190 }
1191
1192 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1193                          struct drm_file *file_priv)
1194 {
1195         drm_i915_private_t *dev_priv = dev->dev_private;
1196         drm_i915_vblank_pipe_t *pipe = data;
1197
1198         if (!dev_priv) {
1199                 DRM_ERROR("called with no initialization\n");
1200                 return -EINVAL;
1201         }
1202
1203         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1204
1205         return 0;
1206 }
1207
1208 /**
1209  * Schedule buffer swap at given vertical blank.
1210  */
1211 int i915_vblank_swap(struct drm_device *dev, void *data,
1212                      struct drm_file *file_priv)
1213 {
1214         /* The delayed swap mechanism was fundamentally racy, and has been
1215          * removed.  The model was that the client requested a delayed flip/swap
1216          * from the kernel, then waited for vblank before continuing to perform
1217          * rendering.  The problem was that the kernel might wake the client
1218          * up before it dispatched the vblank swap (since the lock has to be
1219          * held while touching the ringbuffer), in which case the client would
1220          * clear and start the next frame before the swap occurred, and
1221          * flicker would occur in addition to likely missing the vblank.
1222          *
1223          * In the absence of this ioctl, userland falls back to a correct path
1224          * of waiting for a vblank, then dispatching the swap on its own.
1225          * Context switching to userland and back is plenty fast enough for
1226          * meeting the requirements of vblank swapping.
1227          */
1228         return -EINVAL;
1229 }
1230
1231 struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
1232         drm_i915_private_t *dev_priv = dev->dev_private;
1233         return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
1234 }
1235
1236 /**
1237  * This is called when the chip hasn't reported back with completed
1238  * batchbuffers in a long time. The first time this is called we simply record
1239  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1240  * again, we assume the chip is wedged and try to fix it.
1241  */
1242 void i915_hangcheck_elapsed(unsigned long data)
1243 {
1244         struct drm_device *dev = (struct drm_device *)data;
1245         drm_i915_private_t *dev_priv = dev->dev_private;
1246         uint32_t acthd;
1247
1248         /* No reset support on this chip yet. */
1249         if (IS_GEN6(dev))
1250                 return;
1251
1252         if (!IS_I965G(dev))
1253                 acthd = I915_READ(ACTHD);
1254         else
1255                 acthd = I915_READ(ACTHD_I965);
1256
1257         /* If all work is done then ACTHD clearly hasn't advanced. */
1258         if (list_empty(&dev_priv->mm.request_list) ||
1259                        i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
1260                 dev_priv->hangcheck_count = 0;
1261                 return;
1262         }
1263
1264         if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1265                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1266                 i915_handle_error(dev, true);
1267                 return;
1268         }
1269
1270         /* Reset timer case chip hangs without another request being added */
1271         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1272
1273         if (acthd != dev_priv->last_acthd)
1274                 dev_priv->hangcheck_count = 0;
1275         else
1276                 dev_priv->hangcheck_count++;
1277
1278         dev_priv->last_acthd = acthd;
1279 }
1280
1281 /* drm_dma.h hooks
1282 */
1283 static void ironlake_irq_preinstall(struct drm_device *dev)
1284 {
1285         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1286
1287         I915_WRITE(HWSTAM, 0xeffe);
1288
1289         /* XXX hotplug from PCH */
1290
1291         I915_WRITE(DEIMR, 0xffffffff);
1292         I915_WRITE(DEIER, 0x0);
1293         (void) I915_READ(DEIER);
1294
1295         /* and GT */
1296         I915_WRITE(GTIMR, 0xffffffff);
1297         I915_WRITE(GTIER, 0x0);
1298         (void) I915_READ(GTIER);
1299
1300         /* south display irq */
1301         I915_WRITE(SDEIMR, 0xffffffff);
1302         I915_WRITE(SDEIER, 0x0);
1303         (void) I915_READ(SDEIER);
1304 }
1305
1306 static int ironlake_irq_postinstall(struct drm_device *dev)
1307 {
1308         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1309         /* enable kind of interrupts always enabled */
1310         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1311                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1312         u32 render_mask = GT_PIPE_NOTIFY;
1313         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1314                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1315
1316         dev_priv->irq_mask_reg = ~display_mask;
1317         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1318
1319         /* should always can generate irq */
1320         I915_WRITE(DEIIR, I915_READ(DEIIR));
1321         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1322         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1323         (void) I915_READ(DEIER);
1324
1325         /* user interrupt should be enabled, but masked initial */
1326         dev_priv->gt_irq_mask_reg = 0xffffffff;
1327         dev_priv->gt_irq_enable_reg = render_mask;
1328
1329         I915_WRITE(GTIIR, I915_READ(GTIIR));
1330         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1331         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1332         (void) I915_READ(GTIER);
1333
1334         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1335         dev_priv->pch_irq_enable_reg = hotplug_mask;
1336
1337         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1338         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1339         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1340         (void) I915_READ(SDEIER);
1341
1342         if (IS_IRONLAKE_M(dev)) {
1343                 /* Clear & enable PCU event interrupts */
1344                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1345                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1346                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1347         }
1348
1349         return 0;
1350 }
1351
1352 void i915_driver_irq_preinstall(struct drm_device * dev)
1353 {
1354         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1355
1356         atomic_set(&dev_priv->irq_received, 0);
1357
1358         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1359         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1360
1361         if (HAS_PCH_SPLIT(dev)) {
1362                 ironlake_irq_preinstall(dev);
1363                 return;
1364         }
1365
1366         if (I915_HAS_HOTPLUG(dev)) {
1367                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1368                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1369         }
1370
1371         I915_WRITE(HWSTAM, 0xeffe);
1372         I915_WRITE(PIPEASTAT, 0);
1373         I915_WRITE(PIPEBSTAT, 0);
1374         I915_WRITE(IMR, 0xffffffff);
1375         I915_WRITE(IER, 0x0);
1376         (void) I915_READ(IER);
1377 }
1378
1379 /*
1380  * Must be called after intel_modeset_init or hotplug interrupts won't be
1381  * enabled correctly.
1382  */
1383 int i915_driver_irq_postinstall(struct drm_device *dev)
1384 {
1385         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1386         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1387         u32 error_mask;
1388
1389         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1390
1391         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1392
1393         if (HAS_PCH_SPLIT(dev))
1394                 return ironlake_irq_postinstall(dev);
1395
1396         /* Unmask the interrupts that we always want on. */
1397         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1398
1399         dev_priv->pipestat[0] = 0;
1400         dev_priv->pipestat[1] = 0;
1401
1402         if (I915_HAS_HOTPLUG(dev)) {
1403                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1404
1405                 /* Note HDMI and DP share bits */
1406                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1407                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1408                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1409                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1410                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1411                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1412                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1413                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1414                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1415                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1416                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1417                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1418                 /* Ignore TV since it's buggy */
1419
1420                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1421
1422                 /* Enable in IER... */
1423                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1424                 /* and unmask in IMR */
1425                 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1426         }
1427
1428         /*
1429          * Enable some error detection, note the instruction error mask
1430          * bit is reserved, so we leave it masked.
1431          */
1432         if (IS_G4X(dev)) {
1433                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1434                                GM45_ERROR_MEM_PRIV |
1435                                GM45_ERROR_CP_PRIV |
1436                                I915_ERROR_MEMORY_REFRESH);
1437         } else {
1438                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1439                                I915_ERROR_MEMORY_REFRESH);
1440         }
1441         I915_WRITE(EMR, error_mask);
1442
1443         /* Disable pipe interrupt enables, clear pending pipe status */
1444         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1445         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1446         /* Clear pending interrupt status */
1447         I915_WRITE(IIR, I915_READ(IIR));
1448
1449         I915_WRITE(IER, enable_mask);
1450         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1451         (void) I915_READ(IER);
1452
1453         opregion_enable_asle(dev);
1454
1455         return 0;
1456 }
1457
1458 static void ironlake_irq_uninstall(struct drm_device *dev)
1459 {
1460         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1461         I915_WRITE(HWSTAM, 0xffffffff);
1462
1463         I915_WRITE(DEIMR, 0xffffffff);
1464         I915_WRITE(DEIER, 0x0);
1465         I915_WRITE(DEIIR, I915_READ(DEIIR));
1466
1467         I915_WRITE(GTIMR, 0xffffffff);
1468         I915_WRITE(GTIER, 0x0);
1469         I915_WRITE(GTIIR, I915_READ(GTIIR));
1470 }
1471
1472 void i915_driver_irq_uninstall(struct drm_device * dev)
1473 {
1474         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1475
1476         if (!dev_priv)
1477                 return;
1478
1479         dev_priv->vblank_pipe = 0;
1480
1481         if (HAS_PCH_SPLIT(dev)) {
1482                 ironlake_irq_uninstall(dev);
1483                 return;
1484         }
1485
1486         if (I915_HAS_HOTPLUG(dev)) {
1487                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1488                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1489         }
1490
1491         I915_WRITE(HWSTAM, 0xffffffff);
1492         I915_WRITE(PIPEASTAT, 0);
1493         I915_WRITE(PIPEBSTAT, 0);
1494         I915_WRITE(IMR, 0xffffffff);
1495         I915_WRITE(IER, 0x0);
1496
1497         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1498         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1499         I915_WRITE(IIR, I915_READ(IIR));
1500 }